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Transistors

Transistors-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Low power high gain radio frequency amplifier for sensor apparatus
The Regents Of The University Of Michigan
August 09, 2018 - N°20180227002

A wireless communication device is presented for use with a sensor. The wireless communication device includes: an antenna, a driver circuit and a bias circuit.
Output driver pulse overlap control
Microsoft Technology Licensing, Llc
August 09, 2018 - N°20180226978

The control signal edges of pull-up and pull-down output transistors are aligned by a feedback system. The feedback system works to align the edges of these pull-up and pull-down control pulses while also reducing and/or minimizing any overlap of pull-up and pull-down control pulses.
Level shifter
Sii Semiconductor Corporation
August 09, 2018 - N°20180226971

Between a power supply potential and a reference potential, a first pmos transistor and a first nmos transistor are connected in series via an inverting output node and a second pmos transistor and a second nmos transistor are connected in series via a non-inverting output node. A third nmos transistor is connected in parallel to the first nmos transistor and ...
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Electronic switch, and corresponding device and method
Stmicroelectronics S.r.l.
August 09, 2018 - N°20180226964

A high-voltage electronic switch includes first and second transistors defining a current flow path between an input and output of the switch. The transistors have a common point of the current flow path and a common control terminal.
Comparator, solid-state imaging device, electronic apparatus, and driving method
Sony Corporation
August 09, 2018 - N°20180226962

A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a ...
Comparator
Kabushiki Kaisha Toshiba
August 09, 2018 - N°20180226960

A comparator includes a differential pair circuit comprising nmos transistors, the differential pair circuit configured to output a signal corresponding to a difference between first and second input signals supplied thereto, and an input circuit configured to raise a voltage level of the first input signal supplied to the differential pair circuit when the voltage of the first input signal ...
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Systems and methods for real-time inductor current simulation for a switching converter
Texas Instruments Incorporated
August 09, 2018 - N°20180226892

A switching converter having a high-side switching transistor and a low-side switching transistor and an inductor, having a circuit for generating a simulated waveform representing a sawtooth inductor current waveform. A circuit for monitoring and voltage at a switch node between the high-side and low-side transistors to determine a time during which the inductor current is increasing and a time ...
Vertical transport field effect transistors
Globalfoundries Inc.
August 09, 2018 - N°20180226505

The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of ...
Transistors having ultra thin fin profiles and their methods of fabrication
Intel Corporation
August 09, 2018 - N°20180226496

A transistor having an ultra thin fin profile and its method of fabrication is described. The transistor comprises a semiconductor substrate having an insulation layer formed on a semiconductor substrate.
Replacement metal gate scheme with self-alignment gate for vertical field effect transistors
International Business Machines Corporation
August 09, 2018 - N°20180226493

A method is presented for forming a semiconductor structure. The method includes forming a fin structure over a substrate, forming a dummy gate over the fin structure, and etching the dummy gate by a first amount to expose a top portion of the fin structure.
Long channel mos transistors for low leakage applications on a short channel cmos chip
Intel Corporation
August 09, 2018 - N°20180226492

Embodiments of the invention include vertically oriented long channel transistors and methods of forming such transistors. In one embodiment, a method of forming such a transistor may include forming a fin on a semiconductor substrate.
Approach to bottom dielectric isolation for vertical transport fin field effect transistors
International Business Machines Corporation
August 09, 2018 - N°20180226491

A vertical transport fin field effect transistor (vt finfet), including one or more vertical fins on a surface of a substrate, an l-shaped or u-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more ...
Approach to bottom dielectric isolation for vertical transport fin field effect transistors
International Business Machines Corporation
August 09, 2018 - N°20180226489

A vertical transport fin field effect transistor (vt finfet), including one or more vertical fins on a surface of a substrate, an l-shaped or u-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more ...
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  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Structure featuring ferroelectric capacitance in interconnect level for steep sub-threshold complementary metal oxide semiconductor transistors
International Business Machines Corporation
August 09, 2018 - N°20180226417

After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed ...
Structure featuring ferroelectric capacitance in interconnect level for steep sub-threshold complementary metal oxide semiconductor transistors
International Business Machines Corporation
August 09, 2018 - N°20180226416

After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed ...
Structure featuring ferroelectric capacitance in interconnect level for steep sub-threshold complementary metal oxide semiconductor transistors
International Business Machines Corporation
August 09, 2018 - N°20180226415

After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed ...
Integration of vertical field-effect transistors and saddle fin-type field effect transistors
Globalfoundries Inc.
August 09, 2018 - N°20180226402

Structures for the integration of a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit, as well as methods of integrating a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit. A trench isolation is formed in a substrate that defines a first device region and a second device region.
Tipless transistors, short-tip transistors, and methods and circuits therefor
Mie Fujitsu Semiconductor Limited
August 09, 2018 - N°20180226401

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature ...
Front end systems and related devices, integrated circuits, modules, and methods
Skyworks Solutions, Inc.
August 09, 2018 - N°20180226367

Front end systems and related devices, integrated circuits, modules, and methods are disclosed. One such front end system includes a low noise amplifier in a receive path and a multi-mode power amplifier circuit in a transmit path.
Heterojunction bipolar transistors with stress material for improved mobility
Globalfoundries Inc.
August 09, 2018 - N°20180226347

According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate.
Method of manufacturing semiconductor device
Samsung Electronics Co., Ltd.
August 09, 2018 - N°20180226303

A method of manufacturing a semiconductor device includes forming transistors in a cell region of a test wafer, forming a first test pattern on a first test cell in the cell region, the first test pattern being electrically connected to the transistors, and scanning the first test pattern using an electron beam. Forming the transistors in the cell region includes ...
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