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Semiconductor patents

      

This page is updated frequently with new Semiconductor-related patent applications.

Power semiconductor device and power conversion device
A power semiconductor device includes a first power semiconductor element, a second power semiconductor element, a first conductor plate, a second conductor plate, a third conductor plate, and a fourth conductor plate. The power semiconductor device also includes a dc positive terminal, a dc negative terminal, an ac terminal, and a sealing member that integrally seals the first conductor plate, the second conductor plate, the third conductor plate, and the fourth conductor plate.

Low noise cmos image sensor by stack architecture
A pixel circuit for use in a high dynamic range (hdr) image sensor includes a photodiode and a floating diffusion is disposed in the first semiconductor wafer. A transfer transistor is disposed in the first semiconductor wafer and is adapted to be switched on to transfer the charge carriers photogenerated in the photodiode to the floating diffusion.

Semiconductor integrated circuit and control semiconductor integrated circuit
The image forming apparatus of the present invention is a semiconductor integrated circuit including: a first image processing module; a second image processing module; a first sram configured to temporarily store image data for which the first image processing has been performed by the first image processing module; a second sram configured to store a parameter for performing the second image processing for image data that is input to the second image processing module; and a control unit. The control unit stops power supply to the first sram, continues to supply power to a storage area of the second sram in which the parameter is stored, and stops power supply to a control area for writing data to the storage area of the second sram based on that a condition to cause the semiconductor integrated circuit to make a transition into a power-saving mode is satisfied..

Security device having physical unclonable function
The inventive concept provides a security device capable of reducing an area of a die required for implementation of a stable puf by increasing the value of entropy from a predefined number of entropy sources and/or minimizing a blind zone of a validity checking module. The security device uses an asynchronous configuration to minimize a blind zone.

Optoelectronic device having improved optical coupling
An optoelectronic device may include a package having a component for sending/receiving optical signals along a first direction, and a chip of semiconductor material housed within the package. The chip may have a main surface and a portion exposed on the main surface for sending/receiving the optical signals along a second direction different from the first direction.

Stacked mosfet circuits and methods of operating stacked mosfet circuits
Example mosfet circuits include a first metal-oxide-semiconductor field-effect transistor (mosfet) having a gate, a source and a drain, and a second mosfet coupled in series with the first mosfet. The second mosfet has a gate, a source and a drain.

Power switch and semiconductor device thereof
A power switch and a semiconductor device thereof are disclosed. The power switch device includes a first transistor cell, a second transistor cell, a body region and a conductive layer.

Parallel driving circuit of voltage-driven type semiconductor element
A pch driving section of a gate driving circuit applies a high level driving voltage that can be changed by a high side pre-driver to a gate of a p-channel mosfet connected between a high potential side terminal and a high side driving terminal. An nch driving section applies a low level driving voltage to a gate of an n-channel mosfet connected between a low side driving terminal and a low potential side terminal using a low side pre-driver.

Dead time control circuit for a level shifter
Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors.

Semiconductor integrated circuit
A synchronous circuit may be provided. The synchronous circuit may include a first buffer configured to receive an input signal and control the transition timing of an output signal based on a control code.

Semiconductor apparatus

A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.. .

Programmable gain stage based on width ratio of two mosfets

An apparatus and method are provided for controlling the gain of a common source differential amplifier. The common source differential amplifier includes a pair of a metal-oxide-semiconductor field effect transistors (mosfets) each including a gate, a drain, and a source and at least one common source degeneration mosfet in electrical communication between the sources of the pair of mosfets, the at least one common source degeneration mosfet including a plurality of gate structures.

Semiconductor device, semiconductor system, and control semiconductor device

A semiconductor device includes a differential amplification circuit that outputs differential output signals vo1 and vo2, external output terminals pd1 and pd2 to which one of the differential output signals vo1 and vo2 and single end signals vo3 and vo4 is selectively supplied, switch units sw1 and sw2 that control a conduction state between the external output terminal pd1 and the feedback line and a conduction state between the external output terminal pd2 and the feedback line, respectively, resistance elements r1 and r2 respectively provided in series with the switch units sw1 and sw2, a cmfb circuit that controls a common mode voltage of the differential amplification circuit according to a difference between an intermediate voltage vcm of the external output terminals pd1 and pd2 in the feedback line and a reference voltage vref, and a switch unit sw3 that controls to supply a clamp voltage to the feedback line.. .

Power amplifier ramping and power control with forward and reverse back-gate bias

Embodiments of the present disclosure provide a circuit structure and method for power amplifier control with forward and reverse voltage biases to transistor back-gate regions. A circuit structure according to the disclosure can include: a power amplifier (pa) circuit having first and second transistors, the first and second transistors each including a back-gate region, wherein the back-gate region of each of the first and second transistors is positioned within a doped substrate separated from a semiconductor region by a buried insulator layer; and an analog voltage source coupled to the back-gate regions of the first and second transistors of the pa circuit, such that the analog voltage source alternatively supplies a forward bias voltage or a reverse bias voltage to the back-gate regions of the first and second transistors of the pa circuit to produce a continuously sloped power ramping profile..

Switching power supply apparatus and semiconductor device

A switching power supply apparatus includes a pfm control circuit that outputs a clock signal set such that a switching frequency of a switching element varies in accordance with a load state. The clock signal set determines a turn-on timing of the switching element.

Semiconductor device and actuator system

A semiconductor device includes a plurality of h-bridge circuits and a logic circuit which is commonly used for the plurality of h-bridge circuits. The logic circuit controls driving of each of the plurality of h-bridge circuits on the basis of signals which are input thereinto in such a manner that a combination of respective driving states of the plurality of h-bridge circuits meets a predetermined condition..

Semiconductor device and control method thereof

The invention addresses providing a semiconductor device that enables to reduce noise simultaneous with switching. A driver ic which is a semiconductor device includes a drive circuit which drives a control terminal of a pmos drive stage which is a switching element, a noise detection circuit which detects noise in an output signal when switching (turning) the pmos drive stage on or off, and a control circuit which control driving by the drive circuit based on the detected noise..

Semiconductor device

The semiconductor device including first and second transistors configured to provide a first voltage to a first node, the first voltage being a voltage provided from a travel adaptor (ta), a third transistor connected in series with the second transistor and configured to provide a ground voltage to the first node, and a fourth transistor configured to receive a second voltage from a first inductor connected to the first node, and provide the second voltage to a second node as a third voltage for charging a battery connected thereto may be provided.. .

Semiconductor laser and producing a semiconductor laser

In one embodiment of the invention, the semiconductor laser (1) comprises a semiconductor layer sequence (2). The semiconductor layer sequence (2) contains an n-type region (23), a p-type region (21) and an active zone (22) lying between the two.

Ultra-small vertical cavity surface emitting laser (vcsel) and arrays incorporating the same

A laser diode includes a semiconductor structure having an n-type layer, an active region, and a p-type layer. One of the n-type and p-type layers includes a lasing aperture thereon having an optical axis oriented perpendicular to a surface of the active region between the n-type and p-type layers.

Air-cavity dominant vertical cavity surface emitting lasers

Vertical-cavity surface-emitting laser (vcsel) structures are described which enable their use as widely wavelength-swept coherent light sources and multiple-wavelength vcsel arrays. Three general configurations are described: (a) a semiconductor-cavity-dominant (scd) with high reflection at the semiconductor-air interface, (b) an extended-cavity (ec) design in which reflections at the semiconductor-air interface is reduced to insignificance compared to the scd design with a refractive index-matched layer (i.e., ar layer) so the entire structure resonates as one cavity, and (c) an air-cavity-dominant (acd) design which facilitates a larger field confinement in the air gap, and the increased field confinement causes the air gap to be the dominant cavity..

Self-referencing frequency comb based on high-order sideband generation

A frequency comb generator including a semiconductor, wherein the semiconductor outputs a frequency comb in response to frequency mixing of an optical field and at terahertz field in the semiconductor using a high order sideband (hsg) mechanism. The frequency comb spans a bandwidth sufficient for self-referencing and may be used in optical clock applications, for example..

Laser light source device

A laser light source device has a semiconductor laser element, a heat transfer portion having thermal conductivity and connected to the semiconductor laser element, a cooler connected to the heat transfer portion on a side different from the semiconductor laser element, a control object temperature measurement section that measures a control object temperature as the temperature of the heat transfer portion or the cooler, an environmental temperature measurement section that measures an environmental temperature of the laser light source device, and a controller that controls the cooler. The controller is configured to control the cooler such that the control object temperature approaches a predetermined target temperature set according to the environmental temperature.

Semiconductor laser and semiconductor laser arrangement

In one embodiment of the invention, the semiconductor laser (1) comprises a semiconductor layer sequence (2). The semiconductor layer sequence (2) contains an n-type region (23), a p-type region (21) and an active zone (22) lying between the two.

Emitter structures for ultra-small vertical cavity surface emitting lasers (vcsels) and arrays incorporating the same

A laser diode includes a semiconductor structure of a lower bragg reflector layer, an active region, and an upper bragg reflector layer. The upper bragg reflector layer includes a lasing aperture having an optical axis oriented perpendicular to a surface of the active region.

Optoelectronic semiconductor component

The invention relates to an optoelectronic semiconductor component (10) comprising a substrate (1), a first insulator layer (2), and a second insulator layer (3). Furthermore, the semiconductor component (10) comprises an organic semiconductor layer sequence (4) having an active area (4a) which, during operation, generates or receives light, a first electrode (5) and a second electrode (6), and encapsulation (7) which covers the organic semiconductor layer sequence (4) and the first insulator layer (2) completely and covers the second insulator layer (3) and the first electrode (5) or the second electrode (6) partially.

Semiconductor device and manufacturing the same

A semiconductor device includes a first bottom electrode, a second bottom electrode, a switching layer and a top electrode. The first bottom electrode has two edges opposite to each other, and an upper surface.

Electronic device and fabricating the same

This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a semiconductor memory, wherein the semiconductor memory may include: a variable resistance element disposed over a substrate and structured to exhibit different resistance states for storing data; and an upper contact plug disposed over the variable resistance element and coupled to the variable resistance element, wherein the upper contact plug includes a first portion that is disposed between an upper end of the upper contact plug and a lower end of the upper contact plug and the first portion has a width smaller than a width of each of the upper end and the lower end..

A window that covers an optoelectronic semiconductor chip, a panel comprising a plurality of windows, a producing windows and an optoelectronic semiconductor device

A window that covers an optoelectronic semiconductor chip includes an upper face, the upper face including a polygonal shape, wherein at least one corner of the upper face is chamfered. A method of producing a window that covers an optoelectronic semiconductor chip, the method including providing a panel; creating a plurality of holes at an upper face of the panel; dividing the panel along separation lines to obtain a plurality of windows, wherein the separation lines extend through the holes..

Semiconductor light emitting device

A semiconductor light emitting device includes a conductive substrate and a first metal layer disposed on the substrate. The first metal layer is formed so as to be electrically connected with the substrate, and the first metal layer includes an au based material.

Light-emitting diode chip and producing a light-emitting diode chip

A light-emitting diode chip includes a semiconductor layer sequence based on ingaalasp and generates visible light or near-infrared radiation, a current spreading layer located directly on the semiconductor layer sequence and based on algaas, an encapsulation layer applied directly to at least one of the current spreading layer and the semiconductor layer sequence and has an average thickness of 10 nm to 200 nm and a defect density of at most 10/mm2, at least one cover layer applied directly to the encapsulation layer at least in places, at least one non-metallic reflection layer located in places on a side of the current spreading layer facing away from the semiconductor layer sequence and covered in places by the encapsulation layer, and at least one of a mirror layer and an adhesion-promoting layer arranged in places on a side of the reflection layer facing away from the current spreading layers.. .

Light-emitting element

Disclosed according to one embodiment is a light-emitting element comprising: a light-emitting structure comprising a first semiconductor layer, an active layer, and a second semiconductor layer; a second conductive layer electrically connected to the second semiconductor layer; a first conductive layer which is disposed in a plurality of via holes passing through the light-emitting structure and second conductive layer and comprises a plurality of through electrodes electrically connected to the first semiconductor layer; an insulation layer for electrically insulating the plurality of through electrodes from the active layer, second semiconductor layer, and second conductive layer; and an electrode pad disposed in an exposed area of the second conductive layer, wherein the farther away the second conductive layer disposed between the plurality of through electrodes is from the electrode pad, the greater the width of the second conductive layer becomes.. .

Semiconductor light emitting diode

A semiconductor light emitting diode is disclosed. The semiconductor light emitting diode includes a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, a transparent electrode formed on the second conductive semiconductor layer, a non-conductive reflection film covering the circumferential surface of the transparent electrode and having one or more via-holes formed therein, a reflective electrode formed on the non-conductive reflection film, interconnection electrodes filled in the via-holes and electrically connecting the reflective electrode to the transparent electrode, and ohmic contact layers formed between the transparent electrode and the interconnection electrodes and filled in recesses formed at positions of the transparent electrode corresponding to the via-holes by etching or extending through the via-holes from the recesses..

Semiconductor chip

A semiconductor chip (20) is described comprising a semiconductor layer sequence (10) based on a phosphide compound semiconductor material or arsenide compound semiconductor material wherein the semiconductor layer sequence (10) contains a p-type semiconductor region (4) and an n-type semiconductor region (2). The n-type semiconductor region (2) comprises a superlattice structure (20) for improving current spreading, wherein the superlattice structure (20) has a periodic array of semiconductor layers (21, 22, 23, 24).

Method for producing optoelectronic devices comprising light-emitting diodes

A method for producing optoelectronic devices, including the following successive steps: providing a substrate having a first face; on the first face, forming sets of light-emitting diodes including wire-like, conical or frustoconical semiconductor elements; covering all of the first face with a layer encapsulating the light-emitting diodes; forming a conductive element that is insulated from the substrate and extends through the substrate from the second face to at least the first face; reducing the thickness of the substrate; and cutting the resulting structure in order to separate each set of light-emitting diodes.. .

Light emitting diode having improved quantum efficiency at low injection current

Provided is a light emitting semiconductor structure that operates as a light emitting diode (led). In embodiments of the invention, the light emitting semiconductor structure includes a first barrier region, a second barrier region, and a single quantum well having a preselected thickness between the first barrier region and the second barrier region.

Optical semiconductor element and driving optical semiconductor element

An optical semiconductor element includes: an optical waveguide body; a first electrode that is disposed on a second clad layer; a second electrode that is disposed on the second clad layer on one side of the first electrode in a light guiding direction of the optical waveguide body; a third electrode that is disposed on the second clad layer on the other side of the first electrode in the light guiding direction; and at least one fourth electrode that faces the first electrode, the second electrode, and the third electrode with the optical waveguide body interposed therebetween. The optical waveguide body includes a first separation region that electrically separates a first region under the first electrode from a second region under the second electrode and a second separation region that electrically separates the first region under the first electrode and a third region under the third electrode..

Method for manufacturing at least one optoelectronic semiconductor chip, optoelectronic semiconductor chip, and optoelectronic semiconductor component

Disclosed is an optoelectronic semiconductor chip (10) comprising: —a succession of semiconductor layers (1) that has a main plane of extension, an active layer (12) and a bottom surface (1c); —a substrate (41) that is arranged on the bottom surface (1c) of the succession of semiconductor layers (1) and has a base surface (41c) facing away from the bottom surface (1c); and —a succession of joining layers (3) which is arranged in at least some locations between the succession of semiconductor layers (1) and the substrate (41) in a vertical direction; wherein —the substrate (41) laterally protrudes from the succession of semiconductor layers (1) by a maximum of 10 μm.. .

Devices incorporating integrated detectors and ultra-small vertical cavity surface emitting laser emitters

A semiconductor device includes a detector structure. The detector structure includes an integrated circuit on a substrate, and a photo detector on an upper surface of the integrated circuit that is opposite the substrate, where the substrate is non-native to the photo detector.

Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface

A method of forming an electrical device that includes epitaxially growing a first conductivity type semiconductor material of a type iii-v semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type iii-v semiconductor material having a second conductivity type on the plurality of triangular shaped islands to provide a textured surface of a photovoltaic device.

Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface

A method of forming an electrical device that includes epitaxially growing a first conductivity type semiconductor material of a type iii-v semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type iii-v semiconductor material having a second conductivity type on the plurality of triangular shaped islands to provide a textured surface of a photovoltaic device.

Electrical devices making use of counterdoped junctions

An electrical device includes a counterdoped heterojunction selected from a group consisting of a pn junction or a p-i-n junction. The counterdoped junction includes a first semiconductor doped with one or more n-type primary dopant species and a second semiconductor doped with one or more p-type primary dopant species.

Semiconductor device and manufacturing the same

A semiconductor device includes a substrate, a buried doped layer, a first doped well, a multiplication region and a first contact doped region. The substrate has a first doping type, wherein the substrate includes a surface.

Compound semiconductor solar cell

According to an aspect of the present invention, there is provided a compound semiconductor solar cell, comprising a first cell, the first cell including: a first base layer formed of a gallium indium phosphide (gainp)-based compound semiconductor; a first emitter layer forming a p-n junction with the first base layer; a first window layer positioned on a front surface of the first base layer or the first emitter layer; and a first back surface field layer positioned on a back surface of the first emitter layer or the first base layer, wherein the first window layer of the first cell is formed of a four-component iii-v compound semiconductor.. .

Method for manufacturing a compound semiconductor solar cell

According to an aspect of the present invention, there is provided a method for manufacturing a compound semiconductor solar cell, comprising: forming a sacrificial layer on one surface of a mother substrate; forming a compound semiconductor layer on the sacrificial layer; forming a first protective layer formed of a compound semiconductor on the compound semiconductor layer; depositing a second passivation layer on the first passivation layer; attaching a first lamination film on the second protective layer; separating the compound semiconductor layer, the first and second protective layers, and the first lamination film from the mother substrate by performing an elo process to remove the sacrificial layer; forming a back electrode on the compound semiconductor layer; attaching a second lamination film on the back electrode; removing the first lamination film; removing the second protective layer; removing the first protective layer; and forming a front electrode on the compound semiconductor layer.. .

Compound semiconductor solar cell and manufacturing the same

A method for manufacturing a compound solar cell includes forming a rear electrode including a first electrode layer directly contacting a rear surface of a compound semiconductor layer and a second electrode layer positioned on a rear surface of the first electrode layer and formed of a material different from the first electrode layer, and forming a plurality of front electrodes on a front surface of the compound semiconductor layer, forming a plurality of first etch stop layers covering the plurality of front electrodes, and a second etch stop layer covering the front edge portions and the side surfaces of the compound semiconductor layers, etching a portion of the compound semiconductor layer not covered by the plurality of first etch stop layer from the front surface to the rear surface of the compound semiconductor layer, and scribing the rear electrode at a portion where the compound semiconductor layer is removed.. .

Compound semiconductor solar cell and manufacturing a front electrode of the solar cell

According to one aspect of the subject matter described in this application, a method for manufacturing a front electrode of a compound solar cell comprises a step of forming a seed metal layer entirely on a front surface of a compound semiconductor layer, a step of forming a first mask layer covering the seed metal layer in the remaining region except a front electrode formation region, a step of forming a second mask layer on the first mask layer in the same pattern as the first mask layer, a step of forming an electrode metal layer on the seed metal layer in the front electrode formation region, a step of removing the seed metal layer under the first mask layer, and a step of forming a front electrode including the seed metal layer and the electrode metal layer positioned on the front electrode formation region by removing the first mask layer and the second mask layer.. .

Conductive paste composition and semiconductor devices made therewith

The present invention provides a thick-film paste composition comprising an electrically conductive metal and an oxide composition dispersed in an organic medium. The paste composition is printed on the front side of a solar cell device having one or more insulating layers and fired to form an electrode, and is suitable for devices having both highly and lightly doped emitter structures..

Monolithically integrated high voltage photovoltaics with textured surface formed during the growth of wide bandgap materials

A method of forming a photovoltaic device that includes epitaxially growing a first conductivity type semiconductor material of a type iii-v semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type iii-v semiconductor material having a second conductivity type on the plurality of triangular shaped islands..

Monolithically integrated high voltage photovoltaics with textured surface formed during the growth of wide bandgap materials

A method of forming a photovoltaic device that includes epitaxially growing a first conductivity type semiconductor material of a type iii-v semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type iii-v semiconductor material having a second conductivity type on the plurality of triangular shaped islands..

Integrated graphene detectors with waveguides

The present disclosure relates to semiconductor structures and, more particularly, to graphene detectors integrated with optical waveguide structures and methods of manufacture. The structure includes a plurality of non-planar fin structures composed of substrate material, and a non-planar sheet of graphene material extending entirely over each of the plurality of non-planar fin structures..

Semiconductor device and manufacturing same

A semiconductor device includes a first thin film transistor (101) on a substrate (10), the first thin film transistor including: a sub-gate electrode (12); a first insulating layer (14) covering the sub-gate electrode; a main gate electrode (16) formed on the first insulating layer; a second insulating layer (18) covering the main gate electrode; an oxide semiconductor layer (20) having a layered structure of a first layer (20a) and a second layer (20b), the second layer having a larger band gap than the first layer; a first source electrode (22); and a first drain electrode (24), wherein as seen from a direction normal to the substrate, the oxide semiconductor layer (20) includes: a gate opposing region (20g) that overlaps the main gate electrode; a source contact region that is in contact with the first source electrode (22); a drain contact region that is in contact with the first drain electrode; and an offset region (30s, 30d) that is provided at least one of between the gate opposing region and the source contact region and between the gate opposing region and the drain contact region, wherein at least a portion of the offset region overlaps the sub-gate electrode (12) with the first insulating layer (14) and the second insulating layer (18) therebetween.. .

Semiconductor devices

Disclosed is a semiconductor device. The semiconductor device includes a substrate, channel semiconductor patterns vertically stacked and spaced apart from each other on the substrate, a gate electrode running across the channel semiconductor patterns, source/drain regions at opposite sides of the gate electrode, the source/drain regions being connected to the channel semiconductor patterns, and air gaps between the substrate and bottom surfaces of the source/drain regions so that the bottom surfaces of the source/drain regions do not contact the substrate..

Deep gate-all-around semiconductor device having germanium or group iii-v active layer

Deep gate-all-around semiconductor devices having germanium or group iii-v active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate.

Semiconductor device and producing the same

One of the upper surface and the lower surface of a semiconductor layer (7) of a thin-film transistor (101) in a semiconductor device (100) is in contact with a gate insulating layer (5), and the other is in contact with a first insulating layer (11) containing silicon oxide. The semiconductor layer (7) includes a first and second oxide semiconductor layers (7a, 7b).

Multi-gate device

A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.. .

Semiconductor device and forming the same

A semiconductor device is provided, which includes a substrate, a gate and a gate contact. The substrate has a well region, which has a source, a drain and a channel region extending between the source and the drain.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate; at least one source/drain feature at least partially disposed in the substrate; an isolation structure disposed on the substrate and includes a first portion; a gate structure disposed on the first portion of the isolation structure and adjacent to the source/drain feature; and at least one gate spacer disposed on a sidewall of the gate structure, in which a top surface of the first portion of the isolation structure is in contact with the gate structure and is higher than a bottommost surface of the gate spacer.. .

Vertical transistor pass gate device

A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate.

Semiconductor device and charging system using the same

The present disclosure provides a semiconductor device. The semiconductor device includes a transistor.

Semiconductor device comprising a trench structure

A semiconductor device includes a trench structure extending into a semiconductor body from a first surface. The trench structure has a shield electrode, a dielectric structure and a diode structure.

Semiconductor device having compressively strained channel region and making same

A semiconductor device and method making it utilize a three-dimensional channel region comprising a core of a first semiconductor material and an epitaxial covering of a second semiconductor material. The first and second semiconductor materials have respectively different lattice constants, thereby to create a strain in the epitaxial covering.

Heterojunction tfets employing an oxide semiconductor

Heterojunction tunnel field effect transistors (htfets) incorporating one or more oxide semiconductor and a band offset between at least one of a channel material, a source material of a first conductivity type, and drain of a second conductivity type, complementary to the first. In some embodiments, at least one of p-type material, channel material and n-type material comprises an oxide semiconductor.

Semiconductor device

A semiconductor device including: a semiconductor substrate; a drift region of first conductivity type that is formed in the semiconductor substrate; an accumulation region of first conductivity type that is formed above the drift region and has higher concentration than concentration of the drift region; a base region of second conductivity type that is formed above the accumulation region; and a gate trench portion that is formed extending from an upper surface of the semiconductor substrate to the drift region, passing through the base region and the accumulation region, wherein a maximum value of doping concentration of the accumulation region is greater than a maximum value of doping concentration of the base region will be provided.. .

Electric power converter

An electric power converter (100) which is provided with a switching element (101) and a rectifying element (102) that is connected in series to the switching element (101). This electric power converter (100) has a configuration wherein an external electrical load (103) is connected to the connection point of the switching element (101) and the rectifying element (102).

Tunneling field effect transistor (tfet) having a semiconductor fin structure

A tunneling field effect transistor is formed from a fin of semiconductor material on a support substrate. The fin of semiconductor material includes a source region, a drain region and a channel region between the source region and drain region.

Method for making thin film transistor

A method of making a thin film transistor, the method including: forming a gate insulating layer on a gate electrode; placing a semiconductor layer on the gate insulating layer; locating a first photoresist layer, a nanowire structure, a second photoresist layer on the semiconductor layer, the nanowire structure being sandwiched between the first photoresist layer and the second photoresist layer, wherein the nanowire structure comprises one nanowire; forming one opening in the first photoresist layer and the second photoresist layer to form an exposed surface, wherein a part of the nanowire is exposed in the opening; depositing a conductive film layer on the exposed surface of the semiconductor layer, wherein the conductive film layer defines a nano-scaled channel corresponding to the nanowire, the conductive film layer is divided into two regions, one region is used as a source electrode, the other region is used as a drain electrode.. .

Finfet having improved ge channel interfacial layer

A semiconductor device includes a substrate structure. The substrate structure includes a substrate, a plurality of fins each protruding from the substrate structure, a germanium layer on a top surface of the fins, spacers on opposite sides of the germanium layer, an oxide layer on a surface of the germanium layer between the spacers, the oxide layer comprising silicon and germanium, a high-k dielectric layer on the oxide layer and on inner sidewalls of the spacers, and a gate electrode on the high-k dielectric layer..

Method for making thin film transistor

A method of making a thin film transistor, the method including: providing an insulating layer on a semiconductor substrate, forming a semiconductor layer on the insulating layer; locating a first photoresist layer, a nanowire structure, a second photoresist layer on the semiconductor layer, wherein the nanowire structure comprises a nanowire; forming an opening in the first photoresist layer and the second photoresist layer to form an exposed surface, wherein a part of the nanowire is exposed in the opening; depositing a conductive film layer on the exposed surface of the semiconductor layer, wherein the conductive film layer defines a nano-scaled channel corresponding to the nanowire, and the conductive film layer is divided into two regions by the nano-scaled channel, one region is used as a source electrode, and the other region is used as a drain electrode; forming a gate electrode on the semiconductor substrate.. .

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a gate structure on a base substrate and forming a first dielectric layer on the base substrate.

Vertical field effect transistor with reduced parasitic capacitance

Embodiments are directed to a method and resulting structures for a semiconductor device having reduced parasitic capacitance. A semiconductor fin is formed on a substrate.

Replacement metal gate stack with oxygen and nitrogen scavenging layers

A method is presented for tuning work functions of transistors. The method includes forming a high-k dielectric over a semiconductor substrate, and forming a work function stack over the high-k dielectric, the work function stack including a first layer having a nitrogen (n) scavenging element, a second layer having an oxygen (o) scavenging element, and a third layer being a conducting layer..

Semiconductor devices and structures and methods of formation

A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate.

Semiconductor device

A semiconductor device includes first and second electrodes spaced apart along a first direction, a first semiconductor region of a first conductivity type between the first and second electrodes, first and second conductive regions between the first semiconductor region and the second electrode and electrically connected to the second electrode, a third electrode between the first and second conductive regions, second and third semiconductor regions of a second conductivity type respectively between the first and second conductive regions and the third electrode, and fourth and fifth semiconductor regions of the first conductivity type respectively between the second and third semiconductor regions and the second electrode. The third electrode extends in the first direction toward the first electrode farther than portions of the second and third semiconductor regions that are alongside the third electrode..

Semiconductor device having an electrostatic discharge protection structure

A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. A transistor structure is formed is the semiconductor body.

Silicon carbide semiconductor device and manufacturing silicon carbide semiconductor device

A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide layer of the first conductivity type, and an insulating film. In the silicon carbide semiconductor device, no fluorine or chlorine is detectable in the insulating film, at a boundary layer of the insulating film and the first silicon carbide layer, or at the surface of first silicon carbide layer where the insulating film is provided..

Doped diamond semiconductor and manufacture

A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer.

Semiconductor device and manufacturing same

A semiconductor device includes a first semiconductor layer of a first conductivity type having a first surface crossing a first direction; a first semiconductor region of a second conductivity type provided in the first semiconductor layer, and including first and second layers aligned in the first direction; a second semiconductor region of the second conductivity type electrically connected to the first semiconductor region, and having a portion provided between the first surface and the first semiconductor region; and a third semiconductor region of the first conductivity type having a portion provided between the first surface and the portion of the second semiconductor region. The semiconductor device further includes a control electrode provided on the second semiconductor region via a first insulating film; an electrode electrically connected to the second and third semiconductor regions; and a sidewall region provided between the first semiconductor region and the first semiconductor layer..

Semiconductor device

A semiconductor device includes: a first gan based semiconductor layer; a second gan based semiconductor layer disposed on the first layer and having a bandgap larger than that of the first layer; a first electrode disposed on the second layer; a second electrode disposed on the second layer; a p-type third gan based semiconductor layer disposed between the first electrode and the second electrode on the second layer; a third electrode disposed on the third layer; a p-type fourth gan based semiconductor layer disposed directly on the second layer and disposed separated from the third layer; a first insulating film disposed on the fourth layer; and a first field plate electrode disposed interposing the first insulating film in a space with the fourth layer, the first field plate electrode being separated from the fourth layer, and the first field plate electrode electrically connected to the first electrode.. .

Organic light emitting display

Organic light-emitting display is disclosed. The organic light-emitting display includes a first substrate, a semiconductor layer positioned on the first substrate, a first insulating layer positioned on the semiconductor layer, a gate metal layer positioned on the first insulating layer, a second insulating layer with a contact hole exposing part of the gate metal layer, a source-drain metal layer positioned on the second insulating layer and electrically connected to the gate metal layer via the contact hole, a third insulating layer positioned on the source-drain metal layer, a fourth insulating layer positioned on the third insulating layer, and a pixel electrode positioned on the fourth insulating layer, wherein the fourth insulating layer fully covers the contact hole, and a stepped portion of the pixel electrode caused by the fourth insulating layer is spaced apart from the contact hole..

Organic electroluminescent display panel, manufacturing manufacturing the same, and display device

An organic electroluminescent display panel and a method for manufacturing the same and a display device are disclosed. The organic electroluminescent display panel includes a base substrate, an anode and a cathode on the base substrate, and an organic light emitting layer located between the anode and the cathode, wherein the organic electroluminescent display panel further includes a semiconductor layer covering the entire base substrate, the semiconductor layer located between one of the anode and the cathode and the organic light emitting layer..

Solid state image sensor, production method thereof and electronic device

A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.. .

Image sensors

An image sensor includes a photoelectric conversion element and a charge storage node coupled to the photoelectric conversion element. The charge storage node may store photocharges generated in the photoelectric conversion element.

Semiconductor device and manufacturing the same

A semiconductor device includes a first conductive wiring, at least one first dielectric layer, at least one second dielectric layer and a second conductive wiring. The at least one first dielectric layer is over the first conductive wiring.

Method for manufacturing cmos image sensor

A semiconductor device includes a substrate, a conductive layer, a transparent layer, a transparent hard mask layer, a carrier, and a device layer. The substrate has a first surface and a second surface opposite to each other.

Optoelectronic modules operable to collect spectral data and distance data

Optoelectronic modules operable to collect distance data and spectral data include demodulation pixels operable to collect spectral data and distance data via a time-of flight approach. The demodulation pixels include regions with varying charge-carrier mobilities.

Implantation process for semiconductor device

A semiconductor device includes a substrate and a device. The substrate has a first surface and a second surface opposite to each other.

Photoelectric conversion device

An off-leakage current of a photodiode is reduced in a photoelectric conversion device. A photoelectric conversion device (100) includes: an oxide semiconductor layer (5) provided on a substrate (1); a passivation film (6) and a planarizing film (7) which are stacked on the oxide semiconductor layer; and a photodiode (9) including a lower electrode (91), a photoelectric conversion layer (92), and an upper electrode (93).

Solid-state imaging device, manufacturing the same, and electronic device

The present technology relates to a solid-state imaging device capable of inhibiting peeling of a fixed charge film while inhibiting dark current, a method of manufacturing the same, and an electronic device.—a solid-state imaging device provided with a semiconductor substrate in which a plurality of photodiodes is formed, a groove portion formed in a depth direction from a light incident side for forming an element separating unit between adjacent photoelectric conversion elements on the semiconductor substrate, a first fixed charge film formed so as to cover a surface of a planar portion on the light incident side of the semiconductor substrate, and a second fixed charge film formed so as to cover an inner wall surface of the groove portion formed on the semiconductor substrate is provided. The present technology is applicable to a backside illumination cmos image sensor, for example..

Image sensor

An image sensor includes first photoelectric elements, second photoelectric elements under the first photoelectric elements, and a pixel circuit including first semiconductor devices and second semiconductor devices under second photoelectric elements. The first semiconductor devices are connected to at least one of the first photoelectric elements.

Solid-state image sensor and manufacturing the same

A method of manufacturing a solid-state image sensor, includes forming a first isolation region of a first conductivity type in a semiconductor layer having first and second surfaces, the forming the first isolation region including first implantation for implanting ions into the semiconductor layer through the first surface, forming charge accumulation regions of a second conductivity type in the semiconductor layer, performing first annealing, forming an interconnection on a side of the first surface of the semiconductor layer after the first annealing, and forming a second isolation region of the first conductivity type in the semiconductor layer, the forming the second isolation region including second implantation for implanting ions into the semiconductor layer through the second surface. The first and second isolation regions are arranged between the adjacent charge accumulation regions..

Manufacturing array substrate

A manufacturing method for an array substrate is provided. The manufacturing method includes steps of: forming a first metal layer, a gate electrode layer, a gate electrode insulated layer, a semiconductor layer, a second metal layer, a source electrode layer, and a drain electrode layer on a base substrate in order.

Display device, semiconductor device, and manufacturing display device

A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.. .

Logic circuit and semiconductor device

To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13a or less per micrometer in channel width.

Gate structure, manufacturing gate structure, and display device

A method for manufacturing a gate structure includes: forming a buffer layer on a lateral surface of a substrate; forming a groove on the buffer layer, where the groove penetrates the buffer layer; forming a gate in the groove, where an upper surface of the gate and an upper surface of the buffer layer are located on a same plane; forming an insulating layer on the upper surface of the gate and the upper surface of the buffer layer; forming, on an upper surface of the insulating layer, a semiconductor layer disposed opposite the gate; and forming, on an upper surface of the semiconductor layer and/or the upper surface of the insulating layer, a data line partially overlapping the semiconductor layer. A display device is further disclosed.

Semiconductor device

An object is to provide a semiconductor device using an oxide semiconductor having stable electric characteristics and high reliability. A transistor including the oxide semiconductor film in which a top surface portion of the oxide semiconductor film is provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film and functioning as a channel protective film is provided.

Active matrix substrate and manufacturing same, display device using active matrix substrate

An active matrix substrate (1001) includes: a plurality of pixel regions arranged on a substrate (1) in a matrix pattern extending in a first and a second direction; a plurality of gate lines g extending in the first direction; and a plurality of source lines s extending in the second direction, the active matrix substrate having a display area (800) including a plurality of pixel regions and a non-display area (900) located in a periphery of the display area, wherein: the pixel regions each include a thin-film transistor (101) including an oxide semiconductor layer, and a pixel electrode (15) formed integral with a drain electrode (9); gate electrode (3) and the gate lines g are made of a first transparent conductive film; the drain electrode (9) and the pixel electrode (15) are made of a second transparent conductive film and provided in the non-display area (900); and the active matrix substrate further includes a plurality of gate signal lines made of a metal film and a first connecting portion that connects each of the gate lines g to one of the gate signal lines.. .

Asymmetric junction engineering for narrow band gap mosfet

A method for forming a semiconductor device. It includes forming fin structures on a substrate, where the fin structure defines source and drain regions.

Finfet devices with multiple channel lengths

A method including patterning a continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an angle relative to the second line segment, and forming a first gate and a second gate substantially parallel to each other, the first gate substantially covering sides and a top of a portion of the first segment of the continuous fin, the second gate substantially covering sides and a top of a portion of the second segment of the continuous fin.. .

Semiconductor device and fabricating the same

A semiconductor device includes a stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.. .

Manufacturing semiconductor structure

A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: forming a bottom oxide layer; forming a first conductive layer on the bottom oxide layer; forming a stack including alternately arranged second conductive layers and insulating layers on the first conductive layer; forming a first opening having a first cross-sectional width and penetrating through the stack and a portion of the first conductive layer; forming a second opening having a second cross-sectional width and penetrating through the first conductive layer below the first opening for exposing the bottom oxide layer, wherein the second cross-sectional width is smaller than the first cross-sectional width; and forming a memory layer on a sidewall of the first opening and filled in the second opening..

Method of manufacturing semiconductor device

A semiconductor device is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage misfet is formed over the semiconductor substrate in a lower-breakdown-voltage misfet formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage misfet is formed over the semiconductor substrate in a higher-breakdown-voltage misfet formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage misfet, and the higher-breakdown-voltage misfet.

Semiconductor device and manufacturing method thereof

In a semiconductor device including a higher-breakdown-voltage misfet, an improvement is achieved in the breakdown voltage of the misfet, while preventing an increase in the area of the misfet. A gate pattern including a gate electrode of the higher-breakdown-voltage misfet is formed higher in level than a gate pattern including a gate electrode of a lower-breakdown-voltage misfet.

Semiconductor memory device

A semiconductor memory device includes a first electrode film and a second electrode film spreading along a first direction and a second direction, first insulating plates intermittently disposed along the first direction and each of two columns separated in the second direction from each other, second insulating plates provided between the two columns, intermittently disposed along the first direction and each of n columns, third insulating plates provided between one of the two columns and a column formed of the second insulating plates, intermittently disposed along the first direction, a first insulating member provided between the first insulating plate and the third insulating plate, and a second insulating member provided between the second insulating plate and the third insulating plate. The first electrode film is divided into two parts between the two columns.

Methods of fabricating semiconductor memory devices

A method of fabricating a semiconductor memory device includes forming a bit line and a bit line capping pattern on the semiconductor substrate, forming a first spacer covering a sidewall of the bit line capping pattern and a sidewall of the bit line, forming a contact plug in contact with a sidewall of the first spacer and having a top surface that is lower than an upper end of the first spacer, removing an upper portion of the first spacer, forming a first sacrificial layer closing at least an entrance of the void, forming a second spacer covering the sidewall of the bit line capping pattern and having a bottom surface in contact with a top surface of the first spacer, and removing the first sacrificial layer. The bit line capping pattern is on the bit line.

Semiconductor device and fabricating the same

A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.. .

Semiconductor devices including structures for reduced leakage current and fabricating the same

A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer.

Memory cells and memory arrays

Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors.

Semiconductor devices and methods of manufacturing the same

A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgas sing prevention pattern sequentially stacked..

Vertical fet with reduced parasitic capacitance

A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas.

Two dimension material fin sidewall

A semiconductor structure, such as a microchip that includes a finfet, includes fins that have a 2d material, such as graphene, upon at least the fin sidewalls. The thickness of the 2d material sidewall may be tuned to achieve desired finfet band gap control.

Two dimension material fin sidewall

A semiconductor structure, such as a microchip that includes a finfet, includes fins that have a 2d material, such as graphene, upon at least the fin sidewalls. The thickness of the 2d material sidewall may be tuned to achieve desired finfet band gap control.

Two dimension material fin sidewall

A semiconductor structure, such as a microchip that includes a finfet, includes fins that have a 2d material, such as graphene, upon at least the fin sidewalls. The thickness of the 2d material sidewall may be tuned to achieve desired finfet band gap control.

Metal-oxide semiconductor (mos) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent mos standard cells

Metal-oxide semiconductor (mos) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent mos standard cells are disclosed. In one aspect, a mos standard cell includes supply rails disposed in a first metal layer and along respective axes in an x-axis direction.

Semiconductor device and manufacturing the same

According to one embodiment, a semiconductor device includes: a first semiconductor layer; and a plurality of first transistors including a plurality of first gate structures provided on the first semiconductor layer, a first channel region provided in the first semiconductor layer and under the first gate structure, and a plurality of first diffusion regions provided in the first semiconductor layer in a manner to sandwich the first channel region.. .

Semiconductor package

A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip..

Substrate with array of leds for backlighting a display device

A circuit component for a display includes a substrate and a circuit trace having a predetermined pattern disposed on a surface of the substrate. A plurality of semiconductor die are connected to the substrate via the circuit trace.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a first substrate including a plurality of first pads disposed on a first surface of the first substrate, a second substrate including a plurality of second pads disposed on a second surface of the substrate, a plurality of conductive bumps bonded the plurality of first pads with the plurality of second pads correspondingly, a solder bracing material disposed on the first surface and surrounded the plurality of conductive bumps, an underfill material surrounded the plurality of conductive bumps and disposed between the solder bracing material and the second surface, and a rough interface between the solder bracing material and the underfill material. The rough interface includes a plurality of protruded portions and a plurality of recessed portions..

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes an interconnect structure, at least one first metal pad, at least one second metal pad, at least one first bump, at least one second bump, at least one photosensitive material, and a bonding layer. The first metal pad and the second metal pad are disposed on and electrically connected to the interconnect structure.

Semiconductor device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5).

Package structure

A package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer.

Control of warpage using abf gc cavity for embedded die package

Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer.

Semiconductor device

A semiconductor device encompasses a cooler made of ceramics, having a first main face and a second main face, being parallel and opposite to the first main face, defined by two opposite side faces perpendicular to the first and second main faces, a plurality of conductive-pattern layers delineated on the first main face, a semiconductor chip mounted on the first main face via one of the plurality of conductive-pattern layers, and a seal member configured to seal the semiconductor chip.. .

Semiconductor device and manufacturing the semiconductor device

According to the present invention, a semiconductor device includes a substrate having a metallic pattern formed on a top surface of the substrate, a semiconductor chip provided on the metallic pattern, a back surface electrode terminal in flat plate form connected to the metallic pattern with a wire, a front surface electrode terminal in flat plate form, the front surface electrode terminal being in parallel to the back surface electrode terminal above the back surface electrode terminal, extending immediately above the semiconductor chip, and being directly joined to a top surface of the semiconductor chip, a case surrounding the substrate and a seal material for sealing an inside of the case.. .

Semiconductor device and manufacturing method thereof

A semiconductor device having an emi shield layer and/or emi shielding wires, and a manufacturing method thereof, are provided. In an example embodiment, the semiconductor device includes a semiconductor die, an emi shield layer shielding the semiconductor die, and an encapsulating portion encapsulating the emi shield layer.

Porous silicon dicing

A method of dicing a semiconductor wafer may include forming a porous silicon layer along an outline of dies singulated from the semiconductor wafer. The method may include sealing an active surface of the semiconductor wafer, including the porous silicon layer.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, a carbon-containing diffusion barrier, a phosphorus-containing source/drain feature, a gate structure, and a gate spacer. The substrate has a channel region.

Semiconductor device with multi-layer metallization

One or more embodiments are related to a semiconductor device, comprising: a metallization layer comprising a plurality of portions, each of the portions having a different thickness. The metallization layer may be a final metal layer..

Fuse of semiconductor device and forming the same

A fuse of a semiconductor device may include: fuse link suitable for extending in a first direction and connecting first and second electrodes; a dummy strip suitable for extending in the first direction, and with a predetermined distance from the fuse link in a second direction perpendicular to the first direction; and an air channel formed between the fuse link and the dummy strip to contact with the fuse link.. .

Methods of forming a semiconductor device comprising first and second nitride layers

A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.. .

Semiconductor device structure and forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate.

Forming conductive plugs for memory device

Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs..

Three-dimensional semiconductor device with isolated dummy pattern

A three-dimensional (3d) semiconductor device is provided, comprising: a substrate having a first area and a second area, and the second area adjacent to and surrounding the first area (i.e. Active area), wherein an array pattern is formed in the first area; a stack structure having multi-layers formed above the substrate, and the multi-layers comprising active layers (ex: conductive layers) alternating with insulating layers above the substrate.

Semiconductor package and manufacturing the same

A semiconductor package includes a first semiconductor chip positioned above a first substrate. A second substrate is positioned above the first substrate.

Integration of a passive component in an integrated circuit package

A semiconductor package includes a leadframe and a semiconductor die attached to the leadframe by way of solder posts. In a stacked arrangement, the package also includes a passive component disposed between the leadframe and the semiconductor die and electrically connected to the semiconductor die through the leadframe..

Integration of a passive component in a cavity of an integrated circuit package

A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement..

Integration of a passive component in a cavity of an integrated circuit package

A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in which at least a portion of the passive component is disposed in a stacked arrangement..

Smd package

A package encloses a power semiconductor die that has a first load terminal at a die frontside facing a footprint side of the package and a second load terminal arranged at a die backside facing a top side of the package. The package also includes a lead frame configured to electrically and mechanically couple the package to a support.

Semiconductor device

In a semiconductor device, the marginal edge of a resist member on the side closer to a substrate is between first and third positions on a metal base plate. The third position is directly under an outer side surface of a metal plate.

Semiconductor device, manufacturing semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.. .

Semiconductor device, manufacturing semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.. .

Semiconductor device, manufacturing semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.. .

Semiconductor component and producing a semiconductor component

According to an embodiment of a method, the method includes forming a first thermally conductive layer on an outer surface of a semiconductor package. The first thermally conductive layer formed on the outer surface of the semiconductor package is configured to be mounted to an external heat sink..

Conditions for burn-in of high power semiconductors

Techniques for improving reliability of iii-n devices include holding the iii-n devices at a first temperature less than or equal to 30° for a first period of time while applying a first gate-source voltage lower than a threshold voltage of the iii-n devices and a first drain-source voltage greater than 0.2 times a break down voltage of the iii-n devices; and holding the iii-n devices at a second temperature greater than the first temperature for a second period of time while applying a second gate-source voltage lower than a threshold voltage of the iii-n devices and a second drain-source voltage greater than 0.2 times a breakdown voltage of the iii-n devices. After holding the iii-n devices at the first and second temperatures, screening the iii-n devices based on electrical performance of one or more parameters of the iii-n devices..

Target location in semiconductor manufacturing

A method of overlay control in silicon wafer manufacturing comprises firstly locating a target comprising a diffraction grating on a wafer layer; and then measuring the alignment of patterns in successive layers of the wafer. The location of the target may be done by the pupil camera rather than a vision camera by scanning the target to obtain pupil images at different locations along a first axis.

Finfet semiconductor structure having hybrid substrate and fabricating the same

A finfet semiconductor structure includes first fins and second fins extended from a semiconductor substrate, and a gate structure disposed over the first fins and the second fins. Each first fin includes a first semiconductor portion connected to the semiconductor substrate and a second semiconductor portion over the semiconductor substrate.

Semiconductor device

A substrate has an nmos region and a pmos region. A first gate electrode structure is disposed on the nmos region of the substrate.

Semiconductor device and fabrication method thereof

A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes providing a base substrate including a first region and a second region; and forming a first doped region in the first region, and a second doped region in the second region.

Method and structure for forming vertical transistors with shared gates and separate gates

A method for manufacturing a semiconductor device includes forming a fin on a substrate, removing one or more portions of the fin prior to forming a gate structure on the fin, forming the gate structure on the fin, and simultaneously removing one or more additional portions of the fin and one or more portions of the gate structure aligned with the one or more additional portions of the fin to create a fin edge portion aligned with a gate structure edge portion.. .

3d semiconductor device and system

A 3d semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors overlaying the at least one first metal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell overlaying the memory peripheral circuits; and a second memory cell overlaying the first memory cell, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type.. .

Conductive powder formation method, device for forming conductive powder, and forming semiconductor device

A method of forming a conductive powder includes reducing, by a reduction reaction, a conductive powder precursor gas using a plasma. Reducing the conductive powder precursor gas forms the conductive powder.

Three-dimensional memory device having conductive support structures and making thereof

An alternating stack of insulating layers and sacrificial material layers is formed over a horizontal layer, which can be formed over a lower-interconnect-level dielectric material layer overlying a substrate. Structural integrity of insulating layers vertically spaced from one another by backside recesses during replacement of sacrificial material layers with electrically conductive layers can be enhanced by forming electrically inactive laterally-insulated support structures concurrently with formation of laterally-insulated conductive via structures that vertically extend through each layer in the alternating stack and through the horizontal layer and to lower-interconnect-level metal interconnect structures.

Method of manufacturing a semiconductor device

Provided herein may be a method of manufacturing a semiconductor device. The method may include: forming a first stack in which a first pad region, a second pad region and first dummy region are successively defined; forming a second stack on the first stack; forming a first pad structure and a first reference pattern by patterning the second stack, the first pad structure being disposed on the first pad region and having a stepped shape, the first reference pattern being disposed on the first dummy region of the first stack; forming a first pad mask pattern on the first stack, the first pad mask pattern being aligned by measuring the distance from the first reference pattern thereto and covering the first and second pad regions; and forming a second pad structure having a stepped shape by patterning the second pad region while shrinking the first pad mask pattern..

Methods of forming one or more covered voids in a semiconductor substrate, methods of forming field effect transistors, methods of forming semiconductor-on-insulator substrates, methods of forming a span comprising silicon dioxide, methods of cooling semiconductor devices, methods of forming electromagnetic radiation emitters and conduits, methods of forming imager systems, methods of forming nanofluidic channels, fluorimetry methods and integrated circuitry

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials.

Semiconductor device, semiconductor wafer and semiconductor device manufacturing method

A semiconductor device manufacturing method is disclosed. The semiconductor device manufacturing method includes: a preparation step of preparing a semiconductor wafer; a removal step of removing a thickness part of the semiconductor wafer; and a cutting step of cutting the semiconductor wafer.

Semiconductor package device and forming package body

An apparatus for packaging a semiconductor device is provided. The apparatus includes a first mold, a second mold and a support element.

Light irradiation type heat treatment apparatus

A light diffusion plate made of quartz and provided with a plurality of recessed spherical surfaces is placed on an upper chamber window so as to be in opposed relation to a central portion of a semiconductor wafer. Flashes of light emitted from flash lamps and passing by the side of the light diffusion plate impinge upon a peripheral portion of the semiconductor wafer.

Control warpage in a semiconductor chip package

A method to control warpage in a semiconductor chip package that includes: attaching a semiconductor chip to a semiconductor chip package; attaching a stiffener to the semiconductor chip package so that the semiconductor chip is contained within the stiffener, the stiffener having a coefficient of thermal expansion (cte) less than that of the substrate on which the chip is assembled; attaching the semiconductor chip package to a laminate substrate; and removing the stiffener.. .

Method of making a plurality of packaged semiconductor devices

A method of making a plurality of packaged semiconductor devices. The method includes providing a carrier blank having a die receiving surface and an underside.

Substrate design for semiconductor packages and forming same

A device includes a first die, a second die, one or more redistribution layers (rdls) electrically connected to the first die, a plurality of connectors on a surface of the one or more rdls and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more rdls and the plurality of connectors.

Fan-out wafer level package with resist vias

Fan-out wafer level packages with resist vias are provided. In an implementation, an example wafer level process or panel fabrication process includes adhering a die to a carrier, applying a temporary resist layer over the die and the carrier, developing the resist layer to form channels or spaces, filling the channels or the spaces with a molding material, removing the remaining resist to create vias in the molding material, and metalizing the vias in the molding material to provide conductive vias for the microelectronics package.

Reduction of dishing during chemical mechanical polish of gate structure

A semiconductor device includes a semiconductor substrate, a gate structure and at least one cmp resistant structure. The gate structure is over the semiconductor substrate.

Spectrally and temporally engineered processing using photoelectrochemistry

Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface.

Methods for manufacturing semiconductor devices

An example method for manufacturing a semiconductor device includes forming a nitride, carbide, or metal film on a substrate in a chamber using pe-ald, pulse-pe-cvd or pe-cvd, purging an interior of the chamber, forming an oxide film on the substrate in the chamber using pe-ald, pulse-pe-cvd or pe-cvd, and supplying a reducing gas into the chamber to create a reduction atmosphere and purging the interior of the chamber. The forming of the nitride film, carbide, or metal, purging, forming an oxide film, and supplying the reducing gas may be repeated a plurality of times..

Semiconductor device with metallization structure and manufacturing thereof

A semiconductor device includes a semiconductor substrate with a first side and a second side, and at least one doping region formed at the first side of the semiconductor substrate. The semiconductor device further includes a first metallization structure at the first side of the semiconductor substrate and on and in contact with the at least one doping region, and a second metallization structure at the second side of the semiconductor substrate.

Semiconductor device manufacturing method and semiconductor device

To enhance efficiency of a process of implanting impurities into a silicon carbide semiconductor layer. To provide a method of manufacturing a semiconductor device including a silicon carbide semiconductor layer, the method of manufacturing including: implanting impurities multiple times to an impurity implantation region in the silicon carbide semiconductor layer to different depths, with temperature of the silicon carbide semiconductor layer being set to be equal to or lower than 150° c.

Optical modulation of on-chip thermionic emission using resonant cavity coupled electron emitters

A photonic electron emission device includes an emitter, a photonic energy conduit evanescently coupled to the emitter, and an anode. The emitter includes a component selected from the group consisting of a metal, a semimetal, a semiconductor having a bandgap that is less than about 3.5 ev.

Photoelectric conversion element and photoelectric conversion element module

There are provided a photoelectric conversion element and a photoelectric conversion element module including the photoelectric conversion element, the photoelectric conversion element including a transparent substrate, a first and second transparent conductive layer arranged on the transparent substrate, a photoelectric conversion layer arranged on the first transparent conductive layer, a porous insulating layer covering the photoelectric conversion layer, a reflective layer arranged on the porous insulating layer, and a counter conductive layer that are arranged on the reflective layer, in which the photoelectric conversion layer contains a porous semiconductor, a carrier-transport material, and a photosensitizer, and in which an area of the orthogonal projection of the porous insulating layer onto the transparent substrate and an area of the orthogonal projection of the reflective layer onto the transparent substrate are each larger than an area of the orthogonal projection of the photoelectric conversion layer onto the transparent substrate.. .

Semiconductor memory device

A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation.

Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and operating

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell.

Semiconductor memory device

According to embodiments, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode and includes a metal film and a resistance change film.

Multi-port memory and semiconductor device

A memory circuit includes: a control circuit generating first and second start signals within a single signal cycle of an input clock signal; an address control circuit coupled to a plurality of address ports for receiving a plurality of address signals and activating one of word lines corresponding to one of the address signals based on the first or second start signals; and a data input/output circuit for writing or reading data by selecting one of memory cells coupled to the activated word line. The control circuit includes: a start signal generation unit that generates the first start signal in response to a first pulse signal and the second start signal in response to a second pulse signal, and a pulse signal generation unit that generates the first pulse signal in response to the input clock signal and the second signal in response to the first start signal..

Semiconductor memory device and operating method thereof

A semiconductor memory device may include a sense amplifier for sensing and amplifying data of a bit line pair with pull-up and pull-down driving voltages; a voltage supplier for supplying a power supply voltage or an internal voltage lower than the power supply voltage as the pull-up driving voltage through a pull-up power supply line in response to a first or second pull-up control signal, and supplying a ground voltage as the pull-down driving voltage through a pull-down power supply line in response to a pull-down control signal; a voltage detector for detecting a voltage level of the power supply voltage and outputting a detection signal; and a control signal generator for generating the first and second pull-up control signals, and the pull-down control signal and delaying an enabling timing of one of the first pull-up and pull-down control signals in response to the detection signal.. .

Semiconductor memory device and reading semiconductor memory device

A semiconductor memory device includes: a first bit line; a second bit line connected to the first bit line via a first switch; a charge transfer section including: a first holding section connected to the second bit line, the first holding section being configured to hold a readout voltage from a memory section that stores data, and a second holding section connected to the first bit line, the second holding section being configured to hold a voltage generated due to transfer of charges between the first holding section and the second holding section, the charge transfer section being configured to transfer charges between the first holding section and the second holding section via the first bit line; and a comparison section configured to compare a voltage held in the second holding section with a reference voltage.. .

Data processing device

A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position.

Display with wireless data driving and making same

A large-panel liquid crystal display uses wireless data transmission to provide display data to the pixels arranged in a two-dimensional array of pixel rows and pixel columns in the display area. Pixels are also arranged into pixel groups with each group having a plurality of pixel blocks.

System, method and computer program product for systematic and stochastic characterization of pattern defects identified from a semiconductor wafer

A system, method, and computer program product are provided for systematic and stochastic characterization of pattern defects identified from a fabricated component. In use, a plurality of pattern defects detected from a fabricated component are identified.

Embedded sensor chips in polymer-based coatings

Systems, methods, and electronic circuits facilitating embedded sensor chips in polymer-based coatings are provided. In one example, a method comprises fabricating an electronic circuit, the electronic circuit comprising one or more semiconductor devices, one or more sensors, and a communication element; encapsulating the electronic circuit within an insulator, resulting in an encapsulated circuit; and dispersing the encapsulated circuit into a lacquer solution comprising a polymer carrier and a solvent..

Embedded sensor chips in polymer-based coatings

Systems, methods, and electronic circuits facilitating embedded sensor chips in polymer-based coatings are provided. In one example, a method comprises fabricating an electronic circuit, the electronic circuit comprising one or more semiconductor devices, one or more sensors, and a communication element; encapsulating the electronic circuit within an insulator, resulting in an encapsulated circuit; and dispersing the encapsulated circuit into a lacquer solution comprising a polymer carrier and a solvent..

Pattern centric process control

Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns.

Information processing device and control method therefor

An information processing apparatus manufactured at low cost and with ease and that is capable of making a search for a ground state of an arbitrary ising model. An information processing unit containing a plurality of semiconductor chips, each retains a value of one spin or values of a plurality of spins and simulates interactions among the spins, inter-chip wiring between the necessary semiconductor chips, and a control unit that cause each semiconductor chip to perform interaction computation.

Semiconductor device

A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (roi) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor..

Semiconductor device, position detection device, and control semiconductor device

A sampling circuit samples a signal and outputs sampling data. A arithmetic circuit calculates a real part and an imaginary part of the sampling data.

Array substrate, touch display panel and calculating touch pressure

Provided are an array substrate, a touch display panel and a method for calculating touch pressure. The array substrate includes: a display region with a non-display region around the display region, thin film transistors in the display region and having an active layer, at least two semiconductor pressure sensors, a bias voltage applying circuit for applying a bias voltage to each semiconductor pressure sensor, and a voltage detecting circuit for acquiring a strain voltage from each semiconductor pressure sensor.

Pattern forming method, manufacturing electronic device, monomer for producing resin for semiconductor device manufacturing process, resin, producing resin, actinic ray-sensitive or radiation-sensitive resin composition, and actinic ray-sensitive or radiation-sensitive film

Provided are a pattern forming method including a film forming step of forming a film using a resin composition containing a resin (a) obtained from a monomer having a silicon atom, the monomer having a turbidity of 1 ppm or less based on jis k0101:1998 using formazin as a reference material and an integrating sphere measurement system as a measurement system, in which the pattern forming method is capable of remarkably improving scum defect performance, particularly in formation of an ultrafine pattern (for example, a line-and-space pattern having a line width of 50 nm or less, or a hole pattern having a hole diameter of 50 nm or less); and a method for manufacturing an electronic device, using the pattern forming method.. .

Mask blank, manufacturing phase shift mask, and manufacturing semiconductor device

The mask blank (100) in which a phase shift film (2) made of a material containing silicon, a light shielding film (3) made of a material containing chromium, oxygen, and carbon, and a hard mask film (4) made of a material containing one or more elements selected from silicon and tantalum are provided in this order on a transparent substrate (1) is characterized in that the light shielding film (3) is a single layer film having a composition gradient portion with an increased oxygen content at a surface on the hard mask film (4) side and in a region close thereto, the light shielding film (3) has a maximum peak of n1s narrow spectrum obtained by analysis of x-ray photoelectron spectroscopy of lower detection limit or less, and a part of the light shielding film (3) excluding the composition gradient portion has a chromium content of 50 atom % or more and has a maximum peak of cr2p narrow spectrum obtained by analysis of x-ray photoelectron spectroscopy at binding energy of 574 ev or less.. .

Semiconductor device and method of manufacturing same

To reduce a production cost of a semiconductor device and provide a semiconductor device having improved characteristics. A grating coupler has a plurality of projections separated from each other in an optical waveguide direction and a slab portion formed between any two of the projections adjacent to each other and formed integrally with them; a mos optical modulator has a projection extending in the optical waveguide direction and slab portions formed on both sides of the projection, respectively, and formed integrally therewith.

Method of forming photonics structures

The disclosed embodiments relate to an integrated circuit structure and methods of forming them in which photonic devices are formed on the back end of fabricating a cmos semiconductor structure containing electronic devices. Doped regions associated with the photonic devices are formed using microwave annealing for dopant activation..

Methods and systems for microelectronic packaging

Hybrid optical integration places very strict manufacturing tolerances and performance requirements upon the multiple elements to exploit passive alignment techniques as well as having additional processing requirements. Alternatively, active alignment and soldering/fixing where feasible is also complex and time consuming with 3, 4, or 6-axis control of each element.

Optical-scanning-type object detection device

Provided is an object detection device which unlikely causes vignetting of a beam reflected from a mirror surface during rotation, and fully ensures object detection performance a light projecting system and a light receiving system are disposed so that a larger one of the area of a region on a mirror surface occupied by a beam emitted from a semiconductor laser and the area of a region on the mirror surface occupied by a beam incident on a photodiode has a longer movement length on the mirror surface during rotation than a smaller one.. .

Pump and probe type second harmonic generation metrology

Various approaches to can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ second harmonic generation and in some cases may utilize pump and probe radiation.

Solid state sensor for metal ion detection and trapping in solution

A device, apparatus and method for trapping metal ions and detecting metal ion contamination in a solution provide a semiconductor device formed on a semiconductor substrate and including an n-well formed over a p-type substrate and at least a contact portion of the n-well in electrical contact with the solution. When the semiconductor device is optically illuminated, a p/n junction is formed as a result of photovoltaic phenomena.

Process for manufacturing a mems pressure sensor, and corresponding mems pressure sensor

A process for manufacturing a mems pressure sensor having a micromechanical structure envisages: providing a wafer having a substrate of semiconductor material and a top surface; forming a buried cavity entirely contained within the substrate and separated from the top surface by a membrane suspended above the buried cavity; forming a fluidic-communication access for fluidic communication of the membrane with an external environment, set at a pressure the value of which has to be determined; forming, suspended above the membrane, a plate made of polysilicon, separated from the membrane by an empty space; and forming electrical-contact elements for electrical connection of the membrane and of the plate, which are designed to form the plates of a sensing capacitor, the value of capacitance of which is indicative of the value of pressure to be detected. A corresponding mems pressure sensor having the micromechanical structure is moreover described..

Transmission small-angle x-ray scattering metrology system

Methods and systems for characterizing dimensions and material properties of semiconductor devices by transmission small angle x-ray scatterometry (tsaxs) systems having relatively small tool footprint are described herein. The methods and systems described herein enable q space resolution adequate for metrology of semiconductor structures with reduced optical path length.

Laser scanning semiconductor device staircase step width measurement

A method of determining a width of a step in a stepped surface of a microstructure includes scanning an incident measurement laser beam across the stepped surface of the microstructure, detecting a reflected laser beam from the microstructure, and determining a width of the step in the stepped surface by at least one of detecting a consecutive pair of phase inflection points or consecutive pair of shifts in the detected reflected laser beam intensity.. .

Self-limited organic molecular beam epitaxy for precisely growing ultrathin c8-btbt, ptcda and their heterojunctions on surface

Disclosed is a method for depositing ultrathin c8-btbt, ptcda and their heterojunctions with precise control of the molecular layers. In the method, source of the organic semiconductor material to grow (c8-btbt or ptcda) and a support are spaced from each other in a vacuum chamber with a temperature gradient, and ultrathin organic semiconductor crystal can be deposited on the support in crystalline form and with precisely controlled molecular layers.

Plating power supply with headroom control and ethercat interface

A system for controlling the operation of apparatus for electroplating semiconductor substrates includes operating in a high mode of operation in which an off-the-shelf power supply provides current or voltage that is directly used to produce the channel control signal and in a low mode of operation in which the off-the-shelf power supply biases a circuit that provides a current or voltage to produce the channel control signal.. .

Microelectronic substrate electro processing system

In a processing system for electroplating semiconductor wafers and similar substrates, the contact ring of the electroplating processor is removed from the rotor of the processor and replaced with a previously deplated contact ring. This allows the contact ring to be deplated in ring service module of the system, while the processor continues to operate.

Graphite susceptor

Embodiments described herein include a susceptor for semiconductor processing including an oriented graphite plate that may have a thickness of at least 1 mm. The susceptor may have a support member, and the oriented graphite plate may be disposed on the support member.

Tritiated nitroxides and uses thereof

Long-term and high-density energy sources are described that utilize radioisotope batteries that provide a tritium (3h)-based direct energy conversion system. The beta radiation source is a nitroxide compound with a synthetic yield near 100%.

Semiconductor nanocrystal film

A semiconductor nanocrystal film according to an exemplary embodiment of the present invention includes a glass cloth including a glass fiber having a composition of e glass, s glass, t glass, or e-cr glass, a polymer matrix impregnated in the glass cloth, and a semiconductor nanocrystal dispersed in the polymer matrix, and thus may exhibit uniform light emitting distribution, a low coefficient of thermal expansion, and excellent mechanical strength.. .

Microelectromechanical device, manufacturing a microelectromechanical device, and manufacturing a system on chip using a cmos process

A microelectromechanical systems (mems) device is provided and includes a bulk semiconductor substrate, a cavity formed in the bulk semiconductor substrate, a movably suspended mass, a cap structure and a capacitive structure is shown. The movably suspended mass is defined in the bulk semiconductor substrate by one or more trenches extending from a main surface area of the bulk semiconductor substrate to the cavity.

Semiconductor wafer processing method

Disclosed is a semiconductor wafer processing method wherein, a thin disc-like wafer is manufactured by slicing a semiconductor single crystal ingot (slicing step), a planarized coating layer is formed by applying a curable material to the whole first surface of the wafer (coating layer forming step), and the coating layer is cured (coating layer curing step). A wafer second surface on the reverse side of the first surface is flatly grind by means of a grinding apparatus, the coating layer is removed from the first surface of the wafer.

Light-based spectroscopy with improved signal-to-noise ratio

A measurement system includes a light source having semiconductor sources, a multiplexer, and one or more fused silica fibers configured to form an output optical beam having one or more optical wavelengths modulated at a modulation frequency. A light beam set-up includes a monochromator forming a filtered optical beam.

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Integrated circuit with laminated magnetic core inductor and magnetic flux closure layer

A structure comprises a semiconductor integrated circuit, an inductor, and a magnetic flux closure layer. The inductor is integrated into a multilevel wiring network in the semiconductor integrated circuit.

Integrated circuit with laminated magnetic core inductor including a ferromagnetic alloy

A structure includes a semiconductor integrated circuit comprising a multilevel wiring network and an inductor integrated into the multilevel wiring network. The inductor includes a planar laminated magnetic core and a conductive winding that turns around in a generally spiral manner on the outside of the planar laminated magnetic core.

Laminated magnetic core inductor with insulating and interface layers

An inductor includes a planar laminated magnetic core and a conductive winding. The planar magnetic core includes an alternating sequence of a magnetic layer and a non-magnetic layer.

Stretchable/conformable electronic and optoelectronic circuits, methods, and applications

A fabrication method for stretchable/conformable electronic and optoelectronic circuits and the resulting circuits. The method may utilize a variety of electronic materials including, but not limited to silicon, gaas, insb, pbse, cdte, organic semiconductors, metal oxide semiconductors and related alloys or hybrid combinations of the aforementioned materials.

Semiconductor structures and methods

A method includes attaching a substrate to a carrier, aligning external connectors on a first surface of a first semiconductor package to first conductive pads on a first surface of the substrate facing away from the carrier, and performing a reflow process, where a difference in coefficients of thermal expansion (ctes) between the substrate and the carrier causes a first shape for the first surface of the substrate during the reflow process, where differences among ctes of materials of the first semiconductor package causes a second shape for the first surface of the first semiconductor package during the reflow process, and wherein the first shape substantially matches the second shape. The method further includes removing the carrier from the substrate after the reflow process..

Electronic device

An electronic device according to one embodiment includes a wiring substrate, the wiring substrate having a first wiring connected to a first external terminal and a second wiring connected to a second external terminal and extending along the first wiring. Additionally, the above electronic device has a semiconductor device mounted on the above wiring substrate and electrically connected to each of the first and second wirings.

Acoustic transducer and microphone using the acoustic transducer

Provided is an acoustic transducer including: a semiconductor substrate; a vibrating membrane, provided above the semiconductor substrate, including a vibrating electrode; and a fixed membrane, provided above the semiconductor substrate, including a fixed electrode, the acoustic transducer detecting a sound wave according to changes in capacitances between the vibrating electrode and the fixed electrode, converting the sound wave into electrical signals, and outputting the electrical signals. At least one of the vibrating electrode and the fixed electrode is divided into a plurality of divided electrodes, and the plurality of divided electrodes outputting the electrical signals..

Solid-state imaging device and imaging system

A solid-state imaging device including a plurality of pixels including a photoelectric conversion portion, a charge holding portion accumulating a signal charge transferred from the photoelectric conversion portion, and a floating diffusion region to which the signal charge of the charge holding portion is transferred, wherein the photoelectric conversion portion includes a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type formed under the first semiconductor region, the charge holding portion includes a third semiconductor region of the first conductivity type, and a fourth semiconductor region of the second conductivity type formed under the third semiconductor region, and a p-n junction between the third semiconductor region and the fourth semiconductor region is positioned deeper than a p-n junction between the first semiconductor region and the second semiconductor region.. .

Solid-state imaging device and driving solid-state imaging device

In the imaging device, a photoelectric conversion unit generates charge corresponding to an exposure amount in a predetermined exposure period. A generated charge retaining unit is formed to have a predetermined impurity concentration in a semiconductor substrate and retains the charge.

Semiconductor integrated circuit

An object of the present invention is to reduce burden on a program for changing an operation mode of an internal circuit in accordance with an internal clock frequency without mounting a large-scale circuit in an lsi in which setting of the frequency of an internal clock can be dynamically changed. In an lsi including an internal clock generation circuit generating an internal clock from a clock source in accordance with a parameter supplied, a register storing frequency information of the clock source, a register storing the parameter, and an internal circuit having a plurality of operation modes, a table circuit controlling the operation mode of the internal circuit in association with the frequency information and the parameter supplied from the registers is provided..

Amplifier and semiconductor apparatus using the same

An amplifier may include a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal, a plurality of current sinks coupled between a ground terminal and the differential pair circuit, and a feedback circuit configured to sense a level of the output signal and generate a feedback signal. At least one of the plurality of current sinks is controlled according to the feedback signal..

High-frequency semiconductor amplifier circuit

According to an embodiment, a high-frequency semiconductor amplifier circuit includes an input terminal and an output terminal. A gate of a first transistor is connected to the input terminal.

Integrated circuit-based wireless charging system and method

An integrated circuit for wireless power transfer is disclosed. The integrated circuit may comprise a boost controller configured to pump up a system input to a dc input, an oscillator configured to generate a frequency signal, a mos (metal-oxide-semiconductor) driver coupled to the oscillator, and a power switch coupled to the mos driver.

Multi-wavelength semiconductor comb lasers

Examples disclosed herein relate to multi-wavelength semiconductor comb lasers. In some examples disclosed herein, a multi-wavelength semiconductor comb laser may include a waveguide included in an upper silicon layer of a silicon-on-insulator (soi) substrate.

Optical module

An optical module includes a semiconductor laser with an active layer disproportionately positioned closer to the first surface. The semiconductor laser includes a reflector for reflecting the light outgoing from the active layer in a direction along the first surface toward another direction.

Organic thin film transistor and manufacturing method thereof

An organic thin film transistor includes a substrate, a hydrophobic layer, an oxide layer, a hydrophilic layer, a semiconductor layer, and a source/drain layer. The hydrophobic layer covers a surface of the substrate.

Methods for fabricating artificial neural networks (ann) based on doped semiconductor elements

A method of forming semiconductor elements in an artificial neural network, the method including forming a substrate including an oxide layer, forming a silicon layer on the oxide layer, depositing a thin film dopant layer on the silicon layer, and controlling a concentration of the dopant in the thin film dopant layer.. .

Light emitting device

A light emitting device includes a light emitting element and a mounting substrate on which the light emitting element is mounted such that the mounting substrate faces an upper side of the light emitting element. The light emitting element includes a substrate, first and second light emitting cells each including a semiconductor layered structure that includes an n-side semiconductor layer and a p-side semiconductor layer in order from a substrate side, a first insulating layer, wiring electrodes, and a second insulating layer.

Light-emitting diode and manufacturing same

A light-emitting diode includes, a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer. The light-emitting diode also includes a transparent conductive layer including a first transparent conductive layer disposed on the second semiconductor layer and a second transparent conductive layer disposed on the first transparent conductive layer.

Light-emitting device

Disclosed is a light-emitting device comprising a light-emitting stack having a length, a width, a first semiconductor layer, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are stacked in a stacking direction. A first electrode is coupled to the first semiconductor layer and extended in a direction parallel to the stacking direction and a second electrode is coupled to the second semiconductor layer and extended in a direction parallel to the stacking direction.

Light emitting diode for surface mount technology, manufacturing the same, and manufacturing light emitting diode module

A light emitting diode including a first conductive type semiconductor layer; a mesa disposed on the first conductive type semiconductor layer and including an active layer and a second conductive type semiconductor layer; an electrode disposed on the mesa and configured to be in ohmic-contact with the corresponding second conductive type semiconductor layer of the mesa, a current spreading layer disposed on the mesa and the electrode and including a first portion, a second portion, and a third portion configured to be in ohmic-contact with a first end portion, a second end portion, and a middle portion of the first conductive type semiconductor layer, respectively, an insulation layer disposed on the mesa and the first conductive type semiconductor layer and having a first region having a thickness that varies along a longitudinal direction of the first semiconductor layer.. .

Control of p-contact resistance in a semiconductor light emitting device

A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A surface of the p-type region perpendicular to a growth direction of the semiconductor structure includes a first portion and a second portion.

Method for producing an optoelectronic semiconductor component, and optoelectronic semiconductor component

A method is specified for producing an optoelectronic semiconductor component, comprising the following steps: a) providing a structured semiconductor layer sequence (21, 22, 23) having—a first semiconductor layer (21) with a base region (21c), at least one well (211), and a first cover region (21a) in the region of the well (211) facing away from the base surface (21c),—an active layer (23), and—a second semiconductor layer (22) on a side of the active layer (23) facing away from the first semiconductor layer (21), wherein—the active layer (23) and the second semiconductor layer (22) are structured jointly in a plurality of regions (221, 231) and each region (221, 231) forms, together with the first semiconductor layer (21), an emission region (3), b) simultaneous application of a first contact layer (41) on the first cover surface (21a) and a second contact layer (42) on a second cover surface (3a) of the emission regions (3) facing away from the first semiconductor layer (21) in such a way that—the first contact layer (41) and the second contact layer (42) are electrically separated from each other, and—the first contact layer (41) and the second contact layer (42) run parallel to each other.. .

Insulation paste, producing insulation paste, manufacturing solar cell device, and solar cell device

An insulation paste for forming a protective layer of a solar cell device includes: a siloxane resin; an organic solvent; and multiple fillers each having a surface covered with an organic coating containing at least one material different from a material of the siloxane resin. A method for producing the insulation paste includes: preparing the multiple fillers; and mixing together a precursor of the siloxane resin, water, a catalyst, an organic solvent, and the multiple fillers.

Back-contact thin film semiconductor device structures and methods for their production

Systems and methods taught herein provide thin film semiconductor devices such as thin film photovoltaic devices having via holes that enable electrical connection with a bottom surface of a topside contact of the thin film semiconductor device via the back side of the device (e.g., during mounting of the device). In some embodiments, the via holes are electrically insulated..

Photoelectric conversion device

A photoelectric conversion device includes a quantum dot layer formed by integrating a plurality of quantum dots on a main surface of a semiconductor substrate. The quantum dot layer contains not less than two types of organic molecules having different carbon numbers, among the quantum dots.

Photoelectric conversion device and manufacturing same

A photoelectric conversion device includes, on one principal surface of a semiconductor substrate, a first conductivity-type region, a second conductivity-type region, and a boundary region which is in contact with each of the first conductivity-type region and the second conductivity-type region to separate these two regions. A first conductivity-type semiconductor layer is disposed over the entire first conductivity-type region and extending over the boundary region.

Semiconductor device and manufacturing the same

In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing in or ga, the oxide semiconductor film has an amorphous structure or a microcrystalline structure, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.. .

Semiconductor device and a fabricating the same

A semiconductor device includes a semiconductor substrate, a tunnel dielectric disposed on the semiconductor substrate, a floating gate disposed on the tunnel dielectric, a control gate disposed on the floating gate, and an insulation layer disposed between the floating gate and the control gate. The semiconductor device further includes a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, and the spacer overlaps portions of the top surface of the floating gate..

Formation method and structure of semiconductor device with source/drain structures

Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate.

Method and structure of improving contact resistance for passive and long channel devices

A semiconductor device includes a gate arranged on a substrate; a source/drain formed on the substrate adjacent to the gate; a source/drain contact extending from the source/drain and through an interlayer dielectric (ild) over the source/drain, a portion of the source/drain positioned adjacent to the source/drain contact; and a silicide positioned along a sidewall of the source/drain contact between the portion of the source/drain and the source/drain contact, and along an endwall of the source/drain contact between the source/drain contact and the substrate.. .

Integrated circuit devices and methods of manufacturing the same

An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other.

Vertical transistor having dual work function materials and fabricating thereof

A semiconductor device includes a substrate, a semiconductor column vertically disposed on the substrate, a first contact material layer on the substrate and in contact with a lower portion of the semiconductor column, a first insulating material layer on the first contact material layer and having an upper surface lower than an upper surface of the semiconductor column, a gate dielectric material layer on the first insulating material layer and on a portion of sidewalls of the semiconductor column while exposing an upper portion of the semiconductor column, and a gate stack structure on the gate dielectric material layer and surrounding a portion of the gate dielectric material layer on the sidewalls of the semiconductor column. The gate stack structure includes from inside to outside a p-type work function layer, an n-type work function layer, and a gate..

Silicon carbide semiconductor device and manufacturing silicon carbide semiconductor device

A trench gate structure vertical mosfet includes a silicon carbide substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, a trench, a gate electrode, an interlayer insulating film, a barrier layer, a contact electrode, a first electrode, and a second electrode. The barrier layer includes a layer made of tin, and the thickness of the tin layer is 10 to 80 nm.

Semiconductor device and display device including the same

A first transistor and a second transistor are stacked. The first transistor and the second transistor have a gate electrode in common.

Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a finfet device

One illustrative method disclosed includes, among other things, forming a gate structure around a fin and above a layer of insulating material, forming a gate spacer adjacent the gate structure and a fin spacer positioned adjacent the fin above the insulating material, the fin spacer leaving an upper surface of the fin exposed, and performing at least one etching process to remove at least a portion of the fin positioned between the fin spacer, the fin having a recessed upper surface that at least partially defines a fin recess positioned between the fin spacer. In this example, the method further includes forming an epi semiconductor material on the fin recess and removing the fin spacer from adjacent the epi semiconductor material while leaving a portion of the gate spacer in position adjacent the gate structure..

High-electron-mobility transistor and manufacturing method thereof

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate.

Method of forming gate-all-around structures

A manufacturing method for gate-all-around structures in semiconductor ic manufacturing field includes forming a buried gate layer on the semiconductor substrate, forming an epitaxial layer in non-buried-gate-layer regions and planarizing the epitaxial layer so that the top surface of the epitaxial layer is at the same level with the top surface of the buried gate layer; forming a fin structure on the buried gate layer; forming a gate structure traversing and surrounding the fin structure. Since the gate structure wraps around four sides of the fin to effectively control the channel, the channel width is increased compared with the double-gate or triple gate structure, thereby increasing the effective area of the channel.

3d semiconductor device

A 3d semiconductor device, the device including: a first level including a plurality of first single crystal transistors, contacts, and a first metal layer, where a portion of the first single crystal transistors are interconnected, where the interconnected includes the first metal layer and the contacts, and where the portion of the first single crystal transistors are interconnected forms memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a fourth level overlaying the third level, the fourth level including a plurality of fourth transistors; and a second metal layer overlaying the fourth level, where the plurality of second transistors are aligned to the plurality of first transistors with a less than 40 nm alignment error.. .

Transistor having a gate with a variable work function and manufacturing the same

The present disclosure provides a method for manufacturing a transistor having a gate with a variable work function, comprising: providing a semiconductor substrate; forming a dummy gate stack on the semiconductor substrate and performing ion implantation on an exposed area of the semiconductor substrate at both sides of the dummy gate stack to form source/drain regions; removing the dummy gate and annealing the source/drain regions; providing an atomic layer deposition reaction device; introducing a precursor source reactant into the atomic layer deposition reaction device; and controlling an environmental factor for the atomic layer deposition device to grow a work function metal layer. The present disclosure also provides a transistor having a gate with a variable work function.

Vertical field effect transistor with reduced parasitic capacitance

Embodiments are directed to a method and resulting structures for a semiconductor device having reduced parasitic capacitance. A semiconductor fin is formed on a substrate.

Semiconductor device and fabrication method thereof

Semiconductor device and fabrication method are provided. The method includes: providing a base substrate; forming gate structures on the base substrate; forming source/drain doped regions in the base substrate on sides of each gate structure, where the source/drain doped regions have recessed top surfaces and are doped with source/drain ions; and doping into the recessed top surfaces of the source/drain doped regions with contact ions to form contact doped regions in top portions of the source/drain doped regions, where the contact ions have a conductivity type same as the source/drain ions..

Epitaxial substrate for semiconductor elements, semiconductor element, and manufacturing epitaxial substrates for semiconductor elements

Provided is an epitaxial substrate for semiconductor elements which suppresses leakage current and has high breakdown voltage. An epitaxial substrate for semiconductor elements includes: a semi-insulating free-standing substrate formed of gan being doped with zn; a buffer layer formed of group 13 nitride to be adjacent to the free-standing substrate; a channel layer formed of group 13 nitride to be adjacent to the buffer layer; and a barrier layer formed of group 13 nitride on an opposite side of the buffer layer with the channel layer therebetween, wherein part of a first region consisting of the free-standing substrate and the buffer layer is a second region containing si at a concentration of 1×1017 cm−3 or more, and a minimum value of a concentration of zn in the second region is 1×1017 cm−3..

Polarization-doped enhancement mode hemt

The present invention belongs to the field of semiconductor technology and relates to a polarization-doped enhancement mode hemt device. The technical solution of the present invention grows the first barrier layer and the second barrier layer that contain gradient al composition sequentially on the buffer layer.

Field-effect semiconductor device and a manufacturing method therefor

A semiconductor device includes a semiconductor body having first and second opposite sides, a drift region, a body layer at the second side, and a field-stop region in ohmic connection with the body layer. A source metallization at the second side is in ohmic connection with the body layer.

Electronic device including a termination structure

An electronic device can include a termination structure that includes a substrate, a semiconductor layer, and a first trench. The substrate includes a semiconductor material of a first conductivity type.

Semiconductor device

A semiconductor device includes: a fin-type active region protruding from a substrate and extending in a first direction; at least one nano-sheet spaced apart from an upper surface of the fin-type active region and facing the upper surface of the fin-type active region, the at least one nano-sheet having a channel region; a gate extending on the fin-type active region in a second direction crossing the first direction and surrounding at least a portion of the at least one nano-sheet; a source/drain region on the fin-type active region on both sides of the at least one nano-sheet; and a source/drain protection layer on a sidewall of the at least one nano-sheet and between the source/drain region and the at least one nano-sheet.. .

Metal resistors having nitridized dielectric surface layers and nitridized metal surface layers

A semiconductor structure containing at least two metal resistor structures having different resistivities is provided and includes a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first nitridized dielectric surface layer portion having a first nitrogen content, a first metal layer portion and a first nitridized metal surface layer.

Manufacturing complementary tft device and manufacturing oled display panel

The invention provides a manufacturing method for complementary tft device. The manufacturing method for complementary tft device uses a solution method to continuously form a metal oxide semiconductor tft and an organic semiconductor tft; the metal oxide semiconductor tft and the organic semiconductor tft are electrically connected, and one of the metal oxide semiconductor tft and the organic semiconductor tft is an n-type channel tft, and the other is a p-type channel tft.

Method for fabricating an array of diodes, in particular for a non-volatile memory, and corresponding device

The array of diodes comprises a matrix plane of diodes arranged according to columns in a first direction and according to rows in a second direction orthogonal to the first direction. The said diodes comprise a cathode region of a first type of conductivity and an anode region of a second type of conductivity, the said cathode and anode regions being superposed and disposed on an insulating layer situated on top of a semiconductor substrate..

Semiconductor packaging method and semiconductor device based on molding process

The present invention provides a semiconductor packaging method and semiconductor device based on a molding process. In the packaging method, first, at least a portion of a compensation part is kept on at least a portion of a bonding region formed between a first adjoining surface of a semiconductor element and a second adjoining surface of a packaging component, to form a semi-finished product of a semiconductor device; then, during hardening of the packaging component, the compensation part is caused to undergo different degrees of deformation at different positions to compensate for a difference between a magnitude of deformation of the packaging component and a magnitude of deformation of the semiconductor element, so as to package the semiconductor element to form the semiconductor device.

Image sensor and image-capturing device

An image sensor includes: a semiconductor substrate having a light receiving unit that receives incident light passed through a microlens; and a light shielding unit that blocks a part of the light passed through the microlens and enters the semiconductor substrate. The light receiving unit receives the incident light passed through the microlens, between the microlens and the light shielding unit..

Chip-scale image sensor package and associated making

A chip-scale image sensor package includes a semiconductor substrate, a transparent substrate, a thin film, and a plurality of conductive pads. The semiconductor substrate has (i) a pixel array, and (ii) a peripheral region surrounding the pixel array.

Solid-state imaging device, manufacturing method thereof, and electronic apparatus

A solid-state imaging device having a backside illuminated structure, includes: a pixel region in which pixels each having a photoelectric conversion portion and a plurality of pixel transistors are arranged in a two-dimensional matrix; an element isolation region isolating the pixels which is provided in the pixel region and which includes a semiconductor layer provided in a trench by an epitaxial growth; and a light receiving surface at a rear surface side of a semiconductor substrate which is opposite to a multilayer wiring layer.. .

Semiconductor structure

A semiconductor structure includes a semiconductive substrate includes a first side and a second side opposite to the first side, a radiation sensing device disposed in the semiconductive substrate, an interlayer dielectric (ild) disposed over the first side of the semiconductive substrate, and a conductive pad disposed in the semiconductive substrate and the ild, wherein a thickness of the conductive pad is less than a sum of a thickness of the semiconductive substrate and a thickness of the ild.. .

Display device and manufacturing method thereof

Disclosed is a display device including a transistor showing extremely low off current. In order to reduce the off current, a semiconductor material whose band gap is greater than that of a silicon semiconductor is used for forming a transistor, and the concentration of an impurity which serves as a carrier donor of the semiconductor material is reduced.

Manufacturing semiconductor device

A substrate in which an insulating layer, a semiconductor layer and an insulating film are stacked on a semiconductor substrate and an element isolation region is embedded in a trench is prepared. After the insulating film in a bulk region is removed by dry etching and the semiconductor layer in the bulk region is removed by dry etching, the insulating layer in the bulk region is thinned by dry etching.

Semiconductor device and manufacturing the same

According to one embodiment, a semiconductor device includes a substrate, a stacked body, and a columnar portion. The stacked body, provided on the substrate, includes first conductive layers and first insulating layers provided alternately along a first direction.

Three dimensional semiconductor memory devices

A three-dimensional semiconductor memory device includes a cell string vertically extending from a top surface of a substrate and having first and second cell transistors, first and second word lines connected to gate electrodes of the first and second cell transistors respectively, a first pass transistor connecting the first word line to a row decoder, and a second pass transistor connecting the second word line to the row decoder. The first pass transistor includes a plurality of first sub-transistors connected in parallel between the first word line and the row decoder..

Semiconductor device and critical dimension defining method thereof

A semiconductor device includes a semiconductor substrate, a circuit unit and an align mark. The circuit unit is disposed on the semiconductor substrate.

Three-dimensional semiconductor device

A three-dimensional semiconductor device and a method of manufacturing the same are provided. The three-dimensional semiconductor device includes a stack structure including insulating layers and electrodes that are alternately stacked on a substrate, a horizontal semiconductor pattern between the substrate and the stack structure, vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and a common source plug at a side of the stack structure.

Memory device and fabricating the same

A memory device includes a semiconductor substrate, a first conductive layer, a plurality of second conductive layers, a plurality insulating layers, at least one contact plug and at least one dummy plug. The first conductive layer is disposed on the semiconductor substrate.

Vertical stack memory device

A vertical stack memory device includes a doped semiconductor substrate having a common source to which a source power is applied and a low band gap layer that is spaced apart from the common source, and the low band gap comprising low band gap materials. A stack gate structure has gate electrodes and insulation interlayer patterns that are alternately and vertically stacked on the substrate in a first direction.

Semiconductor structure with contact plug and fabricating the same

A semiconductor structure having a contact plug includes a substrate. A memory cell region and a peripheral circuit region are defined on the substrate.

Apparatuses containing finfets

Some embodiments include a method of forming a memory array. A wordline is formed to extend along a first direction, and along a rail of semiconductor material.

Self aligned buried power rail

The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure..

Semiconductor device having insulating layer higher than a top surface of the substrate, and reducing the difficulty of filling an insulating layer in a recess

The present invention provides a semiconductor structure including a substrate defining a memory cell region and a peripheral region, a periphery gate stacking structure located within the peripheral region, wherein the periphery gate stacking structure includes at least a first gate layer, and a second gate layer disposed on the first gate layer. The semiconductor structure further includes a cell stacking structure located within the memory cell region, the cell stacking structure having at least a first insulating layer partially disposed in the substrate, a top surface of the first insulating layer being higher than a top surface of the substrate, and the top surface of the first insulating layer and a top surface of the first gate layer being on a same level..

Semiconductor device and manufacturing the same

There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion.

Semiconductor device

A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction.

Air gap spacer for metal gates

A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure.

Finfet device

A semiconductor device includes an active region having a doped region, a first contact member on the doped region, gate structures including a first gate structure having a first gate and a second gate structure having a second gate, the first and second gate structures being adjacent to each other and on opposite sides of the first contact member, an interlayer dielectric layer on the active region and surrounding the first and second gate structures, and the first contact member, a first insulator layer on a portion of the interlayer dielectric layer, a first contact on an upper surface of the first gate and a second contact on an upper surface of the second gate, and a second insulator layer surrounding the first and second contacts each having an upper surface lower than an upper surface of the second insulator layer.. .

Semiconductor device and manufacturing method thereof

Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate.

Semiconductor devices with trench gate structures in a semiconductor body with hexagonal crystal lattice

A semiconductor device with a trench gate structure in a semiconductor body with a hexagonal crystal lattice is disclosed. In an embodiment a semiconductor device includes a semiconductor body with a hexagonal crystal lattice, wherein a mean surface plane of a first surface of the semiconductor body is tilted with respect to a <1-100> crystal direction of the hexagonal crystal lattice by an off-axis angle, a trench gate structure extending into the semiconductor body and at least two transistor mesas formed from portions of the semiconductor body and adjoining the trench gate structure, wherein sidewalls of the at least two transistor mesas are aligned with a (11-20) crystal plane and deviate from a normal to the mean surface plane by at most 5 degrees, and wherein each transistor mesa comprises a mos gate channel..

Semiconductor device

A semiconductor device is provided, in which a loss of a sensing element is small. A semiconductor device including a semiconductor substrate is provided, the semiconductor device including: an upper-surface electrode that is provided on an upper surface of the semiconductor substrate; a sensing electrode that is provided on the upper surface of the semiconductor substrate and is separated from the upper-surface electrode; a lower-surface electrode that is provided on a lower surface of the semiconductor substrate; a main transistor portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; a main diode portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; and a sense diode portion that is provided to the semiconductor substrate and is connected to the sensing electrode and the lower-surface electrode..

Semiconductor device, semiconductor device manufacturing method, and power conversion apparatus

An rc-igbt includes a first electrode disposed on a first main surface of a semiconductor substrate over a transistor region and a diode region. The semiconductor substrate includes a mos gate structure on a first main surface side in the transistor region.

Semiconductor device and manufacturing the same

A semiconductor device of an embodiment includes a conductive semiconductor substrate, an insulating film formed on the semiconductor substrate, an overvoltage protection diode configured to be formed on the insulating film and to include an n-type semiconductor layer and a p-type semiconductor layer alternately arranged adjacent to each other, and an insulating film that covers the overvoltage protection diode. The concentration of the p-type impurities in the p-type semiconductor layer is lower than the concentration of the n-type impurities in the n-type semiconductor layer.

Semiconductor devices

A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors.

Semiconductor device

A semiconductor device includes semiconductor chips fixed to a board, an insulating plate having a through-hole formed therein, a first lower conductor including a lower main body formed on the lower surface of the insulating plate and soldered to any of the semiconductor chips, and a lower protrusion portion that connects with the lower main body, and extends to the outside of the insulating plate, a second lower conductor formed on a lower surface of the insulating plate and soldered to any of the semiconductor chips, an upper conductor including an upper main body formed on the upper surface of the insulating plate, and an upper protrusion portion that connects with the upper main body and extends to the outside of the insulating plate, and a connection portion provided in the through-hole and connects the upper main body and the second lower conductor.. .

Semiconductor device including vertically integrated groups of semiconductor packages

A semiconductor device is disclosed including at least first and second vertically stacked and interconnected groups of semiconductor packages. The first and second groups of semiconductor packages may differ from each other in the number of packages and functionality..

Semiconductor chip and semiconductor module including the same

The present disclosure provides a semiconductor chip. The semiconductor chip includes a switching element having a gate electrode, a first pad, and a second pad.

Semiconductor device assemblies with molded support substrates

Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly includes a support substrate formed from a molded material, a first semiconductor die at least partially embedded within the support substrate, a plurality of interconnects extending at least partially through the molded material, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate.

Method of batch transferring micro semiconductor structures

A method of batch transferring micro semiconductor structures is provided for effectively and efficiently picking up a batch of or a large amount of micro structures and transferring them to a target substrate, so it can be widely applied in transferring a lot of various micro semiconductor structures. The method includes steps of: attaching an adhesive material to a plurality of array-type micro semiconductor structures; and providing a roll-to-attach mechanism for alternately processing linear contacts between the array-type micro semiconductor structures and a target substrate.

Semiconductor device package and manufacturing the same

A surface mount structure includes a substrate, a sensor, an electrical contact and a package body. The substrate has a first surface and a second surface opposite to the first surface.

Semiconductor device and ball bonder

In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening.

Electrically conductive adhesive film and dicing die bonding film

A means that exhibits excellent heat resistance and mounting reliability when bonding a power semiconductor device on to a metal lead frame, which is also lead-free and places little burden on the environment. Specifically, an electrically conductive adhesive film, which includes metal particles, a thermosetting resin, and a compound having lewis acidity or a thermal acid generator, wherein the compound having lewis acidity or thermal acid generator is selected from: boron fluoride or a complex thereof, a protonic acid with a pka value of −0.4 or lower, or a salt or acid obtained by combining an anion that is the same as the salt thereof with hydrogen ion or any other cation.

Semiconductor device

A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening.

Terahertz detector comprised of p-n junction diode

A method of forming a semiconductor detector including: forming a p-n junction diode in an active device layer of a silicon-on-insulator (soi) substrate, the active device layer being formed on an insulator layer of the soi substrate; forming a first opening through the insulator layer to access a backside of a first doped region of the diode, the first doped region underlying a second doped region of the diode; forming a back contact on a back surface of the first doped region and electrically connecting with the first doped region; forming a conductive interconnect layer on an upper surface of the soi substrate, the interconnect layer including a first top contact providing electrical connection with the second doped region; and forming an electrode in the first opening on the backside of the detector structure, the electrode providing electrical connection with the back contact of the diode.. .

Semiconductor package structure

A semiconductor package structure includes a first redistribution layer, a second redistribution layer and an interconnecting structure. The first redistribution layer has a first surface and a second surface opposite to each other.

Dummy conductive structures for emi shielding

A semiconductor device has a first conductive layer and a second conductive layer. A first portion of the first conductive layer is aligned with a first portion of the second conductive layer.

Semiconductor device and fabrication method thereof

Semiconductor device and fabrication method are provided. The method includes: providing a base substrate with a bottom metallic layer in the base substrate and a dielectric layer on the base substrate; forming interconnect openings through the dielectric layer and exposing the bottom metallic layer, where each interconnect openings includes a contacting hole and a groove on the contacting hole; forming a first conducting layer in the contacting hole, where the first conducting layer is made of a material having a first conductivity along a direction from the bottom metallic layer to a top surface of the first conducting layer; and after forming the first conducting layer, forming a second conducting layer in the groove, where the second conducting layer is made of a material having a second conductivity along a direction parallel to the top surface of the base substrate and the first conductivity is greater than the second conductivity..

Systems and methods for interconnecting dies

Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die first die area of a first die and a second die area of a second die separate from the first die area.

Semiconductor package structure

Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, and a first re-distribution layer (rdl) wire disposed on the second surface of the molding material and electrically separated from the through-via.

Three-dimensional semiconductor memory device and fabricating the same

Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate a substrate including a peripheral circuit region and a cell array region, an electrode structure including a plurality of electrodes vertically stacked on the cell array region of the substrate, a peripheral logic circuit provided on the peripheral circuit region of the substrate, the peripheral logic circuit including a first impurity region doped with first impurities, a peripheral contact plug connected to the first impurity region, and a second impurity region between the first impurity region and the peripheral contact plug, the second impurity region being including second impurities different from the first impurities.

Nickel-silicon fuse for finfet structures

Semiconductor fuses include a semiconductor fin having a metallized region between two non-metallized regions. Conductive layers are formed on the semiconductor fin above the two non-metallized regions.

Semiconductor device

A sop has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads.

Semiconductor device, electronic circuit having the same, and semiconductor device forming method

A semiconductor device includes: a plurality of first wires formed in a first layer and indicating fixed potentials; and an inductor formed in a second layer stacked on the first layer, and wiring widths of the first wires located within a range of a formation region of the inductor in a plan view among the plurality of first wires are formed narrower than wiring widths of the first wires located outside the range of the formation region of the inductor.. .

Semiconductor device

A plurality of unit misfet elements connected in parallel with each other to make up a power misfet are formed in an ldmosfet forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power misfet is formed in a driver circuit region on the main surface of the semiconductor substrate.

Integrated circuit having heterogeneous contacts and semiconductor device including the integrated circuit

Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact..

Semiconductor package including a rewiring layer with an embedded chip

A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate.

Semiconductor device and manufacturing method thereof

A semiconductor device includes: a first semiconductor chip that includes through electrodes; a second semiconductor chip; and an interposer that has a recessed portion formed in a front surface thereof and includes a first wiring provided under a bottom surface of the recessed portion, in which the first semiconductor chip is fitted in the recessed portion with a chip top surface thereof flipped down to be electrically connected to the first wiring, the second semiconductor chip is connected on the front surface, of the interposer, around the recessed portion, and at the same time, is stacked on the first semiconductor chip in a manner to partially overlap the first semiconductor chip, and is electrically connected to the first semiconductor chip via the through electrodes.. .

Semiconductor device, manufacturing semiconductor device, and interface unit

A semiconductor device includes a base plate, a plurality of semiconductor units provided in parallel on the base plate, the plurality of semiconductor units implementing a pair, each semiconductor unit including a semiconductor chip and a rod-shaped unit-side control terminal, the unit-side control terminal being connected to the semiconductor chip, the unit-side control terminal extending opposite to the base plate; and an interface unit including a box-shaped accommodating portion, the accommodating portion being provided on the plurality of semiconductor units, the accommodating portion including an internal wiring and a rod-shaped external-connecting control terminal, the internal wiring being connected to each of the plurality of the unit-side control terminals extending from the plurality of semiconductor units, the external-connecting control terminal extending to the outside opposite to the semiconductor units, the external-connecting control terminal being connected to the internal wiring.. .

Power semiconductor device and package

A power semiconductor device and package includes multiple electrically parallel semiconductor device legs designed to share source regions and share a drain region between two devices in each leg laterally staggered from each other to distribute thermal conductivity across the shared source regions. A multitude of jigsaw patterned lateral isolation trenches are formed in a substrate of the device.

Radiation plate structure, semiconductor device, and manufacturing radiation plate structure

A radiation plate structure includes a radiation plate, and a solder resist disposed on a main surface of the radiation plate and having at least one opening. The solder resist is made of any of polyimide (pi), polyamide (pa), polypropylene (pp), polyphenylene sulfide (pps), a resin containing particulate ceramic (e.g., aluminum nitride (aln), silicon nitride (si3n4), or aluminum oxide (al2o3)), and a high-melting-point insulator made of, for instance, glass..

Power semiconductor device and manufacturing the same, and power conversion device

A power semiconductor device includes a casing, a first insulating circuit board, a second insulating circuit board, and a sealing material. The first insulating circuit board is disposed to be surrounded by the casing.

Semiconductor device and manufacturing the semiconductor device

A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nmos gate electrode formed in an nmos region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.. .

Multi-layer work function metal gates with similar gate thickness to achieve multi-vt for vfets

A method is presented for forming a device having multiple field effect transistors (fets) with each fet having a different work function. In particular, the method includes forming multiple microchips in which each fet has a different threshold voltage (vt) or work-function.

Multi-layer work function metal gates with similar gate thickness to achieve multi-vt for vfets

A method is presented for forming a device having multiple field effect transistors (fets) with each fet having a different work function. In particular, the method includes forming multiple microchips in which each fet has a different threshold voltage (vt) or work-function.

Laser processing method

Laser light is converged at an object including a semiconductor substrate formed with a plurality of functional devices on a front surface, from a back surface of the semiconductor substrate, and while a distance between the front surface and a first converging point of the laser light is maintained at a first distance, whereby a first modified region is formed along the line. The laser light is converged at the object from the back surface, and while a distance between the front surface and a second converging point is maintained at a second distance, and while the second converging point is offset with respect to a position at which the first converging point is converged, whereby a second modified region is formed along the line.

Semiconductor package having exposed redistribution layer features and related methods of packaging and testing

A method of packaging a semiconductor device having a bond pad on a surface thereof includes forming a redistribution material electrically coupled to the bond pad, forming a dielectric material over the redistribution material, and removing a first portion of the dielectric material to expose a first portion of the redistribution material. Semiconductor packages may include a redistribution layer having a first portion adjacent and coupled to a first contact of the package, a second portion exposed by a first opening in a dielectric material, and a redistribution line electrically coupled to a first bond pad, the first portion, and the second portion.

Method for manufacturing a semiconductor device

In a pattern forming method, a stacked structure, including a bottom layer, a middle layer and a first mask layer, is formed. The middle layer includes a first cap layer, an intermediate layer and a second cap layer.

A manufacturing semiconductor-on-insulator

The disclosed method is suitable for producing a semiconductor-on-insulator structure, such as a ge(si)-on-insulator structure or a ge-on-insulator structure. According to the method, a multilayer comprising alternating pairs of layers, comprising a layer of silicon and a layer of germanium optionally with silicon is deposited on a silicon substrate comprising a germanium buffer layer.

Method of filling retrograde recessed features with no voids

A method is described for void-free material filling of fine recessed features found in semiconductor devices. According to one embodiment, the method includes providing a patterned substrate containing a recessed feature having an opening, a sidewall and a bottom, the sidewall including an area of retrograde profile relative to a direction extending from a top of the recessed feature to the bottom of the recessed feature, coating the substrate with a metal-containing catalyst layer, deactivating a portion of the metal-containing catalyst layer that is near the opening of the recessed feature by exposure to a halogen-containing gas, and selectively depositing a material on the metal-containing catalyst layer in the recessed feature that has not been deactivated by the halogen-containing gas.

Semiconductor structure and fabrication method thereof

Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate; forming a dielectric layer having an opening on the base substrate; forming a ruthenium (ru)-containing layer on side surfaces and a bottom of the opening and on a top surface of the dielectric layer; forming a copper (cu) containing layer to fill the opening and cover the ruthenium (ru)-containing layer; performing a first chemical mechanical polishing (cmp) step to remove a first partial thickness of the copper (cu)-containing layer; performing a second cmp step using a polishing slurry containing a cu-corrosion-inhibitor to remove a second partial thickness of the copper (cu)-containing layer above the ruthenium (ru)-containing layer; and performing a third cmp step using a polishing slurry containing a cu-corrosion-inhibitor to remove a third partial thickness of the copper (cu)-containing layer above the dielectric layer..

Electrostatic chuck mechanism and semiconductor processing device having the same

An electrostatic chuck mechanism and a semiconductor processing device having the same are provided. The electrostatic chuck mechanism includes a base, an edge assembly, a main electrostatic heating layer, and an edge electrostatic heating layer.

Semiconductor manufacturing apparatus, failure prediction semiconductor manufacturing apparatus, and failure prediction program for semiconductor manufacturing apparatus

A semiconductor manufacturing apparatus including: a first device; one or more sensors; a first calculation circuit that calculates one or more feature quantities of the first device from the detected physical quantities; and a failure prediction circuit that compares the one or more feature quantities with a plurality of pieces of model data of a temporal change in one or more feature quantities until the first device fails, decides a piece of model data with the minimum difference from the calculated one or more feature quantities among the plurality of pieces of model data, calculates predicted failure time from a difference between a failure point in time and a point in time at which a difference from the calculated one or more feature quantities is the minimum in the piece of model data.. .

Semiconductor processing device equipped with process chamber

A semiconductor processing device according to the present invention includes a process chamber having an inner space in which plasma is generated and a chuck unit disposed in the inner space and supporting a substrate processed by the plasma. The process chamber includes a first chamber portion and a second chamber portion that are opened from each other, and when the first chamber portion and the second chamber portion are closed together, the process chamber is provided with the inner space in which the plasma is generated.

Semiconductor processing device

A semiconductor processing device is provided. The device includes a reaction chamber, a first gas inlet mechanism, and a second gas inlet mechanism that includes a gas inlet, a uniform-flow chamber, at least one gas outlet, and at least one switch element.

Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill

Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies.

Method for anisotropic dry etching of titanium-containing films

Methods for anisotropic dry etching of titanium-containing films used in semiconductor manufacturing have been disclosed in various embodiments. According to one embodiment, the method includes providing a substrate having a titanium-containing film thereon, and etching the titanium-containing film by a) exposing the substrate to a chlorine-containing gas to form a chlorinated layer on the substrate, b) exposing the substrate to a plasma-excited inert gas to remove the chlorinated layer, and c) repeating the exposing steps at least once..

Vertical transistor having a silicided bottom and fabricating thereof

A method of manufacturing a semiconductor device includes providing a substrate structure including a substrate and a semiconductor column vertically protruding from the substrate, sequentially forming a first protective layer and a second protective layer on the substrate;, etching a portion of the second protective layer to expose a portion of the first protective layer on the substrate and a portion of the first protective layer on an upper surface of the semiconductor column, removing the exposed portion of the first protective layer on the substrate to expose a lower portion of the semiconductor column, removing a remaining portion of the second protective layer, and forming a first contact material layer on the substrate and in contact with the lower portion of the semiconductor column. The first contact material layer in contact with the lower portion of the semiconductor column does not increase the source series resistance..

Wiring board, tft substrate, manufacturing wiring board, and manufacturing tft substrate

There is provided a tft substrate that prevents corrosion of a gate electrode and a method for manufacturing the tft substrate. The tft substrate comprises a substrate; a gate comprising a gate electrode and a gate wiring, the gate comprising copper and formed on one surface of the substrate; a protection film to cover the gate; an insulation film formed on the protection film; a semiconductor film formed on the insulation film; and a source and a drain formed on the semiconductor film and facing each other with a space therebetween above the gate electrode, wherein the protection film covers entire exposed surface of the gate..

Sidewall spacer with controlled geometry

Embodiments herein describe techniques for forming sidewalls on vertical structures on a semiconductor substrate. In one embodiment, the semiconductor substrate includes a first layer (e.g., a conductive layer such as an electrode) on which a second layer (e.g., an insulator) is disposed.

Semiconductor on insulator substrate

Various semiconductor wafers and their methods of fabrication are disclosed. One exemplary process comprises, forming a layer consisting essentially of aluminum nitride on a first wafer.

Process for obtaining semiconductor nanodevices with patterned metal-oxide thin films deposited onto a substrate, and semiconductor nanodevices thereof

Processes for obtaining a semiconductor nanodevice comprising a substrate, onto which patterned metal-oxide thin films having semiconductor properties are deposited, are provided, as well as semiconductor devices comprising them. The present invention belongs to the field of semiconductor nanodevices..

Surface modification to improve amorphous silicon gapfill

Methods for gapfilling semiconductor device features, such as high aspect ratio trenches, with amorphous silicon (a-si) film that involves pretreating the surface of the substrate to modify the underlying hydroxy-terminated silicon (si—oh) or hydrogen-terminated silicon (si—h) surface to oxynitride-terminated silicon (si—on) or nitride-terminated silicon (si—n) and enhance the subsequent a-si deposition are provided. First, a substrate having features formed in a first surface of the substrate is provided.

Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer

A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures.

Semiconductor integrated circuit device including test pads

A semiconductor integrated circuit device may include a plurality of semiconductor chips, a scribe lane, connecting wiring, and a selection circuit. Each of the semiconductor chips may include a peripheral circuit.

Semiconductor device

A semiconductor device includes a memory circuit, a first fifo, a second fifo and an input/output circuit. The memory circuit outputs data.

Reduced voltage nonvolatile flash memory

Systems include a first semiconductor die comprising a charge pump to generate power supply signals, a second semiconductor die comprising a memory array and programming circuitry, and a bus connected to the first and second semiconductor dies to carry the power supply signals to the programming circuitry. The programming circuitry is adapted to program memory cells of the memory array to respective threshold voltages that are each less than or equal to the first voltage..

Semiconductor memory device and operating the same

Provided herein may be a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to apply an erase voltage to a source line and a plurality of select lines of a selected memory block among the plurality of memory blocks during an erase operation; and a control logic configured to control the peripheral circuit to form a trap in an area below at least one of a plurality of source select transistors included in the selected memory block, before the erase voltage is applied to the selected memory block..

Semiconductor device

A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit.

Storage device and operating the same

Provided herein may be a storage device having disturb characteristics and a method of operating the storage device. The storage device may include one or more semiconductor memory devices, each including a plurality of memory cells, and a memory controller configured to set levels of pass voltages of the one or more semiconductor memory devices depending on program speeds of the plurality of memory cells..

Semiconductor memory device

A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.. .

Semiconductor device and system

A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal.

Semiconductor device and operation

A semiconductor device includes a clock shifting circuit suitable for shifting a write pulse which is synchronized with a clock, in response to write latency signals, and generating shifting pulses and a mask write read signal; and a flag generation circuit suitable for generating a mask write flag by latching a mask write command or outputting the mask write command as the mask write flag, in response to the shifting pulses.. .

Light scanning device and image forming apparatus with the same

A light scanning device includes: a first semiconductor laser 44a that emits a light beam l1; a polygonal mirror 42 that deflects the light beam l1; a reflective mirror 64a that reflects the light beam l1 deflected by the polygonal mirror 42 and causes the light beam l1 to enter a photosensitive drum 13; and a bd sensor 72 that detects the light beam l1 deflected by the polygonal mirror 42. The light scanning device scans the photosensitive drum 13 with the light beam l1 and set scanning timing of the photosensitive drum 13 using the light beam l1 based on detection timing of the light beam l1 using the bd sensor 72.

Method for simulating characteristics of semiconductor device

Disclosed is a method for simulating characteristics of a semiconductor device. An overlap matrix and a hamiltonian representing atomic interaction energy information of a target semiconductor device are extracted by using a density functional theory (dft), and bloch states for corresponding energies are calculated based on the hamiltonian, the overlap matrix, and energy-k relation within an effective energy region.

Semiconductor device

An address processing circuit may be provided. The address processing circuit may include an address latch control circuit configured to generate a plurality of latch control signals for separately inputting/outputting a normal operation-related address signal or a data error correction operation-related address signal based on a plurality of internal command signals pertaining to a normal operation and an error correction operation.

Semiconductor device

A semiconductor device containing a cpu capable of receiving an interrupt request signal and a task control circuit is provided. The semiconductor device includes a cpu (processor), a save circuit, and a task control circuit.

Abnormality detection system, semiconductor device manufacturing system and semiconductor device manufacturing method

To provide an abnormality detection system capable of reducing work load of an engineer. An algorithm storage unit stores therein a detection algorithm corresponding to identification information of a detection target.

Substrate loading in microlithography

Methods, systems, and apparatus for the loading and unloading of substrates, such as semiconductor wafers, involving microlithography and similar nano-fabrication techniques. The system includes two or more pedestals; a substrate chuck including two or more channels; a turntable having a top surface and a first end positioned opposite a second end, each of the first and second ends including a respective opening, each opening including two or more cutouts and two or more tabs, the turntable rotatable between first and second positions and an actuator system to adjust distances between the turntable and the substrate chuck and between the turntable and the pedestals..

Method for forming semiconductor structure using modified resist layer

Methods for forming a semiconductor structure are provided. The method for forming a semiconductor structure includes forming a material layer over a substrate and forming a resist layer over the material layer.

Projective mems device for a picoprojector of the flying spot type and related manufacturing method

A projective mems device, including: a fixed supporting structure made at least in part of semiconductor material; and a number of projective modules. Each projective module includes an optical source, fixed to the fixed supporting structure, and a microelectromechanical actuator, which includes a mobile structure and varies the position of the mobile structure with respect to the fixed supporting structure.

Method and system for grating couplers incorporating perturbed waveguides

Methods and systems for grating couplers incorporating perturbed waveguides are disclosed and may include in a semiconductor photonics die, communicating optical signals into and/or out of the die utilizing a grating coupler on the die, where the grating coupler comprises perturbed waveguides. The perturbed waveguides may include rows of continuous waveguides with scatterers extending throughout a length of said perturbed waveguides a variable width along their length.

Wide color-gamut vehicle infotainment display system

The various embodiments set forth a display device that includes a liquid crystal module, a nano-particle semiconductor material, and a light source that includes a blue light-emitting diode configured to generate a blue output light. The nano-particle semiconductor material is configured to receive the blue output light, convert a first portion of the blue output light to a green light emission, convert a second portion of the blue output light to a red light emission, and transmit a remainder portion of the blue output light.

Solid-state imaging element and electronic device

The present disclosure relates to a solid-state imaging element and an electronic device capable of effectively inhibiting occurrence of reflection and diffraction of light on a light incident surface. A fine uneven structure including a recess and a protrusion is formed with a predetermined pitch on a light incident surface of a semiconductor layer in which photoelectric conversion sections are formed for a plurality of pixels; and an antireflective film is laminated on the fine uneven structure, the anti reflective film being formed with a film thickness different for each color of light received by each of the pixels.

Testing of semiconductor devices and devices, and designs thereof

In accordance with an embodiment of the present invention, a method of testing a plurality of semiconductor devices includes applying a stress voltage having a peak voltage on a shield line disposed over a substrate. The substrate has functional circuitry of a semiconductor device.

Charge decay measurement systems and methods

Various approaches to can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ second harmonic generation and in some cases may utilize pump and probe radiation.

Method of manufacturing semiconductor device

Electrical properties of a semiconductor device are reproducibly and stably measured in a testing step of the semiconductor device. A probe pin includes a first plunger, a second plunger, a cleaning shaft, a first coil spring, and a second coil spring.

Device and detection of analytes

A detection device and associated systems and methods for detecting analytes from a multiplex reaction are described. In particular, a device for conducting at least one detection reaction using a modified elisa method including a surface with a detection region and a reference region, a detection sensor, and a light source.

Semiconductor wafer evaluation method and semiconductor wafer

A method of evaluating a semiconductor wafer, which has a polished surface, by using a laser surface-inspection device including incident and light-receiving systems, includes evaluating the semiconductor wafer by detecting, as a light point defect, an abnormality of a process-induced defect and a surface-adhered foreign matter present on the polished surface of the semiconductor wafer, on the basis of measurement result obtained by directing incident light to the polished surface of the semiconductor wafer from one incident system and receiving, with a first light-receiving system, radiation light which has been radiated by the incident light being reflected or scattered by the polished surface, measurement result obtained by receiving the radiation light with a second light-receiving system, and measurement result obtained by receiving the radiation light with a third light-receiving system, and at least one of a light-receiving angle and polarization selectivity differs among the first, second and third light-receiving systems.. .

System for measuring the quantity of semiconductor nanocrystals present in a fluid

The present invention concerns a system for measuring the quantity of fluorescent semiconductor nanocrystals present in a fluid. The system in accordance with the invention comprises a fluid circulation device (1), a light source (2) and a fluorescence detector (3) for the semiconductor nanocrystals (4)..

Overlapping pattern projector

An optoelectronic device includes a semiconductor substrate, an array of optical emitters arranged on the substrate in a two-dimensional pattern, a projection lens and a diffractive optical element (doe). The projection lens is mounted on the semiconductor substrate and is configured to collect and focus light emitted by the optical emitters so as to project optical beams containing a light pattern corresponding to the two-dimensional pattern of the optical emitters on the substrate.

Heat treating furnace

A heat treating furnace of the type used in semiconductor manufacturing having a housing with a tubular and cylindrical inner layer constructed of ceramic fiber. Electrical heating elements are supported by the inner layer while a microporous silica layer surrounds and is in contact with the ceramic fiber layer.

Light module for a motor vehicle including a semiconductor light source

A light module including a semiconductor light source, an optical reflector that is positioned with respect to the light source, and a reference surface, belonging to a heat sink radiator, on which the light source and the optical reflector are fastened, wherein the light source is supported by a mount that is fastened on the reference surface. The light module includes means for adjusting the position of the mount with respect to the reference surface and means for fastening the mount, in the adjusted position, on the reference surface..

Light emitter, producing light emitter, and biological substance labeling agent

A light emitter is formed from nanoparticles including a compound semiconductor containing an ag component, in component, and se component. The peak wavelength of the emission intensity falls within the range of 700 to 1400 nm, and the half-value width Δh for the peak wavelength is 100 nm or less.

Process for preparing thiadiazolo-isoindole-dione derivatives

The invention relates to a novel process for preparing 5h-[1,2,5]thiadiazolo[3,4-f]isoindole-5,7(6h)-dione (“tid”) derivatives, especially for preparing 4,8-diaryl-tid derivatives, to novel intermediates obtained and/or used in this process, to novel tid derivatives prepared by this process, to the use of these tid derivatives as monomers or building blocks for preparing conjugated polymers, and to the use of these tid derivatives or conjugated polymers as organic semiconductors or in organic electronic (oe) devices.. .

Double perovskite

The present invention relates to a semiconductor device comprising a semiconducting material, wherein the semiconducting material comprises a compound comprising: (i) one or more first monocations [a]; (ii) one or more second monocations [bi]; (iii) one or more trications [biii]; and (iv) one or more halide anions [x]. The invention also relates to a process for producing a semiconductor device comprising said semiconducting material.

Semiconductor packages and methods for fabricating semiconductor packages

According to various embodiments, there is provided a method for fabricating a semiconductor package, the method including forming a cap structure and a pillar from a first wafer; bonding the first wafer to a second wafer; and filling a gap between the pillar and the cap structure with a mold compound.. .

Semiconductor-oxides nanotubes-based composite particles useful for dye-removal and process thereof

Semiconductor-oxides nanotubes-based composite particles useful for dye-removal and process thereof, has been described in this invention, which relates to an innovative method, involving an ion-exchange mechanism operating under the dark-condition in an aqueous solution, for the processing of innovative products consisting of the nanotubes of semiconductor-oxides deposited on (or anchored to or attached to) the surface of flyash particles and metal-oxide (magnetic and non-magnetic) nanoparticles. The resulting micro-nano and nano-nano integrated composite particles find potential application in the removal of an organic synthetic-dye from an aqueous solution and industry effluent via the surface-adsorption process, involving the ion-exchange and electrostatic-attraction mechanisms, operating in the dark-condition.

Cooling devices

A cooling device includes a package substrate, a plurality of cooling units, and device electronics. The plurality of cooling units are configured to cool a user's body.

High signal-to-noise ratio light spectroscopy of tissue

A diagnostic system includes a light source having semiconductor sources, optical amplifiers, and fibers configured to deliver a first optical beam to a nonlinear element configured to broaden a spectrum of the first optical beam to at least 10 nanometers through a nonlinear effect in the nonlinear element, wherein a broadened-spectrum output beam comprises a near-infrared wavelength between 600-1000 nanometers. An interface device, having a cap with fiber leads configured to couple to the light source and to a receiver having one or more detectors, delivers the output optical beam to a tissue sample.

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Semiconductor device and manufacturing method therefor, and resin composition for forming flexible resin layer

Disclosed is a method for producing a semiconductor device including a circuit board having a flexible resin layer that encapsulates a circuit component. The method may include a step of immersing a flexible substrate in an encapsulant, drying the encapsulant, and thereby encapsulating the circuit component with the encapsulant; and a step of curing the encapsulant, and thereby forming a flexible resin layer..

Circuit board module, electronic device, and manufacturing circuit board module

According to one embodiment, an electronic device includes housing, a circuit board in the housing, a semiconductor package, and a support plate on a second surface of the circuit board. The support plate is arranged at a position corresponding to a corner of the first area and includes a main portion, a first projecting portion in contact with the main portion at a first side of the main portion, and a second projecting portion in contact with the main portion at a second side of the main portion.

Semiconductor device

A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded.

Solid-state image capturing element, manufacturing method therefor, and electronic device

The present disclosure relates to a solid-state image capturing element, a manufacturing method therefor, and an electronic device, which are capable of controlling a thickness of a depletion layer. The solid-state image capturing element includes pixels each in which a photoelectric conversion film configured to perform photoelectric conversion on incident light and a fixed charge film configured to have a predetermined fixed charge are stacked on a semiconductor substrate.

Method for manufacturing the semiconductor structure

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a gate structure, a first dielectric layer and two air gaps.

Millimeter wave cmos engines for waveguide fabrics

The present disclosure is directed to systems and methods for communicating between rack mounted devices disposed in the same or different racks separated by distances of less than a meter to a few tens of meters. The system includes a cmos first mm-wave engine that includes mm-wave transceiver circuitry, mm-wave modem circuitry, power distribution and control circuitry, and a mm-wave waveguide connector.

Semiconductor device, operating a semiconductor device, and system including the same

A semiconductor device may be provided. The semiconductor device may include a first input signal-inverting circuit, a second input signal-inverting circuit, a first level-shifting circuit and a second level-shifting circuit.

Cross bar switch structure for highly congested environments

A semiconductor circuit is provided having a crossbar switch arrangement, which includes at least one multiplexer, an output of which corresponds to an output of the crossbar switch arrangement. The arrangement also includes: a set of input lines connected to data inputs of the multiplexer, the input lines extending along a first direction of the semiconductor circuit; and a set of select lines connected to select inputs of the multiplexer, the select lines extending along a second direction of the semiconductor circuit, where the second direction differs from the first direction.

Photomask transportation stage in semiconductor fabrication and using the same

A transportation stage for transporting a photomask is provided. The transportation stage includes a vacuum source and a supporting plate.

Near-field based thermoradiative device

A thermoradiative device for generating power includes a thermoradiative element having a top surface and a bottom surface, wherein the thermoradiative element is a semiconductor material having a bandgap energy eg. The device includes a thermal conductive element having a first surface and a second surface, wherein the first surface is arranged to face the bottom surface of the thermoradiative element, and the first surface is a structured surface having a periodic structure, wherein the structured surface is separated from the bottom surface with a distance d to establish near-field resonance between the bottom surface and the structured surface.

Rectifier circuit

A rectifier circuit is configured to receive first and second alternate current (ac) signals that have opposite phases. The rectifier circuit includes a first half-wave rectifier circuit that includes a first metal-oxide-semiconductor (mos) transistor and a second mos transistor connected in series, and performs half-wave rectification on the first ac signal to generate a first direct current (dc) signal, a second half-wave rectifier circuit that includes a third mos transistor and a fourth mos transistor connected in series, and performs the half-wave rectification on the second ac signal to generate a second dc signal, the first dc signal and the second dc signal being outputted by the rectifier circuit to a load, and a body potential setting circuit configured to set a body potential of each of the first mos transistor, the second mos transistor, the third mos transistor, and the fourth mos transistor..

Rectifier device

A rectifier device is described herein. According to one example the rectifier device includes a semiconductor substrate, an anode terminal and a cathode terminal connected by a load current path of a first mos transistor and a diode connected parallel to the load current path.

Power semiconductor device and snubber circuit thereof

The present disclosure relates to a snubber circuit which comprises a static snubber unit, connected in parallel with the switch, for balancing a static voltage sharing across a switch when the switch is in a state of turn-on or turn-off; and a dynamic snubber unit for balance a dynamic voltage sharing across the switch when the switch is in a process of turn-on or turn-off, comprising a dynamic voltage sharing capacitor connected in parallel with the switch and having a relationship between a capacitance and a voltage of the dynamic voltage sharing capacitor; and a controller for controlling the capacitance of the dynamic voltage sharing capacitor to be in a predetermined working area of capacitance rising while the voltage across the switch is increasing. The present disclosure also relates to a power semiconductor device..

Optical semiconductor device

An optical semiconductor device capable of reducing the influence of reflected light is disclosed. The optical semiconductor device includes: a base; an optical semiconductor element that is provided on the upper surface of the base and emits light from a front end face and a rear end face, the rear end face facing the base; a cap that is provided on the base and has an emission window in a position facing the front end face of the optical semiconductor element, the light passing through the emission window; and a first optical absorption film that is provided in a region on the upper surface of the base and absorbs the light, the region facing the rear end face of the optical semiconductor element..

Method of fabricating semiconductor optical device and surface-emitting semiconductor laser

A method of fabricating a semiconductor optical device includes the steps of preparing a substrate product including a first side and a second side opposite to the first side, the first side including device sections and a street region extending between the device sections; forming a mask on the first side, the mask including device covering portions covering the respective device sections and an opening defining the device covering portions, the opening being provided in the street region; etching the substrate product using the mask so as to form a groove in the street region, the groove defining the device sections; after removing the mask, securing the first side to a support member; and forming an array of semiconductor chips on the support member by removing part of the substrate product from the second side until the groove is exposed so as to separate the device sections from each other.. .

Vcsels with improved optical and electrical confinement

An optoelectronic device includes a semiconductor substrate with a first set of epitaxial layers formed on an area of the substrate defining a lower distributed bragg-reflector (dbr) stack. A second set of epitaxial layers formed over the first set defines a quantum well structure, and a third set of epitaxial layers, formed over the second set, defines an upper dbr stack.

Method of fabricating surface-emitting laser

A method of fabricating a surface-emitting laser includes the steps of preparing an epitaxial substrate that includes an active layer and an upper stacked semiconductor layer provided on the active layer, the upper stacked semiconductor layer including a structure for forming an upper distributed bragg reflector; forming a mask for forming a semiconductor post on the epitaxial substrate; and etching the epitaxial substrate by dry etching using the mask. The step of etching the epitaxial substrate includes the steps of measuring photoluminescence from the epitaxial substrate in response to excitation light during the etching so as to monitor an end point of the dry etching in accordance with a result of the measuring; and ending the dry etching in response to detection of the end point..

Optical semiconductor device, optical transmitter module, optical module, and optical transmission equipment, and manufacturing thereof

Provided is an optical semiconductor device including a semiconductor substrate; a first semiconductor multilayer that is stacked on a first surface side of the semiconductor substrate, has a mesa structure extending along a light emitting direction, and emits light from an exit end surface; an electrode pad portion for wire bonding which is electrically connected to the upper surface of the mesa structure of the first semiconductor multilayer, is disposed on one side of the mesa structure, and is electrically connected to outside; and an electrode pad peripheral portion including a first rising surface which is in contact with the outer edge of the electrode pad portion on the exit end surface side and rises along the stacking direction from the electrode pad portion, in which a lower surface of the electrode pad portion is higher than the upper surface of the mesa structure of the first semiconductor multilayer.. .

Laser device

There is provided a laser device that is able to reduce management tasks by employing microbubble-containing water in which cooling water contains microbubbles. A semiconductor laser device includes a laser oscillation device that includes the one or more laser cavities and a housing that houses the one or more laser cavities; a cooling unit that is arranged outside the laser oscillation device, and can cool circulated cooling water that is used to cool the laser oscillation device; and a cooling water circulation passage that links the laser oscillation device and the cooling unit to allow the circulated cooling water to circulate therethrough, the circulated cooling water being microbubble-containing water that contains microbubbles having a peak diameter of 100 μm or less..

Light emitting device

A light emitting device includes a base, a frame, one or more semiconductor laser elements, a cover member, an optical member fixed to the cover member via an adhesive member, and a pressing member. The adhesive member includes one or more first adhesive portion disposed between an upper surface of the cover member and a lower surface of the optical member, and two or more second adhesive portions respectively disposed at locations in contact with or spaced apart from the one or more first adhesive portions when viewed from above, in contact with the first inner lateral surface of the cover member and the lateral surface of the optical member..

Light source device

Provided is a light source device, including: a base member; a semiconductor laser disposed on the base member; a lateral wall portion formed so as to surround the semiconductor laser; a light-transmissive lid covering a gap surrounded by the base member and the lateral wall portion; and a connection member that airtightly connects an upper surface of the lateral wall portion and a lower surface of the lid over an entire perimeter of the lateral wall portion. The lateral wall portion has a reflecting surface which is an inside surface connected to an upper surface, the reflecting surface being inclined so that light emitted from the semiconductor laser is reflected toward the lid.

Vertical channel organic thin-film transistor and manufacturing method thereof

The present invention provides a vertical channel organic thin-film transistor and a manufacturing method thereof. The vertical channel organic thin-film transistor includes: an annular organic semiconductor layer, an annular drain electrode and an annular source electrode respectively set in contact with upper and lower sides of the annular organic semiconductor layer, and a gate electrode arranged inwardly of an inner circle of the annular organic semiconductor layer and insulated and isolated from the annular organic semiconductor layer.

Organic semiconductor polymers

The organic semiconductor polymers relate to polymers containing an indolo-naphthyridine-6,13-dione thiophene (indt) chromophore. The organic semiconductor polymers are formed by polymerizing indt monomer with thiophene to obtain a conjugated polymer of the chromophore linked by thiophene monomers (indt-t), with phenyl to obtain a conjugated polymer of the chromophore linked by phenyl monomers (indt-p), with selenophene to obtain a conjugated polymer of the chromophore linked by selenophene monomers (indt-s), or with benzothiadazole to obtain a conjugated polymer of the chromophore linked by benzothiadazole monomers (indt-bt)..

Semiconductor device and fabricating the same

A semiconductor device includes a first word line, a first bit line, a mold film, and a first memory cell. The first bit line crosses a direction of the first word line and is spaced from the first word line.

Methods of forming magnetic memory cells and semiconductor devices

A magnetic cell includes a free region between an intermediate oxide region (e.g., a tunnel barrier) and a secondary oxide region. Both oxide regions may be configured to induce magnetic anisotropy (“ma”) with the free region, enhancing the ma strength of the free region.

Thermoelectric conversion device

A thermoelectric conversion device includes: a base material; a thermoelectric conversion element in which an n-type semiconductor layer and a p-type semiconductor layer are stacked on a first surface side of the base material with insulating layers therebetween; and a heat transfer part thermally joined to the base material and passing through the thermoelectric conversion element in a thickness direction of the thermoelectric conversion element, wherein first end sides of the n-type semiconductor layers and the p-type semiconductor layers are thermally joined to the heat transfer part on a side of the thermoelectric conversion element facing the heat transfer part in a state where the n-type semiconductor layer and the p-type semiconductor layer are electrically insulated from the heat transfer part.. .

Semiconductor light-emitting device

A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case.

Optoelectronic component having a lead frame with a stiffening structure

An optoelectronic component includes at least one optoelectronic semiconductor chip, wherein the semiconductor chip is arranged on a leadframe section, the leadframe section includes a stiffening structure projecting away laterally from the leadframe section, and the lead-frame section, the stiffening structure and the semiconductor chip are embedded in an electrically insulating housing.. .

Semiconductor light-emitting module and semiconductor led chip thereof

The present invention provides a semiconductor light-emitting module and a semiconductor led chip thereof. The semiconductor led chip includes a semiconductor light-emitting structure, a light-guiding structure layer, and a light-reflecting structure layer.

Light emitting diode module for surface mount technology and manufacturing the same

An led is provided to include: a first conductive type semiconductor layer; an active layer positioned over the first conductive type semiconductor layer; a second conductive type semiconductor layer positioned over the active layer; and a defect blocking layer comprising a masking region to cover at least a part of the top surface of the second conductive semiconductor layer and an opening region to partially expose the top surface of the second conductive type semiconductor layer, wherein the active layer and the second conductive type semiconductor layer are disposed to expose a part of the first conductive type semiconductor layer, and wherein the defect blocking layer comprises a first region and a second region surrounding the first region, and a ratio of the area of the opening region to the area of the masking region in the first region is different from a ratio of the area of the opening region to the area of the masking region in the second region.. .

Semiconductor light-emitting device

0.6≤tan(β)≤1.0. .

Semiconductor device

The semiconductor device includes a first conductivity-type semiconductor structure comprising a first stack and a second stack, wherein the first stack comprises alternate first layers and second layers, the second stack comprises alternate third layers and fourth layers. The semiconductor device includes a second conductivity-type semiconductor structure on the first conductivity-type semiconductor and includes an active structure between the first conductivity-type semiconductor structure and the second conductivity-type semiconductor structure.

Nitride semiconductor light emitting element

A nitride semiconductor light emitting element includes: an n-side layer; a p-side layer; an active layer including: a well layer containing al, ga, and n, and a barrier layer containing al, ga, and n, wherein an al content of the barrier layer is higher than that of the well layer; and an electron blocking structure layer between the active layer and the p-side layer and including: a first electron blocking layer disposed between the p-side layer and the active layer and having a bandgap larger than that of the barrier layer, a second electron blocking layer disposed between the p-side layer and the first electron blocking layer and having a bandgap larger than that of the barrier layer, but smaller than the bandgap of the first electron blocking layer, and an intermediate layer disposed therebetween and having a bandgap smaller than that of the second electron blocking layer.. .

Optoelectronic semiconductor chip and producing an optoelectronic semiconductor chip

An optoelectronic chip includes a semiconductor layer sequence including at least one n-doped semiconductor layer, at least one p-doped semiconductor layer, an active layer arranged between the at least one n-doped semiconductor layer and the at least one p-doped semiconductor layer, wherein the p-doped semiconductor layer is electrically contacted by a p-connection contact, the n-doped semiconductor layer is electrically contacted by an n-connection contact, the semiconductor chip has at least two trenches, the p-connection contact is located within the first trench and the n-connection contact is located within the second trench, below the p-connection contact and within the first trench a first dielectric mirror element is arranged, which is electrically insulated, and below the n-connection contact and within the second trench and between the n-connection contact and the n-doped semiconductor layer, a second dielectric mirror element is arranged at least in regions, the second dielectric mirror element being electrically insulated.. .

Method for manufacturing light emitting element

A method of manufacturing a plurality of light emitting elements, the method includes: providing a semiconductor wafer; dividing the p-side nitride semiconductor layer into a plurality of demarcated element regions; forming a protective layer on regions including an outer periphery of an upper surface of the p-side nitride semiconductor layer of each of the plurality of demarcated element regions and exposed side surfaces in the semiconductor structure that are formed by the selectively removing the portion of the p-side nitride semiconductor layer; reducing a resistance of regions of the p-side nitride semiconductor layer; and dividing the semiconductor wafer into a plurality of light emitting elements.. .

Method for producing an optoelectronic semiconductor component and optoelectronic semiconductor component

A method for producing an optoelectronic semiconductor component and an optoelectronic semiconductor component are disclosed. In an embodiment the method include a) providing at least two source substrates, wherein each of the source substrates is equipped with a specific type of radiation-emitting semiconductor chip; b) providing a target substrate having a mounting plane, the mounting plane being configured for mounting the semiconductor chip; and c) transferring at least part of the semiconductor chips with a wafer-to-wafer process from the source substrates onto the target substrate so that the semiconductor chips, within one type, maintain their relative position with respect to one another, so that each type of semiconductor chips arranged on the target substrate has a different height above the mounting plane, wherein the semiconductor chips are at least one of at least partially stacked one above the other or at least partially applied to at least one casting layer..

Inorganic salt-nanoparticle ink for thin film photovoltaic devices and related methods

Compositions for solution-based deposition of cigs films are described. The compositions include ternary, quaternary or quinary chalcogenide nanoparticles (i.e., cigs nanoparticles) and one or more inorganic salts dissolved or dispersed in a solvent to form an ink.

Optical device and manufacturing the same

Solution: an optical device includes a substrate 11, a semiconductor lamination portion formed on the substrate 11 and configured to receive or emit a light, a protective layer 3 that has a shape to cover an entire surface of the semiconductor lamination portion, a mold resin 6 configured to seal the protective layer 3 and the substrate 11 excluding a surface of the substrate 11 on an opposite side of a surface on which the semiconductor lamination portion is formed. The light is entered or emitted from a side of the substrate 11, and the mold resin 6 includes a through hole 61 configured to pass through from a top surface of the mold resin 6 to the protective layer 3.

Solar cell and manufacturing solar cell

A solar cell includes: a crystalline semiconductor substrate of a first conductivity type or a second conductivity type; an amorphous layer provided on a principal surface of the substrate; a first-conductivity-type semiconductor layer provided on the amorphous layer; a first high-conduction portion provided inside a first recess portion in the amorphous layer, the first high-conduction portion having a higher conductivity than the amorphous layer, the first high-conduction portion being in contact with the first-conductivity-type semiconductor layer; and a first electrode provided on the first-conductivity-type semiconductor layer. The first-conductivity-type semiconductor layer may be provided in a first region.

High voltage photovoltaics with stacked multi-junctions using wide bandgap materials

A photovoltaic device including a first cell positioned at a light receiving end of the photovoltaic device. The first cell has a first sequence of first semiconductor material layers of a first composition and the first junction has a first thickness.

High voltage photovoltaics with stacked multi-junctions using wide bandgap materials

A photovoltaic device including a first cell positioned at a light receiving end of the photovoltaic device. The first cell has a first sequence of first semiconductor material layers of a first composition and the first junction has a first thickness.

Mechanical matrix for enhancing the thermomechanical and chemical reliability of optoelectronic device technologies

Mechanical scaffolds within optoelectronic devices are provided to enhance the overall thermomechanical and chemical stability of these devices. For example, extremely fragile perovskite solar cells were reinforced by scaffolding in the following way: following printing, the scaffold was sequentially filled with an electron (hole) transport layer, photoactive perovskite semiconductor, a hole (electron) transport layer, and finally capped with a top electrode.

Reduced junction area barrier-based photodetector

A photodetector structure having a barrier layer disposed between a pair of like-conductively doped semiconductor layers, the barriers layer having a surface area smaller than the surface area of the upper one of the pair of semiconductor layers. A fill material is disposed between outer peripheral edges of the barrier layer and a region between outer peripheral edges of the first and second layers..

Wire-based metallization for solar cells

Approaches for fabricating wire-based metallization for solar cells, and the resulting solar cells, are described. In an example, a solar cell includes a substrate having a back surface and an opposing light-receiving surface.

Method of processing inconsistencies in solar cell devices and devices formed thereby

The present disclosure is directed to a method of processing a solar cell device. The method comprises detecting at least one inconsistency at a surface of a semiconductor substrate having a solar cell active region formed therein.

Coated foil-based metallization of solar cells

Coated foil-based approaches for metallization of solar cells, and the resulting solar cells, are described. For example, a solar cell includes a substrate.

Semiconductor device having resistance voltage dividing circuit

All resistors configuring a resistance voltage dividing circuit are formed by alternately arranging an n-type polycrystalline silicon and a p-type polycrystalline silicon and connecting the same in parallel or in series. The respective resistors themselves cancel a stress received from a resin upon packaging of the resistance voltage dividing circuit since the n-type polycrystalline silicon and the p-type polycrystalline silicon respectively indicate a shift amount in a reverse direction with respect to a stress.

Semiconductor device and manufacturing the same

It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer.

Semiconductor device and production same

A semiconductor device includes a thin film transistor including an oxide semiconductor layer and a wire connecting portion (201). The wire connecting portion (201) includes a lower electrically-conductive portion (3t) formed out of a same electrically-conductive film as the gate electrode, an insulating layer (15) having a contact hole (ch2) through which at least a part of the lower electrically-conductive portion (3t) is exposed, and an upper electrically-conductive portion (19t), at least a part of which is provided inside the contact hole (ch2).

Semiconductor device with reduced parasitic capacitance

A semiconductor device comprising a substrate and a transistor comprising a source, drain, and gate formed on the substrate. The semiconductor device further comprises a deep well formed in the substrate at a predetermined distance below the surface of the substrate and a contact configured to electrically couple the deep well to a voltage source such that a voltage can be applied to the deep well to create a substrate depletion region for reducing parasitic capacitance between the transistor and the substrate..

Semiconductor structure and fabrication method thereof

Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having a semiconductor substrate and a plurality of fins on the semiconductor substrate; forming an isolation structure on the semiconductor substrate, between adjacent fins and with a top surface lower than the top surfaces of the fins; forming a gate structure across of the fins by covering portions of top and side surfaces of the fins; forming a sidewall material layer to cover the gate structure and the fins; etching the sidewall material layer to form gate sidewall spacers on side surfaces of the gate structure and shadowing sidewall spacers on portions of side surfaces of the fins adjacent to the isolation structure; and performing an ion implantation process on the fins using the gate sidewall spacers and the shadowing sidewall spacers as a mask to form lightly doped regions in the fins..

Finfets with strained channels and reduced on state resistance

The present disclosure generally relates to semiconductor structures and, more particularly, to finfets with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material..

Semiconductor device structure having low rdson and manufacturing method thereof

A semiconductor device including a first p-type well region and an asymmetric second p-type well region each formed in a semiconductor substrate; a gate insulating layer and a gate electrode formed on the substrate; a first n-type source/drain region and a second n-type source/drain region that are formed on respective sides of the gate electrode; and an asymmetric ldd region of n-type formed to extend from the second source/drain region, wherein the asymmetric second p-type well region encompasses the second n-type source/drain region and the asymmetric ldd region, and the first n-type source/drain region both the asymmetric second p-type well region and the substrate, and the asymmetric second p-type well region is formed encompassing the second n-type source/drain region and in contact with the first n-type source/drain region. .

Method for manufacturing a silicon carbide semiconductor device

A step of forming a silicon carbide substrate includes steps of: forming a first impurity region having a first conductivity type by epitaxial growth; forming an embedded region by performing ion implantation into the first impurity region, the embedded region having a second conductivity type different from the first conductivity type, the embedded region being disposed cyclically; and forming a second impurity region by epitaxial growth, the second impurity region being in contact with the first impurity region and the embedded region, the second impurity region having the second conductivity type, the second impurity region having an impurity concentration lower than an impurity concentration of the embedded region. A trench is formed to have a side portion and a bottom portion.

Laterally diffused metal-oxide semiconductor field-effect transistor

A laterally diffused metal-oxide semiconductor field-effect transistor, comprising a substrate, a first conductivity type well region, a second conductivity type well region, a drain electrode in the first conductivity type well region, a source electrode and a body region in the second conductivity type well region, and a gate electrode arranged across surfaces of the first conductivity type well region and the second conductivity type well region, and also comprising a floating layer ring arranged on the top of the first conductivity type well region and located between the gate electrode and the drain electrode and a plurality of groove polysilicon electrodes running through the floating layer ring and stretching into the first conductivity type well region.. .

Semiconductor device and manufacturing method thereof

A semiconductor device in which a trench in a cell outer peripheral region configured to pull out a gate electrode and a trench in a cell region having a vertical transistor are formed with the same width to enable a reduction in chip area, and a manufacturing method thereof in which a gate contact hole is formed directly on a trench in a cell outer peripheral region on a self-alignment basis, and a gate wiring electrode is connected thereto are provided.. .

Semiconductor device and manufacturing method thereof

A provided method of manufacturing a semiconductor device includes formation of an interlayer insulating. The interlayer insulating film includes first and second insulating layers.

High frequency device

A high frequency device includes a first nitride semiconductor layer; a second nitride semiconductor layer provided on the first nitride semiconductor layer, and a third nitride semiconductor layer provided on the second nitride semiconductor layer. The second nitride semiconductor layer includes indium atoms, and has a layer thickness in a range of not less than 0.26 nanometers and not more than 100 nanometers..

Aluminum-rich field-plated nitride transistors for record high currents

New nitride semiconductor epitaxy incorporating high aluminum content is presented. It incorporated traces of indium that adequately tuned its lattice size closer to that of a narrower bandgap semiconductor that interfaced it and formed a 2deg device channel qw.

Semiconductor device

A semiconductor device having a first surface formed at a first height and a second surface formed at a second height on a semiconductor substrate includes: a base region formed in the semiconductor substrate; a trench formed from the first surface and the second surface into the semiconductor substrate; a gate insulating film covering an inner side of the trench; a gate electrode embedded to a third height; an insulating film formed on the gate electrode; a first region which has the first surface and in which a base contact region is formed; and a second region which has the second surface and in which a source region is formed, the first region and the second region being alternately arranged in the trench extension direction to prevent a reduction in channel formation density.. .

Method of forming semiconductor fin structure

A method of forming a semiconductor fin structure is provided. A substrate is provided, which has at least two sub regions and a dummy region disposed between the two sub regions.

Semiconductor device and manufacturing such a semiconductor device

A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) for forming two channel layers applying a first mask and applying a p first dopant, for forming two source regions forming a second mask by applying a further layer on the lateral sides of the first mask and applying an n second dopant, for forming two well layers forming a third mask by removing such part of the second mask between the source regions and applying a p third dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers; wherein the well layers surround the plug in the lateral direction and separate it from the two source regions.. .

Semiconductor device structure and forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a top surface, a source region, and a drain region.

Finfet structure with composite gate helmet

A finfet device includes a fin structure, a gate structure, a gate helmet, a pair of spacers and a contact structure. The fin structure protrudes from a semiconductor substrate.

Semiconductor device

A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion.

Methods of forming a semiconductor device with a gate contact positioned above the active region

One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a stepped final gate structure with a second recess defined therein, wherein, when viewed from above, the second recess is axially and laterally offset from the first recess. In this example, the device also includes a layer of insulating material positioned above the stepped conductive source/drain structure and the stepped final gate structure, a conductive gate (cb) contact that is conductively coupled to the stepped final gate structure and a conductive source/drain (ca) contact that is conductively coupled to the stepped conductive source/drain structure..

Semiconductor device

A semiconductor device includes first and second electrodes, a first semiconductor region between the first and second electrodes, a second semiconductor region between the first semiconductor region and the second electrode, a third semiconductor region between the second semiconductor region and the second electrode, a fourth semiconductor region between the third semiconductor region and the second electrode, a fifth semiconductor region between first and second portions of the fourth semiconductor region, first and second conductive regions extending inwardly of second, third and fourth semiconductor regions and insulated therefrom, an insulating region between the fourth semiconductor region and the second electrode and between the first and second conductive regions and the second electrode, and third and fourth conductive regions extending from respective first and second conductive regions inwardly of the third insulating region. Widths of third and fourth conductive regions are less than widths of first and second conductive regions, respectively..

Semiconductor device, inverter circuir, and vehicle

A semiconductor device according to embodiments described herein includes a p-type sic layer, a gate electrode, and a gate insulating layer between the sic layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, a first region, and a second region.

Semiconductor device and manufacturing the same

In a vertical power mosfet having a superjunction structure, the withstand voltage of the power mosfet can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions pr1 are formed on the sides of an n-type column nc1 adjacent to a p-type column region pc1.

Methods of forming a vertical transistor device with a channel structure comprised of alternative semiconductor materials

One illustrative method disclosed herein includes, among other things, forming a sacrificial mandrel structure above a semiconductor substrate comprising a first semiconductor material and forming a plurality of vertically-oriented channel semiconductor (vocs) structures on at least opposing lateral sidewall surfaces of the sacrificial mandrel structure, the vocs structures comprising a second semiconductor material that is different than the first semiconductor material. In this example, the method also includes selectively removing the sacrificial mandrel structure relative to the vocs structures and forming upper and lower source/drain regions in each of the vocs structures and a gate structure around each of the vocs structures..

Semiconductor device and manufacturing the same

A semiconductor device 1 includes: a well region 5 provided on a surface layer of a semiconductor substrate 2; a source region 14s and a drain region 15d disposed to be distant from each other on the surface layer of the well region 5; a channel region 6 provided between the source region 14s and the drain region 15d; and a gate electrode 8 provided over the channel region 6 with a gate insulator 7 interposed therebetween. A gate length of the gate electrode 8 is 1.5 μm or less, the channel region 6 includes indium as a channel impurity, a distance between a surface of the channel region 6 and a concentration peak position of the channel impurity is 20 nm to 70 nm, and a concentration of the channel impurity gradually decreases in a direction from the concentration peak position of the channel impurity to the surface of the channel region..

Ldd-free semiconductor structure and manufacturing the same

The present disclosure provides an ldd-free semiconductor structure including a semiconductor layer, a gate over the semiconductor layer and a regrowth region made of semiconductor material positioned in the semiconductor layer. The regrowth region forms a source region or a drain region of the ldd-free semiconductor structure.

Semiconductor device and manufacturing semiconductor device

A high-electron-mobility transistor has a buffer layer, a channel layer, a barrier layer, a mesa-shaped cap layer, a source electrode formed on one side of the cap layer, a drain electrode formed on the other side, and a gate electrode formed over the cap layer via a gate insulating film. The semiconductor device has an element isolation region defining an active region in which the semiconductor device is provided.

Field effect transistor structure having notched mesa

A field effect transistor structure is provided having: a semi-insulating substrate; a semiconductor mesa structure disposed on the substrate and having a notch in an outer sidewall of the mesa structure; a source electrode disposed within the opposing sidewalls in ohmic contact with a source region of the mesa structure; a drain electrode disposed within the opposing sidewalls in ohmic contact with a drain region of the mesa; and a gate electrode, having an inner portion disposed between, and laterally of, the source electrode and the drain electrode and in schottky contact with the mesa structure, extending longitudinally towards the notch and having outer portions extending beyond the mesa structure and over portions of the substrate outside of the mesa structure. In one embodiment, the mesa structure includes a pair of notches projecting inwardly towards each other and the inner portion of the gate extends longitudinally between the pair of notches..

Method for manufacturing semiconductor device and edge termination structure of semiconductor device

A method for manufacturing a semiconductor device having a edge termination region comprises a stacking process, an ion implantation process, and a heat treatment process. In the stacking process, a p-type semiconductor layer containing a p-type impurity is stacked on an n-type semiconductor layer containing an n-type impurity.

Semiconductor device having a field electrode and a gate electrode in a trench structure and manufacturing method

A semiconductor device includes a semiconductor body having a semiconductor substrate of a first conductivity type and a semiconductor layer of the first conductivity type on the substrate. A trench structure extends into the semiconductor body from a first surface and includes a gate electrode and at least one field electrode arranged between the gate electrode and a bottom side of the trench structure.

Semiconductor device

A semiconductor device is provided, including a semiconductor substrate; a first conductivity type drift region provided inside the semiconductor substrate; a plurality of gate trench portions provided extending from an upper surface of the semiconductor substrate and reaching the drift region; a dummy trench portion provided between two gate trench portions and provided extending from the upper surface of the semiconductor substrate and reaching the drift region; a second conductivity type base region provided: in a region of the semiconductor substrate adjacent to any of the gate trench portions; and between the upper surface of the semiconductor substrate and the drift region; and a second conductivity type first well region provided: in a region of the semiconductor substrate adjacent to the dummy trench portion; and reaching a position deeper than a lower end of the dummy trench portion; and having a doping concentration higher than that of the base region.. .

Sinusoidal shaped capacitor architecture in oxide

A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places an oxide layer on top of a metal layer.

Radio frequency resistor element

A radio frequency resistor element comprises a resistive polysilicon trace, an isolation component and a semiconductor substrate. The resistive polysilicon trace is located above the isolation component.

Coating made of a semiconductor material

The present disclosure relates to coated particles. The teachings thereof may be embodied in coated particles, a method for their production, and the use of the coated particles in x-ray detectors, gamma detectors, uv detectors, or solar cells.

Solid-state image sensor, and electronic device

There is provided an image sensor including a semiconductor substrate having a first side and a second side and a photoelectric conversion element disposed at the first side of the semiconductor substrate. In addition, a through electrode is coupled to the photoelectric conversion element, where the through electrode includes a conductive portion and an insulating film.

Methods and three-dimensional nonvolatile memory

A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The nonvolatile memory material includes a semiconductor material layer, a conductive oxide material layer and a semiconductor oxide region.

Semiconductor device having data storage pattern

A semiconductor device including a data storage pattern is provided. The semiconductor device includes a first conductive line disposed on a substrate and extending in a first direction, a second conductive line disposed on the first conductive line and extending in a second direction, and a first data storage structure and a first selector structure disposed between the first conductive line and the second conductive line and connected in series.

Methods and three-dimensional nonvolatile memory

A method is provided that includes forming a bit line above a substrate; forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-volatile memory material coupled in series with an isolation element.

Semiconductor light emitting device

A semiconductor light emitting device includes a plurality of light emitting cells including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer between the first and second conductivity type semiconductor layers, an insulating layer on the plurality of light emitting cells and having a first opening and a second opening defining a first contact region of the first conductivity type semiconductor layer and a second contact region of the second conductivity type semiconductor layer, respectively, in each of the plurality of light emitting cells, a connection electrode on the insulating layer and connecting the first contact region and the second contact region to electrically connect the plurality of light emitting cells to each other, a transparent support substrate on the insulating layer and the connection electrode, and a transparent bonding layer between the insulating layer and the transparent support substrate.. .

Systems and methods for manufacturing semiconductor modules

A method for manufacturing semiconductor modules for image-sensing devices is disclosed. The method may comprise applying a removable layer on a first surface of a printed circuit board (pcb) which comprises a plurality of pcb units; mounting a photosensitive member to a second surface of each of the pcb units; and encapsulating the photosensitive member with an encapsulation layer on each pcb unit.

Dual active layer semiconductor device and manufacturing the same

Some embodiments include an imaging system. The imaging system includes an active matrix pixel array having a flexible substrate and a pixel.

Semiconductor device and solid-state imaging device

The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a si substrate and wiring layers laminated on the si substrate and a second substrate that is constituted by a si substrate and wiring layers laminated on the si substrate and is joined to the upper substrate.

Semiconductor apparatus and equipment having laminated layers

In a semiconductor apparatus including: a semiconductor substrate in which a plurality of semiconductor elements are provided; a first semiconductor layer which is overlapped on the semiconductor substrate and in which a plurality of photoelectric conversion elements are provided; a second semiconductor layer that is arranged between the semiconductor substrate and the first semiconductor layer; a first wiring structure that is arranged between the first semiconductor layer and the second semiconductor layer; a second wiring structure that is arranged between the second semiconductor layer and the semiconductor substrate; and a third wiring structure that is arranged between the second wiring structure and the semiconductor substrate, widths of a plurality of through electrodes are different from each other.. .

Back-illuminated solid-state imaging element

A back-illuminated solid-state imaging element includes a semiconductor substrate which has a front surface and a back surface provided with a recess, and in which a thinned section, which is a bottom section of the recess, is an imaging area, a signal read-out circuit formed on the front surface of the semiconductor substrate, a boron layer formed on at least the back surface of the semiconductor substrate and a lateral surface of the recess, a metal layer formed on the boron layer, and provided with an opening opposing a bottom surface of the recess, and an anti-reflection layer formed on the bottom surface of the recess.. .

Semiconductor structure, back-side illuminated image sensor and manufacturing the same

A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (beol) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the beol metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.. .

Method of manufacturing optical semiconductor device

A method of manufacturing an optical semiconductor device includes preparing a semiconductor substrate having a plurality of photoelectric conversion parts, forming a trench in the semiconductor substrate to separate the plurality of photoelectric conversion parts from each other, forming a boron layer on an inner surface of the trench by a vapor phase growth method, and forming an accumulation layer in the semiconductor substrate along the inner surface of the trench by performing a thermal diffusion treatment on the boron layer.. .

Optical semiconductor device

An optical semiconductor device includes a semiconductor substrate having a plurality of photoelectric conversion parts and having a trench formed to separate the plurality of photoelectric conversion parts from each other, an insulating layer formed on at least an inner surface of the trench, a boron layer formed on the insulating layer, and a metal layer formed on the boron layer.. .

Optical isolation structure for reducing crosstalk between pixels and fabrication method thereof

An optical isolation structure and a method for fabricating the same are provided. The optical isolation structure includes an epitaxial layer and a dielectric layer.

Tft substrate and manufacturing method thereof

A manufacturing method of a tft substrate uses a top gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced.

Display device

According to one embodiment, a display device includes a pixel, a scanning line, a signal line, a pixel electrode, a first switching element, and a capacitance line producing capacitance together with the pixel electrode. The first switching element includes a first semiconductor layer connected to the signal line and the pixel electrode, and a first gate electrode opposed to the first semiconductor layer and connected to the scanning line.

Display device

The purpose of the invention is to improve reliability of the tft of the oxide semiconductor. The invention is characterized as follows.

Display device

The purpose of the present invention is to improve reliability of the tft of the oxide semiconductor. The feature of the invention is: a display device comprising: a substrate including a display area where plural pixels are formed, the pixel includes a first tft of a first oxide semiconductor, a first gate insulating film is formed under the first oxide semiconductor, a first gate electrode is formed under the first gate insulating film, an interlayer insulating film is formed on the first oxide semiconductor; a drain wiring, which connects with the first oxide semiconductor, and a source wiring, which connects with the first oxide semiconductor, are formed on the interlayer insulating film; the drain wiring or the source wiring is a laminated structure of a second oxide semiconductor and a first metal, the second oxide semiconductor is under the first metal..

Display device

The purpose of the present invention is to realize the tft of the oxide semiconductor having a superior characteristics and high reliability during the product's life. The structure of the present invention is as follows.

Display device and manufacturing the same

An object of the present invention is to decrease substantial resistance of an electrode such as a transparent electrode or a wiring, and furthermore, to provide a display device for which is possible to apply same voltage to light-emitting elements. In the invention, a auxiliary wiring that is formed in one layer in which a conductive film of a semiconductor element such as an electrode, wiring, a signal line, a scanning line, or a power supply line is connected to an electrode typified by a second electrode, and a wiring.

Semiconductor device

A semiconductor device which can suppress leakage current between a wiring and a connection electrode connected to a floating node is provided. The semiconductor device includes a first insulator, a first conductor over the first insulator, a second conductor over the first insulator, and a second insulator over the first insulator, the first conductor, and the second conductor.

Semiconductor integrated circuit device

A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (area a to area i).

Non-volatile memory device and manufacturing same

According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer.

Semiconductor device and a manufacturing method thereof

In a monos memory having an ono film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ono film and a semiconductor substrate under the ono film. When a polysilicon film formed over the ono film on is processed to form the control gate electrode, the ono film is not processed.

Memory cell, nonvolatile semiconductor storage device, and manufacturing nonvolatile semiconductor storage device

When a memory cell (mc) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (s2) with a high impurity concentration inside the fin (s2), the shape of the fin (s2) can be set such that a potential difference between a memory gate electrode (mg) and the fin (s2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (mc) achieves downsizing and suppression of the occurrence of disturbance..

Devices with contact-to-gate shorting through conductive paths between fins and fabrication methods

Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method includes, for instance: obtaining wafer with a substrate, at least one fin, at least one hard mask, and an oxide layer; etching the oxide layer to reveal at least one of a portion of the hard masks; forming sacrificial pillars over the substrate; forming sacrificial gates, wherein at least one sacrificial gate contacts at least one sacrificial pillar; growing an epitaxial layer between the at least one sacrificial gate and the at least one sacrificial pillar; starting a rmg process on the sacrificial gates; etching to remove the sacrificial pillars and form pillar openings; and completing the rmg process to fill the pillar openings and the gate openings with a metal..

Semiconductor memory device

A semiconductor memory device having a memory cell including a plurality of memory cells, a first p-type well region, a second p-type well region, and an n-type well region disposed between the first p-type well region and the second p-type well region. The semiconductor memory element defines a plurality of first regions, a plurality of second regions, a plurality of third regions, and a plurality of fourth regions, and each first region includes the memory cell.

Semiconductor device and manufacturing method thereof

The present invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate with a memory cell region and a peripheral region, a gate line in the peripheral region, an etch-stop layer covering the gate line and the semiconductor substrate, a first insulating layer covering the etch-stop layer, two contact plugs disposed on the semiconductor substrate in the peripheral region, two pads disposed on the contact plugs respectively, and a second insulating layer disposed between the pads.

Semiconductor memory devices including separate upper and lower bit line spacers

A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer.

Semiconductor memory device and forming the same

A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a plurality of active areas, a shallow trench isolation, a plurality of trenches and a plurality of gates. The active areas are defined on a semiconductor substrate, and surrounded by the shallow trench isolation.

Method of forming semiconductor memory device

A method of forming a semiconductor memory device includes following steps. First of all, a dielectric layer is formed on a semiconductor substrate, and a conductive pad is formed in the dielectric layer.

Semiconductor structures with deep trench capacitor and methods of manufacture

An integrated finfet and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (soi) substrate.

Semiconductor constructions, and semiconductor processing methods

Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces.

Semiconductor device

An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor.

Semiconductor device and forming the semiconductor device

A semiconductor device includes a first sige fin formed on a substrate and including a first amount of ge, and a second sige fin formed on a substrate and including a central portion including a second amount of ge, and a surface portion comprising a third amount of ge which is greater than the second amount.. .

Method of fabricating semiconductor device

A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant..

Semiconductor device and fabricating the same

A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern.

Three dimensional lvdmos transistor structures

A semiconductor device having a first stack and a second stack of device components. The first stack has a transistor switching element having a channel, a source in contact with the channel, a drain in contact with the channel, and a gate structure at least partially disposed in a space defined between and separating the source and the drain.

Semiconductor device with snubber and associated fabrication method

A semiconductor device having a dummy trench structure. The dummy trench structure vertically extends from the top surface of the semiconductor device through a body region into a semiconductor initial layer, and the body region separates the dummy trench structure from a source region.

Cmos compatible fuse or resistor using self-aligned contacts

A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure is formed in the gap on the dielectric layer and extends longitudinally beyond the gap on end portions.

Method and device for electrical overstress and electrostatic discharge protection

A semiconductor device is protected from electrical overstress (eos) and electro-static discharge (esd) events by a series protection circuit electrically coupled in series along the transmission line between a signal source and a load. The series protection circuit includes a first field-effect transistor (fet) electrically coupled in series between the signal source and load.

Semiconductor device and operation the same

To make a gate insulating film of a selecting transistor coupled in series to a monos memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an soi substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other..

Semiconductor device packages, packaging methods, and packaged semiconductor devices

Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region.

Hybrid bonding with through substrate via (tsv)

A semiconductor device structure is provided. The semiconductor device structure includes a bonding structure formed between a first substrate and a second substrate.

Power semiconductor module for an inverter circuit and manufacturing the same

A semiconductor device according to the present invention incudes a semiconductor chip, a conductive member for supporting the semiconductor chip, a joint material provided between the conductive member and the semiconductor chip, and a release groove formed on the surface of the conductive member and arranged away from the semiconductor chip with the one end and the other end of the release groove connected to the peripheral edges of the conductive member, respectively.. .

Apparatus for direct transfer of semiconductor device die

An apparatus for performing a direct transfer of a die. The apparatus includes a first frame to hold the first substrate and a second frame to hold the second substrate.

Semiconductor packages and methods of manufacturing the same

There may be provided a method of manufacturing a semiconductor package. The method may include forming a plurality of stack structures on a wafer to be laterally spaced apart from each other.

System on package architecture including structures on die back side

Embodiments include devices and methods, including a device including a substrate comprising a semiconductor, the substrate including a front side comprising active elements and a backside opposite the front side. The device includes a dielectric layer on the backside, and a passive component on the dielectric layer on the backside.

Resin composition, bonded body and semiconductor device

A resin composition is provided, including a binder resin, and silver-coated particles in which a functional group is introduced to a surface. A ratio (a/b) of young's modulus (a) of the silver-coated particles to young's modulus (b) of the binder resin after being cured is 0.1 to 2.0, and the young's modulus (a) of the silver-coated particles is 0.05 to 2.0 gpa..

Resin-encapsulated semiconductor device and manufacturing the same

The resin-encapsulated semiconductor device includes a bump electrode (2) formed on an element surface side of a semiconductor chip (1), a conductive layer (3) electrically connected to the bump electrode (2), and a resin encapsulation body (6) covering the semiconductor chip (1), the bump electrode (2), and the conductive layer (3). On a back surface of the semiconductor chip (1) that is flush with a back surface of the resin encapsulation body (6), a metal layer (4) and a laminated film (5) are formed.

Methods of interconnect for high density 2.5d and 3d integration

Methods and apparatus are described for enabling copper-to-copper (cu—cu) bonding at reduced temperatures (e.g., at most 200° c.) by significantly reducing cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas).

Package structure and forming package structure

A package structure includes a first dielectric layer, a first semiconductor device, a first redistribution line, a second dielectric layer, a second semiconductor device, a second redistribution line, a first conductive feature, and a first molding material. The first semiconductor device is over the first dielectric layer.

Package structure and forming package structure

A method of forming a package structure includes disposing a semiconductor device over a first dielectric layer, wherein a first redistribution line is in the first dielectric layer, forming a molding compound over the first dielectric layer and in contact with a sidewall of the semiconductor device, forming a second dielectric layer over the molding compound and the semiconductor device, forming a first opening in the second dielectric layer, the molding compound, and the first dielectric layer to expose the first redistribution line, and forming a first conductor in the first opening, wherein the first conductor is electrically connected to the first redistribution line.. .

Processing techniques for silicon-based transient devices

Provided are methods of making a transient electronic device by fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by a mother substrate. The components may independently comprise a selectively transformable material and, optionally, further have a preselected transience profile.

Semiconductor device and manufacturing the same

A semiconductor device includes a substrate, a device layer, and a film. The substrate includes a first semiconductor element, and has a first surface, a second surface, and a side surface between the first surface and the second surface.

Wafer level packages, semiconductor device units, and methods of fabricating the same

A wafer level package and or a semiconductor device unit may be provided. The wafer level package may include semiconductor chips disposed on an interconnection structure layer and laterally spaced apart from each other.

Semiconductor power device and a assembling a semiconductor power device

Some embodiments are directed to a semiconductor power device and a method of assembling such a device is provided. The semiconductor power device includes a first substrate, a second substrate and an interconnect structure.

Die interconnect substrates, a semiconductor device and a forming a die interconnect substrate

Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure.

Semiconductor device and method

A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of depositing a first insulating material over a substrate, and forming a first conductive contact in the first insulating material. The first conductive contact has a protruding uppermost surface, with a first height along a central portion of the first conductive contact, and a second height along a vertical vector projection of a sidewall of the first conductive contact.

Semiconductor device

A semiconductor device includes an active fin extended in a first direction on a substrate. A gate structure extends in a second direction, wherein the gate structure intersects the active fin and covers an upper portion of the active fin.

Semiconductor device having contacts with varying widths

A semiconductor device includes a substrate having a plurality of fins protruding therefrom and an active region on the fins. The device further includes a contact including a conductive region having a concave portion defining an upper portion and a lower portion of the conductive region, an interlayer insulating layer on the active region, and a side insulating layer interposed between the interlayer insulating layer and the lower portion of the conductive region..

Semiconductor device

Provided is a semiconductor device including a fuse element arranged on an interlayer insulating film formed on a semiconductor substrate. The fuse element is formed of polysilicon and a silicide region arranged on an upper surface of the polysilicon.

Semiconductor device having multilayer interconnection structure and manufacturing the same

A method of manufacturing a semiconductor device includes forming a stacked structure including at least one interconnection pattern layer and at least one contact plug on over a substrate, forming an interlayer insulation material layer over an uppermost interconnection pattern layer or an uppermost contact plug of the stacked structure, patterning the interlayer insulation layer to form an interlayer insulation layer including one or more openings that expose the uppermost interconnection pattern layer or the uppermost contact plug, forming a metal nitride thin film along a surface of a resulting structure of the interlayer insulation layer, forming a metal thin film over the metal nitride thin film by filling at least the remaining portions of the one or more openings after the metal nitride thin film is formed, and planarizing the metal thin film and the metal nitride thin film using chemical mechanical polishing.. .

Interconnects for semiconductor packages

Interconnects for semiconductor packages are described. An apparatus may comprise a decoupling capacitor on a logic board, and a conductive interconnect element on the logic board, the conductive interconnect element to connect the decoupling capacitor on the logic board to a power conductor comprising a power pad of a semiconductor package, the conductive interconnect element at a different layer than a ground-potential layer of the logic board.

Non-planar metal-insulator-metal capacitor formation

A method for forming a semiconductor structure having a non-planar mim capacitor is provided. The method includes forming a first dielectric layer on a base structure that has one or more recesses each comprising contours formed at two or more planar levels.

Transistor structures

The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines..

Package structure and forming thereof

A package structure includes a semiconductor device, a first redistribution line, a dielectric layer, a first conductive bump and a first sealing structure. The dielectric layer is over the first redistribution line and has a first opening therein.

Fan-out semiconductor package

A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection member; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed therein and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the passive component is electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member..

Semiconductor device and manufacturing semiconductor device

A semiconductor device includes a base plate to which a stacked substrate is bonded, the stacked substrate being mounted on a semiconductor chip. The semiconductor device further includes a heat sink mounted to the base plate, via thermal paste and a metal ring.

Method of packaging a semiconductor die

A method of packaging a semiconductor die includes connecting an interposer frame directly to a substrate, wherein the interposer frame has a plurality of conductive columns. The method further includes attaching the semiconductor die to the substrate in an opening of the interposer frame, wherein the semiconductor die directly contacts the substrate.

Semiconductor device and electronic apparatus

Provided is a semiconductor device enabling highly accurate adjustment of a mounting height at a time when the semiconductor device is mounted on an assembly board, and an electronic apparatus. A linear lead is extracted from a bottom surface of a cylindrical resin sealing body covering a semiconductor chip, and a plurality of helical leads are arranged so as to wind around the linear lead, to thereby form a multi-helical structure.

3d-microstrip branchline coupler

The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias.

Method of forming semiconductor device having a dual material redistribution line

A method of making a semiconductor device includes plating a first conductive material over a first passivation layer, wherein the first conductive material fills an opening in the first passivation layer and electrically connects to an interconnect structure. The method further includes planarizing the first conductive material, wherein a top surface of the planarized first conductive material is coplanar with a top surface of the first passivation layer.

Method for producing semiconductor device and semiconductor device

A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a through via extending through the semiconductor substrate from the first surface to the second surface, a metal layer adjacent an inside surface of the through via, and an insulating film including oh bonds located between the semiconductor substrate and the metal layer, the insulating film having a thickness of 1 μm or less.. .

Method for producing semiconductor device and semiconductor device

A method of producing a semiconductor device includes forming, on a semiconductor substrate comprising a first surface on which an insulating layer covering a wiring structure and a first through via passing through the insulating layer are formed and a second surface opposed to, and facing away from, the first surface, a patterned first insulating film comprising at least one opening therethrough on the second surface, forming a through via hole inwardly of the second surface within which the wiring structure is exposed, by anisotropic dry etching into the second surface side of the semiconductor substrate through the at least one opening in the first insulating film, using a gas mixture containing sf6, o2, sif4, and at least one of cf4, cl2, bcl3, cf3i, and hbr, and forming a second through via in the through via hole.. .

Power module apparatus, cooling structure, and electric vehicle or hybrid electric vehicle

A power module apparatus (10) comprises: a power module (100a) comprising a package (110) configured to seal a perimeter of a semiconductor device, and a heat radiator (42) bonded to one surface of the package; a cooling device (30) comprising a coolant passage (33) through which coolant water flows, in which the heat radiator is attached to an opening (35) provided on a way of the coolant passage, wherein the heat radiator (42) of the power module (100a) is attached to the opening (35) of the cooling device (30) so that a height (ha) and a height (hb) are substantially identical to each other. The power module in which the heat radiator is attached to the opening formed at the upper surface portion of the cooling device can also be efficiently cooled, and thereby it becomes possible to reduce degradation due to overheating..

Semiconductor device and manufacturing semiconductor device

A space having a certain thickness is provided between a metal base and a heat-dissipation fin set or the like. A semiconductor device is provided, including: a package portion; a metal base which is housed in the package portion and is exposed at a lower surface of the package portion; a semiconductor chip which is housed in the package portion and is placed above the metal base; and a frame portion provided to surround a penetration space penetrating the package portion, wherein a lower end of the frame portion protrudes below the lower surface of the package portion and a lower surface of the metal base.

Heat transfer plate having small cavities for taking up a thermal transfer material

A power semiconductor device module includes, among other parts, a dmb structure. The dmb structure includes a ceramic sheet, a top metal plate that is directly bonded to the top of the ceramic, and a bottom metal plate that is directly bonded to the bottom of the ceramic.

Package structure and forming package structure

A package structure includes a semiconductor device, a first molding compound, a through-via, a first dielectric layer, a first redistribution line, and a second molding compound. The first molding compound is in contact with a sidewall of the semiconductor device.

Semiconductor module

A semiconductor module includes a metal substrate having a mounting surface, a first conductive plate on the mounting surface, an insulating substrate on the first conductive plate, a second conductive plate on the insulating substrate, a conductive pad on the insulating substrate, a semiconductor element on the second conductive plate, a circuit board electrically connected to the conductive pad, a resin case connected to the metal substrate and extending along at least a portion thereof, and around the first conductive plate, the insulating substrate, the second conductive plate, the conductive pad, the semiconductor element, and the circuit board, and a silicone gel in a region bounded by the metal substrate and the resin case. The circuit board comprises a plurality of planar surfaces oriented perpendicular to the mounting surface of the metal substrate..

Semiconductor device and power converter

A semiconductor device includes: at least one power semiconductor element; a sealing resin disposed so as to seal the power semiconductor element; and a plurality of electrical terminals each electrically connected to the power semiconductor element and each including a protrusion protruding from a surface of the sealing resin. The protrusion includes a first part that is provided on a side of the sealing resin in a protrusion direction of the protrusion and of which a cross-section intersecting the protrusion direction has one of a circular shape and an oval shape..

Semiconductor device comprising a die seal including long via lines

A semiconductor device includes a metallization system positioned above a substrate and a die seal positioned at least in the metallization system and delimiting a die region. The die seal includes a via line feature having an axial length and including one or more first portions having a first target dimension and one or more second portions along the axial length.

Semiconductor module

Provided is a semiconductor module in which a case and a base plate joined together with a simple structure, the semiconductor module having high insulation strength. The semiconductor module includes the following: a base plate; at least one semiconductor chip disposed inside the base plate other than the outer periphery of the base plate and above the base plate; and a case joined to the outer periphery of the base plate with an adhesive, and containing the at least one semiconductor chip.

Methods for optical endpoint detection using an endpoint booster

Plasma etching a semiconductor wafer in a vacuum etch chamber includes transmitting an optical signal through an aperture in an endpoint booster that is coupled to a vacuum side of the vacuum etch chamber, analyzing the optical signal to determine an endpoint of the plasma etch process, ending the plasma etch process when the optical signal reaches a first threshold, and cleaning the viewport when the optical signal is below a second threshold. The endpoint booster inhibits process byproducts from accumulating on the viewport during the plasma process, which increases the time between chamber cleanings.

Manufacturing semiconductor device, semiconductor device, and inspection semiconductor device

In a wafer inspection step for testing electrical characteristics of an integrated circuit in a chip region (cp) formed in a wafer, a first probe needle having a relatively small diameter is brought into contact with a first pad for small current and a second probe needle having a relatively large diameter is brought into contact with a second pad for large current. A wiring and a field effect transistor, which are used for forming the integrated circuit, are arranged directly under the first pad to which a relatively small needle pressure of the first probe needle is to be applied.

Method for measuring charge accumulation in fabrication process of semiconductor device and fabricating semiconductor device

A method for measuring charge accumulation in a fabrication process of a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided.

Method for fabricating a row of mos transistors

A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other.

Integration of semiconductor structures

At least one embodiment relates to a method for integrating si1-xgex structures with si1-x′gex′ structures in a semiconductor device. The method includes providing a device that includes a plurality of si1-xgex structures, where 0≤x<1.

Technological preventing, by means of buried etch stop layers, the creation of vertical/lateral inhomogeneities when etching through-silicon vias

Method for producing a semiconductor device by providing a silicon wafer having a plurality of equal height raised portions on a first surface thereof; depositing an etch stop layer on the first surface; planarizing a surface of the etch stop layer; permanently bonding a first carrier wafer on the etch stop layer surface; producing components on or in a second wafer surface in a feol process; etching a plurality of trenches into the wafer, each trench formed at the respective location of one of the raised portions; depositing side wall insulation layers on side walls of the trenches; forming through-silicon vias by filling the trenches with electrically conductive material; producing a conductor path stack in a beol process for contacting the active components on the second surface; temporarily bonding a second carrier wafer onto a surface of the conductor path stack; removing the first carrier wafer and exposing the vias.. .

Forming self-aligned vias and air-gaps in semiconductor fabrication

A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench.

Semiconductor structure and fabrication method thereof

A semiconductor structure and a fabrication method are provided. The fabrication method includes: providing a substrate; forming a dielectric layer with an opening on the substrate; forming a first barrier layer on sidewall and bottom surfaces of the opening, the first barrier layer being doped by manganese; and forming a metal interconnect on the first barrier layer, the metal interconnect being located within the opening..

Parallel plate waveguide for power semiconductor package

A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device by performing a process on a substrate includes: forming a protective layer made of a polymer having a urea bond by supplying a raw material for polymerization to a surface of a substrate on which a protected film to be protected is formed; forming a sealing film at a first temperature lower than a second temperature at which the polymer is depolymerized so cover a portion where the protective layer is exposed; subsequently, subjecting the substrate to a treatment at a third temperature equal to or higher than the second temperature at which the polymer as the protective layer is depolymerized; subsequently, performing a treatment which causes damage to the protected film when the protective layer is not present; and after the performing a treatment which causes damage to the protected film, depolymerizing the polymer by heating the substrate.. .

Semiconductor structure capable of improving row hammer effect in dynamic random access memory and fabrication method thereof

A semiconductor structure includes a substrate with a first conductivity type and a first doping concentration, an active area with its longitudinal axis extending along a first direction, a trench isolation structure contiguous with an end surface of the active area, a passing gate in the trench isolation structure and extending along a second direction that is not parallel with the first direction, and a localized doping region with a second conductivity type and a second doping concentration that is located on the end surface.. .

Manufacturing sample table

A manufacturing method of sample table is provided. The sample table holds a semiconductor wafer on which a plasma process is to be performed, and the manufacturing method includes: preparing an adsorption plate that has a contact surface on which a lapping process has been performed and surface-contacting the semiconductor wafer, and that adsorbs the semiconductor wafer; and preparing a supporting substrate which has a recess surface to which a noncontact surface of the adsorption plate is adhered, wherein a difference between a depth of an approximate center portion of the recess surface and a depth of a distant portion spaced apart from the approximate center portion is larger than a difference between a thickness of the adsorption plate at a portion contacting the approximate center portion and a thickness of the adsorption plate at a portion contacting the distant portion..

Pickup unit and pickup system of semiconductor device including the same

A pickup apparatus includes a plurality of pickers sliding along a first direction and a space adjuster including a plurality of space adjusting plates. Each picker includes a protruding portion combined with a picker body, and each of the space adjusting plates is between a respective pair of adjacent pickers.

Protective tape and manufacturing semiconductor device

A protective tape including an adhesive agent layer, a thermoplastic resin layer, and a matrix film layer in this order to a surface of a wafer on which a bump electrode is formed; grinding a surface of the wafer opposite to the surface on which the protective tape is pasted; pasting an adhesive tape to the ground surface of the wafer; peeling the protective tape so that the adhesive agent layer remains and other layers are removed; dicing the wafer to which the adhesive tape is pasted to obtain individual semiconductor chips; and curing the adhesive agent layer before dicing; the adhesive agent layer after curing has a shear storage modulus of 3.0e+08 pa to 5.0e+09 pa, and the ratio of the thickness of the adhesive agent layer of the protective tape before pasting to the height of the bump electrode is 1/30 to ⅙.. .

Sheet for semiconductor processing

The sheet for semiconductor processing of the present invention includes a base, an unevenness-absorbing layer provided on one surface of the base, and a pressure sensitive adhesive layer provided on the unevenness-absorbing layer, wherein the pressure sensitive adhesive layer is composed of an energy ray-curable pressure sensitive adhesive, and a stress at rupture of the pressure sensitive adhesive layer after energy ray curing is 10 mpa or more.. .

Manufacturing semiconductor device

In order to avoid cracking of a semiconductor wafer when separating the semiconductor wafer from an electrostatic chuck, there is provided a manufacturing method of a semiconductor device including a step of monitoring the potential of the electrostatic chuck from the adsorption starting state of the semiconductor wafer by the electrostatic chuck to the adsorption finishing state thereof. The above step further includes a step of determining the semiconductor wafer to be in the adsorption finishing state when the potential of the electrostatic chuck is within a predetermined range..

Humidity control in semiconductor systems

Method for forming a clean environment for semiconductor substrates with low humidity level, including the steps of measuring a humidity level in the environment using a humidity sensor to keep the environment within a predetermined interval around a humidity set point or at a humidity set point and providing a gas to the environment until the humidity level reduces to a value within the predetermined interval around the set point or to the set point.. .

Methods for inspection sampling on full patterned wafer using multiple scanning electron beam column array

A method of operating a multi-column electron beam array for quality inspection of a semiconductor wafer involves dividing the whole wafer area collectively in equally divided areas allocated to each column of the array, and assigning each of the areas as a column working space having the same dimensions and orientations. The array of column working spaces are assigned to an array of column optical axes, wherein a field of view of each column is defined as a covered region in which critical wafer patterns can be scanned by one or more columns to take an image.

Method of controlling display of operation of semiconductor manufacturing apparatus and non-transitory computer readable storage medium therefor, and system for performing display concerning operation of semiconductor manufacturing apparatus

A method is provided, the method including: repeatedly acquiring a state of one or more devices included in the semiconductor manufacturing apparatus; providing a first animation indicating an operation of the semiconductor manufacturing apparatus by displaying at least an image indicating the state of one or more devices on a display unit each time the state is acquired; storing, in a memory, the acquired state of one or more devices and a time related to the state; receiving an input for switching a display mode; and providing a second animation of the semiconductor manufacturing apparatus by displaying, one by one on the display unit, at least one or more images respectively indicating the state of one or more devices related to one or more times including a reference time stored in the memory, after receiving the input for switching a display mode.. .

Position-detecting and chip-separating device

The present invention provides a position-detecting and chip-separating device applied to a semiconductor structure that includes a base layer and a plurality of light emitting chips disposed on the base layer. The position-detecting and chip-separating device includes a position detecting module and a chip separating module.

Apparatus and manufacturing a semiconductor device

The invention relates to an apparatus for manufacturing a semiconductor device comprising a reaction chamber comprising a substrate holder for holding a substrate; and, a heater for heating the substrate. The heater may comprise a vertical cavity surface emitting laser constructed and arranged to emit a radiation beam to a substrate held by the substrate holder to heat the substrate..

Laminated member

The present invention provides a laminated member that prevents contact of a semiconductor chip and an external leading terminal etc. Without increasing the number of components.

Semiconductor device and manufacturing the same

A method of manufacturing a semiconductor device by connecting a semiconductor chip to a lead frame using a jig, the semiconductor chip including a main electrode provided at a surface of the semiconductor chip, the lead frame including a connection projecting portion and a positioning portion, the positioning portion including at least one of a convex shape and a concave shape provided around the connection projecting portion, the method may include: engaging the jig to the positioning portion in a state where a clearance is provided between the connection projecting portion and the jig; engaging the jig to the semiconductor chip; and connecting the connection projecting portion to the main electrode of the semiconductor chip via solder in a state where the jig is engaged to the positioning portion and the semiconductor chip.. .

Anisotropic etching systems and methods using a photochemically enhanced etchant

The systems and methods described herein use at least one etchant and at least one photochemically active material in conjunction with electromagnetic energy applied simultaneous with the etchant and photochemically active material during the etching process. The interaction between the electromagnetic energy and the photochemically active material preferentially increases the etch rate in a direction along the axis of incidence of the electromagnetic energy, thereby permitting the anisotropic formation of voids within the semiconductor substrate.

Polishing process for forming semiconductor device structure

A method for forming a semiconductor device structure is provided. The method includes providing a wafer over a polishing platen.

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched.

Method for manufacturing semiconductor device

The present invention provides a method for manufacturing a semiconductor device including following steps. A substrate, a hard mask layer disposed on the substrate and a first mask pattern disposed on the hard mask layer are provided, and the substrate has a device region and a cutting line region.

Metal gate and manufacturing method thereof

The present disclosure provides a semiconductor structure, including an active region with a first surface; an isolated region having a second surface, surrounding the active region, the first surface being higher than the second surface; and a metal gate having a plurality of metal layers disposed over the first surface and the second surface. A ratio of a thinnest portion and a thickest portion of at least one of the plurality of metal layers is greater than about 40%..

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device comprises: a stacking process that stacks a p-type semiconductor layer of group iii nitride containing a p-type impurity on a first n-type semiconductor layer of group iii nitride containing an n-type impurity; a p-type ion implantation process that ion-implants the p-type impurity into the p-type semiconductor layer; and a heat treatment process that performs heat treatment to activate the ion-implanted p-type impurity. The p-type ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a first p-type impurity containing region in at least part of the first n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed..

Method of manufacturing semiconductor device

A technique that recovers from degradation in crystalline nature in an ion-implanted region is provided. A method of manufacturing a semiconductor device, includes: an ion implantation step of ion-implanting p-type impurities by a cumulative dose d into an n-type semiconductor layer containing n-type impurities; and a thermal annealing step of annealing an ion-implanted region of the n-type semiconductor layer where the p-type impurities are ion-implanted, in an atmosphere containing nitrogen, at a temperature t for a time t, wherein the cumulative dose d, the temperature t, and the time t satisfy a predetermined relationship..

Semiconductor device and manufacturing thereof

A semiconductor device includes an n−-type drift layer of an formed on an n+-type sic substrate; a p-type layer provided on a surface opposite that facing the n+-type sic substrate; and an n-type buffer layer provided, as a recombination promoting layer, between the n−-type drift layer and the n+-type sic substrate, the n-type buffer layer having an impurity concentration higher than that of the n−-type drift layer. In the buffer layer, as a recombination site, a defect energy-level is introduced at a high concentration of 1×1012/cm3 or higher.

Removal of trilayer resist without damage to underlying structure

A method for semiconductor processing includes removing, from a first region of a semiconductor device, a top layer of a trilayer photoresist structure formed in the first region and a second region of the semiconductor device to expose a middle layer of the trilayer photoresist structure in the first region. The middle layer is disposed between the top layer and a bottom layer of the trilayer photoresist structure.

Forming semiconductor device by providing an amorphous silicon core with a hard mask layer

The invention relates to a method of forming a semiconductor device by patterning a substrate by providing an amorphous silicon layer on the substrate and forming a hard mask layer on the amorphous silicon layer. The amorphous silicon layer is provided with an anti-crystallization dopant to keep the layer amorphous at increased temperatures (relative to not providing the anti-crystallization dopant).

Semiconductor device and manufacturing the same

Provided herein is a method for manufacturing a semiconductor device. The method may include: forming a stack including at least one first material layer and at least one second material layer which are alternately stacked; forming first holes through which the at least one first material layer is exposed; forming etch stop patterns in the respective first holes; forming at least one slit passing through the stack; replacing the at least one first material layer with at least one third material layer through the at least one slit; and forming first contact plugs in the respective first holes, the first contact plugs passing through the etch stop patterns and coupled with the at least one third material layer..

Method of manufacturing integrated circuit device

A method of manufacturing an integrated circuit device and an integrated circuit device prepared according to the method, the method including forming a silicon oxycarbonitride (siocn) material layer on an active region of a substrate, the forming the siocn material layer including using a precursor that has a bond between a silicon (si) atom and a carbon (c) atom; etching a portion of the active region to form a recess in the active region; baking a surface of the recess at about 700° c. To about 800° c.

Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures

Methods for forming a doped metal oxide film on a substrate by cyclical deposition are provided. In some embodiments, methods may include contacting the substrate with a first reactant comprising a metal halide source, contacting the substrate with a second reactant comprising a hydrogenated source and contacting the substrate with a third reactant comprising an oxide source.

Two-step process for gapfilling high aspect ratio trenches with amorphous silicon film

Methods for gapfilling semiconductor device features, such as high aspect ratio trenches, with amorphous silicon film are provided. First, a substrate having features formed in a first surface thereof is positioned in a processing chamber.

Semiconductor device with amorphous silicon filled gaps and methods for forming

Amorphous silicon-filled gaps may be formed having no or a low occurrence of voids in the amorphous silicon fill, while maintaining a smooth exposed silicon surface. A gap in a substrate may be filled with amorphous silicon by heating the substrate to a deposition temperature between 300 and 500° c.

Production semiconductor

There is provided a method for producing a semiconductor device, the method facilitating removal of a growth substrate from a semiconductor layer. A decomposition layer formation step involves extension of a plurality of threading dislocations during growth of a decomposition layer.

Removing a residual photo-mask fence in photolithography

A first material is filled during a semiconductor fabrication process in a space bound on at least one side by a fence formation created as a result of an etching operation. A solvent-removable material is deposited such that the solvent-removable material encapsulates at least that portion of the fence formation which is protruding from the structure such that a height of the fence formation exceeds a height of the structure.

Epitaxial substrate and manufacturing the same

An epitaxial substrate and a method of manufacturing the same are provided. The epitaxial substrate includes a handle substrate, a heat dissipation layer on the handle substrate, a high-resistance silicon substrate on the heat dissipation layer, and a iii-v semiconductor layer grown on the high-resistance silicon substrate.

Method for manufacturing semiconductor device, non-transitory computer-readable recording medium, and substrate processing apparatus

By sequentially performing, a plurality of times, a step of supplying a mixed gas of an organic metal-containing source gas and an inert gas to a process chamber housing a substrate by adjusting a flow velocity of the mixed gas on the substrate to 7.8 m/s to 15.6 m/s and adjusting a partial pressure of the organic metal-containing source gas in the mixed gas to 0.167 to 0.3, a step of exhausting the process chamber, a step of supplying an oxygen-containing gas to the process chamber, and a step of exhausting the process chamber, a metal oxide film is formed on the substrate.. .

Process of depositing silicon nitride (sin) film on nitride semiconductor

A process of forming a silicon nitride film on a nitride semiconductor layer as a passivation film is disclosed. The process first set a temperature lower than 500° c.

Apparatus and electrodeposition of metals with the use of an ionically resistive ionically permeable element having spatially tailored resistivity

An apparatus for electroplating metal on a semiconductor substrate with improved plating uniformity includes in one aspect: a plating chamber configured to contain an electrolyte and an anode; a substrate holder configured to hold the semiconductor substrate; and an ionically resistive ionically permeable element comprising a substantially planar substrate-facing surface and an opposing surface, wherein the element allows for flow of ionic current towards the substrate during electroplating, and wherein the element comprises a region having varied local resistivity. In one example the resistivity of the element is varied by varying the thickness of the element.

Semiconductor-free vacuum field effect transistor fabrication and 3d vacuum field effect transistor arrays

A vacuum field-emission-transistor device, a drain comprised of either a metal or a semimetal material, a gate arranged adjacent to, but separated from, the drain, a source comprised of either a metal or a semimetal material adjacent to, but separated from the metal gate, and a void through the metal drain and the metal gate to expose the drain, wherein the distance between the drain and the source is shorter than a mean free path distance of electrons in air.. .

Magnetic material and preparation method thereof

A method of preparing a mnb-based magnetic material, the method including the steps of preparing a mixture including manganese oxide and boron, and heat-treating the mixture under an inert atmosphere, a mnb-based magnetic material prepared thereby, and a material absorbing or shielding electromagnetic waves, or a semiconductor, electronic, communication, or display device including the mnb-based magnetic material, are provided.. .

Semiconductor memory device and testing semiconductor memory device

A semiconductor memory device includes: a memory cell including a first cell that stores data, and a second cell that stores complementary data that is complementary to the data; a redundant memory cell including a third cell that stores margined complementary data in which a margin is added to the complementary data, and a fourth cell that stores margined data in which a margin is added to the data; and a controller that causes the data and the margined complementary data to be compared and a test of the first cell to be executed, and the complementary data and the margined data to be compared and a test of the second cell to be executed.. .

Semiconductor memory apparatus and test method thereof

A semiconductor memory apparatus includes a comparison circuit generating a detection code in response to stored data and expected data, a counting circuit generating a counting code in response to the detection code, a selection code output circuit outputting one of a plurality of expected codes as a selection code in response to a selection signal, and a plurality of signal storage circuits. A comparison result output circuit including a plurality of signal storage circuits which stores a comparison result of a comparison between the counting code and the selection code in one signal storage circuit among the plurality of signal storage circuits according to the selection signal, and a value stored in one signal storage circuit among the plurality of signal storage circuits is output as a result signal in response to an output enable signal..

System and generating random numbers based on non-volatile memory cell array entropy

A memory device that generates a unique identifying number, and includes a plurality of memory cells and a controller. Each of the memory cells includes first and second regions formed in a semiconductor substrate, wherein a channel region of the substrate extends between the first and second regions, a floating gate disposed over and insulated from a first portion of the channel region, and a select gate disposed over and insulated from a second portion of the channel region.

Semiconductor memory device

A semiconductor memory device including a memory cell having a plurality of memory cells, a first p-type well region, a second p-type well region, and an n-type well region disposed between the first p-type well region and the second p-type well region. The semiconductor memory element defines a plurality of first regions and a plurality of second regions, each of the first regions and each of the second regions including one of the memory cells, each of the second regions further includes at least two first voltage providing contacts, and at least one second voltage providing contact, wherein the first voltage providing contacts and the second voltage providing contact are not located within each first region..

Semiconductor device and timing calibration method

When the same processing as initial training is executed to cope with fluctuation in the timing of a signal, the performance of a semiconductor device utilizing the relevant memory is degraded. A delay adjustment circuit adjusts a delay amount of write data to a memory device.

Semiconductor device and control method thereof

A semiconductor device includes a connector configured for connection to a host, a power circuit supplied with a first voltage from the host via the connector, the power circuit including first and second channels configured to generate second and third voltages, respectively, from the first voltage, a semiconductor memory supplied with the second voltage via the first channel, and a controller for the semiconductor memory, supplied with the third voltage via the second channel. When the first voltage is less than a first threshold, the power circuit turns off the first channel and the second channel..

Semiconductor device and electronic appliance

The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output.

Semiconductor device

A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals.

Semiconductor device

In order to provide a 1h-magnitude neuro-semiconductor device, a semiconductor device that constitutes a neural network in which a plurality of sets each including a plurality of synapse bonds and a neuron section are connected with each other. The semiconductor device includes the synapse bonds that perform non-contact communications using magnetic coupling, and the neuron sections including a wired connection and a logical circuit.

Semiconductor device, non-contact electronic device, and period detection method

A semiconductor device, a non-contact electronic device, and a period detection method are provided. The semiconductor device includes an edge detection unit that detects edges of one of rises and falls of a data signal received via radio waves, a counting unit that counts a number of n-divided clock signals having a frequency which is 1/n (n is an integer equal to or greater than 2) of a frequency of a reference clock signal having a predetermined frequency according to the data signal in a section of the adjacent edges, a fraction counting unit that counts fractions of the n-divided clock signals determined according to a phase difference between the edge and the n-divided clock signal, and a first addition unit that adds a value obtained by multiplying the counted number by n to the fractions, and outputs a resultant value as a period of the data signal..

Method to synthesize a cross bar switch in a highly congested environment

A facility is provided for automatically generating design data for a semiconductor circuit including a crossbar switch. The method includes synthesizing the crossbar switch using predefined multiplexer building blocks, where the predefined multiplexer building blocks include at least a multiplexer, an input driver and a select driver.

Semiconductor device

A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (roi) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor..

Memory system, memory management method and semiconductor device

A memory system of the present invention has a controller which, for each of a plurality of management groups each including k pieces of blocks (k is an integer equal to two or greater), produces physical block information correspondingly indicating state information indicative of no good when a no-good block is present within the management group. For each management group associated with the state information indicative of no good, the controller employs, as a reuse block, a block other than the no-good block among the k pieces of the blocks included in the management group, and when the total number of the reuse blocks is k, sets the k pieces of the reuse blocks as a new management group..

Semiconductor device and controlling semiconductor device

A semiconductor device includes a connector connectable to a host, a power supply circuit which includes an input portion that receives first power from the host via the connector, an output portion, and a switch that is connected to the input portion and the output portion and controls whether to supply the first power to the output portion, the power supply circuit generating second power and third power from the first power, a semiconductor memory which receives the second power from the output portion, and a controller which receives the third power from the output portion and controls the semiconductor memory. The power supply circuit turns off the switch and stops supply of power to the semiconductor memory and the controller when the second power exceeds a first value or when the third power exceeds a second value..

Current reference circuit and semiconductor integrated circuit including the same

A current reference circuit and a semiconductor ic including the current reference circuit, the current reference circuit including a proportional to absolute temperature (ptat) current generator configured to generate, in an output branch, a first current proportional to a temperature; and a current subtractor configured to generate a reference current by subtracting a second current generated based on a current flowing in an internal branch of the ptat current generator, from the first current flowing in the output branch. The second current is set to have a same temperature-based change characteristic as the first current and a level different from a level of the first current..

Metrology a semiconductor manufacturing process

A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features.

Display substrate

A display substrate includes a base substrate, a gate electrode, a semiconductor layer, a source electrode, a drain electrode, a first black organic layer, a data line and a pixel electrode. The gate electrode is disposed on the base substrate.

Substrate structure and manufacturing substrate structure

A display substrate includes a base substrate, a gate metal pattern, a semiconductor layer, and a data metal pattern. The base substrate includes a display area and a peripheral area.

Pixel array substrate

A pixel array substrate including a plurality of pixel units disposed on a substrate is provided. Each of the pixel units includes a scan line, a data line and an active element.

Liquid crystal display device and touch panel

To provide a highly reliable liquid crystal display device including flexible substrates and a crystalline oxide semiconductor film for a backplane. The device includes a flexible first substrate, a flexible second substrate facing the first substrate, and a liquid crystal layer sealed between the substrates with a sealing member.

Multi-function semiconductor and electronics processing

A method of tailoring beam characteristics of a laser beam during fabrication of an electronic device. The method includes: providing a substrate comprising one or more layers; adjusting one or more characteristics of a laser beam; and impinging the laser beam having the adjusted beam characteristics on the substrate to carry out at least one process step for fabricating the electronic device.

Photonic integrated circuit having a relative polarization-rotating splitter/combiner

A photonic integrated circuit (pic) having two tapered planar waveguide cores that are separated from one another by a relatively narrow gap, with each of these waveguide cores having a respective portion thereof located on a tapered planar slab core. The relative positions of the slab core and the two waveguide cores are such that the light crossing between the two waveguide cores undergoes a polarization rotation between the tm and te polarizations with a relatively low insertion loss.

Optical material, optical element and manufacturing same

An optical member to be arranged in an optical path of a light, includes an optical medium made of an insulator or a semiconductor; a first element provided at a first position in the optical medium and made of a first electric conductor having a width approximately same as or smaller than a wavelength of the light, the first position being a position in the optical path; and a second element provided at a second position, in the optical medium, different from the first position, and made of a second electric conductor having a width approximately same as or smaller than the wavelength of the light, the second position being a position in the optical path.. .

Electronic device

An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.. .

Multi-chip package with selection logic and debug ports for testing inter-chip communications

A microelectronic package has an ic chip that includes logical circuitry for routing certain i/o signals to debug ports disposed on an outer surface of the microelectronic package. The i/o signals include data and command signals that are transmitted between semiconductor chips in the microelectronic package via conductive traces that are not physically accessible via with conventional debugging techniques.

Monitoring circuit and semiconductor device

Provided is a monitoring circuit for a system including an ldo regulator. The monitoring circuit includes: a non-saturation detection circuit configured to detect a non-saturation state of an output transistor of the ldo regulator configured to supply a power supply voltage to an mpu; a current detection circuit configured to detect that an output current from the output transistor is equal to or more than a predetermined current value; and a watchdog timer configured to monitor operation of the mpu.

Device for attaching a semiconductor device to a circuit board

A device used for attaching a semiconductor device to a circuit board over a first temperature. The device includes a hook member that includes a first hook, a second hook, and a body between the first hook and the second hook.

Optoelectronic device for the selective detection of volatile organic compounds and related manufacturing process

An optoelectronic device for detecting volatile organic compounds is described, including a die with a semiconductor body, the die forming a mosfet transistor and at least one photodiode. The optoelectronic device is optically couplable to an optical source that emits radiation with a spectrum at least partially overlapping the absorption spectrum range of the semiconductor body.

Gas sensor

A sensor element includes a sensor fet provided in a main surface of a semiconductor substrate, a cavity provided in the sensor fet and into which a detection target gas is introduced, and an ion pump provided over the cavity. By laminating the ion pump over the sensor fet via the cavity, a part of a front surface of a gate layer is exposed to the cavity, and a part of a lower surface of an ion pump electrode is exposed to the cavity.

Apparatus and method to measure temperature of 3d semiconductor structures via laser diffraction

Embodiments of the present invention generally relate to apparatus for and methods of measuring and monitoring the temperature of a substrate having a 3d feature thereon. The apparatus include a light source for irradiating a substrate having a 3d feature thereon, a focus lens for gathering and focusing reflected light, and an emissometer for detecting the emissivity of the focused reflected light.

Laminated core type heat sink

Thickness t2 of a second plate 4b positioned on the second in the lamination direction from an end lid 9 to which a semiconductor is attached is made greater than thickness t1 of a first plate 4a other than the second plate 4b.. .

Method for improved semiconductor processing equipment tool pedestal / pad vibration isolation and reduction

A method to improve vibration isolation in semiconductor process level inhibits vibration frequencies transmitted through building structure from production tools, pumps, compressors, chillers, ahus (air handling units), and footfalls traffic on raised floor system on to tool pedestals and pads from affecting semiconductor fabrication processes. Rapid advancement and technological evolution in semiconductor industry foresee the imminent requirements for decrease in semiconductor chip node sizes to single digit nanometer.

Process for developing a subterranean formation by injection of a fluid comprising an additive labelled with a luminescent semiconducting nanocrystal

The present invention concerns a process for developing a subterranean formation, in which at least one fluid is injected. In accordance with the invention, the fluid comprises at least one additive, the additive being labelled with at least one luminescent semiconductor nanocrystal (fluorescent or phosphorescent).

Method for producing a semiconductor wafer with epitaxial layer in a deposition chamber, producing a semiconductor wafer with epitaxial layer, and semiconductor wafer with epitaxial layer

Unloading the deposition chamber by contacting the susceptor and transporting the susceptor and a semiconductor wafer with epitaxial layer, the semiconductor wafer having been produced in the course of depositing the epitaxial layer and lying on the susceptor, from the deposition chamber into the load lock chamber.. .

Copper sulfate, copper sulfate solution, plating solution, producing copper sulfate, producing semiconductor circuit board, and producing electronic apparatus

Copper sulfate which includes an al with a concentration of 0.08 ppm by mass or less.. .

Assembly of gas injector and ceiling for semiconductor processes and film deposition

An assembly of a gas injector and a ceiling is used in a film deposition apparatus for semiconductor processes. The assembly comprises a gas injector and a ceiling.

Carbon nanotube single-photon source

An atom, molecule, atomic layer molecular layer is adhered to a carb-nnanotube surface, or the surface is doped with the atom, molecule, atomic layer, or molecular layer, to form a deep localized level so that an exciton is localized. Alternatively, an atom, molecule, inorganic or organic substance of an atomic or molecular layer, a metal, a semiconductor, or an insulator is absorbed to, deposited on, or encapsulated in the carbon tube inside surface to make permittivity of the portion undergoing the absorption, deposition, or encapsulation higher than that of a clean portion free of the absorption, deposition, or encapsulation so that binding energy of the exciton in the clean portion is high, or reduce a band gap of the portion undergoing the absorption, deposition, or encapsulation so that the exciton is confined and localized in the clean portion or the position undergoing the absorption, deposition, or encapsulation..

Fullerene derivative and n-type semiconductor material

Wherein r1 represents aryl optionally substituted with at least one substituent, r2 represents an organic group, r3 represents an organic group, with the proviso that at least one of r2 and r3 is alkyl optionally substituted with at least one substituent or alkyl ether optionally substituted with at least one substituent, r4 represents hydrogen or an organic group, and a ring a represents a fullerene ring.. .

Bare optical fiber manufacturing method and ultraviolet irradiation device

A bare optical fiber manufacturing method includes applying an ultraviolet curable resin applied around an optical fiber; and irradiating the ultraviolet curable resin with ultraviolet light emitted from semiconductor ultraviolet light emitting elements, by use of an ultraviolet irradiation device having plural ultraviolet irradiation units each having plural positions where the ultraviolet light is emitted toward the ultraviolet curable resin, the plural positions being arranged on the same circle, the plural ultraviolet irradiation units being arranged in a traveling direction of the optical fiber such that the optical fiber passes centers of the circles, at least two of the plural ultraviolet irradiation units being differently arranged with respect to circumferential direction angles thereof around an axis that is the traveling direction of the optical fiber.. .

Method for manufacturing a micro electro-mechanical system

A method of fabricating a semiconductor device, includes, in part, growing a first layer of oxide on a surface of a first semiconductor substrate, forming a layer of insulating material on the oxide layer, patterning and etching the insulating material and the first oxide layer to form a multitude of oxide-insulator structures and further to expose the surface of the semiconductor substrate, growing a second layer of oxide in the exposed surface of the semiconductor substrate, and removing the second layer of oxide thereby to form a cavity in which a mems device is formed. The process of growing oxide in the exposed surface of the cavity and removing this oxide may be repeated until the cavity depth reaches a predefined value.

Eutectic bonding with alge

A mems device formed in a first semiconductor substrate is sealed using a second semiconductor substrate. To achieve this, an aluminum germanium structure is formed above the first substrate, and a polysilicon layer is formed above the second substrate.

Mems device including a capacitive pressure sensor and manufacturing process thereof

Mems device, in which a body made of semiconductor material contains a chamber, and a first column inside the chamber. A cap of semiconductor material is attached to the body and forms a first membrane, a first cavity and a first channel.

Vehicle

A vehicle includes a motor housing accommodating motors for driving wheels, and a power control unit fixed on the motor housing. The power control unit includes: a stacked unit in which multiple power modules accommodating power semiconductor elements for electric power conversion and multiple coolers are stacked; and reactors.

System with a high-voltage battery and a coupling device, motor vehicle, and operating a coupling device

A system with a high-voltage battery and a coupling device that couples the high-voltage battery to a high-voltage onboard power supply system of a motor vehicle. The coupling device couples a positive pole and a negative pole with corresponding phases of the high-voltage power supply system.

Liquid discharge head and liquid discharge apparatus including the same

A liquid discharge head is provided. The liquid discharge head includes: a semiconductor substrate including a first pressure chamber; an insulating film disposed above the semiconductor substrate; a first piezoelectric element disposed on an opposite side to the first pressure chamber of the insulating film and having a piezoelectric layer and a first and second electrode; and a doped layer formed in the semiconductor substrate.

Fluid ejection device, printhead, printer, and manufacturing the ejection device

Ejection device for fluid, comprising a solid body including: first semiconductor body including a chamber for containing the fluid, an ejection nozzle in fluid connection with the chamber, and an actuator operatively connected to the chamber to generate, in use, one or more pressure waves in the fluid such as to cause ejection of the fluid from the ejection nozzle; and a second semiconductor body including a channel for feeding the fluid to the chamber, coupled to the first semiconductor body, in such a way that the channel is in fluid connection with the chamber. The second semiconductor body integrates a damping cavity over which extends a damping membrane, the damping cavity and the damping membrane extending laterally to the channel for feeding the fluid..

Semiconductor apparatus, liquid discharge head substrate, liquid discharge head, and liquid discharge apparatus

An apparatus includes a substrate, a transistor provided on the substrate and connected to a first terminal supplied with a first voltage, an anti-fuse element provided on the substrate and connected between the transistor and a second terminal supplied with a second voltage, a first resistive element provided on the substrate and connected in parallel to the anti-fuse element and between the transistor and the second terminal, and an adjusting unit provided on the substrate and configured to function so as to reduce an influence of variation in resistance of the first resistive element in reading out of information from the anti-fuse element.. .

Laminate film for temporary bonding, methods for producing substrate workpiece and laminate substrate workpiece using the laminate film for temporary bonding, and producing semiconductor device using the same

The present invention provides a laminate film for temporary bonding which is excellent in heat resistance, capable of providing a flat film even at the periphery of a substrate, and capable of making a semiconductor circuit formation substrate and a support substrate or a support film layer adhere to each other with one type of adhesive, and which can be peeled off at room temperature under mild conditions. The present invention provides a laminate film for temporary bonding, including at least three layers of (a) a protective film layer, (b) an adhesive layer, and (c) a support film layer, wherein the adhesive layer (b) contains at least a siloxane polymer represented by a specific general formula or a compound represented by a specific general formula..

Manufacturing semiconductor device

A manufacturing method of a semiconductor device includes the steps of: preparing a lead frame; mounting a plurality of semiconductor chips on the lead frame; and sealing one portion of the lead frame with a sealing resin. The resin-sealing step includes the step of: disposing the lead frame, molds having main surfaces on which cavity parts are formed, the lead frame being disposed on the main surface of the heated molds; injecting a resin in the main surfaces of the heated molds so as to seal the one portion of the lead frame with the sealing resin; and taking out the lead frame from the heated molds.

Aluminum-diamond-based composite and producing same

The present invention provides an aluminum-diamond composite which combines high thermal conductivity and a coefficient of thermal expansion close to a semiconductor clement, and in which the difference between the thicknesses of both surfaces is reduced so as to be suitable for use as a heat sink etc. For a semiconductor element.

Chemical mechanical polishing pad

The present invention provides methods of cmp polishing a metal surface, such as a copper or tungsten containing metal surface in a semiconductor wafer, the methods comprising cmp polishing the substrate with a cmp polishing pad that has a top polishing surface in a polishing layer which is the reaction product of an isocyanate terminated urethane prepolymer and a curative component comprising a polyol curative having a number average molecular weight of 6000 to 15,000, and having an average of 5 to 7 hydroxyl groups per molecule and a polyfunctional aromatic amine curative, wherein the polishing layer would if unfilled have a water uptake of 4 to 8 wt. % after one week of soaking in deionized (di) water at room temperature.

Soldering material, solder joint, and inspecting soldering material

The present invention accurately distinguishes a soldering material less likely to oxidize. A cu core ball has a cu ball having a predetermined size, and a solder layer coating the cu ball.

Acid purifier

An acid purifier, comprising: a container (1) for an acid to be purified; a heater (2); a condenser (3) including a peltier semiconductor cooler, a condenser body (600) and a refrigerant temperature sensor; a purified acid liquid collection bottle (4) connected with the condenser; a controller; an integrated liquid level control component (300) for the acid to be purified, connected with the container (1) for the acid to be purified, and arranged in such a way that a liquid level pipe (320), a liquid adding funnel (310) and a waste liquid discharge valve (330) are integrated; and an acid liquid temperature sensor (400, 500) arranged in the acid to be purified.. .

Mitsubishi Chemical Corporation

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Toshiba Memory Corporation

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Renesas Electronics Corporation

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Air Water Inc.

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Semiconductor device

According to embodiments, a semiconductor device includes a first switching element in which a first reference voltage is input to a gate; a second switching element in which a first voltage is input to a gate; a third switching element to which the first switching element is in darlington connection; a fourth switching element to which the second switching element is in darlington connection; a first current mirror circuit to regulate currents flowing in the third and fourth switching elements; a fifth switching element switched between on and off states based on a difference between the first reference and the first voltages; a constant current circuit; a second current mirror circuit; and a voltage setting resistance element between a source of the first switching element and a gate of the third switching element or between a source of the second switching element and a gate of the fourth switching element.. .
Kabushiki Kaisha Toshiba

Laterally grown edge emitting laser

A laterally grown edge emitting laser is provided. A semiconductor structure is disposed on a substrate.
International Business Machines Corporation

Surface-emitting semiconductor laser

A surface-emitting semiconductor laser includes a stacked semiconductor layer on a substrate; and a post including a current constriction structure including an oxide portion and a semiconductor portion, and an active layer. The post includes a peripheral portion and first to fourth portions.
Sumitomo Electric Industries, Ltd.

Submount, optical transmitter module, optical module, optical transmission equipment, and control method therefor

A submount which has a mounting surface on which three or more semiconductor lasers are arranged in a first direction, and includes a heat generator configured to increase the temperatures of the three or more semiconductor lasers, in which, where the heat generator generates heat, a first heat of the heat absorbed by a first semiconductor laser of the three or more semiconductor lasers disposed at one end along the first direction is larger than a second heat of the heat absorbed by a second semiconductor laser of the three or more semiconductor lasers disposed to be adjacent to the first semiconductor laser on the mounting surface.. .
Oclaro Japan, Inc.

Optical transmitter module, optical module, optical transmission equipment and manufacturing thereof

An optical transmitter module includes optical semiconductor devices including a first optical semiconductor device, a temperature adjustment means for collectively performing temperature adjustment on the optical semiconductor devices, and a first thermal resistor that is disposed between the first optical semiconductor device and the temperature adjustment means, in which, when the temperature adjustment means is driven, the temperature of the first optical semiconductor device is higher than temperatures of other optical semiconductor devices which are different from the first optical semiconductor device.. .
Oclaro Japan, Inc.

Semiconductor laser device

Disclosed herein is a semiconductor laser device utilizing a sub-mount substrate that is capable of having a further sufficient heat dissipation property. The semiconductor laser device comprises: a monocrystalline sub-mount substrate having a crystalline structure including a first crystalline plane (c-plane) having a normal line direction on a first crystalline axis (c-axis) and a second crystalline plane (a-plane) having a normal line direction on a second crystalline axis (a-axis) having a higher thermal conductivity than the first crystalline axis; and a semiconductor laser chip configured to be joined to a side of a first surface of the sub-mount substrate.
Ushio Opto Semiconductors, Inc.

Semiconductor laser device

Disclosed herein is a semiconductor laser device utilizing a monocrystalline sic substrate that is capable of assuring a sufficient heat dissipation property. The semiconductor laser device comprises: a monocrystalline sic substrate having an electrical conductivity, the substrate having a first surface and a second surface; and a semiconductor laser chip (ld chip) arranged on the first surface.
Ushio Opto Semiconductors, Inc.

Optical subassembly, optical module, and optical transmission equipment

To provide an optical subassembly, an optical module, and an optical transmission equipment including simpler components. A first component with an optical semiconductor device mounted thereon that dissipates heat generated by the optical semiconductor device to outside, a second component in contact with the first component to form a box type housing, and a receptacle terminal that optically joined to the optical semiconductor device are provided, wherein the second component includes a window structure for transmitting light transmitted between the optical semiconductor device and the receptacle terminal, and the receptacle terminal is fused and fixed to the outside of the window structure..
Oclaro Japan, Inc.

Laser diode module

A laser diode module is described herein. In accordance with a first exemplary embodiment, the laser diode module includes a first semiconductor die including at least one electronic switch, and a second semiconductor die including at least one laser diode.
Infineon Technologies Ag

Radiation detector

According to one embodiment, a radiation detector includes a first conductive layer, a second conductive layer, and an intermediate layer. The intermediate layer is provided between the first conductive layer and the second conductive layer.
Kabushiki Kaisha Toshiba

Method for producing vapor deposition mask, and producing organic semiconductor element

A method for producing a vapor deposition mask capable of satisfying both enhancement in definition and reduction in weight even when a size is increased, and a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition are provided. A vapor deposition mask is produced by the steps of preparing a metal plate with a resin layer in which a resin layer is provided on one surface of a metal plate, forming a metal mask with a resin layer by forming a slit that penetrates through only the metal plate, for the metal plate in the metal plate with a resin layer, and thereafter, forming a resin mask by forming openings corresponding to a pattern to be produced by vapor deposition in a plurality of rows lengthwise and crosswise in the resin layer by emitting a laser from the metal mask side..
Dai Nippon Printing Co., Ltd.

Method of forming a layer and a fabricating a variable resistance memory device using the same

A method of forming a target layer in semiconductor fabrication is disclosed that includes steps of forming a first layer by performing a first process at least one time and forming a second layer by performing a second process at least one time, wherein the first process may include supplying a first source gas, supplying a second source gas several times, and supplying an inert gas several times.. .
Samsung Electronics Co., Ltd.

Semiconductor memory device and manufacturing same

A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including(a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon..
Toshiba Memory Corporation

Nand-type finfet dielectric rram

A semiconductor device includes one or more bit lines, first and second select gates on the one or more bit lines, a plurality of word lines on the one or more bit lines and between the first and second select gates, and a source and a plurality of drains on the one or more bit lines. The source is disposed at an outside of the first select gate, and the plurality of drains are disposed at an outside of the second select gate.
Semiconductor Manufacturing International (beijing) Corporation

Memory device

A memory device includes a first conductive layer, a second conductive layer, and a variable resistance layer provided between the first and second conductive layers. The variable resistance layer includes a first layer having a semiconductor or a first metal oxide containing a first metal, and a second layer provided between the first layer and the second conductive layer, having a second metal oxide containing a second metal, and having crystal grains that are not in contact with at least one of an end face of the second layer on a side of the first conductive layer or an end face of the second layer on a side of the second conductive layer..
Toshiba Memory Corporation

Semiconductor devices with magnetic and attracter materials and methods of fabrication

A magnetic cell includes an attracter material proximate to a magnetic region (e.g., a free region). The attracter material is formulated to have a higher chemical affinity for a diffusible species of a magnetic material, from which the magnetic region is formed, compared to a chemical affinity between the diffusible species and at least another species of the magnetic material.
Micron Technology, Inc.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes the following configuration. A resistance change element has first, second and third magnetic layers and a non-magnetic layer disposed between the first and second magnetic layers, and a metal layer disposed between the second and third magnetic layers.
Toshiba Memory Corporation

Semiconductor light emitting device

A semiconductor light emitting device includes a substrate made of resin, a first wiring and a second wiring formed on the substrate, a light emitting element disposed on the substrate and electrically connected to the first wiring and the second wiring, and a transparent sealing resin configured to seal the light emitting element. The substrate contains an acrylic resin, and the sealing resin contains silicon..
Rohm Co., Ltd.

Nitride semiconductor ultraviolet light emitting device and manufacturing same

A nitride semiconductor ultraviolet light emitting device 1 is configured such that a nitride semiconductor ultraviolet light emitting element 10 is mounted on a base 30 by flip-chip mounting and sealed with an amorphous fluororesin whose terminal functional group is perfluoroalkyl group. The nitride semiconductor ultraviolet light emitting element 10 includes a sapphire substrate 11, a semiconductor laminated portion 12 of an algan-based semiconductor laminated on a front surface of the sapphire substrate 11, an n electrode 13, a p electrode 14 and a back surface covering layer 15 which is formed on a back surface of the sapphire substrate 11 and transmits ultraviolet light.
Asahi Glass Company, Limited

Light-emitting device package and light-emitting apparatus comprising same

A light-emitting device package of embodiments comprises: a substrate; a light-emitting structure which is arranged below the substrate and comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; a first electrode which is connected to the first conductive type semiconductor layer; a first insulation layer which is arranged on the side section of the light-emitting structure and the side and lower sections of the first electrode; a first pad which passes through the first insulation layer and is connected to the first conductive type semiconductor layer; a second electrode which passes through the first insulation layer, the first conductive type semiconductor layer and the active layer and is connected to the second conductive type semiconductor layer; a second pad which is connected to the second electrode; and a protective layer which extends from the top of the first insulation layer arranged on the side section of the light-emitting structure to the top of the first insulation layer arranged on the top of the first electrode, and is arranged so as to cover a bent part of the first insulation layer.. .
Lg Innotek Co., Ltd.

Optoelectronic device and manufacturing same

An optoelectronic device including first and second active regions suitable for emitting or detecting electromagnetic radiation and containing a first semiconductor material that predominantly contains a first compound selected from compounds iii-v, compounds ii-vi, and mixtures of same. The first active regions have a first polarity, and the second active regions have a second polarity different from the first polarity.
Centre National De La Recherche Scientifique

Semiconductor light emitting element and manufacturing semiconductor light emitting element

A semiconductor light emitting element includes: an n-type clad layer formed of an n-type aluminum gallium nitride (algan) based semiconductor material; an intermediate layer provided on the n-type clad layer and having a higher oxygen (o) concentration than the n-type clad layer; an active layer provided on the intermediate layer and formed of an algan-based semiconductor material; and a p-type semiconductor layer provided on the active layer. The intermediate layer may contain at least oxygen (o) and aluminum (al)..
Nikkiso Co., Ltd.

Color light source structure

The present invention discloses a color light source structure, which comprises at least one light source and a semiconductor substrate. The at least one light source is located on the semiconductor substrate.
Sitronix Technology Corp.

Method and device for passivating defects in semiconductor substrates

The invention relates to methods and an apparatus for passivating defects of a semiconductor substrate, in particular a silicon based solar cell. According to the method, the substrate is irradiated with electromagnetic radiation during a first process phase, wherein the radiation directed onto the substrate has wavelengths at least in the region below 1200 nm and an intensity of at least 8000 watt/m2.
Centrotherm International Ag

Fabrication and use of large-grain templates for epitaxial deposition of semiconductor materials

Methods for growing and using large-grain templates are provided. According to an aspect of the invention, a method includes depositing a small-grain layer of a semiconductor material; treating the small-grain layer such that the small-grain layer becomes a large-grain layer; and growing an epitaxial layer of the semiconductor material on the large-grain layer.
Alliance For Sustainable Energy, Llc

Group-iv solar cell structure using group-iv or iii-v heterostructures

Device structures, apparatuses, and methods are disclosed for photovoltaic cells that may be a single-junction or multijunction solar cells, with at least a first layer comprising a group-iv semiconductor in which part of the cell comprises a second layer comprising a iii-v semiconductor or group-iv semiconductor having a different composition than the group-iv semiconductor of the first layer, such that a heterostructure is formed between the first and second layers.. .
The Boeing Company

Method of manufacturing of a solar cell and solar cell thus obtained

The method of manufacturing of a solar cell comprises the steps of: providing a semiconductor substrate (100) comprising an electrically conductive region (11) extending at a first side thereof; and providing a tunnelling oxide (13) by thermal oxidation followed by a boron doped polysilicon lpcvd deposited layer on the second side of the semiconductor substrate. Herein, the provision of the doped polysilicon layer (20) comprises depositing a multilayer stack of first sublayers (21, 22, 23) of silicon and second sublayers (31, 32) of boron dopant in alternation, and subsequent annealing.
Tempress Ip B.v.

Photodetector with reduced dark current

The photodetector includes a photon absorbing region formed by a first semiconductor material having a first bandgap energy value. It also includes a blocking region formed by at least second and third semiconductor materials configured to prevent the majority charge carriers from passing between the photon absorbing region and a contact region, the second semiconductor material presenting a second bandgap energy value higher than the first bandgap energy value to form a quantum well with the third semiconductor material.
SociÉtÉ FranÇaise De DÉtecteurs Infrarouges - Sofradir

Solar cell and manufacturing the same

A solar cell can include a silicon semiconductor substrate having a first conductive type; a oxide layer on a first surface of the silicon semiconductor substrate; a polysilicon layer on the oxide layer and having the first conductive type; an emitter region at a second surface of the silicon semiconductor substrate opposite to the first surface and having a second conductive type opposite to the first conductive type; a first passivation film on the polysilicon layer; a first electrode connected to the polysilicon layer through an opening formed in the first passivation film; a second passivation film on the emitter region; and a second electrode connected to the emitter region through an opening formed in the second passivation film.. .
Lg Electronics Inc.

Semiconductor device including an ultraviolet light receiving element and manufacturing the same

First and second semiconductor light receiving elements each include: a first p-type semiconductor region which is formed in an n-type semiconductor substrate; a first n-type semiconductor layer region which is formed in the first p-type semiconductor region; a p-type semiconductor region having a high concentration which is formed in the first p-type semiconductor region; and an n-type semiconductor region having a high concentration which is formed in the first n-type semiconductor layer region. On the semiconductor substrate, insulating oxide films are formed.
Ablic Inc.

Iii-v semiconductor diode

A stacked iii-v semiconductor diode that has an n+ layer having a dopant concentration of at least 1019 n/cm3, an n− layer having a dopant concentration of 1012 n/cm3 to 1016 n/cm3, a layer thickness of 10 μm to 300 μm, a p+ layer having a dopant concentration of 5·1018 n/cm3 to 5·1020 cm3 and a layer thickness greater than 2 μm, the layers following each other in the specified order, each including a gaas compound or being made from a gaas compound and having a monolithic design, the n+ layer or the p+ layer being a substrate, and a lower side of the n− layer being integrally connected to an upper side of the n+ layer. The stacked iii-v semiconductor diode including a first defect layer having a layer thickness greater than 0.5 μm, the defect layer being situated within the n− layer..
3-5 Power Electronics Gmbh

Iii-v semiconductor diode

A stacked iii-v semiconductor diode having an n+-layer with a dopant concentration of at least 1019 n/cm3, an n−-layer with a dopant concentration of 1012-1016 n/cm3, a layer thickness of 10-300 microns, a p+-layer with a dopant concentration of 5×1018-5×1020 cm3, with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a gaas compound. The n+-layer or the p+-layer is formed as the substrate and a lower side of the n−-layer is materially bonded with an upper side of the n+-layer, and a doped intermediate layer is arranged between the n−-layer and the p+-layer and materially bonded with an upper side and a lower side..
3-5 Power Electronics Gmbh

Thin film transistor and manufacturing the same, array substrate and display device

A method for manufacturing a thin film transistor includes: providing a substrate having a first surface and a second surface which are opposed to each other; forming a metal layer on the first surface of the substrate and patterning the metal layer to form a source electrode and a drain electrode; forming a semiconductor layer on the metal layer; forming a first insulating area and a gate electrode on the semiconductor layer; forming a second insulating layer on the semiconductor layer and the gate electrode; and forming a source lead and a drain lead on the second insulating layer, wherein the source lead passes through the second insulating layer and the semiconductor layer and is coupled to the source electrode, and the drain lead passes through the second insulating layer and the semiconductor layer and is coupled to the drain electrode.. .
Boe Technology Group Co., Ltd.

Nanowire semiconductor device having high-quality epitaxial layer and manufacturing the same

A nanowire semiconductor device having a high-quality epitaxial layer. The semiconductor device may include: a substrate; one or more nanowires spaced apart from the substrate, wherein the nanowires each extend along a curved longitudinal extending direction; and one or more semiconductor layers formed around peripheries of the respective nanowires to at least partially surround the respective nanowires, wherein the respective semiconductor layers around the respective nanowires are spaced apart from each other..
Institute Of Microelectronics, Chinese Academy Of Sciences

Finfets and methods of forming finfets

An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.. .
Taiwan Semiconductor Manufacturing Company, Ltd.

Complementary metal oxide semiconductor device and forming the same

A method for forming a complementary metal oxide semiconductor device is disclosed. First, a substrate having a first device region and a second device region is provided.
United Microelectronics Corp.

Semiconductor structure

A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (ldd) region. The first semiconductor fin is disposed on the substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Vertical field effect transistor with improved reliability

Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes forming a semiconductor fin on a source/drain region, forming a liner including a first dielectric material along sidewalls of the semiconductor fin and along sidewalls of the source/drain region, forming a second dielectric material along sidewalls of the liner including the first dielectric material, and removing the liner including the first dielectric material from sidewalls of the semiconductor fin.
International Business Machines Corporation

Vertical field effect transistor with improved reliability

Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes forming a semiconductor fin on a source/drain region, forming a liner including a first dielectric material along sidewalls of the semiconductor fin and along sidewalls of the source/drain region, forming a second dielectric material along sidewalls of the liner including the first dielectric material, and removing the liner including the first dielectric material from sidewalls of the semiconductor fin.
International Business Machines Corporation

Termination region architecture for vertical power transistors

A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (mosfet), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage.
D3 Semiconductor Llc

Semiconductor structure

A semiconductor structure includes a substrate, a source/drain region, a composite layer and a plug. The source/drain region and the composite layer are over the substrate.
Taiwan Semiconductor Manufacturing Company Ltd.

Compound semiconductor field effect transistor gate length scaling

A compound semiconductor transistor may include a channel layer. The compound semiconductor transistor may also include a dielectric layer on the channel layer.
Qualcomm Incorporated

Single-electron transistor with self-aligned coulomb blockade

Semiconductor devices include a thin channel region formed on a buried insulator. A source and drain region is formed on the buried insulator, separated from the channel region by notches.
International Business Machines Corporation

Method and structure for forming improved single electron transistor with gap tunnel barriers

A semiconductor device includes a single electron transistor (set) having an island region, a bottom source/drain region under the island region, and a top source/drain region over the island region, a first gap between the bottom source/drain region and the island region, a second gap between the top source/drain region and the island region, and a gate structure on a side of the island region.. .
International Business Machines Corporation

Semiconductor device and manufacturing the same

A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions.
Renesas Electronics Corporation

Semiconductor device

A semiconductor device includes first and second electrodes, first semiconductor region of first conductivity type between the first and second electrodes, a second semiconductor region of second conductivity type between the first semiconductor region and the first electrode, a third semiconductor region of the second conductivity type between the first semiconductor region and the second electrode, a fourth semiconductor region of the first conductivity type between the third semiconductor region and the second electrode, a plurality of third electrodes between the second electrode and the first semiconductor region, wherein a gate insulating film is between each third electrode and the third semiconductor region, a fourth electrode extending between the third semiconductor region and the second electrode and electrically connected to the third semiconductor region and the second electrode, and a first insulating film between the second and electrodes. The fourth electrode is in ohmic contact with the third semiconductor region..
Kabushiki Kaisha Toshiba

Bipolar junction transistor and integrated circuit device

A bipolar junction transistor includes a semiconductor substrate, a fin structure, an epitaxial emitter, an epitaxial collector and a gate. The fin structure is disposed on the semiconductor substrate and has a base portion of a first conductivity type, a first recessed portion and a second recessed portion.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device and fabricating the same

A semiconductor device includes a substrate, at least one first semiconductor layer, and at least one second semiconductor layer. The at least one first semiconductor layer is disposed on the substrate, and the at least one second semiconductor layer is disposed on the at least one first semiconductor layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

Reducing bending in parallel structures in semiconductor fabrication

A first layer of a first material is deposited on a first structure and a second structure, a surface of the first structure being disposed substantially parallelly to a surface of the second structure in at least one direction. A selectively removable material is deposited over the first layer and removed up to a height of a first step.
International Business Machines Corporation

High-speed semiconductor device and forming the same

A method for forming a semiconductor device is provided. The method includes forming a gate structure over a fin structure.
Taiwan Semiconductor Manufacturing Co., Ltd.

Thin film transistor substrate, manufacturing thin film transistor substrate, and liquid crystal display

A first semiconductor layer is opposed to a first gate electrode with intermediation of a gate insulation film, and is formed of amorphous silicon. First and second contact layers each have a portion arranged on the first semiconductor layer, and are formed of an oxide semiconductor.
Mitsubishi Electric Corporation

Production thin-film transistor, thin-film transistor, display apparatus, and fingerprint recognition unit

This disclosure discloses a production method of a thin-film transistor, a thin-film transistor, a display apparatus, and a fingerprint recognition unit. Said method comprises the steps of: sequentially depositing a metal layer and an indium zinc oxide layer as a protective layer on a substrate; etching the metal layer and the indium zinc oxide layer to form a first electrode and a second electrode of a photosensitive device; and forming a photoelectric semiconductor of the photosensitive device on the first electrode..
Boe Technology Group Co., Ltd.

Semiconductor device and manufacturing the same

A method for manufacturing a semiconductor device is provided by follows. A fin is formed over a substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Compound semiconductor field effect transistor with self-aligned gate

A compound semiconductor field effect transistor (fet) may include a channel layer. The semiconductor fet may also include an oxide layer, partially surrounded by a passivation layer, on the channel layer.
Qualcomm Incorporated

Source/drain parasitic capacitance reduction in finfet-based semiconductor structure having tucked fins

A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance.
Globalfoundries Inc.

Gate structure of a semiconductor device

A cmos semiconductor device includes a substrate comprising an isolation region separating a p-active region and an n-active region. The cmos semiconductor device further includes a p-metal gate electrode over the p-active region and extending over the isolation region, wherein the p-metal gate electrode includes a p-work function metal and a doped tin layer between the p-work function metal and substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor structure and fabrication method thereof

A semiconductor structure and a fabrication method are provided. The fabrication method includes: providing a substrate; forming a gate dielectric layer on the substrate; forming a dielectric barrier layer structure on the gate dielectric layer, a first silicon source gas being used to dope silicon in the dielectric barrier layer structure; forming a work function layer on the dielectric barrier layer structure; forming a gate barrier layer structure on the work function layer, a second silicon source gas being used to dope silicon in the gate barrier layer structure; and forming a gate electrode layer on the gate barrier layer structure..
Semiconductor Manufacturing International (beijing) Corporation

Semiconductor device

A semiconductor device includes a semiconductor layer provided on a substrate, a drain electrode and a source electrode provided on the semiconductor layer, and a gate electrode provided on the semiconductor layer such that an angle between a lateral surface and the semiconductor layer gradually decreases toward the semiconductor layer.. .
Toshiba Infrastructure Systems & Solutions Corporation

Unmerged epitaxial process for finfet devices with aggressive fin pitch scaling

Methods for forming a semiconductor device include forming a first spacer on a plurality of fins. A second spacer is formed on the first spacer, the second spacer being formed from a different material from the first spacer.
Globalfoundries Inc.

Nonvolatile memory device

A nonvolatile memory device includes a semiconductor substrate, a tunnel insulation layer disposed on the semiconductor substrate, a charge trap layer disposed on the tunnel insulation layer, and a control gate electrode disposed on the charge trap layer. The tunnel insulation layer includes an antiferroelectric material..
Sk Hynix Inc.

Semiconductor device and manufacturing method therefor

The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a semiconductor structure, where the semiconductor structure includes an active region and a gate structure located in the active region, the gate structure at least including a gate electrode, and the active region exposing an upper surface of the gate electrode; forming a surface insulator layer on the upper surface of the gate electrode; forming a patterned interlayer dielectric layer on the semiconductor structure, where the interlayer dielectric layer covers the surface insulator layer, and has a first through hole exposing a portion of the active region; and forming a conductive contact layer passing through the first through hole and contacting with the active region.
Semiconductor Manufacturing International (beijing) Corporation

Semiconductor device, manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator

A semiconductor device according to an embodiment includes a silicon carbide layer, an insulating layer, and a region provided between the silicon carbide layer and the insulating layer, the region including a plurality of first atoms of one element from the group consisting of nitrogen (n), phosphorus (p), arsenic (as), antimony (sb), and bismuth (bi), at least some of the plurality of first atoms being four-fold coordinated atoms and/or five-fold coordinated atoms.. .
Kabushiki Kaisha Toshiba

Semiconductor device with transistor cells and enhancement cells

A semiconductor device includes transistor cells and enhancement cells. Each transistor cell includes a body zone that forms a first pn junction with a drift structure.
Infineon Technologies Ag

Method for processing a semiconductor workpiece and semiconductor device

A method for processing a semiconductor workpiece, including: forming a trench structure in a first region of a semiconductor workpiece, extending from a surface of the semiconductor workpiece to a first depth, forming at least one recess in a second region of the semiconductor workpiece laterally next to the first region, the recess extending from the surface of the semiconductor workpiece into the semiconductor workpiece to a second depth less than the first depth; forming a material layer over the semiconductor workpiece, the material layer filling the trench structure and recess and covering the surface of the semiconductor workpiece in the first region and in the second region; and planarizing the semiconductor workpiece to partially remove the material layer in the first region and in the second region, wherein the material layer remains in the trench structure and in the at least one recess.. .
Infineon Technologies Ag

Semiconductor device and manufacturing the same

According to one embodiment, a semiconductor device includes a semiconductor element having a substrate with at least two bending portions formed on a first side surface thereof. The two bending portions are displaced from each other in a first direction that is perpendicular to the first side surface of the substrate and parallel to a front surface of the substrate and in a second direction parallel to the front surface of the substrate and perpendicular to a top surface of the substrate.
Toshiba Memory Corporation

Nucleation layer for growth of iii-nitride structures

Nucleation layers for growth of iii-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate.
1qe, Pie

Semiconductor device

A current sensing part that detects overcurrent of a main semiconductor element is arranged on a same silicon carbide base as the main semiconductor element. An isolating part is arranged between the main semiconductor element and the current sensing part.
Fuji Electric Co., Ltd.

Silicon carbide semiconductor device and manufacturing

A semiconductor device includes a trench structure extending from a first surface into a silicon carbide semiconductor body. The trench structure includes an auxiliary electrode at a bottom of the trench structure and a gate electrode arranged between the auxiliary electrode and the first surface.
Infineon Technologies Ag

Semiconductor device and manufacturing the same

Semiconductor device 101 includes semiconductor substrate 10, drift layer 20, first electrode 50, and second electrode 60. Semiconductor substrate 10 is of a first conductivity type and is formed of a silicon carbide semiconductor, a gallium nitride semiconductor, or the like.
Panasonic Intellectual Property Management Co., Ltd.

Silicon carbide epitaxial substrate and manufacturing silicon carbide semiconductor device

A silicon carbide epitaxial substrate has a silicon carbide single-crystal substrate and a silicon carbide layer. An average value of carrier concentration in the silicon carbide layer is not less than 1×1015 cm−3 and not more than 5×1016 cm−3.
Sumitomo Electric Industries, Ltd.

Semiconductor device, inverter circuit, drive device, vehicle, and elevating machine

A semiconductor device of an embodiment includes first and second electrodes, a first gate electrode, a semiconductor layer disposed between the first electrode and a band gap of the semiconductor layer being wider than a band gap of silicon, a silicon layer between the semiconductor layer and the first electrode, a metal layer between the semiconductor layer and the silicon layer, a first semiconductor region of a first-conductivity type in the semiconductor layer, a first silicon region of the first-conductivity type in the silicon layer, a second silicon region of a second-conductivity type in the first silicon region, a third silicon region of the second-conductivity type in the first silicon region and separated from the second silicon region, a first gate insulating layer, a fourth silicon region of the first-conductivity type in the second silicon region, and a fifth silicon region in the third silicon region.. .
Kabushiki Kaisha Toshiba

Semiconductor integrated circuit with guard ring

A semiconductor integrated circuit includes a first conduction-type semiconductor region, a second conduction-type first impurity region, and a guard ring formed using a first conduction-type second impurity region so as to form a protection device of an electrostatic protection circuit. The first impurity region is formed inside the semiconductor region to have a rectangular planar structure with long and short sides.
Renesas Electronics Corporation

Porous semiconductor handle substrate

An integrated circuit (ic) may include an active device layer on a front-side surface of a semiconductor device substrate. The ic may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer.
Qualcomm Incorporated

Semiconductor device and manufacturing same

According to one embodiment, the joint part has a diameter larger than a diameter of the first columnar part and a diameter of the second columnar part. The joint part includes an intermediate semiconductor body continuous with the first semiconductor body and the second semiconductor body.
Toshiba Memory Corporation

Method of manufacturing a substrate with reduced threading dislocation density

A method of manufacturing a substrate with reduced threading dislocation density is disclosed, which comprises: (i) at a first temperature, forming a first layer of wafer material on a semiconductor substrate, the first layer arranged to be doped with a first concentration of at least one dopant that is different to the wafer material; and (ii) at a second temperature higher than the first temperature, forming a second layer of the wafer material on the first layer to obtain the substrate, the second layer arranged to be doped with a progressively decreasing concentration of the dopant during formation, the doping configured to be decreased from the first concentration to a second concentration. The wafer material and dopant are different to silicon.
Massachusetts Institute Of Technology

Nanowire finfet transistor

Semiconductor devices and methods of forming the same are provided. A semiconductor device includes a substrate having a fin.
Taiwan Semiconductor Manufacturing Company, Ltd.

Co-integration of silicon and silicon-germanium channels for nanosheet devices

Nanosheet semiconductor devices and methods of forming the same include forming a first stack having layers of a first material and layers of a second material. A second stack is formed having layers of a third material, layers of the second material, and a liner formed around the layers of the third material.
International Business Machines Corporation

Semiconductor device

A semiconductor device according to an embodiment includes a semiconductor substrate, source electrodes, drain electrodes provided between the source electrodes, gate electrodes provided between the source electrodes and the drain electrodes, first p-type region in the semiconductor substrate, n-type source regions in the semiconductor substrate extending in a first direction and electrically connected to the source electrodes, n-type drain regions in the semiconductor substrate extending in the first direction and electrically connected to the drain electrodes, and first n-type regions extending in the first direction, the first p-type region interposed between the first n-type regions and the n-type source regions, the first p-type region interposed between the first n-type regions and the n-type drain regions. A distance between one first n-type region among the first n-type regions and the source electrodes is less than a distance between the one first n-type region and the drain electrodes..
Kabushiki Kaisha Toshiba

Oscillating capacitor architecture in polysilicon for improved capacitance

A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places a polysilicon layer on top of an oxide layer which is on top of a metal layer.
Advanced Micro Devices, Inc.

Surface area enhancement for stacked metal-insulator-metal (mim) capacitor

A method for forming a metal-insulator-metal (mim) capacitor on a semiconductor substrate is presented. The method includes forming a first electrode defining columnar grains, forming a dielectric layer over the first electrode, and forming a second electrode over the dielectric layer.
International Business Machines Corporation

Semiconductor capacitor and power supply module

A semiconductor capacitor includes a semiconductor substrate having a first and second principal surfaces. A first set of one or more trenches is formed on the first principal surface and a second set of one or more trenches formed on the second principal surface.
Murata Manufacturing Co., Ltd.

Surface area enhancement for stacked metal-insulator-metal (mim) capacitor

A method for forming a metal-insulator-metal (mim) capacitor on a semiconductor substrate is presented. The method includes forming a first electrode defining columnar grains, forming a dielectric layer over the first electrode, and forming a second electrode over the dielectric layer.
International Business Machines Corporation

Semiconductor device having resistance elements and fabrication method thereof

A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration cx.
Mie Fujitsu Semiconductor Limited

Semiconductor device, display device, and electronic device

A load, a transistor which controls a current value supplied to the load, a capacitor, a power supply line, and first to third switches are provided. After a threshold voltage of the transistor is held by the capacitor, a potential in accordance with a video signal is inputted and a voltage that is the sum of the threshold voltage and the potential is held.
Semiconductor Energy Laboratory Co., Ltd.

Radiation detector

According to one embodiment, a radiation detector includes a first conductive layer, a second conductive layer, and an intermediate layer. The intermediate layer is provided between the first and second conductive layers.
Kabushiki Kaisha Toshiba

Solid-state image sensor, producing the same, and electronic apparatus

A solid-state image sensor includes a pixel formed, upon forming a structure where a photoelectric conversion layer is laminated on a wiring layer constituting a pixel circuit, by forming at least the photoelectric conversion layer and a wiring layer bonding layer on a different substrate from a semiconductor substrate in which the wiring layer is formed, and by bonding the wiring layer bonding film of the different substrate and the wiring layer of the semiconductor substrate together.. .
Sony Semiconductor Solutions Corporation

Semiconductor device

A semiconductor device includes a semiconductor pillar and a control electrode. The semiconductor pillar extends in a first direction, and includes a first region, a second region and an intermediate region provided along the first direction.
Toshiba Memory Corporation

Semiconductor storage device

A semiconductor storage device includes first and second wirings that are in a first layer above the substrate, extend along a first direction, and are adjacent to each other along a second direction, third and fourth wirings that are in a second layer above the first layer, extend along the second direction, and are adjacent to each other along the first direction, first and second memory cells on the first wiring, and a third memory cell on the second wiring. The first to third memory cells each include a variable resistance element and a switching element.
Toshiba Memory Corporation

Semiconductor device

The present technology relates to a semiconductor device which enables yield to be enhanced. A volatile logic circuit has a storage node, and stores inputted information.
Sony Corporation

Micro light emitting diode and display panel

A micro led including an epitaxial stack layer, a first electrode and a second electrode is provided. A lower surface of the first electrode is in contact with an upper surface of a first semiconductor layer of the epitaxial stack layer.
Playnitride Inc.

Light-emitting device

A light-emitting device includes: a substrate comprising a first side and a second side opposite to the first side; multiple semiconductor stacks on the first side and separated from each other, wherein each of the multiple semiconductor stacks comprises a light extraction area and an electrode pad area connected to the light extraction area; multiple electrode pads, wherein each of the multiple electrode pads is on one of the electrode pad areas; and a blocking layer between one of the semiconductor stacks and the substrate.. .
Epistar Corporation

Display device using semiconductor light emitting device

A display device including a substrate; a sub-pixel portion disposed on the substrate; and a wiring electrode electrically connected to the sub-pixel portion. Further, the sub-pixel portion includes a first light emitting portion and a second light emitting portion configured to output light of a same color and spaced apart with a groove therebetween, and the wiring electrode includes a base electrode configured to transmit a same electric signal to the first light emitting portion and the second light emitting portion, a first sub-electrode extended from the base electrode and electrically connected to the first light emitting portion, and a second sub-electrode extended from the base electrode and electrically connected to the second light emitting portion..
Lg Electronics Inc.

Semiconductor device, fabrication a semiconductor device and electronic apparatus

Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.. .
Sony Corporation

Solid-state imaging device, manufacturing solid-state imaging device, and imaging apparatus

A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of amos transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of amos transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion.. .
Sony Corporation

Stacked grid design for improved optical performance and isolation

A back side illumination (bsi) image sensor with a dielectric grid opening having a planar lower surface is provided. A pixel sensor is arranged within a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Solid-state imaging device, imaging system, and movable object

A solid-state imaging device includes a plurality of pixels each including a photoelectric conversion unit, a first holding portion holding charges transferred from the photoelectric conversion unit, a second holding portion holding charges transferred from the first holding portion, and an amplifier unit outputting a signal based on charges in the second holding portion. The photoelectric conversion unit includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region thereunder, a first conductivity type third semiconductor region thereunder, and a second conductivity type fourth semiconductor region thereunder.
Canon Kabushiki Kaisha

Active matrix substrate and producing the same

An active matrix substrate includes a first tft (10), a second tft (20) disposed per pixel, and a circuit including the first tft. The first and second tfts each include a gate electrode (102a, 102b), a gate insulating layer (103), an oxide semiconductor layer (104a, 104b), and source and drain electrodes in contact with an upper surface of the oxide semiconductor layer.
Sharp Kabushiki Kaisha

Mechanisms for forming finfet device

Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor memory device

A semiconductor memory device includes wirings arranged in parallel along a first direction, the wirings including first and second wirings that are adjacent and a third wiring adjacent to the second wiring, a first pillar between the first and second wirings and a second pillar between the second and third wirings, the first and second pillars each extending in a second direction crossing the first direction toward the semiconductor substrate, and first and second bit lines connected to the first and second pillars, respectively. A first voltage is applied to the second wiring during a program operation on a first memory cell at an intersection of the second wiring and the first pillar, and a second voltage higher than the first voltage is applied to the second wiring during a program operation on a second memory cell at an intersection of the second wiring and the second pillar..
Toshiba Memory Corporation

Semiconductor memory device and manufacturing the same

According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a circuit section, a first insulating layer, and a first columnar part. The stacked body is provided on the substrate and includes a plurality of electrode layers stacked with spacing from each other.
Toshiba Memory Corporation

Semiconductor memory device and manufacturing the same

According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a first insulating film, and a first film. The stacked body is provided on the substrate.
Toshiba Memory Corporaion

Semiconductor memory device

A semiconductor memory device includes a substrate, electrode films provided on a first direction side of the substrate and arranged with spacing from each other along the first direction, semiconductor members extending in the first direction, a charge storage member provided between each of the electrode films and each of the semiconductor members, and a control circuit. Memory cells are formed in crossing portions of the electrode films and the semiconductor members.
Toshiba Memory Corporation

Semiconductor device and manufacturing the same

According to an embodiment, a semiconductor device includes a substrate, a stacked body, a first insulating film, a second insulating film and a plurality of contacts. The stacked body is provided on the substrate and includes a plurality of electrode films stacked with spacing from each other.
Toshiba Memory Corporation

Semiconductor memory device and manufacturing semiconductor memory device

According to an embodiment, a semiconductor memory device includes a stacked body in which insulating layers and electrode films are alternately stacked, a pillar member arranged in a memory hole that is disposed in the stacked body in a thickness direction, and a semiconductor layer provided below the pillar member. The pillar member has a structure in which a memory film and a channel layer are stacked in order from a side of the stacked body.
Toshiba Memory Corporation

Semiconductor memory device and manufacturing same

A semiconductor memory device includes a stacked body in which electrode films and insulating films are stacked alternately along a first direction, a semiconductor member extending in the first direction, and a charge storage member provided between the semiconductor member and the electrode film. The electrode film includes a first conductive layer and a second conductive layer.
Toshiba Memory Corporation

Semiconductor device and manufacturing the same

Provided herein is a semiconductor device. The semiconductor device may include conductive layers each including a line, and a pad which is coupled with the line and has a thickness greater than that of the line, the conductive layers being stacked such that the pads are exposed; insulating layers interposed between the conductive layers; first spacers each of which is interposed between the pad of the corresponding upper conductive layer and the pad of the corresponding low conductive layer; and second spacers covering the respective first spacers..
Sk Hynix Inc.

Semiconductor device and manufacturing the same

Provided herein may be a semiconductor device. The semiconductor device may include a stack, channel holes passing through the stack, dummy channel holes passing through the stack and disposed between the channel holes, a slit passing through the stack and the dummy channel holes..
Sk Hynix Inc.

Semiconductor device and manufaturing same

According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a semiconductor body, and a charge storage portion. The stacked body includes a plurality of electrode layers stacked with an air gap interposed, a plurality of select gate layers stacked in a stacking direction of the electrode layers, and an insulating body provided between the select gate layers adjacent to each other in the stacking direction.
Toshiba Memory Corporation

Semiconductor device and manufacturing the same

A semiconductor device includes a first electrode layer and a second electrode layer formed thereon to be spaced from the first electrode layer, a columnar portion penetrating the first and second electrode layers in a first direction and including a semiconductor layer, a first insulating film between the first and second electrode layers and the semiconductor layer and in contact with the first electrode layer, a charge storage layer between the second electrode layer and the first insulating film, and an insulating film between the second electrode layer and the charge storage layer. The semiconductor layer includes a first portion facing the second electrode layer in a second direction intersecting with the first direction and a second portion in contact with the first portion in the first direction.
Toshiba Memory Corporation

Semiconductor device and manufacturing method thereof

In a method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral area, a mask layer is formed over a substrate in the memory cell area and the peripheral area. A resist mask is formed over the peripheral area.
Taiwan Semiconductor Manufacturing Co., Ltd.

Pads and pin-outs in three dimensional integrated circuits

A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.. .
Callahan Cellular L.l.c.

Semiconductor device and manufacturing the same

Provided is a semiconductor device which has a non-volatile memory including: a semiconductor substrate; a tunnel insulating film formed on a surface of the semiconductor device; a floating gate formed on the tunnel insulating film; a memory cell transistor drain region and a memory cell transistor source region formed from the surface to an inside of the semiconductor substrate in a vicinity of both ends of the floating gate; a first interface formed between the semiconductor substrate and the tunnel insulating film; and a second interface formed between the floating gate and the tunnel insulating film. The first interface and the second interface form an uneven structure having a curvature that changes at an identical period with respect to a place in sectional view..
Ablic Inc.

Semiconductor memory device and forming the same

A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a plurality of bit lines, a gate, a spacer layer and a first spacer. The substrate has a memory cell region and a periphery region, the a plurality of bit lines are disposed on the substrate, within the memory cell region, and the gate is disposed on the substrate, within the periphery.
Fujian Jinhua Integrated Circuit Co., Ltd.

Semiconductor device and fabricating the same

A method for fabricating a semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the substrate; forming a thyristor on the cell region; removing the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer on the peripheral region; and forming a metal oxide semiconductor (mos) transistor on the peripheral region.. .
Fujian Jinhua Integrated Circuit Co., Ltd.

Integrated circuit and manufacturing method thereof

An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

A semiconductor device includes: channel patterns disposed on a substrate; a pair of source/drain patterns disposed at first and second sides of each of the channel patterns; and a gate electrode disposed around the channel patterns, wherein the gate electrode includes a first recessed top surface between adjacent channel patterns, wherein the channel patterns are spaced apart from the substrate, and wherein the gate electrode is disposed between the substrate and the channel patterns.. .
Samsung Electronics Co., Ltd.

Semiconductor device

A semiconductor device includes a first transistor. The first transistor includes a first terminal, a first contact, a second terminal, and a second contact.
Taiwan Semiconductor Manufacturing Co., Ltd.

Contact formation in semiconductor devices

A technique relates to fabricating a pfet device and nfet device. A contact trench is formed through an inter-level dielectric layer (ild) and a spacer layer.
International Business Machines Corporation

Structure and multiple threshold voltage definition in advanced cmos device technology

A method of fabricating a semiconductor structure having multiple defined threshold voltages includes: forming multiple field-effect transistor (fet) devices in the semiconductor structure, each of the fet devices including a channel and a gate stack formed of one of at least two different work function metals, the gate stack being formed proximate the channel; and varying a bang-gap of the channel in each of at least a subset of the fet devices by controlling a percentage of one or more compositions of a material forming the channel; wherein a threshold voltage of each of the fet devices is configured as a function of a type of work function metal forming the gate stack and the percentage of one or more compositions of the material forming the channel.. .
International Business Machines Corporation

Method of fabricating integrated circuit

A method includes forming a transistor over a substrate, wherein the transistor includes a source, a drain over the source, a semiconductor channel between the source and the drain, and a gate surrounding the semiconductor channel. A silicide layer is formed over the drain of the transistor.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor integrated circuit and logic circuit

Disclosed herein is a driver circuit including first and second n-channel transistors connected together in series between first and second nodes. The first n-channel transistor is comprised of n fin transistor(s) having an identical gate length and an identical gate width where n is equal to or greater than one, and has its gate connected to a first input node.
Socionext Inc.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate; a first gate stack disposed on the substrate; a second gate stack disposed on the substrate, wherein a metal component of the first gate stack is different from a metal component of the second gate stack; and a dielectric structure disposed over the substrate and between the first gate stack and the second gate stack, in which the dielectric structure is separated from the first gate stack and the second gate stack, and a distance between the dielectric structure and the first gate stack is substantially equal to a distance between the dielectric structure and the second gate stack.. .
Taiwan Semiconductor Manufacturing Co., Ltd.

Normally off iii nitride transistor

A semiconductor device containing an enhancement mode gan fet on a iii-n layer stack includes a low-doped gan layer, a barrier layer including aluminum over the low-doped gan layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer.
Texas Instruments Incorporated

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate; a first device disposed on the substrate, and the first device includes at least two first gate stacks, in which the two adjacent first gate stacks have a first distance therebetween; a plurality of first gate spacers having a first thickness disposed on opposite sidewalls of the first gate stacks; the semiconductor device further includes a second device disposed on the substrate, and the second device includes at least two second gate stacks, in which the two adjacent second gate stacks have a second distance therebetween, and the first distance is smaller than the second distance; a plurality of second gate spacers having a second thickness disposed on opposite sidewalls of the second gate stacks, and the first thickness is greater than the second thickness.. .
Taiwan Semiconductor Manufacturing Co., Ltd.

Method for forming capacitor, semiconductor device, module, and electronic device

A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device having electro-static discharge protection structure

A semiconductor device, having an electro-static discharge (esd) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer.
Csmc Technologies Fab2 Co., Ltd.

Semiconductor device

A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a plurality of first semiconductor areas provided on the first plane, a plurality of second semiconductor areas provided between the plurality of first semiconductor areas, a plurality of insulator regions provided between the first semiconductor areas and the second semiconductor areas, first-conductivity-type drain regions provided in the first semiconductor areas, first-conductivity-type source regions provided in the second semiconductor areas, gate electrodes, first-conductivity-type first impurity regions that are provided between the first-conductivity-type drain regions and the second plane and have a lower first-conductivity-type impurity concentration than the first-conductivity-type drain regions, and a plurality of second-conductivity-type second impurity regions provided between the first-conductivity-type source regions and the second plane. The width of at least one of the plurality of first semiconductor areas is greater than the width of the other first semiconductor areas..
Kabushiki Kaisha Toshiba

Methods for processing a 3d semiconductor device

A method for processing a 3d semiconductor device, the method including: providing a wafer including a plurality of first dies, the plurality of first dies including a first transistor layer and a first interconnection layer; completing a step of transferring a plurality of second dies each overlaying at least one of the first dies, where each of the plurality of second dies includes a second transistor layer, where at least one of the plurality of first dies is substantially larger in area than at least one of the plurality of second dies, and where each of the plurality of second dies has a thickness greater than six microns; and completing a step of thinning the plurality of second dies, where each of the plurality of second dies has a thickness of less than 2 microns.. .
Monolithic 3d Inc.

Semiconductor package

A semiconductor package includes a substrate having opposing first and second surfaces, first memory chips stacked on the first surface, second memory chips stacked on the first surface, a controller chip for the first and second memory chips, installed on the first surface between the stacked first memory chips and the stacked second memory chips, a sealing portion that seals the first and second memory chips, and the controller chip, and a plurality of solder balls installed on the second surface. The first memory chips are stacked such that a first memory chip located directly above another first memory chip is shifted further toward the controller chip relative to said another first memory chip.
Toshiba Memory Corporation

Wafer level chip scale filter packaging using semiconductor wafers with through wafer vias

An electronics package includes a semiconductor substrate having one or more passive devices formed thereon and a cavity defined in a first surface thereof. A piezoelectric substrate is bonded to the semiconductor substrate and has a radio frequency (rf) filter formed thereon.
Skyworks Solutions, Inc.

Semiconductor structure and manufacturing the same

A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate including a front surface and a back surface; a backside metallization layer formed over the semiconductor substrate, the backside metallization layer being closer to the back surface than to the front surface of the semiconductor substrate, at least a portion of the backside metallization layer forming an inductor structure; and an electrically non-conductive material formed in the semiconductor substrate, the electrically non-conductive material at least partially overlapping the inductor structure from a top view, and the electrically non-conductive material including a top surface, a bottom surface, and sidewalls, the top surface being adjacent to the back surface of the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company Ltd.

Transfer head and transfer system for semiconductor light-emitting device and transferring semiconductor light-emitting device

The present invention relates to a display device and, more particularly, to a transfer head for a semiconductor light-emitting device applied to the display device and a method for transferring a semiconductor light-emitting device. The transfer head for a semiconductor light-emitting device, according to the present invention, comprises: a base substrate; and an electrode unit disposed on the base substrate to generate an electrostatic force by charging an un-doped semiconductor layer of the semiconductor light-emitting device with electric charges, wherein the base substrate and the electrode unit are formed of light-transmitting materials so that at least a part of the semiconductor light-emitting device is viewable through the base substrate and the electrode unit in sequence..
Lg Electronics Inc.

Semiconductor device and a manufacturing the same

A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure..
Renesas Electronics Corporation

3d semiconductor device and structure

A 3d semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; a second metal layer overlaying the plurality of second transistors; a plurality of third transistors overlaying the second transistors; a third metal layer overlaying the plurality of third transistors; and a connective metal path between the third metal layer and at least one of the first transistors, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error, where the first metal layer is powered by a first voltage and the second metal layer is powered by a second voltage.. .
Monolithic 3d Inc.

Semiconductor device and manufacturing method thereof

An improvement is achieved in the reliability of a semiconductor device. A first semiconductor chip includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate, an insulating film formed over the wiring structure, and a first insulating film formed over the insulating film.
Renesas Electronics Corporation

Semiconductor device

A semiconductor device comprises a first semiconductor chip comprising a first substrate. A first magnetic tunnel junction is on the first substrate.
Samsung Electronics Co., Ltd.

Semiconductor device

A semiconductor device includes a first and a second chips. A first inductor is above a first surface or a second surface located on an opposite side to the first surface.
Toshiba Memory Corporation

Semiconductor device and manufacturing method thereof

A device includes a wiring substrate. A first semiconductor-chip has a first face, a second face, and a first side face between an outer edge of the first face and an outer edge of the second face, where the first side face is a first condition plane.
Toshiba Memory Corporation

Semiconductor device

A semiconductor device includes a substrate having first and second principal surfaces, and a semiconductor chip disposed on the first principal surface. The substrate includes a first conductor layer disposed on the first principal surface, a second conductor layer disposed on the second principal surface, at least one third conductive layer between the first conductive layer and the second conductive layer, a detection interconnection disposed in either the first conductive layer or the third conductive layer, and first and second pads disposed on the second conductive layer and connected to the detection interconnection.
Toshiba Memory Corporation

Semiconductor package for multiphase circuitry device

In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element.
Infineon Technologies Ag

Method of manufacturing semiconductor device

To provide a semiconductor device having improved reliability. A method of manufacturing the semiconductor device includes connecting a wire comprised of copper with a conductive layer formed on the pad electrode of a semiconductor chip, heat treating the semiconductor chip, and then sealing the semiconductor chip and the wire with a resin..
Renesas Electronics Corporation

Pressure contact type semiconductor apparatus

In a pressure contact type semiconductor apparatus, a second intermediate electrode on a second semiconductor chip has one or more second through holes. The one or more second through holes are fluidly separated from a space hermetically sealed by a cylindrical body, a first common electrode plate and a second common electrode plate.
Mitsubishi Electric Corporation

Solder joining

The present invention suppresses fracture at an interface between different materials, and provides a solder joining which includes: a solder joining layer 10 having a melted solder material, containing sb at more than 5.0% by mass and 10.0% by mass or less, ag at 2.0 to 4.0% by mass, ni at more than 0 and 1.0% by mass or less, and a balance made up of sn and inevitable impurities; and joining members 11 and 123 at least one of which is a cu or cu-alloy member 123, in which the solder joining layer includes a first structure 1 containing (cu, ni)6(sn, sb)5 and a second structure 2 containing (ni, cu)3(sn, sb)x (in the formula, x is 1, 2, or 4) at an interface with the cu or cu-alloy member 123, and an electronic device and a semiconductor device including the solder joining.. .
Fuji Electric Co., Ltd.

Liquid ejection head substrate and semiconductor substrate

A liquid ejection head substrate includes an electrode pad for receiving driving power for liquid ejection from an outside, the electrode pad including at least a conductor layer and a layer of gold. A portion of the conductor layer has an opening region, and an upper layer portion in a laminating direction above the conductor layer including the opening region has at least the layer of gold.
Canon Kabushiki Kaisha

Ldmos transistor structure and manufacture

In an embodiment, a method includes forming a first opening in a front surface of a semiconductor substrate including a ldmos transistor structure, and covering the first opening with a first layer to form an enclosed cavity defined by material of the semiconductor substrate and the first layer. The material of the first layer lines sidewalls of the enclosed cavity..
Infineon Technologies Ag

Semiconductor arrangement in fan out packaging including magnetic structure around transmission line

A semiconductor arrangement in fan out packaging has a molding compound adjacent a side of a semiconductor die. A magnetic structure is disposed above the molding compound, above the semiconductor die, and around a transmission line coupled to an integrated circuit of the semiconductor die.
Taiwan Semiconductor Manufacturing Company Limited

Semiconductor memory device and manufacturing the same

According to an embodiment, a semiconductor memory device includes a substrate, an insulating film, a plurality of conductive films, an insulating member, a plurality of stacked bodies, and a first member. The insulating member is provided on the insulating film, is positioned between the conductive films in a first direction along the substrate, and extends in a second direction along the substrate, the second direction crossing the first direction.
Toshiba Memory Corporation

Semiconductor device

A semiconductor device includes a mounting substrate including an interface, which is connectable with a host, and a first ground layer, a surface-mounted component mounted on the mounting substrate, and a plurality of solder balls between the mounting substrate and the surface-mounted component. The surface-mounted component includes a semiconductor chip, a package substrate that is positioned between the semiconductor chip and the solder balls and includes a second ground layer, a sealing portion that covers the semiconductor chip, and has an opening, a first conductive portion on a top surface of the sealing portion, and a second conductive portion on a side surface of the opening and electrically connected to the first conductive portion and the second ground layer.
Toshiba Memory Corporation

Semiconductor device and manufacturing the same

According to one embodiment, a semiconductor device includes a first semiconductor circuit layer including a first conductive layer, a second semiconductor circuit layer including a second conductive layer, and a third semiconductor circuit layer between the first semiconductor circuit layer and the second semiconductor circuit layer, the third semiconductor circuit layer including a third conductive layer in contact with the first conductive layer, a fourth conductive layer in contact with the second conductive layer, and a fifth conductive layer in contact with the third conductive layer and electrically connected to the fourth conductive layer. The fifth conductive layer has a width that is narrower than a width of the third conductive layer..
Toshiba Memory Corporation

Packages with interposers and methods for forming the same

A package structure includes an interposer, a die over and bonded to the interposer, and a printed circuit board (pcb) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor memory device and manufacturing the same

According to an embodiment, a semiconductor memory device includes a substrate, a first stacked body, a columnar part, a second insulating film, and a second stacked body. The first stacked body is provided in a first region on the substrate.
Toshiba Memory Corporation

Method of manufacturing semiconductor device and semiconductor device

A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.. .
Toshiba Memory Corporation

Power electronics assemblies and vehicles incorporating the same

A power electronics assembly includes a semiconductor device, a metal substrate, and a cooling structure. The metal substrate includes a plurality of stress-relief features that extend at least partially through a thickness of the metal substrate.
Toyota Motor Engineering & Manufacturing North America, Inc.

Semiconductor package and manufacturing method thereof

A semiconductor package includes a ground electrode formed on an upper surface of a substrate, a first electronic component disposed on the upper surface of the substrate, a sealing member sealing the electronic component, and a shielding member surrounding the first electronic component and disposed in the sealing member.. .
Samsung Electro-mechanics Co., Ltd.

Semiconductor device and manufacturing thereof

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising one or more conductive shielding members and an emi shielding layer, and a method of manufacturing thereof..
Amkor Technology, Inc.

Semiconductor package and semiconductor package manufacturing method

A semiconductor package includes a substrate, a semiconductor element disposed on the substrate, an encapsulating layer covering side surfaces and a top surface of the semiconductor element, an electromagnetic shield layer covering side surfaces of the substrate and side surfaces and a top surface of the encapsulating layer, and a titanium oxide layer formed above a top surface of the electromagnetic shield layer, and including a first portion containing divalent titanium oxide and a second portion containing tetravalent titanium oxide.. .
Toshiba Memory Corporation

Graphene wiring structure, semiconductor device, manufacturing graphene wiring structure, and manufacturing wiring structure

A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film..
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing the semiconductor device

Even if a via hole is displaced, erosion of a first layer made of titanium is suppressed when the via hole is cleaned. A semiconductor includes a wire layer, a side protective film, an interlayer insulating film, and via plugs.
Renesas Electronics Corporation

Semiconductor device and manufacturing thereof

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising multiple encapsulating layers and multiple signal distribution structures, and a method of manufacturing thereof..
Amkor Technology, Inc.

Semiconductor device

A semiconductor device includes a first chip having a through via, a second chip having a first terminal that is electrically connected to the through via, and a substrate having a second terminal disposed on a first surface thereof and electrically connected to the first terminal. When viewed along a straight line that intersects a center axis that is perpendicular to the first surface and intersects a center point of the substrate, the first terminal is disposed further towards the center axis than the second terminal and the through via is disposed further towards the center axis than the first terminal..
Toshiba Memory Corporation

Contact formation in semiconductor devices

A technique relates to fabricating a semiconductor device. A contact trench is formed in an inter-level dielectric layer.
International Business Machines Corporation

Reducing metallic interconnect resistivity through application of mechanical strain

Methods are provided for fabricating metallic interconnect structures having reduced electrical resistivity that is obtained by applying mechanical strain to the metallic interconnect structures, as well as semiconductor structures having metallic interconnect structures formed with permanent mechanical strain to provide reduced electrical resistivity. For example, a method includes forming a metallic interconnect structure in an interlevel dielectric (ild) layer of a back-end-of-line (beol) structure of a semiconductor structure, and forming a stress layer in contact with the metallic interconnect structure.
International Business Machines Corporation

Differential inductor and semiconductor device including the same

Provided are a differential inductor and a semiconductor device including the same, the differential inductor including first circular parts and second circular parts disposed on a first layer and composing a first spiral shape, a first semi-circular part disposed on the first layer and in the first circular part that is an innermost one of the first circular parts, and a second semi-circular part disposed outside the first circular part that is an outermost one of the first circular parts, third semi-circular parts and fourth semi-circular parts disposed on a second layer under the first layer and composing a second spiral shape, connection means configured to connect, to one, the first and second circular parts, and the first to fourth semi-circular parts, wherein the second circular parts are respectively interposed between the first circular parts, and a part of the fourth semi-circular parts is respectively interposed between the second semi-circular parts.. .
Electronics And Telecommunications Research Institute

Semiconductor device and manufacturing semiconductor device

A semiconductor device in which the generation of a distortion of a signal is suppressed, and a method for manufacturing the semiconductor device are disclosed. The semiconductor device includes a transistor region in which a field effect transistor is provided; and an interconnection region in which a metal layer electrically connected to the field effect transistor is provided.
Sony Corporation

Semiconductor device

There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film.
Mie Fujitsu Semiconductor Limited

Storage device

A storage device includes a first wiring layer, a second wiring layer spaced from the first wiring layer in a first direction, and a plurality of electrode layers stacked in the first direction between the first wiring layer and the second wiring layer. A semiconductor pillar penetrates the plurality of electrode layers in the first direction.
Toshiba Memory Corporation

Semiconductor memory device and manufacturing same

A semiconductor memory device includes a first electrode film, a second electrode film group composed of a plurality of electrode films provided on the first electrode film, a third electrode film group composed of a plurality of electrode films provided on the first electrode film and spaced from the second electrode film group, a semiconductor member extending in a first direction in which the first electrode film and the second electrode film group are arranged, a charge storage member provided between the first electrode film and the semiconductor member, a first conductive film connecting the plurality of electrode films of the second electrode film group to each other and a second conductive film connecting the plurality of electrode films of the third electrode film group to each other.. .
Toshiba Memory Corporation

A semiconductor power device comprising additional tracks and manufacturing the semiconductor power device

Some embodiments relate to a semiconductor power device that includes a first substrate, a second substrate, a stack and an interconnect structure. The first substrate includes a first patterned electrically conductive layer on a first surface and a switching semiconductor element.
Irt Saint Exupery (aese)

Circuit boards and semiconductor packages including the same

A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled.
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing the same

A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate, and a first capacitor including a first electrode and a second electrode, and mounted on the wiring substrate. The wiring layers include a first wiring layer including a first terminal pad electrically connected with the first electrode of the first capacitor and a second terminal pad electrically connected with the second electrode of the first capacitor; and a second wiring layer on an inner side by one layer from the first wiring layer of the wiring substrate and including a first conductor pattern having a larger area than each of the first terminal pad and the second terminal pad.
Renesas Electronics Corporation

Laminate and making method

A laminate is provided comprising a support, a resin layer, a metal layer, an insulating layer, and a redistribution layer. The resin layer comprises a photo-decomposable resin having light-shielding properties and has a transmittance of up to 20% with respect to light of wavelength 355 nm.
Shin-etsu Chemical Co., Ltd.

Semiconductor device and lead frame

A semiconductor device according to a first aspect of the present invention includes a device main body, a single power supply wiring board, a plurality of output wiring boards, and a plurality of semiconductor elements. In a long-side direction of the device main body, the narrow portion of one of any two adjacent wiring boards faces the wide portion of another one of the any two adjacent wiring boards.
Shindengen Electric Manufacturing Co., Ltd.

Semiconductor device

A semiconductor device 1 includes a first drain terminal 4, connected to a drain electrode of a first semiconductor chip, a first gate terminal 5, connected to a gate electrode of the first semiconductor chip, a second drain terminal 6, connected to a drain electrode of a second semiconductor chip, a second gate terminal 7, connected to a gate electrode of the second semiconductor chip, a common source terminal 8, connected to a source electrode of the first semiconductor chip and a source electrode of the second semiconductor chip, and a sealing resin 9, sealing the respective semiconductor chips and the respective terminals. The respective terminals have exposed surfaces (lower surfaces) 43, 53, 63, 73, and 83 substantially flush with an outer surface (lower surface) 9b of the sealing resin 9 and exposed from the outer surface 9b..
Rohm Co., Ltd.

Semiconductor device

A semiconductor device includes field-effect transistor having a gate, a drain, and a source. A first clamping circuit is connected between the drain and the gate.
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing the same

To reduce a package size of a semiconductor device. According to embodiments, there is a semiconductor device comprising: a first die pad; a first inner lead arranged inside a molded resin; a second die pad; and a second inner lead arranged inside the resin, wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other, a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin..
Kabushiki Kaisha Toshiba

Semiconductor package with interconnected leads

A semiconductor package includes a semiconductor die and a ceramic package body covering the semiconductor die. The ceramic package body includes a plurality of contact pads.
Texas Instruments Incorporated

Semiconductor device having corrugated leads and forming

A semiconductor device includes a lead frame site including a die attach region and corrugated metal leads around the die attach region. Each of the corrugated metal leads includes two or more corrugations.
Nxp Usa, Inc.

Methods and semiconductor device having bi-material die attach layer

Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous.
Texas Instruments Incorporated

Semiconductor device, manufacturing semiconductor device, and electrode plate

A semiconductor device includes an electrode plate, a metallic member, and solder connecting the metallic member with the electrode plate. On a surface of the electrode plate, a first groove and a group of second grooves are provided.
Toyota Jidosha Kabushiki Kaisha

Methods and a semiconductor device having bi-material die attach layer

Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous.
Texas Instruments Incorporated

Onboard control device

Provided is an inexpensive and highly reliable resin sealed-type onboard electronic control device is mounted in a vehicle such as an engine control unit and a control unit for automatic transmission, which have a heat dissipation structure for dissipating heat generated from an electronic component such as a semiconductor element. The onboard control device includes a circuit board, a member provided to face the circuit board, a heat generating electronic component mounted between the circuit board and the member, a heat dissipating material provided between the heat generating electronic component and the member, and a sealing resin to seal the circuit board and the heat generating electronic component.
Hitachi Automotive Systems, Ltd.

Semiconductor device

A semiconductor device with a finfet, which provides enhanced reliability. The semiconductor device includes a first n channel fet and a second n channel fet which are coupled in series between a wiring for output of a 2-input nand circuit and a wiring for a second power potential.
Renesas Electronics Corporation

Semiconductor device manufacturing method and semiconductor device

To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented..
Renesas Electronics Corporation

Method for optimizing dry absorber efficiency and lifetime in epitaxial applications

Increasing efficiency of absorbers is provided herein. In some embodiments, a method of processing a substrate may include determining a quantity of a removal species in an effluent stream flowing from a semiconductor processing chamber, wherein determining comprises: detecting or predicting a quantity of the removal species upstream of a chamber abatement apparatus in the effluent stream flowing from the semiconductor processing chamber; and removing the removal species from the effluent stream with the chamber abatement apparatus if the determined quantity of the removal species exceeds a threshold value of the removal species..
Applied Materials, Inc.

Semiconductor device and manufacturing the same

Semiconductor layer 110 is formed on semiconductor substrate 101. Semiconductor layer 110 has a plurality of well regions 103 in a surface remote from semiconductor substrate 101.
Panasonic Intellectual Property Management Co., Ltd.

Manufacturing system for semiconductor device, manufacturing semiconductor device, and control device

According to an embodiment, a manufacturing system for a semiconductor device includes a first processing device and a second processing device, a measurement section, and an analysis section. The first processing device and the second processing device are adapted to perform a film formation process on a substrate in a wafer.
Toshiba Memory Corporation

Manufacturing semiconductor device, inspection device of semiconductor device, and semiconductor device

A resistance value between a pogo pin and a test pin is measured by bringing a plurality of pogo pins of a socket mounted over a test board included in an inspection device of a semiconductor device into contact with a plurality of solder balls, respectively, and bringing the test pin provided in the socket into contact with a first solder ball of a plurality of solder balls at a position different from a position where the pogo pin is brought into contact with the first solder ball. Thereby, a coupling failure between the pogo pin and the first solder ball is detected, so that a conductive state is inspected..

Semiconductor device and manufacturing the same

A semiconductor device includes at least one n-channel, at least one p-channel, at least one first high-k dielectric sheath, at least one second high-k dielectric sheath, a first metal gate electrode and a second metal gate electrode. The first high-k dielectric sheath surrounds the n-channel.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method for manufacturing cmos structure

The present disclosure relates to a method for manufacturing a cmos structure. A first gate stack is formed on a semiconductor substrate in a first region.
Silergy Semiconductor Technology (hangzhou) Ltd

Vertical transistor top epitaxy source/drain and contact structure

An nfet vertical transistor is provided in which a p-doped top source/drain structure is formed in contact with an n-doped semiconductor region that is present on a topmost surface of a vertical nfet channel. The p-doped top source/drain structure is formed utilizing a low temperature (550° c.
International Business Machines Corporation

Vertical transistor top epitaxy source/drain and contact structure

An nfet vertical transistor is provided in which a p-doped top source/drain structure is formed in contact with an n-doped semiconductor region that is present on a topmost surface of a vertical nfet channel. The p-doped top source/drain structure is formed utilizing a low temperature (550° c.
International Business Machines Corporation

Variable gate lengths for vertical transistors

The method includes prior to depositing a gate on a first vertical fet on a semiconductor substrate, depositing a first layer on the first vertical fet on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical fet on the semiconductor substrate, depositing a second layer on the second vertical fet on the semiconductor substrate.
International Business Machines Corporation

Stacked vertical devices

A semiconductor structure containing a plurality of stacked vertical field effect transistor (fets) is provided. After forming a first vertical fet of a first conductivity type at a lower portion of a semiconductor fin, a second vertical fet of a second conductivity type is formed on top of the first vertical fet.
International Business Machines Corporation

Method to improve cmos device performance

A method for manufacturing a semiconductor device includes providing a substrate including a first device region and a second device region spaced apart from each other, forming a first oxide layer on the first device region and the second device region, forming a second oxide layer below the first oxide layer, forming a mask layer on the first oxide layer on the first device region while exposing the first oxide layer on the second device region, removing the first and second oxide layers on the second device region using the mask layer as a mask, removing the mask layer, and forming a gate oxide layer on the second device region. The thus formed gate oxide layer structure has improved quality and reliability..
Semiconductor Manufacturing International (beijing) Corporation

Method to form hybrid sige fin

A method for manufacturing a semiconductor device includes providing a semiconductor structure having a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a hardmask on a second portion of the dielectric layer while exposing a first portion of the dielectric layer; forming a copolymer on the semiconductor structure; performing an annealing treatment such that the copolymer forms a staggered configuration of a first monomer and a second monomer; removing the first monomer; performing a first etching process on the first portion using the second monomer as a mask to form a first trench extending to the semiconductor substrate; removing the second monomer and the first hardmask; and epitaxially growing a first semiconductor fin in the first trench.. .
Semiconductor Manufacturing International (beijing) Corporation

Semiconductor device and manufacturing method thereof

An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that may achieve low power consumption in a digital circuit and reduce influence of noise in an analog circuit. The manufacturing method of the semiconductor device includes a first source/drain forming step of forming a first source region and a first drain region by implanting impurities of a second conductivity type into a digital side second conductivity type impurity layer using a gate electrode and a sidewall as a mask and a second drain/source forming step of forming a second source region and a second drain region by implanting impurities of the second conductivity type into an analog side second conductivity type impurity layer using a gate electrode and a sidewall as a mask more shallowly than the impurities of the second conductivity type implanted in the first source/drain forming step..
Asahi Kasei Microdevices Corporation

Semiconductor device

A main semiconductor element and a temperature sensing part are arranged on a single silicon carbide base. The main semiconductor element is a vertical mosfet and the temperature sensing part is a horizontal diode.
Fuji Electric Co., Ltd.

Method of manufacturing semiconductor device

According to an embodiment, a method of manufacturing a semiconductor device includes forming a first modified zone in a wafer by irradiating the wafer with a laser having transmissivity with respect to the wafer along a part of a dicing line on the wafer, and forming a second modified zone in the wafer by irradiating the wafer with the laser along the dicing line on the wafer. The first modified zone is partially formed between a surface of the wafer and the second modified zone, a semiconductor interconnect layer being formed on the surface of the wafer..
Toshiba Memory Corporation

Process of forming ohmic electrode on nitride semiconductor material

A process of forming an ohmic electrode containing aluminum (al) on a nitride semiconductor material is disclosed. The process includes steps of: (a) depositing an ohmic metal on the semiconductor material; (b) forming an insulating film such that the insulating film covers a side of the ohmic metal but exposes a top of the ohmic metal; and (c) alloying the ohmic metal at a temperature higher than 500° c.
Sumitomo Electric Device Innovations, Inc.

Reflow interconnect using ru

A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches.
International Business Machines Corporation

Reflow interconnect using ru

A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches.
International Business Machines Corporation

Semiconductor device and formation thereof

A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer.
Taiwan Semiconductor Manufacturing Company Limited

Power semiconductor package having a parallel plate waveguide

A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals.
Infineon Technologies Ag

Semiconductor structure with integrated passive structures

A metal-oxide-semiconductor field-effect transistor (mosfet) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (sti) structure adjacent to the stacked structure.
International Business Machines Corporation

Systems and methods for performing epitaxial smoothing processes on semiconductor structures

Systems and methods for processing semiconductor structures are provided. The methods generally include determining a desired removal map profile for a device layer of a semiconductor structure, determining a set of process parameters for use in an epitaxial smoothing process based on the desired removal map profile, and selectively removing material from the device layer by performing an epitaxial smoothing process on an outer surface of the device layer..
Sunedison Semiconductor Limited

Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers

A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized.
Sunedison Semiconductor Limited (uen201334164h)

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (sti) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the sti, wherein the void is at least partially disposed within the second portion of the sti.. .
Taiwan Semiconductor Manufacturing Company Ltd.

Semiconductor device, making method, and laminate

A semiconductor device is provided comprising a support, an adhesive resin layer, an insulating layer, a redistribution layer, a chip layer, and a mold resin layer. The adhesive resin layer consists of a resin layer (a) comprising a photo-decomposable resin containing a fused ring in its main chain and a resin layer (b) comprising a non-silicone base thermoplastic resin and having a storage elastic modulus e′ of 1-500 mpa at 25° c.
Shin-etsu Chemical Co., Ltd.

Electrostatic chuck assembly incorporating a gasket for distributing rf power to a ceramic embedded electrode

An electrostatic chuck assembly for processing a semiconductor substrate is provided. The electrostatic chuck assembly includes a first layer, a baseplate, a second layer, and at least one annular gasket.
Lam Research Corporation

Substrate processing device and manufacturing semiconductor device

A substrate processing device capable of stabilizing an etching amount of a metal film provided on a substrate is provided. The substrate processing device includes a first container, a second container and a control unit.
Toshiba Memory Corporation

Substrate treatment apparatus and manufacturing semiconductor device

According to an embodiment, a substrate treatment apparatus includes a vacuum chamber, a cylindrical member, a gas feed member, a support member and a plurality of plate members. The cylindrical member is disposed in the vacuum chamber and includes a gas outlet.
Toshiba Memory Corporation

Semiconductor manufacturing apparatus

According to an embodiment, a semiconductor manufacturing apparatus includes a process chamber, a load lock chamber, a gas purge mechanism and a movement mechanism. The process chamber treats a substrate using process gas in a vacuum state.
Toshiba Memory Corporation

Manufacturing semiconductor device and semiconductor device

In a manufacturing method of a semiconductor device, by arranging a lead in the vicinity of a gate portion serving as a resin injection port of a mold, a void is prevented from remaining within an encapsulation body when two semiconductor chips arranged so as to overlap in the y direction are encapsulated with resin. Further, a length of an inner lead portion of the lead in the y direction is greater than a length of an inner lead portion of another lead overlapping a chip mounting portion in the y direction..
Renesas Electronics Corporation

Semiconductor device with tiered pillar and manufacturing method thereof

A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers.
Amkor Technology, Inc.

Method of manufacturing semiconductor device

In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed.
Semiconductor Energy Laboratory Co., Ltd.

Method for manufacturing a semiconductor device comprising etching a semiconductor material

According to embodiments, a method for manufacturing a semiconductor device includes forming a mask comprising a pattern of inert structures on a side of a first main surface of a semiconductor substrate. A semiconductor layer is formed over the first main surface, and the semiconductor substrate is thinned from a second main surface opposite to the first main surface.
Infineon Technologies Ag

Heating method, film forming method, semiconductor device manufacturing method, and film forming apparatus

There is provided heating method for heating a substrate having a germanium film or a silicon germanium film formed on a surface of the substrate, the method including: loading the substrate kept in an air atmosphere at least a predetermined time into a processing container; and heating the substrate in a state in which an interior of the processing container is kept in a hydrogen gas-containing atmosphere.. .
Tokyo Electron Limited

Manufacturing semiconductor device and semiconductor manufacturing apparatus

A manufacturing method of a semiconductor device according to an embodiment implants impurities into a central portion of a polishing target film or an outer peripheral portion of the central portion of the polishing target film to cause an impurity concentration in the outer peripheral portion of the polishing target film and an impurity concentration in the central portion thereof to be different from each other, thereby modifying a surface of the polishing target film. The modified surface of the polishing target film is polished by a cmp method..
Toshiba Memory Corporation

Fluid dispense methodology and imprint lithography

A method of can be used to generating a fluid droplet pattern for an imprint lithography process. A fluid dispense head can include a set of fluid dispense ports, wherein the fluid dispense ports are in a fixed arrangement.
Canon Kabushiki Kaisha

Planarization method

A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer.
Fujian Jinhua Integrated Circuit Co., Ltd.

Method of planarizing semiconductor device

A method of planarizing a semiconductor device includes forming a first region and a second region on a semiconductor substrate. The first region has a larger thickness than a thickness of the second region.
Taiwan Semiconductor Manufacturing Co., Ltd.

Planarization processing device

A planarization processing device for polishing a substrate, e.g., a semiconductor wafer, includes two planarization processing sections (sp1, sp2) that each include a holder (62) for holding a workpiece (w), a drive motor (71) that rotates the holder (62), a support plate (4) holds a pad (5), a linear guide (3) that guides reciprocal movement of the support plate (4) in a direction parallel to the surface of the pad (5), and a drive cylinder (72) that advances the holder (62) or the support plate (4) in a direction that intersects the surface of the workpiece w or the pad (5) to cause the opposing surfaces of the workpiece and the pad (5) to be at least proximal to each other. A primary driver (pd) causes the support plates (4) of the planarization processing sections (sp1, sp2) to reciprocate along the same straight line in opposite phases..
Toho Engineering Co., Ltd.

Manufacturing a semiconductor device

A manufacturing method of a semiconductor device comprises forming an ohmic electrode on a surface of a semiconductor substrate, the ohmic electrode including an aluminum layer in a side opposite to a side in contact with the semiconductor substrate, performing a heat treatment on the ohmic electrode, performing an acid treatment on a surface of the aluminum layer in the ohmic electrode that has been subjected to the heat treatment and forming a wiring electrode in the side of the aluminum layer opposite to the side where the semiconductor substrate is provided after the acid treatment.. .
Toyoda Gosei Co., Ltd.

Semiconductor device structures including two-dimensional material structures, and related semiconductor devices and electronic systems

A method of forming a semiconductor device structure comprises forming at least one 2d material over a substrate. The at least one 2d material is treated with at least one laser beam having a frequency of electromagnetic radiation corresponding to a resonant frequency of crystalline defects within the at least one 2d material to selectively energize and remove the crystalline defects from the at least one 2d material.
Micron Technology, Inc.

Semiconductor power device and producing same

A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench.
Rohm Co., Ltd.

Rework of patterned dielectric and metal hardmask films

A method for reworking a semiconductor device includes, in a pattern stack formed on an interlevel dielectric (ild) layer, polishing the pattern stack to remove a top hardmask layer of the pattern stack. Each hardmask layer of the pattern stack is selectively wet etched to remaining layers of the pattern stack and the ild layer.
International Business Machines Corporation

Post growth heteroepitaxial layer separation for defect reduction in heteroepitaxial films

A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings.
International Business Machines Corporation

Post growth heteroepitaxial layer separation for defect reduction in heteroepitaxial films

A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings.
International Business Machines Corporation

Femtosecond laser-induced formation of single crystal patterned semiconductor surface

The interaction between multiple intense ultrashort laser pulses and solids typically produces a regular nanoscale surface corrugation. A coupled mechanism has been identified that operates in a specific range of fluences in gaas that exhibits transient loss of the imaginary part of the dielectric function and x2, which produces a unique corrugation known as high spatial frequency laser induced periodic surface structures (hsfl).
The Regents Of The University Of Michigan

Method of manufacturing semiconductor device, substrate processing apparatus and recording medium

There is provided a technique that includes (a) pre-etching a surface of a substrate made of single crystal silicon by supplying a first etching gas to the substrate; (b) forming a silicon film on the substrate with the pre-etched surface, by supplying a first silicon-containing gas to the substrate; (c) etching a portion of the silicon film by supplying a second etching gas, which has a different molecular structure from a molecular structure of the first etching gas, to the substrate; and (d) forming an additional silicon film on the etched silicon film by supplying a second silicon-containing gas to the substrate.. .
Hitachi Kokusai Electric Inc.

Compound semiconductor substrate with sic layer

A compound semiconductor substrate has an sic (silicon carbide) layer, an aln (aluminum nitride) buffer layer formed on the sic layer, an al (aluminum) nitride semiconductor layer formed on the aln buffer layer, a first gan (gallium nitride) layer formed on the al nitride semiconductor layer, a first aln intermediate layer formed on the first gan layer in contact with the first gan layer, and a second gan layer formed on the first aln intermediate layer in contact with the first aln intermediate layer.. .

Under layer composition and manufacturing semiconductor device

Under layer composition and methods of manufacturing semiconductor devices are disclosed. The method of manufacturing semiconductor device includes the following steps.
Taiwan Semiconductor Manufacturing Co., Ltd.

Surface treatment methods and compositions therefor

The disclosure provides methods and compositions therefor for treating a surface wherein a surface treatment layer is formed on the surface, thereby minimizing or preventing pattern collapse as the surface is subjected to typical cleaning steps in the semiconductor manufacturing process.. .
Fujifilm Electronic Materials U.s.a., Inc.

Substrate processing apparatus, manufacturing semiconductor device, and recording medium

There is provided a technique that includes a process chamber in which a process is performed to a substrate, the process including forming a film containing a main element, a first nozzle configured to supply a precursor containing the main element to the substrate in the process chamber, and a second nozzle configured to supply a reactant to the substrate in the process chamber. The first nozzle includes a first ceiling hole provided at a ceiling portion of the first nozzle and opened in a vertical direction, and a plurality of first side holes provided at a side portion of the first nozzle and opened in a horizontal direction.
Hitachi Kokusai Electric Inc.

Semiconductor structure and forming the same

A method of forming a semiconductor structure is disclosed. A substrate is provided with a pad metal and a fuse metal formed thereon.
Fujian Jinhua Integrated Circuit Co., Ltd.

Semiconductor device and semiconductor device manufacturing method

A semiconductor device manufacturing method according to one embodiment includes the steps of: forming a gate insulator on a surface of a semiconductor substrate; forming at least one semiconductor element on the surface of the semiconductor substrate, the semiconductor element including a source region, a drain region, and a gate electrode; forming a first film on the surface of the semiconductor substrate; and cleaning the semiconductor substrate with an acid solution. The first film is made of a material that is oppositely charged with respect to a material constituting the semiconductor substrate in the acid solution.
Renesas Electronics Corporation

Semiconductor device and diagnostic method therefor

An address generation circuit generates a target address to be tested in a memory. A test data generation circuit generates write data for the address and expected value data for read data from the address.
Renesas Electronics Corporation

Automated semiconductor platform testing

The present disclosure is directed to systems and methods for autonomously generating test methods for testing features included on semiconductor platforms. The systems and methods described herein either manually or autonomously receive information and/or data indicative of the features included in, on, or about a semiconductor platform to be tested.
Intel Corporation

Semiconductor storage device

A word-line controller applies a voltage to a selected word-line. A bit-line controller applies voltages to bit-lines.
Toshiba Memory Corporation

Memory system

According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory is configured to execute a first to third read operations.
Toshiba Memory Corporation

Semiconductor memory device and read control method thereof

A semiconductor memory device includes a nonvolatile memory and a controller. The nonvolatile memory has a plurality of memory cells that are connected to word lines to which a read voltage is applied at the time of reading data stored in the memory cells.
Toshiba Memory Corporation

Memory system

According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range.
Toshiba Memory Corporation

Semiconductor memory device

A semiconductor memory device includes a memory cell array, a temperature sensor that generates a first voltage which is based on a temperature of the semiconductor memory device, compares the first voltage with a second voltage that is based on a result of previous temperature measurement, and generates a voltage generation signal based on a result of comparing the first voltage with the second voltage, and a voltage generating circuit that generates a voltage applied to the memory cell array based on the voltage generation signal.. .
Toshiba Memory Corporation

Semiconductor memory device

The controller determines an (n+k)-th (where n is an integer not less than 1 and k is an integer not less than 2) verify operation based on comparison between an n-th verify operation and an (n+1)-th verify operation in the write sequence.. .

Method for controlling memory device

A memory device includes stacked word lines stacked and a semiconductor channel passing through the word lines in a first direction. Memory cells are disposed along the semiconductor channel in the first direction.
Toshiba Memory Corporation

Semiconductor memory device

A semiconductor memory device includes memory cell transistors, a word line connected to the plurality of memory cell transistors, bit lines that are respectively connected to the memory cell transistors, and a control circuit. The control circuit carries out a write operation on the memory cell transistors connected to the word line by performing, in sequence, a first loop of operations, including a first program operation followed by at least one verification operation, that are carried out until all memory cell transistors targeted by the first program operation have passed the at least one verification operation, a second loop of operations, including a second program operation and no verification operation, that are carried out for a fixed number of loops and a third loop of operations, including a third program operation and no verification operation, that are carried out for a fixed number of loops..
Toshiba Memory Corporation

Semiconductor memory device

The present embodiment discloses a semiconductor memory device which includes a memory cell array, a signal pad, a first voltage pad, a first regulation circuit and a first operation circuit. The signal pad supplies an output signal associated with the memory cell array.
Toshiba Memory Corporation

Semiconductor storage device

A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line..
Toshiba Memory Corporation

Semiconductor memory device

A semiconductor memory device includes a plurality of blocks of memory cells, including first, second, and third blocks of a first group of blocks and fourth fifth and sixth blocks of a second group of blocks, a plurality of word lines for each of the blocks, a first decode circuit for the first group, and a second decode circuit for the second group. When the first block is selected, the first decode circuit transfers a first voltage to the word lines of the first block, transfers a second voltage lower than the first voltage to the word lines of the second block, and causes the word lines of the third block to go into an electrically floating state, and the second decode circuit causes the words lines of the fourth block, the fifth block, and the sixth block into the electrically floating state..
Toshiba Memory Corporation

Semiconductor device

According to one embodiment, a semiconductor device includes: a first memory cell provided in a first semiconductor chip; a first output buffer circuit configured to output data of the first memory cell outside, the first output buffer circuit provided in the first semiconductor chip; a first calibration control circuit configured to calibrate an impedance of the first output buffer circuit, a first terminal connected to the first calibration control circuit, the first calibration control circuit provided in the first semiconductor chip; and a first resistance element connected to the first terminal, the first resistance element provided in the first semiconductor chip.. .
Toshiba Memory Corporation

Semiconductor integrated circuit

According to one embodiment, a semiconductor integrated circuit includes a rom, an sram, a memory and a selector. The rom stores initialization data.
Kabushiki Kaisha Toshiba

Variable resistance memory

A semiconductor device according to an embodiment includes a memory cell array and a drive circuit section. The memory cell array includes memory cells.
Toshiba Memory Corporation

Semiconductor memory device

A semiconductor memory device includes a first conductor extending in a first direction and a second conductor extending in a second direction and disposed above the first conductor in a third direction. Third and fourth conductors extend in the first direction and adjacent to each other in the second direction.
Toshiba Memory Corporation

Semiconductor memory device

A semiconductor memory device includes a first memory cell having a first end connected to a first wiring and a second end connected to a second wiring and a second memory cell having a first end connected to the first wiring and a second end connected to a third wiring. A sense amplifier is configured to: sense a first current flowing in the first wiring when a first voltage is applied to the second and third wirings and a second voltage, larger than the first voltage, is applied to the first wiring; and sense a second current flowing in the first wiring when a third voltage larger than the second voltage is applied to the first wiring, the first voltage to the second wiring, and the second voltage to the third wiring.
Toshiba Memory Corporation

Semiconductor memory with respective power voltages for memory cells

A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit us configured to provide the first power voltage for the plurality of first memory cells, and to provide the second power voltage, that is independent from the first power voltage, for the plurality of second memory cells.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device and apparatus including the same

A semiconductor device includes a programmable memory array comprising plural memory units disposed above a substrate. One of the memory units comprises a gate electrode disposed above the substrate, a conductive portion spaced apart from the gate electrode, and a dielectric layer contacting the conductive portion and separated from the gate electrode, and the dielectric layer defining a threshold voltage of the related memory unit, wherein at least two of the memory units have different threshold voltages..
Macronix International Co., Ltd.

Timing control for input receiver

Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information signal; a control circuit that provides a plurality of control signals; and a signal receiver replica circuit that receives a first reference signal.
Micron Technology, Inc.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a memory cell including a transistor formed of an oxide semiconductor, an insulation film, and a control electrode, and a capacitance element configured to store a charge, the memory cell being configured to store a coupling weight of a neuron model by a charge amount accumulated in the capacitance element; and a control circuit configured to output a signal as a sum of a product between input data of the memory cell and the coupling weight.. .
Toshiba Memory Corporation

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first memory cell having a first variable resistance element, a second memory cell having a second variable resistance element, and a first circuit which controls writing to the first memory cell and the second memory cell. The first circuit receives a fir command instructing writing to the first memory cell, after receiving the first command, receives a second command instructing writing to the second memory cell, and after receiving the second command, performs writing to the second memory cell when performing writing to the first memory cell..
Toshiba Memory Corporation

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first memory cell including a first resistance change memory element and a first transistor, a first word line electrically coupled to a control terminal of the first transistor, and a first circuit configured to, in a reading, apply a first voltage to the first word line during a first period and apply a second voltage higher than the first voltage to the first word line during a second period after the first period.. .
Toshiba Memory Corporation

Memory system

A memory system includes a semiconductor memory and a controller. The controller is configured to perform a read operation on the semiconductor memory in response to a read instruction received from a host.
Toshiba Memory Corporation

Semiconductor device

A semiconductor device includes a buffer control circuit suitable for generating a buffer control signal in response to a power-down mode signal and a detection pulse, a first buffer circuit suitable for generating a first internal chip select signal by buffering a chip select signal depending on a select signal which is generated in response to the buffer control signal in a power-down mode, and a detection pulse generation circuit suitable for generating the detection pulse in response to the first internal chip select signal.. .
Sk Hynix Inc.

Semiconductor layered device with data bus

Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array..
Micron Technology, Inc.

Semiconductor memory device

A semiconductor memory device includes a power source pad, a first bank including a plurality of memory cells, a second bank including a plurality of memory cells, the first bank being sandwiched between the power source pad and the second bank, first power supply lines connected to the power source pad and supplying power to the first bank and not to the second bank, and second power supply lines connected to the power source pad, passing over the first bank, and supplying power to the second bank and not to the first bank.. .
Toshiba Memory Corporation

Semiconductor device and electronic equipment

According to one embodiment, a semiconductor device includes an input/output circuit to which a signal is input or from which a signal is output; a first terminal connected to a power line of the input/output circuit; a second terminal connected to the power line; a resistance element connected between the second terminal and the power line; and a first capacitance element connected between the second terminal and a ground terminal.. .
Toshiba Memory Corporation

Field-effect transistor, display element, image display device, and system

A field-effect transistor including: a substrate; a passivation layer; a gate insulating layer, formed between the substrate and passivation layer; a source electrode and a drain electrode, formed to be in contact with the gate insulating layer; a semiconductor layer, formed at least between the source electrode and drain electrode and being in contact with the gate insulating layer, source electrode, and drain electrode; and a gate electrode, in contact with the gate insulating layer and facing the semiconductor layer via the gate insulating layer, wherein the passivation layer is formed of a single layer containing a paraelectric amorphous oxide containing a group a element, an alkaline earth metal and a group b element, at least one selected from ga, sc, y, and lanthanoid, and the gate insulating layer contains at least one selected from oxides of si, nitrides of si, and oxynitrides of si.. .
Ricoh Company, Ltd.

Semiconductor device and controller for asynchronous serial communication, and asynchronous serial communication method and system

The present invention discloses an asynchronous serial communication system and method. The asynchronous serial communication system may include a semiconductor device having two terminals and configured to receive a voltage required for an operation from data transmitted through one terminal; and a controller configured to perform asynchronous serial communication with the semiconductor device with two terminals.
Duality Inc.

Monitoring circuit

Provided is a monitoring circuit equipped with a first abnormality detection circuit which detects a first abnormal state of a semiconductor device under surveillance, a second abnormality detection circuit which detects a second abnormal state of the semiconductor device under surveillance, a reset circuit which outputs a reset signal based on a logical sum of a first abnormality detection signal output from the first abnormality detection circuit and a second abnormality detection signal output from the second abnormality detection circuit to a first output terminal, and an output holding circuit which stores which of the first abnormality detection signal and the second abnormality detection signal is supplied, and outputs an abnormality discrimination signal corresponding thereto to a second output terminal.. .
Ablic Inc.

Semiconductor storage device

According to an embodiment, a semiconductor storage device includes a detection circuit configured to detect an error in data read from a first memory cell array. The read data of a size corresponding to a page unit is subjected to detection of an error for each of a plurality of first units into which the page unit is divided.
Toshiba Memory Corporation

Semiconductor memory device

A semiconductor memory device includes a memory cell array including a plurality of planes that are independently operable, a plurality of first output terminals through which data read from the memory cell array are output, a second output terminal through which a ready/busy signal indicating a ready/busy state of the memory cell array is output, a control circuit configured to generate a first signal indicating a ready/busy state of each of the plurality of planes, and a signal converter configured to convert the first signal to a second signal indicating a ready/busy state of each of the plurality of planes, the second signal being output through the second output terminal.. .
Toshiba Memory Corporation

Memory system and data relocating method

A memory system includes a nonvolatile semiconductor memory and a memory controller circuit. The memory controller circuit selects first and second blocks of the nonvolatile semiconductor memory, the first block being a garbage collection target block, the second block being a wear leveling target block or a refresh target block, relocates first data which is valid data stored in the first block in a series of write operations to a third block including first and second write operations, the third block being a block of the nonvolatile semiconductor memory having a free region, and relocates second data which is valid data stored in the second block in a series of write operations to a fourth block including a third write operation, the fourth block having a free region and being different from the third block, wherein the third write operation is performed between the first and second write operations..
Toshiba Memory Corporation

Standard voltage circuit and semiconductor integrated circuit

A standard voltage circuit includes an operational amplifier, first and second diodes, a resistance element, and a dummy leak generation circuit. The first diode is electrically connected to a first node of a first line which is disposed on an output terminal side of the operation amplifier and is electrically connected to a first input terminal of the operation amplifier through the first node.
Toshiba Memory Corporation

Semiconductor circuit

A semiconductor circuit converts an applied input voltage into a desired output voltage and outputs the same from a voltage output terminal. A first resistor, a second resistor, and a third resistor are connected in series between the voltage output terminal and a ground terminal.
Ablic Inc.

Optimization method and seystem for overlay error compensation

An optimization method for overlay error compensation is disclosed. The method comprises setting process parameters for each semiconductor layer of a semiconductor device corresponding to a run path formed by different lithographic apparatus which sequentially process target semiconductor layers from a first target layer to a latest target layer; measuring overlay errors between an actual and a theoretical exposed patterns of the first semiconductor layer; selecting a group of process parameters corresponding to the run path from the first target layer to the latest target layer aligned by the current semiconductor layer; after exposing the current semiconductor layer using the selected process parameters, measuring overlay errors between the current semiconductor layer and its target layer; and correcting the selected process parameters according to the overlay errors between the current semiconductor layer and its target layer, and the overlay errors between the actual and theoretical exposed patterns of the first semiconductor layer..
Shanghai Huali Microelectronics Corporation

Mask blank substrate, substrate with multilayer reflection film, transmissive mask blank, reflective mask, and semiconductor device fabrication method

Disclosed is a mask blank substrate for use in lithography, wherein the main surface on which the transfer pattern of the substrate is formed has a root mean square roughness (rms) of not more than 0.15 nm obtained by measuring an area of 1 μm×1 μm with an atomic force microscope, and has a power spectrum density of not more than 10 nm4 at a spatial frequency of not less than 1 μm−1.. .
Hoya Corporation

Semiconductor optical element and manufacturing the same

A semiconductor optical element is disclosed. The semiconductor optical element includes: a mesa-shaped optical waveguide formed on a substrate; a modulation electrode formed on the optical waveguide; a first resin layer that buries side surfaces of the optical waveguide; a bonding pad formed on the first resin layer; and a connecting wiring line that connects the modulation electrode and the bonding pad.
Sumitomo Electric Industries, Ltd.

Display device

An object is to provide a display device that performs accurate display. A circuit is formed using a transistor that includes an oxide semiconductor and has a low off-state current.
Semiconductor Energy Laboratory Co., Ltd.

Personal ladar sensor

A ladar sensor assembly includes a semiconductor laser and a diffusing optic for illuminating a field of view utilizing modulated laser light from the semiconductor laser. A lens is configured to receive the modulated laser light reflected off at least one object.
Continental Advanced Lidar Solutions Us, Llc

Semiconductor integrated circuit and semiconductor integrated circuit diagnosis method

A semiconductor device according to an embodiment includes a plurality of scan chains each including a retention flip-flop, and a control section configured to perform restoration of data saved in a retention section of each retention flip-flop by reading the data from the retention section and after the data restoration, perform diagnosis of the retention flip-flops by performing comparison to determine whether or not an expected value of an output data string obtained as a result of a scan shift in the plurality of scan chains before the save and a value of an output data string obtained as a result of a scan shift of data in the plurality of scan chains after the restoration.. .
Kabushiki Kaisha Toshiba

Semiconductor integrated circuit and test method thereof

According to one embodiment, a semiconductor integrated circuit comprises: a tested block including a test control circuit; and a control circuit configured to output a first signal. The test control circuit performs a test of at least a first test pattern of the test patterns for the scan chain in accordance with the first signal during a first non-access state period of the tested block, and performs a test of at least a second test pattern following the first test pattern of the test patterns for the scan chain in accordance with the first signal during a second non-access state period of the tested block, and the test of the first test pattern and the test of the second test pattern are performed discontinuously..
Kabushiki Kaisha Toshiba

Apparatus for super-fine pitch integrated circuit testing and methods of constructing

An apparatus, including methods of construction and use, for super-fine pitch integrated circuit testing is disclosed. The apparatus includes a substrate of one or more redistribution layers (rdls), a plurality of vertical interconnect access (via) columns, a material that backs the substrate, and another material that protects the plurality of via columns.
Marvell World Trade Ltd.

Method of carrier profiling in semiconductors

The superimposition of a periodic potential wave to the tip movement control or the bias supply of an stm, in which a microwave frequency comb is generated in its tunneling junction, may be used to reduce or eliminate artifacts or other noise generated from outside the tunneling junction.. .

Semiconductor device inspection of metallic discontinuities

Concepts presented herein relate to approaches for performing substrate inspection. In one aspect, the concepts relate to detecting anomalies or candidate defects on the substrate based on contrast in images obtained of the substrate..
Rudolph Technologies, Inc.

Semiconductor sensor device and manufacturing same

To provide a high-performance semiconductor sensor device and a method for manufacturing the semiconductor sensor device. This semiconductor sensor device has a sensor chip, and a first thin film formed on the sensor chip, said sensor chip being mechanically connected, via the first thin film, to a second thin film formed on a base formed of a polycrystalline material..
Hitachi Automotive Systems, Ltd.

Semiconductor wafer support ring for heat treatment

A support ring for supporting a semiconductor wafer in a boat of a vertical furnace used in processing of the semiconductor wafer includes a semicircular segment. The semicircular segment has an upper surface, a lower surface opposite the upper surface, a radial inner wall defining an inner radius, and a radial outer wall defining an outer radius.
Globalwafers Co., Ltd.

Substrate processing apparatus, manufacturing semiconductor device, and recording medium

There is provided a technique that includes: a process chamber in which a process of forming a film containing a main element on a substrate is performed; a first nozzle configured to supply a precursor containing the main element to the substrate in the process chart; a second nozzle separated from the first nozzle and configured to supply the precursor to the substrate in the process chamber; a third nozzle configured to supply a reactant to the substrate in the process chamber; and a plurality of first exhaust ports configured to exhaust an internal atmosphere of the process chamber, wherein each of the plurality of first exhaust ports is disposed at a position which does not face a first gas ejection hole of the first nozzle and a second gas ejection hole of the second nozzle, in a plan view.. .
Hitachi Kokusai Electric Inc.

Semiconductor manufacturing apparatus and manufacturing semiconductor device

A semiconductor manufacturing apparatus includes a reaction chamber configured to perform a process on a semiconductor substrate using a gas mixture comprising a first gas, and a first path configured to exhaust resultant gas that comprises the first gas from the reaction chamber. The semiconductor manufacturing apparatus further includes a first trap provided in the first path and configured to extract at least a portion of the first gas from the resultant gas, and a second path in which the trap is not provided and configured to exhaust the resultant gas from the reaction chamber..
Toshiba Memory Corporation

Method for manufacturing nitride semiconductor substrate

A method for manufacturing a nitride semiconductor substrate includes: a preparation step of preparing a sapphire substrate; and a buffer layer forming step of forming an aln buffer layer on the sapphire substrate, wherein the buffer layer forming step includes: a group iii nitride semiconductor forming step of forming a precursor of an aln buffer layer on the sapphire substrate; and an annealing step of annealing the sapphire substrate on which the precursor of the aln buffer layer is formed in a gas-tight state in which a principal surface of the precursor of the aln buffer layer is covered with a cover member (such as a sapphire substrate) for inhibiting a component of the group iii nitride semiconductor from dissociating from the principal surface of the formed precursor of the aln buffer layer.. .
Mie University

Semiconductor light emitting device, backlight, color image display device and phosphor to be used for them

A light source provided on a backlight for a color image display device has a semiconductor light emitting device comprising a solid light emitting device to emit light in a blue or deep blue region or in an ultraviolet region and phosphors, in combination. The phosphors comprise a green emitting phosphor and a red emitting phosphor.

Method for preparing semiconductor nanocrystal siloxane composite resin composition

The present invention relates to a method for preparing a semiconductor nanocrystal siloxane composite resin composition, and a cured product using the same. In the preparation method, the semiconductor nanocrystals are added during a non-hydrolytic sol-gel condensation reaction for forming a siloxane structure so that a siloxane resin having a dense inorganic network, which includes a siloxane bond, is encapsulated and thus is dispersed in the semiconductor nanocrystals through a chemical interaction and a chemical bond, thereby preventing a reduction in inherent characteristics (quantum efficiency) of the semiconductor nanocrystals resulting from an external oxidizing environment.
Korea Advanced Institute Of Science And Technology

Method and system for providing ultrapure water with flexible lamp configuration

A method and system of providing ultrapure water for semiconductor fabrication operations is provided. The water is treated by utilizing a free radical scavenging system.
Evoqua Water Technologies Llc

Precision approach path indicator with a novel reflector arrangement

A compact papi having a semiconductor light source and finely distribution of lights is herein proposed. The novel papi includes two artificial light sources each with a plurality of semiconductor emitters as well as two concave and two planar reflectors, one for each artificial light source.
Obelux Oy

Optoelectronic semiconductor component and 3d printer

An optoelectronic semiconductor component and a 3d printer are disclosed. In an embodiment the component includes a carrier, a plurality of individually controllable pixels configured to emit radiation during operation, wherein the plurality of individual pixels is mounted on the carrier and is formed from at least one semiconductor material and a plurality of transport channels configured to transport a gas or a liquid through the semiconductor component in a direction transverse to and towards a radiation exit side of the semiconductor component, wherein the pixels are configured to emit radiation having a wavelength of maximum intensity of 470 nm or less, and wherein all pixels include the same semiconductor layer sequence and emit radiation of the same wavelength..
Osram Opto Semiconductors Gmbh

Cleaning compositions for removing residues on semiconductor substrates

This disclosure relates to a cleaning composition that contains 1) at least one redox agent; 2) at least one water soluble organic solvent; 3) at least one metal-containing additive; 4) at least one cyclic amine, and 5) water.. .
Fujifilm Electronic Materials U.s.a., Inc.

Device and flow and bead speed characterization in microfluidic devices

Method, apparatus, and computer program product for a microfluidic channel having a cover opposite its bottom, such that the cover allows visual inspection inside the channel, and having electrodes with patterned planar conducting materials, integrated onto its bottom. Using the planar conducting materials, once a fluid sample with suspended microparticles is applied into the channel, highly localized modulated electric field distributions are generated inside the channel and the fluid sample.
International Business Machines Corporation

High resolution brain-electronics interface

Aspects include high resolution brain-electronic interfaces and related methods. Aspects include forming a semiconductor circuit on a substrate, depositing a tensile stress layer on the circuit, and separating the semiconductor circuit from a portion of the silicon substrate.
International Business Machines Corporation

Semiconductor device

A semiconductor device includes a mounting substrate including an interface, which is connectable with a host, a surface-mounted component mounted on the mounting substrate and having first and second electrode groups, a first solder portion that is positioned between a first electrode in the first electrode group and the mounting substrate to electrically connect the first electrode and the mounting substrate, and a second solder portion that is positioned between a second electrode in the second electrode group and the mounting substrate to electrically connect the second electrode and the mounting substrate. The second solder portion has a larger contact area with the mounting substrate than the first solder portion.
Toshiba Memory Corporation

Device and controlling light sources of a motor vehicle

A system for supplying electrical power to at least one semiconductor-element-including light source of a motor vehicle. The system includes a mechanism controlling the supply of electrical power to the light source and being configured to deliver an electrical current to the light source.
Valeo Vision

Back-illuminated global-shutter image sensor

A global shutter image sensor of a back-illuminated type includes a semiconductor substrate and pixels. Each pixel includes a photosensitive area, a storage area, a readout area and areas for transferring charges between these different areas.
Stmicroelectronics (crolles 2) Sas

Pixel circuit, semiconductor camera detection circuit and display device

A pixel circuit, a semiconductor camera detection circuit and a display device. The pixel circuit includes: a photodiode, a driving circuit, an initialization circuit, a transmission circuit, a voltage write-in circuit (2 and a compensation circuit.
Boe Technology Group Co., Ltd.

Semiconductor device

A semiconductor device may be provided. The semiconductor device may include an input and output (i/o) circuit configured to output transfer data generated from input data as internal data based on a write enablement signal and configured to output error information on the input data based on the write enablement signal.
Sk Hynix Inc.

Oscillator, semiconductor device and wireless communication apparatus

An oscillator has an oscillator, an integer phase detector, a random number generator, an edge selector, a fractional phase detector, an offset correction arithmetic unit, and a phase error generator. The oscillator generates an oscillation signal having an oscillation frequency in accordance with a phase error signal.
Kabushiki Kaisha Toshiba

Transistor device

Transistor devices are described that include a first transistor and a second transistor coupled in parallel between a first terminal and a second terminal. The second transistor is based on a wide bandgap semiconductor material.
Infineon Technologies Ag

Circuit tuning scheme for fdsoi

A method of circuit tuning, including: applying a first positive voltage and a second positive voltage to a circuit structure, the circuit structure including a p-type metal-oxide semiconductor (pmos) device with a flipped well transistor and an n-type metal-oxide semiconductor (nmos) device; adjusting a first threshold voltage in response to the first positive voltage being applied to a p-well region of the nmos device and adjusting a second threshold voltage in response to the second positive voltage being applied to the p-well region of the pmos device; and compensating the first threshold voltage and the second threshold voltage through a backgate of the pmos device and the nmos device relative to a same common mode voltage.. .
Global Foundries Inc.

Drive device for semiconductor element

A drive device for a semiconductor element includes a drive circuit receiving from outside a pulsed drive signal for driving on/off of the semiconductor element; and a protection circuit receiving a signal representing a chip temperature of the semiconductor element and, when the detected chip temperature exceeds an overheating threshold temperature, controlling operation of the drive circuit so as to adjust a drive control voltage that is provided to the semiconductor element; and a drive information output circuit externally outputting drive information corresponding to the adjusted drive control voltage that is provided to the semiconductor element by the drive circuit.. .
Fuji Electric Co., Ltd.

Overvoltage protection

A drive device adapted to drive a semiconductor power device, wherein the drive device comprises a drive circuit comprising a first terminal adapted for connection to a first terminal of the power device, a gate terminal adapted to provide a driving signal for a gate terminal of the power device, a sensor for detecting overvoltage conditions at the first terminal of the power device, and wherein the drive circuit is adapted to modify the driving signal when the sensor detects an indication of an overvoltage condition, and wherein the drive circuit including the sensor is integrated onto a single substrate.. .
Infineon Technologies Ag

Semiconductor device

A semiconductor device including a first control circuit, a memory and a second control circuit. The first control circuit includes a monitoring section which receives a voltage signal which includes a pulse signal having a plurality of different voltage levels superimposed on a power source voltage, monitors a level of the voltage signal and outputs a monitoring result, and a regulator which generates an internal voltage.
Fuji Electric Co., Ltd.

Intelligent power modules for resonant converters

An intelligent power module includes a power switch, a freewheeling device, and a controller circuit incorporating a gate drive circuit and one or more power switch protection circuits. In one embodiment, the power switch is an insulated gate bipolar transistor (igbt) device, the freewheeling device is a pn junction diode, and the controller circuit is implemented as a semiconductor integrated circuit (ic).
Alpha And Omega Semiconductor (cayman) Ltd.

Semiconductor device

A semiconductor device includes: a semiconductor chip including a level shift circuit to output a high amplitude signal from an input of a logical signal, the level shift circuit including a series coupling circuit coupled to a second power supply, a control circuit coupled to the series coupling circuit for controlling the series coupling circuit based on the logical signal, and a first potential conversion circuit coupled between the series coupling circuit and the control circuit and coupled to a first power supply. The series coupling circuit includes a plurality of first mos transistors coupled in series between the second power supply and a reference power supply, and a plurality of second mos transistors coupled in series between the second power supply and the reference power supply in series with the plurality of first mos transistors..
Renesas Electronics Corporation

Semiconductor device

A semiconductor device includes a first mode signal generation circuit suitable for generating a first mode signal in response to a command, the first mode signal being enabled in the case where a first period determined depending on a current characteristic of a first mos transistor is longer than a second period determined by a first passive element; and a second mode signal generation circuit suitable for generating a second mode signal in response to the command, the second mode signal being enabled in the case where a third period determined by a second passive element is longer than a fourth period determined depending on a current characteristic of a second mos transistor.. .
Sk Hynix Inc.

Reflection type phase shifter with active device tuning

A phase shifter includes first and second rf terminals, a reference potential terminal; a lumped element lc network connected to the first and second rf terminals and the reference potential terminal, and first and second active semiconductor devices connected to the lumped element lc network and to the reference potential terminal. Each of the first and second active semiconductor devices include a control terminal and first and second output terminals.
Infineon Technologies Ag

Brushless electric motor

A brushless electric motor of a motor vehicle, in particular an ancillary unit, including a first phase winding, which is connected in series to a first semiconductor switch, and including a second phase winding, which is connected in series to a second semiconductor switch. The brushless electric motor includes a test circuit, which is connected in parallel to the first semiconductor switch and the second semiconductor switch.
Brose Fahrzeugteile Gmbh & Co. Kommanditgesellschaft, Bamberg

Control of parallel connected power devices

A method and arrangement for controlling semiconductor power switches, e.g. Igbts, in parallel connected power devices, e.g.
Vacon Oy

Power conversion apparatus

A power conversion apparatus is provided in which an upper arm semiconductor device, a lower arm semiconductor device and a capacitor. At least either upper arm semiconductor device or lower arm semiconductor device constitutes a parallel-connected body.
Denso Corporation

Semiconductor integrated circuit device and power supply system

A semiconductor integrated circuit device includes a first voltage terminal, a second voltage terminal, an output terminal, a high-side mosfet connected between the first voltage terminal and the output terminal, a low-side mosfet connected between the output terminal and the second voltage terminal and having first and second gate electrodes, a drive circuit that complementally switches on and off the high-side mosfet and low-side mosfet, and a second gate electrode control circuit that generates a second gate control signal supplied to the second gate electrode of the low-side mosfet. The second gate electrode control circuit has a voltage generating circuit that supplies a negative voltage negative in polarity relative to a voltage at the source of the low-side mosfet, to the second gate electrode of the low-side mosfet..
Renesas Electronics Corporation

Semiconductor package device and manufacturing the same

A semiconductor device package includes a substrate, a package body, a conductive layer, a dielectric layer, a magnetic layer, a first insulating layer and a coil. The package body is disposed on the substrate.
Advanced Semiconductor Engineering, Inc.

Semiconductor element driving device

A semiconductor element driving device including: plural detection units configured to detect information necessary for protection operation for a semiconductor element included in a power conversion device; a protection signal generation unit configured to generate a protection signal having a pulse width different according to each of the plural detection units when the plural detection units detect the information necessary for the protection operation; a protection state monitoring unit configured to generate a protection state signal while any of the plural detection units is detecting the information necessary for the protection operation; and a signal output unit configured to output an alarm signal, the alarm signal changing from a first level to a second level when the protection signal and the protection state signal are input, and changing to an intermediate level between the first level and the second level when the input of the protection signal is stopped.. .
Fuji Electric Co., Ltd.

Semiconductor laser device

A configuration of a dfb laser-based wavelength tunable laser is well known, but long resonators have difficulty in forming uniform resonators due to production variations, thereby inducing limitation in narrowing the spectral linewidth in the dfb laser-based wavelength tunable laser as well. In the semiconductor laser device of the present invention, a semiconductor laser that oscillates in a single mode and a low-loss lightwave circuit using sio2 glass are arranged on the common substrate.
Tohoku University

Semiconductor laser incorporating an electron barrier with low aluminum content

A semiconductor laser may include a substrate, a multi quantum well (mqw) active layer, and an electron stopper layer. The mqw active layer may include a quantum well that is tensile strained and a barrier that is compressively strained.
Macom Technology Solutions Holdings, Inc.

Surface emitting semiconductor laser

A surface emitting semiconductor laser includes a post disposed on a substrate, the post including an active layer and a distributed bragg reflector; a first insulating layer disposed on side and top surfaces of the post and on the substrate, the first insulating layer having an opening on the top surface of the post; an electrode disposed in the opening of the first insulating layer; an electric conductor including a pad electrode on the first insulating layer, the electric conductor extending on the first insulating layer to the electrode; and a second insulating layer disposed on the first insulating layer, the electrode, and the electric conductor so as to cover the electrode in the opening of the first insulating layer, the second insulating layer having an opening on the pad electrode, the opening of the second insulating layer having an edge on a top surface of the pad electrode.. .
Sumitomo Electric Industries, Ltd.

Semiconductor laser

A hybrid single or multi-wavelength laser using an optical gain element, such as a semiconductor optical amplifier (soa), for example a qd rsoa, and a semiconductor, e.g. Silicon, photonics chip is demonstrated.
Elenion Technologies, Llc

Plasmonic mode iii-v laser as on-chip light source

A plasmonic light source includes a substrate and a square nano-cavity formed on the substrate. The nano-cavity includes a quantum well structure.
The George Washington University

Semiconductor light emitting device

A semiconductor light emitting device includes a mount section having an insulating property connected to a heat sink, a plurality of semiconductor laser elements disposed on the mount section, and a heat radiation block having an insulating property disposed on the plurality of semiconductor laser elements. A first wiring made of a metal is disposed on an upper surface of the mount section, and a second wiring made of a metal is disposed on a lower surface of the heat radiation block, a part of the second wiring being electrically connected to the first wiring.
Panasonic Corporation

Photoelectric conversion element, manufacturing photoelectric conversion element, and solid-state imaging device

A photoelectric conversion element includes: a first electrode; a photoelectric conversion layer provided on the first electrode, and including an organic semiconductor with quantum efficiency of 1% or less; and a second electrode provided on the photoelectric conversion layer.. .
Sony Corporation

Thin film transistor and manufacturing the same

A thin film transistor includes a pair of auxiliary structures facing each other on a substrate, an active layer including an organic semiconductor and continuously grown between the pair of auxiliary structures, a gate electrode on the substrate and overlapped by the active layer, and a source electrode and a drain electrode electrically connected to the active layer. A method of manufacturing the thin film transistor is disclosed..
Samsung Electronics Co., Ltd.

Method of producing a plurality of optoelectronic semiconductor components and optoelectronic semiconductor component

A method of producing a plurality of optoelectronic semiconductor components includes a) preparing a composite with a semiconductor layer sequence, wherein the composite includes a plurality of component areas mechanically connected to one another; b) forming a plurality of connecting surfaces on the semiconductor layer sequence, wherein at least one connecting surface is formed on each component area; c) forming a molding compound on the semiconductor layer sequence, wherein the molding compound fills interstices between the connecting surfaces; and d) singulating the composite with the molding compound, wherein during singulation a plurality of molded bodies is formed from the molding compound, each of which is associated with a semiconductor body obtained from a component area of the composite.. .
Osram Opto Semiconductors Gmbh

Semiconductor light emitting apparatus and manufacturing same

A light emitting apparatus includes at least one first light source and at least one second light source. The at least one first light source and at least one second light source may be configured to emit white light and cyan light, respectively, such that a ratio of luminous flux of the white light to luminous flux of the cyan light ranges from 19:1 to 370:1, based on a common magnitude of electrical current being applied to each of the at least one first light source and the at least one second light source..
Samsung Electronics Co., Ltd.

Porous-silicon light-emitting device and manufacturing method thereof

A light-emitting device may include a semiconductor body having a first conductivity type, with a front side and a back side. The light-emitting device may also include a porous-silicon region which extends in the semiconductor body at the front side, and a cathode region in direct lateral contact with the porous-silicon region.
Stmicroelectronics S.r.l.

Patterned layer design for group iii nitride layer growth

A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group iii nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings.
Sensor Electronic Technology, Inc.

Light emitting diode

A light emitting diode includes a first light emitting region and a second light emitting region each comprising a first conductivity type semiconductor layer, a second conductivity type semiconductor layer and an active layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, an ohmic reflective layer disposed on the second conductivity type semiconductor layer of each of the first and second light emitting regions, and a first pad metal layer separated from the ohmic reflective layer and electrically connected to the first conductivity type semiconductor layer of each of the first and second light emitting regions, wherein the second light emitting region surrounds the first light emitting region.. .
Seoul Viosys Co., Ltd.

Manufacturing light emitting diode device and light emitting diode device

A manufacturing method of a light emitting diode device and a light emitting diode device are provided. The manufacturing method of the light emitting diode device includes: forming a light emitting lamination layer on a base substrate, the light emitting lamination layer including a first semiconductor layer, a first light emitting layer, a second semiconductor layer, a second light emitting layer and a third semiconductor layer sequentially formed on the base substrate; dividing the light emitting lamination layer to form a plurality of light emitting units spaced from each other, each light emitting unit including a first area and a second area spaced from each other; and removing the third semiconductor layer and the second light emitting layer in the first area to form a first sub light emitting unit, and the second area being used for forming a second sub light emitting unit..
Beijing Boe Optoelectronics Technology Co., Ltd.

Light-emitting metal-oxide-semiconductor devices and associated systems, devices, and methods

Various embodiments of solid state transducer (“sst”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (mos) capacitor, an active region operably coupled to the mos capacitor, and a bulk semiconductor material operably coupled to the active region.
Micron Technology, Inc.

Nitride semiconductor structure

A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure includes a multiple quantum well structure formed by a plurality of well layers and barrier layers stacked alternately.
Genesis Photonics Inc.

Semiconductor package device and manufacturing the same

An optical device includes a carrier including a light transmitting layer and a light shielding layer disposed on the light transmitting layer. The optical device further includes a light emitter disposed on the carrier and a light detector disposed on the carrier.
Advanced Semiconductor Engineering, Inc.

Inverted metamorphic multijunction solar cells having a permanent supporting substrate

The present disclosure provides a method of manufacturing a solar cell that includes providing a semiconductor growth substrate; depositing on said growth substrate a sequence of layers of semiconductor material forming a solar cell; applying a metal contact layer over said sequence of layers; affixing the adhesive polyimide surface of a permanent supporting substrate directly over said metal contact layer and permanently bonding it thereto by a thermocompressive technique; and removing the semiconductor growth substrate.. .
Solaero Technologies Corp.

Solar cell panel

Disclosed is a solar cell panel including a plurality of solar cells each including a semiconductor substrate and an electrode formed on the semiconductor substrate, and a wire for interconnecting the solar cells. The electrode includes a bus-bar line having a pad portion for attachment of the wire.
Lg Electronics Inc.

Method for forming a multijunction metamorphic solar cell for space applications

A multijunction solar cell assembly and its method of manufacture including interconnected first and second discrete semiconductor body subassemblies disposed adjacent and parallel to each other, each semiconductor body subassembly including first top subcell, second (and possibly third) lattice matched middle subcells; a graded interlayer adjacent to the last middle solar subcell; and a bottom solar subcell adjacent to said graded interlayer being lattice mismatched with respect to the last middle solar subcell; wherein the interconnected subassemblies form at least a four junction solar cell by a series connection being formed between the bottom solar subcell in the first semiconductor body and the bottom solar subcell in the second semiconductor body.. .
Solaero Technologies Corp.

Silicon photonics integration method and structure

Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device.
International Business Machines Corporation

Optical component packaging structure

The instant disclosure provides an optical component packaging structure which includes a far-infrared sensor chip, a first metal layer, a packaging housing and a covering member. The far-infrared sensor chip includes a semiconductor substrate and a semiconductor stack structure.
Pixart Imaging Inc.

Schottky barrier diode

A schottky barrier diode comprises a semiconductor layer configured to include a surface and a plurality of recesses that are recessed relative to the surface; and a schottky electrode arranged to form a schottky contact with the surface. When the semiconductor layer is viewed from a surface side thereof, the surface is arranged continuously, and distances on the surface between adjacent recesses are substantially identical.
Toyoda Gosei Co., Ltd.

Thin-film transistor, manufacturing the same, display panel

A thin-film transistor, a manufacturing for the same, and a display panel are provided. In the annealing process, the aluminum layer combines with oxygen ions in the amorphous oxide semiconductor layer to form an al2o3 layer.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Semiconductor device and manufacturing method thereof

A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof.
Semiconductor Energy Laboratory Co., Ltd.

Tight pitch vertical transistor eeprom

A memory device including a first conductivity type vertically orientated semiconductor device in a first region of a substrate and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common floating gate structure in simultaneous electrical communication with a first fin structure of the first conductivity type vertically orientated semiconductor device and a second fin structure of the second conductivity type vertically orientated semiconductor device..
International Business Machines Corporation

Semiconductor device

A high-performance semiconductor device with high reliability is provided. The semiconductor device includes a first transistor, a second transistor, a first metal oxide covering at least part of the first transistor, an insulating film over the first transistor and the second transistor, and a second metal oxide over the insulating film.
Semiconductor Energy Laboratory Co., Ltd.

Wrapped source/drain contacts with enhanced area

Methods of forming semiconductor devices include forming a first dielectric layer over a semiconductor fin. A second dielectric layer is formed around the first dielectric layer.
International Business Machines Corporation

Wrapped source/drain contacts with enhanced area

Semiconductor device and methods of forming the same, include forming a first dielectric layer over a semiconductor fin. A second dielectric layer is formed around the first dielectric layer.
International Business Machines Corporation

Semiconductor device and a manufacturing the same

A semiconductor device includes an n channel conductivity type fet having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type fet having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel fet has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel fet to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel fet.
Renesas Electronics Corporation

Semiconductor arrangement with one or more semiconductor columns

A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region.
Taiwan Semiconductor Manufacturing Company Limited

Power semiconductor device and manufacturing power semiconductor device

A power semiconductor device of the present invention includes: a semiconductor base body which has a super junction structure formed of a plurality of first conductive-type columnar regions and a plurality of second conductive-type columnar regions; a plurality of trenches; gate insulation films; gate electrodes; an interlayer insulation film; contact holes formed such that two or more contact holes are formed between two trenches disposed adjacently to each other; metal plugs formed by filling the inside of the contact holes with metal; and an electrode, wherein a first conductive-type high concentration diffusion region is formed only between the trench and the metal plug disposed closest to the trench between each two trenches disposed adjacently to each other. According to the power semiconductor device of the present invention, it is possible to provide a power semiconductor device which satisfies a demand for reduction in cost and downsizing of electronic equipment, and has a large breakdown strength..
Shindengen Electric Manufacturing Co., Ltd.

Semiconductor device with extended electrically-safe operating area

In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type.
Texas Instruments Incorporated

Semiconductor base substance, semiconductor device, manufacturing semiconductor base substance, and manufacturing semiconductor device

A semiconductor base substance includes: a substrate; a buffer layer which is made of a nitride semiconductor and provided on the substrate; and a channel layer which is made of a nitride semiconductor and provided on the buffer layer, wherein the buffer layer includes: a first region which is provided on the substrate side and has boron concentration higher than acceptor element concentration; and a second region which is provided on the first region, and has boron concentration lower than that in the first region and acceptor element concentration higher than that in the first region. As a result, the semiconductor base substance which can obtain a high pit suppression effect while maintaining a high longitudinal breakdown voltage is provided..
Shin-etsu Handotai Co., Ltd.

Semiconductor device

A semiconductor device is provided, wherein a semiconductor substrate includes: a first trench portion provided from a front surface of the semiconductor substrate to a predetermined depth, and having a longer portion and a shorter portion as seen from above; and a first conductivity-type floating semiconductor region at least partially exposed on the front surface and surrounded by the first trench portion, an interlayer insulating film has openings to electrically connect an emitter electrode and the floating semiconductor region, the openings include: a first opening closest to an outer end of the floating semiconductor region in a direction parallel to the longer portion; and a second opening second closest to the outer end in the direction parallel to the longer portion, and a distance between the first opening and the second opening is shorter than a distance between any adjacent two of the openings other than the first opening.. .
Fuji Electric Co., Ltd.

Semiconductor device and manufacturing semiconductor device

A semiconductor device is provided, the semiconductor device including a base layer of a first conductivity type having a mos gate structure formed on a front surface side thereof, a collector layer of a second conductivity type formed on a rear surface side of the base layer, and into which a first dopant and a second dopant which is different from the first dopant are implanted, and a collector electrode formed on a rear surface side of the collector layer, wherein an impurity concentration peak of the second dopant is at a deeper position from the rear surface of the collector layer than an impurity concentration peak of the first dopant, and magnitude of the impurity concentration peak of the second dopant is larger than 1/100 of magnitude of the impurity concentration peak of the first dopant.. .
Fuji Electric Co., Ltd.

Power semiconductor device

A power semiconductor device includes: a semiconductor body coupled to a first load terminal and a second load terminal, and includes: a first doped region of a second conductivity type electrically connected to the first load terminal; a recombination zone arranged at least within the first doped region; an emitter region of the second conductivity type electrically connected to the second load terminal; and a drift region of a first conductivity type arranged between the first doped region and the emitter region. The drift region and the first doped region enable the power semiconductor device to operate in: a conducting state during which a load current between the load terminals is conducted along a forward direction; in a forward blocking state during which a forward voltage applied between the load terminals is blocked; and in a reverse blocking state during which a reverse voltage applied between the terminals is blocked..
Infineon Technologies Austria Ag

Vertical field-effect transistors with controlled dimensions

Device structures and fabrication methods for a vertical field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region.
Globalfoundries Inc.

Semiconductor super-junction power device and manufacturing method therefor

The present disclosure relates to the technical field of semiconductor power devices, and in particular relates to a semiconductor super-junction power device and a manufacturing method therefor. The super-junction power device of the present disclosure includes a termination region and a cell region; the cell region includes a substrate epitaxial layer and a drain region at a bottom of the substrate epitaxial layer, the substrate epitaxial layer has a plurality of pillar epitaxial doped regions and a plurality of jfet regions, a body region is arranged at a top of each of the plurality of pillar epitaxial doped regions; the body regions have at least two unequal widths; two source regions are arranged in each of the body regions; a gate oxide layer is arranged on the body regions and the jfet regions; and a gate is arranged on the gate oxide layer..
Suzhou Oriental Semiconductor Co.,ltd

Reducing resistance of bottom source/drain in vertical channel devices

During a fabrication of a semiconductor device, a recess is created in a substrate material disposed along a direction of a plane of fabrication. A layer of a removable material is formed in the recess.
International Business Machines Corporation

Semiconductor device with metal gate

A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (bbm) layer on the high-k dielectric layer. Preferably, the bbm layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition..
United Microelectronics Corp.

Semiconductor device, method, and tool of manufacture

In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness.. .
Taiwan Semiconductor Manufacturing Company, Ltd.

N-channel bipolar power semiconductor device with p-layer in the drift volume

A power semiconductor device having a semiconductor body configured to conduct a load current is disclosed. In one example, the device includes a source region having dopants of a first conductivity type; a semiconductor channel region implemented in the semiconductor body and separating the source region from a remaining portion of the semiconductor body; a trench of a first trench type extending in the semiconductor body along an extension direction and being arranged adjacent to the semiconductor channel region, the trench of the first trench type including a control electrode that is insulated from the semiconductor body.
Infineon Technologies Ag

Semiconductor structures and fabrication methods thereof

A method for fabricating a semiconductor structure. The method includes providing a substrate and forming a plurality of fin structures on the substrate.
Semiconductor Manufacturing International (beijing) Corporation

Hybrid gate dielectrics for semiconductor power devices

In a general aspect, a power semiconductor device can include a silicon carbide (sic) substrate and a sic epitaxial layer disposed on the sic substrate. The device can include a well region disposed in the epitaxial layer, a source region disposed in the well region and a gate trench disposed in the epitaxial layer and adjacent to the source region.
Fairchild Semiconductor Corporation

Field effect transistor air-gap spacers with an etch-stop layer

Provided herewith are embodiments related to a semiconductor structure and a method for forming the semiconductor structure. A first spacer layer and a second spacer layer are formed opposite a major surface of a substrate.
International Business Machines Corporation

Semiconductor structure and manufacturing the same

A method of manufacturing a semiconductor structure is provided. An interlayer dielectric layer is formed conformally over protruding structures formed over a silicon substrate and a surface of the silicon substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.. .
Acorn Technologies, Inc.

Semiconductor device including a gate contact structure

A semiconductor device includes a semiconductor body. The semiconductor body has a first surface and a second surface opposite to the first surface.
Infineon Technologies Dresden Gmbh

Semiconductor device

Machining accuracy of an igbt region is worsened due to a height difference caused by polysilicon. Therefore, there is a problem that characteristic variation of the igbt increases.
Fuji Electric Co., Ltd.

Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts

This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate.
Alpha And Omega Semiconductor Incorporated

2d crystal hetero-structures and manufacturing methods thereof

A method of fabricating a semiconductor device having two dimensional (2d) lateral hetero-structures includes forming alternating regions of a first metal dichalcogenide film and a second metal dichalcogenide film extending along a surface of a first substrate. The first metal dichalcogenide and the second metal dichalcogenide films are different metal dichalcogenides.
National Taiwan University

Nitride semiconductor device

A nitride semiconductor device includes a first semiconductor layer including a nitride semiconductor, a second semiconductor layer contacting the first semiconductor layer and including a nitride semiconductor, a source electrode, a drain electrode, a first gate electrode, a second gate electrode provided on an opposite side, a first insulating layer and a second insulating layer. The gate electrode has a protrusion portion inside the semiconductor layer.
Kabushiki Kaisha Toshiba

Thin-base high frequency lateral bipolar junction transistor

A semiconductor device including a base region present within a fin semiconductor structure that is present atop a dielectric substrate. An epitaxial emitter region and epitaxial collector region are present on opposing sides and in direct contact with the fin semiconductor structure.
International Business Machines Corporation

Method for fabricating semiconductor device

A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a spacer adjacent to the gate structure; forming a recess adjacent to the spacer; forming a buffer layer in the recess, wherein the buffer layer comprises a crescent moon shape; and forming an epitaxial layer on the buffer layer.. .
United Microelectronics Corp.

Semiconductor device

To obtain a semiconductor device in which a reduction in channel formation density in a trench extending direction is suppressed, provided is a semiconductor device including a first region and a second region alternately arranged in the trench extending direction. The first region includes a first front surface semiconductor electrode layer of a first conductivity type having a portion along an outer side surface of the trench from the front surface of the semiconductor device to the first height to which a gate electrode is embedded into the trench.
Ablic Inc.

Semiconductor device and full-wave rectifier circuit

One aspect of a semiconductor device includes a plurality of first structures, in which each of the first structures includes: a first n-type region; a p-type region which is surrounded by the first n-type region; and a second n-type region which is surrounded by the p-type region. The first n-type region and the p-type region are wired, and the plurality of first structures are connected in parallel to form one diode..
Mie Fujitsu Semiconductor Limited

Semi-metal tunnel field effect transistor

A tunnel field effect transistor (100) comprises a source region (102), a drain region (104), and a channel region (106) formed of a single material, in particular a half-metal. The channel extends between the source region and the drain region.
University College Cork

High voltage blocking iii-v semiconductor device

A semiconductor device includes a type iv semiconductor base substrate, a first type iii-v semiconductor layer formed on a first surface of the base substrate, and a second type iii-v semiconductor layer with a different bandgap as the first type iii-v being formed on the first type iii-v semiconductor layer. The semiconductor device further includes first and second electrically conductive device terminals each being formed on the second type iii-v semiconductor layer and each being in ohmic contact with the two-dimensional charge carrier gas.
Infineon Technologies Austria Ag

Semiconductor device and manufacturing semiconductor device

To provide a semiconductor device having a structure capable of forming a superjunction with less thermal history, a semiconductor device is provided, the semiconductor device including a contact trench formed between two gate trenches, penetrating through a source region, and including its lower end arranged in a base region, and a second conductivity-type protruding portion formed protruding toward a lower side from the lower end of the base region in a region opposite to the lower end of the contact trench, wherein the depth from the upper end of the source region to a lower end of the protruding portion is 3 μm or more, and a carrier concentration nd in a first conductivity-type region adjacent to the protruding portion in a lateral direction perpendicular to a depth direction and a carrier concentration na of the protruding portion satisfy a predetermined equation.. .
Fuji Electric Co., Ltd.

Semi-metal rectifying junction

A rectifying junction (15) is formed in a conduction path provided in a material (1). A size of the material (1) is smaller than a threshold size in a first dimension, the threshold size being the size required for the material (1) to exhibit sufficient quantum confinement such that it forms a semiconductor.
University College Cork

Semiconductor device including an ldmos transistor and a resurf structure

In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≥100 ohm.cm, a front surface and a rear surface. An ldmos transistor is arranged in the semiconductor substrate.
Infineon Technologies Ag

Semiconductor device and manufacturing semiconductor device

A semiconductor device including an active region for main current thereof to flow therein and an edge termination region surrounding the active region. The semiconductor device includes a substrate, a drift layer provided on a first main surface of the substrate, a semiconductor layer provided in a surface layer of the drift layer, a trench formed in the active region and reaching the drift layer from a surface of the semiconductor layer, a gate electrode provided in the trench via a gate insulating film, a gate metal formed in the edge termination region and connected with the gate electrode, a gate contact formed in the edge termination region, and having a top thereof in contact with the gate metal, and a semiconductor region that is provided in the surface layer of the drift layer, extends from the active region to the edge termination region, and is connected with the semiconductor layer and a bottom of the gate contact..
Fuji Electric Co., Ltd.

Semiconductor memory device

A semiconductor memory device according to an embodiment comprises a plurality of control gate electrodes, a first semiconductor layer, and a gate insulating layer. The plurality of control gate electrodes are arranged in a first direction that intersects a surface of a substrate.
Toshiba Memory Corporation

Semiconductor devices and methods of forming the same

A semiconductor device 100 comprising a substrate 102 having a through-substrate via hole 106, the through-substrate via hole 106 having formed therein: a first capacitor electrode layer 108a and a second capacitor electrode layer 108b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 108a and the second capacitor electrode layer 108b; and a through-substrate via conductor 116. A method of forming a semiconductor device 100, the semiconductor device 100 comprising a through-substrate via hole 106, the method comprising forming, in the through-substrate via hole 106: a first capacitor electrode layer 108a and a second capacitor electrode layer 108b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 108a and the second capacitor electrode layer 108b; and a through-substrate via conductor 116..
Nanyang Technological University

Semiconductor device

A semiconductor device includes: a bleeder resistor circuit element including a plurality of polycrystalline silicon resistor units; a first metal film divided into a plurality of films so as to individually cover the plurality of polycrystalline silicon resistor units; an integral second metal film for covering an entirety of the bleeder resistor circuit element; and a silicon nitride film formed above the second metal film. Each of the plurality of films of the first metal film includes a first part for covering an electrode portion of the polycrystalline silicon resistor unit, and a second part for covering a portion other than the electrode portion.
Ablic Inc.

Quantum dot array on directly patterned amoled displays and fabrication

An active matrix oled apparatus comprises a plurality of pixels each including a layer of three sub-pixel anodes, a transparent cathode layer, and a layer of three sub-pixel oled emitters disposed between the layer of three sub-pixel anodes and the cathode layer. Each of the plurality of pixels further includes a quantum dot semiconductor nanocrystal layer disposed above the transparent cathode layer, the quantum dot layer comprising a first quantum dot sub-pixel layer having a photoluminescent emission in a first red color wavelength range substantially between 780 to 622 nm, wherein the first quantum dot sub-pixel layer being disposed over one of the three sub-pixel oled emitters having a light emission wavelength in the first red color wavelength range.
Emagin Corporation

Organic photoelectronic device and image sensor

An organic photoelectronic device includes a first electrode and a second electrode facing each other and a light-absorption layer between the first electrode and the second electrode and including a first region closest to the first electrode, the first region having a first composition ratio (p1/n1) of a p-type semiconductor relative to an n-type semiconductor, a second region closest to the second electrode, the second region having a second composition ratio (p2/n2) of the p-type semiconductor relative to the n-type semiconductor, and a third region between the first region and the second region in a thickness direction, the third region having a third composition ratio (p3/n3) of the p-type semiconductor relative to the n-type semiconductor that is greater or less than the first composition ratio (p1/n1) and the second composition ratio (p2/n2).. .
Samsung Electronics Co., Ltd.

Semiconductor memory device

This semiconductor memory device includes: global first wiring lines; global second wiring lines; and memory blocks connected to the global first wiring lines and the global second wiring lines. The memory block includes: local first wiring lines; local second wiring lines; and memory cells connected to the local first wiring lines and the local second wiring lines.
Toshiba Memory Corporation

Growth substrate for forming optoelectronic devices, manufacturing such a substrate, and use of the susbstrate, in particular in the field of micro-display screens

A method for manufacturing a plurality of crystalline semiconductor islands having a variety of lattice parameters comprises providing a substrate including a medium, a flow layer disposed on the medium, and a plurality of strained crystalline semiconductor islands having an initial lattice parameter arranged on the flow layer. The strained semiconductor islands are selectively treated so as to form a first group of strained islands having a first lateral expansion potential, and a second group of strained islands having a second lateral expansion potential that is different from the first lateral expansion potential.
Soitec

Semiconductor structure and fabrication method thereof

A semiconductor structure and a fabrication method are provided. The fabrication method includes: providing a substrate, containing first doping ions and including a pixel region for forming a pixel structure; forming a deeply doped region, in the photosensitive region of the substrate and containing second doping ions; forming a floating diffusion area in the floating diffusion region of the substrate and containing third doping ions; forming a gate structure on the substrate at the junction of the photosensitive region and the floating diffusion region; forming a sidewall film covering the gate structure and the substrate; forming a sidewall spacer; forming a first doped region in the floating diffusion region on one side of the gate structure; forming a metal connection layer on the first doped region; forming an interlayer dielectric layer on the substrate; and forming a source/drain contact plug in the interlayer dielectric layer..
Semiconductor Manufacturing International (beijing) Corporation

Pixel structure of an image sensor and fabrication method thereof

A pixel structure of an image sensor and fabrication methods thereof are provided. The pixel structure includes a semiconductor substrate and plural pixel units disposed on the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device and manufacturing method

A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.. .
Sony Corporation

Solid-state imaging device and manufacturing the same, and imaging apparatus

A solid-state imaging device includes: a semiconductor substrate provided with an effective pixel region including a light receiving section that photoelectrically converts incident light; an interconnection layer that is provided at a plane side opposite to the light receiving plane of the semiconductor substrate; a first groove portion that is provided between adjacent light receiving sections and is formed at a predetermined depth from the light receiving plane side of the semiconductor substrate; and an insulating material that is embedded in at least a part of the first groove portion.. .
Sony Corporation

Semiconductor element and solid-state imaging device

A semiconductor element includes a semiconductor region (11) of a first conductivity type, a buried charge-generation region (16) of a second conductivity type, buried in an upper portion of the semiconductor region (11) to implement a photodiode (d1) together with the semiconductor region (11) to generate charges, a charge-readout region (15) of the second conductivity type, provided in the semiconductor region (11) to accumulate the charges transferred from the buried charge-generation region (16), and a reset-performing region (12) of the second conductivity type, provided in the semiconductor region (11), a variable voltage is applied to the reset-performing region (12) to change the height of a potential barrier generated in the semiconductor region (11) sandwiched between the charge-readout region (15) and the reset-performing region (12) to exhaust the charges accumulated in the charge-readout region (15). The semiconductor element has a high pixel conversion gain, ultralow noise of a photon counting level and implements a solid-state imaging device..
National University Corporation Shizuoka University

Germanium-silicon light sensing apparatus

A method for fabricating an image sensor array having a first group of photodiodes for detecting light at visible wavelengths a second group of photodiodes for detecting light at infrared or near-infrared wavelengths, the method including forming a germanium-silicon layer for the second group of photodiodes on a first semiconductor donor wafer; defining a first interconnect layer on the germanium-silicon layer; defining integrated circuitry for controlling pixels of the image sensor array on a semiconductor carrier wafer; defining a second interconnect layer on the semiconductor carrier wafer; bonding the first interconnect layer with the second interconnect layer; defining the pixels of an image sensor array on a second semiconductor donor wafer; defining a third interconnect layer on the image sensor array; and bonding the third interconnect layer with the germanium-silicon layer.. .
Artilux Corporation

Isolation structure for reducing crosstalk between pixels and fabrication method thereof

An optical isolation structure and a method for fabricating the same are provided. The optical isolation structure includes a first dielectric layer, a second dielectric layer, a third dielectric layer and a dielectric post.
Taiwan Semiconductor Manufacturing Co., Ltd.

Photodetection element

A photodetection element according to an embodiment includes: a photodiode cell, the photodiode cell including: a semiconductor substrate; a first semiconductor layer disposed on the semiconductor substrate; a second semiconductor layer disposed in a region including an interface between the semiconductor substrate and the first semiconductor layer, the second semiconductor layer being of the same conductivity type as the semiconductor substrate; and a third semiconductor layer disposed in a surface region of the first semiconductor layer.. .
Kabushiki Kaisha Toshiba

Assembly of semiconductor devices

A method for manufacturing a display element comprising a plurality of pixels, each comprising a plurality of subpixels. The method comprises undertaking, using a pick up tool, a first placement cycle (1908) comprising picking up a plurality of first, untested led dies and placing them on a display substrate at locations corresponding to the plurality of pixels, testing (1912) the first led emitters on the display substrate to determine one or more locations of non-functional first led emitters, selecting one or more second tested led dies based on a result of the test, configuring the selected one or more second led dies to enable their pick up and placement on the display substrate and undertaking, using the put, a second placement cycle (2008) comprising picking up the selected one or more second led dies and placing them on the display substrate at the determined locations of the nonfunctional first led emitters..
Oculus Vr, Llc

Display device and electronic device including the same

One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component.
Semiconductor Energy Laboratory Co., Ltd.

Thin polysilicon for lower off-capacitance of a radio frequency (rf) silicon-on-insulator (soi) switch field effect transistor (fet)

A radio frequency (rf) switch includes a plurality of series-connected silicon-on-insulator (soi) cmos transistors fabricated in accordance with a semiconductor process having a first minimum line width (e.g., 0.18 microns). While the semiconductor process conventionally implements a polysilicon gate layer having a first thickness (e.g., 2000 angstroms), each of the plurality of soi cmos transistors is fabricated with a polysilicon gate electrode having a second thickness, which is less than the first thickness.
Newport Fab, Llc Dba Jazz Semiconductor, Inc.

3d semiconductor device and structure

A multilevel semiconductor device, the device including: a first level including a first array of first programmable cells and a first control line; a second level including a second array of second programmable cells and a second control line; and a third level including a third array of third programmable cells and a third control line, where the second level overlays the first level, where the third level overlays the second level, where the first programmable cells are self-aligned to the second programmable cells, and where a programmable logic cell includes a plurality of the first programmable cells and a plurality of the second programmable cells.. .
Monolithic 3d Inc.

Semiconductor memory device

According to an embodiment, a semiconductor memory device comprises control gate electrodes and a semiconductor layer. The control gate electrodes are stacked above a substrate.
Toshiba Memory Corporation

Semiconductor memory device and manufacturing same

A semiconductor memory device includes a substrate, a first stacked body provided in a first region on the substrate, a transistor formed in a second region of the substrate, and a block member provided between the first stacked body and the transistor. The first stacked body includes a plurality of first silicon oxide films and a plurality of electrode films stacked alternately one by one.
Toshiba Memory Corporation

Manufacturing semiconductor memory device

A manufacturing method of a semiconductor memory device includes disposing a first stacked body on a substrate, forming a first through via hole in the first stacked body, and determining to remove an upper portion of the first stacked body based on a comparison of a determined value of a width of the first through via hole with a reference value. The method further includes forming a second film in the first through via hole responsive to the determination to remove the upper portion of the first stacked body, removing the upper portion of the first stacked body and a portion of the second film, and disposing a second stacked body on the first stacked body and the second film.
Toshiba Memory Corporation

Semiconductor device

According to an embodiment, a semiconductor device includes a substrate, a stacked body, and a second insulating film. A first insulating film and an electrode film are alternately stacked in the stacked body so as to extend in a first direction along an upper surface of the substrate.
Toshiba Memory Corporation

Finfet vertical flash memory

A plurality of fin structures containing, from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of a first conductivity type, extend upwards from a surface of a first doped semiconductor portion of the first conductivity type. A trapping material (e.g., an electron-trapping material) is present along a bottom portion of sidewall surfaces of each non-doped semiconductor portion and on exposed portions of each first doped semiconductor portion.
International Business Machines Corporation

Semiconductor memory device

Accor