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Semiconductor patents

      

This page is updated frequently with new Semiconductor-related patent applications.

Nitride semiconductor light-emitting element base and manufacturing method thereof
To prevent degradation of electrical characteristics caused by a resin filled between electrodes in an ultraviolet light-emitting operation, the present invention provides a base 10 that comprises an insulating base material 11 and two or more metal films 12 and 13 that are formed on one side of the insulating base material 11 and electrically separated from each other. The two or more metal films are formed to include an upper surface and a side wall surface that are covered by gold or a platinum group metal, to be capable of mounting thereon one or more nitride semiconductor light-emitting elements and the like, and to have, as a whole, a predetermined planar view shape including two or more electrode pads.
Asahi Glass Company, Limited


Configurable computing array die based on printed memory and two-sided integration
The present invention discloses a new type of configurable gate array—a configurable computing array die based on two-sided integration. It is a monolithic die and comprises at least a configurable computing element and a configurable logic element formed on different sides of a semiconductor substrate.
Hangzhou Haicun Information Technology Co., Ltd.


Semiconductor device driving circuit
A semiconductor device driving circuit includes: a threshold adjustment circuit; a desaturation voltage detection circuit; and a drive circuit. The threshold adjustment circuit switches the threshold between a first voltage and a second voltage which is larger than the first voltage, outputs the first voltage as the threshold when the semiconductor switching device is in an off-state, and outputs the second voltage as the threshold when the semiconductor switching device is turned on and a voltage between the first electrode and the second electrode is a saturation voltage..
Mitsubishi Electric Corporation


Semiconductor device having a low power consumption
An amplifying unit includes a converter and a feedback mechanism. The converter has a supply input coupled to a supply node.
Taiwan Semiconductor Manufacturing Company Limted


Semiconductor integrated circuit, sensor reader, and sensor readout method
In a sensor reader, an ic chip has a function for amplifying and outputting a sensor signal from each sensor element included in a sensor array, and includes a plurality of channel amplifiers connected each of the sensor elements. When an output switch is closed and the ic chip is in the outputting state, channel switches operate sequentially, and sensor amplification signals are output sequentially from the channel amplifiers.
Mitsubishi Electric Corporation


Semiconductor-switch control device
A semiconductor-switch control device includes a controller that detects an analog signal of a load current, converts the detected analog signal into a digital signal, and determines an over-current based on the converted digital signal; a short circuit detector that detects an analog signal of a load voltage, and detects an over-current based on the analog signal without converting the detected analog signal into a digital signal; and a drive unit that drives an fet based on a determination result of the over-current determined by the controller or a detection result of the over-current detected by the short circuit detector.. .
Yazaki Corporation


Organic light-emitting component and producing an organic light-emitting component
An organic light-emitting component may include: a substrate, a first electrode arranged over the substrate, at least one organic functional layer stack configured to emit radiation and arranged over the first electrode, at least one conductive current spreading structure which is arranged on the first electrode and faces the at least one organic functional layer stack, and a second electrode arranged over the at least one organic functional layer stack. The at least one conductive current spreading structure may comprise at least one metal, and may be covered with an inorganic passivation layer.
Osram Oled Gmbh


Organic semiconducting compounds
The invention relates to novel organic semiconducting compounds containing a polycyclic unit, to methods for their preparation and educts or intermediates used therein, to compositions, polymer blends and formulations containing them, to the use of the compounds, compositions and polymer blends as organic semiconductors in, or for the preparation of, organic electronic (oe) devices, especially organic photovoltaic (opv) devices, perovskite-based solar cell (psc) devices, organic photodetectors (opd), organic field effect transistors (ofet) and organic light emitting diodes (oled), and to oe, opv, psc, opd, ofet and oled devices comprising these compounds, compositions or polymer blends.. .
Merck Patent Gmbh


Memory cells, semiconductor devices including the memory cells, and methods of operation
Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material.
Micron Technology, Inc.


Electronic device
An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride.. .
Toshiba Memory Corporation


Semiconductor devices and methods of fabricating the same

A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug.

Malfunction detection device for power generator

A malfunction detection device is provided for a power generator that includes a thermoelectric transducer module including, as a plurality of thermoelectric transducers, a plurality of semiconductor single crystals in which the band gap energy of an intrinsic semiconductor part is lower than the band gap energies of an n-type semiconductor part and a p-type semiconductor part. The malfunction detection device performs a malfunction detection of the power generator on a transducer-to-transducer basis.
Toyota Jidosha Kabushiki Kaisha

Light emitting diodes with integrated reflector for a direct view display and making thereof

An led subpixel can be provided with a reflector layer that controls viewing angles. After formation of an array of nanowires including first conductivity type cores and active layers, a second conductivity type semiconductor material layer, a transparent conductive oxide layer, and a dielectric material layer are sequentially formed.
Glo Ab

Optoelectronic component and a producing an optoelectronic component

An optoelectronic component includes a boundary layer is arranged between a semiconductor body and a metallic layer in a lateral direction, adjoins the semiconductor body at least in places, covers an active layer laterally, and has a lower refractive index compared to the semiconductor body, a metallic layer is configured to prevent the electromagnetic radiation generated during operation of the component and passes through the boundary layer from impinging on a mold body, the boundary layer is formed from a radiation-transmitting dielectric material having a refractive index of 1 to 2, and a layer thickness of the boundary layer is at least 400 nm and selected such that an amplitude of an evanescent wave, which is obtained in the event of total internal reflection at an interface between the boundary layer and the semiconductor body, is reduced to less than 37% of its original value within the boundary layer.. .
Osram Opto Semiconductors Gmbh

Optoelectronic lamp device and producing same

An optoelectronic lamp device includes an optoelectronic semiconductor component including a top side including a light-emitting face, and a housing embedding the semiconductor component and leaving free the light-emitting face, wherein a housing face is coated with a light-scattering dielectric resist layer that may scatter light incident on a face of the resist layer facing away from the housing face.. .
Osram Opto Semiconductors Gmbh

Apparatus for high speed printing of semiconductor devices

A device for depositing an unpackaged semiconductor die (“die”) onto a substrate. The device includes a developing unit adjacent to a drum.
Rohinni, Llc

Method for producing optoelectronic conversion semiconductor chips and composite of conversion semiconductor chips

A method for producing optoelectronic conversion semiconductor chips and a composite of conversion semiconductor chips are disclosed. In an embodiment the method includes growing a semiconductor layer sequence on a growth substrate, applying an electric contact on to a rear side of the semiconductor layer sequence facing away from the growth substrate, thinning the growth substrate, after thinning, cutting the growth substrate at least to the semiconductor layer sequence thereby forming a first intermediate space, applying a conversion layer on to the thinned growth substrate and singulating at least the thinned growth substrate and the semiconductor layer sequence..
Osram Opto Semiconductors Gmbh

Semiconductor light-emitting device and fabricating the same

A semiconductor light-emitting device is provided. The semiconductor light-emitting device may include a light-emitting structure, an electrode, an ohmic layer, an electrode layer, an adhesion layer, and a channel layer.
Lg Innotek Co., Ltd.

Semiconductor light emitting device including reflective element and making same

A light emitting device and method of forming the same, the method including etching grooves into semiconductor layers disposed on a substrate to form mesas, forming an insulating layer on the mesas, etching the insulating layer to expose upper surfaces of the mesas, and forming a reflective contact layer on the mesas. The contact layer may include protrusions disposed in the grooves on the etched insulating layer, and facing sidewalls of the mesas..
Glo Ab

Optoelectronic semiconductor chip

In one embodiment, the optoelectronic semiconductor chip (1) comprises a first semiconductor region (21) of a first conductivity type and a second semiconductor region (23) of a second conductivity type. An active zone (22) configured for generating light is situated between these two semiconductor regions (21, 23).
Osram Opto Semiconductors Gmbh

Electron emitter and light emitting apparatus comprising same

The present invention relates to an electron emitter, a method for manufacturing the same, and a light emitting apparatus comprising the same, and, more particularly, to an electron emitter comprising a semiconductor wafer having a nanostructure formed in at least a portion thereof. The present invention is capable of providing a large-area electron emitter, and also capable of providing a light emitting apparatus which has improved light emission efficiency and can be operated by an electron injection method..
Korea Advanced Institute Of Science And Technology

Semiconductor light emitting device and manufacturing the same

A semiconductor light emitting device includes a light emitting structure in which a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer are sequentially laminated, an insulating layer disposed on the light emitting structure and including first and second openings, an electrode layer disposed on the insulating layer and including first and second electrodes, and an adhesive layer disposed between the electrode layer and the insulating layer and including first and second openings. The first opening of the adhesive layer overlaps the first opening of the insulating layer and is equal to or larger than the first opening of the insulating layer.
Samsung Electronics Co., Ltd.

Micro light-emitting diode chip

A micro light-emitting diode chip includes an epitaxial structure, a first electrode, and a second electrode. The epitaxial structure includes a first type doped semiconductor layer, a light emitting layer, and a second type doped semiconductor layer, and the epitaxial structure further includes a first surface, side surface and a second surface opposite to the first surface.
Playnitride Inc.

Ultraviolet light emitting device having current blocking layer

Described herein is a highly efficient light emitting device. The light emitting device includes: a first conductivity-type semiconductor layer; a second conductivity-type semiconductor layer; an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer; a current blocking layer disposed on the second conductivity-type semiconductor layer; a transparent electrode layer covering the current blocking layer; a first electrode electrically connected to the first conductivity-type semiconductor layer; a second electrode disposed on the transparent electrode layer and electrically connected to the transparent electrode layer, the second electrode including a second electrode pad and a second electrode extension extending from the second electrode pad; and a second reflective layer interposed between the second electrode and the transparent electrode layer, wherein each of the second electrode pad and the second electrode extension covers at least part of the current blocking layer..
Seoul Viosys Co., Ltd.

Semiconductor light emitting device including floating conductive pattern

A semiconductor light emitting device including a floating conductive pattern is provided. The semiconductor light emitting device includes a first semiconductor layer including a recessed region and a protruding region, an active layer and a second semiconductor layer disposed on the protruding region, a contact structure disposed on the second semiconductor layer, a lower insulating pattern covering the first semiconductor layer and the contact structure, and having first and second openings, a first conductive pattern disposed on the lower insulating pattern and extending into the first opening, a second conductive pattern disposed on the lower insulating pattern and extending into the second opening, and a floating conductive pattern disposed on the lower insulating pattern.
Samsung Electronics Co., Ltd.

Micro light emitting diode chip and display panel

A micro light emitting diode chip having a plurality of light-emitting regions, including a semiconductor epitaxial structure, a first electrode and a plurality of second electrodes disposed at interval is provided. The semiconductor epitaxial structure includes a first-type doped semiconductor layer, a plurality of second-type doped semiconductor layers and a plurality of light-emitting layers disposed at interval.
Playnitride Inc.

Semiconductor light emitting device

A semiconductor light emitting device including a first conductivity-type semiconductor layer; a second conductivity-type semiconductor layer; an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, the active layer including at least one quantum well layer and at least one quantum barrier layer that are alternately stacked and form a multiple quantum well structure; at least one border layer in contact with the first conductivity-type semiconductor layer and interposed between the first conductivity-type semiconductor layer and the active layer, the at least one border layer having a band gap energy that decreases in a direction away from the first conductivity-type semiconductor layer; and at least one growth blocking layer interposed between the active layer and the border layer, the at least one growth blocking layer having a band gap energy equal to a band gap energy of the at least one quantum barrier layer.. .
Samsung Electronics Co., Ltd.

Semiconductor device and forming the same

A diode, uv radiation detector, and method of manufacturing semiconductor device that includes a diode with a substrate having a first side and a second side. The diode includes an active layer having a rocksalt phase crystalline structure of cas disposed on the first side of the substrate, and an electrical contact disposed on the second side of the substrate.
The Hong Kong University Of Science And Technology

Deformable paper origami optoelectronic devices

Deformable optoelectronic devices are provided, including photodetectors, photodiodes, and photovoltaic cells. The devices can be made on a variety of paper substrates, and can include a plurality of fold segments in the paper substrate creating a deformable pattern.
King Abdullah University Of Science And Technology

Solar cell module and portable charger

A solar cell module having flexibility is disclosed. The solar cell module includes a first solar cell and a second solar cell disposed adjacent to each other.
Lg Electronics Inc.

Method for manufacturing solar cell

Disclosed is a method for manufacturing a solar cell, the method including: forming a semiconductor layer on one surface of a semiconductor substrate; forming a mask layer including a first layer and a second layer sequentially on the semiconductor layer; texturing another surface of the semiconductor substrate using the mask layer as a mask; forming a patterned mask layer by forming an opening at the mask layer through a laser patterning using a laser; and forming a conductive region through a doping process of doping a portion of the semiconductor layer exposed through the opening with a dopant.. .
Lg Electronics Inc.

Semiconductor device and a manufacturing method thereof

In a semiconductor device including a split gate type monos memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the monos memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches..
Renesas Electronics Corporation

Semiconductor structure including a varactor and the formation thereof

A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type.
Globalfoundries Inc.

Semiconductor device, manufacturing method thereof, and electronic device

A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer.
Semiconductor Energy Laboratory Co., Ltd.

Array substrate, and display device, and fabrication methods

A semiconductor device, an array substrate, and a display device, and their fabrication methods are provided. An exemplary semiconductor device includes a first electrode, an insulating layer, and a second electrode, over a substrate.
Boe Technology Group Co., Ltd.

Semiconductor device and manufacturing the same

A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device is manufactured with a high yield, so that high productivity is achieved.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and manufacturing the same

An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and a manufacturing the same

The present invention relates to a semiconductor device and a method of manufacturing the same. There is provided a semiconductor device comprising: a semiconductor substrate with a fin; a gate intersecting with the fin and a source region and a drain region within the fin at both sides of the gate; metal silicides formed at the source region and the drain region and in contact with the source region and the drain region respectively; wherein there is a impurity dopant at a interface of the metal silicide in contact with the source/drain region, which is capable of reducing a schottky barrier height between the metal silicide and the source/drain region.
Institute Of Microelectronics, Chinese Academy Of Sciences

Semiconductor structure having a junction field effect transistor and a high voltage transistor and manufacturing the same

The present examples relate to a junction field effect transistor (jfet) that shares a drain with a high voltage field effect transistor. The present examples are able to control a pinch-off feature of the junction transistor while also maintaining electric features of the high voltage transistor by forming a groove on a lower part of a first conductivity type deep-well region located on a channel region of the junction transistor in a channel width direction..
Magnachip Semiconductor, Ltd.

Reduced resistance source and drain extensions in vertical field effect transistors

Semiconductor devices and methods of forming the same include forming a bottom source/drain region in a semiconductor substrate under a semiconductor fin. First charged spacers are formed on sidewalls of the semiconductor fin.
International Business Machines Corporation

Reduced resistance source and drain extensions in vertical field effect transistors

Semiconductor devices and methods of forming the same include forming semiconductor fins on a semiconductor substrate. A bottom source/drain region is formed in the semiconductor substrate.
International Business Machines Corporation

Multi-gate vertical field effect transistor with channel strips laterally confined by gate dielectric layers, and making thereof

A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics.
Sandisk Technologies Llc

Semiconductor structure and fabrication method thereof

Semiconductor structures and fabrication methods thereof are provided. An exemplary semiconductor structure includes a base substrate having a first well and a second well region; a first insulation layer over the base substrate and dividing the second well region into a first region adjacent to the first well region, a second region away from the first well region and a third region under the first insulation layer; a gate structure over the base substrate in the first well region and the first region of the second well region; a first mask gate structure on a portion of the second region adjacent to the first region; a first stress layer on the first well region at a side of gate structure away from the first insulation layer; and a second stress layer on the second well regions at a side of the mask gate structure away from the isolation layer..
Semiconductor Manufacturing International (beijing) Corporation

P-channel demos device

A p-channel drain extended metal oxide semiconductor (depmos) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain.
Texas Instruments Incorporated

High voltage ldmos transistor and methods for manufacturing the same

A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device

A semiconductor device is provided that includes a semiconductor substrate; an insulating film that is provided on the semiconductor substrate, has an opening through which the semiconductor substrate is exposed, and contains oxygen; a first barrier metal portion that is provided at least on a bottom portion of the opening and in which one or more kinds of films are laminated; and an upper electrode provided above the insulating film. The barrier metal is not provided between an upper surface of the insulating film and the upper electrode, or the semiconductor device further comprises a second barrier metal portion between the upper surface of the insulating film and the upper electrode, the second barrier metal portion having a configuration different from that of the first barrier metal portion..
Fuji Electric Co., Ltd.

Semiconductor device and manufacturing semiconductor device

In a first main surface side of a silicon carbide semiconductor base, a trench is formed. A second base region of a second conductivity type is arranged at a position facing the trench in a depth direction.
Fuji Electric Co., Ltd.

Semiconductor device with a guard structure and corresponding methods of manufacture

A semiconductor device includes a guard structure located laterally between a first active area of a semiconductor substrate and a second active area of the semiconductor substrate. The guard structure includes a first doping region located at a front side surface of the semiconductor substrate, and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region.
Infineon Technologies Ag

Method for fabricating semiconductor device

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first fin-shaped structure thereon; forming a spacer adjacent to the first fin-shaped structure; using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, wherein the second fin-shaped structure comprises a top portion and a bottom portion; and forming a doped portion in the bottom portion of the second fin-shaped structure.. .
United Microelectronics Corp.

Finfet with merge-free fins

A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions..
Globalfoundries Inc.

Semiconductor device, power supply apparatus and high-frequency amplifier

A semiconductor device includes a semiconductor stacked structure in which a semiconductor layer including an electron supply layer and an electron transit layer is stacked, and a gate electrode contacting with the semiconductor layer included in the semiconductor stacked structure or an insulating layer. The portion of the gate electrode contacting with the semiconductor layer or the insulating layer is an oxide of a metal configuring the portion of the gate electrode contacting with the semiconductor layer or the insulating layer..
Fujitsu Limited

Semiconductor device

A nitride semiconductor device is disclosed. The semiconductor device includes a semiconductor stack with a top layer containing gallium (ga) and nitrogen (n), electrodes of a source, a gate and a drain provided on the semiconductor stack, and a silicon nitride (sin) film provided on the gan layer between the drain electrode and the gate electrode but apart from the gate electrode.
Sumitomo Electric Device Innovations, Inc.

Semiconductor device

A semiconductor device has a semiconductor substrate including a first conductivity-type drift layer, a second conductivity-type base layer disposed in a surface layer portion of the drift layer, and a second conductivity-type collector layer and a first conductivity-type cathode layer disposed opposite to the base layer with respect to the drift layer. In the semiconductor substrate, an igbt region and a diode region are alternately and repetitively arranged.
Denso Corporation

Semiconductor device and manufacturing the same

A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.. .
Semiconductor Energy Laboratory Co., Ltd.

Method for manufacturing semiconductor device

A manufacturing method of a semiconductor device including a step of forming a silicon layer over a formation substrate, a step of forming a resin layer over the silicon layer, a step of forming a transistor over the resin layer, a step of forming a conductive layer over the silicon layer and the resin layer, and a step of separating the formation substrate and the transistor. The resin layer has an opening over the silicon layer.
Semiconductor Energy Laboratory Co., Ltd.

Oxide semiconductor film etching method and semiconductor device manufacturing method

An oxide semiconductor film etching method includes the step of: preparing a substrate (1) with an oxide semiconductor formed on a surface thereof, the oxide semiconductor film (7) containing in, sn, and zn; and etching the oxide semiconductor film (7) using an etching solution containing ammonium fluoride.. .
Sharp Kabushiki Kaisha

Manufacturing top gate thin-film transistor

The present invention provides a manufacturing method of a top gate thin-film transistor, which includes forming a reducing metal layer on an oxide semiconductor layer and applying laser annealing to reduce the oxide semiconductor layer that is covered with the reducing metal layer to conductors to respectively form a source contact zone and a drain contact zone, such that the source contact zone and the drain contact zone that have been reduced to conductors are used to respectively contact a source electrode and a drain electrode thereby greatly reducing the contact resistance of the source electrode and the drain electrode and improving the performance of a top gate thin-film transistor. The manufacturing process is simple..
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Method to improve reliability of replacement gate device

A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.. .
Globalfoundries Inc.

Semiconductor structure and fabrication method thereof

Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a dummy gate structure over the base substrate; forming source/drain regions having source/drain doping ions in the base substrate at both sides of the dummy gate structure; forming a dielectric layer on the source/drain regions and covering the side surfaces of the dummy gate structure; removing the dummy gate structure to form an opening in the dielectric layer; performing one or more of a first ion implantation process, for implanting first barrier ions in the base substrate toward the source region to form a first barrier layer under the opening, and a second ion implantation process, for implanting second barrier ions in the base substrate toward the source region to form a second barrier layer under the opening; and forming a gate structure in the opening..
Semiconductor Manufacturing International (beijing) Corporation

Contact plugs and methods forming same

A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an inter-layer dielectric (ild). The dummy gate stack is in the ild, and the ild covers a source/drain region in the semiconductor region.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device structure and forming the same

A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Nonvolatile storage circuit and semiconductor memory device including the same

A nonvolatile storage circuit may include a nonvolatile storage unit configured to include fuse set groups respectively including a plurality of fuse sets and a flag fuse; a rupture control unit configured to program an input address to the fuse sets in a first program mode, and to program a same input address to a specific fuse set among the plurality of fuse sets in a specific fuse set group among the fuse set groups and to program the flag fuse of the specific fuse set group in a second program mode; and a boot-up control unit configured to control the address programmed in the fuse sets to be outputted as fuse data, and to control the address programmed in the specific fuse set to be outputted as fuse data of remaining fuse sets among the plurality of fuse sets in the specific fuse set group.. .
Sk Hynix Inc.

Semiconductor device including sgt and producing the same

An sgt is formed in si pillars. The sgt includes wsi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions..
Unisantis Electronics Singapore Pte. Ltd.

Semiconductor device

A semiconductor device includes at least one memory cell including a first conductivity type first semiconductor region, a second conductivity type second semiconductor region, which is a source region of the memory cell, over a portion of the first semiconductor region, and a second conductivity type third semiconductor region, which is a drain region of the memory cell, over a portion of the first semiconductor region spaced from the second semiconductor region in a first direction, a gate insulating layer extending over a channel region of the memory cell, which includes a portion of the first semiconductor region between the second and third semiconductor regions, and including a first portion of first thickness and a second portion of second thickness less than the first thickness, an electrically floating gate electrode on the gate insulating layer, and a control gate adjacent to, and spaced from, the electrically floating gate electrode.. .
Toshiba Memory Corporation

Tft array substrate, manufacturing method thereof, and liquid crystal display apparatus

The present disclosure discloses a tft array substrate, a manufacturing method thereof and a liquid crystal display apparatus. The tft array substrate comprising: a substrate; and a tft disposed on the substrate; the tft comprises a semiconductor layer and both a source electrode and a drain electrode disposed on the semiconductor layer, and wherein a contact surface between the semiconductor layer and the source electrode and/or a contact surface between the semiconductor layer and the drain electrode are uneven structure.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Semiconductor device and manufacturing the same

A semiconductor device (100) is provided with a thin film transistor including an oxide semiconductor layer (5), a gate electrode (3), a gate insulating layer (4), and a source electrode (7s) and a drain electrode (7d) that are in contact with the oxide semiconductor layer, at least one electrode of the source electrode (7s), the drain electrode (7d), and the gate electrode (3) has a multilayer structure that includes a first layer (3a, 7a) containing copper and a second layer (3b, 7b) containing titanium or molybdenum, the thickness of the first layer (3a, 7a) is more than the thickness of the second layer (3b, 7b), when the source electrode (7s) or the drain electrode (7d) has the multilayer structure, the second layer is arranged on the oxide semiconductor layer side of the first layer so as to be in contact with the surface of the oxide semiconductor layer (5), when the gate electrode (3) has the multilayer structure, the second layer is arranged on the substrate (1) side of the first layer, and the thickness of the second layer is 15 nm or more and 25 nm or less.. .
Sharp Kabushiki Kaisha

Memory cell and non-volatile semiconductor storage device

A semiconductor integrated circuit device includes first and second select gate electrodes that are sidewall-shaped along sidewalls of a memory gate structure. With this configuration, the memory gate structure is not disposed on the first select gate electrode and the second select gate electrode.
Floadia Corporation

Field effect transistor and semiconductor device including the same

A semiconductor device, a field effect transistor, and a fin field effect transistor are provided. The semiconductor device may include a channel layer, a source/drain layer, and a gate electrode.
Samsung Electronics Co., Ltd.

Semiconductor device with silicided source/drain region

A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.. .
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor.
Taiwan Semiconductor Manufacturing Company. Ltd.

Co-integration of elastic and plastic relaxation on the same wafer

An n-doped field effect transistor (nfet) section of an integrated device logic region is provided. The nfet section includes a semiconductor substrate, a layer at least partially formed of silicon germanium (sige) disposed on the semiconductor substrate and fin formations.
International Business Machines Corporation

Structure comprising a 2-dimensional material

A semiconductor structure is provided including an electrically-conducting substrate and a layer of a two-dimensional material. The structure further includes a solid organic spacer layer arranged between the electrically-conducting substrate and the layer of the two-dimensional material..
International Business Machines Corporation

Semiconductor device

A semiconductor device includes: an active layer that is located in an soi substrate, and in which an element included in a circuit is formed; a buried insulation layer that is located in the soi substrate, and is in contact with the active layer; a deep trench isolation (dti) region that is formed in the active layer to surround a whole formation region of the element in plan view, and extends from an upper surface to a lower surface of the active layer; and a first conductive film formed above the element. The dti region has a first hole inside, and a film thickness of the first conductive film is greater than a thickness of the active layer..
Panasonic Intellectual Property Management Co., Ltd.

Power semiconductor device with charge balance design

A semiconductor body having first and second vertically spaced apart surfaces is formed. A gate trench that vertically extends from the first surface of the semiconductor body towards the second surface is formed.
Infineon Technologies Ag

Semiconductor device and manufacturing semiconductor device

In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited.
Fuji Electric Co., Ltd.

Metal resistors having varying resistivity

A semiconductor structure is provided that includes a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first nitridized dielectric surface layer portion having a first nitrogen content, a first metal portion, and a first dielectric capping layer portion.
International Business Machines Corporation

Semiconductor device structure useful for bulk transistor and manufacturing same

A semiconductor device including a semiconductor substrate with a first surface and a second surface facing each other, the semiconductor substrate having an element region in which a transistor is provided on the first surface, and a separation region in which an element separating layer surrounding the element region is provided; a contact plug extending from the first surface to the second surface, in the element region of the semiconductor substrate; and an insulating film covering a periphery of the contact plug.. .
Sony Corporation

Integrated magnetic tunnel junction (mtj) in back end of line (beol) interconnects

A method is presented for forming a semiconductor structure. The method includes depositing a barrier layer, such as a tantalum nitride (tan) layer, over a dielectric incorporating magnetic random access memory (mram) regions, forming magnetic tunnel junction (mtj) stacks over portions of the tan layer, patterning and encapsulating the mtj stacks, forming spacers adjacent the mtj stacks, and laterally etching sections of the tan layer, after spacer formation, to form an electrode under the mtj stacks.
International Business Machines Corporation

Imaging device, manufacturing method, and substrate dividing method

There is provided semiconductor devices and methods of forming the same, including: a first substrate; and a second substrate adjacent to the first substrate, where a side wall of the second substrate includes one or more diced portions that can include a blade diced portion and a stealth diced portion; and also imaging devices and methods of forming the same, including: a first substrate; a transparent layer; an adhesive layer between the first substrate and the transparent layer; a second substrate, where the first substrate is disposed between the adhesive layer and the second substrate; and a groove extending from the adhesive layer to the second substrate, where the groove is filled with the adhesive layer.. .
Sony Semiconductor Solutions Corporation

Solid-state imaging device

A solid-state imaging device includes a substrate of p type and a wiring layer. The substrate includes: a first semiconductor region disposed on a first principle surface and extending in a direction from the first principal surface toward the second principal surface; a second semiconductor region disposed between the second principal surface and the first semiconductor region and connected to the first semiconductor region; a p type semiconductor region disposed between the second principal surface and the second semiconductor regions of two pixels; and a pixel isolation region disposed inside the substrate, between the first semiconductor regions of the two pixels.
Panasonic Intellectual Property Management Co., Ltd.

Imaging device, manufacturing method, semiconductor device, and electronic device

The present disclosure relates to an imaging device, a manufacturing method, a semiconductor device, and an electronic device that can further improve image quality. An imaging device includes a photoelectric conversion unit that receives and photoelectrically converts light, a floating diffusion layer that accumulates charge generated by the photoelectric conversion unit, and a diffusion layer that serves as a source or a drain of a transistor.
Sony Semiconductor Solutions Corporation

Thin film transistor, display substrate and display panel having the same, and fabricating method thereof

The present application discloses a method of fabricating a thin film transistor, including forming a semiconductor layer having a pattern corresponding to that of the active layer on a base substrate; forming a first photoresist layer on a side of the semiconductor layer distal to the base substrate; the first photoresist layer being in an area corresponding to the channel region, the second doped region, and the fourth doped region; doping a region of the semiconductor layer corresponding to the first doped region and the third doped region using the first photoresist layer as a mask plate; forming a second photoresist layer by removing a portion of the first photoresist layer to expose an initial portion of the semiconductor layer corresponding to at least a portion of the second doped region and at least a portion of the fourth doped region; and doping the initial portion of the semiconductor layer using the second photoresist layer as a mask plate.. .
Ordos Yuansheng Optoelectronics Co., Ltd.

Array substrate and manufacturing method thereof

The present invention provides an array substrate and a manufacturing method thereof. The method includes covering a reduction metal layer on an oxide semiconductor layer film and simultaneously forming a source pattern, a drain pattern, a pixel electrode pattern, and an oxide semiconductor layer through patterning the oxide semiconductor layer film and the reduction metal layer with one mask-based operation, followed by reducing the source pattern, the drain pattern, and the pixel electrode pattern to conductors through laser annealing to simultaneously form a source electrode, a drain electrode, and a pixel electrode.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Display device

To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film.
Japan Display Inc.

Semiconductor device and electronic device

To provide a semiconductor device that is not easily damaged by esd in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 ev and less than or equal to 4.2 ev, preferably greater than or equal to 2.7 ev and less than or equal to 3.5 ev is provided to overlap with a dicing line.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and display device including the semiconductor device

Provided is a novel semiconductor device. The semiconductor device comprises a first transistor and a second transistor.
Semiconductor Energy Laboratory Co., Ltd.

Finfets with various fin height

A device and method of forming a semiconductor circuit having finfet devices that have fins of different height is provided. There is a shallow trench isolation layer (sti) on top of a semiconductor substrate.
International Business Machines Corporation

Semiconductor device

A semiconductor device includes a substrate, a first wiring line, a semiconductor film, a second wiring line, and an insulating film. The substrate includes first, second, and third regions provided adjacently in this order in a predetermined direction.
Joled Inc.

Electronic component having field effect transistor cells

An electronic component made up of field-effect transistor (fet) cells is disclosed. Each fet cell includes a finger region having drain, gate, and source fingers disposed over a semiconductor substrate.
Qorvo Us, Inc.

Multi-level ferroelectric memory device and manufacturing the same

A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor substrate may have a recess.
Sk Hynix Inc.

Multi-level ferroelectric memory device and manufacturing the same

A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor substrate may have a recess.
Sk Hynix Inc.

Nonvolatile semiconductor memory device and manufacturing same

A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.. .
Toshiba Memory Corporation

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device, includes: loading a substrate including a laminated film including an insulating film and a sacrificial film, a channel hole formed in the laminated film, a charge trapping film formed on a surface in the channel hole, a first channel film formed on a surface of the charge trapping film, and a common source line exposed on the bottom of the channel hole; receiving information on a distribution of hole diameter of the channel hole; and forming a second channel film on a surface of the first channel film by supplying a first processing gas and a second processing gas to a center side and an outer peripheral side of the substrate, respectively, so as to correct the distribution of the hole diameter based on the information.. .
Hitachi Kokusai Electric Inc.

Three-dimensional memory device with enhanced mechanical stability semiconductor pedestal and making thereof

After formation of an alternating stack of insulating layers and sacrificial material layers, a memory opening can be formed through the alternating stack, which is subsequently filled with a columnar semiconductor pedestal portion and a memory stack structure. Breakage of the columnar semiconductor pedestal portion under mechanical stress can be avoided by growing a laterally protruding semiconductor portion by selective deposition of a semiconductor material after removal of the sacrificial material layers to form backside recesses.
Sandisk Technologies Llc

Nonvolatile memory with erase gate region

A nonvolatile memory (nvm) cell includes a semiconductor substrate having a first od region and a second od region for forming an erase gate (eg) region. The second od region is spaced apart from the first od region and is separated from the first od region by a trench isolation region.
Ememory Technology Inc.

Semiconductor device and manufacturing same

The semiconductor device includes a base material, a plurality of electrode layers, and a first contact portion. The plurality of electrode layers are provided above the base material and arranged along a first direction.
Toshiba Memory Corporation

Semiconductor device and manufacturing method thereof

A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line.
Taiwan Semiconductor Manufacturing Co., Ltd.

Flash memory device and fabrication method thereof

Flash memory devices and fabrication methods thereof are provided. An exemplary method includes providing discrete bit lines on a semiconductor substrate, a first dielectric layer on top surfaces of the bit lines, and a floating gate structure on the first dielectric layer, trenches being formed between adjacent bit lines and on the semiconductor substrate; forming a sacrificial layer with a top surface above the top surfaces of the bit lines in the trenches; forming a second dielectric layer on top and side surfaces of the floating gate structure and the top surface of the sacrificial layer; forming a control gate structure on the second dielectric layer; removing portions of the second dielectric layer, the floating gate structure and the first dielectric layer to expose a portion of the sacrificial layer; and removing the sacrificial layer from the adjacent bit lines and the semiconductor substrate, thereby forming air gaps..
Semiconductor Manufacturing International (beijing) Corporation

Semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof include providing a substrate including an active region of a conductivity type and an isolation structure, in which the isolation structure surrounds the active region; forming a word line trench on the substrate, the word line trench intersecting the active region; and forming two doped regions in the active region at two sides of the word line trench respectively, in which each doped region and a bottom surface of the word line trench are located in a same level, and each doped region includes dopants of the conductivity type or an intrinsic semiconductor dopants.. .
Fujian Jinhua Integrated Circuit Co., Ltd.

Semiconductor memory devices having an undercut source/drain region

A semiconductor memory device includes, for example, a substrate having a fin having a web portion extending from the substrate and a first overhanging fin portion extending outward from the web portion and spaced from the substrate, the fin comprising a source/drain region in the web portion of the fin, a first source/drain region in the first overhanging fin portion, an isolation material surrounding the web portion and disposed under the first overhanging fin portion of the fin, an upper surface of the isolation material being below an upper surface of the fin, a first gate disposed over the fin between the source/drain region in the web portion of the fin and the first source/drain region in the first overhanging fin portion of the fin, and a capacitor operably electrically connected to the first source/drain region in the first overhanging fin portion.. .
Globalfoundries Inc.

Semiconductor device having buried gate structure and manufacturing the same, memory cell having the same and electronic device having the same

A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.. .
Sk Hynix Inc.

Semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The method includes providing a substrate, a plurality of word lines and a plurality of bit lines, and then forming a storage node contact on each source/drain region, so that a width of a top surface of each storage node contact in a direction is less than a width of a bottom surface of each storage node contact..
Fujian Jinhua Integrated Circuit Co., Ltd.

Semiconductor devices including varied depth recesses for contacts

A first conductivity type finfet device can include first embedded sources/drains of a first material that have a first etch rate. The first embedded sources/drains can each include an upper surface having a recessed portion and an outer raised portion relative to the recessed portion.
Samsung Electronics Co., Ltd

Semiconductor device

Provided is a semiconductor device including a substrate with first, second, and third logic cells, active patterns provided in each of the first to third logic cells to protrude from the substrate, and gate structures crossing the active patterns. The second and third logic cells are spaced apart from each other in a first direction with the first logic cell interposed therebetween.
Samsung Electronic Co., Ltd.

Finfet transistor with fin back biasing

A semiconductor device includes multiple first fins oriented lengthwise along a first direction and multiple first gate structures oriented lengthwise along a second direction generally perpendicular to the first direction. Each of the first fins includes an end that is narrower than a main body of the respective first fin.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device containing hemt and misfet and forming the same

A semiconductor structure with a misfet and a hemt region includes a first iii-v compound layer. A second iii-v compound layer is disposed on the first iii-v compound layer and is different from the first iii-v compound layer in composition.
Taiwan Semiconductor Manufacturing Company, Ltd.

Composite semiconductor device

A composite semiconductor device with improved response performance and reliability is provided while an increase in wiring area being suppressed. Fingers 1 are arranged in a plurality of rows and a plurality of columns.
Sharp Kabushiki Kaisha

Power semiconductor device having trench gate type igbt and diode regions

Switching loss is reduced. A first surface of a semiconductor substrate has a portion included in an igbt region and a portion included in a diode region.
Mitsubishi Electric Corporation

Power semiconductor device having trench gate type igbt and diode regions

Switching loss is reduced. A first surface of a semiconductor substrate has a portion included in an igbt region and a portion included in a diode region.
Mitsubishi Electric Corporation

Method of producing a semiconductor device

A semiconductor body having a drift region layer, a body region layer adjoining the drift region layer, and a source region layer adjoining the body region layer and forming a first surface of the semiconductor body is provided. At least two trenches extend from the first surface of the semiconductor body through the source region layer and the body region layer.
Infineon Technologies Austria Ag

Semiconductor integrated circuit device

A semiconductor integrated circuit device with a “pad on i/o cell” structure in which a pad lead part is disposed almost in the center of an i/o part so as to reduce the chip layout area. In the i/o part, a transistor lies nearest to the periphery of the semiconductor chip.
Renesas Electronics Corporation

Device for protection against electrostatic discharges with a distributed trigger circuit

An esd protection device includes a mos transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the mos transistor in response to an esd event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the mos transistor and includes a capacitive element and a resistive element.
Stmicroelectronics Sa

Packaging mechanisms for dies with different sizes of connectors

A semiconductor package includes a package substrate. A redistribution structure is bonded to the package substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Optoelectronic semiconductor component

An optoelectronic semiconductor component is disclosed, comprising: a semiconductor body (1) having a semiconductor layer sequence (2) with a p-type semiconductor region (3), an n-type semiconductor region (5), and an active layer (4) arranged between the p-type semiconductor region (3) and the n-type semiconductor region (5); a support (10) having a plastic material and a first via (11) and a second via (12); a p-contact layer (7) and an n-contact layer (8), at least some regions of which are arranged between the support (10) and the semiconductor body (1), wherein the p-contact layer (7) connects the first via (11) to the p-type semiconductor region (3) and the n-contact layer (8, 8a) connects the second via (12) to the n-type semiconductor region (5); and an esd protection element (15) which is arranged between the support (10) and the semiconductor body (1), wherein the esd protection element (15) is electrically conductively connected to the first via (11) and to the second via (12), and wherein a forward direction of the esd protection element (15) is anti-parallel to a forward direction of the semiconductor layer sequence (2).. .
Osram Opto Semiconductors Gmbh

Lighting module

The invention relates to a lighting module (1) comprising an assembly body (3) extending between a rear side (31) and a front side (30) opposite the rear side, and comprising a plurality of semiconductor components (2) provided for generating radiation, wherein: the assembly body has a plurality of recesses (35) on the rear side, in which the semiconductor components are arranged; the assembly body is permeable to the radiation generated in the semiconductor components, and said radiation passes out of the front side of the assembly body; a contact layer (5) is arranged on the rear side of the assembly body, to which the semiconductor components are connected in an electrically conductive manner via connecting lines; and a reflector layer (6) is arranged on the rear side of the assembly body, said reflector layer entirely covering at least the recesses.. .
Osram Opto Semiconductors Gmbh

Power semiconductor device

Provided is a power semiconductor device which is able to have improved connection reliability between a wiring line and an electrode of a power semiconductor element in comparison to conventional power semiconductor devices. This power semiconductor device is provided with: a semiconductor element; an insulating substrate having an electrode layer to which the semiconductor element is bonded; an external wiring line which is solder bonded to an upper surface electrode of the semiconductor element and has an end portion for external connection, said end portion being bent toward the upper surface; and a frame member which is affixed to the electrode layer of the insulating substrate.
Mitsubishi Electric Corporation

Clip and related methods

Implementations of a clip for a semiconductor package may include: an electrically conductive clip having a first end and a second end and a middle section between the first end and the second end. The first end may be configured to couple to a first die through a bonding material.
Semiconductor Components Industries, Llc

Semiconductor device and manufacturing semiconductor device

The manufacturing method of a semiconductor device includes applying a conductive paste containing metal particles to a specified area in an electrode plate including a recess in a surface of the electrode plate, the specified area being adjacent to the recess. The manufacturing method of a semiconductor device includes placing a semiconductor chip on the conductive paste so that an outer peripheral edge of the semiconductor chip is located above the recess.
Toyota Jidosha Kabushiki Kaisha

Fan-out semiconductor package

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; a resin layer disposed on the encapsulant; and a rear redistribution layer embedded in the encapsulant so that one surface thereof is exposed by the encapsulant, wherein the resin layer covers at least portions of the exposed one surface of the rear redistribution layer, and the rear redistribution layer is electrically connected to the redistribution layer of the first connection member through connection members formed in first openings penetrating through the resin layer and the encapsulant.. .
Samsung Electro-mechanics Co., Ltd.

Semiconductor package and manufacturing the same

A semiconductor package includes a substrate portion including a core layer having a device accommodating portion formed therein, and a buildup layer stacked on each of opposing sides of the core layer; an electronic device disposed in the device accommodating portion; and heat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device.. .
Samsung Electro-mechanics Co., Ltd.

Three-dimensional integrated circuit assembly with active interposer

Embodiments of the disclosure relate to a three-dimensional (3d) integrated circuit (ic) (3dic) assembly with active interposer. The 3dic assembly includes an antenna substrate having at least one electromagnetic radiating structure (e.g., an antenna) and a carrier substrate having layered conductive interconnects.
Qorvo Us, Inc.

Vanishing via for hardware ip protection from reverse engineering

A semiconductor device can include a first metal trace, a first via disposed on the first metal trace, a second metal trace disposed on the first via, and an insulator interposed between the first metal trace and the first via. The insulator can be configured to lower an energy barrier or redistribute structure defects or charge carriers, such that the first metal trace and the first via are electrically connected to each other when power is applied.
University Of Florida Research Foundation, Incorporated

Fan-out semiconductor package and manufacturing same

The present disclosure relates to a fan-out semiconductor package including a frame having a through hole, a semiconductor chip disposed in the through hole, a first encapsulant disposed in a space between the frame and the semiconductor chip, a second encapsulant disposed on one sides of the frame and the semiconductor chip, and a redistribution layer disposed on the other sides of the frame and the semiconductor chip, and a method of manufacturing the same. The first encapsulant and the second encapsulant may include different materials..
Samsung Electro-mechanics Co., Ltd.

Three dimensional integrated circuit (3dic) with support structures

Some embodiments of the present disclosure relate to an integrated circuit. The integrated circuit has a first semiconductor die and a second semiconductor die.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device manufacturing method and semiconductor wafer

A semiconductor wafer provided with a pseudo chip between a product chip and a pattern prohibiting region is prepared. With the edge portion of the semiconductor wafer left, the bottom surface of the inner semiconductor substrate is ground, and then, the semiconductor wafer is cut in a ring shape to remove the edge portion.
Renesas Electronics Corporation

Semiconductor device chip and manufacturing semiconductor device chip

A semiconductor device chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a semiconductor device disposed on the first surface of the semiconductor substrate, an interconnect pattern having an end connected to the semiconductor device and another end exposed on a surface of a function layer disposed on the first surface of the semiconductor substrate, plurality of external connection electrodes mounted on the surface of the function layer and electrically connected to the other end of the interconnect pattern, an electromagnetic wave shield film for shielding electromagnetic waves, which is disposed on the second surface of the semiconductor substrate and side surfaces of the function layer, and a ground interconnect electrically connected to the electromagnetic shield film and disposed on the function layer.. .
Disco Corporation

Semiconductor device and semiconductor device manufacturing method

A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a semiconductor chip provided upon an upper surface of the island, and having a pair of side portions mutually opposing each other; a plurality of signal terminals disposed at an external periphery of at least the pair of side portions of the semiconductor chip, and formed by the metallic layer; a grounding terminal disposed at an external periphery of the plurality of signal terminals, and formed by the metallic layer; electrically conductive connection members that are connected between each of a plurality of electrodes of the semiconductor chip and each of the plurality of signal terminals; sealing resin that seals the island, the semiconductor chip, the electrically conductive connection members, the plurality of signal terminals, and the grounding terminal, so that a lower surface of the island, lower surfaces of the plurality of signal terminals, and a lower surface of the grounding terminal are exposed to the exterior; and a metallic shielding layer that covers over an outer peripheral side surface and an supper surface of the sealing resin, and a portion of the grounding terminal.. .
Mitsubishi Electric Corporation

Semiconductor package with emi shield and fabricating method thereof

A semiconductor device with emi shield and a fabricating method thereof are provided. In one embodiment, the semiconductor device includes emi shield on all six surfaces of the semiconductor device without the use of a discrete emi lid..
Amkor Technology, Inc.

Wiring board with embedded component and integrated stiffener, making the same and face-to-face semiconductor assembly using the same

A wiring board includes an electronic component laterally surrounded by a stiffener, and a third routing circuitry disposed beyond the space laterally surrounded by the stiffener and extends over the stiffener. The electronic component includes a first routing circuitry, an encapsulant, an array of vertical connecting elements and a second routing circuitry integrated together.
Bridge Semiconductor Corporation

Semiconductor device including fuse structure

An efuse structure of a semiconductor device may include a first metal formed at a first level on a substrate, a second metal formed at a second level between the first level and the substrate, a third metal formed at a third level between the second level and the substrate, a first via connecting the first metal to the second metal, and a second via connecting the second metal to the third metal. The first metal may include a first portion extending in a first direction, a second portion extending in the first direction and being adjacent to the first portion, and a third portion connecting the first portion to the second portion.
Samsung Electronics Co., Ltd.

Interconnection structures for semiconductor devices and methods of fabricating the same

An interconnection structure includes an underlying layer including a lower interconnection, and an interlayered dielectric layer including a contact hole and a trench therein. The contact hole exposes a portion of the lower interconnection, and the trench extends along a first direction to be connected to the contact hole.
Samsung Electronics Co., Ltd.

Semiconductor device

An object is to provide a technique capable of enhancing electrical characteristics and reliability of a semiconductor device. The semiconductor device includes a plurality of semiconductor chips, a plurality of electrodes each being electrically connected to each of the plurality of semiconductor chips, a sealing member, and a joint part.
Mitsubishi Electric Corporation

3d semiconductor device and structure

A 3d semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; a plurality of third transistors overlaying the second transistors; a second metal layer overlaying the third transistors; and input/output pads to provide connection to external devices, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an electrostatic discharge (“esd”) structure connected to at least one of the input/output pads, where at least one of the third transistors is a junction-less transistor, and where a memory cell includes at least one of the third transistors.. .
Monolithic 3d Inc.

Molding compound structure

A device comprises a package component comprising a plurality of bumps formed on a first side of the package component, a semiconductor die mounted on the first side of the package component, a dielectric material formed over the first side of the package component, wherein four corners of the top surface of the package component are free from the dielectric material and a top package bonded on the first side of the package component, wherein the semiconductor die is located between the top package and the package component.. .
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device with frame having arms and related methods

A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an ic die pad in the opening, and arms extending outwardly from the ic die pad and coupled to the circuit board.
Stmicroelectronics, Inc.

Conductive clip connection arrangements for semiconductor packages

Conductive clip connection arrangements for semiconductor packages are disclosed. Some examples provide electrically conductive clip connection arrangements for semiconductor packages that improve electrical performance and fabrication reliability while maintaining compatibility with existing quality control processes.
Silanna Asia Pte Ltd

Semiconductor device

A semiconductor device includes a semiconductor element, a lead on which the semiconductor element is mounted, a bonding member fixing the semiconductor element to the lead, and a resin package enclosing the semiconductor element and a portion of the lead. This lead is formed with a groove recessed at a location spaced from the semiconductor element.
Rohm Co., Ltd.

Surface passivation having reduced interface defect density

Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect density. A semiconductor layer is formed on a substrate.
International Business Machines Corporation

Surface passivation having reduced interface defect density

Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect density. A semiconductor layer is formed on a substrate.
International Business Machines Corporation

Thermally enhanced semiconductor package with thermal additive and process for making the same

The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die.
Qorvo Us, Inc.

Semiconductor device

A semiconductor device includes a semiconductor element, a base, and an outer packaging resin. The base has a mounting surface, on which the semiconductor element is mounted, and a groove provided around the semiconductor element on the mounting surface.
Panasonic Intellectual Property Management Co., Ltd.

Semiconductor device, chip module, and semiconductor module

Provided is a semiconductor device having a surface layer power supply path in a surface layer wiring layer, on which a chip module is mounted, of a main substrate that has a plurality of wiring layers and through holes, the surface layer power supply path supplying power to a semiconductor chip via an inner peripheral-side power supply terminal group and an outer peripheral-side power supply terminal group. The surface layer power supply path overlaps the inner peripheral-side power supply terminal group and the outer peripheral-side power supply terminal group as seen in the orthogonal direction, and is formed continuously so as to extend in a direction from a position at which the surface layer power supply path is connected to the inner peripheral-side power supply terminal group toward the outer peripheral side of the main substrate..
Aisin Aw Co., Ltd.

Semiconductor module

A semiconductor module includes a case. The case includes a bottom part, a case frame, and a case lid.
Mitsubishi Electric Corporation

Replacement gate process for semiconductor devices

Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (hm) layer over the electrode layer, and a second hm layer over the first hm layer.
Taiwan Semiconductor Manufacturing Company, Ltd.

Self-aligned doping in source/drain regions for low contact resistance

Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method includes forming a first semiconductor fin in a first region of a substrate and a second semiconductor fin in a second region of the substrate.
International Business Machines Corporation

Self-aligned doping in source/drain regions for low contact resistance

Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method includes forming a first semiconductor fin in a first region of a substrate and a second semiconductor fin in a second region of the substrate.
International Business Machines Corporation

Semiconductor devices having fin active regions

Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region..
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing the same

A method for manufacturing a semiconductor is provided. A first oxide layer is formed on a substrate.
Samsung Electronics Co., Ltd.

Replacement channel etch for high quality interface

Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage.
Intel Corporation

3d vertical fet with top and bottom gate contacts

A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side above the gate structure and a bottom side below the gate structure.
International Business Machines Corporation

3d vertical fet with top and bottom gate contacts

A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side above the gate structure and a bottom side below the gate structure.
International Business Machines Corporation

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate, and forming an interlayer dielectric layer on the base substrate and having an opening exposing surface portions of the base substrate.
Semiconductor Manufacturing International (beijing) Corporation

Method of forming a fin structure of semiconductor device

A method of forming a fin structure of a semiconductor device, such as a fin field effect transistor (finfet) is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin.
Taiwan Semiconductor Manufacturing Company, Ltd.

Fin spacer protected source and drain regions in finfets

A method includes forming shallow trench isolation (sti) regions in a semiconductor substrate and a semiconductor strip between the sti regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer.
Taiwan Semiconductor Manufacturing Company, Ltd.

Pnp-type bipolar transistor manufacturing method

A pnp transistor is manufactured in parallel with the manufacture of npn, nmos, and pmos transistors. A first semiconductor layer is deposited on a p-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base.
Stmicroelectronics (crolles 2) Sas

Organic light emitting diode display device and fabricating the same

An organic light emitting diode display device comprises a driving thin film transistor including a first semiconductor layer, a gate insulating layer formed on the first semiconductor layer. The device further includes a storage capacitor including a first capacitor electrode electrically coupled to a drain electrode of the driving thin film transistor, a buffer layer formed on the first capacitor electrode, a second semiconductor layer formed on the buffer layer, and a second capacitor electrode formed on the second semiconductor layer and electrically coupled to a gate electrode of the driving thin film transistor.
Lg Display Co., Ltd.

Manufacturing process of element chip

Provided is a manufacturing process of an element chip, which comprises a preparation step for preparing a substrate including a semiconductor layer having first and second sides and a wiring layer on the first side thereof, the substrate having a plurality of dicing regions and element regions defined by the dicing regions, a scribing step for radiating a laser beam towards the first side of the wiring layer onto the dicing regions to form apertures exposing the semiconductor layer along the dicing regions, and a dicing step for dicing the substrate along the apertures into a plurality of the element chips, wherein the laser beam has a beam profile having a m-shaped distribution whose peripheral intensity is greater than a central intensity in a width direction of the laser beam along the dicing regions.. .
Panasonic Intellectual Property Management Co., Ltd.

Semiconductor device with an interconnect structure and forming the same

A method for forming a semiconductor device structure includes providing a substrate and forming a gate electrode on the substrate. A first contact structure is formed in and on the gate electrode.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method for forming fin field effect transistor (finfet) device structure with interconnect structure

A semiconductor device structure includes a first metal layer formed over a substrate and an interconnect structure formed over the first metal layer. The interconnect structure includes an upper portion, a middle portion and a lower portion, the middle portion is connected between the upper portion and the lower portion.
Taiwan Semiconductor Manufacturing Co., Ltd.

Deposition of aluminum oxide etch stop layers

Aluminum oxide films characterized by a dielectric constant (k) of less than about 7 (such as between about 4-6) and having a density of at least about 2.5 g/cm3 (such as about 3.0-3.2 g/cm3) are deposited on partially fabricated semiconductor devices over both metal and dielectric to serve as etch stop layers. The films are deposited using a deposition method that does not lead to oxidative damage of the metal.
Lam Research Corporation

Semiconductor on insulator structure comprising a sacrificial layer and manufacture thereof

A method is provided for preparing a semiconductor-on-insulator structure comprising a sacrificial layer.. .
Sunedison Semiconductor Limited (uen201334164h)

Semiconductor device and manufacturing same

To provide a semiconductor device having improved performance. The semiconductor device has a first insulating film formed on the main surface of a semiconductor substrate and a second insulating film formed on the first insulating film.
Renesas Electronics Corporation

Semiconductor wafer surface protection film and manufacturing semiconductor device

This semiconductor wafer surface protection film has a substrate layer a, an adhesive absorption layer b, and adhesive surface layer c, in the stated order. The adhesive absorption layer b comprises an adhesive composition containing a thermoset resin b1, said adhesive absorption layer b having a minimum value g′bmin of the storage elastic modulus g′b in the range of 25° c.
Mitsui Chemicals Tohcello, Inc.

Apparatus and methods for testing semiconductor devices

The invention is a cost effective multisite parallel wafer tester that has an array of stationary wafer test sites; a single mobile wafer handling and alignment carriage that holds a wafer handling robot, a wafer rotation pre-alignment assembly, a wafer alignment assembly, a wafer front opening unified pod (foup), and a wafer camera assembly; and a robot that moves the wafer handling and alignment carriage to and from each test site. Each test site contains a wafer probe card assembly and a floating chuck.

Semiconductor device and its manufacturing method

The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a pad electrode formed at the uppermost layer of a plurality of wiring layers, a surface protective film having an opening over the pad electrode, a redistribution line being formed over the surface protective film and having an upper surface and a side surface, a sidewall barrier film comprising an insulating film covering the side surface and exposing the upper surface of the redistribution line, and a cap metallic film covering the upper surface of the redistribution line.
Renesas Electronics Corporation

Hard masks for block patterning

Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (sit) block patterning. The method includes forming a first hard mask on a substrate.
International Business Machines Corporation

Hard masks for block patterning

Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (sit) block patterning. The method includes forming a first hard mask on a substrate.
International Business Machines Corporation

Layout effect mitigation in finfet

Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as finfet devices, long isolation cut masks may be used.
Qualcomm Incorporated

Doping semiconductor device

A doping method for a semiconductor device including the following steps is provided. A substrate is provided.
United Microelectronics Corp.

Methods of fabricating semiconductor device

An etching target layer is formed on a substrate. An upper mask layer is formed on the etching target layer.

Fin patterns with varying spacing without fin cut

Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of multiple mandrels using an angled deposition process. A second sidewall of one or more of the mandrels is masked in a finless region.
International Business Machines Corporation

High electron mobility transistor manufacturing method and high electron mobility transistor

Examples of a high electron mobility transistor manufacturing method includes forming a buffer layer including a nitride semiconductor doped with any one of carbon, iron, and magnesium on a substrate, forming a schottky layer on the buffer layer, and irradiating the schottky layer and the buffer layer with electrons or protons.. .
Mitsubishi Electric Corporation

Systems and methods for graphene based layer transfer

A graphene-based layer transfer (gblt) technique is disclosed. In this approach, a device layer including a iii-v semiconductor, si, ge, iii-n semiconductor, sic, sige, or ii-vi semiconductor is fabricated on a graphene layer, which in turn is disposed on a substrate.
Massachusetts Institute Of Technology

Silicon chalcogenate precursors and methods of forming the silicon chalcogenate precursors

A silicon chalcogenate precursor comprising the chemical formula of si(xr1)nr24-n, where x is sulfur, selenium, or tellurium, r1 is hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, each r2 is independently hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, and n is 1, 2, 3, or 4. Methods of forming the silicon chalcogenate precursor, methods of forming silicon nitride, and methods of forming a semiconductor structure are also disclosed..
Micron Technology, Inc.

Buffer layer to inhibit wormholes in semiconductor fabrication

Reducing wormhole formation during n-type transistor fabrication includes providing a starting structure, the starting structure including a semiconductor substrate, a n-type source region and a n-type drain region of a transistor. The method further includes removing a portion of each of the n-type source region and the n-type drain region, the removing creating a source trench and a drain trench, and forming a buffer layer of silicon-based material(s) over the n-type source region and n-type drain region that is sufficiently thick to inhibit interaction between metal contaminants that may be present below surfaces of the n-type source trench and/or the n-type drain trench, and halogens subsequently introduced prior to source and drain formation.
Globalfoundries Inc.

Methods of forming staircase-shaped connection structures of three-dimensional semiconductor devices

Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween.
Samsung Electronics Co., Ltd.

Resist pattern coating composition including vinyl group- or (meth) acryloxy group-containing polysiloxane

A composition to be applied onto a resist pattern comprising a polysiloxane obtained by hydrolytically condensing a hydrolyzable silane and a carboxylic ester solvent or an ether solvent, wherein the hydrolyzable silane includes a vinyl group- or (meth)acryloxy group-containing hydrolyzable silane. A hydrolyzable silane includes the vinyl group- or (meth)acryloxy group-containing hydrolyzable silane at a content of 20 to 100 mol % in the total hydrolyzable silane.
Nissan Chemical Industries, Ltd.

Semiconductor device and manufacturing semiconductor device

A second protective film is formed by applying high-viscosity resin by an inkjet method, in two patterns that extend parallel to and along a boundary between a first protective film and a plating film, the boundary being sandwiched between the two patterns. A low-viscosity resin is applied between these first and second patterns of the second protective film by the inkjet method.
Fuji Electric Co., Ltd.

Cathode with improved rf power efficiency for semiconductor processing equipment with rf plasma

A cathode assembly for use in a plasma processing chamber is provided. A metal bowl that is grounded is provided.
Lam Research Corporation

Integrated circuit analysis systems and methods with localized evacuated volume for e-beam operation

Provided are new techniques for fault analysis in ic semiconductor devices, including system designs and methods to enable the probing of circuitry within an ic device under test (dut) using electron beam (e-beam) techniques while the dut is being stimulated electrically, or while the device is active on its own or within a host system mounted in a circuit board or other module. The dut could be a packaged ic, or an ic in some unpackaged form.
Fei Company

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation.
Toshiba Memory Corporation

Nonvolatile semiconductor memory device

When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block.
Toshiba Memory Corporation

Three dimensional stacked nonvolatile semiconductor memory

A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential.
Toshiba Memory Corporation

Semiconductor memory device

A semiconductor memory device includes first and second memory cells, first and second select transistors having first ends connected to the first and second memory cells, respectively, first and second bit lines connected to second ends of the first and second select transistors, respectively, and a select gate line connected to the first and second select transistors. A write operation includes first and second program loops.
Toshiba Memory Corporation

Memory read stability enhancement with short segmented bit line architecture

In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

This invention relates to a semiconductor device that reduces energy consumed to write data to a nonvolatile storing section. A write control circuit 34 stores the same data as that held in mtj elements mtj1 and mtj2.
Sony Corporation

Semiconductor devices

A semiconductor device may be provided. The semiconductor device may include an error scrub control circuit and or an active period signal generation circuit.
Sk Hynix Inc.

Apparatuses and methods for a memory device with dual common data i/o lines

Apparatuses are presented for a semiconductor device utilizing dual i/o line pairs. The apparatus includes a first i/o line pair coupled to a first local i/o line pair.
Micron Technology, Inc.

Semiconductor device

Disclosed is a semiconductor device, including a memory cell array including a plurality of memory cells, a read circuit suitable for generating read data corresponding to a read current flowing in a first direction through a selected memory cell of the plurality of memory cells, a reverse read control circuit suitable for generating a reverse read control signal corresponding to the read data, and a reverse current generation circuit suitable for generating a reverse current flowing in a second direction through the selected memory cell in response to the reverse read control signal.. .
Sk Hynix Inc.

Semiconductor device and operating method thereof

A semiconductor memory device may include a memory cell array. The semiconductor memory device may include a peripheral circuit coupled to the memory cell array through word lines.
Sk Hynix Inc.

Localized business analytics

A system includes a memory and a semiconductor-based processor coupled to form logic circuits. The logic circuits provide a localization (lpn) web service to a computer application having business analytics functions, for a recommendation on how to localize the business analytics performed by the computer application to target a specific group of consumers, prepare a recommendation on reconfiguring the business analytics logic of the computer application to perform business analytics localized to target the specific group of consumers, and provide the recommendation to the computer application to set up a localized (lpn) computer application to perform business analytics targeting the specific group of consumers..
Sap Se

Method for operating semiconductor device

Provided is a method of operating a semiconductor device. A method of operating a semiconductor device includes storing secure data in a secure area of a memory in response to detecting a system failure; encrypting the secure data stored in the secure area by using a random key to generate encrypted secure data; storing the encrypted secure data in the secure area; and dumping the secure area and a non-secure area of the memory..
Samsung Electronics Co., Ltd.

Methods for cell phasing and placement in dynamic array architecture and implementation of the same

A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates.
Tela Innovations, Inc.

Semiconductor memory device with data buffering

A semiconductor storage device includes at least two nonvolatile semiconductor memories, a buffer in which data received from a host and to be written to the nonvolatile semiconductor memories in response to a write command received from the host can be temporarily stored, and a controller connected to the nonvolatile semiconductor memories and configured to transfer data stored in the buffer to a number n of the nonvolatile semiconductor memories in parallel. The number n is set according to a reception of data from the host, and n is greater than or equal to 1 and less than or equal to m, which is the number of nonvolatile semiconductor memories connected to the controller..
Toshiba Memory Corporation

Memory controller, memory control method and semiconductor storage apparatus

In a memory controller, command, address and data are allocated to transmit the command, the address and the data to each of the plurality of memory devices through the same bus signal line and an identification signal to identify the command, the address and the data on the bus signal line is allocated to a memory common signal line in common among the plurality of memory devices to transmit the identification signal. When the memory controller indicates the data through the identification signal so as to make a first memory device transfer the data through the bus signal line, the memory controller makes the data transfer by the first memory device suspended, indicates the command through the identification signal so as to issue the command to a second memory device, and indicates the address through the identification signal so as to issue the address to the second memory device..
Hitachi, Ltd.

Semiconductor device

A semiconductor device includes a write read control circuit for outputting a write enable signal which is enabled in response to a write command, and a test mode signal; and an error correction circuit suitable for performing a calculation operation of determining an error information of input data in response to the write enable signal and then outputting an internal parity signal including the error information, and outputting internal data by delaying the input data in response to the write enable signal.. .
Sk Hynix Inc.

Memory device

According to one embodiment, a semiconductor memory device includes: a memory configured to store data; an error correcting circuit configured to correct an error in data read from the memory, and to generate a first signal of a first state, which is transmitted to an external along with the data if the error in the data cannot be corrected; and a first pin configured to transmit the first signal to the external and receive a data mask signal from the external.. .
Toshiba Memory Corporation

Semiconductor device with power on reset circuitry

A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below.
Renesas Electronics Corporation

Semiconductor device

A semiconductor device includes a detection signal generation circuit generating a detection signal by detecting a phase difference of an input signal and an internal clock, and generating delayed input signals by delaying the input signal. The semiconductor device further includes an output enable signal generation circuit outputting an output enable signal by selecting one of the delayed input signals in response to the detection signal and latching the selected one of the delayed input signals in synchronization with the internal clock.
Sk Hynix Inc.

Optical transmission apparatus, semiconductor integrated driving device

An optical transmission apparatus includes: a mach-zehnder modulator including a first arm waveguide having electrodes; and a driver driving the mach-zehnder modulator in response to a pulse amplitude modulated signal, the driver including driving circuits connected to the respective electrodes and each of the driving circuits including a comparator receiving the pulse amplitude modulated signal.. .
Sumitomo Electric Industries, Ltd.

Display device

To achieve a display device that is suitable for increasing in size and to provide a high-resolution display device. In the display device, three or more adjacent gate lines are supplied with the same selection signal.
Semiconductor Energy Laboratory Co., Ltd.

Liquid crystal display

A liquid crystal display includes a first substrate, a gate line disposed on an upper portion of the first substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line and a drain electrode disposed on the semiconductor layer, a passivation layer which covers the data line and the drain electrode and defines a contact hole which exposes a part of the drain electrode, a common electrode provided at an upper portion of the passivation layer and having a planar structure, a pixel electrode electrically connected to the drain electrode through the contact hole and including a plurality of pixel branch electrodes, and a second substrate corresponding to the first substrate, where an opening is defined in the common electrode at a position which corresponds to a middle region of the plurality of pixel branch electrodes.. .
Samsung Display Co., Ltd.

Method and system for electro-absorption modulator drivers in cmos

Methods and systems for electro-absorption modulator drivers in cmos may comprise an electro-absorption modulator optically coupled to a laser source and electrically coupled to a modulator driver circuit that is in a complementary metal oxide semiconductor (cmos) chip. The electro-absorption modulator includes a summer for receiving a negative bias voltage and a programmable offset voltage, a voltage regulator for receiving the output of the summer and generating a negative dc voltage of lower magnitude than the negative bias voltage, level shifting circuitry for shifting a received data signal to a dc voltage level between the negative dc voltage from the voltage regulator and the negative bias voltage, and an electrical coupling structure for dc-coupling the level shifted data signal to the modulator.
Maxlinear, Inc.

Radiation detector

The present invention provides a radiation detection system for detecting x-ray and gamma rays featuring cd1-xmgxte in solid solution as a crystal semiconductor and electrical connection means. The crystal has a composition in the range of cd0.99mg0.01te to cd0.71mg0.29te and may be doped with indium or another group iii element, which may be suitable for use at room temperature as well as controlled temperatures.
International Crystal Laboratories

Optical modulating device and system including the same

Provided are an optical modulating device and a system including the optical modulating device. The optical modulating device includes a substrate, and a phase modulator formed on the substrate and including a fabry-perot cavity.
California Institute Of Technology

Test architecture with an fpga based test board to simulate a dut or end-point

An automated test equipment (ate) system capable of performing a test of semiconductor devices is presented. The system comprises a first test board including a first fpga communicatively coupled to a controller via an interface board, wherein the first fpga comprises a first core programmed to implement a communication protocol, and further wherein the fpga is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a dut.
Advantest Corporation

Free piston stirling cooler temperature control system for semiconductor test

A portable cooling system and apparatus for semiconductor device testing includes a free piston stirling cooler. This eliminates the need for cumbersome remotely located equipment, such as a chillers, compressors, coolant storage equipment, hoses and hose connections.
Sensata Technologies

Cmos compatible biofet

The present disclosure provides a bio-field effect transistor (biofet) and a method of fabricating a biofet device. The method includes forming a biofet using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (cmos) process.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method of measuring an adhesive force of interlayer adhesive layer in tensile mode for stacked semiconductor device and measuring the same

A method includes providing a device under test, which includes a lower test layer and an upper test layer that is stacked on the lower test layer and includes an overhang protruding past an edge of the lower test layer by a predetermined length, fixing the lower test layer onto a mounting stage, and measuring adhesive force of an interlayer adhesive layer in a tensile mode by applying a load to a bottom surface of the overhang of the upper test layer in a first direction. An apparatus includes a mounting stage fixing the device under test, a load applying tip applying the load to the bottom surface of the overhang, a location adjuster adjusting a distance between the device under test and the load carrying tip, a load cell detecting a magnitude of the applied load, and a controller controlling the location adjuster and the load cell..
Industry-academic Cooperation Foundation, Yeungnam University

Window blind

A window blind is disclosed. The window blind includes a slat having a convex curved surface.
Lg Electronics Inc.

Wavelength conversion member and light-emitting device

A wavelength conversion member includes a light-transmitting medium and phosphor-containing particles dispersed in the light-transmitting medium and including a resin and a semiconductor nanoparticle phosphor dispersed in the resin, wherein the phosphor-containing particles have a particle size that is equal to or larger than a particle size of the semiconductor nanoparticle phosphor and that is equal to or smaller than a minimum thickness of the wavelength conversion member. A light-emitting device includes a light source and a wavelength converter including a light-transmitting medium and phosphor-containing particles including a resin including a constitutional unit derived from an ionic liquid having a polymerizable functional group and a semiconductor nanoparticle phosphor dispersed in the resin, wherein the phosphor-containing particles have a particle size that is equal to or larger than a particle size of the semiconductor nanoparticle phosphor and that is equal to or smaller than a minimum thickness of the wavelength converter..
Sharp Kabushiki Kaisha

Devices and methods for electrochemical liquid phase epitaxy

Electrochemical liquid phase epitaxy (ec-lpe) processes and devices are provided that can form precipitated epitaxial crystalline films or layers on a substrate. The precipitated films may comprise a semiconductor, such as germanium, silicon, or carbon.
The Regents Of The University Of Michigan

Protective oxide coating with reduced metal concentrations

A method is introduced for creating a protective oxide layer over a surface of a metallic structure for use in a semiconductor processing system. The method includes providing the metallic structure, anodizing the surface of the metallic structure to form an anodization layer on the surface, and converting, using a plasma electrolytic oxidation process, at least a portion of the anodization layer to form the protective oxide layer..
Mks Instruments, Inc.

Deposition method

A deposition method relating to semiconductor technology is presented. The deposition method includes: conducting a first deposition in a reaction chamber at a first deposition temperature; conducting a cool-down process on the reaction chamber, and conducting a second deposition during the cool-down process.
Semiconductor Manufacturing International (beijing) Corporation

Thermally conductive composition, semiconductor device, manufacturing semiconductor device, and bonding heatsink

A thermally conductive composition of the present invention contains metal particles (a) and a dispersion medium (b) in which the metal particles (a) are dispersed, wherein the metal particles (a) form a particle coupling structure by being sintered through a thermal treatment, the metal particles (a) have a particle size d50 at 50% in a volume-based cumulative distribution of equal to or greater than 0.8 μm and equal to or smaller than 5 μm, and the metal particles (a) have a standard deviation of the particle size of equal to or less than 2.0 μm.. .
Sumitomo Bakelite Co., Ltd.

Optical sensor with narrow angular response

An optical sensor based on cmos technology including a semiconductor substrate; an array of photocells, each of which includes a respective photodetector active area that is formed in and exposed on a given planar surface of said semiconductor substrate; a multilayer structure that includes metal and dielectric layers and is formed on the given planar surface; and light shielding means formed in or on the multilayer structure; wherein each photodetector active area is associated with a corresponding optical path extending through the light shielding means and directed towards said photodetector active area. All the photocells are connected in parallel to provide an overall output electrical signal related to incident light impinging on the photodetector active areas.
Lfoundry S.r.l.

Body parameter monitoring device

An apparatus for determining at least one physiological parameter includes a carrier and one or more semiconductor components. At least one of the semiconductor components includes a sensor for sensing a physiological parameter.
Steadysense Gmbh

Sony Corporation

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Shin-etsu Chemical Co., Ltd.

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Nec Corporation

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Furukawa Electric Co., Ltd.

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Display device using semiconductor light-emitting device and manufacturing method therefor

The present invention relates to a display device and, particularly, to a display device using a semiconductor light-emitting device. The display device according to the present invention comprises a semiconductor light-emitting device, and the semiconductor light-emitting device comprises: a first conductive semiconductor layer; a second conductive semiconductor layer having a lateral surface, and overlapped with the first conductive semiconductor layer; a first conductive electrode electrically connected to the first conductive semiconductor layer; and a second conductive electrode electrically connected to the second conductive semiconductor layer, wherein the second conductive semiconductor layer has an inclined part inclined with respect to the lateral surface, and the second conductive electrode is formed so as to cover the inclined part..
Lg Electronics Inc.

System for identifying a 3d chip

A semiconductor chip includes a plurality of superposed semiconductor levels. The semiconductor levels include a plurality of elementary circuits coupled to a common input node.
Stmicroelectronics (crolles 2) Sas

Solid-state imaging device

A solid-state imaging device includes a photodetecting unit and a signal readout unit, and further includes a control unit controlling an operation of each of the photodetecting unit and the signal readout unit. The photodetecting unit includes m×n pixels on a first principal surface of a semiconductor substrate having the first principal surface and a second principal surface opposite to each other.
Hamamatsu Photonics K.k.

Display unit, manufacturing the same, and electronic apparatus

A display unit includes: a display layer including a pixel electrode; a semiconductor layer provided in a layer below the display layer, the semiconductor layer including a wiring layer that includes a material removable by an etchant by which the pixel electrode is also removable; and a terminal section configured to electrically connect the semiconductor layer to an external circuit, the terminal section including a first electrically-conductive layer made of a material same as a material of the wiring layer.. .
Sony Corporation

Nonvolatile semiconductor devices including non-circular shaped channel patterns and methods of manufacturing the same

A non-volatile memory structure can include a substrate extending horizontally and a filling insulating pattern extending vertically from the substrate. A plurality of active channel patterns can extend vertically from the substrate in a zig-zag pattern around a perimeter of the filling insulating pattern, where each of the active channel patterns having a respective non-circular shaped horizontal cross-section.
Samsung Electronics Co., Ltd.

Systems and methods for a gate drive circuit

Systems and methods provided herein relate to a gate drive circuit for controlling operation of a wide bandgap semiconductor switch. The systems and methods receive a control signal and configuring an operation signal configured to activate a wide bandgap switch (wbg switch).
General Electric Comapny

Insulated gate semiconductor device and manufacturing insulated gate semiconductor device

An insulating gate semiconductor device includes an insulating gate semiconductor element, an insulating circuit board, and a main-current path member. A main-current of the insulating gate semiconductor element flows toward a first external terminal in the main-current path member; and a gate-current path member, being patterned so as to have a linearly extending portion arranged in parallel to a linearly extending portion of the main-current path member in a planar pattern on the insulating circuit board, being provided to connect between a second external terminal and a gate electrode of the insulating gate semiconductor element.
Fuji Electric Co., Ltd.

Bulk acoustic wave filter and a frequency tuning for bulk acoustic wave resonator of bulk acoustic wave filter

A method for forming cavity of bulk acoustic wave resonator comprising following steps of: forming a sacrificial epitaxial structure mesa on a compound semiconductor substrate; forming an insulating layer on the sacrificial epitaxial structure mesa and the compound semiconductor substrate; polishing the insulating layer by a chemical-mechanical planarization process to form a polished surface; forming a bulk acoustic wave resonance structure on the polished surface, which comprises following steps of: forming a bottom electrode layer on the polished surface; forming a piezoelectric layer on the bottom electrode layer; and forming a top electrode layer on the piezoelectric layer, wherein the bulk acoustic wave resonance structure is located above the sacrificial epitaxial structure mesa; and etching the sacrificial epitaxial structure mesa to form a cavity, wherein the cavity is located under the bulk acoustic wave resonance structure.. .
Win Semiconductors Corp.

Semiconductor device drive circuit and inverter device

A semiconductor device drive circuit drives a semiconductor switching device including a first electrode, a second electrode, and a control electrode. The semiconductor device drive circuit includes an input terminal that receives an input signal; a level shift unit that shifts a voltage level of the input signal and outputs a drive signal to be supplied to the control electrode; a first resistor that generates a first current from a first voltage applied to the first electrode; a second resistor that generates a second current from a second voltage applied to the second electrode; and a voltage difference determination unit that outputs a detection signal when a difference between the first current and the second current is equal to or greater than a predetermined desaturation determination value.
Mitsubishi Electric Corporation

Electric compressor

A motor-driven compressor includes a compressor unit, a motor unit including a motor, and an inverter unit that drives the motor. The compressor unit, the motor unit, and the inverter unit are lined up in an axial direction of the motor.
Kabushiki Kaisha Toyota Jidoshokki

Power distribution systems

A power distribution system has a power converter with a plurality of semiconductor switching devices per phase, a pwm controller, and a current limitation controller. The current limitation controller is adapted, at least when a short-circuit fault is detected, to calculate the difference between a measured current for each phase and a reference current for the corresponding phase.
Ge Energy Power Conversion Technology Limited

Light-emitting device having iii-v semiconductor gain section coupled to whistle-geometry tunable filter

The invention concerns a wavelength tunable semiconductor laser comprising a laser gain section (510) optically coupled to an underlying optical waveguide (520). According to an embodiment of the invention, a first and a second passive microring resonators (530, 560) having a whistle geometry, are arranged on both sides of the laser gain section and evanescently coupled with the optical waveguide (520).
Stc.unm

Folded waveguide structure semiconductor laser

A laser apparatus is provided, comprising a semiconductor substrate, an active layer disposed on the semiconductor substrate, a folded waveguide disposed on the active layer and forming a resonant structure, the folded waveguide comprising at least two substantially straight waveguide portions coupled by a connecting waveguide structure, with the folded waveguide having a first end and a second end located at one or more edges of the semiconductor substrate, wherein at least one of the ends includes a mirror, and an electrode coupled to the folded waveguide and configured to create photons in the folded waveguide when receiving electrical power. The waveguide emits laser light comprising the photons, with the laser light emitted at an edge of the semiconductor substrate..
Futurewei Technologies, Inc.

Wavelength-tunable external-cavity laser and adjustable light emission module

A wavelength-tunable external cavity laser comprises a semiconductor optical amplifier chip and a laser external cavity, the laser external cavity comprising a grid filter, a phase adjustor and a silicon-based micro-ring chip, the grid filter and the silicon-based micro-ring chip constituting a wavelength-tunable optical filter which implements wavelength tuning by spectral tuning of the grid filter and/or the silicon-based micro-ring chip. A micro-ring filter in the silicon-based micro-ring chip of the tunable external-cavity laser is manufactured by adopting a mature silicon light technology, which can greatly reduce a manufacturing difficulty of the adjustable filter, and reduce the manufacturing cost of a device.
Accelink Technologies Co., Ltd.

Heat-dissipating semiconductor assembly

The invention provides a heat-dissipating semiconductor assembly, comprising: a heat-dissipating substrate, a metal solder layer, and an edge emitting laser diode. The heat-dissipating substrate has one side formed with a flat surface for mounting the edge emitting laser diode.
Luxnet Corporation

Semiconductor laser device, photoelectric converter, and optical information processing unit

A semiconductor laser device that enables flip-chip assembly by having an embedding section around a mesa section, and that has an improved emission lifetime, as well as a photoelectric converter and an optical information processing unit each having such a semiconductor laser device. The semiconductor laser device includes: a mesa section including an active layer, and having a first electrode on a top surface; an embedding section covering the mesa section, and having a first connection aperture that reaches the first electrode; and a first wiring provided on the embedding section overlaying the first connection aperture, the first wiring being electrically connected to the first electrode through the first connection aperture..
Sony Corporation

Millimeter wave fabric network over dielectric waveguides

Radio frequency (rf) data transfer between components in rack mounted systems is facilitated through the use of dielectric waveguides and millimeter wave (mm-wave) transceivers. A signal generator provides one or more data signals to a serializer/deserializer (serdes) which serializes a plurality of parallel data signals to produce a single, serialized, signal containing data from each of the input signals to the serdes.
Intel Corporation

Frequency dependent light emitting devices

An electroluminescent device described herein, in one aspect, comprises a first electrode and second electrode and a light emitting layer positioned between the first and second electrodes. A current injection gate is positioned between the first electrode and the light emitting layer or the second electrode and the light emitting layer.
Wake Forest University

Organic electronic/optoelectronic devices

An electronic or optoelectronic device including a semiconductor layer, wherein the semiconductor layer comprises at least a semiconductive organic material, water species, and at least one additive in an amount of at least 0.1% by weight relative to the semiconductive organic material, which additive at least partly negates a charge carrier trapping effect caused by the water species on the semiconductive organic material.. .
Cambridge Enterprise Limited

Organic semiconductor compositions

The present invention relates to organic copolymers and organic semiconducting compositions comprising these materials, including layers and devices comprising such organic semiconductor compositions. The invention is also concerned with methods of preparing such organic semiconductor compositions and layers and uses thereof.
Smartkem Limited

Method for producing vapor deposition mask, vapor deposition mask preparation body, producing organic semiconductor element, producing organic el display, and vapor deposition mask

A vapor deposition mask preparation body in which a metal mask is provided on one surface of a resin plate for obtaining a resin mask, and a protective sheet with peel strength not less than about 0.0004 n/10 mm and less than about 0.2 n/10 mm in conformity with jis z-0237:2009 is provided on the other surface of the resin plate is prepared, with respect to the vapor deposition mask preparation body, the resin plate is irradiated with laser light from the metal mask side to form a resin mask opening corresponding to a pattern to be produced by vapor deposition in the resin plate, and the protective sheet is peeled off from the resin mask in which the resin mask opening corresponding to the pattern to be produced by vapor deposition is formed.. .
Dai Nippon Printing Co., Ltd.

Resistive random access memory device having nano-scale tip and nanowire, memory array using the same and fabrication method thereof

A resistive random access memory device having a nano-scale tip and a nanowire is provided. A memory array using the same also is provided and fabrication method thereof.
Incheon University Industry Academic Cooperation Foundation

Thermoelectric module

Provided is a thermoelectric module including electrodes and p-type and n-type semiconductors formed on a substrate by a printing method. The thermoelectric module includes upper and lower substrates (110 and 120) formed of ceramic or aluminum and forming upper and lower surfaces of the thermoelectric module; electrodes (130) disposed on surfaces of the upper and lower substrates (110 and 120), the electrodes being formed of an electrically conductive material for transmitting electric power; a plurality of p-type and n-type semiconductors (140 and 150) spaced between the electrodes (130), the p-type and n-type semiconductors (140 and 150) being forming by sintering a paste mixture of thermoelectric powder and an organic solvent, wherein the electrodes (130) and the p-type and n-type semiconductors (140 and 150) are formed by a printing method.
Korea Institute Of Machinery & Materials

Silicone-organic resin composite laminate and manufacturing method thereof, and light-emitting semiconductor apparatus using the same

The invention provides a silicone-organic resin composite laminate comprising a laminate in which an organic resin layer containing an inorganic fiber cloth into which a thermosetting organic resin has been impregnated, and a silicone resin layer containing an inorganic fiber cloth into which a curable silicone resin has been impregnated, being laminated with each one or more layers, and metal foils laminated at an uppermost surface and a lowermost surface of the laminate. There can be provided a silicone-organic resin composite laminate which has low linear expansion, good thermal dimensional stability, excellent mechanical characteristics, and excellent heat resistance and light resistance, and is suitable as a mounting substrate for an led which corresponds to increase in luminance of the led mounted substrate..
Shin-etsu Chemical Co., Ltd.

Photon extraction from ultraviolet light-emitting devices

In various embodiments, a layer of organic encapsulant is provided over a surface of an ultraviolet (uv) light-emitting semiconductor die, and at least a portion of the encapsulant is exposed to uv light to convert at least some of said portion of the encapsulant into non-stoichiometric silica material. The non-stoichiometric silica material includes silicon, oxygen, and carbon, and a carbon content of the non-stoichiometric silica material is greater than 1 ppm and less than 40 atomic percent..

Nitride semiconductor wafer, manufacturing method thereof, nitride semiconductor ultraviolet light-emitting element, and nitride semiconductor ultraviolet light-emitting device

To prevent degradation of electrical characteristics caused by a resin filled between electrodes in an ultraviolet light-emitting operation, there is provided a nitride semiconductor wafer having ultraviolet light-emitting elements on a substrate 12, each element including a semiconductor laminated portion 21 constituted by an n-type algan layer 16, an active layer 17 composed of an algan layer, and p-type algan layers 19 and 20, an n-electrode 23, a p-electrode 22, a protective insulating film 24, first and second plated electrodes 25 and 26, and a fluororesin film 27. The p-electrode is formed on an upper surface of the p-type algan layer in the first region r1 and the n-electrode is formed on an upper surface of the n-type algan layer in the second region r2.
Asahi Glass Company, Limited

Multistep deposition of zinc oxide on gallium nitride

A method for fabricating a zinc oxide (zno) conductive film on a semiconductor material, including depositing a doped zno seed layer on a diode, wherein the zno seed layer forms an electrical contact to the diode; and depositing a zno layer on the zno seed layer, wherein the zno seed layer and the zno layer each have a thickness, a crystal quality, and a doping level such that (1) the diode comprising iii-nitride material is turned on with a turn on voltage of 2.75 volts or less applied across the zno layers and the diode, and (2) a contact resistance, of a structure comprising the zno layers and the diode, is lower as compared to a contact resistance of a structure comprising the zno layer directly on the diode without the zno seed layer.. .
The Regents Of The University Of California

Method for producing an optoelectronic semiconductor device and optoelectronic semiconductor device

A method for producing an optoelectronic semiconductor device and an optoelectronic semiconductor device are disclosed. In an embodiment the method includes providing a semiconductor layer sequence including a light-emitting and/or light-absorbing active zone and a top face downstream of the active zone in a stack direction extending perpendicular to a main plane of extension of the semiconductor layer sequence, applying a layer stack onto the top face, wherein the layer stack includes an oxide layer containing indium, and an intermediate face downstream of the top face in the stack direction and applying a contact layer onto the intermediate face, wherein the contact layer includes indium tin oxide, and wherein the layer stack is, within the bounds of manufacturing tolerances, free of tin..
Osram Opto Semiconductors Gmbh

Electrode and photoelectric semiconductor device using the same

An electrode and a photoelectric semiconductor device using the same are provided. The electrode includes a pad layer, a barrier layer and a reflection layer, which are formed in order.
Lextar Electronics Corporation

Light-emitting element comprising a plurality of wavelength converters, and production method therefor

Disclosed are a light-emitting element and a production method therefor. In one aspect, a light-emitting element is provided to comprise a light-emitting structure comprising a first and second semiconductor layers and an active layer; a first and second contact electrodes respectively making ohmic contact with the first and second semiconductor layers; an insulating layer for insulating the first contact electrode and second contact electrode; a first and second bulk electrodes respectively electrically linked to the first and second contact electrodes; an insulating support covering the side surfaces of the first and second bulk electrodes; a first wavelength converter covering the light-emitting structure; a light-transmitting layer positioned on the first wavelength converter; and a second wavelength converter positioned on the light-transmitting layer, and, in the present invention, white light emitted from the light-emitting element has a ciex value of at least 0.390 on the cie colour coordinate chart..
Seoul Viosys Co., Ltd.

Light-emitting device

A light-emitting device according to the present invention comprises: a light-emitting structure comprising a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; a second electrode layer coupled to the second conductive semiconductor layer at the bottom of the light-emitting structure; and a plurality of first electrode layers coupled to the first conductive semiconductor layer through penetration of the light-emitting structure at preset intervals.. .
Lg Innotek Co., Ltd.

Light emitting device and light emitting module

A light emitting device disclosed in an embodiment includes: a light emitting chip including a plurality of semiconductor layers and first and second electrodes under the plurality of semiconductor layers; a first lead frame disposed under a first electrode of the light emitting chip; a second lead frame disposed under a second electrode of the light emitting chip; a protective chip disposed between the first and second lead frames and electrically connected to the first and second electrodes; and a reflective member disposed on a periphery of the light emitting chip and the first and second lead frames.. .
Lg Innotek Co., Ltd.

Light emitting device and light emitting module (as amended)

A light emitting device disclosed in an embodiment includes: a light emitting chip including a light emitting part, including a plurality of semiconductor layers, and a first electrode and a second electrode under the light emitting part; a first support member under the light emitting chip; a second support member under the first support member; a first lead electrode connected to the first electrode and a second lead electrode connected to the second electrode, in the second support member, the first lead electrode being separated from the second lead electrode; a protection chip disposed between the first and second lead electrodes; and a reflective member disposed on a periphery of the light emitting chip, wherein the first support member includes a ceramic material between the second support member and the light emitting chip.. .
Lg Innotek Co., Ltd.

Light-emitting device and light-emitting device package including the same

A light-emitting device according to an embodiment of the present invention includes a substrate; a light-emitting structure provided on the substrate, and including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer provided between the first conductive type semiconductor layer and the second conductive type semiconductor layer; a first electrode provided on the light-emitting structure; a first connecting electrode provided on the first electrode; a second electrode provided on the light-emitting structure; a second connecting electrode provided on the second electrode; and a support layer provided around the first electrode, the first connecting electrode, the second electrode and the second connecting electrode. The support layer includes a first support layer having a first coefficient of thermal expansion, and a second support layer provided on the first support layer and having a second coefficient of thermal expansion..
Lg Innotek Co., Ltd.

Semiconductor optical device

A semiconductor optical device has a multilayer structure 30 including a first compound semiconductor layer 31, an active layer 33, and a second compound semiconductor layer 32. A second electrode 42 is formed on the second compound semiconductor layer 32 through a contact layer 34.
Sony Corporation

Light emitting diode

A light emitting diode is provided to comprises: a substrate that has an elongated rectangular shape in one direction; a light emitting structure positioned on the substrate and having an opening for exposing a first conductive semiconductor layer; a first electrode pad disposed to be closer to a first corner of the substrate; a second electrode pad disposed to be relatively closer to a second corner of the substrate opposing to the first corner; a first extension extending from the first electrode pad; and a second extension and a third extension extending from the second electrode pad to sides of the first extension, wherein an imaginary line connecting an end of the second extension and an end of the third extension is located between the first electrode pad and the first corner.. .
Seoul Viosys Co., Ltd.

Semiconductor light-emitting device

A semiconductor light-emitting device includes a first conductive semiconductor layer on a substrate, a superlattice layer including a plurality of first quantum barrier layers and a plurality of first quantum well layers, the plurality of first quantum barrier layers and the plurality of first quantum well layers being alternately stacked on the first conductive semiconductor layer, an active layer on the superlattice layer, and a second conductive semiconductor layer on the active layer, wherein a si doping concentration of at least one of the plurality of first quantum well layers is equal to or greater than 1.0×1016/cm3 and less than or equal to 1.0×1018/cm3. Thus, the semiconductor light-emitting device may have increased light output and reliability..
Samsung Electronics Co., Ltd.

Solid state lighting devices with dielectric insulation and methods of manufacturing

Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials.
Micron Technology, Inc.

Optical isolation systems and circuits and photon detectors with extended lateral p-n junctions

Disclosed examples include lateral photovoltaic sensors and systems with one or more semiconductor structures individually including a lateral sensor face to receive photons of a given wavelength, and an extended lateral junction region having an effective junction distance greater than 5 times an absorption depth for the semiconductor structure that corresponds to the given wavelength, to facilitate high current transfer ratios for use in low-noise, high-efficiency power supply applications as well as optically isolated data transfer or photon detector applications.. .
Texas Instruments Incorporated

Multijunction metamorphic solar cell for space applications

A multijunction solar cell assembly and its method of manufacture including first and second discrete semiconductor body subassemblies, each semiconductor body subassembly including first, second and third lattice matched subcells; a graded interlayer adjacent to the third solar subcell and functioning as a lateral conduction layer; and a fourth solar subcell adjacent to said graded interlayer being lattice mismatched with respect to the third solar subcell; wherein the average band gap of all four cells is greater than 1.44 ev.. .
Solaero Technologies Corp.

Group-iv solar cell structure using group-iv or iii-v heterostructures

Device structures, apparatuses, and methods are disclosed for photovoltaic cells that may be a single-junction or multijunction solar cells, with at least a first layer comprising a group-iv semiconductor in which part of the cell comprises a second layer comprising a iii-v semiconductor or group-iv semiconductor having a different composition than the group-iv semiconductor of the first layer, such that a heterostructure is formed between the first and second layers.. .
The Boeing Company

Group-iv solar cell structure using group-iv or iii-v heterostructures

Device structures, apparatuses, and methods are disclosed for photovoltaic cells that may be a single-junction or multijunction solar cells, with at least a first layer comprising a group-iv semiconductor in which part of the cell comprises a second layer comprising a iii-v semiconductor or group-iv semiconductor having a different composition than the group-iv semiconductor of the first layer, such that a heterostructure is formed between the first and second layers.. .
The Boeing Company

Solar cell having a plurality of sub-cells coupled by cell level interconnection

Methods of fabricating solar cells having a plurality of sub-cells coupled by cell level interconnection, and the resulting solar cells, are described herein. In an example, a solar cell includes a plurality of sub-cells.
Sunpower Corporation

Compound-based solar cell and manufacturing light absorption layer

A compound-based solar cell including a first electrode, a second electrode, a first type doped semiconductor layer and a second type doped semiconductor layer is provided. The first type doped semiconductor layer is disposed between the first electrode and the second electrode, and the second type doped semiconductor layer is disposed between the first type doped semiconductor layer and the second electrode.
Industrial Technology Research Institute

Radiation detector having pixelated anode strip-electrodes

A radiation detection system is provided. The radiation detection system includes a radiation detector.
General Electric Company

Photovoltaic device

In a photovoltaic device (1), first amorphous semiconductor portions (102n) and second amorphous semiconductor portions (102p) are provided alternately on one of faces of a semiconductor substrate (101). Each first amorphous semiconductor portion (102n) has at least one first amorphous semiconductor strip (1020n), and each second amorphous semiconductor portion (102p) has at least one second amorphous semiconductor strip (1020p).
Sharp Kabushiki Kaisha

Photoelectric conversion element

A photoelectric conversion element includes a composite passivation film disposed on a second surface of a semiconductor substrate that is opposite to a first surface on which light is incident. The composite passivation film includes a first passivation film having negative fixed charges and a protection film that protects the first passivation film.
Sharp Kabushiki Kaisha

Metallization structures for solar cells

Methods of fabricating a solar cell including metallization techniques and resulting solar cells, are described. In an example, forming a first semiconductor region and a second semiconductor region on the back side of a substrate.
Sunpower Corporation

High voltage pin diode

A pin diode is formed on an insulating structure on a substrate of semiconductor. The insulating structure is disposed on a high voltage doped region in the substrate.
Nuvoton Technology Corporation

Semiconductor device and manufacturing the semiconductor device

An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and manufacturing method thereof

A semiconductor device including a field effect transistor (fet) device includes a substrate and a channel structure formed of a two-dimensional (2d) material. An interfacial layer is formed on the channel structure.
Taiwan Semiconductor Manufacturing Co., Ltd.

Display apparatus and manufacturing the same

A display apparatus includes a thin film transistor on a first base substrate, the thin film transistor including a gate electrode disposed on the first base substrate, an active pattern disposed on the first base substrate and including a semiconductor layer including of amorphous silicon and an ohmic contact layer which is on the semiconductor layer, a drain electrode disposed on the ohmic contact layer and having a first thickness, and a source electrode disposed on the ohmic contact layer and having a second thickness which is greater than the first thickness.. .
Samsung Display Co., Ltd.

Semiconductor device having channel regions

A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.. .
Samsung Electronics Co., Ltd.

Semiconductor device

Provided is a highly integrated semiconductor device, a semiconductor device with large storage capacity with respect to an area occupied by a capacitor, a semiconductor device capable of high-speed writing, a semiconductor device capable of high-speed reading, a semiconductor device with low power consumption, or a highly reliable semiconductor device. The semiconductor device includes a first transistor, a second transistor, and a capacitor.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device, manufacturing the same, and electronic device

A semiconductor device in which parasitic capacitance is reduced is provided. A first insulating layer is deposited over a substrate.
Semiconductor Energy Laboratory Co., Ltd.

Manufacturing semiconductor device

A miniaturized transistor with less variation and highly stable electrical characteristics is provided. Further, high performance and high reliability of a semiconductor device including the transistor are achieved.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and manufacturing method thereof

The semiconductor device includes a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers. The first conductive layer and the second conductive layer are connected to the oxide semiconductor layer.
Semiconductor Energy Laboratory Co., Ltd.

Thin film transistor, manufacturing the same, and organic light emitting display device including the same

Disclosed are a thin film transistor, a method of manufacturing the same, and an organic light emitting display device including the same, in which a driving stability of a driving transistor is enhanced even without connecting a source electrode to a bottom gate electrode of the driving transistor. The film transistor includes a n-type semiconductor layer, a p-type semiconductor layer on the n-type semiconductor layer, a first gate electrode on the p-type semiconductor layer, a gate insulation layer between the first gate electrode and the p-type semiconductor layer, a first source electrode connected to a first side of the p-type semiconductor layer, and a first drain electrode connected to a second side of the p-type semiconductor layer..
Lg Display Co., Ltd.

Semiconductor device and manufacturing semiconductor device

A manufacturing method of a semiconductor device includes forming an amorphous silicon film on an insulation surface, forming a silicon oxide film using an oxidation treatment from the amorphous silicon film, forming an oxide semiconductor layer above the silicon oxide film, forming a gate insulating film above the oxide semiconductor layer, and forming a gate electrode interposed by the gate insulating film above the oxide semiconductor layer.. .
Japan Display Inc.

Thin film transistor substrate and display device

Disclosed is a thin film transistor substrate that may include a base substrate, a first protection film disposed on the base substrate, an oxide semiconductor layer disposed on the first protection film, a gate electrode insulated from the oxide semiconductor layer and partially overlapped with at least one portion of the oxide semiconductor layer, a source electrode connected with the oxide semiconductor layer, and a drain electrode provided at a predetermined interval from the source electrode and connected with the oxide semiconductor layer, wherein the oxide semiconductor layer has a hydrogen content of 2.4 at % (atomic % or atom %)˜2.6 at %.. .
Hangyang University Industry-university Cooperation Foundation

Semiconductor device

A semiconductor device is provided which includes a first fin-type pattern including a first side surface and a second side surface opposite to each other, a first trench of a first depth adjacent to the first side surface, a second trench of a second depth adjacent to the second side surface. The second depth differs from the first depth, and a first field insulating film partially fills the first trench and a second field insulating film partially fills the second trench.
Samsung Electronics Co., Ltd.

Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions

A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region with a gate insulating film therebetween; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.. .
Sony Corporation

Metal oxide semiconductor device having recess and manufacturing method thereof

The present invention provides a mos (metal-oxide-silicon) device and a manufacturing method thereof. The mos device includes: a semiconductor substrate, a gate, a source, a drain, and two ldds (lightly-doped-drains).
Richtek Technology Corporation

Semiconductor devices with gate-controlled energy filtering

The present disclosure relates to semiconductor devices with gate-controlled energy filtering. One example embodiment includes a semiconductor device.
Universiteit Antwerpen

Method and structure to provide integrated long channel vertical finfet device

A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical finfet device independent of the fin height.
Globalfoundries Inc.

High-voltage semiconductor device

A high-voltage semiconductor device is disclosed. The high-voltage semiconductor device includes a gate structure on a substrate structure.
Nuvoton Technology Corporation

High voltage p-type lateral double-diffused metal oxide semiconductor field effect transistor

A high voltage p-type lateral double-diffused metal oxide semiconductor field effect transistor (10) comprises: a substrate (100); an n-type lateral double-diffused metal oxide semiconductor field effect transistor (200) formed on the substrate (100); and a p-type metal oxide semiconductor field effect transistor (300) formed at a drain of the n-type lateral double-diffused metal oxide semiconductor field effect transistor (200); wherein a gate of the p-type metal oxide semiconductor field effect transistor (300) serves as a gate of the high voltage p-type lateral double-diffused metal oxide semiconductor field effect transistor (10); a drain of the p-type metal oxide semiconductor field effect transistor (300) serves as a drain of the high voltage p-type lateral double-diffused metal oxide semiconductor field effect transistor (10); a source of the n-type lateral double-diffused metal oxide semiconductor field effect transistor (200) serves as a source of the high voltage p-type lateral double-diffused metal oxide semiconductor field effect transistor (10).. .
Csmc Technologies Fab1 Co., Ltd.

Laterally diffused metal oxide semiconductor with gate poly contact within source window

An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe.
Texas Instruments Incorporated

Semiconductor device with extended electrically-safe operating area

In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type.
Texas Instruments Incorporated

3d semiconductor device and structure

A 3d semiconductor device, the device including: a first layer including first transistors each including a silicon channel; a second layer including second transistors each including a silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer underlying the first transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistor is a junction-less transistor.. .
Monolithic 3d Inc.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device and a fabricating the same

A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ild) layer formed over the electronic device, a wiring pattern formed on the ild layer and a contact formed in the ild layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ild layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

High-voltage metal-oxide-semiconductor transistor capable of preventing occurrence of exceedingly-large reverse current

An embodiment of the invention shows a high-voltage mos field-effect transistor connected in series with a schottky diode. When the schottky diode is forwardly biased, the high-voltage mosfet can act as a switch and sustain a high drain-to-source voltage.
Leadtrend Technology Corporation

Semiconductor devices with raised doped crystalline structures

Semiconductor devices including an elevated or raised doped crystalline structure extending from a device layer are described. In embodiments, iii-n transistors include raised crystalline n+ doped source/drain structures on either side of a gate stack.
Intel Corporation

Semiconductor device and manufacturing same

To achieve a semiconductor device equipped with a low on voltage and high load short circuit withstand trench gate igbt. A collector region on a back surface of a semiconductor substrate is comprised of a relatively lightly-doped p+ type first collector region and a relatively heavily-doped p++ type second collector region.
Renesas Electronics Corporation

Semiconductor device with multiple hbts having different emitter ballast resistances

The present disclosure relates to a semiconductor device with multiple heterojunction bipolar transistors (hbts) that have different emitter ballast resistances. The disclosed semiconductor device includes a substrate, a first hbt and a second hbt formed over the substrate.
Qorvo Us, Inc.

Electronic device including a tunnel layer

An electronic device includes a semiconductor layer, a tunneling layer formed of a material including a two-dimensional (2d) material so as to directly contact a certain region of the semiconductor layer, and a metal layer formed on the tunneling layer.. .
Samsung Electronics Co., Ltd.

Devices having a semiconductor material that is semimetal in bulk and methods of forming the same

Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region.
Taiwan Semiconductor Manufacturing Company, Ltd.

Oxide thin film transistor, manufacturing the same, and display panel and display device including the oxide thin film transistor

Disclosed are an oxide thin film transistor (tft), a method of manufacturing the same, a display panel including the oxide tft, and a display device including the display panel, in which a crystalline oxide semiconductor is provided on a metal insulation layer including metal through a metal organic chemical vapor deposition (mocvd) process. The oxide tft includes a metal insulation layer including metal, a crystalline oxide semiconductor adjacent to the metal insulation layer, a gate including metal, a gate insulation layer between the crystalline oxide semiconductor and the gate, a first conductor in one end of the crystalline oxide semiconductor, and a second conductor in another end of the crystalline oxide semiconductor..
Lg Display Co., Ltd.

Transistor structure with varied gate cross-sectional area

Aspects of the present disclosure include finfet structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin..
Globalfoundries Inc.

Methods for forming semiconductors by diffusion

In some embodiments, a compound semiconductor is formed by diffusion of semiconductor species from a source semiconductor layer into semiconductor material in a substrate. The source semiconductor layer may be an amorphous or polycrystalline structure, and provides a source of semiconductor species for later diffusion into the other semiconductor material.
Asm Ip Holding B.v.

Method of forming semiconductor structure and resulting structure

The disclosure is directed to a semiconductor structure and method of forming same. The method including: implanting a species within a region of a substrate adjacent to a gate stack; forming a first spacer laterally adjacent to the gate stack over the substrate; and forming an opening within the implanted region of the substrate, the opening being substantially u-shaped and self-aligned with the first spacer.
Globalfoundries Inc.

Transient voltage suppression devices with symmetric breakdown characteristics

The present disclosure relates to a symmetrical, punch-through transient voltage suppression (tvs) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer.
General Electric Company

Nitride semiconductor device and manufacturing the same

A nitride semiconductor device includes: an electron transit layer including gaxin1-xn (0<x≤1); an electron supply layer formed on the electron transit layer and including alyin1-yn (0<y≤1); a gate insulating film formed to pass through the electron supply layer to contact the electron transit layer; and a gate electrode facing the electron transit layer with the gate insulating film interposed therebetween, wherein, in the electron transit layer, a portion contacting the gate insulating film and a portion contacting the electron transit layer are flush with each other.. .
Rohm Co., Ltd.

Devices with strained source/drain structures and forming the same

A device includes a substrate and a gate structure over the substrate. The device further includes source/drain (s/d) features in the substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device and manufacturing method therefor

The present invention discloses a manufacturing method for a semiconductor device. The manufacturing method includes: providing a substrate; forming a semiconductor stacked structure on the substrate; forming at least apart of a stacked cap layer on the semiconductor stacked structure, wherein the part of the stacked cap layer includes a nitride layer; removing a part of the nitride layer; forming the rest part of the stacked cap layer; forming a protection layer on the stacked cap layer, and etching the protection layer to form an opening, wherein the nitride layer is not exposed by the opening; and introducing an etchant material into the opening to etch the substrate.
Pixart Imaging Incorporation

Semiconductor device having asymmetric spacer structures

A semiconductor device including a semiconductor substrate, agate on the semiconductor substrate, a drain doping region in the semiconductor substrate on a first side of the gate, a source doping region in the semiconductor substrate on a second side of the gate, a first spacer structure on a first sidewall of the gate between the gate and the drain doping region, and a second spacer structure on a second sidewall of the gate between the gate and the source doping region. The first spacer structure is composed of a low-k dielectric layer on the first sidewall of the gate and a first spacer material layer on the low-k dielectric layer.
United Microelectronics Corp.

Shared metal gate stack with tunable work function

Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack that includes a bottom layer, a middle layer, and a top layer is formed over the at least one semiconductor fin in the first region.
International Business Machines Corporation

Semiconductor device and formation

A semiconductor device and method of formation are provided. The semiconductor device includes a channel surrounding a dielectric tube and a gate surrounding the channel.
National Taiwan University

Gate cut device fabrication with extended height gates

Semiconductor devices and methods of forming the same include forming a dummy gate structure across multiple device regions that includes a dummy gate and a dummy gate hardmask. A lower dielectric layer is formed to a height below a height of the dummy gate hardmask.
International Business Machines Corporation

Semiconductor device and manufacturing the same

A semiconductor device includes an active region in a shape of a fin extending in a first direction, the fin having source/drain regions spaced apart therein, gate structures crossing the fin between the source/drain regions, each including a gate electrode, a first contact structure in electrical contact with a first source/drain region, the first contact structure including a first lower contact and a first upper contact directly thereon, a second contact structure in electrical contact with a gate electrode of a gate structure, the second contact structure including a second lower contact and a second upper contact directly thereon, and a third contact structure in electrical contact with a gate electrode of a second gate structure and in electrical contact with a second source drain region, the third contact structure including a third lower contact and a third upper contact directly thereon.. .
Samsung Electronics Co., Ltd.

Semiconductor device and fabrication method

The position of the side wall of a metal electrode is precisely controlled and the coverage of a layer above the metal electrode is improved. A semiconductor device is provided, including: a semiconductor substrate; and a metal electrode formed above an upper surface of the semiconductor substrate, wherein a side wall of the metal electrode includes a lower portion contacting the semiconductor substrate, and an upper portion that is formed upper than the lower portion and has a smaller inclination relative to the upper surface of the semiconductor substrate than the lower portion.
Fuji Electric Co., Ltd.

Semiconductor chip package with cavity

Various embodiments disclosed relate to a semiconductor package. The semiconductor package includes a substrate having first and second opposed major surfaces.

Method for fabricating semiconductor substrate, semiconductor substrate, and semiconductor device

In a method for fabricating a semiconductor substrate according to an embodiment, an sic substrate is formed by vapor growth and c (carbon) is introduced into the surface of the sic substrate to form an n-type sic layer on the sic substrate by an epitaxial growth method.. .
Kabushiki Kaisha Toshiba

Metal oxide semiconductor device having mitigated threshold voltage roll-off and threshold voltage roll-off mitigation method thereof

The present invention provides a mos (metal-oxide-silicon) device having mitigated threshold voltage roll-off and a threshold voltage roll-off mitigation method therefor. The mos device includes: a substrate, a well region, an isolation region, a gate, two ldds (lightly-doped-drains), a source, a drain and a compensation doped region.
Richtek Technology Corporation

Semiconductor devices

A semiconductor device includes a device isolation layer on a substrate, a first active pattern defined by the device isolation layer, and source/drain regions. The first active pattern extends in a first direction and includes a channel region between a pair of recesses formed at an upper portion of the first active pattern.
Samsung Electronics Co., Ltd.

Semiconductor structure and manufacturing method thereof

The present invention provides a semiconductor structure, the semiconductor structure includes a substrate, at least one active area is defined on the substrate, a buried word line is disposed in the substrate, a source/drain region disposed beside the buried word line, a diffusion barrier region, disposed at the top of the source/drain region, the diffusion barrier region comprises a plurality of doping atoms selected from the group consisting of carbon atoms, nitrogen atoms, germanium atoms, oxygen atoms, helium atoms and xenon atoms, a dielectric layer disposed on the substrate, and a contact structure disposed in the dielectric layer, and electrically connected to the source/drain region.. .
Fujian Jinhua Integrated Circuit Co., Ltd.

High density memory cell structures

The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor.
Globalfoundries Inc.

Vertical gate-all-around transistor with top and bottom source/drain epitaxy on a replacement nanowire, and manufacturing the same

After providing a group iv semiconductor nanowire on a substrate, a sacrificial material portion is formed on sidewalls of a bottom portion of the group iv semiconductor nanowire. A sacrificial gate layer is then formed over the sacrificial material portion to laterally surround a middle portion of the group iv semiconductor nanowire, followed by forming a sacrificial spacer on sidewalls of a remaining top portion of the group iv semiconductor nanowire.
International Business Machines Corporation

Strain retention semiconductor member for channel sige layer of pfet

A pfet includes a semiconductor-on-insulator (soi) substrate; and a trench isolation within the soi substrate, the trench isolation including a raised portion extending above an upper surface of the soi substrate. A compressive channel silicon germanium (csige) layer is over the soi substrate.
Globalfoundries Inc.

Semiconductor device

A semiconductor device is disclosed. The semiconductor device includes a substrate structure including a high side region, a low side region, a level shift region and an isolation region.
Nuvoton Technology Corporation

Semiconductor device

A semiconductor device including a substrate of a first conductivity type, a metal-oxide-semiconductor-field-effect transistor (mosfet), junction gate field-effect transistors (jfets), an isolation structure, and a buried layer of a second conductivity type is provided. The mosfet is located on the substrate and has a first epitaxial layer of the second conductivity type.
Nuvoton Technology Corporation

Semiconductor device

A semiconductor device including a substrate, a metal-oxide-semiconductor field-effect transistor (mosfet), and a plurality of junction gate field-effect transistors (jfets) connected in parallel is provided. The mosfet is disposed on a substrate.
Nuvoton Technology Corporation

High-voltage semiconductor device

High-voltage semiconductor devices are provided. The high-voltage semiconductor device includes a substrate having a first conductive type and a gate region disposed on the substrate.
Nuvoton Technology Corporation

Precise/designable finfet resistor structure

A resistive material is formed straddling over each semiconductor fin that extends upward from a surface of a substrate. The resistive material is then disconnected by removing the resistive material from atop each semiconductor fin.
International Business Machines Corporation

Semiconductor device and a fabricating the same

A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view..
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor resistor structure and making

Disclosed examples include a resistor comprising a semiconductor structure having a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends, first and second metal-semiconductor compound structures on the semiconductor structure proximate the first and second ends of the semiconductor structure, the first and second metal-semiconductor compound structures being spaced apart from each other along the length dimension of the semiconductor structure, and at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the semiconductor structure between the first and second ends, the intermediate metal-semiconductor compound structure being spaced apart from the first and second metal-semiconductor compound structures on the semiconductor structure.. .
Texas Instruments Incorporated

Method for fabricating a semiconductor device

A method for fabricating a semiconductor device includes the steps of: forming a channel layer on a substrate; forming a gate dielectric layer on the channel layer; forming a source layer and a drain layer adjacent two sides of the gate dielectric layer; forming a bottom gate on the gate dielectric layer; forming a phase change layer on the bottom gate; and forming a top gate on the phase change layer.. .
United Microelectronics Corp.

Semiconductor led display devices

The subject of this invention is a full-color display device based on iii-nitride semiconductors. The display device includes an array of micro-leds, monolithically integrated on a single chip of the epitaxially grown led heterostructure, and flip-chip bonded to a silicon backplane of active matrix driving circuits, and color conversion layers.

Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip

The invention relates to a method for producing an optoelectronic semiconductor chip (1). A semiconductor layer sequence (3) is provided, comprising a first semiconductor layer (3a) and a second semiconductor layer (3b).
Osram Opto Semiconductors Gmbh

Image sensors

An image sensor includes a separation impurity layer in a semiconductor layer and defining a photoelectric conversion region and a readout circuit region, a photoelectric conversion layer in the semiconductor layer of the photoelectric conversion region and surrounded by the separation impurity layer, a floating diffusion region spaced apart from the photoelectric conversion layer and in the semiconductor layer of the photoelectric conversion region, a transfer gate electrode between the photoelectric conversion layer and the floating diffusion region, and impurity regions in the semiconductor layer of the readout circuit region. When the photoelectric conversion layer is integrated with photo-charges, the separation impurity layer has a first potential level around the photoelectric conversion layer and a second potential level on a portion between the photoelectric conversion layer and the impurity regions of the readout circuit region.
Samsung Electronics Co., Ltd.

Image sensors

An image sensor includes a transfer gate including a gate buried portion extending into a semiconductor substrate from a surface of the semiconductor substrate, a plurality of photoelectric conversion parts that are disposed in the semiconductor substrate on a side of the gate buried portion and vertically overlap each other, and a plurality of floating diffusion parts that are apart from and vertically overlap each other in the semiconductor substrate on other side of the gate buried portion, wherein at least one of the floating diffusion parts is positioned at a height of at least one of corresponding photoelectric conversion parts.. .
Samsung Electronics Co., Ltd.

Solid-state imaging device

A solid-state imaging device according to the present disclosure includes: a charge storage region that stores a signal charge obtained through photoelectric conversion in a photoelectric conversion film; an amplification transistor that amplifies the signal charge stored in the charge storage region in a corresponding pixel; a contact plug that is electrically connected to the charge storage region and contains a semiconductor material; and a line that is disposed above the contact plug and contains a semiconductor material. The contact plug and the charge storage region are electrically connected, and the contact plug and a gate electrode of the amplification transistor are electrically connected via the line..
Panasonic Intellectual Property Management Co., Ltd.

Hybrid sensor chip assembly and reducing radiative transfer between a detector and read-out integrated circuit

Aspects and examples described herein provide a hybrid imaging sensor chip assembly for reducing undesired radiative transfer between a complementary metal-oxide semiconductor (cmos) read-out integrated circuit (roic) and an optical detector, and methods of manufacturing a hybrid imaging sensor chip assembly. In one example, a hybrid imaging sensor chip assembly includes an optical detector configured to collect electromagnetic radiation incident thereon, a complementary metal-oxide semiconductor (cmos) read-out integrated circuit (roic), and a radiation-shielding wafer interposed between the optical detector and the cmos roic, the radiation-shielding wafer including a plurality of through wafer vias (twvs) electrically coupled to the optical detector and the cmos roic, the radiation-shielding wafer being positioned to prevent radiative transfer between the cmos roic and the optical detector..
Raytheon Company

Methods and applications of non-planar imaging arrays

System, devices and methods are presented that provide an imaging array fabrication process method, comprising fabricating an array of semiconductor imaging elements, interconnecting the elements with stretchable interconnections, and transfer printing the array with a pre-strained elastomeric stamp to a secondary non-planar surface.. .
Mc10, Inc.

Imaging device and manufacturing imaging device

A first semiconductor chip includes a signal input transistor in which an input signal which is a signal corresponding to incident light is input to a control terminal, a reference input transistor which forms a differential pair along with the signal input transistor and in which a reference signal is input to a control terminal, a first signal line which delivers a change in a current flowing in one of the signal input transistor and the reference input transistor as a result of comparison between the input signal and the reference signal when the current is changed in accordance with a difference between the input signal and the reference signal, and a first pad which is electrically connected to the first signal line. A second semiconductor chip includes a processing circuit which processes the result of the comparison, a second signal line which is electrically connected to the processing circuit and delivers the result of the comparison to the processing circuit, and a second pad which is electrically connected to the second signal line and the first pad..

High-speed light sensing apparatus ii

An optical apparatus including a semiconductor substrate; a first light absorption region supported by the semiconductor substrate, the first light absorption region configured to absorb photons and to generate photo-carriers from the absorbed photons; one or more first switches controlled by a first control signal, the one or more first switches configured to collect at least a portion of the photo-carriers based on the first control signal; one or more second switches controlled by a second control signal, the one or more second switches configured to collect at least a portion of the photo-carriers based on the second control signal; and a counter-doped region formed in a first portion of the first light absorption region, the counter-doped region including a first dopant and having a first net carrier concentration lower than a second net carrier concentration of a second portion of the first light absorption region.. .
Artilux Corporation

Semiconductor device and electronic apparatus

Provided is a semiconductor device including: a multilayer substrate including an optical element; a light-transmitting plate provided on the substrate to cover the optical element; and a lens of an inorganic material provided between the substrate and the light-transmitting plate. A structure having a same strength as a strength per unit area of the lens is provided at a portion outside an effective photosensitive region where the optical element is formed, when the substrate is viewed in plan..
Sony Corporation

High-speed light sensing apparatus ii

An optical apparatus including a semiconductor substrate; a first light absorption region supported by the semiconductor substrate, the first light absorption region including germanium and configured to absorb photons and to generate photo-carriers from the absorbed photons; a first layer supported by at least a portion of the semiconductor substrate and the first light absorption region, the first layer being different from the first light absorption region; one or more first switches controlled by a first control signal, the one or more first switches configured to collect at least a portion of the photo-carriers based on the first control signal; and one or more second switches controlled by a second control signal, the one or more second switches configured to collect at least a portion of the photo-carriers based on the second control signal, wherein the second control signal is different from the first control signal.. .
Artilux Corporation

Image sensor

An image sensor of reduced chip size includes a semiconductor substrate having an active pixel region in which a plurality of active pixels are disposed and a power delivery region in which a pad is disposed. A plurality of first transparent electrode layers is disposed over the semiconductor substrate, respectively corresponding to the plurality of active pixels.
Samsung Electronics Co., Ltd.

Array of optoelectronic structures and fabrication thereof

A method of fabrication of an array of optoelectronic structures includes first providing a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells includes an opening to the substrate.
International Business Machines Corporation

Image sensor

An image sensor includes a semiconductor substrate having first and second surfaces facing each other and a first device isolation layer provided in the semiconductor substrate. The first device isolation layer defines pixel regions of the semiconductor substrate and includes first and second portions crossing each other.
Samsung Electronics Co., Ltd.

Cmos image sensor

A complementary metal-oxide semiconductor (cmos) image sensor includes a device isolation layer provided in a trench of a substrate, the device isolation layer defining a pixel; and a photoelectric conversion device provided in the pixel. The device isolation layer includes a conductive layer, a tunneling layer interposed between the conductive layer and the substrate, and a trap layer interposed between the tunneling layer and the conductive layer..
Samsung Electronics Co., Ltd.

Thin film transistor and manufacturing the same, and display device including the same

A thin film transistor and a method for manufacturing the same, and a display device including the same are disclosed, in which a p type semiconductor characteristic is realized using an active layer that includes a sn based oxide. The thin film transistor comprises an active layer that includes an sn(ii)o based oxide; a metal oxide layer being in contact with one surface of the active layer; a gate electrode overlapped with the active layer; a gate insulating film provided between the gate electrode and the active layer; a source electrode being in contact with a first side of the active layer; and a drain electrode being in contact with a second side of the active layer..
Lg Display Co., Ltd.

Thin film transistor, manufacturing the same, and semiconductor device

In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer.
Semiconductor Energy Laboratory Co., Ltd.

Thin film transistor substrate and manufacturing same

The present invention relates to a tft substrate, and a pixel includes a gate electrode selectively provided on a substrate, a gate insulating film covering the gate electrode, a semiconductor channel layer selectively provided on the gate insulating film, a protective insulating film provided on the semiconductor channel layer, a first interlayer insulating film provided on the substrate, a source electrode and a drain electrode that are separated from each other and directly in contact with the semiconductor channel layer via respective contact holes penetrating the first interlayer insulating film and the protective insulating film, and a pixel electrode extending from the drain electrode. A first light shielding film is provided on the protective insulating film to overlap with at least a channel region in plan view, and a second light shielding film is provided on the source electrode and the drain electrode to overlap with the semiconductor channel layer and the first light shielding film in plan view..
Mitsubishi Electric Corporation

Semiconductor device and semiconductor device production system

A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formulation region of a tft, thereby preventing grain boundaries from lowering the mobility of the tft greatly, from lowering on current, and from increasing off current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film.
Semiconductor Energy Laboratory Co., Ltd.

Asymmetric band gap junctions in narrow band gap mosfet

A semiconductor device with one or more fin structures formed from a first material, gate, source, and drain regions formed from a second material, and a contact insulator layer deposited over the substrate, where an etching process applied to the substrate removes the insulator to create a trench over the source region. The device also includes a lower band gap source material that is deposited into the trench, a second contact insulator layer, and a metalizing material that is deposited over the substrate.
International Business Machines Corporation

Standard cell having vertical transistors

The disclosed technology generally relates to semiconductor devices, and more particularly to a standard cell semiconductor device comprising transistors having vertical channels and a common gate. In one aspect, a standard cell semiconductor device comprises a substrate, a unit cell having a first transistor and a second transistor, a gate layer common to the first and second transistor, and a set of routing tracks for contacting the first and second transistor.
Vrije Universiteit Brussel

Semiconductor device and manufacturing the same

A method for manufacturing a semiconductor device includes forming a first semiconductor layer, forming a stacked body including alternately formed first and second layers on the first semiconductor layer, forming a hole from an upper surface of the stacked body to the first semiconductor layer to expose the first semiconductor layer therein. A first insulating layer is formed on the inner wall of the hole, and a second semiconductor layer is formed on the first insulating layer within the hole, wherein the second semiconductor layer is electrically connected to the first semiconductor layer.
Toshiba Memory Corporation

Select transistors with tight threshold voltage in 3d memory

Disclosed herein is a 3d memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate.
Sandisk Technologies Llc

Semiconductor devices and fabrication methods thereof

A semiconductor device includes a base substrate including an nmos region and a pmos region. The pmos region includes a first p-type region and a second p-type region.
Semiconductor Manufacturing International (beijing) Corporation

Method of forming semiconductor memory device

A method of forming semiconductor memory device including following steps. Firstly, a substrate having a memory cell region and a peripheral region is provided, and a first semiconductor layer is formed on the substrate within the periphery region.
Fujian Jinhua Integrated Circuit Co., Ltd.

Method for fabricating semiconductor device

A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first buried gate and a second buried gate in the substrate on the memory region; forming a first silicon layer on the substrate on the periphery region; forming a stacked layer on the first silicon layer; forming an epitaxial layer on the substrate between the first buried gate and the second buried gate; and forming a second silicon layer on the epitaxial layer on the memory region and the stacked layer on the periphery region.. .
Fujian Jinhua Integrated Circuit Co., Ltd.

Semiconductor storage device and manufacturing method thereof

A manufacturing method of a semiconductor storage device includes forming a plurality of bit line structures on a semiconductor substrate and forming a plurality of storage node contacts disposed between the bit line structures. The method of forming the storage node contacts includes forming a plurality of conductive patterns on the semiconductor substrate followed by performing an etching back process to the conductive patterns for decreasing a thickness of the conductive patterns.
Fujian Jinhua Integrated Circuit Co., Ltd.

Semiconductor device and fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; performing an ion implantation process to implant ions into the substrate underneath the trench; performing an in-situ steam generation (issg) process to form a gate dielectric layer in the trench; forming a gate electrode on the gate dielectric layer; and forming a doped region in the substrate adjacent to two sides of the gate electrode.. .
Fujian Jinhua Integrated Circuit Co., Ltd.

Method for fabricating semiconductor device

A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the substrate; performing a first ion implantation process to form a first doped region having a first conductive type in the substrate adjacent to the trench; forming a gate electrode in the trench; and performing a second ion implantation process to form a second doped region having a second conductive type in the substrate above the gate electrode.. .
Fujian Jinhua Integrated Circuit Co., Ltd.

Manufacturing semiconductor memory device

A manufacturing method of a semiconductor memory device is provided in the present invention. A cleaning treatment to a storage node contact on a semiconductor substrate is performed, and a metal silicide layer is formed after the cleaning treatment.
Fujian Jinhua Integrated Circuit Co., Ltd.

Method for forming semiconductor device

The present invention provides a method for fabricating a semiconductor device, comprising at least the steps of: providing a substrate in which a memory region and a peripheral region are defined, the memory region includes a plurality of memory cells, each memory cell includes at least a first transistor and a capacitor, the peripheral region compress a second transistor, a first insulating layer is formed within the memory region and the peripheral region by an atomic layer deposition process, covering the capacitor of the memory cells in the memory region and the second transistor in the peripheral region, and a second insulating layer is formed, overlying the first insulating layer and the peripheral region. Finally, a contact structure is formed within the second insulating layer, and electrically connecting the second transistor..
Fujian Jinhua Integrated Circuit Co., Ltd.

Capacitor structure and fabrication method thereof

A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad..
Fujian Jinhua Integrated Circuit Co., Ltd.

Method of manufacturing a semiconductor device

The present invention proposes a method of manufacturing a semiconductor device, which includes the steps of providing a substrate with a memory region and a logic region, forming bit lines and logic gates respectively in the memory region and the logic region, wherein storage node regions are defined between bit lines, forming a first low-k dielectric layer on sidewalls of bit lines, forming a doped silicon layer in the storage node regions between bit lines, wherein the top surface of doped silicon layer is lower than the top surface of bit line, forming a second low-k dielectric layer on sidewalls of storage node regions, and filling up storage node regions with metal plugs.. .
Fujian Jinhua Integrated Circuit Co., Ltd.

Semiconductor device and manufacturing method thereof

In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device and manufacturing method thereof

In in a method of manufacturing a semiconductor device, an interlayer dielectric (ild) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device and manufacturing method thereof

In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device and corresponding manufacturing method

A semiconductor device includes a semiconductor body having a first silicon carbide region and a second silicon carbide region which forms a pn-junction with the first silicon carbide region, a first metallization on a front side of the semiconductor body, a contact region that forms an ohmic contact with the second silicon carbide region, and a barrier-layer between the first metallization and the contact region and that is in ohmic connection with the first metallization and the contact region. The barrier-layer forms a schottky-junction with the first silicon carbide region, and includes molybdenum nitride or tantalum nitride.
Infineon Technologies Ag

Method of operating an igbt having switchable and non-switchable diode cells

A method of operating an igbt is described. The igbt has gate, emitter and collector terminals, and igbt cells, switchable diode cells, and non-switchable diode cells integrated in a semiconductor substrate, wherein each of the igbt cells and switchable diode cells includes an operable switchable channel region.
Infineon Technologies Ag

Semiconductor device with an igbt region and a non-switchable diode region

A semiconductor device includes a semiconductor substrate having a body layer arranged between a front side and a drift layer, and forming a pn-junction with the drift layer. A front metallization is on the front side in ohmic connection with the body layer, and a back metallization opposite is in ohmic connection with the drift layer.
Infineon Technologies Ag

High density capacitors formed from thin vertical semiconductor structures such as finfets

A vertical structure may be used as a high density capacitance for an integrated circuit. These thin vertical structures can be configured to operate as an insulator in a metal-insulator-metal (mim) capacitor.
Cirrus Logic, Inc.

Semiconductor carrier with vertical power fet module

A monolithic power management module provides a chip carrier with surfaces, ground traces, signal and power interconnects; a three dimensional fet formed on the chip carrier to modulate currents through the carrier or on the carrier surface; a toroidal inductor or transformer coil with a ceramic magnetic core formed on the chip carrier adjacent to the fet and having a first winding connected to the fet, and a plurality of passive ceramic components formed on the chip carrier surface.. .

Electronic device with integrated galvanic isolation, and manufacturing the same

A method of manufacturing an electronic device for providing galvanic isolation includes forming a dielectric layer on a semiconductor body and integrating, in the dielectric layer, a galvanic isolation module, the integrating including forming a first metal region at a first height of the dielectric layer. A second metal region is formed at a second height greater than the first height of the dielectric layer, the first and second metal regions being at least one of capacitively and magnetically coupleable together.
Stmicroelectronics S.r.l.

Silicon-controlled rectifiers having a cathode coupled by a contact with a diode trigger

Silicon-controlled rectifiers, electrostatic discharge circuits, and methods of fabricating a silicon-controlled rectifier for use in an electrostatic discharge circuit. A device structure for the silicon controlled rectifier includes a first well of a first conductivity type in a semiconductor layer, a second well of a second conductivity type in the semiconductor layer, a cathode coupled with the first well, and an anode coupled with the second well.
Globalfoundries Inc.

Transient overvoltage protection device

In one embodiment, an overvoltage protection device may include a semiconductor substrate comprising an n-type body region. The overvoltage protection device may further include a first p-type region disposed in a first surface region of the semiconductor substrate, and forming a first p/n junction with the n-type body region, and a second p-type region disposed in a second surface region of the semiconductor substrate opposite the first surface, and forming a second p/n junction with the n-type body region, wherein the n-type body region, first p-type region, and second p-type region form a breakdown device having a breakdown voltage greater than 100v when an external voltage is applied between the first surface region and second surface region..
Littelfuse, Inc.

Semiconductor device

A semiconductor device according to the present invention includes: a substrate; a plurality of trenches formed in the substrate; and a plurality of functional element forming regions arrayed along each of the trenches, including a channel forming region as a current path, wherein the plurality of functional element forming regions includes a first functional element forming region in which the area of the channel forming region per unit area is relatively small and a second functional element forming region in which the area of the channel forming region per unit area is relatively large, and the first functional element forming region is provided at a region where heat generation should be suppressed.. .
Rohm Co., Ltd.

Semiconductor device comprising a clamping structure

Semiconductor device is provided with a semiconductor body that includes a clamping structure including a first pn junction diode and a second pn junction diode serially connected back to back between a first contact and a second contact. A breakdown voltage of the first pn junction diode is greater than 100 v, and a breakdown voltage of the second pn junction diode is greater than 10 v..
Infineon Technologies Austria Ag

Semiconductor integrated circuit device

Disclosed herein is a semiconductor integrated circuit device which includes a standard cell with a plurality of fins extending in a first direction and arranged in a second direction that is perpendicular to the first direction. An active fin of the fins forms part of an active transistor.
Socionext Inc.

Power semiconductor module

A power semiconductor module including a positive-side switching device and a positive-side diode device which are mounted on a positive-side conductive pattern, and a negative-side switching device and a negative-side diode device which are mounted on an output-side conductive pattern. When an insulating substrate is viewed in plan view, the positive-side diode device and the negative-side diode device are disposed between the positive-side switching device and the negative-side switching device, and the negative-side diode device is disposed closer to the positive-side switching device than the positive-side diode device is..
Mitsubishi Electric Corporation

Configurable semiconductor package

Configurable semiconductor packages and processes to attain a defined configuration are provided. A configurable semiconductor package includes a base semiconductor package including a semiconductor die mounted on a surface of a package substrate.
Intel Ip Corporation

Laser lift-off on isolated iii-nitride light islands for inter-substrate led transfer

A laser liftoff process is provided. A device layer can be provided on a transfer substrate.
Glo Ab

Semiconductor package device and manufacturing the same

An electronic device comprises a carrier, an emitter, a detector, a separation wall and a light shielding layer. The emitter is disposed on a first portion of the top surface of the carrier.
Advanced Semiconductor Engineering, Inc.

Semiconductor device comprising pn junction diode and schottky barrier diode

A semiconductor device includes a mosfet including a pn junction diode. A unipolar device is connected in parallel to the mosfet and has two terminals.
Rohm Co., Ltd.

Package structure and manufacturing the same

The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided.
United Microelectronics Corp.

3-d stacking semiconductor assembly having heat dissipation characteristics

A semiconductor assembly having heat dissipation characteristics includes stacked semiconductor chips thermally conductible to a thermal pad of an interconnect substrate and electrically connected to the interconnect substrate through bonding wire. The bonding wires extending from a primary routing circuitry in between the stacked chips can accommodate the height difference between the stacked chips and the interconnect substrate.
Bridge Semiconductor Corporation

Semiconductor device including dual pad wire bond interconnection

A semiconductor device is disclosed including semiconductor die formed with a row of functional die bond pads and an adjacent row of dummy die bond pads. The functional die bond pads may be electrically connected to the integrated circuits formed within the semiconductor die.
Sandisk Semiconductor (shanghai) Co., Ltd.

3d semiconductor device and structure

A 3d semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; at least one connection from the plurality of first transistors to a plurality of through silicon vias (tsvs); a plurality of third transistors overlaying the plurality of second transistors, where the plurality of second transistors are self-aligned to the plurality of third transistors having been processed following the same lithography step; and a first memory array and a second memory array, where the first memory array includes the plurality of second transistors and the second memory array includes the plurality of third transistors.. .
Monolithic 3d Inc.

Semiconductor sensor package

A package packaged with a cap. The package features trenches, through holes, and a non-conductive coupling element forming a locking mechanism integrated embedded or integrated within a substrate.
Stmicroelectronics Pte Ltd

Wiring with external terminal

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a connection wiring of a ring-shape having comprising a hole and a conductive layer surrounding the hole, the conductive layer including a first connection point and a second connection point that are located so that a straight line between the first connection point and the second connection point crosses over the hole; an external terminal coupled to the first connection point of the conductive layer of the connection wiring; and an internal circuit coupled to the second connection point of the conductive layer of the connection wiring..
Micron Technology, Inc.

Semiconductor device and manufacturing semiconductor device

A semiconductor device includes an electrode having a flat part and a non-flat part made up of a concave part, a joint layer being made of a sintered body of metal crystal grains provided on the flat part and the non-flat part of the electrode, and a semiconductor element being joined to the electrode with the joint layer therebetween, wherein the joint layer has a first region sandwiched between the non-flat part and the semiconductor element and a second region sandwiched between the flat part and the semiconductor element, and either one of the first region and the second region having a larger film thickness has a filling rate of the metal crystal grains smaller than the other one of the first region and the second region having a smaller film thickness. The present invention enhances reliability of a joint layer made of a sintered body of metal crystal grains..
Mitsubishi Electric Corporation

Packaged semiconductor device with a reflow wall

A packaged semiconductor device includes a lead frame and a semiconductor device. A solder joint is coupled between the lead frame and a terminal on the semiconductor device.
Texas Instruments Incorporated

Semiconductor package and preparing the same

A semiconductor package includes a first device and a bump structure disposed over the first device. In some embodiments, the first device has a first upper surface and a first side, wherein the first upper surface and the first side form a first corner of the first device.
Nanya Technology Corporation

Semiconductor devices having metal posts for stress relief at flatness discontinuities

A semiconductor device includes a first body having a first coefficient of thermal expansion (cte) and a first surface, a third body having a third cte and a third surface facing the first surface, and a fourth surface at an angle with respect to the third surface defining an edge of the third body, and a second body having a second cte higher than the first and the third cte, the second body contacting the first and the third surfaces. A post having a fourth cte lower than the second cte, transects the second body and contacts the edge..
Texas Instruments Incorporated

Semiconductor device and manufacturing method therefor

An aluminum electrode (2) is provided on a semiconductor device (1). A metallic film (3) for a solder joint is provided on the aluminum electrode (2).
Mitsubishi Electric Corporation

Fan-out semiconductor package

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and the passivation layer has a modulus of elasticity greater than that of the insulating layer of the second interconnection member..
Samsung Electro-mechanics Co., Ltd.

Guard ring structure and forming the same

A method for forming a seal ring structure provides a semiconductor substrate having a first doping region formed over a top portion thereof. The method forms a plurality of patterned photoresist layers over the semiconductor substrate, encircling the semiconductor substrate, wherein each of the patterned photoresist layers has a plurality of parallel strip portions extending along a first direction and a plurality of bridge portions formed between the parallel strip portions, and then performs an etching process to a first doping region of the substrate.
Mediatek Singapore Pte. Ltd

Standoff members for semiconductor package

Semiconductor packages having support members are provided. Support members can mitigate damage to a semiconductor die mounted on a semiconductor package.
Intel Corporation

Conductive adhesive layer for semiconductor devices and packages

In various embodiments this disclosure is directed to conductive adhesives layers that can be used, in one example embodiment, to connect one or more shielding structures (for example, metal cans and/or covers) to a semiconductor package to enclose one or more electronic components on the semiconductor package. In another embodiment, the conductive adhesive layers disclosed herein can be used in connection with optoelectronic devices (for example, optoelectronic devices including laser diodes and/or avalanche photodiodes, apds).
Intel Corporation

Fan-out semiconductor package

A fan-out semiconductor package includes: a first semiconductor chip; a first encapsulant; a connection member including first vias and a first redistribution layer; a second semiconductor chip; a second encapsulant; a second redistribution layer; second vias; and third vias. A length of the longest side of a first cut surface of the second via is less than that of the longest side of a second cut surface of the third via, the first cut surface of the second via and the second cut surface of the third via being cut by a plane on any level parallel to the second active surface..
Samsung Electro-mechanics Co., Ltd.

Contacts for local connections

The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer..
Globalfoundries Inc.

Semiconductor device structures including stair step structures, and related semiconductor devices

A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps.
Micron Technology, Inc.

Semiconductor memory device and a manufacturing method thereof

A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly..
Fujian Jinhua Integrated Circuit Co., Ltd.

Semiconductor device including a porous dielectric layer, and forming the semiconductor device

A method of forming a semiconductor device, includes forming a conductive layer in a recessed portion of a porous dielectric layer, partially removing a top portion of the conductive layer while maintaining a height of the porous dielectric layer, forming a conformal cap layer on the porous dielectric layer and the conductive layer in the recessed portion, polishing the conformal cap layer to form a gap in the conformal cap layer, such that an upper surface of the porous dielectric layer is exposed through the gap and an upper surface of the conductive layer is protected by the cap layer, and performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer.. .
International Business Machines Corporation

Semiconductor package with embedded mim capacitor, and fabricating thereof

An interposer includes a first redistribution layer, an organic substrate, a capacitor, a hard mask layer, a conductive pillar, and a second redistribution layer. The organic substrate is on the first redistribution layer.
Micron Technology, Inc.

Semiconductor device and fabricating 3d package with short cycle time and high yield

A method of making a semiconductor device comprising the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (kgu), disposing a known good semiconductor die (kgd) over the first kgu of the first redistribution interconnect structure, and dicing the first kgu and kgd from the first redistribution interconnect structure.
Stats Chippac Pte. Ltd.

Fan-out package structure and method

A device comprises a semiconductor structure in a molding compound layer, a first polymer layer on the molding compound layer, a second polymer layer on the first polymer layer, a first interconnect structure having a first via portion in the first polymer layer and a first metal line portion in the second polymer layer, a third polymer layer on the second polymer layer, a fourth polymer layer on the third polymer layer and a second interconnect structure having a second via portion in the third polymer layer and a second metal line portion in the fourth polymer layer, wherein the second via portion is vertically aligned with the first via portion.. .
Taiwan Semiconductor Manufacturing Company, Ltd.

Packaged semiconductor device with a particle roughened surface

A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame.
Texas Instruments Incorporated

Modified leadframe design with adhesive overflow recesses

The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess.
Stmicroelectronics, Inc.

Leadframe with lead protruding from the package

The present disclosure is directed to a leadframe package having leads with protrusions on an underside of the leadframe. The protrusions come in various shapes and sizes.
Stmicroelectronics, Inc.

Method of manufacturing semiconductor products, corresponding semiconductor product and device

A method for use in manufacturing semiconductor devices such as, e.g., semiconductor power devices includes providing: a semiconductor die provided with bonding pads, a lead frame for the semiconductor die, a wire bonding layout including electrically conductive wires coupling bonding pads of the semiconductor die with leads in the lead frame. One or more bonding pads of the semiconductor die is/are coupled to a respective lead in the lead frame via a plurality of wires with a plurality of mutually insulated testing lands in the respective lead, so that the plurality of wires are coupled to respective testing lands.
Stmicroelectronics S.r.l.

Semiconductor device having through-silicon-via and methods of forming the same

Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material..
Micron Technology, Inc.

Semiconductor device and manufacturing semiconductor device

In a semiconductor device, a plurality of small depressions are formed to overlap each other in a first joining region of a back surface of a heat releasing plate. A streaky scratch or the like created on the back surface of the heat releasing plate is removed or reduced, by forming the small depressions overlapping each other on the heat releasing plate.
Fuji Electric Co., Ltd.

Ceramic metal circuit board and semiconductor device using the same

The present invention provides a ceramic metal circuit board including a ceramic substrate and metal plates bonded to both surfaces of the ceramic substrate through respective bonding layers, wherein a metal film is provided on a surface of one metal plate bonded to one surface of the ceramic substrate; and at least a part of another metal plate bonded to another surface of the ceramic substrate is not provided with the metal film. Preferably, a protruding portion is formed as a portion of the bonding layer so as to protrude from a side surface of each of the metal plates.
Toshiba Materials Co., Ltd.

Semiconductor device, corresponding apparatus and method

A semiconductor device, such as a semiconductor power device, includes: a semiconductor die having a semiconductor die front surface, a package formed onto the semiconductor die, the package having a portion facing the front surface of the semiconductor die, and a thermally-conductive layer including graphene over the front portion of the package facing the front surface of the semiconductor die.. .
Stmicroelectronics S.r.l.

Semiconductor device, corresponding circuit and method

A semiconductor device includes a layered package having a semiconductor die embedded therein, the semiconductor die coupled with a thermally-conductive element. The layered package includes, e.g., pcb boards with an intermediate layer having the semiconductor die arranged therein, and a pair of outer layers, with the thermally-conductive element including a thermally-conductive inlay in one of the outer layers..
Stmicroelectronics S.r.l.

Packaged semiconductor devices and methods of packaging semiconductor devices

Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device including an encapsulation material defining notches

A semiconductor device includes a first contact element, a second contact element, a semiconductor chip, and an encapsulation material. The first contact element is on a first side of the semiconductor device.
Infineon Technologies Ag

Semiconductor device, metal electrode member, and manufacturing the semiconductor device

On a conductive plate of an insulated substrate, one open end of a main body part of a cylindrical contact member is bonded by solder. In a hollow part of a hollow cylinder shaped external electrode terminal, a part of the other open end side of the main body part of the cylindrical contact member is inserted from an open end of the external electrode terminal.
Fuji Electric Co., Ltd.

Semiconductor device package and a manufacturing the same

A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel..
Advanced Semiconductor Engineering, Inc.

Semiconductor wafer and probe testing

A semiconductor test system has a wafer holder with a tape portion and one or more openings through the tape portion. A semiconductor wafer is mounted over the opening in the tape portion of the wafer holder with an electrical connection to the semiconductor wafer through the opening in the tape portion during probe test.
Semiconductor Components Industries, Llc

Semiconductor wafer with scribe line conductor and associated method

A semiconductor wafer is provided that includes at least two integrated circuits (ics); a scribe line extends adjacent to the at least two ics; and a first conductor extends within the scribe line and is electrically coupled to the at least two ics.. .

Method and a device for measuring gas dissociation degrees with an optical spectrometer

The present invention may be applied to any device and/or any apparatus that requires measuring of gas dissociation degrees, including but not limited to physical vapor deposition device, chemical vapor deposition device, etching device and any other relevant device in the semiconductor, photoelectric, panel industries and any other relevant industry. The present invention may also be directly disposed in a remote plasma source device.

Hybrid-channel nano-sheet fets

Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material.
International Business Machines Corporation

Semiconductor devices and methods of forming the same

Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates.
Samsung Electronics Co., Ltd.

Method for preparing substrate with carrier trapping center

The present disclosure provides a method for preparing a substrate with a carrier trapping center. The method includes: implanting bubbling ions into the semiconductor substrate to form a splitting layer, and implanting modified ions into the insulating layer to form a nano cluster; providing a supporting substrate; bonding the supporting substrate to the semiconductor substrate by using the insulating layer as an intermediate layer; performing a first heat treatment for the bonded substrate such that a splitting layer is formed at the position where the bubbling ions are implanted, and causing the semiconductor substrate to split at the position of the splitting layer; performing rapid thermal annealing for the substrate; and performing a second heat treatment for the rapidly thermally annealed semiconductor substrate to consolidate the bonding interface and form the nano cluster at the position where the modified ions are implanted..
Shanghai Simgui Tehcnology Co., Ltd.

Methods for removal of hard mask

Embodiments of a method of processing semiconductor devices are presented. The method includes providing a substrate prepared with isolation regions having a non-planar surface topology.
Globalfoundries Singapore Pte. Ltd.

Peeling method, semiconductor device, and peeling apparatus

To improve peelability, yield in a peeling step, and yield in manufacturing a flexible device. A peeling method is employed which includes a first step of forming a peeling layer containing tungsten over a support substrate; a second step of forming, over the peeling layer, a layer to be peeled formed of a stack including a first layer containing silicon oxynitride and a second layer containing silicon nitride in this order and forming an oxide layer containing tungsten oxide between the peeling layer and the layer to be peeled; a third step of forming a compound containing tungsten and nitrogen in the oxide layer by heat treatment; and a fourth step of peeling the peeling layer from the layer to be peeled at the oxide layer..
Semiconductor Energy Laboratory Co., Ltd.

Film for semiconductor back surface

Provided is a film for semiconductor protection, which can prevent warpage in a semiconductor wafer or a semiconductor chip and can also prevent the occurrence of chipping or ref low cracking. The film for semiconductor protection of the invention has a metal layer to be stuck to the back surface of a semiconductor chip, and an adhesive layer for adhering the metal layer to the back surface of the semiconductor chip, the surface free energy of the face of the adhesive layer on the side that is adhered to the semiconductor chip and the surface free energy of the face on the side that is adhered to the metal layer are together 35 mj/m2 or greater, and the peeling force between the adhesive layer in the b-stage state and the metal layer is 0.3 n/25 mm or higher..
Furukawa Electric Co., Ltd.

Semiconductor package structures including redistribution layers

A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip.
Micron Technology, Inc.

Bowing semiconductor wafers

Methods for processing semiconductor wafers, methods for loading semiconductor wafers into wafer carriers, and semiconductor wafer carriers. The methods and wafer carriers can be used for increasing the rigidity of wafers, e.g., large and thin wafers, by intentionally bowing the wafers to an extent that does not break the wafers.
Sunpower Corporation

Semiconductor wafer carriers

Semiconductor wafer carriers, methods for manufacturing the semiconductor wafer carriers, and methods for using the semiconductor wafer carriers. The semiconductor wafer carriers can include features for avoiding double-slotting, for preventing glove marks on semiconductor wafers, and for providing additional sitting and storage options for the wafer carrier.
Sunpower Corporation

Composite heat-dissipating substrate

The present invention provides a composite heat-dissipating substrate structure, comprising: a heat-dissipating substrate and a heat-conducting metal layer. The heat-dissipating substrate includes a substrate body and a socket formed on the substrate body; and the heat-conducting metal layer widely covers the socket of the substrate body and have one side formed as a loaded side on which a laser semiconductor is to be mounted and a opposite side formed as a heat-dissipating side, so that after the loaded side absorbs heat from the laser semiconductor, the heat-dissipating side reverse to the heat-conducting metal layer diffuses the heat to the heat-dissipating substrate..
Luxnet Corporation

Semiconductor packaging method, semiconductor package and stacked semiconductor packages

A semiconductor packaging method, a semiconductor package and stacked semiconductor packages are provided. The method includes providing a carrier (10) having a plurality of semiconductor chip receiving areas (12) and attaching a plurality of first semiconductor chips (14) to the semiconductor chip receiving areas (12).
Pep Innovation Pte Ltd.

Method for fabricating semiconductor device

A silicon oxide film having at least one opening portion is formed, on a silicon substrate. A structural member formed of a material less prone to be etched by hydrofluoric acid than a silicon oxide film is formed, wherein the structural member is provided on the silicon oxide film and reaches the silicon substrate in the opening portion.
Mitsubishi Electric Corporation

Semiconductor device and a fabricating the same

In a method of manufacturing a semiconductor device, an interlayer dielectric (ild) layer is formed over an underlying structure. The underlying structure includes gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate, source/drain epitaxial layers disposed between two adjacent gate structures, and an etching-stop layer (esl) covering the source/drain epitaxial layers.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor structure and fabrication method thereof

A semiconductor structure and a fabrication method are provided. The fabrication method includes forming a first dielectric layer on a base substrate, the first dielectric layer containing an opening exposing a surface portion of the base substrate; forming an initial gate dielectric layer on the surface portion of the base substrate and on a sidewall surface of the opening in the first dielectric layer; forming a gate dielectric layer by removing a portion of the initial gate dielectric layer from the sidewall surface of the opening, such that a top surface of the gate dielectric layer on the sidewall surface is lower than a top surface of the first dielectric layer; forming a gate electrode on the gate dielectric layer to fill the opening, a portion of the gate electrode being formed on a portion of the sidewall surface of the first dielectric layer; and forming a second dielectric layer on the gate electrode and on the first dielectric layer..
Semiconductor Manufacturing International (beijing) Corporation

Method of manufacturing semiconductor device, substrate processing apparatus, recording medium, and supply system

A method of manufacturing a semiconductor device, includes: forming a film on a substrate by performing a cycle a predetermined number of times, the cycle including: supplying two or more kinds of halogen-based precursors having the same major elements and different halogen elements, or different major elements and the same halogen elements, or different major elements and different halogen elements to the substrate while overlapping at least portions of supply periods of the two or more kinds of halogen-based precursors; and supplying a reactant having a chemical structure different from chemical structures of the two or more kinds of halogen-based precursors to the substrate.. .
Hitachi Kokusai Electric Inc.

Organic thin film transistor and manufacturing organic thin film transistor

An object is to provide an organic thin film transistor in which a high mobility can be obtained and a method for manufacturing an organic thin film transistor. The object is achieved by providing a base material, a gate electrode, a gate insulating layer, an organic semiconductor layer, a source electrode, and a drain electrode, further providing charge injection layers which are provided between the source electrode and a layer on a base material side of the source electrode and between the drain electrode and a layer on a base material side of the drain electrode and have a thickness that decreases in a direction opposite to a direction in which the source electrode and the drain electrode face each other on a side of the source electrode facing the drain electrode and a side of the drain electrode facing the source electrode, and scanning a metal layer with a laser so as to form the source electrode and the drain electrode, and dropwise-adding a solution which becomes the charge injection layers to a laser-scanned portion..
Fujifilm Corporation

Gate electrodes with notches and methods for forming the same

A device includes a semiconductor substrate, and a device isolation (di) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the di region.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor devices and methods for manufacturing the same

A method for manufacturing a semiconductor device includes forming a first well region in a semiconductor substrate, forming isolation structures on the semiconductor substrate, and forming second well regions and a third well region in the first well region, wherein the second well regions are isolated from the third well region by the isolation structures, and two of the adjacent second well regions have a first distance between them. The method also includes performing a rapid thermal annealing process to shorten the first distance to a second distance.
Vanguard International Semiconductor Corporation

Point-of-use enrichment of gas mixtures for semiconductor structure fabrication and systems for providing point-of-use enrichment of gas mixtures

Point-of-use enrichment of gas mixtures for semiconductor structure fabrication, and systems for providing point-of-use enrichment of gas mixtures, are described herein. In an example, a system for fabricating a semiconductor structure includes a process chamber for processing a substrate of a semiconductor structure.
Sunpower Corporation

Fin patterns with varying spacing without fin cut

Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of a plurality of mandrels using a directional deposition process. A finless region is masked by forming a mask on a second sidewall of one or more of the plurality of mandrels.
International Business Machines Corporation

Semiconductor device and semiconductor device manufacturing method

If a sio2 film is formed on a semiconductor substrate using teos (tetraethylorthosilicate: si(oc2h5)4), carbon (c) may be mixed in the sio2 film in some cases. In a sio2 film, carbon may function as fixed charges.
Fuji Electric Co., Ltd.

Semiconductor structure having insulator pillars and semiconductor material on substrate

One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars..
Globalfoundries Inc.

Showerhead having a detachable high resistivity gas distribution plate

Embodiments of showerheads having a detachable gas distribution plate are provided herein. In some embodiments, a showerhead for use in a semiconductor processing chamber may include a body having a first side and a second side opposing the first side; a gas distribution plate disposed proximate the second side of the body, wherein the gas distribution plate is formed from a material having an electrical resistivity between about 60 ohm-cm to 90 ohm-cm; a clamp disposed about a peripheral edge of the gas distribution plate to removably couple the gas distribution plate to the body; and a thermal gasket disposed in a gap between the body and gas distribution plate..
Applied Materials, Inc.

Dye sensitized solar cell module and dye sensitized solar cell comprising the same

The present invention relates to a dye-sensitized solar cell module, and more particularly, to a dye-sensitized solar cell module capable of minimizing a burst phenomenon of the dye-sensitized solar cell module caused by the bubbles by preventing occurrence of bubbles in an electrolyte solution, and securing reliability by preventing separation of a dye adsorbed onto a oxide semiconductor, and a dye-sensitized solar cell including the same.. .
Dongjin Semichem Co., Ltd.

Working electrode of dye-sensitized solar cell

The present invention relates to a dye-sensitized solar cell electrode, and more particularly, to a dye-sensitized solar cell electrode capable of enhancing a bond between a dye and an oxide semiconductor to secure reliability and efficiency of a dye-sensitized solar cell.. .
Dongjin Semichem Co., Ltd.

Composition for a layer of a power cable and such cable

The invention relates to a method for manufacturing a cable, including, from the inside to the outside, a central electrical conductor (1), a first semiconductor screen (2), an intermediate electric insulator (3), a second semiconductor screen (4), a metal screen (5) and an outer sheath (6), the method comprising a step of extruding a composition comprising at least one polyolefin for forming at least one layer constituting the first semiconductor screen, the intermediate electric insulator or second semiconductor screen and a step of cross-linking said layer. According to the invention, the method comprises the step of injecting, into the composition, a liquid solution containing at least one peroxide and at least one so-called cross-linking coagent, during the manufacture of said layer.
Silec Cable

Semiconductor memory device and operating method thereof

A semiconductor memory device may include a memory core unit including a plurality of memory cells suitable for storing data, an error correction code (ecc) control unit suitable for detecting an error of the data to output a flag signal corresponding to a result of detection of the error, and an address control unit suitable for adjusting a refresh interval of at least one memory cell that stores data in which the error is detected, or repairing the memory cell among the memory cells, in response to the flag signal.. .
Sk Hynix Inc.

Semiconductor memory device capable of reducing chip size

According to one embodiment, a first well of the first conductivity type which is formed in a substrate. A second well of a second conductivity type which is formed in the first well.
Toshiba Memory Corporation

Semiconductor memory device and operating the same

There may be provided a semiconductor memory device including a memory cell array, an erase count storage unit, and a control logic. The memory cell array may include a plurality of memory blocks.
Sk Hynix Inc.

Semiconductor memory device and operating the same

Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a plurality of pages each including a plurality of memory cells, peripheral circuits configured to perform a program operation of a selected page among the plurality of pages and a control logic configured to control the peripheral circuits such that a main program operation is performed on the selected page and, when the main program operation is completed, a compensation program operation is performed on memory cells having lower threshold voltage retention characteristics compared to remaining memory cells, among the memory cells included in the selected page..
Sk Hynix Inc.

Semiconductor memory device and operating method thereof

A semiconductor memory device including a memory cell array including a plurality of memory blocks, a voltage generator applying operation voltages to a selected memory block, among the plurality of memory blocks, a control logic generating converted data by converting data bit sets respectively corresponding to at least one set of program states among a plurality of program states, during a program operation, and a read and write circuit temporarily storing the converted data and performing a program operation by controlling potential levels of bit lines of the memory cell array in accordance with stored converted data.. .
Sk Hynix Inc.

Semiconductor device, operating method thereof and memory system

A method for operating a semiconductor device includes activating a first selection line coupled to a selected first memory string and deactivating a second selection line coupled to an unselected second memory string, applying a read voltage to a selected word line and a pass voltage to an unselected word line, and equalizing the selected word line and the unselected word line, wherein the second selection line is turned on during the equalizing of the selected and unselected word lines.. .
Sk Hynix Inc.

Semiconductor storage device and memory system

According to an embodiment, a control circuitry performing: a first operation of reading data out of a memory cell with a first voltage applied to a word line while changing the first voltage by a first shift amount within a first range, and a second operation of reading data out of the memory cell with a second voltage applied to the word line while changing the second voltage by a second shift amount within a second range, wherein the second shift amount is smaller than the first shift amount, and wherein the control circuitry performs the second operation to apply the second voltage to the word line subsequently to application of the first voltage to the word line in the first operation.. .
Toshiba Memory Corporation

Ferroelectric-modulated schottky non-volatile memory

Ferroelectric-modulated schottky non-volatile memory is disclosed. A resistive memory element is provided that is based on a semiconductive material.
Qualcomm Incorporated

Scan driver and display device including the same

A scan driver, includes a plurality of stage circuits, each of which includes a driving circuit unit providing an output signal and an inverter inverting the output signal of the driving circuit unit and generating a scan signal, in which the inverter includes a first transistor and a second transistor, which are complementarily operated, the first transistor is a p-type polysilicon transistor, and the second transistor is an n-type oxide semiconductor transistor. A display device may include the scan driver..
Samsung Display Co., Ltd

Secure boot sequencer and secure boot device

A boot secure device that performs a secure booting operation of a semiconductor system includes an external memory interface that provides an interface with an external memory, a first internal memory that stores a boot image stored in the external memory, a second internal memory that stores a hash of a first public key, a secure accelerator that verifies the boot image using the hash of the first public key, and a secure boot sequencer that includes a plurality of states and a plurality of operation and that controls the external memory interface, the first internal memory, the second internal memory, and the secure accelerator using at least one of the plurality of operations when a state transition occurs between two of the plurality of states.. .
Samsung Electronics Co., Ltd.

Secure device state apparatus and method and lifecycle management

A semiconductor chip device include device state fuses that may be used to configure various device states and corresponding security levels for the semiconductor chip as it transitions from wafer manufacturing to provisioned device. The device states and security levels prevent the semiconductor chip from being accessed and exploited, for example, during manufacturing testing.
Google Inc.

Integrated circuit and designing layout of integrated circuit

A method of designing a layout of an integrated circuit (ic) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern.
Samsung Electronics Co., Ltd.

Interconnect circuits at three-dimensional (3-d) bonding interfaces of a processor array

Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One embodiment comprises multiple semiconductor dies and at least one interconnect circuit for exchanging signals between the dies.
International Business Machines Corporation

Memory channel that supports near memory and far memory access

A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel.
Intel Corporation

Semiconductor system including heterogeneous memory module

A semiconductor system includes a cpu connected to a heterogeneous memory module via a system bus. The heterogeneous memory module includes; a volatile memory module, a nonvolatile memory module, an internal bus separate from the system bus and connecting the volatile memory module and the nonvolatile memory module, and a swap manager configured to control execution of a swap operation transferring target data between the volatile memory module and nonvolatile memory module using the internal bus and without using of the system bus..
Industry-academic Cooperation Foundation, Yonsei University

Memory apparatus, memory module and semiconductor system capable of dynamic mirroring

A semiconductor system may include a host, a memory controller and a memory apparatus. The host may generate a mirror request when a program requiring a mirroring operation is executed.
Sk Hynix Inc.

Semiconductor device

A semiconductor device includes a delay selection signal generation circuit, an internal read signal generation circuit, and an internal write signal generation circuit. The delay selection signal generation circuit generates a delay selection signal in response to an information code signal.
Sk Hynix Inc.

Semiconductor device and operating same

A processor includes; a processor core, a register selectively controlled by either external hardware during a first operation mode or the processor core during a second operation mode, and a selection circuit receiving first data provided by the external hardware to the register during the first operation mode and second data provided by the processor core to the register during the second operation mode.. .
Samsung Electronics Co., Ltd.

Semiconductor integrated circuit cards and communication systems including the same

A semiconductor integrated card includes an external package, a subscriber identification module (sim) circuit, a plurality of sim pins, a storage device and a plurality of memory pins. The sim circuit is formed inside of the external package and is configured to store subscriber information.
Samsung Electronics Co., Ltd.

Memory system and controlling memory system

According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode.
Toshiba Memory Corporation

Control logic, semiconductor memory device, and operating method

Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.. .
Sk Hynix Inc.

Semiconductor chip and electronic apparatus including the same

A semiconductor chip includes a hardware performance monitor (hpm) unit and an hpm controller. The hpm unit is driven during an initial operation period, a first operation period, and a second operation period, outputs initial hpm data, first hpm data, and second hpm data in the initial operation period, the first operation period, and the second operation period, respectively.
Samsung Electronics Co., Ltd.

Apparatus for controlling flow and calibrating same

Apparatuses for controlling gas flow are important components for delivering process gases for semiconductor fabrication. In one embodiment, a method of calibrating an apparatus for controlling gas flow is disclosed.
Reno Technologies, Inc.

Pattern-formation methods

Pattern-formation methods comprise: (a) providing a substrate; (b) forming a photoresist pattern over the substrate; (c) applying a pattern treatment composition to the photoresist pattern, the pattern treatment composition comprising a solvent mixture comprising a first organic solvent and a second organic solvent, wherein the first organic solvent has a boiling point that is greater than a boiling point of the second organic solvent, and wherein the first organic solvent has a boiling point of 210° c. Or more; and (d) thereafter heating the photoresist pattern.
Rohm And Haas Electronic Materials Llc

Manufacturing fringe field switching array substrate

A manufacturing method of a fringe field switching (ffs) array substrate is provided. The method has steps of: forming gate electrodes and common electrodes on a glass substrate, wherein the gate electrodes are formed on a portion of the common electrodes; forming semiconductor active layer precursors and pixel electrode precursors; and executing an ion implantation process for two ends of each of the semiconductor active layer precursors which are uncovered by a photoresist layer, so as to transform they into transparent conductors; and finally forming source electrodes and drain electrodes..
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Color conversion panel and display device including the same

A color conversion display panel includes a first color conversion layer and a second color conversion layer disposed on a color conversion substrate and including semiconductor nanocrystals, and a transmission layer, wherein a first distance between the first and second color conversion layers is different from a second distance between one of the first and second color conversion layers and the transmission layer.. .
Samsung Display Co., Ltd.

Method of laser irradiation, laser irradiation apparatus, and manufacturing a semiconductor device

If an optical path length of an optical system is reduced and a length of a laser light on an irradiation surface is increased, there occurs curvature of field which is a phenomenon that a convergent position deviates depending on an incident angle or incident position of a laser light with respect to a lens. To avoid this phenomenon, an optical element having a negative power such as a concave lens or a concave cylindrical lens is inserted to regulate the optical path length of the laser light and a convergent position is made coincident with a irradiation surface to form an image on the irradiation surface..
Semiconductor Energy Laboratory Co., Ltd.

Optical communication module configured for enhancing optical coupling efficiency

An optical communication module configured for enhancing optical coupling efficiency, which includes an optical butt joint receptacle and a light emitting body provided on one side of the optical butt joint receptacle. The optical butt joint receptacle has a receptacle body and a through hole provided in the receptacle body for a dual-core optical fiber to extend through.
Luxnet Corporation

Optical communication module configured for enhancing optical coupling efficiency

An optical communication module configured for enhancing optical coupling efficiency, which includes an optical butt joint receptacle and a light emitting body provided on one side of the optical butt joint receptacle. The optical butt joint receptacle has a receptacle body and a through hole provided in the receptacle body for a dual-core optical fiber to extend through.
Luxnet Corporation

Semiconductor optical waveguide. manufacturing the same, and optical communication device using the same

The present invention includes: a substrate; a semiconductor optical waveguide structure arranged on the substrate; a planar region formed around the semiconductor optical waveguide structure on the substrate; and a semiconductor dummy structure that is arranged around the planar region on the substrate and is formed of a plurality of dummy patterns, wherein the semiconductor optical waveguide structure includes a line-symmetric pattern on a plane that is parallel to the substrate; and the plurality of dummy patterns are arranged symmetrically with respect to the symmetry axis of the line-symmetric pattern.. .

Compositions, optical component, system including an optical component, devices, and other products

A composition useful for altering the wavelength of visible or invisible light is disclosed. The composition comprising a solid host material and quantum confined semiconductor nanoparticles, wherein the nanoparticles are included in the composition in amount in the range from about 0.001 to about 15 weight percent based on the weight of the host material.
Samsung Electronics Co., Ltd.

Ray detector

A ray detector is disclosed, which includes a ray conversion layer for converting a ray incident on the ray detector into visible light, a photoelectric conversion layer for receiving the visible light and converting it into a charge signal, a pixel array having a plurality of pixels for detecting the charge signal, and a substrate below the photoelectric conversion layer, at least for directly or indirectly carrying the photoelectric conversion layer. The photoelectric conversion layer is made from a two-dimensional semiconductor material.
Boe Technology Group Co., Ltd.

High-speed light sensing apparatus ii

An optical apparatus including a semiconductor substrate; a first light absorption region supported by the semiconductor substrate, the first light absorption region configured to absorb photons and to generate photo-carriers from the absorbed photons; one or more first switches controlled by a first control signal, the one or more first switches configured to collect at least a portion of the photo-carriers based on the first control signal; and one or more second switches controlled by a second control signal, the one or more second switches configured to collect at least a portion of the photo-carriers based on the second control signal. The one or more first switches include a first trench located between the first p-doped region and the first n-doped region.
Artilux Corporation

High precision optical characterization of carrier transport properties in semiconductors

A precise optical technique for measuring electronic transport properties in semiconductors is disclosed. Using tightly focused laser beams in a photo-modulated reflectance system, the modulated reflectance signal is measured as a function of the longitudinal (z) displacement of the sample from focus.

Device with stress controlling structure and testing

An optoelectronic device with at least one stress controlling structure and method of testing the device is disclosed. The optoelectronic device includes a stress controlling structure formed adjacent to a semiconductor heterostructure.
Sensor Electronic Technology, Inc.

Method of testing semiconductor devices and system for testing semiconductor devices

Provided are a method of testing semiconductor device and a system for testing semiconductor device. The method includes measuring a minimum operating voltage of each of a plurality of sample semiconductor devices and an operating frequency of corresponding ring oscillators included in each of the plurality of sample semiconductor devices, generating a model between the operating frequencies of the ring oscillators and the minimum operating voltages of the sample semiconductor devices, measuring an operating frequency of ring oscillators included in a target semiconductor device, and determining a target minimum operating voltage of the target semiconductor device based on the operating frequency of the ring oscillators of the target semiconductor device and the model..
Samsung Electronics Co., Ltd.

System and determining if deterioration occurs in interface of semiconductor die of electric power module

The present invention concerns a system for determining if a deterioration occurs in an interface of a semiconductor die of an electric power module, the electric power module further comprising a substrate and at least one electromechanical transductor, the semiconductor die and the at least one electromechanical transductor being placed on or embedded within the substrate, wherein the system comprises: —means for transferring at least one electric signal to the at least one electromechanical transductor, —means for measuring the impedance of the at least one electromechanical transductor, —means for comparing the impedance of the at least one electromechanical transductor to a predetermined value, —means for deciding that the deterioration occurs in the interface of the semi-conductor die according to the comparison result.. .
Mitsubishi Electric Corporation

Moisture detecting use in an igbt or a mosfet

A moisture detecting system has a power semiconductor module having a gate driver with the gate in which the gate driver has an on condition and an off condition, a power supply connected to the gate driver so as to supply voltage to the gate driver, a controller cooperative between the power supply and the gate driver so as to set the gate driver between the on condition and the off condition, and a sensor connected to the gate driver so as to detect a leakage of current across the gate driver. The controller is cooperative at the power supply so as to turn off the power supply when the signal is indicative of the leakage of current.

Semiconductor structure and reviewing defects

A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.. .
United Microelectronics Corp.

Integrated electronic device for detecting ultraviolet radiation

An integrated electronic device for detecting the composition of ultraviolet radiation includes a cathode region formed by a semiconductor material with a first type of conductivity. A first anode region and a second anode region are laterally staggered with respect to one another and are set in contact with the cathode region.
Stmicroelectronics S.r.l.

Lighting device for a vehicle, combining two light sources

The lighting device for a vehicle has two light sources and a wavelength conversion device excited by the combination of the radiations from the two light sources. A first light source is associated with a scanning system projecting, by scanning, a first light radiation onto a first conversion region of the device, while a second light source with semiconductors emits a second light radiation into a second conversion region of the device.
Valeo Vision

Micropump with electrostatic actuation

A micropump includes: a pumping chamber, between a first semiconductor substrate and a second semiconductor substrate bonded to each other; an inlet valve, having an inlet shutter element between an inlet passage and the pumping chamber; an outlet valve, having an outlet shutter element between the pumping chamber and an outlet passage; a first recess for housing the inlet shutter element when the inlet valve is in the open configuration, the first recess and the pumping chamber being fluidly coupled; a second recess for housing the outlet shutter element when the outlet valve is in the open configuration, the second recess and the pumping chamber being fluidly decoupled.. .
Politecnico Di Milano

Substrate processing apparatus, and manufacturing semiconductor device

Provided is a technique capable of purging a adiabatic region without adversely affecting a processing region. A process chamber including a processing region for processing a substrate and a adiabatic region located below the processing region is included inside.
Hitachi Kokusai Electric Inc.

Semiconductor nanoparticle, dispersion liquid, film, and producing semiconductor nanoparticle

An object of the present invention is to provide a semiconductor nanoparticle having high emission efficiency and excellent durability; a method of producing the same; and a dispersion liquid and a film obtained by using a semiconductor nanoparticle. The semiconductor nanoparticle of the present invention is a semiconductor nanoparticle in which oxygen, zinc, and sulfur are detected by x-ray photoelectron spectroscopy analysis and a peak (ich3) which is derived from a hydrocarbon group and present in a range of 2800 cm−1 to 3000 cm−1 and a peak (icoo) which is derived from coo− and present in a range of 1400 cm−1 to 1600 cm−1 are detected by fourier transform infrared spectroscopy analysis..
Fujifilm Corporation

Near-ir emitting cationic silver chalcogenide quantum dots

A novel near-ir emitting cationic silver chalcogenide quantum dot with a mixed coating wherein the coating comprises of at least 2 different types of materials and is capable of luminescence at the desired near ir bandwidth at wavelengths of 800-850 nm. The quantum dot is fabricated via an advantageous single-step, homogeneous, aqueous method at a low temperature resulting a near ir emitting semiconductor quantum dot with high quantum yield, high transfection with low toxicity.
KoÇ Üniversitesi

Ligands for semiconductor nanocrysals

In this invention, polyimidazole ligands (pils) incorporating pendant imidazole moieties for nanocrystal binding and either sulfonatebetaine, carboxybetaine, or phosphocholinebetaine moieties for water-solubilization have been developed. Greatly enhanced stability of nanocrystals (both over time and in wide ph range) was achieved by incorporating multi-dentate imidazole moieties which provide strong coordination of the ligand to the nanocrystal surface and prevent aggregation of nanocrystals.
Massachusetts Institute Of Technology

Heat-curable resin composition for semiconductor encapsulation

(d) a spherical inorganic filler.. .

Complementary metal oxide semiconductor (cmos) ultrasonic transducers and methods for forming the same

Complementary metal oxide semiconductor (cmos) ultrasonic transducers (cuts) and methods for forming cuts are described. The cuts may include monolithically integrated ultrasonic transducers and integrated circuits for operating in connection with the transducers.
Butterfly Network, Inc.

Fet based sensory systems

This invention describes the structure and function of an integrated multi-sensing system. Integrated systems described herein may be configured to form a microphone, pressure sensor, gas sensor, multi-axis gyroscope or accelerometer.

Method of producing semiconductor chip, and mask-integrated surface protective tape used therein

(d) an ashing step of removing the mask material layer by the plasma irradiation.. .

Flexible complementary metal-oxide-semiconductor probes for chronic, large-scale neural stimulation and recording

Systems and methods for providing neural stimulation and recording on a subject using flexible complementary cmos probes are provided. Disclosed systems can include a flexible probe adapted for insertion into a portion of a brain of the subject, the flexible probe comprising a tail portion and a head portion.
The Trustees Of Columbia University In The City Of New York

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. .

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Gallium nitride semiconductor device with improved termination scheme

This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein..
Sunglory Beheer B.v.

Renesas Electronics Corporation

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Mitsubishi Electric Corporation

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Renesas Electronics Corporation

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Renesas Electronics Corporation

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Image processor and semiconductor device

An object of the present invention is to detect a failure of a camera input in a system including a camera or a video transmission path (camera input). An image processor includes a hash derivation circuit having a computing unit that calculates hash values on an input screen and a storage circuit that stores the hash values.
Renesas Electronics Corporation

Solid-state imaging device, imaging system and movable object

A solid-state imaging device includes a plurality of pixels, each of the plurality of pixels including a photoelectric converter. The photoelectric converter includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided under the first semiconductor region, and a third semiconductor region of the first conductivity type provided under the second semiconductor region.
Canon Kabushiki Kaisha

Imaging element, driving method, and electronic device

A pixel is included, the pixel including a photoelectric conversion portion configured to convert incident light to a charge by photoelectric conversion and accumulate the charge, a charge transfer unit configured to transfer the charge generated in the photoelectric conversion portion, a diffusion layer to which the charge is transferred through the charge transfer unit, the diffusion layer having a predetermined storage capacitance, a conversion unit configured to convert the charge transferred to the diffusion layer to a pixel signal, and connection wiring configured to connect the diffusion layer and the conversion unit. The connection wiring is connected to the diffusion layer and the conversion unit through contact wiring extending in a vertical direction with respect to a semiconductor substrate on which the diffusion layer is formed and is formed closer to the semiconductor substrate than other wiring provided in the pixel..
Sony Semiconductor Solutions Corporation

Extended dynamic range cis pixel achieving ultra-low noise

An extended range compatible metal oxide semiconductor image sensor and method for operating it is provided, the sensor comprising: a first conversion node; a first switch connected to said first conversion node; a second switch disposed in series with said first switch; and a capacitive element disposed between said first and said second switches.. .
Bae Systems Information And Electronic Systems Integration Inc.

Receiving circuit, and semiconductor device and system configured to use the receiving circuit

A receiving circuit may include a decision feedback equalizer circuit and buffer. The buffer may be configured to receive an external signal and to generate an input signal.
Sk Hynix Inc.

Efficiently managing multiple power supplies

An apparatus comprises multiple power supply switches each including a respective power metal oxide semiconductor field effect transistor (mosfet) to receive a respective one of multiple power voltages ranked incrementally from a lowest priority to a highest priority, and multiple control modules each coupled to, and configured to control, a respective one of the power mosfets, each control module to receive all of the power voltages having higher priorities than the power voltage received at the respective power mosfet controlled by that control module, each control module to control the respective power mosfet so as to turn off the respective power mosfet if any of the higher priority power voltages are present, or permit the respective power mosfet to turn on responsive to the respective power voltage if all of the higher priority power voltages are absent.. .
Cisco Technology, Inc.

Semiconductor device and power converter

A semiconductor device has a configuration in which a plurality of transistors are equivalently coupled in parallel by including a plurality of control electrodes for controlling a current flowing between a first main electrode and a second main electrode. A resistance value of a transmission path of a control signal from a common control terminal varies with respect to each of the control electrodes..

Semiconductor apparatus and inverter system

The present disclosure attempts to improve performance of a semiconductor apparatus including a power transistor such as an igbt. In a semiconductor apparatus, an igbt module 110 includes igbt elements swa and swb connected in parallel to each other, a resistor r1a connected to a gate terminal of the igbt element swa, and a diode d1a connected in parallel to the resistor r1a.
Renesas Electronics Corporation

Semiconductor device and dc-dc converter

According to an embodiment, a semiconductor device includes: a first modulation circuit configured to generate a reference signal based on a first clock signal; a second modulation circuit configured to generate a feedback signal with a phase negative relative to a phase of the reference signal based on a second clock signal with a phase negative relative to a phase of the first clock signal; a comparator configured to compare the reference signal with the feedback signal to determine duty and generate a comparator signal; and a driver configured to output a drive signal.. .
Kabushiki Kaisha Toshiba

Power holding circuit device

A power holding circuit device adapted for a vehicle microcontroller unit (mcu), a car battery, and an ignition switch (ign) comprises a metal-oxide-semiconductor field-effect transistor (mosfet) switch unit, wherein the mosfet switch unit is connected to the car battery; a first bipolar junction transistor (bjt), wherein the first bjt is connected to the mosfet switch unit and the ignition switch; and a second bipolar junction transistor (bjt), wherein the second bjt is connected to the mosfet switch unit and the vehicle mcu.. .
Industrial Technology Research Institute

Semiconductor device and overcurrent protection device

A semiconductor device includes a first main mos transistor and a second main mos transistor of a vertical structure that are inversely coupled to each other in series by sharing a drain electrode and a first sense mos transistor and a second sense mos transistor of a vertical structure that are inversely coupled to each other in series by sharing a drain electrode. The first sense mos transistor is used for detecting the main current of the first main mos transistor, and the second sense mos transistor is used for detecting the main current of the second main mos transistor..

System and anti-ambipolar heterojunctions from solution-processed semiconductors

Van der waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-swcnt) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios.
Regents Of The University Of Minnesota

Pulse-amplitude modulated hybrid comparator circuit

Some embodiments include apparatus and methods using a first latch to receive an input signal at a gate of a transistor of the first latch and compare the input signal with a reference signal to provide a first output signal at an output node of the first latch, and a second latch coupled to the output node of the first latch, the second latch including a complementary metal-oxide semiconductor (cmos) inverter to generate a second output signal at an output node of the second latch based on the first output signal. The second output signal has a signal swing greater than a signal swing of the first output signal..

Cell of transmission gate free circuit and integrated circuit layout including the same

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings..
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

To provide an inexpensive semiconductor device capable of suppressing the influence by crosstalk. A semiconductor device includes a signal wiring disposed in an organic interposer, an output circuit which is coupled to a first end of the signal wiring and which sets an impedance so as to generate a reflected wave antiphase to a waveform transmitted to the first end and periodically outputs data, and an input circuit which is coupled to a second end of the signal wiring and sets an impedance so as to generate a reflected wave of the same phase as a waveform transmitted to the second end.
Renesas Electronics Corporation

Control device using gan semiconductor

A control device includes: a differential amplification circuit that amplifies a difference with respect to an input signal; and a clipping circuit that is connected to an output side of the differential amplification circuit and clips an input voltage. The differential amplification circuit includes a plurality of switching elements formed of a gan semiconductor, and the clipping circuit includes a switching element formed of the gan semiconductor..
Advantest Corporation

Semiconductor device and power conversion device

To solve the problem of multi-pulse control in which the load of the control software is increased and further switching/timing adjustment is required, a semiconductor device includes a control unit including a cpu and a memory, a pwm output circuit for controlling the driver ic to drive the power semiconductor device, a current detection circuit for detecting the motor current, and an angle detection circuit for detecting the angle of the motor. The pwm output circuit includes a square wave generator circuit to generate a square wave based on the angle of the angle detection circuit as well as the base square wave information..
Renesas Electronics Corporation

Semiconductor device

A semiconductor device disclosed in the present specification has a structure that includes: a first terminal that is to be externally connected to a power source line; a second terminal that is to be externally connected to a ground line; a third terminal that is internally connected to the first terminal and to be externally connected to a first terminal of a bypass capacitor; and a fourth terminal that is internally connected to the second terminal and to be externally connected to a second terminal of the bypass capacitor.. .
Rohm Co., Ltd.

Power conversion device

A power conversion device including: a first capacitor and a second capacitor which are connected to each other in series; a plurality of first power semiconductor modules having terminals disposed on one surface; a plurality of second power semiconductor modules having terminals disposed on one surface; and a laminated bus bar connecting the first capacitor and the second capacitor and the plurality of modules, wherein the first power semiconductor modules and the second power semiconductor modules are disposed in such a manner that their respective output terminals face each other in a disposition direction of the terminals, and in the laminated bus bar, an output bus bar connecting the output terminals of the first power semiconductor modules and the second power semiconductor modules to each other is held in an insulated manner in an opening portion provided to the intermediate bus bar.. .
Fuji Electric Co., Ltd.

Power conversion device

A power conversion device comprising: a plurality of first power semiconductor modules incorporating a series circuit of a first semiconductor device and a second semiconductor device, the series circuit connected in parallel to a series circuit of a first capacitor and a second capacitor which are connected in series to a direct current power supply; a plurality of second power semiconductor modules incorporating a bi-directional semiconductor device connected between a connection point between the first capacitor and the second capacitor and a connection point between the first semiconductor device and the second semiconductor device; and a laminated bus bar connecting main circuit terminals of the plurality of first power semiconductor modules and the plurality of second power semiconductor modules to each other. The laminated bus bar incudes a pair of output bas bars disposed at a front side and a back side, respectively so as to facing each other..
Fuji Electric Co., Ltd.

Auxiliary power supply for switch-mode power supplies

A combined voltage regulator and snubber circuit generally has a voltage regulator device in parallel with the energy storage element of the snubber circuit operatively connectable in series with a leakage inductance current path; the leakage inductance being part of a magnetic component utilized in a switch-mode power supply having an input voltage source, controllable semiconductor switches, freewheeling semiconductor switches, feedback controller, reactive energy storage components and a load; the voltage regulator generally providing constant or variable voltage to the gate driver of the controllable semiconductor and/or feedback controller.. .
Appulse Power Inc.

Semiconductor laser

A semiconductor laser operable by a reduced bias is disclosed. The semiconductor laser includes a substrate, an active area including a quantum well structure, an emitter area and a collector area, where those areas laterally extend on the substrate as the emitter and collector areas sandwich the active area therebetween.
Sumitomo Electric Industries, Ltd.

Laser devices

An electrically-operated semiconductor laser device and method for forming the laser device are provided. The laser device includes a fin structure to which a waveguide is optically coupled.
Universiteit Gent

High-efficiency semiconductor laser

Embodiments of the present disclosure may relate to a hybrid silicon distributed feed-back (dfb) laser, wherein light is to propagate through the dfb laser along a length of the dfb laser. The dfb laser may include a mesa with a current channel that extends from the first side of the mesa to the second side of the mesa.
Intel Corporation

Surface-emitting semiconductor laser

Certain examples described herein relate to a surface-emitting semiconductor-laser which includes an oxide window, a light emitting cavity, and at least one phase matching window. The oxide window, the light emitting cavity, and the at least one phase matching layer are arranged so that a predetermined phase relationship is satisfied.
Sae Magnetics (h.k.) Ltd.

Method for manufacturing laser package

A method of manufacturing a laser package includes: providing a plurality of laser devices, each including: a submount, and an edge-emitting semiconductor laser element disposed on the submount; providing one or more optical members; providing a substrate; disposing a first bonding material and a second bonding material on the substrate; placing the plurality of laser devices on the upper surface of the substrate via the first bonding material, and placing the one or more optical members on the upper surface of the substrate via the second bonding material; and collectively heating the plurality of laser devices and the one or more optical members on the substrate without pressing the plurality of laser devices and the one or more optical members onto the substrate, so as to bond the laser devices and the one or more optical members to the substrate via the first and second bonding materials.. .
Nichia Corporation

Semiconductor device and semiconductor device manufacturing method

A semiconductor device is provided, in order to prevent tilt of a terminal pin in the semiconductor device with a printed board in which the terminal pin is pressed, the semiconductor device comprising a printed board, a plurality of pins pressed in the printed board, a resin block in which a plurality of through holes are formed, the plurality of pins respectively pressed in the plurality of through holes, and a resin case covering at least a part of the printed board and the resin block.. .
Fuji Electric Co., Ltd.

Semiconductor device and electronic device including the same

A semiconductor device capable of inputting signals and power without the use of an fpc is provided. The semiconductor device includes a first substrate and a second substrate.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and manufacturing method thereof

As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film..
Semiconductor Energy Laboratory Co., Ltd.

Method for manufacturing secondary cell

A method for manufacturing a secondary cell, the secondary cell including a charging layer that captures electrons by forming energy levels in a band gap by causing a photoexcited structural change in an n-type metal oxide semiconductor coated with an insulating material, includes: a coating step to coat a liquid so as to form a coating film that includes constituents that will form the charging layer; a drying step to dry the coating liquid coated in the coating step; a uv irradiating step to form a uv-irradiated coating film by irradiating the dried coating film obtained through the drying step with ultraviolet light; and a burning step to burn a plurality of the uv-irradiated coating films, after forming the plurality of uv-irradiated coating films by repeating a set plural times, the set including the coating step, the drying step, and the uv irradiating step.. .
Kabushiki Kaisha Nihon Micronics

Electronic device and fabricating the same

An electronic device including a semiconductor memory. The semiconductor memory may include a variable resistance element.
Sk Hynix Inc.

Semiconductor device

The vertical hall element includes: a second conductivity type semiconductor layer formed on a first conductivity type semiconductor substrate; a plurality of high-concentration second conductivity type electrodes formed in a straight line on a surface of the semiconductor layer having substantially the same shape, and spaced at a first interval; a plurality of electrode isolation layers each formed between two electrodes out of the plurality of electrodes to isolate the plurality of electrodes from one another having substantially the same shape, and spaced at a second interval; and a first added layer and a second added layer each formed along the straight line outside of the outermost electrodes, and each having substantially the same structure as that of each electrode isolation layer.. .
Sii Semiconductor Corporation

Semiconductor device and manufacturing the same

A semiconductor device includes a hall element, a sealing resin and at least one mount surface. The hall element includes a functional surface and at least one electrode provided on the functional surface.
Rohm Co., Ltd.

Semiconductor device comprising passive magnetoelectric transducer structure

A semiconductor device comprising a passive magnetoelectric transducer structure adapted for generating a charge via mechanical stress caused by a magnetic field. The first transducer structure has a first terminal electrically connectable to the control terminal of an electrical switch, and having a second terminal electrically connectable to the first terminal of the electrical switch for providing a control signal for opening/closing the switch.
Melexis Bulgaria Ltd.

Arrangement

An arrangement is disclosed. In an embodiment the arrangement includes at least one semiconductor component and a heat sink, wherein the semiconductor component is arranged on the heat sink, wherein the heat sink is configured to dissipate heat from the semiconductor component, wherein the heat sink comprises a thermally conductive material, and wherein the material comprises at least aluminum and silicon..
Osram Opto Semiconductors Gmbh

Component and producing a component

A component comprising a support and a semiconductor body arranged on the support, the support formed by a molded body and a metal layer. The metal layer has a first subregion and a second subregion laterally spaced apart by an intermediate space and thereby electrically separated.
Osram Opto Semiconductors Gmbh

Package for an ultraviolet emitting device

Embodiments of the invention include a light emitting diode (uvled), the uvled including a semiconductor structure with an active layer disposed between an n-type region and a p-type region. The active layer emits uv radiation.
Rayvio Corporation

Light emitting unit

A light emitting unit includes a light emitting semiconductor chip and a wavelength converter for the light of the semiconductor chip. The wavelength converter has a substrate with a first surface.
Osram Opto Semiconductors Gmbh

Light emitting device and manufacturing the same

A light emitting device includes a substrate, a light emitting element, a plurality of bumps and a cover member. The bumps are disposed between the substrate and the light emitting element to mount the light emitting element on the substrate.
Nichia Corporation

Light emitting diodes with sensor segment for operational feedback

Light emitting diodes (leds) having a sensor segment for operational feedback are described. A semiconductor stack is grown on a sapphire substrate.
Lumileds Llc

Component having improved coupling-out properties

A component includes a carrier and a semiconductor body arranged on the carrier, wherein the semiconductor body has an active layer arranged between the first and second semiconductor layers and is configured to generate, during operation of the component, an electromagnetic radiation that can be coupled out from the component through a first main surface, the first main surface of the component has an electrical contact layer configured to electrically contact a first semiconductor layer and in a plan view the carrier covers the first main surface in places, and in direct vicinity of the electrical contact layer the component includes a shielding structure configured to prevent electromagnetic radiation generated by the active layer from impinging onto the contact layer.. .
Osram Opto Semiconductors Gmbh

Light-emitting diode

A light emitting diode includes a substrate, a lower semiconductor layer disposed on the substrate, a light emitting unit comprising a first upper semiconductor layer disposed in one region of the lower semiconductor layer and an active layer interposed between the lower semiconductor layer and the first upper semiconductor layer, a second current spreading portion comprising a third upper semiconductor layer disposed in another region of the lower semiconductor layer and an active layer interposed between the lower semiconductor layer and the third upper semiconductor layer, a first electrode disposed on the light emitting cell and electrically connected to the first upper semiconductor layer, and a second electrode separated from the light emitting cell and electrically connected to the lower semiconductor layer.. .
Seoul Viosys Co., Ltd.

Method of manufacturing light-emitting device

A method of manufacturing a light-emitting device includes: providing a light-emitting element, the light-emitting element comprising a layered semiconductor partially comprising an active layer in a plan view; mounting the light-emitting element on a supporting member; forming a phosphor layer so as to cover the light-emitting element; determining a surplus portion of the phosphor layer; and removing at least a portion of the phosphor layer in a region in the plan view in which the active layer is not disposed.. .
Nichia Corporation

Light-emitting element

A light-emitting element includes: a semiconductor structure; light-reflecting electrodes; a first insulating film having: one or more first n-side openings and one or more first p-side openings; one or more interconnect electrodes on an upper surface of the first insulating film; a first electrode on the upper surface of the first insulating film; a second electrode on the upper surface of the first insulating film; a second insulating film having: one or more second n-side openings and one or more second p-side openings; a first external connection portion; and a second external connection portion.. .
Nichia Corporation

Semiconductor light emitting device

A semiconductor light emitting device includes a first semiconductor layer, an active layer disposed on the first semiconductor layer to emit ultraviolet light, a second semiconductor layer disposed on the active layer, and a first electrode disposed on the first semiconductor layer and being in ohmic contact with a portion of the first semiconductor layer, the first electrode including a contact electrode including aluminum (al) and at least one other material and having a first region adjacent to the first semiconductor layer and a second region, with each region having an al composition ratio defined by the amount of al relative to the amount of the at least one other material, wherein the al composition ratio of the first region is greater than the al composition ratio of the second region, and a metal layer disposed on the contact electrode.. .
Seoul Viosys Co., Ltd.

Light emitting device

An embodiment provides a light emitting element comprising: a first conductive semiconductor layer including a first layer and a second layer; an active layer on the first conductive semiconductor layer; a second conductive semiconductor layer on the active layer; and a first electrode and a second electrode arranged on the first conductive semiconductor layer and the second conductive semiconductor layer, respectively, wherein the first layer includes a plurality of first grooves, and a growth prevention layer is arranged on the bottom surface and side surfaces of each of the first grooves.. .
Lg Innotek Co., Ltd.

Semiconductor structure and semiconductor device

There are provided a semiconductor structure exhibiting excellent crystallinity by preventing the occurrence of a strain, and a semiconductor device. The semiconductor structure comprises a substrate, a bridging portion bridged to the substrate, a semiconductor layer formed on the bridging portion, a void defined by the substrate and the bridging portion.
Toyoda Gosei Co., Ltd.

Group iii nitride semiconductor light-emitting device and production method therefor

To provide a group iii nitride semiconductor light-emitting device in which a semiconductor layer is grown using a substrate containing al such as aln substrate while suppressing polarity inversion, and a production method therefor. The light-emitting device includes a substrate, a first oxide film formed in contact with the substrate, a first group iii nitride layer formed in contact with the first oxide film, a second oxide film formed in contact with the first group iii nitride layer, and an n-type contact layer on the second oxide film.
Toyoda Gosei Co., Ltd.

Method for producing group iii nitride semiconductor light-emitting device

To provide a method for producing a group iii nitride semiconductor light-emitting device using a substrate containing al such as aln substrate while suppressing polarity inversion. The production method comprising an oxide film formation step, a first group iii nitride layer formation step, a first semiconductor layer formation step, a light-emitting layer formation step, and a second semiconductor layer formation step.
Toyoda Gosei Co., Ltd.

Group iii nitride semiconductor light-emitting device

There are provided a group iii nitride semiconductor light-emitting device having complicated irregularities on the light extraction surface. The light-emitting device comprises a substrate, a p-type semiconductor layer, a light-emitting layer, and an n-type semiconductor layer.
Toyoda Gosei Co., Ltd

Compound semiconductor solar cell

A compound semiconductor solar cell that includes: a light absorbing layer; a first electrode; and a second electrode, wherein the light absorbing layer includes; a first semiconductor layer having a first band gap, a second semiconductor layer having a second band gap being larger than the first band gap and forming a hetero junction with the first semiconductor layer, and including a first material and a second material, and wherein in the junction buffer layer, a concentration of the first material on a surface in contact with the second semiconductor layer is larger than the concentration of the first material on a surface in contact with the first semiconductor layer, and a concentration of the second material on the surface in contact with the second semiconductor layer is smaller than the concentration of the second material on the surface in contact with the first semiconductor layer is disclosed.. .
Lg Electronics Inc.

Optoelectronic device and producing the same

A two-terminal optoelectronic device includes a substrate having a first and a second series of grooves. A channel may transect the grooves of the first and second series of grooves.
Big Solar Limited

Optical sensing device having integrated optics and methods of manufacturing the same

The present disclosure provides a communication system, a sensing device, and a semiconductor device, among other things. One example of the disclosed sensing device includes a semiconductor die having a photodetector, an optical element optically coupled to and disposed on the photodetector, at least one support structure substantially surrounding the optical element, and a top metal portion disposed on the semiconductor die adjacent to but distanced away from the optical element and the at least one support structure..
Avago Technologies General Ip (singapore) Pte. Ltd.

Solar cell and manufacturing the same

Disclosed is a solar cell including a plurality of first electrodes electrically connected to a plurality of first conductive regions; and a plurality of second electrodes electrically connected to a plurality of second conductive regions. The plurality of first conductive regions and the plurality of second conductive regions are spaced apart from an edge of a semiconductor substrate by a first interval, the plurality of first conductive regions and the plurality of second conductive regions are spaced apart from each other in a second direction crossing a first direction by a second interval, and the second interval is the same as or less than the first interval..
Lg Electronics Inc.

Pressure sensor and display device having the same

A pressure sensor includes a semiconductor layer, a gate electrode, a gate insulating layer, and a source electrode, and may be incorporated as a switching transistor in a display device. The gate electrode is configured to overlap the semiconductor layer.
Unist(ulsan National Institute Of Science And Technology)

Semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate having a tunneling well, a tunneling oxide layer, a charge storage layer and a control gate.
United Microelectronics Corp.

Manufacturing semiconductor device

A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator..
Semiconductor Energy Laboratory Co., Ltd.

Substrates and transistors with 2d material channels on 3d geometries

Roughly described, a transistor is formed with a semiconductor 2d material layer wrapped conformally on at least part of a 3d structure. The 3d structure can be for example a ridge made of a dielectric material, or made of dielectric material alternating longitudinally with a semiconductive or conductive material.
Synopsys, Inc.

Thin film transistor, fabricating the same, display substrate and display device

A thin film transistor, a method for fabricating the same, a display substrate, and a display device are disclosed. The method comprises: forming in sequence a light shielding layer, an insulating layer, and a semiconductor layer; and forming a pattern of the light shielding layer, the insulating layer, and the semiconductor layer in one patterning process.
Boe Technology Co., Ltd.

Manufacturing semiconductor device

To provide a highly reliable semiconductor device manufactured by giving stable electric characteristics to a semiconductor device including an oxide semiconductor. In a manufacturing process of a transistor, an oxide semiconductor layer, a source electrode layer, a drain electrode layer, a gate insulating film, a gate electrode layer, and an aluminum oxide film are formed in this order, and then heat treatment is performed on the oxide semiconductor layer and the aluminum oxide film, whereby an oxide semiconductor layer from which an impurity containing a hydrogen atom is removed and which includes a region containing oxygen more than the stoichiometric proportion is formed.
Semiconductor Energy Laboratory Co., Ltd.

Process for fabricating a field effect transistor having a coating gate

A process for fabricating a gate-wrap-around field-effect transistor is provided, including: providing a superposition of first to third nanowires, each made of a semiconductor, the second nanowire being subjected to a strain along its longitudinal axis, a median portion of the first to third nanowires being covered by a sacrificial gate; forming voids by removing a portion of the first and third nanowires that is intermediate between their ends and their median portion, while preserving the superposition of the first to third nanowires level with the ends and under the sacrificial gate; forming an electrical insulator in the voids around the second nanowire; removing the sacrificial gate and the median portion of the first and third nanowires; and forming a gate electrode wrapped around the median portion of the second nanowire.. .
Commissariat A L'energie Atomique Et Aux Energies Alternatives

Precise junction placement in vertical semiconductor devices using etch stop layers

A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region.
International Business Machines Corporation

Method of manufacturing a semiconductor device

An interlayer insulating film is formed on a gate insulating film and a gate electrode, and the interlayer insulating film is opened forming contact holes. Next, the interlayer insulating film and regions exposed by the contact holes are covered by a titanium nitride film, and the titanium nitride film is etched to remain only at portions of the gate insulating film and the interlayer insulating film exposed in the contact holes.
Fuji Electric Co., Ltd.

Semiconductor device and manufacturing the same

A semiconductor device according to one embodiment includes a semiconductor substrate having a first surface, an insulating isolation film disposed at the first surface, and a gate electrode. The semiconductor substrate has a source region, a drain region, a drift region, and a body region.
Renesas Electronics Corporation

Semiconductor device

Each first p+-type region is provided between adjacent trenches embedded with a mos gate and is in contact with a p-type base region. Second p+-type regions face a bottom and bottom corner portions of the trenches in a depth direction.
National Institute Of Advanced Industrial Science And Technology

Silicon carbide semiconductor device and manufacturing silicon carbide semiconductor device

A silicon carbide semiconductor device, including a silicon carbide substrate, a drift layer provided on a front surface of the silicon carbide substrate, an embedded layer selectively provided in a surface layer of the drift layer, an epitaxial layer provided on the drift layer, a channel layer provided on the epitaxial layer, a source region selectively provided in a surface layer of the channel layer, a trench penetrating the source region and the channel layer and reaching the epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a source electrode in contact with the channel layer and the source region, and a drain electrode provided on a rear surface of the silicon carbide substrate. The embedded layer is arranged underneath the trench in a depth direction.
Fuji Electric Co., Ltd.

Semiconductor device and manufacturing semiconductor device

A p-type base region is constituted by first to fifth p-type base regions. The first p-type base region is provided deeper than gate trenches.
Fuji Electric Co., Ltd.

Semiconductor device and manufacturing thereof

A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the second conductivity type, a third semiconductor region of the first conductivity type, a trench, a first electrode, and a schottky electrode. Between trenches where the schottky electrode is provided, a sidewall of each of the trenches is in contact with first semiconductor layer; and between trenches where the first electrode is provided, a sidewall of each of the trenches is in contact with the second semiconductor region and the third semiconductor region.
Fuji Electric Co., Ltd.

Semiconductor device and manufacturing the semiconductor device

On a front surface of a semiconductor base, a first n−-type drift region, a second n-type drift region, and a third n+-type drift region are provided. In the front surface of the semiconductor base, a gate trench is provided penetrating the n+-type source region and the p-type base region, and reaching the second n-type drift region.
National Institute Of Advanced Industrial Science And Technology

Switching element and manufacturing switching element

A switching element includes a semiconductor substrate that includes a first n-type semiconductor layer, a p-type body layer constituted by an epitaxial layer, and a second n-type semiconductor layer separated from the first n-type semiconductor layer by the body layer, a gate insulating film that covers a range across the surface of the first n-type semiconductor layer, the surface of the body layer, and the surface of the second n-type semiconductor layer, and a gate electrode that faces the body layer through the gate insulating film. An interface between the first n-type semiconductor layer and the body layer includes an inclined surface.
Toyota Jidosha Kabushiki Kaisha

Electronic device using group iii nitride semiconductor and its fabrication method

The present invention discloses an electronic device formed of a group iii nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy.
Sixpoint Materials, Inc.

Electronic device using group iii nitride semiconductor and its fabrication method

The present invention discloses an electronic device formed of a group iii nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy.
Sixpoint Materials, Inc.

Transistor having high electron mobility

A method for manufacturing a transistor having high electron mobility, encompassing a substrate having a heterostructure, in particular an algan/gan heterostructure, having the steps of: generation of a gate electrode by patterning a semiconductor layer that is applied onto the heterostructure, the semiconductor layer encompassing, in particular, polysilicon; application of a passivating layer onto the semiconductor layer; formation of drain regions and source regions by generation of first vertical openings that extend at least into the heterostructure; generation of ohmic contacts in the drain regions and in the source regions by partly filling the first vertical openings with a first metal at least to the height of the passivating layer; and application of a second metal layer onto the ohmic contacts, the second metal layer projecting beyond the passivating layer.. .
Robert Bosch Gmbh

Semiconductor structures and fabricating the same

A semiconductor structure is provided. The semiconductor structure includes a silicon substrate having a groove, an epitaxial layer disposed on the sidewalls of the groove, and a gate disposed above the epitaxial layer and electrically connected to the epitaxial layer.
Industrial Technology Research Institute

Semiconductor device and manufacturing the semiconductor device

A semiconductor device includes a semiconductor substrate having a first surface and a second surface, first to eighth regions, a first thyristor, and a second thyristor. The seventh region with the impurity concentration higher than that of the first region is formed in the first region while being apart from the sixth region electrically connected to the gate electrode, and being electrically connected to the first electrode.
Shindengen Electric Manufacturing Co., Ltd.

Trench gate igbt

A high-performance trench gate igbt is provided. A trench gate igbt according to one embodiment includes: a semiconductor substrate (11); a channel layer (15) provided on the semiconductor substrate (11); two floating p-type layer (12) provided on both sides of the channel layer 15, the floating p-type layers (12) being deeper than the channel layer (15); two emitter trenches (13) disposed between the two floating p-type layers (12), the emitter trenches (13) being respectively in contact with the floating p-type layers (12); at least two gate trenches (14) disposed between the two emitter trenches (13); and a source diffusion layer (19) disposed between the two gate trenches 14, the source diffusion layer (19) being in contact with each of the gate trenches (14)..
Renesas Electronics Corporation

Igbt semiconductor structure

Igbt semiconductor structure having a p+ substrate, an n− layer, at least one p region adjacent to the n− layer, and at least one n+ region adjacent to the p region, a dielectric layer and three terminal contacts. The p region forms a first p-n junction together with the n− layer, and the n+ region forms a second p-n junction together with the at least one p region.
3-5 Power Electronics Gmbh

Electronic device using group iii nitride semiconductor and its fabrication method

The present invention discloses an electronic device formed of a group iii nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy.
Sixpoint Materials, Inc.

Electronic device using group iii nitride semiconductor and its fabrication method

The present invention discloses an electronic device formed of a group iii nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy.
Sixpoint Materials, Inc.

Hemt having heavily doped n-type regions and process of forming the same

A hemt made of nitride semiconductor materials and a process of forming the same are disclosed, where the hemt has n-type regions beneath the source and drain electrodes with remarkably increased carrier concentration. The hemt provides the n-type regions made of at least one of epitaxially grown zno layer and mgzno layer each doped with at least aluminum and gallium with density higher than 1×1020 cm−3.
Sumitomo Electric Industries, Ltd.

Semiconductor device and manufacturing the same

To provide a semiconductor device with favorable electrical characteristics. To provide a method for manufacturing a semiconductor device with high productivity.
Semiconductor Energy Laboratory Co., Ltd.

Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid phase doping

A method of forming semiconductor devices that includes forming an oxide that is doped with a punch through dopant on a surface of a first semiconductor material having a first lattice dimension, and diffusing punch through dopant from the oxide into the semiconductor material to provide a punch through stop region. The oxide may then be removed.
Globalfoundries Inc.

Finfet isolation structure and fabricating the same

A semiconductor device includes a semiconductor substrate and a semiconductor fin on the semiconductor substrate and a fin isolation structure on the semiconductor substrate. The fin isolation structure has an air gap dividing the semiconductor fin into two portions of the semiconductor fin, in which the air gap extends into the semiconductor substrate for a distance.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method of manufacturing a semiconductor device integrating a vertical conduction transistor, and semiconductor device

A method of manufacturing a vertical conduction semiconductor device comprising the steps of: forming a recess in a monocrystalline silicon substrate; forming a silicon oxide seed layer in the recess; carrying out an epitaxial growth of silicon on the substrate, simultaneously growing a polycrystalline silicon region in the seed layer and a monocrystalline silicon region in surface regions of the substrate, which surround the seed layer; and implanting dopant species in the polycrystalline silicon region to form a conductive path in order to render the second conduction terminal electrically accessible from a front side of the vertical conduction semiconductor device.. .
Stmicroelectronics S.r.l.

Semiconductor device and fabricating the same

A semiconductor device includes a substrate having a first conductive type. An epitaxial layer having a second conductive type is disposed on the substrate.
Nuvoton Technology Corporation

Method for forming a semiconductor structure

A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided.
United Microelectronics Corp.

Semiconductor device and fabricating the same

A method for fabricating a semiconductor device includes: forming a semiconductor structure including a pattern; forming an epitaxial layer having a first dopant concentration in the pattern; forming in-situ an interface layer having a second dopant concentration higher than the first dopant concentration, over the epitaxial layer; forming a metal silicide layer over the interface layer; and forming a metal plug over the metal silicide layer.. .
Sk Hynix Inc.

Multi-threshold voltage semiconductor device

A semiconductor device preferably includes: a first metal-oxide semiconductor (mos) transistor on a substrate; a first ferroelectric (fe) layer connected to the first mos transistor; a second mos transistor on the substrate; and a second fe layer connected to the second mos transistor. Preferably, the first fe layer and the second fe layer include different capacitance..
United Microelectronics Corp.

Circuits using gate-all-around technology

A semiconductor structure includes a first gaa transistor and a second gaa transistor. The first gaa transistor includes: a first diffusion region, a second diffusion region, and a first nanowire.
Taiwan Semiconductor Manufacturing Company Ltd.

Semiconductor device and manufacturing method thereof

A fin fet semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The fin fet device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor devices and contact plugs

A semiconductor device has a high electric connection reliability and includes a base substrate having a connection target layer, a lower contact plug formed over the base substrate and electrically connected to the connection target layer, and an upper contact plug formed over the lower contact plug, wherein the lower contact plug includes a lower plug layer having a gap portion extending inward from a top portion of the lower plug layer, a gap cover layer filling the gap portion, and an upper cover layer covering a top surface of the lower plug layer.. .
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing the same

Characteristics of a semiconductor device are improved. An active region including a mos transistor is structured such that the active region includes, in a plan view, a first side extending in x direction, a second side opposing the first side, an extension part projecting from the first side, and a cut-away portion recessed from the second side.
Renesas Electronics Corporation

Semiconductor device, manufacturing semiconductcor device, and electronic device

A semiconductor device includes a compound semiconductor layer, a gate electrode, and first and second insulating layers. The first insulating layer covers the gate electrode on the compound semiconductor layer and has a cavity that surrounds the gate electrode.
Fujitsu Limited

V-grooved vertical channel-type 3d semiconductor memory device and manufacturing the same

A method of fabricating a vertical channel 3d semiconductor memory device is disclosed. In one aspect, the method comprises providing a stack of alternating layers of conductive material and dielectric material on a major surface of substrate, providing in the stack at least one trench, having sloped sidewalls sloping towards the major surface, extending at least below the lowest layer of conductive material, forming, in order, a programmable material, a channel liner, and a filler material on the sidewalls of the trench.
Imec Vzw

Semiconductor device and manufacturing thereof

In a semiconductor device, a width of a second epitaxial layer is greater than a width of a first epitaxial layer, and a thickness of an end portion of the second epitaxial layer, which is in contact with an element isolation portion, is smaller than a thickness of an end portion of the first epitaxial layer, which is in contact with the element isolation portion, and a second shortest distance between the element isolation portion and a second plug is greater than a first shortest distance between the element isolation portion and a first plug.. .
Renesas Electronics Corporation

Two dimensional field effect transistors

The disclosed technology relates generally to semiconductor devices, and more particularly to field-effect transistors (fets) comprising nanostructures, such as nanowires, fins, and two dimensional materials. In an aspect, a fet device comprises a substrate having an insulating surface and a vertical structure extending in a direction substantially perpendicular to the insulating surface, where the vertical structure has at least outer surfaces formed of an insulating material.
Imec Vzw

Forming nanosheet transistors with differing characteristics

A method of forming a transistor in an integrated circuit device can include forming a first and second nanosheet structure with alternating sheets of silicon and silicon germanium. A first and second transistor structure are constructed using the first and second nanosheet structures as first and second channels.
International Business Machines Corporation

Semiconductor device and manufacturing semiconductor device

In an active region, a contact trench in which a source electrode is embedded is provided. In a boundary region between the active region and the edge termination region, a tapered trench is provided.
Fuji Electric Co., Ltd.

Semiconductor device

A semiconductor device includes a substrate that includes active patterns extending in a second direction, a third device isolation layer disposed on an upper portion of the substrate that includes a pmosfet region and an nmosfet region, and a gate electrode that extends across the active patterns in a first direction that crosses the second direction. The active patterns extend across the pmosfet region and the nmosfet region.
Samsung Electronics Co., Ltd.

Semiconductor device

Active patterns protrude from a substrate. The active patterns include a first active pattern, a second active pattern spaced apart from the first active pattern at a first distance, and a third active pattern spaced apart from the second active pattern at a second distance greater than the first distance.
Samsung Electronics Co., Ltd.

Semiconductor device, power conversion device, and manufacturing semiconductor device

A buffer layer includes a first buffer layer being joined to an active layer and having one peak point of an impurity concentration and a second buffer layer being joined to the first buffer layer and a drift layer, having at least one peak point of an impurity concentration, and having a maximum impurity concentration lower than that of the first buffer layer, and the maximum impurity concentration of the second buffer layer is higher than the impurity concentration of the drift layer and equal to or lower than 1.0×1015 cm−3.. .

Capacitor structure and semiconductor device including the same

A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes..
Samsung Electronics Co., Ltd.

Mis capacitor

In one embodiment of the present invention, there is provided an mis capacitor, including: a lower electrode formed with a semiconductor substrate having electrical conductivity and through which an electrical signal passes at a lower surface thereof; an insulating layer formed on the lower electrode; an upper electrode formed on the insulating layer and through which the electrical signal passes at an upper surface thereof; and a first conductive layer formed on side surfaces of the lower electrode so that the electrical signal passing the lower surface and an upper surface of the lower electrode passes along the side surfaces of the lower electrode, wherein the first conductive layer has electro conductivity higher than the electro conductivity of the lower electrode.. .
Korea Electronics Technology Institute

Array substrate for thin film transistor and display device of the same

A thin-film transistor array substrate and a display device are disclosed. The thin-film transistor array substrate includes a substrate, a gate electrode disposed on the substrate, an active layer, which opposites the gate electrode, has a first region and a second region having different thicknesses, and comprises at least a semiconductor material, a gate insulating film interposed between the gate electrode and the active layer, and a source electrode and a drain electrode, which are respectively in contact with the active layer..
Lg Display Co., Ltd.

Substrate for display device and display device including the same

A substrate for a display device and a display device including the same are disclosed. The substrate includes a first thin-film transistor including an oxide semiconductor layer, a second thin-film transistor spaced apart from the first thin-film transistor and including a polycrystalline semiconductor layer, and a storage capacitor including at least two storage electrodes.
Lg Display Co., Ltd.

Photo electric converter, imaging system, and manufacturing photoelectric converter

A method for manufacturing a photoelectric converter includes a first step of preparing a semiconductor substrate including a metal oxide semiconductor (mos) transistor, a second step of forming a plurality of interlayer insulating films above the semiconductor substrate, and a third step of forming a photoelectric conversion portion above the semiconductor substrate. The second step includes a step of forming a first film containing hydrogen.
Canon Kabushiki Kaisha

Backside metal grid and metal pad simplification

An image sensor includes a semiconductor material including a plurality of photodiodes disposed in the semiconductor material. The image sensor also includes a first insulating material disposed proximate to a frontside of the semiconductor material, and an interconnect disposed in the first insulating material proximate to the frontside of the semiconductor material.
Omnivision Technologies, Inc.

Semiconductor apparatus, system, and producing semiconductor apparatus

A semiconductor apparatus includes a silicon layer including first and second semiconductor regions; an insulator film, on the silicon layer, having first and second holes positioned on the first and second semiconductor regions; a first metal portion containing a first metal element in the first hole; a first conductor portion containing a second metal element between the first metal portion and the first semiconductor region; a first silicide region containing the second metal element between the first conductor portion and the first semiconductor region; a second metal portion containing the first metal element in the second hole; a second conductor portion containing the second metal element between the second metal portion and the second semiconductor region; and a second silicide region containing a third metal element between the second conductor portion and the second semiconductor region, wherein the first conductor portion thickness is greater than the second conductor portion thickness.. .
Canon Kabushiki Kaisha

Image sensor with processor package

A semiconductor package and a method for forming a semiconductor package are disclosed. The semiconductor package includes a multi-layer package substrate having interconnect structures embedded therein.
Utac Headquarters Pte. Ltd.

Semiconductor device and fabricating the same

A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, first and second recesses spaced apart from each other in a first direction within the substrate, a first gate electrode filling the first recess and protruding above the substrate, a second gate electrode filling the second recess and protruding above the substrate, a first source/drain formed between the first and second recesses, a second source/drain formed in an opposite direction to the first source/drain with respect to the first recess, and a third source/drain formed in an opposite direction to the first source/drain with respect to the second recess and electrically connected to the second source/drain..
Samsung Electronics Co., Ltd.

Protection ring for image sensors

Some embodiments relate to a pixel sensor array including a plurality of photosensors arranged in a semiconductor substrate. A protection ring circumscribes an outer perimeter of the pixel sensor array.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method for manufacturing a semiconductor device

The pixel characteristics are prevented from being degraded due to diffusion of electrons and fe (iron) from the surface of an element isolation trench formed in the top surface of a semiconductor substrate into a photodiode forming the pixel of an image sensing element. Further, oxygen is prevented from being diffused from a boron oxide film formed at the surface of the element isolation trench into the photodiode.
Renesas Electronics Corporation

Solid-state image sensing device, electronic device, and manufacturing solid-state image sensing device

The present technology relates to a solid-state image sensing device for preventing a reduction in light receiving sensitivity of an avalanche photodiode, an electronic device, and a method for manufacturing the solid-state image sensing device. A solid-state image sensing device includes an avalanche photodiode having a first region of a first conductive type, a second region of a second conductive type different from the first conductive type, and an avalanche region sandwiched between the first region and the second region, which extend in a thickness direction of a semiconductor substrate, and a film formed on at least one side of the semiconductor substrate and including a metal oxide film, a metal nitride film, or a mix crystal-based film of metal oxide film and metal nitride film.
Sony Semiconductor Solutions Corporation

Thin film transistors, arrays substrates, and manufacturing methods

The present disclosure relates to a tft includes an active layer formed on a substrate, wherein the active layer includes a first semiconductor layer and a second semiconductor layer stacked together. The first semiconductor layer is made by indium gallium zinc oxide (igzo) having an atomic ratio in/(ga+zn) smaller than 50%, and the second semiconductor layer is made by igzo having the atomic ratio in/(ga+zn) greater than 55%.
Wuhan China Star Optoelectronics Technology Co., Ltd.

Array substrate and manufacturing the same

The present application discloses an array substrate and a method of manufacturing the same. The array substrate includes a first insulating layer disposed on the substrate; a source electrode pattern disposed within the first insulating layer; an annular gate electrode pattern disposed on the first insulating layer and surrounded the periphery of the source electrode pattern; a second insulating layer covering on the annular gate electrode pattern; a semiconductor pattern disposed in the annular area of the annular gate electrode pattern, and is electrically connected to the exposed portion of the source electrode pattern, the semiconductor pattern is further electrical insulation to the annular gate electrode pattern through the second insulating layer; a pixel electrode disposed on the second insulating layer and electrically connected to a side of the semiconductor pattern remote from the substrate..
Shenzhen China Star Optoelectronics Technology Co. , Ltd.

Display device

By applying an ac pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an ac pulse.
Semiconductor Energy Laboratory Co., Ltd.

Structure and fully depleted silicon on insulator structure for threshold voltage modification

A method for fabricating a fully depleted silicon on insulator (fdsoi) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate.
Globalfoundries Inc.

3d nand high aspect ratio structure etch

Embodiments of the present disclosure provide methods for forming features in a film stack. The film stack may be utilized to form stair-like structures with accurate profiles control in manufacturing three dimensional (3d) stacking of semiconductor chips.
Applied Materials, Inc.

Vertical semiconductor devices

A vertical semiconductor device includes odd and even cell blocks, and odd and even block pad structures. Each of the odd cell blocks includes first conductive line structures including conductive lines and insulation layers alternatively stacked in a first direction.
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing the semiconductor device

Characteristics of a semiconductor device having a nonvolatile memory are improved. A high dielectric constant film is provided on an insulating film between a memory gate electrode and a fin as components of a nonvolatile memory.
Renesas Electronics Corporation

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region.
Toshiba Memory Corporation

Semiconductor device and manufacturing the same

In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area.
Taiwan Semiconductor Manufacturing Co., Ltd.

Three-dimensional memory devices containing inter-tier dummy memory cells and methods of making the same

A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at least one joint-level doped semiconductor portion.. .
Sandisk Technologies Llc

Manufacturing semiconductor device and semiconductor device

After a dummy control gate electrode and a memory gate electrode are formed and an interlayer insulating film is formed so as to cover the gate electrodes, the interlayer insulating film is polished to expose the dummy control gate electrode and the memory gate electrode. Thereafter, the dummy control gate electrode is removed by etching, and then a control gate electrode is formed in a trench which is a region from which the dummy control gate electrode has been removed.
Renesas Electronics Corporation

Semiconductor device and manufacturing the same

A semiconductor device in which the cell size is small and disturbance in reading operation is suppressed, and a method for manufacturing the semiconductor device. A first memory cell has a first memory transistor.
Renesas Electronics Corporation

Methods of forming memory arrays

Some embodiments include a method of forming a memory array. A wordline is formed to extend along a first direction, and along a rail of semiconductor material.
Micron Technology, Inc.

Memory arrays

Some embodiments include a memory array having memory cells arranged in rows and columns. The rows extend along a first direction and the columns extend along a second direction, with an angle between the first and second directions being less than 90°.
Micron Technology, Inc.

Stacked three-dimensional arrays of two terminal nanotube switching devices

Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.. .
Nantero, Inc.

Semiconductor device

A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.. .
Samsung Electronics Co., Ltd.

Tall single-fin fin-type field effect transistor structures and methods

Disclosed are methods of forming improved fin-type field effect transistor (finfet) structures and, particularly, relatively tall single-fin finfet structures that provide increased drive current over conventional single-fin finfet structures. The use of such a tall single-fin finfet provides significant area savings over a finfet that requires multiple semiconductor fins to achieve the same amount of drive current.
Globalfoundries Inc.

Conductivity modulated drain extended mosfet

An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (igbt) is formed upon the semiconductor substrate in which the igbt has an anode terminal, a cathode terminal, and a gate terminal, and a drift region.
Texas Instruments Incorporated

Semiconductor device

A semiconductor device that allows easy hole extraction is provided. The semiconductor device includes: a semiconductor substrate having drift and base regions; a transistor portion formed in the semiconductor substrate; and a diode portion formed adjacent to the transistor portion and in the semiconductor substrate.
Fuji Electric Co., Ltd.

Fin-shaped field effect transistor and capacitor structures

A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface.
Avago Technologies General Ip (singapore) Pte. Ltd.

Semiconductor device and manufacturing semiconductor device

A semiconductor device of the present invention includes, in a region 1c, a top electrode made by a semiconductor layer of an soi substrate, a capacitive insulating film made by an insulating layer, a bottom electrode made by a supporting board, and a lead part (a high-concentration impurity region of an n type) of the bottom electrode coupled to the supporting board. An soi transistor in a region 1b is formed over a main surface of the semiconductor layer over the insulating layer as a thin film, and threshold voltage can be adjusted by applying a voltage to a well arranged on the rear face side of the insulating layer..
Renesas Electronics Corporation

Controlled resistance integrated snubber for power switching device

A semiconductor substrate has a main surface, a rear surface, an active device region, and an inactive region adjacent the active device region. Doped source, body, drift and drain regions, and electrically conductive gate and field electrodes are disposed in the active device region.
Infineon Technologies Americas Corp.

Integrated semiconductor device having isolation structure for reducing noise

An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.. .
Magnachip Semiconductor, Ltd.

Semiconductor module

A semiconductor module includes: a first substrate having a first insulating substrate and a first conductor layer; a power device part having a first electrode, a second electrode and a gate electrode; a second substrate having a second insulating substrate and a second conductor layer, wherein the second conductor layer has a bonding portion and a surrounding wall portion formed at a position which surrounds the bonding portion as viewed in a plan view; an inner resin portion; a control ic; and an outer resin portion, wherein the power device part is disposed such that the gate electrode is positioned outside a region defined by the surrounding wall portion as viewed in a plan view, and the gate electrode is electrically connected to an output terminal of the control ic through a connecting member.. .
Shindengen Electric Manufacturing Co., Ltd.

Manufacturing high-voltage light-emitting diode

The disclosure relates to a high-voltage light-emitting diode (hv led) and a manufacturing method thereof. A plurality of led dies connected in series, in parallel, or in series and parallel are formed on a substrate.
Genesis Photonics Inc.

Micro-led module and fabricating the same

A micro-led module is disclosed. The micro-led module includes: a micro-led including a plurality of led cells, each of which includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; a submount substrate mounted with the micro-led; a plurality of electrode pads formed on the micro-led cells; a plurality of electrodes formed corresponding to the plurality of electrode pads on the submount substrate; a plurality of connection members through which the plurality of electrode pads are connected to the corresponding plurality of electrodes; and a gap fill layer formed in the gap between the micro-led and the submount substrate and having a bonding strength to the micro-led and the submount substrate..
Lumens Co., Ltd.

Stacked semiconductor dies with selective capillary under fill

Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing a semiconductor device includes forming at least three stacks of semiconductor dies over a substrate, the stacks spaced apart from one another by gaps.
Micron Technology, Inc.

Semiconductor device

A semiconductor device comprising a plurality of semiconductor chips and a plurality of electric wirings. The plurality of semiconductor chips are stacked in a first direction, each semiconductor chip of the plurality of semiconductor chips including a plurality of conductive pads that are aligned in an aligning direction, orthogonal to the first direction.
Buffalo Memory Co, Ltd.

Thermal management of molded packages

An embodiment includes an apparatus comprising: a semiconductor die; package molding that is molded onto and conformal with a first die surface of the semiconductor die and at least two sidewalls of the semiconductor die, the package molding including: (a)(i) a first surface contacting the semiconductor die, (a)(ii) a second surface opposite the first surface, and (a)(iii) an aperture that extends from the first surface to the second surface; and a polymer substantially filling the aperture; wherein the package molding includes a first thermal conductivity (watts per meter kelvin (w/(m·k)) and the polymer includes a second thermal conductivity that is greater than the first thermal conductivity. Other embodiments are described herein..
Intel Corporation

Systems and methods for bonding semiconductor elements

A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element, wherein the surfaces of each of the plurality of first conductive structures and the plurality of second conductive structures include aluminum; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures.. .
Kulicke And Soffa Industries, Inc.

Semiconductor device and manufacturing semiconductor device

Provided is a semiconductor device comprising; a semiconductor chip, a first electrode pair, a first wire group that has a plurality of bonding wires connecting electrodes of the first electrode pair in parallel, and a sealing portion that mold-seals said elements, wherein the plurality of bonding wires belonging to the first wire group are wired such that length of each of the bonding wires on a far side in a first direction parallel with an in-plane direction of the semiconductor chip is longer than length of each of the bonding wires on a near side, and each height at respective positions of each of the bonding wires on the far side in the first direction is not lower than each height at respective positions, corresponding to the respective positions of each of the bonding wires on the far side, of each of the bonding wires on the near side.. .
Fuji Electric Co., Ltd.

Method of manufacturing semiconductor device

As one embodiment, a method of manufacturing a semiconductor device includes the following steps. That is, the method of manufacturing a semiconductor device includes a first step of applying ultrasonic waves to a ball portion of a first wire in contact with a first electrode of the semiconductor chip while pressing the ball portion with a first load.
Renesas Electronics Corporation

Common contact semiconductor device package

A semiconductor device package includes a conductive clip that has a recess and that is configured to mount to a substrate along a first surface and a second surface that bound the recess, and that includes at least two vertical channel transistors that are of a same type and that are mounted within the recess in a same orientation such that a drain or source contact is coupled to the conductive clip, and such that a gate contact and a source or drain contact extend exposed within the recess and along a same long axis of the conductive clip.. .
Infineon Technologies Americas Corp.

Semiconductor device and making semiconductor device

Inexpensive production is achieved while avoiding the degradation of electrical performance caused by the lowering of heat dissipation. The base plate 11 used here has a linear expansion coefficient of 2 to 10 ppm/k, which differs from the linear expansion coefficient of the semiconductor chip 13 by an absolute value of 7 ppm/k or smaller.
Sumitomo Electric Industries, Ltd.

Multi-layer redistribution layer for wafer-level packaging

Aspects of the embodiments include a semiconductor package that includes a printed circuit board (pcb) and a semiconductor die. The semiconductor die including an interconnect landing pad on an active side of the semiconductor die; a solder material on the interconnect landing pad; a partial redistribution layer on the active side of the semiconductor die; and a protection layer on the partial redistribution layer, the protection layer comprising the solder material.
Intel Ip Corporation

Semiconductor device and manufacturing semiconductor device

A semiconductor device includes a semiconductor substrate, a conductor provided on a main surface of the semiconductor substrate, an insulating layer disposed to cover a surface of the conductor and having a recess from a surface thereof towards the conductor, the recess having an opening provided at a bottom portion of the recess and exposing a portion of the conductor, and an external connection terminal connected to the portion of the conductor exposed from the opening. In a plan view of the semiconductor device, the external connection terminal covers the entire opening, and the entire external connection terminal is within the recess..
Lapis Semiconductor Co., Ltd.

Packaging assembly and making the same

A packaging assembly includes a semiconductor device. The semiconductor device includes a conductive pad having a first width, and an under-bump metallization (ubm) layer on the conductive pad, wherein the ubm layer has a second width greater than the first width.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor memory device including a dummy word line

A semiconductor memory device having dummy word lines is disclosed. In the semiconductor memory device, a number of dummy word lines are arranged at both ends of a cell mat..
Sk Hynix Inc.

Semiconductor device

A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side.
Renesas Electronics Corporation

Semiconductor device and power electronics apparatus

A semiconductor device is provided, the semiconductor device having: a semiconductor chip; a wiring substrate which supports the semiconductor chip and is electrically connected to the semiconductor chip; a first metal plate which supports the wiring substrate; a second metal plate which is arranged between the wiring substrate and the first metal plate; a first bonding part which bonds the wiring substrate and the second metal plate; and a second bonding part which bonds the first metal plate and the second metal plate, and having a thickness of an outer circumferential part of the second metal plate being larger than a thickness of a center part of the second metal plate.. .
Hitachi, Ltd.

Semiconductor package manufacturing method

A plurality of semiconductor packages are manufactured by a method that includes the steps of bonding a plurality of semiconductor chips on the front side of a wiring substrate, next supplying a sealing compound to the front side of the wiring substrate to form a resin layer from the sealing component on the front side of the wiring substrate, thereby forming a sealed substrate including the wiring substrate and the resin layer covering the semiconductor chips, next cutting the sealed substrate from the resin layer side by using a v blade to thereby form a v groove along each division line, next dividing the wiring substrate along each v groove to obtain a plurality of individual bare packages, and finally forming an electromagnetic shield layer on the upper surface and an inclined side surface of each bare package, thereby obtaining the plural semiconductor packages.. .
Disco Corporation

Methods for fabricating semiconductor shielding structures

The present disclosure is drawn to, among other things, a method of forming a semiconductor shield from a stock material having a thickness. In some aspects the methods includes providing a first layer of material on a first surface of the stock material, wherein at least a portion of the first layer of material includes a first window that exposes a portion of the first surface; providing a second layer of material on a second surface of the stock material, wherein the second surface of the stock material is spaced from the first surface by the thickness of the stock material, and wherein at least portion of the second layer of material includes a second window that exposes a portion of the second surface; and selectively removing a portion of the stock material exposed at the first or second windows, wherein the portion removed includes less than an entirety of the thickness of the stock material..
Everspin Technologies, Inc.

Semiconductor arrangement with a sealing structure

A semiconductor arrangement includes a semiconductor body with a first surface, an inner region and an edge region, the edge region surrounding the inner region, an attachment layer spaced apart from the first surface of the semiconductor body in a first direction, an intermediate layer arranged between the first surface of the semiconductor body and the attachment layer, and at least one first type sealing structure. The sealing structure includes a first barrier, a second barrier, and a third barrier.
Infineon Technologies Ag

Corrosion and/or etch protection layer for contacts and interconnect metallization integration

The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (cop) on the metallization structure.
Globalfoundries Inc.

Semiconductor device

A semiconductor device includes an insulating film formed to cover an electric fuse (ef1), an insulating film (il1), an insulating film (il2), an electric fuse (ef1), an insulating film (il1), and an insulating film (il2). The electric fuse (ef1) includes a fuse-blowing portion (fc1), a first pad portion (pd1), and a second pad portion (pd2).
Renesas Electronics Corporation

Method of tuning components within an integracted circuit device

A method of tuning inductive and/or capacitive components within an integrated circuit device. The method comprises measuring bare-die mounted performance of such a component formed within a semiconductor die, determining a package distribution layer pattern for the at least one component for achieving a desired performance for the at least one component based at least partly on the measured bare-die mounted performance, and packaging the semiconductor die with the determined package distribution layer pattern for the at least one component..
Nxp Usa, Inc.

Semiconductor package device and manufacturing the same

The disclosure relates to an electronic module and a manufacturing method of the same. The electronic module includes a substrate, an electronic component, a first package body, a magnetic layer, a coil and a second package body.
Advanced Semiconductor Engineering, Inc.

Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches

Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ild).
Intel Corporation

Wiring board and semiconductor device

A wiring board includes an insulator layer having a top surface, and a plurality of pads arranged in a pad arrangement region on the top surface of the insulator layer. The pad arrangement region includes a first region in which a first plurality of pads among the plurality of pads are arranged at a first density, and a second region in which a second plurality of pads among the plurality of pads are arranged at a second density lower than the first density.
Shinko Electric Industries Co., Ltd.

Semiconductor device

A semiconductor device which provides improved reliability. The semiconductor device includes: a wiring substrate having a first surface and a second surface opposite to the first surface; a chip condenser built in the wiring substrate, having a first electrode and a second electrode; a first terminal and a second terminal disposed on the first surface; and a third terminal disposed on the second surface.
Renesas Electronics Corporation

Semiconductor device and forming cantilevered protrusion on a semiconductor die

A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material.
Semiconductor Components Industries, Llc

High density package interconnects

Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part.
Intel Corporation

Package for semiconductor device and semiconductor device

A package for a semiconductor device includes: a plate-shaped base member having a substantially rectangular shape in a plan view; a first and second electrode solder pads configured to be electrically connected to a semiconductor element when the semiconductor element is mounted on an upper surface of the base member, the electrode solder pads being disposed at a lower surface side of the base member to face each other in a first direction; and first and second auxiliary solder pads disposed on a lower surface of the base member, the auxiliary solder pads being disposed at both sides of the electrode solder pads such that the first and second electrode solder pads are disposed between the first and second auxiliary solder pads in a plan view.. .
Nichia Corporation

Semiconductor device and manufacturing semiconductor device

A semiconductor device includes: a frame; a first-external-terminal provided to a first side portion of the frame; a first substrate enclosed in the frame and having a first-conductive-layer at an upper surface; a first-semiconductor-element: mounted on the first-conductive-layer; having, on a lower surface, a first main electrode connecting with the first-conductive-layer; and having a second main electrode and a control electrode on an upper surface; a first terminal connecting portion establishing a connection between the first-external-terminal and an exposed portion of the first-conductive-layer between the first-semiconductor-element and the first-external-terminal; a first-external-control-terminal provided above a wire in the frame and between the first main electrode of the first-semiconductor-element and the first-external-terminal; and a first control terminal connecting portion establishing a connection: between the control electrode of the first-semiconductor-element and the first-external-control-terminal; and above a wire between the first main electrode of the first-semiconductor-element and the first-external-terminal.. .
Fuji Electric Co., Ltd.

Packaged semiconductor device having nanoparticle adhesion layer patterned into zones of electrical conductance and insulation

A device comprises a substrate and an adhesive nanoparticle layer patterned into zones of electrical conductance and insulation on top of the substrate surface. A diffusion region adjoining the surface comprises an admixture of the nanoparticles in the substrate material.
Texasinstrumentslncorporated

Semiconductor device and manufacturing method thereof

An improvement is achieved in the reliability of a semiconductor device. A sip includes an analog chip, a microcomputer chip having a main surface smaller in area than a main surface of the analog chip, a die pad over which the analog chip and the microcomputer chip are mounted, and a plurality of leads arranged so as to surround the die pad.
Renesas Electronics Corporation

Fan-out semiconductor package

A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection member; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed therein and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the passive component is electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member..
Samsung Electro-mechanics Co., Ltd.

Semiconductor array and production micro device

There are provided a semiconductor array and a method for producing a micro device, in which the semiconductor laminate used in the micro device can be readily separated from the substrate. The semiconductor array includes a substrate, a bridging portion bridged to the substrate, a plurality of semiconductor laminates arranged on the bridging portion, and first voids defined by the substrate and the bridging portion.
Toyoda Gosei Co., Ltd.

Power module semiconductor device and inverter equipment, and fabrication the power module semiconductor device, and metallic mold

The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (d) disposed on the insulating substrate (10); a semiconductor chip (q) disposed on the first pattern; a power terminal (st, dt) and a signal terminal (cs, g, ss) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate..
Rohm Co., Ltd.

Semiconductor device package with stress relief layer

A semiconductor device package includes an encapsulation layer, a die, a stress relief layer, and a redistribution layer. The encapsulation layer has an opening, and the die is disposed in the opening of the encapsulation layer.
Powertech Technology Inc.

Semiconductor device and manufacturing the same

A semiconductor device includes: a base plate; an insulating substrate provided on an upper surface of the base plate; a conductive pattern provided on an upper surface of the insulating substrate; a semiconductor chip mounted on an upper surface of the conductive pattern; a case surrounding the base plate, the insulating substrate, the conductive pattern, and the semiconductor chip; a sealing resin sealing an interior of the case; and an external connection terminal provided to the case. One end portion of the external connection terminal is connected to the conductive pattern, the case has a terminal insertion portion enabling insertion of the other end portion of the external connection terminal in a peripheral wall portion thereof, and a portion of the external connection terminal other than the other end portion is sealed by the sealing resin with the other end portion being inserted in the terminal insertion portion..
Mitsubishi Electric Corporation

Case, semiconductor device and manufacturing case

A case and a semiconductor device including the case are provided for solving the following issues: when fixing a lid body to a case body by an adhesive, a process of attaching the lid body to the case body by applying the adhesive and curing the adhesive by heating is necessary, which requires much labor; also, when fixing the lid body to the case body by an engaging claw, it still requires much labor due to forming the engaging claw. The case includes a first member and a second member that is engaged with the first member to form an accommodation space inside the case, and the first member has a protruding portion extending from the first member side toward the second member side and having an end portion crushed from the opposite side of the first member to fix the second member to the first member..
Fuji Electric Co., Ltd.

Test structure for testing via resistance and method

Aspects of the present disclosure include a semiconductor test device and method. The test device includes a first kelvin testable structure and a second kelvin testable structure.
Globalfoundries Inc.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor apparatus, manufacturing the same, and equipment

A semiconductor apparatus includes a semiconductor substrate having an upper surface on which a semiconductor element is disposed, a lower surface opposite to the upper surface, and a side surface connecting the upper surface and the lower surface. The side surface has a plurality of concavities that each extend along the edge of the upper surface and that are arranged in a direction intersecting with the upper surface and the lower surface, and a plurality of ridges that are each located at the boundary between adjacent two of the plurality of concavities.
Canon Kabushiki Kaisha

Microelectronic assembly from processed substrate

Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate.
Invensas Bonding Technologies, Inc.

Processed substrate

Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate.
Invensas Bonding Technologies, Inc.

Systems and methods for wetting substrates

Methods of wetting a semiconductor substrate may include forming a controlled atmosphere in a processing chamber housing the semiconductor substrate. The semiconductor substrate may define a plurality of features, which may include vias.
Applied Materials, Inc.

Semiconductor chip, semiconductor wafer and manufacturing semiconductor wafer

The present disclosure relates to the technical field of semiconductors, and in particular to a semiconductor chip, a semiconductor wafer and a method for manufacturing a semiconductor wafer. The semiconductor chip comprises: a substrate, devices provided on a side of the substrate, via holes running through the substrate, conductive material filled in the via holes and contacted with the devices, and a backside metal layer provided on the other side of the substrate away from the devices, the backside metal layer coming into contact with the conductive material so as to be electrically connected to the devices via the conductive material.
Dynax Semiconductor, Inc.

Method for preparing substrate with carrier trapping center

The present disclosure provides a method for preparing a substrate with a carrier trapping center. The method includes: injecting bubbling ions into the semiconductor substrate to form a splitting layer, and injecting modified ions into the insulating layer to form a nano cluster; providing a supporting substrate; bonding the supporting substrate to the semiconductor substrate by using the insulating layer as an intermediate layer; performing a first heat treatment for the bonded substrate such that a splitting layer is formed at the position where the bubbling ions are injected, and causing the semiconductor substrate to split at the position of the splitting layer; thinning a splitting surface of the split semiconductor substrate; and performing a second heat treatment for the thinned semiconductor substrate to consolidate the bonding interface and form the nano cluster at the position where the modified ions are injected..
Shanghai Simgui Tehcnology Co., Ltd.

Method for transferring monocrystalline pads

A method of transferring blocks of semiconductor material to a substrate comprises the following steps: a. Providing an intermediate substrate, the intermediate substrate comprising, on one of its faces, blocks, the blocks comprise a monocrystalline material, the blocks comprising an embrittlement area delimiting a block portion intended to be transferred onto a final substrate; b.
Soitec

Wafer pin chuck fabrication and repair

In a wafer chuck design featuring pins or “mesas” making up the support surface, engineering the pins to have an annular shape, or to contain holes or pits, minimizes sticking of the wafer, and improves wafer settling. In another aspect of the invention is a tool and method for imparting or restoring flatness and roughness to a surface, such as the support surface of a wafer chuck.
M Cubed Technologies, Inc.

Electronic system for testing and controlling semiconductor manufacturing equipment

An electronic system includes a memory and a processor. The memory stores first setting data of a manufacturing process condition of semiconductor manufacturing equipment.
Samsung Electronics Co., Ltd.

Method for manufacturing a semiconductor device

A compact and high-reliability semiconductor device is implemented. The bonding wires situated in the vicinity of a gate, and the bonding wires situated in the vicinity of a vent facing to the gate across the center of a semiconductor chip in a molding step have a loop shape falling inwardly of the semiconductor chip, have a weaker pulling force (tension) than those of other bonding wires, and are loosely stretched with a margin.
Renesas Electronics Corporation

Semiconductor module cooling system

A cooling apparatus includes a discrete module and a plastic housing. The discrete module incudes a semiconductor die encapsulated by a mold compound, a plurality of leads electrically connected to the semiconductor die and protruding out of the mold compound and a first cooling plate at least partly uncovered by the mold compound.
Infineon Technologies Ag

Process for the manufacture of a semiconductor element comprising a layer for trapping charges

A process for the manufacture of a semiconductor element includes a stage of rapid heat treatment of a substrate comprising a charge-trapping layer, which is capable of damaging an rf characteristic of the substrate. The rapid heat treatment stage is followed by a healing heat treatment of the substrate between 700° c.
Soitec

Systems and methods for anisotropic material breakthrough

Processing methods may be performed to remove unwanted materials from a substrate, such as a native oxide material. The methods may include forming an inert plasma within a processing region of a processing chamber.
Applied Materials, Inc.

Semiconductor device and manufacturing the same

In a split-gate-type monos memory, increase in a defective rate due to variation in a gate length of a memory gate electrode is prevented, and reliability of a semiconductor device is improved. A first dry etching having a high anisotropic property but a low selection ratio relative to silicon oxide is performed to a silicon film, and then, a second dry etching having a low anisotropic property but a high selection ratio relative to silicon oxide is performed thereto, so that a control gate electrode composed of the silicon film is formed, and then, a sidewall-shaped memory gate electrode is formed on a side surface of the control gate electrode.
Renesas Electronics Corporation

Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate

The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion.
President & Fellows Of Harvard College

Forming recombination centers in a semiconductor device

Disclosed is a method. The method includes implanting recombination center particles into a semiconductor body via at least one contact hole in an insulation layer formed on top of the semiconductor body, forming a contact electrode electrically connected to the semiconductor body in the at least one contact hole, and annealing the semiconductor body to diffuse the recombination center particles in the semiconductor body.
Infineon Technologies Austria Ag

Semiconductor device and fabrication method thereof

A semiconductor device and a fabrication method are provided. The fabrication method includes providing a base substrate including a core region having a first gate structure formed thereon, and an edge region having a second gate structure formed thereon; forming a source/drain doped layer, in the core region of the base substrate on both sides of the first gate structure, and in the edge region of the base substrate on both sides of the second gate structure, respectively, the source/drain doped layer including first ions; and doping the second ions in the source/drain doped layer in the edge region, the second ions having a conductivity type opposite to the first ions..
Semiconductor Manufacturing International (beijing) Corporation

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes: forming a light absorbing layer on a front surface of a semiconductor substrate or in the semiconductor substrate; forming a high concentration layer, in which an impurity concentration is increased, by implanting impurities into the semiconductor substrate; and heating the high concentration layer so as to activate the impurities in the high concentration layer. The formation of the light absorbing layer and the formation of the high concentration layer are performed such that the light absorbing layer and the high concentration layer at least partially overlap each other.
Toyota Jidosha Kabushiki Kaisha

Impurity diffusion agent composition and manufacturing semiconductor substrate

A diffusion agent composition that can be evenly applied onto the whole area of an inner surface of the fine voids, whereby boron can be well and uniformly diffused into the semiconductor substrate even by heating at a low temperature, and a method for manufacturing a semiconductor substrate using the diffusion agent composition. In a diffusion agent composition including an impurity diffusion component, the impurity diffusion component, which can be applied onto a surface of a semiconductor substrate to form a diffusion layer, and which is a boron compound including a nitrogen atom, is used..
Tokyo Ohka Kogyo Co., Ltd.

Method of forming fine patterns of a semiconductor device

A method of forming fine patterns includes forming an upper mask layer on a substrate, forming preliminary mask patterns on the upper mask layer, and forming upper mask patterns by etching the upper mask layer using the preliminary mask patterns as etch masks. Forming the upper mask patterns includes etching the upper mask layer by performing an etching process using an ion beam.
Samsung Electronics Co., Ltd.

Method of manufacturing switching element

A method of manufacturing a switching element includes forming a recessed portion in a surface of a gan semiconductor substrate in which a first n-type semiconductor layer is exposed on the surface, growing a p-type body layer within the recessed portion and on the surface of the gan semiconductor substrate, removing a surface layer portion of the body layer to expose the first n-type semiconductor layer on the surface of the gan semiconductor substrate, and leave the body layer within the recessed portion, forming a second n-type semiconductor layer which is separated from the first n-type semiconductor layer by the body layer and is exposed on the surface of the gan semiconductor substrate, and forming a gate electrode which faces the body layer through an insulating film.. .
Toyota Jidosha Kabushiki Kaisha

Method and system for vertical power devices

A method of forming a semiconductor device includes providing an engineered substrate. The engineered substrate includes a polycrystalline ceramic core, a barrier layer encapsulating the polycrystalline ceramic core, a bonding layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the bonding layer.
Qromis, Inc.

Method of manufacturing semiconductor device

A technique capable of forming a side wall of a gate electrode having high resistance-to-etching and low leakage current is provided. A method of manufacturing a semiconductor device according to the technique includes: (a) loading a substrate into a processing space in a process vessel, the substrate having thereon a gate electrode and an insulating film formed on a side surface of the gate electrode as a side wall; and (b) forming an etching-resistant film containing carbon and nitrogen on a surface of the insulating film by supplying a carbon-containing gas into the processing space..
Hitachi Kokusai Electric Inc.

Method for manufacturing restored substrate and manufacturing light emitting element

A method for manufacturing a restored substrate includes: removing a nitride semiconductor layer from a stacked-layer in which the nitride semiconductor layer has been laminated on a substrate; oxidizing material adhering to the substrate to produce an oxide deposit after the removing of the nitride semiconductor layer from the stacked-layer; and removing the oxide deposit from the substrate. A method for manufacturing a light emitting element includes stacking nitride semiconductor layers including an active layer on the restored substrate obtained by the above method..
Nichia Corporation

Production semiconductor structure and production semiconductor device

There are provided a method for producing a semiconductor structure exhibiting excellent crystallinity by preventing the occurrence of a strain, and a method for producing a semiconductor device. The semiconductor structure production method includes a decomposition layer formation step, a bridging portion formation step, a decomposition step, and a semiconductor layer formation step.
Toyoda Gosei Co., Ltd.

High power low pressure uv bulb with plasma resistant coating

An envelope of an ultraviolet (uv) bulb comprises a tube of uv transmissive material configured to contain a uv emissive material and a plasma resistant coating on an inner surface of the tube wherein the coating has been deposited by atomic layer deposition (ald) and is the only material attached to the inner surface of the tube. The tube can be an endless tube having a circular shape and the coating can be an ald aluminum oxide coating.
Lam Research Corporation

Substrate processing apparatus, manufacturing semiconductor device and non-transitory computer-readable recording medium

Described herein is a technique capable of uniformly processing substrates. According to the technique described herein, there is provided a substrate processing apparatus including: a process chamber where a substrate is processed; a gas supply configured to supply a gas into the process chamber; a plasma generator configured to plasma-excite the gas supplied into the process chamber, the plasma generator including an electrode electrically connected to a high frequency power source; an impedance meter configured to measure an impedance of the plasma generator; a determiner configured to determine an amount of active species generated by the plasma generator based on the impedance measured by the impedance meter; and a controller configured to control the high frequency power source based on the amount of active species determined by the determiner..
Hitachi Kokusai Electric Inc.

Plasma system and fabricating a semiconductor device using the same

A plasma system includes an electrode and an rf power supply unit supplying an rf power to the electrode to generate a plasma on the electrode. The rf power is provided in a pulse having a valley-shaped portion during an on-pulsing interval of the pulse.
Samsung Electronics Co., Ltd.

Photoelectric conversion element and electronic component having the same

In an embodiment, a photoelectric conversion element includes an electrode 1, a counter-electrode 2, and an electrolyte layer 3 interposed between the electrode 1 and the counter electrode 2, wherein: a semiconductor oxide layer 10, as well as semiconductor oxide grains 21 and sensitizing dye 22 fixed via the semiconductor oxide layer 10, are provided on at least a part of a face of the electrode 1 facing the counter-electrode 2; the semiconductor oxide layer 10 has a film structure constituted by grains which are more densely packed than are the fixed semiconductor oxide grains 21; the electrolyte layer 3 contains i3− and i−; and the concentration of i− in the electrolyte layer 3 is 1 to 10 mol/l and is 2 million to 200 million times that of i3−. The photoelectric conversion element is capable of generating a large amount of electricity and high electrical current..
Taiyo Yuden Co., Ltd.

Conductive paste comprising lubricating oils and semiconductor device

The invention relates to a conductive paste, comprising from 50 to 97 wt % of electrically conductive particles, 3 to 50 wt % of an organic medium and 0 to 20 wt % of a glass frit, the organic medium comprising a solvent, wherein the organic medium additionally comprises 10 to 90 wt % of a hydrocarbon-based lubricating oil and 2 to 60 wt % of a polymeric component, each based on the total amount of the organic medium, the polymeric component having a solubility of at least 100 g/kg in the lubricating oil. The invention further relates to a semiconductor device comprising a semiconductor substrate with at least one surface onto which an electrically conductive pattern is printed by using the paste..
Basf Se

Electronic device

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the plurality of first lines and the plurality of second lines; a first test circuit configured to apply a stress pulse to a first selection line coupled to a defective memory cell among the plurality of memory cells during a first test period, in response to a first test control signal, the first selection line including any one of the plurality of first lines; and a control unit configured to generate the first test control signal based on a first test mode signal..
Sk Hynix Inc.

Semiconductor storage device

A semiconductor storage device, that includes: a pre-decoder circuit that decodes an input address signal and generates a first pre-decode signal corresponding to a first address indicated by the address signal; a control signal generation circuit that generates a control signal based on the address signal, the control signal indicating whether the first address is taken as an access target, or whether a second address, which is a next address consecutive from the first address, is taken as the access target; and a selection circuit that, based on the control signal, selects and outputs one of the first pre-decode signal or a second pre-decode signal corresponding to the second address.. .
Lapis Semiconductor Co., Ltd.

Semiconductor device and operating method thereof

A semiconductor device and or method of operating the same may be provided. The semiconductor device may include a pass circuit unit configured to connect global signal lines to signal lines to set voltage levels of the signal lines..
Sk Hynix Inc.

Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and operating

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.. .
Zeno Semiconductor, Inc.

Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and operating

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell.
Zeno Semiconductor, Inc.

Multistage set procedure for phase change memory

Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (pm) to a first temperature for a first period of time.
Intel Corporation

Sense amplifier having offset cancellation

A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first p-type metal-oxide-semiconductor (pmos) transistor, a second pmos transistor, a first n-type metal-oxide-semiconductor (nmos) transistor, and a second nmos transistor.
Samsung Electronics Co., Ltd.

Sub word line driver of semiconductor memory device

A layout structure of a sub word line of a semiconductor memory device is disclosed. A sub word line driver of a semiconductor memory device includes: a plurality of first active regions arranged in a line shape in a first direction; a plurality of second active regions spaced apart from the plurality of first active regions a predetermined distance in a second direction, and arranged in a line shape in the first direction; a first main word line disposed over the first active regions, and formed in a diagonal direction in the first active regions; a second main word line disposed over the second active regions, and formed in a diagonal direction in the second active regions; and a pickup active region disposed between the first main word line and the second main word line..
Sk Hynix Inc.

Semiconductor memory apparatus

A semiconductor memory apparatus includes a driving voltage providing circuit suitable for selectively providing a first driving voltage, a second driving voltage, a third driving voltage, a ground voltage, and a precharge voltage to a first driving line and a second driving line in response to an active signal, a cell characteristic information signal, and a precharge signal. The semiconductor memory apparatus also includes a sense amplifier suitable for operating by being applied with voltages provided from the first and second driving lines..
Sk Hynix Inc.

Semiconductor device verifying signal supplied from outside

Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit.
Longitude Semiconductor S.a.r.l.

Semiconductor memory

A semiconductor memory according to the present invention includes a first discharge circuit for discharging electric charge stored in a pair of bit lines; a second discharge circuit for discharging electric charge stored in the pair of bit lines; and a control part for selectively executing a low-speed discharge mode for operating only the second discharge circuit of the first and second discharge circuits, a high-speed discharge mode for operating both of the first and second discharge circuits, and a stop mode for stopping both of the first and second discharge circuits.. .
Lapis Semiconductor Co., Ltd.

Semiconductor memory device

According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier.
Sk Hynix Inc.

Semiconductor device and semiconductor system

Disclosed are a semiconductor device and a semiconductor system. The semiconductor device includes a command processing circuit for generating a write enable signal and a read enable signal in response to a command, a data strobe signal processing circuit for generating a data strobe signal in response to a clock and the read enable signal or for receiving the data strobe signal in response to the write enable signal and outputting a write data strobe signal, and a data processing circuit for converting analog data into digital data in response to the write data strobe signal and the write enable signal and converting the digital data into the analog data in response to the read enable signal..
Sk Hynix Inc.

Data processing device using neural network, electronic component, and electronic device

To provide a data processing device using a neural network that can suppress increase in the occupied area of a chip. A product-sum operation circuit is formed using a transistor including an oxide semiconductor having an extremely small off-state current.
Semiconductor Energy Laboratory Co., Ltd.

Barcode-reading system

A barcode reader is disclosed. The barcode reader may include a semiconductor package and an optic system.
The Code Corporation

Encryption engine with an undetectable/tamper-proof private key in late node cmos technology

A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory.
International Business Machines Corporation

License managing method, semiconductor device suitable for license management and license managing system

A license managing method including an execution device that executes software and a software storage device coupled to the execution device further includes a license storage device that stores license information indicating the number of licenses for permitting a license of the software, and the license managing method includes the step of license-managing of controlling storage of the software to be downloaded into the software storage device or execution of the software by the execution device based on the license information stored in the license storage device when the software whose license permission is required is downloaded.. .
Renesas Electronics Corporation

Electronic device and fabricating the same

An electronic device includes a semiconductor memory. The semiconductor memory includes first and second lower plugs, a first pad, a second pad, a first lower line, a second lower line, a first insulation pattern, a second insulation pattern, an upper plug, an upper line, and a plurality of variable resistance elements disposed at regions where the first and second lower lines overlap the upper line..
Sk Hynix Inc.

Semiconductor device and fabricating the same

A semiconductor device includes a fin, first to fourth gate electrodes, first and second storage devices, first and second search terminals, and first and second dummy search terminals. The fin extend in a first direction.
Samsung Electronics Co., Ltd.

Dynamic termination circuit, semiconductor apparatus and system including the same

A semiconductor apparatus may include a receiver circuit and a termination circuit. The receiver circuit may be coupled to a receiving node, and configured to receive a signal transmitted through a signal transmission line.
Sk Hynix Inc.

Semiconductor device

The semiconductor device includes a central processing unit, a plurality of functional blocks, and an event controller. Each functional block includes an interrupt factor detection unit that detects an interrupt factor and outputs an event processing request based on the interrupt factor, an event id input unit that receives an input of an event id outputted from the event controller, an event response specification unit that determines whether or not the inputted event id is an event id that requires response and, when the inputted event id is an event id that requires response, specifies response content corresponding to the inputted event id, and an event response processing unit that performs event response processing based on the specified response content..

Cache memory device and semiconductor device

A cache memory device includes: data memory that stores cache data corresponding to data in main memory; tag memory that stores tag information to identify the cache data; an address estimation unit that estimates a look-ahead address to be accessed next; a cache hit determination unit that performs cache hit determination on the look-ahead address, based on the stored tag information; and an access controller that accesses the data memory or the main memory based on the retained cache hit determination result in response to a next access.. .
Renesas Electronics Corporation

Semiconductor memory device including an error correction code circuit

A semiconductor memory device may be disclosed. The semiconductor memory device may include a first memory cell array region and a second memory cell array region, each of which includes memory cells.
Sk Hynix Inc.

Semiconductor device

The aim of the present disclosure is to provide a watchdog timer that can perform a fault diagnosis during the actual use of a semiconductor device. In a semiconductor device provided with a watchdog timer, the watchdog timer includes a counter; a counter control circuit that changes a count value of the counter to a desired value in the refresh period of the count value; and a fault diagnosis module.
Renesas Electronics Corporation

Semiconductor device, security process execution device, and security process execution method

It is possible to prevent a central processing unit and a security processing unit from accessing of a non-volatile memory at the same time. A data flash 13 includes a secure area 31 and a user area 32.
Renesas Electronics Corporation

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.. .
Toshiba Memory Corporation

Array substrate, display panel and display device

An array substrate, a display panel and a display device are disclosed. The array substrate includes a base substrate, and a bias voltage applying circuit and a plurality of semiconductor pressure sensors both disposed at a side of the base substrate.
Xiamen Tianma Micro-electronics Co., Ltd.

Performance boosting method and system of semiconductor device

A performance boosting method of a semiconductor device includes monitoring input of a user and an amount of system usage, generating user system information in response to an event occurring, the user system information including first information and the amount of system usage, the first information regarding input of the user, adaptively determining a performance boosting target value based on the user system information, and boosting an operating frequency according to the performance boosting target value.. .
Samsung Electronics Co., Ltd.

Semiconductor device, operating condition controlling method, and non-transitory computer readable medium

An operating condition is controlled from viewpoints both processing capacity and power consumption. A cpu 11 includes, for example, a plurality of cpu cores 11a to 11d, and configured to such that an operating condition can be varied.
Renesas Electronics Corporation

Low dropout regulator (ldo) circuit

The present disclosure relates to the technical field of semiconductors, and discloses a low dropout regulator (ldo) circuit. The ldo circuit includes a first adjustment pipe, a second adjustment pipe, a first error amplifier, and a second error amplifier.
Semiconductor Manufacturing International (shanghai) Corporation

Mask blank, phase-shift mask and manufacturing semiconductor device

Wherein rm is a ratio of the content of transition metal to the total content of transition metal and silicon in said one layer, and cn is the content of nitrogen in said one layer.. .

Light modulation element

A light modulation element constituted by a substrate type optical waveguide has a mach-zehnder interferometer; and a traveling wave electrode having a signal electrode arranged at least between a first phase modulator and a second phase modulator and electrically connected to both of the first phase modulator and the second phase modulator. A polarity of a semiconductor region of the first phase modulator connected to the signal electrode and a plurality of a semiconductor region of the second phase modulator connected to the signal electrode are different from each other..
Fujikura Ltd.

Backlight unit and liquid crystal display device including the same

A backlight unit for a liquid crystal display device including a liquid crystal panel, includes: a light source including a light-emitting diode (“ed”) which generates and emits light; and a light converting layer between the light source and the liquid crystal panel, spaced apart from the light source, and converting the light from the light source into white light and emitting the white light toward the liquid crystal panel. The light converting layer includes: semiconductor nanocrystals, and a barrier material which restricts penetration of moisture or oxygen..
Samsung Electronics Co., Ltd.

Micro-electro-mechanical device with a movable structure, in particular micromirror, and manufacturing process thereof

A micro-electro-mechanical (mems) device is formed in a first wafer overlying and bonded to a second wafer. The first wafer includes a fixed part, a movable part, and elastic elements that elastically couple the movable part and the fixed part.
Stmicroelectronics S.r.l.

Semiconductor device and manufacturing method thereof

A si photonics device includes: a first semiconductor chip; a second semiconductor chip having a laser diode and mounted on the first semiconductor chip; a third semiconductor chip taking in a laser beam emitted from the laser diode and mounted on the first semiconductor chip; and a resin layer disposed on the first semiconductor chip so as to face the second semiconductor chip. Further, the si photonics device has: a bump electrode connecting the second semiconductor chip and an upper layer electrode pad provided on the resin layer of the first semiconductor chip; and a bump electrode connecting the first semiconductor chip and the third semiconductor chip, and the second semiconductor chip is mounted on the first semiconductor chip via the resin layer..
Renesas Electronics Corporation

Waveguide formation using cmos fabrication techniques

Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (cmos) processing).
Massachusetts Institute Of Technology

Method of making semiconductor x-ray detectors

Disclosed herein is a method of making an apparatus suitable for detecting x-ray, the method comprising: obtaining a substrate having a first surface and a second surface, wherein the substrate comprises an electronics system in or on the substrate, wherein the substrate comprises a plurality of electric contacts are on the first surface; obtaining a first chip comprising a first x-ray absorption layer, wherein the first x-ray absorption layer comprises an electrode; bonding the first chip to the substrate such that the electrode of the first x-ray absorption layer is electrically connected to at least one of the electrical contacts.. .
Shenzhen Xpectvision Technology Co., Ltd.

Systems and methods for sub-pixel location determination at sidewalls and corners of detectors

A radiation detector system is provided that includes a semiconductor detector, plural pixelated anodes, and a side anode. The semiconductor detector has a surface.
General Electric Company

Radiation measuring apparatus and radiation measuring method

A radiation measuring apparatus (20) includes a scatterer detector (10a), an absorber detector (10b) and a processing unit (12). Pixel electrodes (2) of the scatterer detector (10a) and the absorber detector (10b) are arranged such that a distance between centers of two neighbor pixel electrodes (2) is smaller than a mean free path of a recoil electron generated in the compton scattering of an electromagnetic radiation.
Hamamatsu Photonics K.k.

Transmission of wireless signal having information on a local oscillator signal

A semiconductor package having an antenna; and a semiconductor die which is coupled to the antenna and comprises a transmitter configured to transmit wirelessly via the antenna a wireless signal having information on a local oscillator signal to a further semiconductor package comprising a further semiconductor die.. .
Infineon Technologies Ag

Semiconductor device and diagnostic test method

A semiconductor device (1) according to the present invention includes a circuit to be tested (2) having a scan chain, and a first test control device (3) and a second test control device (4) that perform a scan test of the circuit to be tested by using the scan chain. The second test control device (4) performs a second scan test of the circuit to be tested (2), the circuit to be tested (2) gives the first test control device (3) an instruction to perform a first scan test after the second scan test is performed, and the first test control device (3) performs a first scan test of the circuit to be tested (2) in response to an instruction from the circuit to be tested (2)..
Renesas Electric Corporation

Evaluation apparatus of semiconductor device and evaluating semiconductor device using the same

Provided is an evaluation apparatus of a semiconductor device suppressing a discharge occurring in a part of a semiconductor device at a time of evaluating its electrical characteristics. The evaluation apparatus of a semiconductor device includes a stage to support a semiconductor device; a plurality of probes located above the stage; an insulating body having a frame shape to surround the plurality of probes and located above the stage; and an evaluation part injecting a current into the semiconductor device via the plurality of probes.
Mitsubishi Electric Corporation

Ethylenic compound sensor including an organic semiconductor

An ethylene-sensitive sensor is described that includes a power source; an ethylene-sensitive semiconductor component electrically connected to the power source, the semiconducting component comprising a semiconducting organic compound; an input electrode electrically connected to the semiconductor component; and an output electrode electrically connected to the semiconductor component. The semiconductor material is at least partially exposed such that it can be contacted by a vapor.
Johns Hopkins Technology Ventures

Pressure sensor, pressure sensor module, electronic apparatus, and vehicle

A pressure sensor includes a semiconductor substrate having a diaphragm that flexurally deforms by pressurization, a sensor part provided in the diaphragm, an insulating layer provided on the diaphragm, a conducting layer provided on the insulating layer, and a drive circuit that supplies a predetermined potential so that the drive voltage may be applied to the sensor part, wherein the conducting layer is set at a same potential as the predetermined potential or a potential larger than the predetermined potential.. .
Seiko Epson Corporation

Edge-coupled semiconductor photodetector

A device is disclosed for monitoring power from a laser diode. The device includes a substrate having a top surface and a first facet perpendicular to the top surface through which light enters the substrate.
Global Communications Semiconductors, Llc

Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium

A method of manufacturing a semiconductor device includes: (a) processing a substrate accommodated in a process chamber by supplying an inert gas into a tank storing a precursor via a first supply pipe, supplying the precursor from an interior of the tank into the process chamber via a second supply pipe connected to the first supply pipe by a connection pipe, and exhausting the precursor from the interior of the process chamber; and (b) purging an interior of the first supply pipe, an interior of the connection pipe and an interior of the second supply pipe by alternately repeating: supplying a heated inert gas into the first supply pipe, the connection pipe and the second supply pipe, and exhausting the heated inert gas; and vacuumizing the interior of the first supply pipe, the interior of the connection pipe, and the interior of the second supply pipe.. .
Hitachi Kokusai Electric Inc.

Novel self-photosensitized nonphotosynthetic microorganism

The present invention provides for a genetically modified microorganism capable of photosynthesizing an organic compound from carbon dioxide, wherein the microorganism comprises a semiconductor nanoparticle on the surface of the microorganism.. .
The Regents Of The University Of California

Composition for etching

The disclosure is related to a composition for etching, a method for manufacturing the composition, and a method for fabricating a semiconductor using the same. The composition may include a first inorganic acid, at least one of silane inorganic acid salts produced by reaction between a second inorganic acid and a silane compound, and a solvent.
Soulbrain Co., Ltd.

Process for preparing a quantum dot, a quantum dot prepared therefrom, and an electronic device including the same

A process for preparing a quantum dot of a core-shell structure including obtaining a first mixture including first precursor including a first metal, a ligand compound, and a solvent; adding a second precursor and a particle including a first semiconductor nanocrystal to the first mixture to obtain a second mixture; and heating the second mixture up to a reaction temperature and performing a reaction between the first precursor and the second precursor to form a layer of a shell including a crystalline or amorphous material, during formation of the layer of the shell or after formation of the layer of the shell, wherein the process includes adding an organic solution including an ammonium fluorinated salt including a solid salt having a melting point of greater than or equal to about 110° c. To the second mixture..
Samsung Sdi Co., Ltd.

Composite material containing graphene

In one aspect, a composite material is disclosed herein that includes graphene platelets dispersed in a matrix. In some cases, the graphene platelets are randomly oriented within the matrix.
The Boeing Company

Vehicular lamp

A converter controller controls a switching converter. A current detection circuit generates a current detection signal vcs that corresponds to a coil current il of the switching converter.
Koito Manufacturing Co., Ltd

Piezoelectric micro-machined ultrasonic transducer (pmut) and manufacturing the pmut

A piezoelectric micro-machined ultrasonic transducer (pmut) comprising: a semiconductor body having a first cavity and a membrane, which is suspended over the first cavity and faces a front side of the semiconductor body; and a piezoelectric transducer assembly extending at least in part on the membrane, which may be actuated for generating a deflection of the membrane. A second cavity extends buried in a peripheral region of the membrane and delimits a central region of the membrane.
Stmicroelectronics S.r.l.

Imaging apparatus

A tomographic imaging system includes a source configured to irradiate an object; a first image sensor including a first semiconductor substrate having a first face upon which a monolithic first pixel array is located; and a gantry configured to hold the first image sensor and rotate the image sensor around the object about a first rotation axis, the first pixel array including a first plurality of pixels configured to receive light that travels through or from the object based on the irradiation, the first plurality of pixels of the first pixel array being arranged in one or more rows and a plurality of columns such that, a total number of the one or more rows is less than a total number of the plurality of columns, and the one or more rows extend in a first direction, the first image sensor being arranged such that an angle between the first direction and a second direction is greater than 45 degrees and equal to or less than 90 degrees, the second direction being a direction parallel to the rotation axis or a direction in which the object moves during analysis of the object by the imaging system.. .

Semiconductor processing apparatus with a ceramic-comprising surface which exhibits fracture toughness and halogen plasma resistance

A solid solution-comprising ceramic article useful in semiconductor processing, which article may be in the form of a solid, bulk ceramic, or may be in the form of a substrate having a ceramic coating of the same composition as the bulk ceramic material on at least one outer surface. The ceramic article is resistant to erosion by halogen-containing plasmas and provides advantageous mechanical properties.
Sunglory Beheer B.v.

Dai Nippon Printing Co., Ltd.

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Commissariat A L'energie Atomique Et Aux Energies Alternatives

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Commissariat A L'energie Atomique Et Aux Energies Alternatives

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International Business Machines Corporation

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Commissariat A L'energie Atomique Et Aux Energies Alternatives

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Semiconductor light emitting device growing active layer on textured surface

In accordance with embodiments of the invention, at least partial strain relief in a light emitting layer of a iii-nitride light emitting device is provided by configuring the surface on which at least one layer of the device grows such that the layer expands laterally and thus at least partially relaxes. This layer is referred to as the strain-relieved layer.
Lumileds Llc

Semiconductor photodiode

A semiconductor photodiode, including a light-absorbing layer; an optical waveguide via which light can evanescently be coupled into the light-absorbing layer, and a doped contact layer arranged between the light-absorbing layer and the optical waveguide. The optical waveguide at least sectionally has a doping which produces a diffusion barrier counteracting a diffusion of dopant of the contact layer into the optical waveguide..
Fraunhofer-gesellschaft Zur Förderung Der Angewandten Forschung E.v.

Interdigitated back contact metal-insulator-semiconductor solar cell with printed oxide tunnel junctions

Screen-printable metallization pastes for forming thin oxide tunnel junctions on the back-side surface of solar cells are disclosed. Interdigitated metal contacts can be deposited on the oxide tunnel junctions to provide all-back metal contact to a solar cell..
Zhejiang Kaiying New Materials Co., Ltd.

Double layered transparent conductive oxide for reduced schottky barrier in photovoltaic devices

A device and method for fabricating a photovoltaic device includes forming a double layer transparent conductive oxide on a transparent substrate. The double layer transparent conductive oxide includes forming a doped electrode layer on the substrate, and forming a buffer layer on the doped electrode layer.
Bay Zu Precision Co., Ltd.

Solar cell and solar cell module

Provided is a solar cell that includes: a semiconductor substrate on which at least pn junctions are formed; a multiplicity of finger electrodes that are formed in a comb-like shape on at least one surface of the semiconductor substrate; and a plurality of bus bar electrodes that are arranged so as to be orthogonal to the lengthwise direction of the finger electrodes and are connected with the finger electrodes. This solar cell is configured so that the finger electrodes connected with one of the bus bar electrodes are separated from the finger electrodes connected with another bus bar electrode that is arranged so as to be parallel to this one of the bus bar electrodes, and ends in the lengthwise direction of adjacent two or more of the finger electrodes connected with each bus bar electrode are electrically connected with one another by auxiliary electrodes.
Shin-etsu Chemical Co., Ltd.

Solar cell and organic semiconductor material

The present invention aims to provide a solar cell having high photoelectric conversion efficiency and excellent high-temperature durability, and an organic semiconductor material. The present invention relates to a solar cell having: an electrode; a counter electrode; a photoelectric conversion layer disposed between the electrode and the counter electrode; and a hole transport layer disposed between the photoelectric conversion layer and the counter electrode, the hole transport layer containing an ionic compound that contains an organic semiconductor cation and a fluorine-containing compound anion, the hole transport layer having a metal concentration of 1,000 ppm or lower..
Sekisui Chemical Co., Ltd.

Solar cells having differentiated p-type and n-type architectures

Methods of fabricating solar cell emitter regions with differentiated p-type and n-type region architectures, and the resulting solar cells, are described herein. In an example, a solar cell includes an n-type semiconductor substrate having a light-receiving surface and a back surface.
Sunpower Corporation

Semiconductor device

A semiconductor device includes first to fourth semiconductor regions, and first and second electrodes. The second semiconductor region is selectively disposed in a surface layer of one main surface of the first semiconductor region.
Fuji Electric Co., Ltd.

Semiconductor device including zener diode and manufacturing thereof

A semiconductor device, including an insulator formed on a top surface of a semiconductor substrate, a semiconductor layer, containing a first region of a first conductivity type, formed on the insulator layer, wherein the first region is a p+ region or an n+ region, a second region of a second conductivity type in direct contact with the first region and forming a p-n junction with the first region, wherein the p-n junction comprises a first portion parallel to the top surface of the semiconductor substrate, and the second region is the semiconductor substrate and partially covered by the semiconductor layer, a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region. .
Vanguard International Semiconductor Corporation

Semiconductor device and manufacturing method thereof

A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions.
Taiwan Semiconductor Manufacturing Co., Ltd.

2-d material transistor with vertical structure

Semiconductor structures including two-dimensional (2-d) materials and methods of manufacture thereof are described. By implementing 2-d materials in transistor gate architectures such as field-effect transistors (fets), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-d materials such as graphene, transition metal dichalcogenides (tmds), or phosphorene..
Taiwan Semiconductor Manufacturing Co., Ltd.

Vertical transistor including controlled gate length and a self-aligned junction

A vertical transistor includes a gate structure interposed between a proximate spacer doped with a first dopant-type and a distal spacer doped with the first dopant-type. The proximate spacer is formed on an upper surface of a semiconductor substrate.
International Business Machines Corporation

Semiconductor device

In a semiconductor device using a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. The semiconductor device includes a gate electrode over an insulating surface; an oxide semiconductor film overlapping with the gate electrode; a gate insulating film that is between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film; a protective film in contact with a surface of the oxide semiconductor film that is an opposite side of a surface in contact with the gate insulating film; and a pair of electrodes in contact with the oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor structure including one or more nonvolatile memory cells and the formation thereof

A semiconductor structure includes a support substrate including a semiconductor material, a buried insulation layer positioned above the support substrate, a semiconductor layer positioned above the buried insulation layer, the semiconductor layer having an upper surface and a lower surface, the lower surface being positioned on the buried insulation layer, and at least one nonvolatile memory cell. The nonvolatile memory cell includes a channel region, a front gate structure, a doped back gate region and a charge storage material.
Globalfoundries Inc.

Oxide semiconductor film and semiconductor device

To provide an oxide semiconductor film having stable electric conductivity and a highly reliable semiconductor device having stable electric characteristics by using the oxide semiconductor film. The oxide semiconductor film contains indium (in), gallium (ga), and zinc (zn) and includes a c-axis-aligned crystalline region aligned in the direction parallel to a normal vector of a surface where the oxide semiconductor film is formed.
Semiconductor Energy Laboratory Co., Ltd.

Thin-film transistor and manufacturing method thereof

The invention relates to a thin-film transistor and a manufacturing method thereof. The manufacturing method of the thin-film transistor includes the following steps: an insulating layer is formed to cover a gate on a substrate; a semiconductor pattern having a first region and a second region is formed on the insulating layer; a plurality of island patterns is formed, wherein at least a portion of the plurality of island patterns is disposed on the semiconductor pattern, and the plurality of island patterns is separated from one another by a gap; and a source and a drain are formed to cover a portion of the plurality of island patterns and fill the gaps to respectively be electrically connected to the first region and the second region of the semiconductor pattern..
Chunghwa Picture Tubes, Ltd.

Metal oxide thin-film transistor and manufacturing the same

The present invention relates to a metal oxide thin-film transistor and manufacturing for the same. The thin-film transistor includes a substrate; a source electrode, a barrier layer and a drain electrode which are sequentially formed on the substrate; and a semiconductor active layer formed on side surfaces of the source electrode and the drain electrode; wherein, the semiconductor active layer is respectively connected with the source electrode and the drain electrode.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Semiconductor device and method

A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure.
Taiwan Semiconductor Manufacturing Company, Ltd.

High doped iii-v source/drain junctions for field effect transistors

A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a iii-v material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped iii-v material between doped iii-v materials, the doped iii-v materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.. .
Stmicroelectronics, Inc.

Finfet structures and methods of forming the same

A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device and fabricating the same

A substrate includes a pattern forming region and a peripheral region. A first strain relaxed buffer layer is disposed on the pattern forming region of the substrate.
Samsung Electronics Co., Ltd.

Device with diffusion blocking layer in source/drain region

One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region.
Globalfoundries Inc.

Soi finfet fins with recessed fins and epitaxy in source drain region

Fabrication method for a semiconductor device and structure are provided, which includes: providing an isolation layer at least partially disposed adjacent to at least one sidewall of a fin structure extended above a substrate structure, the fin structure including a channel region; recessing an exposed portion of the fin structure to define a residual stress to be induced into the channel region of the fin structure, wherein upper surfaces of a recessed fin portion and the isolation layer are coplanar with each other; and epitaxially growing a semiconductor material from the recessed exposed portion of the fin structure to form at least one of a source region and a drain region of the semiconductor device.. .
Globalfoundries Inc.

Semiconductor epitaxy bordering isolation structure

A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation..
Taiwan Semiconductor Manufacturing Co., Ltd.

Method for making a semiconductor device with a compressive stressed channel

H) making a gate.. .

Double-gate vertical transistor semiconductor device

A semiconductor device is disclosed that includes a substrate and at least a first, second, third, and fourth vertical transistor supported by the substrate. Each transistor comprises a vertical channel, a polarity gate electrode forming a polarity gate adapted to act on a first portion of the channel to affect a polarity of the channel, and a control gate electrode forming a control gate adapted to act on a second portion of the channel to control the electrical conductivity of the channel.
Katholieke Universiteit Leuven, Ku Leuven R&d

Semiconductor device and manufacturing the same

A recessed portion is formed in a top surface of an isolation insulation film filling an isolation trench between a p+ source region and a p+ drain region. A p− drift region is located below the isolation trench and connected to the p+ drain region.
Renesas Electronics Corporation

Ldmos transistor with segmented gate dielectric layer

A power transistor is provided with at least one transistor finger that lies within a semiconductor material. The gate oxide is segmented into a set of segments with thick field oxide between each segment in order to reduce gate capacitance and thereby improve a resistance times gate charge figure of merit..
Texas Instruments Incorporated

Vertical double diffusion metal-oxide-semiconductor power device with high voltage start-up unit

A vertical double diffusion metal-oxide-semiconductor power device with high voltage start-up unit includes a vertical double diffusion metal-oxide-semiconductor power transistor and the high voltage start-up unit. The vertical double diffusion metal-oxide-semiconductor power transistor includes a first metal layer, a substrate layer with first conductivity type, an epitaxy layer with first conductivity type, a second metal layer, and a plurality of polysilicon layers.
Leadtrend Technology Corp.

Semiconductor device including auxiliary structure

One or more embodiments disclose a semiconductor device that includes a trench extending into a drift zone of a semiconductor body from a surface of the semiconductor body in a first direction; a dielectric structure in the trench; a gate electrode in the dielectric structure; a body region of a first conductivity type other than a second conductivity type of the drift zone; and an auxiliary structure of the second conductivity type adjoining the drift zone, the body region and the dielectric structure, wherein the auxiliary structure extends outwardly from the trench in a second direction, the second direction orthogonal to the first direction, and in the second direction, a first length of the auxiliary structure is larger than a second length of the trench.. .
Sanken Electric Co., Ltd.

Semiconductor device comprising a plurality of transistor cells and manufacturing method

A semiconductor device comprises a plurality of transistor cells. Each one of the plurality of transistor cells comprises a trench extending into a drift zone of a semiconductor body from a first surface, the drift zone being of a first conductivity type.
Infineon Technologies Austria Ag

Semiconductor substrate and semiconductor device

A semiconductor substrate and a semiconductor device are disclosed. The semiconductor substrate includes a base layer, a buffer layer disposed on the base layer, a channel layer disposed on the buffer layer, a barrier layer disposed on the channel layer, and a buried field plate region embedded in the channel layer.
Nuvoton Technology Corporation

Semiconductor device and manufacturing the same

A semiconductor device includes a substrate, a channel layer, a barrier layer, a recess, a charge trapping layer, a ferroelectric material layer, a gate, a source and a drain. The channel layer is disposed on the substrate.
National Chiao Tung University

Semiconductor component with protrusion propagation body and corresponding methods of manufacture

A semiconductor structure includes a substrate, a iii-nitride intermediate stack including the protrusion propagation body situated over the substrate, a transition body over the iii-nitride intermediate stack, a iii-nitride buffer layer situated over the transition body, and a iii-nitride device fabricated over the group iii-v buffer layer. The protrusion propagation body includes at least a protrusion generating layer and two or more protrusion spreading multilayers..
Infineon Technologies Americas Corp.

Bipolar junction transistors with a combined vertical-lateral architecture

Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base.
Globalfoundries Inc.

Symmetrical lateral bipolar junction transistor and use of same in characterizing and protecting transistors

A symmetrical lateral bipolar junction transistor (slbjt) is provided. The slbjt includes a p-type semiconductor substrate, a n-type well, an emitter of a slbjt situated in the n-type well, a base of the slbjt situated in the n-type well and spaced from the emitter by a distance on one side of the base, a collector of the slbjt situated in the n-type well and spaced from the base by the distance on an opposite side of the base, and an electrical connection to the substrate outside the n-type well.
Globalfoundries Inc.

Method of manufacturing oxide thin film transistor

There is provided a method of manufacturing an oxide thin film transistor (tft). The method includes forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer including a channel layer on the gate insulating layer, forming a source electrode and a drain electrode separated from each other on the oxide semiconductor layer, first plasma processing the substrate on which the source electrode and the drain electrode are formed at a carbon (c) atmosphere, secondly plasma processing the substrate at a nitrogen oxide atmosphere, and sequentially forming a first protective layer and a second protective layer on the substrate..
Samsung Display Co., Ltd.

Method of manufacturing thin film transistor

The present application discloses a method of manufacturing a thin film transistor, including following steps: forming a gate electrode on the top surface of the substrate; depositing a gate insulating layer, a semiconductor material and an etching stop layer sequentially on the gate electrode; patterning the etching stop layer by a first mask to form a stopper; depositing a second metal layer; using a second mask and a photoresist to form a source electrode region, a drain electrode region and a channel region on the surface of the second metal layer; etching the periphery region of the source electrode region, the drain electrode region and the channel region to expose the gate insulating layer; removing the photoresist and etching the second metal layer within the channel, and form a source electrode and a drain electrode by the remaining second metal layer; and irradiating the bottom of the substrate.. .
Wuhan China Star Optoelectronics Technology Co., Ltd.

Shallow, abrupt and highly activated tin extension implant junction

Embodiments are directed to a method of forming a semiconductor device and resulting structures having a shallow, abrupt and highly activated tin (sn) extension implant junction. The method includes forming a semiconductor fin on a substrate.
International Business Machines Corporation

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method of fabricating a semiconductor device

A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide.
Taiwan Semiconductor Manufacturing Co., Ltd.

Vertical power mosfet and methods for forming the same

A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode.
Taiwan Semiconductor Manufacturing Company, Ltd.

Method for making a semiconductor device with self-aligned inner spacers

F) making a gate between the outer spacers and between the inner spacers and covering the channel.. .

Method for producing a semiconductor device with self-aligned internal spacers

Producing a gate electrically insulated from the source/drain by the external and internal spacers.. .

3d capacitor and manufacturing same

A three-dimensional (3d) capacitor includes a semiconductor substrate; a fin structure including one or more fins formed on the semiconductor substrate; an insulator material formed between each of the one or more fins; a dielectric layer formed on a first portion of the fin structure; a first electrode formed on the dielectric layer; spacers formed on sidewalls of the first electrode; and a second electrode formed on a second portion of the fin structure. The first and second portions are different.
Taiwan Semiconductor Manufacturing Company, Ltd.

Method for making a semiconductor device with nanowire and aligned external and internal spacers

H) making of an internal spacer within the cavities.. .

Method for manufacturing semiconductor structure with multi spacers

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method for providing a low-k spacer

A method for forming semiconductor devices with spacers is provided. Sico spacers are formed on sides of features.
Lam Research Corporation

Bi-layer metal deposition in silicide formation

A method includes performing a first sputtering to form a first metal film on a surface of a semiconductor region. The first sputtering is performed using a first ion energy.
Taiwan Semiconductor Manufacturing Company, Ltd.

Method for avoiding il regrown in a hkmg process

The present disclosure addresses and solves the current problem of oxygen accumulation in il after an hkmg stack is formed. A fabrication method is provided for fabricating high-k/metal gate semiconductor device by forming at least one titanium (ti) layer between multiple hk layers.
Shanghai Huali Microelectronics Corporation

Binary metal oxide based interlayer for high mobility channels

A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer..
Ulvac, Inc.

Semiconductor device for compensating internal delay, methods thereof, and data processing system having the same.

A method of manufacturing a field effect transistor using a gate last process includes providing the field effect transistor which includes a high-k dielectric formed between an elevated source and an elevated drain and surrounding a metal gate, and performing a chemical mechanical planarization (cmp) process on an upper surface of the elevated source, and in which a height of the metal gate becomes lower than a height of the elevated source according to the cmp process.. .
Samsung Electronics Co., Ltd.

Semiconductor devices and methods for forming semiconductor devices

A semiconductor device includes a transistor doping region of a vertical transistor structure arranged in a semiconductor substrate. Additionally, the semiconductor device includes a graphene layer portion located adjacent to at least a portion of the transistor doping region at a surface of the semiconductor substrate.
Infineon Technologies Ag

Semiconductor device

A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose fermi level is closer to a fermi level of the semiconductor region than a fermi level of si in at least a portion contiguous to the insulating film..
Rohm Co., Ltd.

Fin-type semiconductor device

Fin-type semiconductor device is provided. The semiconductor device includes: a semiconductor substrate and an insulating layer on sidewalls of the plurality of fins.
Semiconductor Manufacturing International (shanghai) Corporation

Forming silicon oxide layers by radical oxidation and semiconductor device with silicon oxide layer

A body structure and a drift zone are formed in a semiconductor layer, wherein the body structure and the drift zone form a first pn junction. A silicon nitride layer is formed on the semiconductor layer.
Infineon Technologies Ag

Insulated gate switching device and manufacturing the same

A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first sic semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second sic semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region..
Denso Corporation

Semiconductor device and manufacturing the same

A method of manufacturing a semiconductor device includes preparing a layer, including columns, the columns extend a first direction parallel to the surface of the layer, the columns are arranged at intervals, interdigitally sandwiching other columns so as to implement a superjunction structure so the columns and the other columns are side by side; forming well regions in the layer; forming source regions in the well regions; forming an insulating film on the well regions; and forming gate electrodes on the gate insulating film, the gate electrodes bridging corresponding source regions in neighboring well regions, a temperature detection diode at an area in the gate electrodes, one column has a first width in a second direction, the temperature detection diode has a second width in the second direction, and the first width equal to the second width, and the second direction is perpendicular to the first direction.. .
Fuji Electric Co., Ltd.

Silicon carbide semiconductor device and manufacturing the silicon carbide semiconductor device

A vertical mosfet of a trench gate structure includes an n−-type drift layer and a p+-type base layer formed by epitaxial growth. The vertical mosfet includes a trench that penetrates the n−-type drift layer and the p+-type base layer.
National Institute Of Advanced Industrial Science And Technology

Trench semiconductor device layout configurations

A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material..
Sanken Electric Co., Ltd.

Memory arrays

The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions.
Micron Technology , Inc.

Semiconductor device and manufacturing method thereof

A method includes forming a crown structure over a substrate; forming fins in the crown structure; forming an intra-device isolation region between the fins and forming inter-device isolation regions on opposing sides of the crown structure; forming a gate structure over the fins; forming a dielectric layer that extends continuously over the inter-device isolation regions, the fins and the intra-device isolation region; performing an etching process to reduce a thickness of the dielectric layer, where after the etching process, upper surfaces of the inter-device isolation regions and upper surfaces of the fins are exposed while an upper surface of the intra-device isolation region is covered by a remaining portion of the dielectric layer; and forming an epitaxial structure over the exposed upper surfaces of the fins, where after the epitaxial structure is formed, there is a void between the epitaxial structure and the intra-device isolation region.. .
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device and manufacturing the same

A semiconductor device including a substrate with a first trench, a first insulation liner on inner flanks of the first trench, and a second insulation liner on inner flanks of a first sub trench, the first insulation trench defined by the first insulation liner in the first trench, a top level of the second insulation liner that adjoins the inner flanks of the first sub trench in a direction perpendicular to a top surface of the substrate being different from the top surface of the substrate outside the first trench, may be provided.. .
Samsung Electronics Co., Ltd.

Power semiconductor device and method therefor

An rc-igbt according to the invention includes a high electric field cell formed in a region surrounded by an igbt cell or in a region surrounded by a diode cell, and an n+ diffusion layer formed at a position opposed to the high electric field cell, the position being on a second main surface of an n− type drift layer. The high electric field cell has a higher maximum electric field intensity generated when a voltage is applied between main terminals than maximum electric field intensities of the igbt cell, the diode cell, and a withstand voltage holding structure.
Mitsubishi Electric Corporation

Method of manufacturing semiconductor device

An impurity of a second conductivity type is selectively doped in a surface of a semiconductor substrate of a first conductivity type to form doped regions. A portion of a surface of the doped regions is covered by a heat insulating film.
Fuji Electric Co., Ltd.

Method of manufacturing switching element

A method of manufacturing a switching element is provided. The method including: preparing a semiconductor substrate which includes an n-type drain region, a p-type body region, and a trench penetrating the body region and reaching the drain region; and forming a lateral surface p-type region extending along a lateral surface of the trench below the body region by heating the semiconductor substrate so as to make a part of the body region flow into the trench.
Toyota Jidosha Kabushiki Kaisha

Semiconductor device

The semiconductor device includes: a semiconductor layer in which a trench is formed having a side surface and a bottom surface; a second conductivity-type layer formed on the semiconductor layer on the side surface and the bottom surface of the trench; a first conductivity-type layer formed on the semiconductor layer so as to contact the second conductivity-type layer; a first electrode electrically connected to the first conductivity-type layer; a second electrode embedded in the trench and electrically connected to the second conductivity-type layer; and a barrier-forming layer which is arranged between the second electrode and the side surface of the trench and which, between said barrier-forming layer and the second conductivity-type layer, forms a potential barrier higher than the potential barrier between the second conductivity-type layer and the second electrode.. .
Rohm Co., Ltd.

Semiconductor device and manufacturing semiconductor device

Provided is a semiconductor device including at least two isolation trench portions; a mesa region that is provided between the at least two isolation trench portions and includes a source region having a first conduction type, a base region having a second conduction type and at least a portion thereof provided below the source region, and a gate trench portion; and a contact layer that is an epitaxial layer provided at least in contact with side portions of the mesa region and bottom portions of the isolation trench portions positioned lower than the gate trench portion, and having a second-conduction-type impurity concentration higher than that of the base region, wherein the same impurities as in the contact layer are present in the source region, or the contact layer is provided higher than the source region.. .
Fuji Electric Co., Ltd.

Semiconductor devices, methods of manufacture thereof, and capacitors

Semiconductor devices, methods of manufacture thereof, and capacitors are disclosed. In some embodiments, a semiconductor device includes a first capacitor and a protection device coupled in series with the first capacitor.
Taiwan Semiconductor Manufacturing Company, Ltd.

Inductor element, inductor element manufacturing method, and semiconductor device with inductor element mounted thereon

An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer.. .
Renesas Electronics Corporation

Organic light emitting diode display

An organic light emitting diode display includes a substrate, a scan line on the substrate for transferring a scan signal, a data line crossing the scan line and for transferring a data signal, a driving voltage line crossing the scan line and for transferring a driving voltage, a switching thin film transistor coupled to the scan line and the data line, a driving thin film transistor coupled to a switching drain electrode of the switching thin film transistor, and an organic light emitting diode (oled) coupled to a driving drain electrode of the driving thin film transistor, wherein a driving semiconductor layer of the driving thin film transistor is bent and in a plane substantially parallel to the substrate.. .
Samsung Display Co., Ltd.

Organic light-emitting diode display

An organic light-emitting diode display is disclosed. The display includes a semiconductor layer formed over a substrate, a scan line formed over the semiconductor layer and configured to provide a scan signal, and a light emission control line formed over the semiconductor layer and configured to provide a light emission control signal.
Samsung Display Co., Ltd.

Substrate for display device and display device including the same

A substrate for a display device and a display device including the same are disclosed. The substrate includes a first thin-film transistor including an oxide semiconductor layer, a second thin-film transistor spaced apart from the first thin-film transistor and including a polycrystalline semiconductor layer, and a storage capacitor including at least two storage electrodes.
Lg Display Co., Ltd.

Semiconductor device and manufacturing semiconductor device

A semiconductor device includes: a printed substrate having a through hole from an upper face to a lower face thereof; a first semiconductor element mounted on the printed substrate; an interposer mounted on the upper face of the printed substrate; a second semiconductor element adjacent to the interposer and arranged to overlap with the through hole; and a bonding wire coupling a first pad to a second pad, the first pad being on an upper face of the interposer and being positioned on the second semiconductor element side, the second pad being on an upper face of the second semiconductor element and being positioned on the interposer side, wherein the interposer has an edge face protruding with respect to a wall face of the through hole of the printed substrate toward the second semiconductor element, and the edge face faces with an edge face of the second semiconductor element.. .
Sumitomo Electric Industries, Ltd.

Semiconductor memory device

According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction.
Toshiba Memory Corporation

Resistive memory and manufacturing the same

A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (rram) elements.
United Microelectronics Corp.

Light emitting device

A light emitting device includes a substrate and a plurality of light emitting cells disposed on the substrate. Each light emitting cell includes a first semiconductor layer and a second semiconductor layer, an active layer between the first and the second semiconductors, a conductive material on the second semiconductor layer, an inclined surface, a first insulation layer overlaps each light emitting cell, an electrically conductive material overlaps the first insulation layer to couple two of the plurality of light emitting cells, and a second insulation layer overlaps the electrically conductive material.
Seoul Viosys Co., Ltd.

Semiconductor structure and manufacturing semiconductor structure

A method for manufacturing a semiconductor structure includes the following steps. A first carrier is adhered to a first surface of a wafer by a first temporary bonding layer.
Xintec Inc.

Semiconductor device manufacturing method

A method includes a first process in which a first wiring is provided on a surface of a semiconductor substrate; a second process in which a light transmitting substrate is attached to the surface; a third process in which the semiconductor substrate is thinned so that the thickness of the semiconductor substrate is smaller than the thickness of the light transmitting substrate; a fourth process in which a through hole is formed in the semiconductor substrate; a fifth process in which a dip coating method is performed using a resin material and thus a resin insulating layer is provided; a sixth process in which a contact hole is formed in the resin insulating layer; and a seventh process in which a second wiring is provided on a surface of the resin insulating layer, and the first wiring and the second wiring are electrically connected via a contact hole.. .
Hamamatsu Photonics K.k.

Solid-state imaging device and producing solid-state imaging device

A solid-state imaging device includes a sensor including an impurity diffusion layer provided in a surface layer of a semiconductor substrate; and an oxide insulating film containing carbon, the oxide insulating film being provided on the sensor.. .
Sony Corporation

Image sensor and manufacturing method therefor

The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The method includes: providing a semiconductor structure, where the semiconductor structure includes: a semiconductor substrate, and a first active region located on the semiconductor substrate, the first active region including a first doped region and a second doped region abutting against the first doped region, and the second doped region being located at an upper surface of the first active region; forming a semiconductor layer on an upper surface of the second doped region; and forming a contact connected to the semiconductor layer.
Semiconductor Manufacturing International (beijing) Corporation

Imaging device and imaging unit

An imaging device having a first surface on which light is incident and a second surface on an opposite side of the first surface, includes a photoelectric conversion section including semiconductors having a same conductivity type, in which an impurity concentration on the second surface side is higher than an impurity concentration on the first surface side.. .
Nikon Corporation

Photosensitive imaging devices and associated methods

Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction.
Sionyx, Llc

Germanium-silicon light sensing apparatus

A method for fabricating an image sensor array having a first group of photodiodes for detecting light at visible wavelengths a second group of photodiodes for detecting light at infrared or near-infrared wavelengths, the method including forming a germanium-silicon layer for the second group of photodiodes on a first semiconductor donor wafer; defining a first interconnect layer on the germanium-silicon layer; defining integrated circuitry for controlling pixels of the image sensor array on a semiconductor carrier wafer; defining a second interconnect layer on the semiconductor carrier wafer; bonding the first interconnect layer with the second interconnect layer; defining the pixels of an image sensor array on a second semiconductor donor wafer; defining a third interconnect layer on the image sensor array; and bonding the third interconnect layer with the germanium-silicon layer.. .
Artilux Corporation

Imaging element, electronic device, manufacturing apparatus, and manufacturing method

This technology relates to an imaging element and an electronic device for reducing any increase in pixel size while lessening any drop in image quality, and to a manufacturing apparatus and a manufacturing method for manufacturing the imaging element and the electronic device. For example, an imaging element includes an element isolation region with an insulator to penetrate a semiconductor layer having transistors formed in a pixel including a photoelectric conversion section.
Sony Corporation

Image sensor and manufacturing method therefor

The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The image sensor includes: a semiconductor substrate; a first active region located on the semiconductor substrate; a doped semiconductor layer located on the first active region; and a contact located on the semiconductor layer, where the first active region includes: a first doped region and a second doped region abutting against the first doped region, wherein the second doped region is located at an upper surface of the first active region, and wherein the second doped region is formed by dopants in the semiconductor layer that are annealed to be diffused to a surface layer of the first doped region.
Semiconductor Manufacturing International (beijing) Corporation

Transistor array panel and display device including the same

A transistor array panel according to an exemplary embodiment includes: a substrate; a first buffer layer positioned on the substrate; and a first transistor and a second transistor positioned on the substrate and separated from each other, wherein the first transistor includes a polycrystalline semiconductor positioned on the substrate, and a first gate electrode overlapping the polycrystalline semiconductor, the second transistor includes an oxide semiconductor positioned on the first buffer layer, and a second gate electrode overlapping the oxide semiconductor, the first buffer layer covers the first gate electrode, and the first buffer layer includes a silicon oxide.. .
Samsung Display Co., Ltd.

Semiconductor device, display system, and electronic device

A novel semiconductor device or display device is provided. A semiconductor substrate is used as a substrate of a display portion and a transistor in the display portion is formed using the semiconductor substrate.
Semiconductor Energy Laboratory Co., Ltd.

Array substrate, manufacturing method thereof and display device

An array substrate, a manufacturing method thereof and a display device are provided. The array substrate includes a display region and a goa region.
Chongqing Boe Optoelectronics Technology Co., Ltd.

Transistor array panel and manufacturing method thereof

A transistor array panel includes a transistor which includes a gate electrode, a semiconductor layer on the gate electrode, and a source electrode and a drain electrode on the semiconductor layer. The semiconductor layer includes a first portion overlapping the source electrode, a second portion overlapping the drain electrode, and a third portion between the first portion and the second portion.
Samsung Display Co., Ltd.

Semiconductor device and fabricating the same

A semiconductor device includes a base substrate, a buried insulating film on the base substrate, a first semiconductor substrate pattern on the buried insulating film, a second semiconductor substrate pattern on the buried insulating film, the second semiconductor substrate pattern being spaced apart from the first semiconductor substrate pattern, a first device pattern on the first semiconductor substrate pattern, a second device pattern on the second semiconductor substrate pattern, the first and second device patterns having different characteristics from each other, an isolating trench between the first semiconductor substrate pattern and the second semiconductor substrate pattern, the isolating trench extending only partially into the buried insulating film, and a lower interlayer insulating film overlying the first device pattern and the second device pattern and filling the isolating trench.. .
Samsung Electronics Co., Ltd.

Semiconductor structure

Semiconductor structures are provided. A semiconductor structure includes a bottom substrate having a first region and a second region; an insulation layer formed on the bottom substrate in the first region; a top substrate on side surface of the trench and the insulation layer; a first fin portion formed over the insulation layer, and a gate structure crossing the first fin portion.
Semmiconductor Manufacturing International (beijing) Corporation

Semiconductor device and a manufacturing the same

A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film.
Renesas Electronics Corporation

Wafers and device structures with body contacts

Wafers for fabrication of devices that include a body contact, device structures with a body contact, methods for forming a wafer that supports the fabrication of devices that include a body contact, and methods for forming a device structure that includes a body contact. The wafer includes a buried oxide layer and a semiconductor layer on the buried oxide layer.
Globalfoundries Inc.

Semiconductor device and manufacturing the same

The present disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor on an insulator (soi) substrate having a bottom substrate, a buried oxide layer on the bottom substrate, and a semiconductor layer on the buried oxide layer.
Vanguard International Semiconductor Corporation

Semiconductor device

A semiconductor device (1) is manufactured which includes a sic epitaxial layer (28), a plurality of transistor cells (18) that are formed in the sic epitaxial layer (28) and that are subjected to on/off control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an on state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electron (19) together.. .
Rohm Co., Ltd.

Semiconductor chip including integrated circuit having cross-coupled transistor configuration and manufacturing the same

A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type.
Tela Innovations, Inc.

Method of controlling a semiconductor memory device

According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit..
Toshiba Memory Corporation

Non-volatile storage device and manufacturing the same

According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film.
Toshiba Memory Corporation

Semiconductor device and manufacturing same

According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate.
Toshiba Memory Corporation

Semiconductor memory device

A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions..
Toshiba Memory Corporation

Semiconductor device and manufacturing the same

Provided herein may be a semiconductor device and a method of manufacturing the same. The method of manufacturing the semiconductor device may include forming a tunnel insulating layer in a channel hole passing through a preliminary stack structure in which interlayer insulating layers and material layers are alternately stacked.
Sk Hynix Inc.

Semiconductor device and manufacturing the same

A method of manufacturing a semiconductor device includes: forming an insulating film above a semiconductor substrate; forming a conductive film on the insulating film; forming a dielectric film on the conductive film; forming a plurality of upper electrodes at intervals on the dielectric film; forming a first protective insulating film on the upper electrodes and the dielectric film by a sputtering method; forming a second protective insulating film on the first protective insulating film by an atomic layer deposition method, thereby filling gaps of a grain boundary of the dielectric film with the second protective insulating film; and patterning the conductive film after the second protective insulating film is formed to provide a lower electrode.. .
Fujitsu Semiconductor Limited

Nonvolatile semiconductor storage device

A nonvolatile semiconductor storage device having a control gate formed on a semiconductor substrate and including a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole.
Toshiba Memory Corporation

Semiconductor device

A static random access memory (sram) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.. .
Unisantis Electronics Singapore Pte. Ltd.

Source and drain formation technique for fin-like field effect transistor

Source and drain formation techniques are disclosed herein for fin-like field effect transistors (finfets). An exemplary method for forming epitaxial source/drain features for a finfet includes epitaxially growing a semiconductor material on a plurality of fins using a silicon-containing precursor and a chlorine-containing precursor.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

A semiconductor device includes a substrate including a cell active region and a peripheral active region, a direct contact arranged on a cell insulating pattern formed on the substrate and connected to the cell active region, a bit line structure including a thin conductive pattern, contacting a top surface of the direct contact and extending in one direction, and a peripheral gate structure in the peripheral active region. The peripheral gate structure include a stacked structure of a peripheral gate insulating pattern and a peripheral gate conductive pattern, the thin conductive pattern includes a first material and the peripheral gate conductive pattern include the first material, and a level of an upper surface of the thin conductive pattern is lower than a level of an upper surface of the peripheral gate conductive pattern..
Samsung Electronics Co., Ltd.

Micro-pattern forming method, capacitor and manufacturing the same, semiconductor device and manufacturing the same, and electronic system including semiconductor device

A method of forming a micro-pattern including forming a mold layer and a supporting material layer on a substrate, patterning the mold layer and the supporting material layer to form recess patterns, forming conductor patterns in the recess patterns, removing a portion of an upper portion of the supporting material layer for causing upper portions of the conductor patterns to protrude, forming a block copolymer layer on the supporting material layer, processing the block copolymer layer to phase-separate the block copolymer layer into a plurality of block parts, selectively removing some of the phase-separated plurality of block parts, and removing the supporting material layer to expose the mold layer at a position corresponding to each of the removed block parts may be provided.. .
Samsung Electronics Co., Ltd.

Semiconductor device and fabricating the same

A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.. .
Sk Hynix Inc.

Semiconductor device

A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate and are repeatedly arranged in a first direction and in a second direction that crosses the first direction, and a first electrode support contacting a sidewall of at least one of the lower electrodes. The first electrode support includes a first support region including a first opening and a second support region disposed at a border of the first support region.
Samsung Electronics Co., Ltd.

Semiconductor device and fabricating the same

A semiconductor device is provided. The provided semiconductor device may have enhanced reliability and operating characteristics.
Samsung Electronics Co., Ltd.

Method for fabricating semiconductor device

A method for fabricating a semiconductor device includes forming a device isolation film on a substrate between first and second regions, forming first and second sealing films, such that an etch selectivity of the second sealing film is smaller than that of the first sealing film, patterning the first and second sealing films to expose the second region and a portion of the device isolation film, such that an undercut is defined under a lower surface of the second sealing film, forming a filling film filling the undercut, a thickness of the filling film being thicker on a side surface of the second sealing film than on an upper surface thereof, removing a portion of the filling film to form a filling spacer in the undercut, forming a high-k dielectric film and a metal film on the filling spacer, and patterning the high-k dielectric film and the metal film.. .
Samsung Electronics Co., Ltd.

Method, apparatus, and system having super steep retrograde well with silicon and silicon germanium fins

At least one method, apparatus and system disclosed involves forming a finfet device having silicon and silicon germanium fins. The method includes: forming an n-doped and a p-doped region in a semiconductor wafer; forming a layer of silicon above both the those regions; removing a portion of the silicon layer above the p-doped region to create a first recess; forming a layer of silicon germanium in the first recess; etching away at least a portion of the silicon layer and the underlying p-doped region; etching away at least a portion of the silicon germanium layer and the underlying n-doped region; forming fins from the unetched silicon and silicon germanium layers; and forming a shallow trench isolation dielectric in the etched away portion of the silicon layer and the underlying p-doped region and in the etched away portion of the silicon germanium layer and the underlying n-doped region..
Globalfoundries Inc.

Multi-gate device and fabrication thereof

A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first semiconductor material.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor devices and manufacutring the same

A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer.
Samsung Electronics Co., Ltd.

Logic circuit block layouts with dual-side processing

An integrated circuit device may include a p-type metal oxide semiconductor (pmos) transistor supported by a backside of an isolation layer. The integrated circuit device may also include an n-type metal oxide semiconductor (nmos) transistor supported by a front-side of the isolation layer, opposite the backside.
Qualcomm Incorporated

Fin-like field effect transistor (finfet) device and manufacturing same

A semiconductor device includes a semiconductor substrate and two fin structures. Channels of the fin structures include a second semiconductor material portion over a first semiconductor material portion.
Taiwan Semiconductor Manufacturing Company, Ltd.

Integrated circuit and manufacturing method thereof

An integrated circuit includes first and second semiconductor fins, first and second epitaxy structures, and first and second dielectric fin sidewall structures. The first and second epitaxy structures are respectively on the first and second semiconductor fins.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

A semiconductor device includes a substrate, a core device disposed above the substrate, and an input/output (i/o) device disposed above the substrate. The core device includes a first gate electrode having a bottom surface and a sidewall that define a first interior angle therebetween.
Taiwan Semiconductor Manufacturing Co., Ltd.

Integrated circuit with a gate structure and method making the same

The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer..
Taiwan Semiconductor Manufacturing Co., Ltd.

Integrated circuit having vertical transistor and semiconductor device including the integrated circuit

An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively.
Samsung Electronics Co., Ltd.

Method of forming mos and bipolar transistors

Bipolar transistors and mos transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer.
Commissariat A L'energie Atomique Et Aux Energies Alternatives

Electrostatic discharge protection device

Semiconductor devices including a diode and a resistor are disclosed herein. An example of a semiconductor device includes a substrate having a surface.
Texas Instruments Incorporated

Vertical double diffusion metal-oxide-semiconductor power device

A vertical double diffusion metal-oxide-semiconductor power device with thermal sensitivity unit includes a vertical double diffusion metal-oxide-semiconductor power transistor and at least one thermal sensitivity unit. The vertical double diffusion metal-oxide-semiconductor power transistor includes a first metal layer, a substrate layer, an epitaxy layer, a second metal layer, and a plurality of first polysilicon layers, wherein each first polysilicon layer of the plurality of first polysilicon layers corresponds to a first oxide layer, a first doping well and a second doping well with second conductivity type, a first doped region and a second doped region with first conductivity type, and a second oxide layer.
Leadtrend Technology Corp.

Apparatuses and methods for semiconductor circuit layout

Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor.
Micron Technology, Inc.

Semiconductor device including overlay patterns

A semiconductor device includes a first overlay group and a second overlay group disposed on a semiconductor substrate. The first overlay group includes first lower overlay patterns which extend in a first direction, first upper overlay patterns overlapping the first lower overlay patterns, and first via overlay patterns interposed between the first lower overlay patterns and the first upper overlay patterns.
Samsung Electronics Co., Ltd.

Semiconductor device

In a semiconductor device (sd), plate-shaped upper electrodes (uel) are formed on a lower electrode (lel) with a dielectric film (dec) interposed therebetween. The lower electrode (lel), the dielectric film (dec), and the upper electrodes (uel) constitute mim capacitors (mca).
Renesas Electronics Corporation

Seal ring structures and methods of forming same

A three-dimensional (3d) integrated circuit (ic) includes a first ic die and a second ic die. The first ic die includes a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor packages including heat transferring blocks and methods of manufacturing the same

A semiconductor package may be provided. The semiconductor package may include a first semiconductor chip and a second semiconductor chip disposed on an interconnection layer.
Sk Hynix Inc.

Hybrid-type power module having dual-sided cooling

A hybrid-type power module having dual-sided cooling is provided. The power module includes semiconductor chips that is disposed on each of an upper board and a lower board at a location between the boards.
Kia Motors Corporation

Pressure contact-type semiconductor module

A pressure contact-type semiconductor module includes a plurality of semiconductor units disposed side-by-side, each of the semiconductor units including: a semiconductor device substrate; a first electrode formed below the semiconductor device substrate, a second electrode formed above the semiconductor device substrate, an electrode plate electrically connected to the second electrode; and a pressure contact adjustment member screwed into the electrode plate, the pressure contact adjustment member having a top surface as a pressure contact-receiving surface to which a lead-out electrode plate that is common to the plurality of semiconductor units is to be pressure-contacted, levels of the respective top surfaces of the pressure contact adjustment members in the plurality of semiconductor units being adjustable to match a reference pressure contact plane so that contact pressures in the respective top surfaces applied by the lead-out electrode plate are substantially the same among the semiconductor units.. .
Fuji Electric Co., Ltd.

Semiconductor device including die bond pads at a die edge

A semiconductor device is disclosed that is formed with die bond pads at an edge of the semiconductor die. The die bond pads may be formed partially in a kerf area between semiconductor die on a wafer.
Sandisk Semiconductor (shanghai) Co., Ltd.

Three dimensional integrated circuit package and manufacturing thereof

A three dimensional integrated circuit (3dic) package includes a redistribution layer, a plurality of semiconductor chips and a plurality of electrical bumpers. The redistribution layer has a first surface and a second surface.
Nanya Technology Corporation

Semiconductor package

A semiconductor package including a first substrate including first upper pads, the first upper pads on a top surface of the first substrate, a second substrate including second upper pads, the second upper pads on a top surface of the second substrate, a pitch of the second upper pads being less than a pitch of the first upper pads, and a first semiconductor chip on and electrically connected to both (i) at least one of the first upper pads and (ii) at least one of the second upper pads may be provided.. .
Samsung Electronics Co., Ltd.

Method for manufacturing semiconductor device

Method for manufacturing a semiconductor device includes: preparing a first subassembly in which an upper surface of the conductive spacer is soldered on the second conductive member and preliminary solder is provided on a lower surface of the conductive spacer; preparing a second subassembly in which the lower surface of the semiconductor element is soldered on the first conductive member and the bonding wire is joined on upper surface of the semiconductor element; and soldering the upper surface of the semiconductor element in the second subassembly on the lower surface of the conducive spacer in the first subassembly by melting the preliminary solder in the first subassembly. .
Toyota Jidosha Kabushiki Kaisha

Bonding machines for bonding semiconductor elements, methods of operating bonding machines, and techniques for improving uph on such bonding machines

A method of operating a bonding machine is provided. The method includes the steps of: (a) carrying a semiconductor element with a transfer tool; and (b) transferring the semiconductor element from the transfer tool to a bonding tool of the bonding machine without the transfer tool and the bonding tool contacting the semiconductor element at the same time..
Kulicke And Soffa Industries, Inc.

Wire bonded wide i/o semiconductor device

A wide i/o semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide i/o semiconductor device.
Sandisk Technologies Llc

Fan-out semiconductor package

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip, and at least one of the first connection member and the second connection member includes a dummy pattern layer..
Samsung Electro-mechanics Co., Ltd.

Uniform electrochemical plating of metal onto arrays of pillars having different lateral densities and related technology

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions.
Micron Technology, Inc.

Semiconductor device with copper migration stopping of a redistribution layer

A semiconductor device having a redistribution layer and a first coating layer. The redistribution layer is formed on a passivation layer of the semiconductor device and has sidewalls and a top surface.
Chengdu Monolithic Power Systems Co., Ltd.

Core material, semiconductor package, and forming bump electrode

A core material including a core and a solder plating layer of a (sn—bi)-based solder alloy made of sn and bi on a surface of the core. Bi in the solder plating layer is distributed in the solder plating layer at a concentration ratio in a predetermined range of, for example, 91.7% to 106.7%.
Senju Metal Industry Co., Ltd.

Method for forming bump of semiconductor package

The present invention provides a method for forming bumps of a semiconductor package to suppress a final height difference between main bumps and support bumps that is caused by a height difference between areas of an underlying layer when viewed on a cross-section. The method may include forming first seed layer patterns and second seed layer patterns which are disposed in the areas and are separated from each other, over the underlying layer having the height difference.
Hyun Jung

Semiconductor device

A semiconductor device is provided that includes a semiconductor chip having a main terminal and a control terminal, a main connection pin electrically connected to the main terminal, and a control connection pin electrically connected to the control terminal and having an electrical resistance higher than that of the main connection pin. The control connection pin may be a control internal connection pin or a control external connection pin.
Fuji Electric Co., Ltd.

Semiconductor chip

According to one embodiment, a semiconductor chip is described including a semiconductor chip body and a semiconductor chip circuit on the body and including a first circuit path coupled to a first and a second node and including at least two gate-insulator-semiconductor structures and a second circuit path coupled to the first and the second node and including at least two gate-insulator-semiconductor structures. The first and the second circuit path are connected to set the first and the second node to complementary logic states.
Infineon Technologies Ag

Packaging devices and methods for semiconductor devices

Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device including corner recess

A semiconductor die is disclosed including corner recesses to prevent cracking of the semiconductor die during fabrication. Prior to dicing the semiconductor die from the wafer, recesses may be formed in the wafer at corners between any pair of semiconductor die.
Sandisk Semiconductor (shanghai) Co., Ltd.

Semiconductor package and semiconductor process for manufacturing the same

A semiconductor package includes a substrate, a dielectric layer, at least one conductive pillar and an electrical device. The dielectric layer is disposed on the substrate and defines at least one through hole corresponding to the respective first pad of the substrate.
Advanced Semiconductor Engineering, Inc.

Semiconductor package and fabricating the same

A semiconductor package including a marking film and a method of fabricating the same are provided wherein a marking film including a thermoreactive layer may be applied to a molding layer to protect a semiconductor chip under the molding layer and to efficiently perform a marking process. The thickness of the molding layer may thereby be reduced so the entire thickness of the semiconductor package may be reduced.
Samsung Electronics Co., Ltd.

Semiconductor device, positioning semiconductor device, and positioning semiconductor device

A semiconductor device includes: a semiconductor chip that has a first connection terminal for wiring connection; a substrate that has a second connection terminal for wiring connection, the second connection terminal being electrically connected to the first connection terminal; and a reflective surface that reflects light from the first connection terminal and the second connection terminal in a thickness direction of the substrate or the semiconductor chip.. .
Olympus Corporation

Planarized interlayer dielectric with air gap isolation

A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap.
Samsung Electronics Co., Ltd.

Semiconductor package and producing same

An object of the present invention is to provide a semiconductor package with which it is possible to reduce a volume of an encapsulation resin and to easily embed a resin regardless of thicknesses of semiconductor chips and a small distance between adjacent semiconductor chips, as well as to provide a thin semiconductor package with which a final product includes no support flat plate. To realize this, a semiconductor package having a structure wherein semiconductor chips are accommodated in cavity parts of a support which is formed by copper plating and includes the cavity parts is provided..
J-devices Corporation

Fan-out semiconductor package

The present disclosure relates to a fan-out semiconductor package in which a plurality of semiconductor chips are stacked and packaged, and are disposed in a special form to be thus electrically connected to a redistribution layer of a connection member through vias rather than wires. The fan-out semiconductor package can further include a connection member having a through-hole, and at least one of the semiconductor chips can be disposed in the through-hole..
Samsung Electro-mechanics Co., Ltd.

Semiconductor memory device

A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region.
Samsung Electronics Co., Ltd.

Method for fabricating semiconductor device

A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a first gate structure on the substrate, a first spacer around the first gate structure, and an interlayer dielectric (ild) layer around the first spacer; performing a first etching process to remove part of the ild layer for forming a recess; performing a second etching process to remove part of the first spacer for expanding the recess; and forming a contact plug in the recess.. .
United Microelectronics Corp.

Self-aligned vertical transistor with local interconnect

A metallization scheme for vertical field effect transistors (fets) is provided. By forming lower-level local interconnects connecting source regions located at bottom portions of semiconductor fins, and upper-level interconnects connecting adjacent metal gates located along sidewalls of channel regions of the semiconductor fins, electrical connections to the source regions and the metal gates can be provided through the lower-level local interconnects and the upper-level local interconnects, respectively.
International Business Machines Corporation

Source-gate region architecture in a vertical power semiconductor device

A vertical drift metal-oxide-semiconductor (vdmos) transistor with improved contact to source and body regions, and a method of fabricating the same. A masked ion implant of the source regions into opposite-type body regions defines the locations of body contact regions, which are implanted subsequently with a blanket implant.
D3 Semiconductor Llc

Semiconductor device

A semiconductor device includes: a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; an active device on the substrate; an interlayer dielectric (ild) layer on the active device; a first contact plug adjacent to the active device; and a second contact plug in the ild layer and electrically connected to the active device. Preferably, the first contact plug includes a first portion in the insulating layer and the second semiconductor layer and a second portion in the ild layer, in which a width of the second portion is greater than a width of the first portion..
United Microelectronics Corp.

Devices and methods of cobalt fill metallization

Devices and methods of fabricating integrated circuit devices via cobalt fill metallization are provided. A method includes, for instance, providing an intermediate semiconductor device having at least one trench, forming at least one layer of semiconductor material on the device, depositing a first cobalt (co) layer on the second layer, and performing an anneal reflow process on the device.
Globalfoundries Inc.

Memory devices, semiconductor devices and related methods

Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures.
Micron Technology, Inc.

Semiconductor device

A semiconductor device may include an insulating layer, a pad, a circuit, at least one first wiring, at least-one second wiring, at least one third wiring, and a pad contact. The pad may be disposed on the insulating layer.
Samsung Electronics Co., Ltd.

Wiring structure, semiconductor package structure and semiconductor process

A wiring structure includes a main body, a first dielectric layer, a first circuit layer and a second dielectric layer. The first dielectric layer is disposed on the main body, and defines a plurality of first grooves and at least one receiving portion between two first grooves.
Advanced Semiconductor Engineering, Inc.

Method of designing a layout of a semiconductor device, and a semiconductor device including a fin

A semiconductor device includes active fins on a substrate. Gate lines each extend in the second direction on the active fins.
Samsung Electronics Co., Ltd.

Semiconductor device and method with clip arrangement in ic package

Various example embodiments concern an integrated circuit (ic) package having a clip with a protruding tough-shaped finger portion. The clip can be used in various ic packages including, for example, soft-soldered compact power packages such as rectifiers with specified surge current capability.
Nexperia B.v.

Method of making a wire support leadframe for a semiconductor device

A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire.
Texas Instruments Incorporated

Integrated circuit chip with molding compound handler substrate and method

Disclosed are integrated circuit (ic) chip structures (e.g., radio frequency (rf) ic chip structures) and methods of forming the structures with an electrically insulative molding compound handler substrate. Each structure includes at least: an electrically insulative molding compound handler substrate; an insulator layer on the handler substrate; and one or more semiconductor devices (e.g., rf semiconductor devices) on the insulator layer.
Globalfoundries Inc.

Power semiconductor packages having a substrate with two or more metal layers and one or more polymer-based insulating layers for separating the metal layers

Power semiconductor packages described herein each include a substrate having two or more metal layers and one or more insulating layers for separating the metal layers. The substrate insulating layers are formed from a polymer material to reduce the cte mismatch between the substrate metal layers and the substrate insulating layers..
Infineon Technologies Ag

Power module having dual-sided cooling

A power module having dual-sided cooling is provided with a semiconductor chip between an upper board and a lower board of the power module. In particular, the upper board includes: a first bonding layer made of a dielectric material, and a first electrode made of a copper material and provided on a first surface of the first bonding layer, and the first electrode is connected to the semiconductor chip.
Kia Motors Corporation

Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology

A semiconductor die assembly in accordance with an embodiment of the present technology includes a first semiconductor die, a package substrate underlying the first semiconductor die, an interposer between the package substrate and the first semiconductor die, and a second semiconductor die between the package substrate and the interposer. The semiconductor die assembly further comprises a heat spreader including a cap thermally coupled to the first semiconductor die at a first elevation, and a pillar thermally coupled to the second semiconductor die at a second elevation different than the first elevation.
Micron Technology, Inc.

Semiconductor memory device and a chip stack package having the same

A semiconductor memory device includes an integrated circuit (ic) chip structure, wherein the ic chip includes a substrate, a memory cell disposed on the substrate, and a local well disposed on the substrate, wherein a conductivity type of the local well is different from a conductivity type of the substrate, a wiring stack structure disposed on the ic chip structure, wherein the wiring stack structure includes a signal transfer pattern connected to the memory cell through a signal interconnector, and a thermal dispersion pattern connected to the local well through a thermal interconnector, and a heat transfer structure connected to the thermal dispersion pattern for transferring heat to the thermal dispersion pattern from a heat source.. .

Semiconductor device

A semiconductor device includes: a first semiconductor chip including an electrode pad on one surface of the first semiconductor chip; a multilayer chip stack that is disposed on the one surface of the first semiconductor chip to be connected to the electrode pad; a columnar spacer that is disposed on the one surface of the first semiconductor chip; and an underfill resin. The multilayer chip stack includes a plurality of second semiconductor chips each of which comprises a connection terminal.
Shinko Electric Industries Co., Ltd.

Semiconductor device

Semiconductor device 1000 includes semiconductor 102, an electric field relaxation structure, at least one surface electrode 112, passivation layer 114, and insulating layer 115. Semiconductor layer 102 has a predetermined element region.
Panasonic Intellectual Property Management Co., Ltd.

Power semiconductor modules with protective coating

A semiconductor package is described which meets a plurality of predetermined electrical, mechanical, chemical and/or environmental requirements. The semiconductor package includes a semiconductor die embedded in or covered by a molded plastic body, the molded plastic body satisfying only a subset of the plurality of predetermined electrical, mechanical, chemical and/or environmental requirements.
Infineon Technologies Ag

Semiconductor package and fabricating a semiconductor package

A method of fabricating a semiconductor package comprises providing a carrier, fabricating an opening in the carrier, attaching a semiconductor chip to the carrier and fabricating an encapsulation body covering the semiconductor chip.. .
Infineon Technologies Ag

Power converting device

In a power converting device, an anode lead plate and a cathode lead plate are disposed opposed in an interior of an insulating plate, whereby the respective current directions are opposed and a magnetic field is negated, because of which inductance is reduced. Also, as external connection terminals, which are end portions of the anode lead plate and the cathode lead plate, pass through the interior of the insulating plate and are disposed in another space of the case from a lower portion of the insulating plate, the wiring distance between a capacitor element and a power semiconductor module is short, and inductance can be reduced..
Mitsubishi Electric Corporation

Scribe lane structure in which pad including via hole is arranged on sawing line

A semiconductor device structure, including integrated circuits of semiconductor chips and scribe lanes between the regions in which the circuits have been formed, has at least one redistribution pad disposed in one of the scribe lanes for simultaneously testing a group of the integrated circuits, and a metal interconnection structure disposed beneath the redistribution pad(s). The metal interconnection structure includes at least conductive via contacting the redistribution pad at the bottom of the pad.
Samsung Electronics Co., Ltd.

Method for testing bridging in adjacent semiconductor devices and test structure

Bridging testing method between adjacent semiconductor devices includes forming patterned diffusion region on semiconductor substrate, and forming first conductive layer over diffusion region. First conductive layer is patterned in same pattern as patterned diffusion region.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor manufacturing device, semiconductor manufacturing method and semiconductor device

According to one embodiment, provided is a semiconductor manufacturing device including a probe card arranged to face a semiconductor chip to be measured, wherein the probe card has: a test probe that obtains the electric characteristics of the semiconductor chip by being brought into contact with a test pad; a temperature extraction probe that extracts temperature information of the semiconductor chip by being brought into contact with a temperature extraction pad that is coupled to a temperature sensor; a contact member that is brought into contact with the upper surface of the semiconductor chip to absorb the heat of the semiconductor chip; a driving unit that moves the contact member so as to allow the contact member to be brought into contact with or to be separated from the upper surface; and a control unit that controls the driving of the driving unit on the basis of the temperature information.. .
Renesas Electronics Corporation

Contacts in semiconductor devices

An example embodiment relates to a method for making a contact to a source or drain region of a semiconductor device. The method may include providing the semiconductor device having at least one source or drain region, the source or drain region having an exposed area.
Imec Vzw

Semiconductor devices comprising nitrogen-doped gate dielectric, and methods of forming semiconductor devices

Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The first transistors include a first gate electrode, a first nitrogen-doped gate dielectric layer and a first high-k material.
Micron Technology, Inc.

Structure and formation semiconductor device structure

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor structure and fabrication method thereof

A semiconductor structure and a fabrication method are provided. The fabrication method includes providing a substrate, including a first region and a second region; forming a first doped region in the first region of the substrate, the first doped region having first doping ions; forming a second doped region in the second region of the substrate, the second doped region having second dopant ions with a conductivity type opposite to the first doping ions; forming a first metallide on a surface of the first doped region having the first doping ions; and forming a second metallide on a surface of the second doped region having the second doping ions, the second metallide and the first metallide being made of different materials..
Semiconductor Manufacturing International (beijing) Corporation

Semiconductor devices

A semiconductor device including a semiconductor substrate including first regions and second regions, at least one of the first regions being disposed between adjacent second regions; a plurality of first gate structures on the first regions of the semiconductor substrate; and a plurality of second gate structures on the second regions of the semiconductor substrate, wherein each of the first and second gate structures includes a lower gate structure including a recess region defined by sidewalls and a bottom connecting the sidewalls; and an upper gate structure including a gap-fill metal pattern that fills the recess region of the lower gate structure, wherein the bottom of the lower gate structure included in the first gate structure has a thickness different from a thickness of the bottom of the lower gate structure included in the second gate structure, and wherein the gap-fill metal patterns of the first and second gate structures have top surfaces at substantially a same level.. .
Samsung Electronics Co., Ltd.

Dual epitaxial growth process for semiconductor device

A method of forming a semiconductor device includes forming first and second fin structures on a substrate and a patterned polysilicon structure on first portions of the first and second fin structures. The method further includes depositing an insulating layer on second portions of the first and second fin structures and on the patterned polysilicon structure, which may be followed by selectively removing the insulating layer from the second portions and patterning a first hard mask layer on the second portion of the second fin structure.
Taiwan Semiconductor Manufacturing Co., Ltd.

Gate structures with various widths and forming the same

Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method of manufacturing a semiconductor device with metal gate etch selectivity control

A method of manufacturing a semiconductor device includes forming a first layer of a conductive material in gate spaces created by removing portions of a dummy gate structure. The first layer further includes a top layer on an entire structure formed on a fin structure, and a gate space for a short channel gate and a gate space for a long channel gate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Multi-depth etching in semiconductor arrangement

Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement.
Taiwan Semiconductor Manufacturing Company Limited

Semiconductor device and method

A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having ge impurities, the source/drain region free of the ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the ge impurities; and forming a metal contact electrically coupled to the silicide layer.. .
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device having merged epitaxial features with arc-like bottom surface and making the same

A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate, and a semiconductor feature over the two semiconductor fins.
Taiwan Semiconductor Manufacturing Co., Ltd.

Isolation structure for micro-transfer-printable devices

A semiconductor structure suitable for micro-transfer printing includes a semiconductor substrate and a patterned insulation layer disposed on or over the semiconductor substrate. The insulation layer pattern forms one or more etch vias in contact with the semiconductor substrate.
X-fab Semiconductor Foundries Ag

Hybrid integrated semiconductor tri-gate and split dual-gate finfet devices and manufacturing

A method for making a tri-gate finfet and a dual-gate finfet includes providing a semiconductor on insulator (soi) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions.
Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor wafer dicing method

A method of dicing a bowed or warped semiconductor wafer includes cutting along the saw streets in a first direction on a first half of the wafer, where the first direction is parallel to the bowing, cutting along the saw streets in the first direction on a second half of the wafer opposite to the first half, and step-cutting along the saw streets in the second direction, such that all of the dies are separated from each other, and the sides of the die in the bowing direction are flat and the sides of the die perpendicular to the bowing direction are stepped.. .
Nexperia B.v.

Semiconductor device and manufacturing the same, and stacked semiconductor device

A semiconductor device includes: a semiconductor substrate; a through silicon via which penetrates the semiconductor substrate; an insulating film which is provided between a side surface of the through silicon via and the semiconductor substrate; and a mos transistor which is provided on the semiconductor substrate, wherein: the semiconductor substrate has a first crystal axis and a second crystal axis, and a propagation amount of stress occurring from the through silicon via is larger in a direction of the first crystal axis than in a direction of the second crystal axis; and the insulating film has a thickness in a direction of a diameter of the through silicon via being a thickness along the direction of the first crystal axis larger than a thickness along the direction of the second crystal axis.. .
Fujitsu Limited

Semiconductor device and manufacturing the semiconductor device

An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive pattern, a second conductive pattern, a dielectric layer and a contact part.
Sk Hynix Inc.

Semiconductor device with reduced via resistance

A method of fabricating a semiconductor interconnect structure by providing a semiconductor structure with a dielectric layer with and an embedded electrically conductive structure. A dielectric capping layer and a metal capping layer separating a second dielectric layer located above the first dielectric layer.
International Business Machines Corporation

Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods

Semiconductor devices having interconnects incorporating negative expansion (nte) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate.
Micron Technology, Inc.

Chamber conditioning for remote plasma process

The methods, systems and apparatus described herein relate to chamber conditioning for remote plasma processes, in particular remote nitrogen-based plasma processes. Certain implementations of the disclosure relate to remote plasma inhibition processes for feature fill that include chamber conditioning.
Lam Research Corporation

Semiconductor device having a discontinued part between a first insulating film and second insulating film

A semiconductor device, in which an increase in the size of a product can be suppressed and a withstand voltage between wiring layers can be improved, and a manufacturing method thereof are provided. A discontinued part, in which the interface between an interlayer insulating film and a passivation film is discontinued, is formed between a first wiring layer and a second wiring layer that are adjacent to each other with a space therebetween.
Renesas Electronics Corporation

Barrier layers in trenches and vias

A semiconductor structure includes a dielectric layer having a trench formed therein and a barrier layer formed on a bottom and sidewalls of the trench, and on a top surface of the dielectric layer. The trench comprises a flared top gap opening and additional area at the bottom such that the top and bottom of the trench are wider than sidewalls of the trench.
International Business Machines Corporation

Device and reducing contact resistance of a metal

A device comprises a semiconductor substrate; a dielectric layer deposited over the semiconductor substrate, the dielectric layer including a trench; and a structure in the trench. The structure includes a chemical vapor deposition (cvd) tan layer formed on a side wall of the trench; a physical vapor deposition (pvd) ta layer formed over the cvd tan layer; and a metal-containing layer formed over the pvd ta layer..
Taiwan Semiconductor Manufacturing Company, Ltd.

Interconnection lines having variable widths and partially self-aligned continuity cuts

A semiconductor cell includes a dielectric layer. An array of parallel metal lines is disposed in a longitudinal direction within the dielectric layer.
Globalfoundries Inc.

Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts

A method includes providing a semiconductor structure having a mandrel layer and a hardmask layer disposed above a dielectric layer. A mandrel cell is patterned into the mandrel layer.
Globalfoundries Inc.

Apparatus and forming interconnection lines having variable pitch and variable widths

A semiconductor cell includes a dielectric layer. An array of at least four parallel metal lines is disposed within the dielectric layer, the metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width.
Globalfoundries Inc.

High resistivity silicon-on-insulator substrate comprising an isolation region

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between rf devices..
Sunedison Semiconductor Limited (uen201334164h)

Semiconductor device

An object is to provide a semiconductor device with reduced standby power. A transistor including an oxide semiconductor as an active layer is used as a switching element, and supply of a power supply voltage to a circuit in an integrated circuit is controlled by the switching element.
Semiconductor Energy Laboratory Co., Ltd.

Slit stress modulation in semiconductor substrates

A disclosed example to modulate slit stress in a semiconductor substrate includes a first controller to, after obtaining a wafer stress measurement of the semiconductor substrate, control a first process to apply a first material to the semiconductor substrate based on the wafer stress measurement, the semiconductor substrate including a slit between adjacent stacked transistor layers, the first material coating walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width; and a second controller to control a second process to apply a second material to the semiconductor substrate, the second material to be deposited in the second width of the slit, the first material and the second material to form a solid structure in the slit between the adjacent stacked transistor layers.. .
Intel Corporation

Methods of fabricating semiconductor devices including fin-shaped active regions

A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.. .
Samsung Electronics Co., Ltd.

Method for forming trench liner passivation

In a method for fabricating a semiconductor device, a trench is etched in a semiconductor substrate having a top surface, and a lining oxide layer is formed conformal to the trench. A negatively-charged liner covering the lining oxide layer and conformal to the trench is formed.
Taiwan Semiconductor Manufacturing Co., Ltd.

Trench isolated ic with transistors having locos gate dielectric

An integrated circuit (ic) including at least one transistor having a metal-oxide-semiconductor (mos) gate includes a substrate having a semiconductor surface. The transistor includes at least one trench isolation region in the semiconductor surface.
Texas Instruments Incorporated

Semiconductor device, method, and tool of manufacture

An embodiment is an apparatus. The apparatus includes: a collective wafer platter including a plurality of individual wafer pockets, the individual wafer pockets having respective individual wafer platters, the individual wafer platters configured to rotate around respective first axes, the collective wafer platter configured to rotate around a second axis; a motor coupled to the collective wafer platter; and a control unit configured to control the motor such that the individual wafer platters rotate around the respective first axes, and the collective wafer platter rotates around the second axis..
Taiwan Semiconductor Manufacturing Company, Ltd.

Wafer level flat no-lead semiconductor packages and methods of manufacture

Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads.
Semiconductor Components Industries, Llc

Substrate processing apparatus and manufacturing semiconductor device

A substrate processing apparatus includes an accommodating chamber including a loading shelf configured to load a storage vessel that accommodates a substrate; a transfer mechanism installed in a ceiling part of the accommodating chamber and configured to hold an upper portion of the storage vessel and transfer the storage vessel; and a port configured to load and unload the storage vessel to and from the accommodating chamber.. .
Hitachi Kokusai Electric Inc.

Fan-out structure and fabricating the same

A semiconductor structure and a method of forming include a first semiconductor die and a first dummy die over a carrier, wherein a thickness of the first semiconductor die is greater than a thickness of the first dummy die, a first molding compound layer over the carrier, the first molding compound layer extending along sidewalls of the first semiconductor die and the first dummy die and a first interconnect structure over the first molding compound layer, wherein the first interconnect structure comprises a first metal feature electrically coupled to the first semiconductor die and the first molding compound layer is formed between the first dummy die and the first metal feature.. .
Taiwan Semiconductor Manufacturing Company, Ltd.

Manufacturing semiconductor device

An object is to provide a technology that reduces the number of components and that is capable of suppressing the cost. A structure including semiconductor elements, a plurality of electrode terminals, and a dam bar for connecting the plurality of electrode terminals is prepared, and a part of the structure including a part of the plurality of electrode terminals and the dam bar is arranged in the terminal hole.
Mitsubishi Electric Corporation

Manufacturing semiconductor device

In a semiconductor device including an oxide semiconductor, a change in electrical characteristics is inhibited and reliability is improved. The semiconductor device is manufactured by a method including first to fourth steps.
Semiconductor Energy Laboratory Co., Ltd.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device may include forming first trenches that define active patterns extending in a first direction on a substrate, forming first insulating layers filling the first trenches, forming first mask patterns extending in the first direction while having a first width along a second direction perpendicular to the first direction, forming a second mask pattern extending in the first direction while having a second width along the second direction, and forming a second trench that partly defines an active region by executing a first etching process that etches the active patterns and the first insulating layer using the first mask patterns and the second mask pattern.. .
Samsung Electronics Co., Ltd.

Technique to deposit sidewall passivation for high aspect ratio cylinder etch

Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner.
Lam Research Corporation

Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme

A method of making a semiconductor device includes disposing a first hard mask (hm), amorphous silicon, and second hm on a substrate; disposing oxide and neutral layers on the second hm; removing a portion of the oxide and neutral layers to expose a portion of the second hm; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (bcp) on the guiding pattern; removing a portion of the bcp to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of hm stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller hm stack with a third hm material; planarizing the surface and exposing both hm stacks; and selectively removing the shorter hm stack and the silicon fins underneath.. .
Globalfoundries, Inc.

Pattern fidelity enhancement with directional patterning technology

A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.. .
Taiwan Semiconductor Manufacturing Co., Ltd.

Production semiconductor device electrode

The present invention provides a method for producing a semiconductor device electrode, the method including the steps of: forming a first thin-film including a first metal on a substrate containing si; forming a second thin-film including a compound of a second metal on the first thin-film; and performing a heat treatment to form an electrode including a silicide of the first metal, and is characterized in that hafnium (hf) is applied as the second metal. Hfn, hfw, hfb or the like is suitable as the compound of the second metal.
Tokyo Institute Of Technology

Semiconductor device and manufacturing the same

According to one embodiment, a semiconductor device includes first, second, and third electrodes, and first, second, third, fourth, and fifth semiconductor regions. The first electrode includes a first conductive region.
Kabushiki Kaisha Toshiba

High pressure low thermal budge high-k post annealing process

A method of fabricating high-k/metal gate semiconductor device by incorporating an enhanced annealing process is provided. The enhanced annealing process in accordance with the disclosure can be operated at relatively low temperature and high pressure and thus can improve the k value and repair the above-mentioned deficiencies of the hk layer.
Shanghai Huali Microelectronics Corporation

Method of lateral oxidation of nfet and pfet high-k gate stacks

A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack.. .
International Business Machines Corporation

Semiconductor structure having low-k spacer and manufacturing the same

The present disclosure provides a semiconductor structure, including a semiconductor fin, a metal gate over the semiconductor fin, and a sidewall spacer composed of low-k dielectric surrounding opposing sidewalls of the metal gate. A portion of the sidewall spacer comprises a tapered profile with a greater separation of the opposing sidewalls toward a top portion and a narrower separation of the opposing sidewalls toward a bottom portion of the sidewall spacer.
Taiwan Semiconductor Manufacturing Company Ltd.

Semiconductor device having buried gate structure and fabricating the same

A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.. .
Sk Hynix Inc.

Hybrid iii-v technology to support multiple supply voltages and off state currents on same chip

Techniques for forming dual iii-v semiconductor channel materials to enable fabrication of different device types on the same chip/wafer are provided. In one aspect, a method of forming dual iii-v semiconductor channel materials on a wafer includes the steps of: providing a wafer having a first iii-v semiconductor layer on an oxide; forming a second iii-v semiconductor layer on top of the first iii-v semiconductor layer, wherein the second iii-v semiconductor layer comprises a different material with an electron affinity that is less than an electron affinity of the first iii-v semiconductor layer; converting the first iii-v semiconductor layer in at least one second active area to an insulator using ion implantation; and removing the second iii-v semiconductor layer from at least one first active area selective to the first iii-v semiconductor layer..
International Business Machines Corporation

Quantum doping method and use in fabrication of nanoscale electronic devices

A novel doping technology for semiconductor wafers has been developed, referred to as a “quantum doping” process that permits the deposition of only a fixed, controlled number of atoms in the form of a monolayer in a substitutional condition where only unterminated surface bonds react with the dopant, thus depositing only a number of atoms equal to the atomic surface density of the substrate material. This technique results in providing a “quantized” set of possible dopant concentration values that depend only on the additional number of layers of substrate material formed over the single layer of dopant atoms..

Forming a metal contact layer on silicon carbide and semiconductor device with metal contact structure

A semiconductor device includes a silicon carbide semiconductor body and a metal contact structure. Interface particles including a silicide kernel and a carbon cover on a surface of the silicide kernel are formed directly between the silicon carbide semiconductor body and the metal contact structure.
Infineon Technologies Ag

Film forming method, boron film, and film forming apparatus

There is provided a method of forming a boron film on a substrate on which a semiconductor device is formed, by plasmarizing a reaction gas containing a boron-containing gas under a process atmosphere regulated to a pressure which falls within a range of 0.67 to 33.3 pa (5 to 250 mtorr). The boron film is formed on a substrate on which a semiconductor device is formed, by plasmarizing a reaction gas containing a boron-containing gas under a process atmosphere regulated to a pressure which falls within a range of 0.67 to 33.3 pa (5 to 250 mtorr)..
Tokyo Electron Limited

Method of manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device

A method of manufacturing a silicon carbide semiconductor device includes, in order: polishing a silicon carbide semiconductor base body from a second main surface side thus forming unevenness on a second main surface; forming a thin metal film made of metal capable of forming a metal carbide on the second main surface of the silicon carbide semiconductor base body; irradiating a laser beam which falls within a visible region or within an infrared region to the thin metal film so as to heat the thin metal film thus forming a metal carbide on a boundary face between the silicon carbide semiconductor base body and the thin metal film; etching a metal containing byproduct layer possibly formed on a surface side of the metal carbide by a non-oxidizing chemical solution thus e