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Memory Device

Memory Device-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Facsimile apparatus, control method thereof, and storage medium
September 13, 2018 - N°20180262628

A facsimile apparatus includes a memory device that stores a user name and a notification destination of a transmission result of facsimile transmission in association with each other. The facsimile apparatus receives, from an external apparatus, a facsimile transmission instruction that includes image data, a transmission destination of facsimile transmission, and a user name; executes, for the transmission destination included ...
Three-terminal non-volatile multi-state memory for cognitive computing applications
September 13, 2018 - N°20180261764

A three-terminal non-volatile multi-state memory device based on mobile ion induced electrical resistivity change is provided. The three-terminal non-volatile multi-state memory device-includes a substrate having a first electrode and a second electrode therein.
3-d flash memory device and manufacture thereof
September 13, 2018 - N°20180261687

A 3-d flash memory device and its manufacturing method, relating to semiconductor technology. The manufacturing method comprises: providing a semiconductor structure comprising a substrate, a first insulation layer on the substrate, a fin structure comprising a first gate layer and a second insulation layer stacked alternately over each other on the first insulation layer, a third insulation layer on two ...
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Memory Device Patent Applications
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Memory device
September 13, 2018 - N°20180261651

According to one or more embodiments, a memory device includes a first interconnection extending in a first direction, a plurality of second interconnections extending in a second direction intersecting the first direction, and a first resistance change film provided between the first interconnection and the second interconnections. The first resistance change film includes a first conductive layer having a first ...
Three-dimensional semiconductor memory device and method of fabricating the same
September 13, 2018 - N°20180261626

A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions ...
Semiconductor device and method of manufacturing the same
September 13, 2018 - N°20180261625

A three-dimensional memory device and method of manufacturing the same, an isolation structure is embedded between the common source region and the substrate thereunder, which can inhibit the undesired diffusion of impurities during the implantation of the common source region, avoiding operation failure due to excessive diffusion of impurities. In programming and reading states of the three-dimensional memory device, electrons ...
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Memory Device Patent Applications
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inventor
  • 2989+ full patent PDF documents of Memory Device-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Three dimensional memory device and method for fabricating the same
September 13, 2018 - N°20180261620

A 3d memory device includes a multi-layer stack, a first contact layer, a memory layer, a cannel layer. The multi-layer stack includes a plurality of conductive layers, a first opening and a second opening.
Semiconductor memory device
September 13, 2018 - N°20180261619

A semiconductor memory device according to an embodiment comprises: when three directions intersecting each other are assumed to be first through third directions, and two directions intersecting each other in a plane extending in the first and second directions are assumed to be fourth and fifth directions, a memory cell array including: a conductive layer stacked in the third direction ...
Semiconductor memory device
September 13, 2018 - N°20180261615

A semiconductor memory device includes a stacked body, a first semiconductor member, a first insulating layer, a second semiconductor member, and a second insulating layer. The stacked body includes an electrode film and an insulating film arranged alternately along a first direction.
Semiconductor memory device
September 13, 2018 - N°20180261614

A semiconductor memory device includes an interconnect layer including a conductive layer and a semiconductor layer of a first conductivity type provided on the conductive layer; a stacked body including a plurality of electrode layers stacked on the interconnect layer, a semiconductor pillar provided in the stacked body and extending through the plurality of electrode layers in a stacking direction ...
Three-dimensional memory device with short-free source select gate contact via structure and method of making ...
September 13, 2018 - N°20180261613

Electrical short caused by misalignment of source select level contact via structure and support pillar structures can be prevented by modifying the pattern of the support pillar structures such that the support pillar structures are omitted from the area in which source select gate contact via structures are formed. The insulating layer at the level overlying the source select level ...
Three-dimensional memory device with level-shifted staircase structures and method of making thereof
September 13, 2018 - N°20180261611

A mesa structure is formed over a substrate. An alternating stack of insulating layers and spacer material layers having a total height of approximately double the height of the mesa structure is formed over the substrate and the mesa structure.
Semiconductor memory device
September 13, 2018 - N°20180261608

A semiconductor memory device includes a stacked body, a semiconductor member, and a first insulating member. Electrode films and insulating films are alternately stacked along a first direction in the stacked body.
Memory Device Patent Pack
Download 2989+ patent application PDFs
Memory Device Patent Applications
Download 2989+ Memory Device-related PDFs
For professional research & prior art discovery
inventor
  • 2989+ full patent PDF documents of Memory Device-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Memory devices which include memory arrays
September 13, 2018 - N°20180261602

Some embodiments include a memory device. The device has a fin with a first source/drain region, a second source/drain region and a channel region.
Semiconductor memory device and structure
September 13, 2018 - N°20180261600

A semiconductor device, including: a plurality of non-volatile memory cells including a first memory cell and a second memory cell, where the plurality of non-volatile memory cells includes source diffusion lines and drain diffusion lines, at least one of the source diffusion lines and drain diffusion lines are shared by the first memory cell and the second memory cell, where ...
Memory device
September 13, 2018 - N°20180261575

A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first ...
Semiconductor memory device and data read method
September 13, 2018 - N°20180261300

According to one embodiment, a semiconductor memory device includes a memory cell array with a plurality of memory cells, an ecc circuit with an encoder for generating error correcting codes and a decoder for performing correcting processing, a page buffer capable of storing the write data, corrected data, and the error correcting codes, and a multiplexer having a first input ...
Memory system including a delegate page and method of identifying a status of a memory ...
September 13, 2018 - N°20180261298

A nonvolatile memory system may include a nonvolatile memory device, a delegate page attacker, and a health status analyzer. The nonvolatile memory device may include at least one memory block including a plurality of storage pages and a delegate page.
Methods of operating a nonvolatile memory device and the nonvolatile memory device thereof
September 13, 2018 - N°20180261296

In a method of operating a nonvolatile memory device including a memory cell array, where the memory cell array includes a plurality of pages, and each of the plurality of pages includes a plurality of nonvolatile memory cells, a first sampling read operation is performed to count a first number of memory cells in a first region of a first ...
Non-volatile memory array with memory gate line and source line scrambling
September 13, 2018 - N°20180261295

A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (nvm) cells coupled in the same column of the memory array, in which each nvm cell may include a memory gate.
Method and apparatus for shielded read to reduce parasitic capacitive coupling
September 13, 2018 - N°20180261292

In one embodiment, an apparatus comprises a nand flash memory device comprising a memory device controller and a memory nand flash memory array, the nand flash memory device to program data into a plurality of nand flash memory cells coupled to a wordline in a single program sequence, wherein the plurality of nand flash memory cells are coupled to a ...
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