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Designs

Designs-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Interfaces for selecting among multiple communications protocols
September 13, 2018 - N°20180262595

Interface circuits are disclosed for manually or automatically selecting among two or more communications protocols in ways that reduce the number of connector pins needed and/or use the same number of connector pins required for a single communications protocol. Such interface circuits are advantageously applicable to selecting and accommodating either rs-485 or 802bw communications protocols in aircraft electronics while ...
Ultra-reliable low-latency communication indication channelization designs
September 13, 2018 - N°20180262311

In some circumstances, a urllc may preempt resource. An apparatus may be configured to receive a set of resource blocks from a base station including at least one of embb data or urllc data in a pdsch.
Repulsive magnetic motor and generator
September 13, 2018 - N°20180262084

The use of repulsive magnetic and electro-static fields as the driving force in the powering of other designs could widened the options available with wind, solar, nuclear, aquatic, oil, coal, wood and even steam power. The theory has presented a new and different way to view older understood actions in science, enabling a better understanding of why the resultant is ...
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Devices with peripheral task bar display zone and under-lcd screen optical sensor module for on-screen ...
September 13, 2018 - N°20180260602

Devices or systems with display designs to include both a main display zone and a peripheral display zone that collectively form a seamless contiguous display area for displaying images, content or information over the two zones as a single display area and further allowing for operating the peripheral display zone independently from the main display zone to display certain images, ...
Integrated circuit layout design methodology with process variation bands
September 13, 2018 - N°20180260512

A system for analyzing ic layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations.
Address generators for verifying integrated circuit hardware designs for cache memory
September 13, 2018 - N°20180260506

Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of ...
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  • 425+ full patent PDF documents of Designs-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Analysis instrument having a sample bearing device location
September 13, 2018 - N°20180257077

Instruments, devices and methods of analysis are provided which fully integrate a significant number of process steps in a continuous operation. Accurate positioning and full contact between components is also provided by the relative movement the designs allow.
Logic circuitry using three dimensionally stacked dual-gate thin-film transistors
Postech Academy-industry Foundation
September 06, 2018 - N°20180254351

Disclosed is a logic circuit using three-dimensionally stacked dual-gate thin-film transistors, including a substrate, a first dual-gate thin-film transistor on the substrate, a second dual-gate thin-film transistor on the first dual-gate thin-film transistor, and a third dual-gate thin-film transistor on the second dual-gate thin-film transistor, wherein the first dual-gate thin-film transistor, the second dual-gate thin-film transistor and the third dual-gate ...
Static warehouse area sizing and slotting of a multi-mode forward area
Intelligrated Headquarters, Llc
September 06, 2018 - N°20180253680

A method, apparatus and computer program product for static warehouse area sizing and slotting of a multi-mode forward area. Method includes: receiving article dimensional attributes and demand information of more than article identified by a stock keeping unit (sku); receiving storage dimensional attributes of more than one storage configuration of pick media; for each of a forward area and a ...
Dynamic layout design
Adobe Systems Incorporated
September 06, 2018 - N°20180253211

Embodiments of the present invention provide systems, methods, and computer storage media for facilitating layout designs. In embodiments, an input event is detected indicating a desire to include a new object within a layout design including a first component.
Method and apparatus for design and fabrication of customized eyewear
September 06, 2018 - N°20180252937

Eyewear can include lenses having perimeters that are customized for an intended wearer. The perimeter of the lenses can be determined based on anatomical features of the wearer's face, field of vision, or other parameters specific to that individual.
Collapsible pistol
September 06, 2018 - N°20180252488

A collapsible pistol features enhanced safety, ease of use, and improved performance as compared to prior designs. The pistol is easily reconfigured from an open, ready-to-fire position to a closed or collapsed position that makes the pistol quite compact, safe, and readily concealable.
Libraries of genetic packages comprising novel hc cdr3 designs
Dyax Corp.
September 06, 2018 - N°20180251912

Provided are compositions and methods for preparing and identifying antibodies having cdr3s that vary in sequence and in length from very short to very long which in certain embodiments may bind to a carbohydrate moiety or the active site of an enzyme. Libraries coding for antibodies with the cdr3s are also provided.
Designs Patent Pack
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  • 425+ full patent PDF documents of Designs-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Modular cabinet with hidden clamping system
September 06, 2018 - N°20180249828

The present invention includes a system for quickly and simply manufacturing semi-custom cabinetry utilizing a hidden pin joining system. The hidden pin joining system allows panels of a cabinet, or other items, to quickly and securely join together, with significant load bearing ability.
Transformable clothing
The Regents Of The University Of California
September 06, 2018 - N°20180249772

A transformable garment that folds and envelops the wearer with a garment body with panels that use origami folding and shape memory alloy (sma) elements to assist to transform the garment from an expanded state to a retracted state is provided. Garment designs with transformable panels and sleeves can benefit those who have trouble dressing by allowing the garment to ...
Low distortion lens using double plane symmetric element
Dynaoptics Ltd
August 23, 2018 - N°20180239132

A low distortion lens suited for a wide variety of applications uses a double plane symmetry lens as part of a lens system to permit aberration correction to be optimized in the field of view of an associated sensor. Wide angle, kepler telescopic and galileo telescopic designs can be implemented.
Method and system for optical data communication via scanning ladar
Aeye, Inc.
August 23, 2018 - N°20180239005

Disclosed herein are a number of example embodiments that employ controllable delays between successive ladar pulses in order to discriminate between “own” ladar pulse reflections and “interfering” ladar pulses reflections by a receiver. Example embodiments include designs where a sparse delay sum circuit is used at the receiver and where a funnel ...
Ladar pulse deconfliction method
Aeye, Inc.
August 23, 2018 - N°20180239004

Disclosed herein are a number of example embodiments that employ controllable delays between successive ladar pulses in order to discriminate between “own” ladar pulse reflections and “interfering” ladar pulses reflections by a receiver. Example embodiments include designs where a sparse delay sum circuit is used at the receiver and where a funnel ...
Method and system for ladar pulse deconfliction to detect and track other ladar systems
Aeye, Inc.
August 23, 2018 - N°20180239001

Disclosed herein are a number of example embodiments that employ controllable delays between successive ladar pulses in order to discriminate between “own” ladar pulse reflections and “interfering” ladar pulses reflections by a receiver. Example embodiments include designs where a sparse delay sum circuit is used at the receiver and where a funnel ...
Method and system for ladar pulse deconfliction using delay code selection
Aeye, Inc.
August 23, 2018 - N°20180239000

Disclosed herein are a number of example embodiments that employ controllable delays between successive ladar pulses in order to discriminate between “own” ladar pulse reflections and “interfering” ladar pulses reflections by a receiver. Example embodiments include designs where a sparse delay sum circuit is used at the receiver and where a funnel ...
Ladar pulse deconfliction apparatus
Aeye, Inc.
August 23, 2018 - N°20180238998

Disclosed herein are a number of example embodiments that employ controllable delays between successive ladar pulses in order to discriminate between “own” ladar pulse reflections and “interfering” ladar pulses reflections by a receiver. Example embodiments include designs where a sparse delay sum circuit is used at the receiver and where a funnel ...
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