|| List of recent Wafer-related patents
|Pattern selection for lithographic model calibration|
The present invention relates generally to methods and apparatuses for test pattern selection for computational lithography model calibration. According to some aspects, the pattern selection algorithms of the present invention can be applied to any existing pool of candidate test patterns.
|Wafer center finding with kalman filter|
A device is provided having a robotic arm for handling a wafer, the robotic arm including one or more encoders that provide encoder data identifying a position of one or more components of the robotic arm. The device also having a processor adapted to apply an extended kalman filter to the encoder data to estimate a position of the wafer..
|Tool optimizing tuning systems and associated methods|
The present disclosure provides various methods for tuning process parameters of a process tool, including systems for implementing such tuning. An exemplary method for tuning process parameters of a process tool such that the wafers processed by the process tool exhibit desired process monitor items includes defining behavior constraint criteria and sensitivity adjustment criteria; generating a set of possible tool tuning process parameter combinations using process monitor item data associated with wafers processed by the process tool, sensitivity data associated with a sensitivity of the process monitor items to each process parameter, the behavior constraint criteria, and the sensitivity adjustment criteria; generating a set of optimal tool tuning process parameter combinations from the set of possible tool tuning process parameter combinations; and configuring the process tool according to one of the optimal tool tuning process parameter combinations..
|Lateral approach expandable spinal implant and method|
An expandable interbody fusion device configured for placement into the intradiscal space between vertebral bodies in a lumbar spine from a lateral approach. The device is expanded by the insertion of a plurality of wafers into the device in situ.
|Polishing apparatus and method of polishing semiconductor wafer|
An aspect of the present embodiment, there is provided a polishing apparatus, including a stage configured to be placed a semiconductor wafer thereon and to be rotated with the semiconductor wafer, a first polishing unit configured to contact a polishing tape to one portion of the semiconductor wafer on the stage, a second polishing unit configured to contact to other portion of the semiconductor wafer, the other portion being different from the one portion, a feed unit configured to feeding the polishing tape, and a recovery unit configured to recovery the polishing tape.. .
|Method for polishing a semiconductor wafer|
A method for polishing at least one wafer composed of semiconductor material that has a front side and the rear side includes performing at least one first polishing step including simultaneously polishing both front and rear sides of the at least one wafer at a process temperature between an upper polishing plate and a lower polishing plate. Each of the upper polishing and lower polishing plates is covered with a polishing pad having an inner edge and an outer edge, a hardness of at least 80° shore a, a compressibility of less than 2.5%, and respective upper and lower surfaces that come into contact with the wafer being polished.
|Wafer processing method|
A wafer processing method divides a wafer into individual devices along crossing streets formed on the front side of the wafer. The wafer has a substrate and a functional layer formed on the substrate, the individual devices being formed from the functional layer and partitioned by the streets.
|Electronic component, a semiconductor wafer and a method for producing an electronic component|
An electronic component includes a semiconductor substrate defined by a generally planar first face, a generally planar second face and side faces extending between the generally planar second face and the generally planar first face. The semiconductor substrate has a curved contour between the generally planar second face and the side faces..
|Manufacturing method of power mosfet using a hard mask as a stop layer between sequential cmp steps|
A manufacturing method of a power mosfet employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed..
|Semiconductor device comprising a passive component of capacitors and process for fabrication|
A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside.
|Flip-chip wafer level package and methods thereof|
An electronic package includes a flip-chip component having a first die coupled to a flip-chip substrate, second die stacked on the first die, an encapsulation compound formed around the first die and the second die, a set of through encapsulant vias (tevs) providing a set of electrical connections from a first side of the electronic package to a second side of the electronic package through the encapsulation compound to the flip-chip substrate, and a redistribution layer electrically connecting a set of contacts on the second die to the set of tevs on the first side of the electronic package.. .
|Methods and arrangements relating to semiconductor packages including multi-memory dies|
Embodiments provide a method comprising providing a multi-memory die that comprises multiple individual memory dies. Each of the individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies.
|Method of forming wafer-level molded structure for package assembly|
A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer.
|Antimony compounds useful for deposition of antimony-containing materials|
Precursors for use in depositing antimony-containing films on substrates such as wafers or other microelectronic device substrates, as well as associated processes of making and using such precursors, and source packages of such precursors. The precursors are useful for deposition of ge2sb2te5 chalcogenide thin films in the manufacture of nonvolatile phase change memory (pcm) or for the manufacturing of thermoelectric devices, by deposition techniques such as chemical vapor deposition (cvd) and atomic layer deposition (ald)..
|Heat treatment apparatus and heat treatment method for heating substrate by irradiating substrate with flash of light|
A flash heating part in a heat treatment apparatus includes 30 built-in flash lamps, and irradiates a semiconductor wafer held by a holder in a chamber with a flash of light. Thirty switching elements are provided in a one-to-one correspondence with the 30 flash lamps.
|Method for forming patterns of semiconductor device by using mixed assist feature system|
A method for forming patterns of a semiconductor device includes providing a photomask that includes an array of contact holes in an active region, a plurality of first dummy contact holes for restricting pattern distortion of the contact holes in an area outside of the array of the contact holes, a plurality of first assist features for restricting pattern distortion of the first dummy contact holes disposed inside a corresponding one of the first dummy contact holes, and an array of second assist features for additionally restricting pattern distortion of the first dummy contact holes. The array of second assist features is disposed outside of the first dummy contact holes.
|Euv mask and method for forming the same|
An extreme ultraviolet (euv) mask can be used in lithography, such as is used in the fabrication of a semiconductor wafer. The euv mask includes a low thermal expansion material (ltem) substrate and a reflective multilayer (ml) disposed thereon.
|Method of producing gaas single crystal and gaas single crystal wafer|
A method of producing a gaas single crystal having high carrier concentration and high crystallinity and to provide a gaas single crystal wafer using such a gaas single crystal. In the method of producing a gaas single crystal, a vertical boat method is performed with a crucible receiving a seed crystal, a si material, a gaas material serving as an impurity, solid silicon dioxide, and a boron oxide material, thereby growing a gaas single crystal..
|Vertical optical coupler for planar photonic circuits|
Described herein are an apparatus, system, and method for providing a vertical optical coupler (voc) for planar photonics circuits such as photonics circuits fabricated on silicon-on-insulator (soi) wafers. In one embodiment, the voc comprises a waveguide made from a material having refractive index in a range of 1.45 to 3.45, the waveguide comprising: a first end configured to reflect light nearly vertical by total internal reflection between the waveguide and another medium, a second end to receive the light for reflection, and a third end to output the reflected light.
|Method of fabricating silicon waveguides with embedded active circuitry|
A method of fabricating silicon waveguides with embedded active circuitry from silicon-on-insulator wafers utilizes photolithographic microfabrication techniques to define waveguide structures and embedded circuit recesses for receiving integrated circuitry. The method utilizes a double masking layer, one layer of which at least partially defines at least one waveguide and the other layer of which at least partially defines the at least one waveguide and at least one embedded circuit recess.
|Plate-shaped body for temperature measurement and temperature measuring apparatus provided with the same|
There are provided a plate-shaped body for temperature measurement which, simply by being mounted on a mounting surface of an electrostatic chuck apparatus and without using a semiconductor wafer itself which is a product, is able to easily optimize the in-plane temperature distribution of the mounting surface of the electrostatic chuck apparatus, the temperature rising characteristics, and the cooling characteristics during decreases in temperature, and a temperature measuring apparatus provided with the same. In such a wafer for temperature measurement (plate-shaped body for temperature measurement) (1), an insulating adhesive (3) is bonded to the entirety of a surface (2a) of a wafer (2), a heater element (4) is provided on the insulating adhesive (3), a temperature measurement region (5) is provided used to measure the temperature of the surface (2a) of the wafer (2) in a region excluding the heater element (4) on the surface (3a) of the insulating adhesive (3), and the heater element (4) and the temperature measurement region (5) are coated with an insulating film (6)..
|Wafer level optical lens structure|
A wafer level optical lens structure is provided. A stress buffer layer is disposed between a light-transmissive substrate and a lens layer, so as to improve production yield of the wafer level optical lens..
|Method of inspecting wafer|
Wafer inspection method to perform wafer inspection based on photo map information. The wafer inspection method may include: detecting a sample center location on a wafer; compensating the detected sample center location to a compensated center location based on photo map information; and detecting defective dies included in the wafer based on the compensated center location..
|Exposure method, exposure apparatus, exposure system and device manufacturing method|
When exposing a same resist layer of a wafer a plurality of times, at least in one exposure of the plurality of exposures, by filling a space between a projection optical system, which projects an exposure light on the wafer, and the wafer with water by a liquid supply/drainage unit, a substantial wavelength of exposure light that reaches the wafer is made to differ from a substantial wavelength of exposure light in another exposure. Accordingly, exposure with high precision and high throughput can be achieved..
|Test system and method for wafer including optical component|
A wafer test system includes an input device configured to transmit a test signal, a wafer including an optical port, an input port configured to receive the test signal, and an output port configured to output a result signal based on the test signal, a measuring device configured to measure the result signal, and an alignment device configured to align an optical fiber port of an optical probe with an alignment port based on the result signal and then align the optical fiber port with the optical port. The alignment port is the input port or the output port.
|Through silicon vias for semiconductor devices and manufacturing method thereof|
The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad.
|Production method of semiconductor device, semiconductor wafer, and semiconductor device|
A semiconductor wafer, includes: a plurality of element regions; a surface electrode that is disposed in each of the plurality of element regions; an insulating layer that is disposed in each of the plurality of element regions and of which height from a front side surface of the semiconductor wafer is higher than that of the surface electrode in a periphery of the surface electrode; and a dicing line groove that is formed in a front side surface of the semiconductor wafer, that surrounds the surface electrode with the insulating layer therebetween, of which height from the front side surface of the semiconductor wafer is lower than that of the insulating layer, and that extends to a perimeter of the semiconductor wafer; in which the insulating layer is formed with a communication passage that extends from a side of the surface electrode to the dicing line groove.. .
|Method of producing composite wafer and composite wafer|
There is provided a method that includes forming a sacrificial layer and the semiconductor crystal layer on a semiconductor crystal layer formation wafer in the stated order, bonding together the semiconductor crystal layer formation wafer and a transfer-destination wafer such that a first surface of the semiconductor crystal layer and a second surface of the transfer-destination wafer face each other, and splitting the transfer-destination wafer from the semiconductor crystal layer formation wafer with the semiconductor crystal layer remaining on the transfer-destination wafer side, by etching away the sacrificial layer by immersing the semiconductor crystal layer formation wafer and the transfer-destination wafer wholly or partially in an etchant. Here, the transfer-destination wafer includes an inflexible wafer and an organic material layer, and a surface of the organic material layer is the second surface..
|Adaptive fin design for finfets|
A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of finfets; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer..
|Light-emitting dies incorporating wavelength-conversion materials and related methods|
In accordance with certain embodiments, semiconductor dies are embedded within polymeric binder to form, e.g., light-emitting dies and/or composite wafers containing multiple light-emitting dies embedded in a single volume of binder.. .
|Wire-last integration method and structure for iii-v nanowire devices|
In one aspect, a method of fabricating a nanowire fet device includes the following steps. A layer of iii-v semiconductor material is formed on an soi layer of an soi wafer.
|Wire-last integration method and structure for iii-v nanowire devices|
In one aspect, a method of fabricating a nanowire fet device includes the following steps. A layer of iii-v semiconductor material is formed on an soi layer of an soi wafer.
|Method and apparatus for cleaning grinding work chuck using a scraper|
A scraper assembly for removing debris deposited on the surface of a porous work chuck during a wafer grinding process.. .
|Shower head unit and chemical vapor deposition apparatus|
A chemical vapor deposition apparatus comprises a chamber, a chamber lead having a gas in port configured to receive a reaction gas, the chamber lead connected to a top surface of the chamber to seal up the chamber, a shower head connected to the chamber lead, the shower head having a plurality of spray holes separated from each other for spraying the reaction gas onto the surface of a wafer in the chamber, and a protrusion surrounding the spray holes on the bottom surface of the shower head so that an induction groove is provided inside the protrusion, wherein the plurality of spray holes have a plurality of main holes and a plurality of supplementary holes, each of the main holes is uniformly arranged in each corner of a square-grid pattern across the shower head and each of the supplementary holes is disposed at each centerpoint of the square-grid pattern.. .
|Vertical diffusion furnace|
A diffusion furnace includes a boat which supports a semiconductor wafer thereon and is rotatable together with the semiconductor wafer. A heater is arranged on the periphery of a core tube which houses the boat therein.
|Substrate processing apparatus and susceptor|
A substrate processing apparatus includes a chamber, a susceptor to receive a substrate and provided in the chamber, a gas supply source to supply a predetermined gas into the chamber, and a high frequency power source to treat the substrate by plasma. The susceptor includes a first ceramics base member including a flow passage to let a coolant pass through, a first conductive layer formed on a principal surface and a side surface on a substrate receiving side of the first ceramics base member, and an electrostatic chuck stacked on the first conductive layer and configured to electrostatically attract the wafer received thereon.
|Wafer processing system using multi-zone chuck|
A wafer processing system includes at least one metrology chamber, a process chamber, and a controller. The at least one metrology chamber is configured to measure a thickness of a first layer on a back side of a wafer.
|Methods of attaching a module on wafer substrate|
Aspects of the present disclosure describe an attachment device for mounting a module to a substrate comprises a module leg with two ends and a module foot. One end of the module leg is configured to be attached to a bottom surface of the module and the other end of the module leg is configured to be attached to the module foot.
|Determining overall optimal yield point for a semiconductor wafer|
A computer determines a component optimal yield point for each component of the plurality of components, where the component optimal yield point represents the process parameter values where maximum yield is achieved for a component. The computer determines a weight factor for each component of the plurality of components, where the weight factor represents an importance of a component to the semiconductor device.
|Leak proof equipment and method for the collection of stoma body wastes|
An apparatus and system for reducing the area of exposure of intestinal effluent on a stoma wafer by 90% to 100%. The apparatus consists of substituting the pouch on a ring of a mechanically connecting ring ostomy pouch and wafer assembly by a membrane.
|Semiconductor device and method of forming through-silicon-via with sacrificial layer|
A semiconductor device can be formed by first providing a semiconductor wafer, and forming a conductive via into the semiconductor wafer. A portion of the semiconductor wafer can be removed so that the conductive via extends above a surface of the semiconductor wafer.
|Methods for forming semiconductor devices using sacrificial layers|
A fabricating method for a semiconductor device is provided. The fabricating method includes providing a first wafer, forming a sacrificial layer on the first wafer, forming a release layer on the sacrificial layer, forming an adhesive layer on the release layer, and placing a second wafer on the adhesive layer and bonding the first wafer to the second wafer..
|Quantum cascade laser manufacturing method|
A quantum cascade laser manufacturing method includes: a step of pressing a mother stamper against a resin film having flexibility to make a resin stamper 201 having a second groove pattern p2; a step of making a wafer with an active layer formed on a semiconductor substrate; a step of forming a resist film 304 on a surface on the active layer side of the wafer; a step of pressing the resin stamper against the resist film 304 by air pressure to form a third groove pattern p3 on the resist film 304; and a step of etching the wafer with the resist film 304 serving as a mask to form a diffraction grating on a surface of the wafer.. .
|Method and system for universal target based inspection and metrology|
Universal target based inspection drive metrology includes designing a plurality of universal metrology targets measurable with an inspection tool and measurable with a metrology tool, identifying a plurality of inspectable features within at least one die of a wafer using design data, disposing the plurality of universal targets within the at least one die of the wafer, each universal target being disposed at least proximate to one of the identified inspectable features, inspecting a region containing one or more of the universal targets with an inspection tool, identifying one or more anomalistic universal targets in the inspected region with an inspection tool and, responsive to the identification of one or more anomalistic universal targets in the inspected region, performing one or more metrology processes on the one or more anomalistic universal metrology targets with the metrology tool.. .
|Semiconductor wafer handling transport|
Modular wafer transport and handling facilities are combined in a variety of ways deliver greater levels of flexibility, utility, efficiency, and functionality in a vacuum semiconductor processing system. Various processing and other modules may be interconnected with tunnel-and-cart transportation systems to extend the distance and versatility of the vacuum environment.
|Epitaxial formation mechanisms of source and drain regions|
The embodiments of mechanisms for monitoring thermal budget of an etch process of a cyclic deposition/etch (cde) process to form an epitaxially grown silicon-containing material are descried to enable and to improve process control of the material formation. The monitoring is achieved by measuring the temperature of each processed wafer as a function of process time to calculate the accumulated thermal budget (atb) of the wafer and to compare the atb with a reference atb (or optimal accumulated thermal budget, oatb) to see if the processed wafer is within an acceptable range (or tolerance).
The present invention provides a light source for light circuits on a silicon platform. A vertical laser cavity is formed by a gain region arranged between a first mirror structure and a second mirror structure, both acting as mirrors, by forming a grating region including an active material in a silicon layer in a semiconductor structure or wafer structure.
|At least one die produced, at least in part, from wafer, and including at least one replicated integrated circuit|
An embodiment may include at least one die produced, at least in part, from a wafer, and may include at least one integrated circuit and/or at least one other integrated circuit. These integrated circuits may be mutual replications of each other and may include respective core and additional blocks.
|Surface shape measuring apparatus|
In related art, consideration is not given to that a spatial distribution of scattered light changes in various direction such as forward/backward/sideways according to a difference in micro roughness. Particularly, although a step-terrace structure appearing on an epitaxial growth wafer produces anisotropy in the scattered light distribution, consideration is not given to this point in the related art.
|Process for producing chip|
A process for producing a chip in which plural ejection orifice arrays are arranged including conducting reduction projection exposure plural times to a wafer having a substrate and a photosensitive resin layer formed thereon while relatively moving positions of the wafer and a reticle to form ejection orifice array patterns in the resin layer, developing the patterns to form ejection orifice arrays in the resin layer, and dividing the wafer to form plural chips in which the plural ejection orifice arrays are arranged. The exposure is conducted once to form in the resin layer a first ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction thereof in one chip, a second ejection orifice array pattern corresponding to all ejection orifice arrays in one chip and a third ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction thereof in one chip..
|Maintaining a wafer/wafer translator pair in an attached state free of a gasket disposed|
A wafer translator and a wafer, removably attached to each other, provides the electrical connection to electrical contacts on integrated circuits on a wafer in such a manner that the electrical contacts are substantially undamaged in the process of making such electrical connections. Various embodiments of the present invention provide a gasketless sealing means for facilitating the formation by vacuum attachment of the wafer/wafer translator pair.
|Detecting apparatus, wafer and electronic device|
Provided is a detection apparatus that detects process variation in a plurality of comparators that each output a comparison result obtained by comparing a signal level of an input signal to a reference level, the detection apparatus comprising a signal input section that inputs the input signal and the reference level in common to the comparators, and sequentially changes the signal level of the input signal; and a detecting section that detects, for each signal level, a number of comparison results that indicate a predetermined result, from among the comparison results of the comparators, and detects the process variation based on a distribution of the number of comparison results that indicate the predetermined result.. .
|Extended redistribution layers bumped wafer|
A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape.
|Wafer-level packaging mechanisms|
A semiconductor package includes a first semiconductor die surrounded by a molding compound. The semiconductor package further includes a first conductive pad on the first semiconductor die, wherein the first conductive pad is at a top metal level of the first semiconductor die.
|Methods for forming backside illuminated image sensors with front side metal redistribution layers|
Methods for forming backside illuminated (bsi) image sensors having metal redistribution layers (rdl) and solder bumps for high performance connection to external circuitry are provided. In one embodiment, a bsi image sensor with rdl and solder bumps may be formed using a temporary carrier during manufacture that is removed prior to completion of the bsi image sensor.
|Substrate free led package|
A method of fabricating a substrate free light emitting diode (led), includes arranging led dies on a tape to form an led wafer assembly, molding an encapsulation structure over at least one of the led dies on a first side of the led wafer assembly, removing the tape, forming a dielectric layer on a second side of the led wafer assembly, forming an oversized contact region on the dielectric layer to form a virtual led wafer assembly, and singulating the virtual led wafer assembly into predetermined regions including at least one led. The tape can be a carrier tape or a saw tape.
|Techniques for forming optoelectronic devices|
Embodiments relate to use of a particle accelerator beam to form thin films of material from a bulk substrate. In particular embodiments, a bulk substrate (e.g.
|Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device|
A methodology enabling the formation of steep channel profiles for devices, such as ssrw fets, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing sti regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between sti regions; forming a recess in the doped silicon wafer between the sti regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming si:c on the doped silicon wafer in the recess..
|Wafer holding apparatus|
A wafer holding apparatus including a container body having a space to receive a wafer and a front opening, a door disposed at the front opening, and a first supporting part disposed on an inner wall of the door may be provided. For example, the first supporting part may include a frame coupled to the inner wall of the door, a plurality of elastic ribs protruding from the frame, a support structure coupled to the plurality of elastic ribs and defining a plurality of grooves, which is spaced apart from the door by the elastic ribs and configured to receive a peripheral portion of the wafer..
|Treatment method of electrodeposited copper for wafer-level-packaging process flow|
A method of treating a copper containing structure on a substrate is disclosed. The method includes electrodepositing the copper containing structure on a substrate, annealing the copper containing structure, and forming an interface between a pad of the copper containing structure and a solder structure after anneal.