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Chemical mechanical planarization platen

Laser-based materials processing apparatus, method and applications

Process and apparatus for treating surfaces of wafer-shaped articles

Date/App# patent app List of recent Wafer-related patents
 Method of calibrating target values and processing systems configured to calibrate the target values patent thumbnailMethod of calibrating target values and processing systems configured to calibrate the target values
A processing method includes processing a wafer based on initial data, measuring errors for each of the plurality of areas, calculating an error similarity of at least some of the plurality of areas as a function of a separation distance between each pair of some of the areas, selecting a first area and a plurality of second areas adjacent to the first area, calculating weight values for the second areas based on the error similarities between each pair of second areas and the error similarities between the first area and each second area, calculating an estimated error of the first area based on the measured errors of the second areas and the weight values for the second areas, and generating estimated data based on the estimated errors for each of the plurality of areas.. .
 Chemical mechanical planarization platen patent thumbnailChemical mechanical planarization platen
A method and system for planarizing or polishing a semiconductor wafer. The system includes a carrier adaptable to hold a semiconductor wafer, a polishing pad, and a platen having a substantially planar surface in contact with the polishing pad, the planar surface having a distribution of holes.
 Laser-based materials processing apparatus, method and applications patent thumbnailLaser-based materials processing apparatus, method and applications
In a particular embodiment, a relatively high-energy thulium fiber laser operating at the wavelength λ=2 μm may be used to selectively modify a front and/or a back surface of silicon and gallium arsenide wafers. The processing regime was studied in terms of the process parameters variation, and the corresponding modification fluence thresholds were determined.
 Process and apparatus for treating surfaces of wafer-shaped articles patent thumbnailProcess and apparatus for treating surfaces of wafer-shaped articles
An apparatus and method for processing wafer-shaped articles utilizes at least first and second liquid-dispensing nozzles, wherein a first liquid-dispensing nozzle is positioned closer to an axis of rotation than the second liquid-dispensing nozzle. A liquid supply system supplies heated process liquid to the nozzles such that process liquid dispensed from the first nozzle has a temperature that differs by an amount within a predetermined range from a temperature of process liquid dispensed from the second liquid-dispensing nozzle..
 Cleaning method, processing apparatus, and storage medium patent thumbnailCleaning method, processing apparatus, and storage medium
Deposits such as particles deposited on a surface of a target object can be easily removed while suppressing damage to the target object such as destruction of pattern formed on the surface of the target object or film roughness on the surface of the target object. In a pre-treatment, vapor of a hydrogen fluoride is supplied to a wafer w to dissolve a natural oxide film 11, so that a deposit 10 attached to a surface of the natural oxide film 11 is slightly separated from a surface of the wafer w.
 Method for manufacturing small-size fin-shaped structure patent thumbnailMethod for manufacturing small-size fin-shaped structure
A method for manufacturing a small-size fin-shaped structure, comprising: forming a first mask layer and a second mask layer on a substrate in sequence; etching the first mask layer and the second mask layer to form a hard mask pattern, wherein a second mask layer pattern is wider than a first mask layer pattern; eliminating the second mask layer pattern; and performing a dry etching of the substrate by taking the first mask layer pattern as a mask, so as to form a fin-shaped structure. According to the method for manufacturing a small-size fin-shaped structure of the present invention, firstly a large-size hard mask is prepared, then a width controllable small-size hard mask is prepared through a wet corrosion, and finally the bulk silicon wafer is etched, so as to obtain the required small-size fin-shaped structure, thereby improving the electrical properties and the integration level of the device, simplifying the processes and reducing the cost..
 Method for incorporating stress sensitive chip scale components into reconstructed wafer based modules patent thumbnailMethod for incorporating stress sensitive chip scale components into reconstructed wafer based modules
Techniques for constructing an electronic module are provided herein. For example, the techniques include orienting at least one die having a top side (e.g., a first side), a bottom side (e.g., a second side) and one or more side walls, on a substrate with the top side of the die proximate the substrate, coating the bottom side and each of the side walls of the die with a stress buffer material, forming a reconstructed wafer by encapsulating the coated die within a mold compound, and removing the substrate to expose the top side of the die..
 Method to package multiple mems sensors and actuators at different gases and cavity pressures patent thumbnailMethod to package multiple mems sensors and actuators at different gases and cavity pressures
A method for fabricating a multiple mems device. A semiconductor substrate having a first and second mems device, and an encapsulation wafer with a first cavity and a second cavity, which includes at least one channel, can be provided.
 Method of manufacturing light emitting element patent thumbnailMethod of manufacturing light emitting element
A light emitting element for flip-chip mounting having a flat mounting surface which allows a decrease in the width of the streets of a wafer. In the light emitting element, the insulating member filling around the bumps and flattening the upper surface is formed with a margin of a region with a width which is equal to or larger than the width of the streets on the dividing lines, so that at the time of dividing the wafer along the dividing lines, the insulating member is not processed, which allows designing of the streets with a small width..
 Buffer material for packing wafer carrier patent thumbnailBuffer material for packing wafer carrier
At the time of packing a wafer carrier into a container, an upper buffer body and a lower buffer body are arranged above and below the wafer carrier. The wafer carrier has: a box-like carrier main body having a frame-like step portion formed on an upper inner peripheral surface of an access opening; and a lid body that closes the access opening in an openable manner when it is accommodated in the frame-like step portion through a gasket.
Device and method for coating of a carrier wafer
A device and corresponding method for coating of an inner circular surface of a coating surface of a carrier wafer with a coating material. The device includes an application means for applying a coating material intended for coating of the inner circular surface to the inner circular surface, a rotating means for accommodating and rotating the carrier wafer around an axis of rotation and for distribution of the coating material on the coating surface, and a second application means for applying a coating inhibitor to an outer circular ring surface which surrounds the inner circular surface, said coating inhibitor at least inhibits the coating of the outer circular ring surface during the distribution of the coating material..
Wafer transfer blade and wafer transfer apparatus having the same
A wafer transfer blade including a body including metal oxide and configured to support a wafer, and an adsorbing part on the body, the adsorbing part having at least one therein and configured to apply vacuum pressure to attach the wafer on the body may be provided. The body may include metal oxide to prevent static electricity..
Method and system for image-based defect alignment
The present disclosure provides one embodiment of a method for defect diagnosis to a semiconductor wafer. The method includes collecting raw data that include a defect image (img), defect coordinate-on-wafer (cw) and layout database (db); performing an image-based defect alignment to img according to cw and db; and compensating coordinate mismatch according to the image-based defect alignment..
Iii-v photonic crystal microlaser bonded on silicon-on-insulator
Novel methods and systems for miniaturized lasers are described. A photonic crystal is bonded to a silicon-on-insulator wafer.
Wafer back side coating as dicing tape adhesive
A semiconductor assembly comprises a semiconductor wafer, an adhesive coating disposed on the back side of the wafer, and a bare dicing tape, preferably uv radiation transparent. The assembly is prepared by the method comprising (a) providing a semiconductor wafer, (b) disposing a wafer back side coating on the semiconductor wafer, (c) partially curing the wafer back side coating to the extent that it adheres to the back side of the wafer and remains tacky, and (d) contacting the bare dicing tape to the partially cured and tacky wafer back side coating, optionally with heat and pressure..
Semiconductor device and method of forming insulating layer in notches around conductive tsv for stress relief
A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer.
Solderless die attach to a direct bonded aluminum substrate
A dba-based power device includes a dba (direct bonded aluminum) substrate. An amount of silver nanoparticle paste of a desired shape and size is deposited (for example by micro-jet deposition) onto a metal plate of the dba.
On-track reverse lithography to thin mask for fabrication of dark-field features
A reversal lithography approach is disclosed in which dark-field features are created on microelectronic substrates using bright-field lithography processes and a pattern reversal method. A wafer stack having a patterned imaging layer is provided that has a plurality of features formed thereon.
Method for embedding a chipset having an intermediary interposer in high density electronic modules
A method for creating a high density electronic module including the steps of coupling a die to an interposer for form a chipset, mounting the chipset to a substrate, coupling a wafer to the substrate so that the chipset is within a window formed in the wafer, filling the window with encapsulant to encapsulate the chipset, removing the substrate to create a reconstructed wafer, and providing an interconnection structure on the interposer to form the high density electronic module.. .
Layer arrangement
A layer arrangement in accordance with various embodiments may include: a wafer; a passivation disposed over the wafer; a protection layer disposed over at least a surface of the passivation facing away from the wafer; and a mask layer disposed over at least a surface of the protection layer facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation, and wherein the mask layer includes a material that is selectively etchable to the material of the protection layer.. .
Modulating bow of thin wafers
Apparatus and methods modulate the bowing of thin wafers. According to a method, a wafer is formed of semiconductor material.
Semiconductor package and method of forming the same
Provided are semiconductor packages and methods of forming the same. A sidewall of a semiconductor chip in the package is exposed.
Ion reduced, ion cut-formed three-dimensional (3d) integrated circuits (ic) (3dics), and related methods and systems
Ion-reduced, ion cut-formed three-dimensional (3d) integrated circuits (ic) (3dics) are disclosed. Related methods and systems are also disclosed.
Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry
In accordance with the invention, an improved image sensor comprises an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques.
Substrate having a charged zone in an insulating buried layer
A substrate comprises a base wafer, an insulating layer over the base wafer, and a top semiconductor layer over the insulating layer on a side thereof opposite the base wafer. The insulating layer comprises a charge-confining layer confined on one or both sides with diffusion barrier layers, wherein the charge-confining layer has a density of charges in absolute value higher than 1010 charges/cm2.
Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
An soi wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (box) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed.
Composite wafer and a method for manufacturing same
A composite wafer includes a substrate and a sic-based functional layer. The substrate includes a porous carbon substrate core and an encapsulating layer encapsulating the substrate core.
Die testing using top surface test pads
Timely testing of die on wafer reduces the cost to manufacture ics. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die.
Methods of fabricating microelectronic substrate inspection equipment
Microelectronic substrate inspection equipment includes a gas container which contains helium gas, a helium ion generator which is disposed in the gas container and converts the helium gas into helium ions and a wafer stage which is disposed under the gas container and on which a substrate to be inspected is placed. The equipment further includes a secondary electron detector which is disposed above the wafer stage and detects electrons generated from the substrate, a compressor which receives first gaseous nitrogen from a continuous nitrogen supply device and compresses the received first gaseous nitrogen into liquid nitrogen, a liquid nitrogen dewar which is connected to the compressor and stores the liquid nitrogen, and a cooling device that is coupled to the helium ion generator.
Separation of doping density and minority carrier lifetime in photoluminescence measurements on semiconductor materials
Methods are presented for separating the effects of background doping density and effective minority carrier lifetime on photoluminescence (pl) generated from semiconductor materials. In one embodiment the background doping density is measured by another technique, enabling pl measurements to be analysed in terms of effective minority carrier lifetime.
Apparatus to improve internal wafer temperature profile
Some embodiments relate to methods and apparatus for providing a homogeneous wafer temperature profile in a wafer cleaning tool without introducing unwanted particles onto the wafer. In some embodiments, a disclosed wafer cleaning tool has a processing chamber configured to house a semiconductor wafer.
Metal filling device
A metal filling apparatus 1 fills a molten metal m into a minute space formed on a surface of a semiconductor wafer k. The metal filling apparatus 1 has a processor body 2 having a processing chamber 5 in which the semiconductor wafer k is held, a molten metal supply mechanism 10, and a molten metal recovery mechanism 20.
Trench process and structure for backside contact solar cells with polysilicon doped regions
A solar cell includes polysilicon p-type and n-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the p-type doped region from the n-type doped region.
Solar cell and method for producing same
A solar cell includes a semiconductor wafer, at least one dielectric layer arranged on the semiconductor wafer, a metal layer arranged on the dielectric layer, and a contact structure arranged in the dielectric layer such that the contact structure provides an electrical connection between the metal layer and the semiconductor wafer. The contact structure has at least one first structure having a minimum dimension and at least one second structure having a maximum dimension, wherein the minimum dimension and the maximum dimension are defined along a surface of the semiconductor wafer and the minimum dimension of the first structure is greater than the maximum dimension of the second structure..
Mocvd apparatus
A metal-organic chemical vapor deposition (mocvd) apparatus includes: a reaction chamber including a chamber main body forming an interior space having a certain volume and a chamber cover hermetically sealing the chamber main body to maintain air-tightness; a susceptor rotatably provided within the chamber main body and having one or more accommodation portions formed in an upper surface thereto to accommodate wafers; a cover member detachably provided on an interior surface of the chamber cover, forming a reaction space between the cover member and the susceptor, and formed by coupling a plurality of section members; and a gas supply unit supplying a reactive gas to the reaction space to allow the reactive gas to flow between the susceptor and the cover member.. .
Transfer position teaching method, transfer position teaching apparatus and substrate processing apparatus
The transfer position teaching apparatus is provided with a teaching substrate having a shape identical to a semiconductor wafer to be processed by substrate processing apparatuses and having an electrically conductive coating thereon. The transfer position teaching apparatus is also provided with a base member having insulator coating thereon and on the base member, entrance contact members, y-direction contact members, x-direction contact member are vertically arranged..
Vertically aligned mesoporous thin film, method of manufacturing the same, and catalytic application thereof
This invention relates to a vertically aligned mesoporous silicate film with site-selective metal deposition from a single polymeric precursor and to diverse catalytic applications thereof. There is an innovative approach of a single precursor to manufacture a vertically aligned mesoporous silicate thin film having high thermal and chemical resistance on a large-area silicon wafer (2 cm×3 cm).
Resist technique
The present disclosure provides various methods for removing a resist layer from a wafer. An exemplary method includes performing an etching process to remove a resist layer from a wafer.
Method for separating support substrate from solid-phase bonded wafer and method for manufacturing semiconductor device
A method is disclosed for separating a support substrate from a solid-phase bonded wafer which includes a si wafer and support substrate solid-phase bonded to back surface of the si wafer. The method includes a step of irradiating the si wafer with laser light with a wavelength which passes through the si wafer and is focused on a solid-phase bonding interface between the si wafer and support substrate to form a breaking layer in at least part of an outer circumferential portion of the solid-phase bonding interface, a step of separating the breaking layer; and a step of separating the solid-phase bonding interface.
Thin film wafer transfer and structure for electronic devices
A method for wafer transfer includes forming a spreading layer, including graphene, on a single crystalline sic substrate. A semiconductor layer including one or more layers is formed on and is lattice matched to the crystalline sic layer.
Method of manufacturing semiconductor device, semiconductor device and multilayer wafer structure
Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line.
Method and apparatus for a wafer seal ring
A wafer seal ring may be formed on a wafer having a pattern structure with a pattern density. The wafer seal ring pattern structure may include a plurality of lines having a width and a spacing that may be approximately equal to a width and a spacing of die bond rings on the wafer.
Method of attaching a light emitting device to a support substrate
A method according to embodiments of the invention includes providing a wafer of semiconductor light emitting devices, each semiconductor light emitting device including a light emitting layer sandwiched between an n-type region and a p-type region. A wafer of support substrates is provided, each support substrate including a body.
Imaging device, semiconductor manufacturing apparatus, and semiconductor manufacturing method
There are provided a susceptor having a recessed wafer mounting section, in which a semiconductor wafer is mounted and which is configured to include a circular bottom portion and a side wall portion, on an upper surface, a reaction chamber in which the susceptor is provided, an imaging unit that is provided above the reaction chamber and images the semiconductor wafer and the wafer mounting section, and an image analysis unit that analyzes the deviation of the semiconductor wafer from the wafer mounting section on the basis of an image captured by the imaging unit.. .
Controlling cd and cd uniformity with trim time and temperature on a wafer by wafer basis
Exemplary embodiments are directed to controlling cd uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone.
Method for forming patterns
A method for forming patterns includes the following steps. A first layout including a first target pattern and a first unprintable dummy pattern is provided.
Adhesive compositions for use in die attach applications
Novel adhesive compositions that can be used in the die attach process. The adhesives include a curable resin component, a curing agent, and a block copolymer additive.
Sic crystal and wafer cut from crystal with low dislocation density
A method of forming an sic crystal including placing in an insulated graphite container a seed crystal of sic, and supporting the seed crystal on a shelf, wherein cushion rings contact the seed crystal on a periphery of top and bottom surfaces of the seed crystal, and where the graphite container does not contact a side surface of the seed crystal; placing a source of si and c atoms in the insulated graphite container, where the source of si and c atoms is for transport to the seed crystal to grow the sic crystal; placing the graphite container in a furnace; heating the furnace; evacuating the furnace; filling the furnace with an inert gas; and maintaining the furnace to support crystal growth to thereby form the sic crystal.. .
Substrate processing apparatus and method of depositing a film
A substrate processing apparatus for performing a plasma process inside a vacuum chamber includes a turntable including substrate mounting portions for the substrates formed along a peripheral direction of the vacuum chamber to orbitally revolve these; a plasma generating gas supplying portion supplying a plasma generating gas into a plasma generating area; an energy supplying portion supplying energy to the plasma generating gas to change the plasma generating gas to plasma; a bias electrode provided on a lower side of the turntable to face the plasma generating area and leads ions in the plasma onto surfaces of the wafers; and an evacuation port evacuating the vacuum chamber, wherein the bias electrode extends from a rotational center of the turntable to an outer edge side, and a width of the bias electrode in a rotational direction is smaller than a distance between adjacent substrate mounting portions.. .
Apparati for fabricating thin semiconductor bodies from molten material
A pressure differential can be applied across a mold sheet and a semiconductor (e.g. Silicon) wafer (e.g.
Centering guide for wafers of different sizes
An apparatus for centering workpieces of different sizes, particularly wafers, featuring a single plane centering guide. The guide features a plate having a cutout region with a first arcuate cutout within which a portion of a circumference of a first circular workpiece is nestable and a second arcuate cutout adjacent to and deeper than the first arcuate cutout and centered along the cutout region within which a portion of a circumference of a smaller second circular workpiece is nestable.
Flexible 3-d photonic device
Three-dimensional flexible photonic integrated circuits on silicon are fabricated in semiconductor wafer form and then transferred to silicon-on-polymer (sop) substrates. Sop provides flexibility for conformal mounting with devices capable of maintaining performance when dynamically deformed to allow routing of light in x, y and z directions.
Semiconductor inspection system
When the lengths of fem wafers are automatically measured, not only the sizes of targets, the lengths of which are to be measured, are often varied from those in registration, but also the patterns of the targets are often deformed. Therefore, it is difficult to automatically determine whether the length measurement is possible or not.
Detecting defects on a wafer using defect-specific and multi-channel information
Methods and systems for detecting defects on a wafer using defect-specific and multi-channel information are provided. One method includes acquiring information for a target on a wafer.
Defect determination in integrated circuit manufacturing process
A method includes inspecting a wafer to find a first potential defect having a first wafer coordinate, and capturing a patch image of the first potential defect from the wafer. The patch image is compared with patterns of a wafer representation to find a first layout coordinate of a location in the wafer representation, wherein the location in the wafer representation corresponds to a location of the first potential defect in the wafer.
Cmos ultrasonic transducers and related apparatus and methods
Cmos ultrasonic transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer.

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Wafer topics: Semiconductor, Semiconductor Wafer, Gallium Nitride, Silicon Wafer, Semiconductor Device, Carbon Dioxide, Semiconductor Material, Carbonate Ion, Carbonic Anhydrase, Bicarbonate, Deionization, Distributed, Electronic Device, Accelerator, Ion Implant

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This listing is a sample listing of patent applications related to Wafer for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Wafer with additional patents listed. Browse our RSS directory or Search for other possible listings.

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