|| List of recent Wafer-related patents
| Determining overall optimal yield point for a semiconductor wafer|
A computer determines a component optimal yield point for each component of the plurality of components, where the component optimal yield point represents the process parameter values where maximum yield is achieved for a component. The computer determines a weight factor for each component of the plurality of components, where the weight factor represents an importance of a component to the semiconductor device.
| Leak proof equipment and method for the collection of stoma body wastes|
An apparatus and system for reducing the area of exposure of intestinal effluent on a stoma wafer by 90% to 100%. The apparatus consists of substituting the pouch on a ring of a mechanically connecting ring ostomy pouch and wafer assembly by a membrane.
| Semiconductor device and method of forming through-silicon-via with sacrificial layer|
A semiconductor device can be formed by first providing a semiconductor wafer, and forming a conductive via into the semiconductor wafer. A portion of the semiconductor wafer can be removed so that the conductive via extends above a surface of the semiconductor wafer.
| Methods for forming semiconductor devices using sacrificial layers|
A fabricating method for a semiconductor device is provided. The fabricating method includes providing a first wafer, forming a sacrificial layer on the first wafer, forming a release layer on the sacrificial layer, forming an adhesive layer on the release layer, and placing a second wafer on the adhesive layer and bonding the first wafer to the second wafer..
| Quantum cascade laser manufacturing method|
A quantum cascade laser manufacturing method includes: a step of pressing a mother stamper against a resin film having flexibility to make a resin stamper 201 having a second groove pattern p2; a step of making a wafer with an active layer formed on a semiconductor substrate; a step of forming a resist film 304 on a surface on the active layer side of the wafer; a step of pressing the resin stamper against the resist film 304 by air pressure to form a third groove pattern p3 on the resist film 304; and a step of etching the wafer with the resist film 304 serving as a mask to form a diffraction grating on a surface of the wafer.. .
| Method and system for universal target based inspection and metrology|
Universal target based inspection drive metrology includes designing a plurality of universal metrology targets measurable with an inspection tool and measurable with a metrology tool, identifying a plurality of inspectable features within at least one die of a wafer using design data, disposing the plurality of universal targets within the at least one die of the wafer, each universal target being disposed at least proximate to one of the identified inspectable features, inspecting a region containing one or more of the universal targets with an inspection tool, identifying one or more anomalistic universal targets in the inspected region with an inspection tool and, responsive to the identification of one or more anomalistic universal targets in the inspected region, performing one or more metrology processes on the one or more anomalistic universal metrology targets with the metrology tool.. .
| Semiconductor wafer handling transport|
Modular wafer transport and handling facilities are combined in a variety of ways deliver greater levels of flexibility, utility, efficiency, and functionality in a vacuum semiconductor processing system. Various processing and other modules may be interconnected with tunnel-and-cart transportation systems to extend the distance and versatility of the vacuum environment.
| Epitaxial formation mechanisms of source and drain regions|
The embodiments of mechanisms for monitoring thermal budget of an etch process of a cyclic deposition/etch (cde) process to form an epitaxially grown silicon-containing material are descried to enable and to improve process control of the material formation. The monitoring is achieved by measuring the temperature of each processed wafer as a function of process time to calculate the accumulated thermal budget (atb) of the wafer and to compare the atb with a reference atb (or optimal accumulated thermal budget, oatb) to see if the processed wafer is within an acceptable range (or tolerance).
| Laser device|
The present invention provides a light source for light circuits on a silicon platform. A vertical laser cavity is formed by a gain region arranged between a first mirror structure and a second mirror structure, both acting as mirrors, by forming a grating region including an active material in a silicon layer in a semiconductor structure or wafer structure.
| At least one die produced, at least in part, from wafer, and including at least one replicated integrated circuit|
An embodiment may include at least one die produced, at least in part, from a wafer, and may include at least one integrated circuit and/or at least one other integrated circuit. These integrated circuits may be mutual replications of each other and may include respective core and additional blocks.
| Surface shape measuring apparatus|
In related art, consideration is not given to that a spatial distribution of scattered light changes in various direction such as forward/backward/sideways according to a difference in micro roughness. Particularly, although a step-terrace structure appearing on an epitaxial growth wafer produces anisotropy in the scattered light distribution, consideration is not given to this point in the related art.
| Process for producing chip|
A process for producing a chip in which plural ejection orifice arrays are arranged including conducting reduction projection exposure plural times to a wafer having a substrate and a photosensitive resin layer formed thereon while relatively moving positions of the wafer and a reticle to form ejection orifice array patterns in the resin layer, developing the patterns to form ejection orifice arrays in the resin layer, and dividing the wafer to form plural chips in which the plural ejection orifice arrays are arranged. The exposure is conducted once to form in the resin layer a first ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction thereof in one chip, a second ejection orifice array pattern corresponding to all ejection orifice arrays in one chip and a third ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction thereof in one chip..
| Maintaining a wafer/wafer translator pair in an attached state free of a gasket disposed|
A wafer translator and a wafer, removably attached to each other, provides the electrical connection to electrical contacts on integrated circuits on a wafer in such a manner that the electrical contacts are substantially undamaged in the process of making such electrical connections. Various embodiments of the present invention provide a gasketless sealing means for facilitating the formation by vacuum attachment of the wafer/wafer translator pair.
| Detecting apparatus, wafer and electronic device|
Provided is a detection apparatus that detects process variation in a plurality of comparators that each output a comparison result obtained by comparing a signal level of an input signal to a reference level, the detection apparatus comprising a signal input section that inputs the input signal and the reference level in common to the comparators, and sequentially changes the signal level of the input signal; and a detecting section that detects, for each signal level, a number of comparison results that indicate a predetermined result, from among the comparison results of the comparators, and detects the process variation based on a distribution of the number of comparison results that indicate the predetermined result.. .
| Extended redistribution layers bumped wafer|
A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape.
| Wafer-level packaging mechanisms|
A semiconductor package includes a first semiconductor die surrounded by a molding compound. The semiconductor package further includes a first conductive pad on the first semiconductor die, wherein the first conductive pad is at a top metal level of the first semiconductor die.
| Methods for forming backside illuminated image sensors with front side metal redistribution layers|
Methods for forming backside illuminated (bsi) image sensors having metal redistribution layers (rdl) and solder bumps for high performance connection to external circuitry are provided. In one embodiment, a bsi image sensor with rdl and solder bumps may be formed using a temporary carrier during manufacture that is removed prior to completion of the bsi image sensor.
| Substrate free led package|
A method of fabricating a substrate free light emitting diode (led), includes arranging led dies on a tape to form an led wafer assembly, molding an encapsulation structure over at least one of the led dies on a first side of the led wafer assembly, removing the tape, forming a dielectric layer on a second side of the led wafer assembly, forming an oversized contact region on the dielectric layer to form a virtual led wafer assembly, and singulating the virtual led wafer assembly into predetermined regions including at least one led. The tape can be a carrier tape or a saw tape.
| Techniques for forming optoelectronic devices|
Embodiments relate to use of a particle accelerator beam to form thin films of material from a bulk substrate. In particular embodiments, a bulk substrate (e.g.
| Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device|
A methodology enabling the formation of steep channel profiles for devices, such as ssrw fets, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing sti regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between sti regions; forming a recess in the doped silicon wafer between the sti regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming si:c on the doped silicon wafer in the recess..
| Wafer holding apparatus|
A wafer holding apparatus including a container body having a space to receive a wafer and a front opening, a door disposed at the front opening, and a first supporting part disposed on an inner wall of the door may be provided. For example, the first supporting part may include a frame coupled to the inner wall of the door, a plurality of elastic ribs protruding from the frame, a support structure coupled to the plurality of elastic ribs and defining a plurality of grooves, which is spaced apart from the door by the elastic ribs and configured to receive a peripheral portion of the wafer..
| Treatment method of electrodeposited copper for wafer-level-packaging process flow|
A method of treating a copper containing structure on a substrate is disclosed. The method includes electrodepositing the copper containing structure on a substrate, annealing the copper containing structure, and forming an interface between a pad of the copper containing structure and a solder structure after anneal.
| Method and system for wafer level singulation|
A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices.
| Method and device for bonding two wafers|
A device for bonding of two wafers on one joining surface v of the wafers. The device includes a pressure transfer means with a pressure surface d for applying a bond pressure to the two wafers on the pressure surface d, wherein the pressure surface d is smaller than the joining surface v.
| Method and device for permanent bonding of wafers, as well as cutting tool|
Exposing the solid substrates that are in contact to temperature in order to form a permanent bond that is at least primarily produced by recrystallization at the bond surfaces.. .
| In situ chamber clean with inert hydrogen helium mixture during wafer process|
Embodiments of the present invention generally relate to a method for cleaning a processing chamber during substrate processing. During a first substrate processing step, a plasma is formed from a gas mixture of argon, helium, and hydrogen in the processing chamber.
| Baking plate for baking ovens|
A baking plate for a baking oven for producing baked products such as soft waffles, crispy wafers, pancakes and the like. The baking plate has a carrier plate and one or more baking inserts disposed thereon, which are configured for receiving the batter to be baked.
|Determining a position of inspection system output in design data space|
Systems and methods for determining a position of output of an inspection system in design data space are provided. One method includes merging more than one feature in design data for a wafer into a single feature that has a periphery that encompasses all of the features that are merged.
|Gas purifier for wafer substrate accommodating unit|
A gas purifier to be applied on a wafer substrate accommodating unit with an inlet hole includes an outer tube and an inner tube. The outer tube is disposed on the wafer substrate accommodating unit and has a plurality of first gas filling apertures.
|Apparatus and method for reducing residual stress of semiconductor|
An apparatus for reducing residual stress of a semiconductor includes a stage configured to support a semiconductor wafer having the residual stress generated by a semiconductor manufacturing process. The apparatus includes an intense pulsed light (ipl) irradiation unit configured to irradiate ipl to the semiconductor wafer to reduce the residual stress of the semiconductor wafer, the ipl radiation unit being separated from the stage.
|Integrated bondline spacers for wafer level packaged circuit devices|
A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.. .
|Method of bonding a substrate to a semiconductor light emitting device|
A method according to embodiments of the invention includes positioning a flexible film (48) over a wafer of semiconductor light emitting devices, each semiconductor light emitting device including a semiconductor structure (13) including a light emitting layer sandwiched between an n-type region and a p-type region. The wafer of semiconductor light emitting devices is bonded to a substrate (50) via the flexible film (48).
|Detecting defects on a wafer using template image matching|
Various embodiments for detecting defects on a wafer are provided. Some embodiments include matching a template image, in which at least some pixels are associated with regions in the device having different characteristics, to output of an electron beam inspection system and applying defect detection parameters to pixels in the output based on the regions that the pixels in the output are located within to thereby detect defects on the wafer..
|High temperature sensor wafer for in-situ measurements in active plasma|
Aspects of the present disclosure disclose a component module in a process condition measuring device comprises a support for supporting a component, one or more legs configured to suspend the support in a spaced-apart relationship with respect to a substrate. An electrically conductive or low-resistivity semiconductor enclosure is configured to enclose the component, the support and the legs between the substrate and the enclosure.
|Mems device with sloped support|
A microelectromechanical (mems) device has a movable member supported in elevated position spaced by a sloped support structure above a substrate. The movable member may be a polished metallic plate such as a mirror of a digital micromirror device (dmd) supported by a flexible hinge above an integrated circuit wafer die region.
|Optical type inspection apparatus, inspection system and the wafer for coordinates management|
This optical inspection device has: a line sensor on which channels are arranged; a moving means for moving a wafer mounted on a stage relative to the line sensor; a stage position detection means for detecting the on-stage positions of pseudo-defects in images formed on the channels as pseudo-defect stage coordinates, said coordinate management wafer being a wafer on which one pseudo-defect die is formed per row and column of a matrix of dies and each pseudo-defect die has a plurality of pseudo-defects formed in a line in the columnar direction; a coordinate transformation means for transforming the pseudo-defect stage coordinates into pseudo-defect die coordinates; a difference computation means for computing the differences of the pseudo-defect die coordinates from design coordinates; and a characteristic pattern acquisition means for obtaining a coordinate error characteristic pattern in which the differences from the pseudo-defect stage coordinates increase or decrease along a straight line.. .
|Fixture planarity evaluation method|
Methods for determining the planarity of two components of a semiconductor processing tool, such as a 3d wafer bonder are disclosed. The two components may be fixtures, chucks, or platens of the tool.
|Euv exposure apparatus, euv mask, and method of measuring distortion|
An euv exposure apparatus according to embodiments includes a reticle stage which suctions a rear surface side of an euv mask to retain the euv mask. In addition, the euv exposure apparatus includes a detection unit which detects a position of a measurement mark formed on the rear surface of the euv mask in the state where the euv mask is suctioned on the reticle stage.
|Device for holding a planar substrate|
A device (1) for holding a planar substrate (4), in particular for a wafer or an ewlb, is shown, with a support (2) which forms a supporting surface (3) for the substrate (2) and has at least one recess (5) provided in the region of the supporting surface (3) for the substrate (2), and with at least one holding means which is connected in terms of flow to said recess (6) and is intended for fixing the substrate (2) on the device (1) with the aid of a vacuum generated between the support (2) and substrate (4). In order to be able to grip a multiplicity of substrates of geometrically differing profile, it is proposed that the support (2) has at least one recess (6) with an elastic seal (7) which is designed to be movable from a position (9) protruding over the edge (8) of the recess (6) into a position (10) pulled back in relation to the edge (8) of the recess (6) or at most corresponding to said edge and which interacts with the recess (5) for sucking the full area of the substrate (4) onto the support (2)..
|Methods for etching through-wafer vias in a wafer|
Apparatus and methods for plasma etching are disclosed. In one embodiment, a method for etching a plurality of features on a wafer includes positioning the wafer within a chamber of a plasma etcher, generating plasma ions using a radio frequency power source and a plasma source gas, directing the plasma ions toward the wafer using an electric field, and focusing the plasma ions using a plasma focusing ring.
|Method of fabricating land grid array semiconductor package|
A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package.
|Low-k chip packaging structure|
A low-k chip packaging structure comprising chip body i (2-1), a chip electrode (2-2), and a chip surface passivation layer (2-3). Chip body i (2-1) has coated thereon thin film layer i (2-3).
|Film thickness metrology|
Methods for determining a target thickness of a conformal film with reduced uncertainty, and an integrated circuit (ic) chip having a conformal film of the target thickness are provided. In an embodiment, a first critical dimension of a structure disposed on a wafer is measured.
|Composite wafer and method for manufacturing the same|
A composite wafer 10 includes a supporting substrate 12 and a semiconductor substrate 14 which are bonded to each other by direct bonding. The supporting substrate 12 is a translucent alumina substrate with an alumina purity of 99% or more.
|Silicon single crystal wafer, manufacturing method thereof and method of detecting defects|
A silicon single crystal wafer is provided. The silicon single crystal wafer includes an idp which is divided into an nig region and an nidp region, wherein the idp region is a region where a cu based defect is not detected, the nig region is a region where an ni based defect is detected and the nipd region is a region where an ni based defect is not detected..
|High-k and metal filled trench-type edram capacitor with electrode depth and dimension control|
Partial removal of organic planarizing layer (opl) material forms a plug of opl material within an aperture that protects underlying material or electronic device such as a deep trench capacitor during other manufacturing processes. The opl plug thus can absorb any differences or non-uniformity in, for example, etch rates across the chip or wafer and preserve recess dimensions previously formed.
|Semiconductor-on-oxide structure and method of forming|
Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer..
|Wafer-level packaging method of bsi image sensors having different cutting processes|
A wafer-level packaging method of bsi image sensors includes the following steps: s1: providing a wafer package body comprising a silicon base, an interconnect layer, a hollow wall and a substrate; s2: cutting the wafer package body via a first blade in a first cutting process to separate the interconnect layer of adjacent bsi image sensors; and s3: cutting the wafer package body via a second blade in a second cutting process to obtain independent bsi image sensors. As a result, damage of the interconnect layer and the substrate may be decreased to improve performance and reliability of the bsi image sensor..
|Bonding transistor wafer to led wafer to form active led modules|
Led modules are disclosed having a control mosfet, or other transistor, in series with an led. In one embodiment, a mosfet wafer, containing an array of vertical mosfets, is aligned and bonded to an led wafer, containing a corresponding array of vertical leds, and singulated to form thousands of active 3-terminal led modules with the same footprint as a single led.
|Self-formed nanometer channel at wafer scale|
A mechanism is provided for fabricating nanochannels for a nanodevice. Insulating film is deposited on a substrate.
|Wafer processing deposition shielding components|
Embodiments described herein generally relate to components for a semiconductor processing chamber, a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a process kit. In one embodiment a lower shield for encircling a sputtering target and a substrate support is provided.
|Method and apparatus for drying a wafer|
The present disclosure provides a method of fabricating a semiconductor device. The method includes dispensing a liquid on a wafer.
|Substrate cleaning apparatus and polishing apparatus|
A substrate cleaning apparatus capable of efficiently cleaning a substrate, such as a wafer, is provided. The substrate cleaning apparatus includes: a substrate holder for holding and rotating a substrate; a chemical liquid nozzle for supplying a chemical liquid onto the substrate; a two-fluid nozzle for supplying a two-fluid jet onto the substrate; and a moving mechanism for moving the chemical liquid nozzle and the two-fluid nozzle together from a center to a periphery of the substrate.
|Back-side electrode of p-type solar cell|
A back-side aluminum electrode adjacently formed on silicon wafer of p-type solar cell, comprising, (a) first aluminum layer and (b) second aluminum layer, wherein (a) first aluminum layer formed adjacent to the silicon wafer, formed from first aluminum paste comprises aluminum powder and glass frit, wherein the weight ratio of the glass frit for the aluminum powder (glass/aluminum) is 0.02-1.0, and wherein (b) second aluminum layer formed adjacent to the first aluminum layer, formed from second aluminum paste comprises at least aluminum powder, wherein the weight ratio (glass/aluminum) of the second aluminum paste is less than the weight ratio(glass/aluminum) of the first aluminum paste.. .
|Wafer scale thermoelectric energy harvester|
An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer.
|Wafer scale thermoelectric energy harvester|
An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer.
|Apparatus and method for edge bevel removal of copper from silicon wafers|
Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems provide the thin layer of pre-rinsing liquid before applying etchant at the edge bevel region of the wafer.
|Apparatus and method for treating substrate|
Provided is a substrate treatment apparatus. The substrate treatment apparatus includes a load port on which a carrier accommodating a plurality of substrates to which a back-ground wafer is attached to a mounting tape fixed to a frame ring is placed, a plasma treatment unit supplying plasma to treat a top surface of the wafer, and a substrate transfer unit transferring the substrate between the carrier and the plasma treatment unit..
|Self-cleaning shutter for cvd reactor|
A chemical vapor deposition reactor and a method of wafer processing are provided. The reactor can include a reaction chamber having an interior and an entry port for insertion and removal of substrates, a gas inlet manifold communicating with the interior of the chamber for admitting process gasses to form a deposit on substrates held within the interior, a shutter mounted to the chamber, and one or more cleaning elements mounted within the chamber.
|Epitaxial wafer manufacturing device and manufacturing method|
Provided is an epitaxial wafer manufacturing device (1) that deposits and grows epitaxial layers on the surfaces of wafers w while supplying a raw material gas to a chamber, wherein a shield (12), arranged in close proximity to the lower surface of a top plate (3) so as to prevent deposits from being deposited on the lower surface of the top plate (3), is removably attached inside the chamber, has an opening (13) in the central portion thereof that forces a gas inlet (9) to face the inside of a reaction space k, and has a structure in which it is concentrically divided into a plurality of ring plates (16), (17) and (18) around the opening (13).. .
|Chucking device and chucking method|
Provided are a chucking device having low dusting characteristics and high detergent properties and capable of vacuum-sucking even a substrate having a large warpage, and a chucking method using the same. A chucking device according to an aspect of the present invention vacuum-sucks and holds a wafer.
|Method for setting substrate-treatment time, and storage medium|
In a method for setting substrate-treatment time, substrate-treatment time is set by the following method. A predicted supply time of wafers of a following lot to a substrate processing apparatus is calculated based on a predicted plasma-treatment completion time of another substrate processing apparatus.