|| List of recent Volatile Memory-related patents
| System and method for live computer forensics|
Embodiments of a system and method for live computer forensics are generally described herein. The system can include a first hypervisor configured to halt a computer system, the computer system including a central processing unit, a drive, a volatile memory, and a non-volatile memory.
| Systems and methods to initiate updating of reference voltages|
In a data storage device that includes a non-volatile memory, a method includes determining that a current error correction code page count (cec) is at least as large as a target error correction code page count (tec). The cec is a page count of error correction code (ecc) pages of data read from the memory during a time period from a previous time to a particular time using a set of reference voltages.
| Memory system|
According to one embodiment, a memory module which includes a plurality of nonvolatile memory cells with a plurality of pages and line-and-space word lines to which more than one of the memory cells are connected, and a controller which receives write data from a host device.. .
| Semiconductor device and memory device|
A memory device includes a command decoder for generating a test selection code and a test setup data by decoding an external command and an external address, a non-volatile memory for storing an internal setup data, a counter for generating an internal selection code by counting a clock, a first selector for selecting the test selection code during a test mode operation, selecting the internal selection code during a boot-up operation, and transferring the selected selection code through a selection code transfer bus, a second selector for selecting the test setup data during the test mode operation, selecting the internal setup data that is outputted from the non-volatile memory during the boot-up operation, and transferring the selected selection code through a setup data transfer bus; and setup circuits for performing a setup operation based on the information transferred through the selection code transfer bus and the setup data transfer bus.. .
| Memory device and integrated circuit|
A memory device includes a nonvolatile memory, operated by using a plurality of voltages and configured to output stored repair information in response to a boot-up signal, a plurality of registers configured to store the repair information output from the nonvolatile memory, a plurality of memory banks configured to replace a normal cell with a redundancy cell using the repair information stored in registers corresponding to the plurality of memory banks among the plurality of registers, and a boot-up control circuit configured to activate the boot-up signal at a time of stabilization of the plurality of voltages.. .
| Storage device|
A storage device of an embodiment includes a voltage measurement unit that measures a voltage of power supplied from a host, a volatile memory, a non-volatile memory including a saving area and a normal area, a data compression and decompression unit, and a controller. The controller includes a power-supply voltage determining unit which compares the voltage measured by the voltage measurement unit to a predetermined threshold value, a data saving unit which writes compression user data obtained by compressing user data by the data compression and decompression unit in the saving area when the voltage is less than the predetermined threshold value and the user data is included in the volatile memory, and a data rewriting unit which writes the compression user data that is decompressed in the normal area when the compression user data is included in the saving area at the time of supplying the power..
To provide a microcontroller that can operate in a low power consumption mode. The microcontroller includes a cpu, a memory, and a peripheral circuit such as a timer circuit.
| Methods and systems for dynamically controlling operations in a non-volatile memory to limit power consumption|
Systems and methods are disclosed for limiting power consumption of a non-volatile memory (nvm) using a power limiting scheme that distributes a number of concurrent nvm operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the nvm, thereby eliminating peak power events.
| Memory device, memory system including the same, and method for operating the memory system|
A memory device includes a non-volatile memory configured to store a repair data and output the repair data in response to an initialization signal, a plurality of registers configured to store the repair data outputted from the non-volatile memory, a plurality of memory banks configured to replace normal cells with redundant cells by using the repair data stored in corresponding registers among the plurality of registers, a verification circuit configured to generate a completion signal for informing that transfer of the repair data from the non-volatile memory to the plurality of registers is completed, and an output circuit configured to output the completion signal to a device other than the memory device.. .
| Image processing apparatus, control method for image processing apparatus, and storage medium|
An image processing apparatus that schedules and executes a process in response to a request for job processing includes a detection unit configured to detect a process which requests backing up of management information to be managed in the job processing, a setting unit configured to set, in a case where a process requesting data backup is detected, a caching destination to which management information requested to be backed up is to be cached to a volatile memory or a non-volatile memory based on a data amount of the management information requested to be backed up, and a cache unit configured to cache the management information in the set caching destination.. .
| Storage virtualization in a block-level storage system|
A data storage system that stores data has a logical address space divided into ordered areas and unordered areas. Retrieval of storage system metadata for a logical address is based on whether the address is located in an ordered area or an unordered area.
| Memory controller, and electronic device having the same and method for operating the same|
A memory controller includes a first interface and a microprocessor. The first interface is configured to receive a first command, a first address, an address state separation command, and a second address, the first address corresponding to the first command, and the address state separation command separating the first and second addresses from each other.
| Memory controller, method of operating memory controller, and system comprising memory controller|
A memory controller controls operation of a nonvolatile memory device comprising a memory area comprising a plurality of multi-level cells (mlcs). The memory controller receives an address of the memory area and data to be programmed to the memory area, analyzes access history information regarding the memory area based on the address, generates first mapping data corresponding to the data or second mapping data based on the data and previous mapping data that has been programmed to the mlcs according to a result of the analysis, and transmits a program command comprising one of the first mapping data and the second mapping data to the nonvolatile memory device..
| Memory controller, electronic device having the same and method for operating the same|
A memory controller includes first and second interfaces, a microprocessor, a register and a plane control unit. The first interface is configured to receive a first command and plane logic information of a plurality of planes in a memory device from a host.
| Solid-state drive device|
A solid state drive (ssd) device using a flash memory and including a non-volatile memory that differs in type from the flash memory. The ssd device receives data to be written to the flash memory; stores the received data in the non-volatile memory; stores the data stored in the non-volatile memory to the flash memory; and stores, in the non-volatile memory, flow data indicating a flow of tasks to be undertaken while storing the received data in the non-volatile memory and storing the data stored in the non-volatile memory to the flash memory..
| Information processing apparatus, information processing method, and program|
Provided is an information processing apparatus, including: a volatile memory; a nonvolatile memory including a rewritable area configured to store rewritable data, and a non-rewritable area configured to store non-rewritable data and a snapshot boot image, the snapshot boot image showing a home window corresponding to an execution status of the non-rewritable data; and a controller configured to load the rewritable data and the snapshot boot image into the volatile memory when booting, and to draw the home window based on difference information and the snapshot boot image, the difference information corresponding to difference data of the rewritable data before and after. .
| Memory system|
According to one embodiment, a memory system according to one embodiment is equipped with several nonvolatile memory chips and a memory controller that controls the nonvolatile memory chips based on a firmware. The firmware is written in a nonvolatile memory chip positioned the farthest distance from the memory controller..
| Sram handshake|
Various exemplary embodiments relate to an integrated circuit including: a rf interface; a wired interface connectable to a host; a volatile memory having a first block and a last block configured to store data transferred between the rf interface and the wired interface; and a memory controller configured to detect when the last block of the volatile memory has been written and to indicate that the volatile memory is ready to read. Various exemplary embodiments relate to a method performed by a tag including: determining that data is to be received on the first interface; blocking the second interface; writing data from the first interface to a volatile memory; detecting that the last block of the volatile memory has been written; unblocking the second interface; indicating that data is available for reading; blocking the first interface; and reading data from the volatile memory to the second interface..
| Heterogeneous data paths for systems having tiered memories|
A nonvolatile memory (“nvm”) buffer can be incorporated into an nvm system between a volatile memory buffer and an nvm to decrease the size of the volatile memory buffer and organize data for programming to the nvm. Heterogeneous data paths may be used for write and read operations such that the nonvolatile memory buffer is used only in certain situations..
| Redundancy schemes for non-volatile memory based on physical memory layout|
A method includes, for a memory die including at least first and second memory planes, each including multiple physical memory blocks, holding a definition of a redundancy mapping between first memory blocks in the first memory plane and respective second memory blocks in the second memory plane, such that a physical separation on the die between each first physical memory block and a corresponding second physical memory block meets a predefined criterion. Data is stored in one or more first physical memory blocks in the first memory plane.
| Efficient xml tree indexing structure over xml content|
A method and apparatus are provided for building and using a persistent xml tree index for navigating an xml document. The xml tree index is stored separately from the xml document content, and thus is able to optimize performance through the use of fixed-sized index entries.
| Method of forming nonvolatile memory device|
A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.. .
| Work function tailoring for nonvolatile memory applications|
Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.
| Electronic device and playing method thereof|
A playing method is executed in an electronic device. The electronic device plays information from a storage unit.
| Method of handling non-access stratum message and related communication device|
A method of handling non-access stratum (nas) mobility management (mm) messages for a user equipment in a wireless communication system when the user equipment is configured for dual priority includes sending a first nas mm request message containing a first priority level to a network in the wireless communication system, and storing a priority indicator indicating the first priority level in a non-volatile memory if the user equipment receives a nas mm reject message with a mobility management back-off (mmbk) timer from the network.. .
| Non-volatile memory device and electronic apparatus|
A non-volatile memory device is provided, which includes a first block for storing a first data group including a test data, a second block for storing a second data group including a complementary data to the first data group, a differential sense amplifier for generating an output value based on a difference between two input signals, a diagnostic circuit for performing a failure diagnosis using a value from the differential sense amplifier, and a control circuit which performs control such that a signal based on the test data and the complementary data is set to the input signal of the differential sense amplifier and the diagnostic circuit executes a failure diagnosis of the differential sense amplifier. The non-volatile memory device performs a failure diagnosis with high reliability capable of distinguishing between a failure of sense amplifier and a failure of a memory cell..
| Nonvolatile memory device and operating method thereof|
A nonvolatile memory device includes a memory cell array including a main cell area and a retention flag cell area, a retention check unit configured to compare a read result for retention flag cells included in the retention flag cell area to a reference value, and determine a retention state of the retention flag cells according to a comparison result, and a control logic configured to provide a retention check result based on the retention state to the external device in response to a retention check request provided from an external device.. .
| Non-volatile memory devices and methods of manufacturing the same|
This technology relates to nonvolatile memory devices and methods of manufacturing the same. A nonvolatile memory device can include a memory cell array configured to include a plurality of strings, a page buffer unit connected to the plurality of strings, respectively, and configured to sense data, and a switching unit disposed between the memory cell array and the page buffer unit and configured to comprise a variable resistor..
| Non-volatile memory device, method for controlling the same, and data processing system using the control method|
A non-volatile memory device, a method for controlling the same, and a data processing system using the device and method are disclosed, which relates to a technology for controlling operations of a flash memory device. The non-volatile memory device comprises a cell array configured to comprise a plurality of cells coupled between a word line and a bit line; a drive controller configured to calculate a constant value corresponding to variation in word-line resistance values measured at individual word-line positions, combine the constant value with a word-line address, and set a rising time of the word line; and a voltage provider configured to provide a bias voltage in response to the rising time set in the drive controller..
| Programming method of nonvolatile memory device|
Provided is a programming method of a nonvolatile memory device which includes a plurality of strings each including a source select transistor, a plurality of memory cells, and a drain select transistor which are connected in series between a common source line and a bit line. The programming method includes: applying a first voltage to the common source line during a first period in which a channel of a plurality of memory cells of an unselected string is floated; and applying a second voltage increased more than the first in voltage to the common source line during a second period in which a selected memory cell is programmed, when a selected word line belongs to a word line group adjacent to the common source line..
| Nonvolatile memory device and operating method thereof|
A nonvolatile memory device includes: a page buffer block including a plurality of cache latches configured to temporarily store data inputted to program memory cells, and configured to program the inputted data into the memory cells; and a column decoder configured to provide column select signals for selecting the cache latches to the cache latches according to a column address, wherein the column decoder activates column select signals for selecting a part of the cache latches at substantially the same time, while data are set up in the cache latches.. .
| Storage device and control method of nonvolatile memory|
According to one embodiment, a storage device includes a nonvolatile memory, a controller configured to copy data stored in a first page in a first block to a second page in a second block, and an ecc circuit. The controller reads data from a part of the first page by using an upper limit voltage and lower limit voltage, performs a direct copy operation in the nonvolatile memory without via the ecc circuit if the number of error cells having threshold voltages higher than the lower limit voltage and lower than or equal to the upper limit voltage is less than or equal to a specified value, and performs error correction by using the ecc circuit if the number of error cells exceeds the specified value..
| Nonvolatile memory device and data storage device including the same|
A nonvolatile memory device includes: a plurality of memory cells arranged in a region where word lines and bit lines intersect, a data read/write circuit including a plurality of latches configured to temporarily store data inputted from an external device, and configured to perform a program operation on the memory cells based on data stored in the latches, and a skip data control unit configured to determine whether data to be programmed into the memory cells are available, and to store program-inhibit data in a latch corresponding to a memory cell which is determined to not contain any data.. .
| Non-volatile memory (nvm) that uses soft programming|
A semiconductor memory device comprises a memory controller, and an array of memory cells coupled to communicate with the memory controller. The memory controller is configured to perform a first soft program operation using first soft program voltages and a first soft program verify level, and determine whether a first charge trapping threshold has been reached.
| Read method for nonvolatile memory device, and data storage system using the same|
Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell.
| Direct multi-level cell programming|
A method is performed in a data storage device that includes a controller coupled to a non-volatile memory. The non-volatile memory includes a group of storage elements.
| Nonvolatile memory device and sub-block managing method thereof|
A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate, the memory block being divided into sub-blocks configured to be erased independently.
| Non-volatile memory device and method for manufacturing the same|
A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a variable resistance element and a first current steering element; and a current steering element parameter generation circuit. The current steering element parameter generation circuit includes: a third line placed between a substrate and a second interlayer dielectric; a fourth line placed above the second interlayer dielectric; and a second current steering element which is connected between the third line and the fourth line without the variable resistance element being interposed therebetween when the variable resistance element is removed between the third line and the fourth line and has the same non-linear current steering characteristics as the first current steering element..
| Non-volatile memory device|
According to an embodiment, a non-volatile memory device includes a first conductive layer, a second conductive layer, and a resistance change layer provided between the first conductive layer and the second conductive layer. The resistance change layer is capable of making a transition between a low-resistance state and a high-resistance state, and includes an oxide containing at least one of hafnium (hf) and zirconium (zr), at least one selected from the group consisting of barium (ba), lanthanum (la), gadolinium (gd) and lutetium (lu), and nitrogen (n)..
| Nonvolatile memory element, nonvolatile memory device, and writing method for use in nonvolatile memory element|
In a nonvolatile memory element, when a voltage value of an electric pulse has a relationship of v2>v1>0 v>v3>v4 and a resistance value of a variable resistance layer has a relationship of r3>r2>r4>r1, the resistance value of the variable resistance layer becomes: r2, when the electric pulse having a voltage value of v2 or greater is applied between electrodes; r4, when the electric pulse having a voltage value of v4 or smaller is applied between the electrodes; r3, when the resistance value of the variable resistance layer is r2 and the electric pulse having a voltage value of v3 is applied between the electrodes; and r1, when the resistance value of the variable resistance layer is r4 and the electric pulse having a voltage value of v1 is applied between the electrodes.. .
| Non-volatile memory including reference signal path|
Some embodiments include apparatuses and methods having a first memory element and a first select component coupled to the first memory element, a second memory element and a second select component coupled to the second memory element, and an access line shared by the first and second select components. At least one of the embodiments can include a circuit to generate a signal indicating a state of the second memory element based on a first signal developed from a first signal path through the first memory element and a second signal developed from a second signal path through the second memory element..
| Nonvolatile memory apparatus and method for driving the same|
A method for driving a nonvolatile memory apparatus includes: a data storage preparation step of setting a write control voltage to a first level of voltage; a data storage step of driving a driving transistor through the write control voltage to generate a write current, and storing an external data in a memory cell through the write current; a data detection step of varying the write control voltage by a predetermined level from a preset voltage level, and reading the data stored in the memory cell; and a data verification step of determining whether the stored data coincides with the external data or not, and repeating the data storage step and the data detection step according to a result of the determining.. .
| Sheet conveying device capable of discharging sheet from conveying path at startup|
A sheet conveying device includes: a conveying unit; a nonvolatile memory; and a controller. The conveying unit is configured to convey a sheet along a conveying path.
| Image display apparatus and method for displaying image on display device|
An image display apparatus is coupled to a nonvolatile memory section, and includes an image processing part configured to display an image on a display device, an initial setting circuit, and a control register configured to control respective parts in the image display apparatus. At power-on or start-up of the image display apparatus, the initial setting circuit reads initialization data from the nonvolatile memory section and sets communication mode for communicating with the nonvolatile memory section to the control register.