|| List of recent Volatile Memory-related patents
| Method for updating firmware of a battery included in a rechargeable battery module, portable electronic device, and rechargeable battery module|
In a method for updating firmware of a battery included in a rechargeable battery module of a portable electronic device, the portable electronic device stores a booting instruction set of the firmware in a battery monitoring unit of the rechargeable battery module, and stores a basic input/output system (bios) of the portable electronic device in a non-volatile memory disposed externally of the rechargeable battery module. In response to bios update information that includes an updated main instruction set of the firmware, the portable electronic device updates the bios, including the main instruction set of the firmware using the bios update information..
| Locating data in non-volatile memory|
Systems and methods presented herein provide for locating data in non-volatile memory by decoupling a mapping unit size from restrictions such as the maximum size of a reducible unit to provide efficient mapping of larger mapping units. In one embodiment, a method comprises mapping a logical page address in a logical block address space to a read unit address and a number of read units in the non-volatile memory.
| Method and device to distribute code and data stores between volatile memory and non-volatile memory|
A method, device, and system to distribute code and data stores between volatile and non-volatile memory are described. In one embodiment, the method includes storing one or more static code segments of a software application in a phase change memory with switch (pcms) device, storing one or more static data segments of the software application in the pcms device, and storing one or more volatile data segments of the software application in a volatile memory device.
| Electronic control unit for vehicle and data communication method|
An electronic control unit for a vehicle includes a nonvolatile memory that is capable of erasing and writing data electrically, and capable of receiving a program to be written into the nonvolatile memory in units of a predetermined size by means of communication using a communication buffer. The electronic control unit for the vehicle uses communication buffers, the number of which is greater than the number of communication buffers used in an in-vehicle communication environment, to receive the program..
| Management of and region selection for writes to non-volatile memory|
Management of and region selection for writes to non-volatile memory of an ssd improves performance, reliability, unit cost, and/or development cost of an ssd. A controller receives and determines characteristics of writes (e.g.
| Translation layer partitioned between host and controller|
A method for using a partitioned flash transition layer is disclosed. Step (a) receives, at an apparatus from a host, a write command having first write data.
| Variable-size flash translation layer|
A method for using a variable-size flash transition layer is disclosed. Step (a) receives a read request to read data corresponding to a logical block address from a nonvolatile memory.
| Multilevel cell nonvolatile memory system|
A multilevel cell (mlc) nonvolatile memory system including a plurality of memory cells each cell storing first bit data and second bit data, and a controller programming the plurality of memory cells on a page-by-page basis, the controller programming original data to an original block and programming copy data that is the same as the original data to a mirroring block, wherein first bit page data and second bit page data of the original data are programmed to memory cells connected to the same word line, but the first bit page data and second bit page data of the copy data are programmed to memory cells connected to different word lines.. .
| System and method of wear leveling for a non-volatile memory|
In an architecture of wear leveling for a non-volatile memory composed of plural storage units, a translation layer is configured to translate a logical address provided by a host to a physical address of the non-volatile memory. A cold-block table is configured to assign a cold block or blocks in at least one storage unit, the cold block in a given storage unit having an erase count being less than erase counts of non-cold blocks in the given storage unit.
| Systems and methods for adaptive soft programming for non-volatile memory using temperature sensor|
Erasing of a non-volatile memory (nvm) having an array of bit cells includes soft programming after an initial erasing of the bit cells. Over-erased bit cells are determined.
| Nonvolatile memory devices, memory systems and related control methods|
A nonvolatile memory device includes a cell array including a plurality of cell strings extending on a substrate in a vertical direction, a page buffer connected to a plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured to provide voltages to a plurality of word lines and the plurality of bit lines, and an input/output buffer configured to temporarily store the sensing data received in a data dump from the page buffer and to output the temporarily stored data to an external device. The nonvolatile memory device further includes control logic configured to set a status of the nonvolatile memory device to a ready state after the sensing data is dumped to the input/output buffer and before recovery of the cell array from a bias voltage of the sensing operation is complete..
| Nonvolatile memory device, memory system having the same, external power controlling method thereof|
An external power control method includes determining whether to apply a second external voltage to a first node according to a drop of a first external voltage; generating a flag signal according to a drop of the second external voltage when the second external voltage is applied to the first node; transferring a voltage of the first node to a second node in response to the flag signal; and discharging at least one voltage of an internal circuit connected to the second node in response to the flag signal.. .
| Dynamic detection method for latent slow-to-erase bit for high performance and high reliability flash memory|
A method and apparatus for detecting a latent slow bit (e.g., a latent slow-to-erase bit) in a non-volatile memory (nvm) is disclosed. A maximum number of soft program pulses among addresses during an erase cycle is counted.
| High voltage switch and a nonvolatile memory device including the same|
A high voltage switch of a nonvolatile memory device includes a depletion type nmos transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage switch into a first driving voltage or a ground voltage, wherein the first and second driving voltages are received from an external device; and a pmos transistor configured to transfer the second driving voltage provided to a first terminal of the pmos transistor from the depletion type nmos transistor to a second terminal of the pmos transistor as the output signal in response to an output of the at least one inverter, wherein the output of the at least one inverter is transferred to a gate terminal of the pmos transistor.. .
| Multi-page program method, non-volatile memory device using the same, and data storage system including the same|
A method of programming a non-volatile memory device including a plurality of strings arranged in rows and columns comprises activating all or a part of selection lines in one column at the same time depending upon data to be programmed, driving a bit line corresponding to the one column with a bit line program voltage, and repeating the activating and the driving until bit lines corresponding to the columns are all driven.. .
| Line voltage boost system and method for non-volatile memory devices and memory devices and processor-based system using same|
The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array..
| Systems and methods of updating read voltages|
A method includes, in a data storage device that includes a non-volatile memory, reading data from the non-volatile memory using a first read voltage. The method includes determining a first count of errors in the data having a first error type and a second count of errors in the data having a second error type.
| Nonvolatile resistive memory device and writing method|
A writing method for a resistive nonvolatile memory device includes writing data to a resistive nonvolatile memory cell using an up/down write pulse signal when the data is first data type, and writing data to the resistive nonvolatile memory cell using only one of an up write pulse signal and a down write pulse signal when the data is second data type.. .
| System of providing multiple voltage references to a radio-frequency device using a single analog line|
A system includes a control board, a controlled board, and a connector connecting the control board to the controlled board. The control board includes a processing unit that configures the reference voltage signals, a non-volatile memory that stores information about the reference voltage signals, and a dac that outputs the reference voltage signals in accordance with instructions from the processing unit.
| Method of making a non-volatile memory (nvm) cell structure|
A non-volatile memory device includes a substrate and a charge storage layer. The charge storage layer comprises a bottom layer of oxide, a layer of discrete charge storage elements on the bottom layer of oxide, and a top layer of oxide on the charge storage elements.
| Non-volatile memory cell having a floating gate and a coupling gate with improved coupling ratio therebetween|
A non-volatile memory cell having a split gate, wherein the floating gate and the coupling/control gate have complimentary non-planar shapes. The shape may be a step shape.
| Variable resistance nonvolatile memory element and method of manufacturing the same|
A variable resistance nonvolatile memory element includes: first and second electrode layers; a first variable resistance layer between the first and second electrode layers; and a second variable resistance layer between the second electrode layer and the first variable resistance layer and having a higher resistance value than the first variable resistance layer. When viewed in a direction perpendicular to the major surface of the second variable resistance layer, an outline of the second variable resistance layer is located inwardly of the outline of any one of the second electrode layer and the first variable resistance layer, and an outline of a face of the second variable resistance layer, the face being in contact with the first variable resistance layer is located inwardly of an outline of a face of the first variable resistance layer, the face being in contact with the second variable resistance layer..
|Apparatus and method for encoding data for storage in multi-level nonvolatile memory|
A controller for a nonvolatile memory includes an encoder and a decoder. The memory includes memory cells that each store data using more than two levels.
|Systems and methods to update reference voltages in response to data retention in non-volatile memory|
A data storage device includes non-volatile memory and a controller. The controller is configured to, at a first time, determine a first count of storage elements having threshold voltages within a voltage range that corresponds to a first reference voltage.
|Managing volatile file copies|
Persistent files are copied from persistent memory to volatile memory to yield volatile files. At least some requests to open for writing or to close to writing persistent files are redirected to the corresponding volatile files.
|Distributed procedure execution and file systems on a memory interface|
Nonvolatile memory (e.g., flash memory, solid-state disk) is included on memory modules that are on a dram memory channel. Nonvolatile memory residing on a dram memory channel may be integrated into the existing file system structures of operating systems.
|Storage control apparatus, data storage apparatus and method for storage control|
According to one embodiment, a storage control apparatus includes a first buffer controller and a second buffer controller. The first buffer controller is configured to store data of a first unit in each of data buffer regions, and the data of the first unit is transmitted from a host and written in a nonvolatile memory, or read from the nonvolatile memory and transmitted to the host.
|Orchestrating management operations among a plurality of intelligent storage elements|
An apparatus and associated methodology contemplating a data storage system having a group of processor-controlled intelligent storage elements (ises). Each ise in the group individually includes storage resources and a network interface.
|Systems and methods of configuring a mode of operation in a solid-state memory|
Disclosed herein is an architecture that pairs a controller with a nvm (non-volatile memory) storage system. The nvm storage system includes a bridge device that communicates with the controller.
|Apparatus and method for booting|
A method and device for a booting that can reduce a booting time is provided. The method includes loading a snapshot image from a non-volatile memory, setting an initialization of a device, decompressing the loaded snapshot image while the device is initialized, and loading another snapshot image from the non-volatile memory while decompressing the loaded snapshot image..
|Fault masking method for non-volatile memories|
A fault masking method is applied to a non-volatile memory array which includes a faulty cell and electrically connected to an address register providing a first address. The faulty cell can only output a fixed value.
|Method and system for reducing the size of nonvolatile memories|
Embodiments relate to system and methods including a plurality of nonvolatile memory elements wherein sets of least two nonvolatile memory elements each share one select element for selecting one of the nonvolatile memory elements of a particular one of the sets of nonvolatile memory elements for a read operation or a program operation.. .
|Method of storing data in nonvolatile memory device and method of testing nonvolatile memory device|
A method of storing data in a nonvolatile memory device comprises performing a program operation on target memory cells among multiple memory cells, performing a first verify operation to determine whether the target memory cells are in a program pass state or a program fail state, and as a consequence of determining that the target memory cells are in the program pass state, performing a second verify operation to determine whether the target memory cells exhibit a program error symptom.. .
A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a mos type first transistor section (3) used for information storage, and a mos type second transistor section (4) which selects the first transistor section.
|Nonvolatile memory and manipulating method thereof|
A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided.
|Memory system and method of operation thereof|
A method of operating a memory system including a non-volatile memory device and a memory controller controlling the non-volatile memory device, includes reading data from a memory cell array in a unit of a page which includes a plurality of sectors; performing error correction decoding on the read data in a unit of a sector of the page; selecting at least one target sector which includes at least one uncorrectable error and selecting at least one pass sector wherein all errors of the pass sector are correctable by the error correction decoding; inhibiting precharging of bit-lines connected to the at least one pass sector while precharging target bit lines connected to the at least one target sector; and performing a read retry operation for data in the at least one target sector.. .
|Non-volatile memory systems and methods|
A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage.
|Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution|
A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data states at which the memory cells may be read.. .
|Read circuit and non-volatile memory using the read circuit|
A read circuit includes a current load circuit configured to supply a load current from a power source to a first input and a second input; a first discharge circuit configured to discharge potential of the first and second inputs to a ground level; an equalization circuit configured to equalize the potential of the first and second inputs; a differential circuit configured to receive the first and second inputs as differential inputs, and to output a first output and a second read output as differential outputs; and a second discharge circuit configured to discharge potential of the first and second read outputs to the ground level.. .
|Nonvolatile memory device using variable resistive element and memory system having the same|
A nonvolatile memory device, which has an improved read reliability through a refresh operation, and a memory system, are provided. The nonvolatile memory device includes a resistive memory cell, a reference resistor corresponding to the resistive memory cell, a reference sense amplifier electrically connected to the reference resistor and configured to change a transition time of an output value of the reference resistor, and a refresh request signal generator configured to output the refresh request signal for the resistive memory cell when the transition time of an output value of the reference resistor is in a preset refresh requiring period..
|A method and device to augment volatile memory in a graphics subsystem with non-volatile memory|
Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (nvram).