|| List of recent Volatile Memory-related patents
|Microcontroller and method for manufacturing the same|
A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a cpu, a memory, and a peripheral circuit such as a timer circuit.
|Power management integrated circuit and operating method thereof|
A power management integrated circuit includes a nonvolatile memory configured to store code data for driving the power management integrated circuit; a processor configured to execute program data stored at a volatile memory; and a decompression logic separated from the processor, the decompression logic being formed of hardware, configured to decompress the code data to generate program data, and configured to store the program data at the volatile memory.. .
|Controllers controlling nonvolatile memory devices and operating methods for controllers|
An operating method of a controller includes selecting bits of code word to be punctured; detecting locations of incapable bits of an input word based on locations of the bits to be punctured and a structure of a generation matrix calculation unit; refreezing the input word such that frozen bits and incapable bits of the input word overlap; generating input word bits by replacing information word bits with frozen bits based on the refreezing result; generating the code word by performing generation matrix calculation on the input word bits; generating output bits by puncturing the code word based on locations of the bits to be punctured; and transmitting the output bits to a nonvolatile memory device.. .
|Portable secure device providing storage service|
A secure device includes a non volatile memory and a secure storage unit for a contactless reader. The storage unit manages logical sectors comprising a preset number of 16-byte data blocks and provides secured access to these data blocks.
|File server node with non-volatile memory processing module coupled to cluster file server node|
Apparatus includes a file server node having (i) a first interface operable to communicate with a network and receiving a network request via network, (ii) a non-volatile memory operable to temporarily store a request related to the network request received by the first interface, (iii) a second interface operable to be coupled to the storage device for storing the request, and (iv) a non-volatile memory processing module, coupled to the first interface, the non-volatile memory and the second interface, and operable to be coupled to another file server node, so that the request can be sent to the non-volatile memory, the second interface and the another file server node after the non-volatile memory processing module receives the file system request.. .
|Data storage architecture and system for high performance computing|
Data storage systems and methods for storing data are described herein. The storage system may be integrated with or coupled with a compute cluster or super computer having multiple computing nodes.
|Use of high endurance non-volatile memory for read acceleration|
A high endurance, short retention nand memory is used as a read cache for a memory of a higher level of non-volatility, such as standard nand flash memory or a hard drive. The combined memory system identifies frequently read logical addresses of the main non-volatile memory or specific read sequences and stores the corresponding data in cache nand to accelerate host reads.
|Apparatus for and method of monitoring condensed water in steam pipes at high temperature|
A system and method for monitoring the properties of a fluid, such as water, in a steam pipe without mechanically penetrating the wall of the pipe. The system uses a piezoelectric transducer to launch an ultrasonic probe signal into the pipe.
|Marine vessel steering system|
A marine vessel steering system includes a basic target turning angle computing unit that computes a basic target turning angle δo* common to two outboard motors based on a steering angle θ detected by a steering angle sensor. A traveling state determining unit determines whether a traveling state of a marine vessel is a straight traveling state based on the received basic target turning angle δo*.
|Nonvolatile memory devices|
A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors.
|Data loading circuit and semiconductor memory device comprising same|
A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.. .
|Non-volatile memory array and method of using same for fractional word programming|
A non-volatile memory device that includes n planes of non-volatile memory cells (where n is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns.
|Non-volatile memory device with plural reference cells, and method of setting the reference cells|
A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells..
|Programming nonvolatile memory device using program voltage with variable offset|
A method of programming a nonvolatile memory device comprises applying at least one test program pulse to selected memory cells located in a scan read area, performing a scan read operation on the selected memory cells following application of the at least one test program pulse to detect at least one one-shot upper cell, calculating an offset voltage corresponding to a scan read region at which the scan read operation is performed, setting a program start bias using the offset voltage, and executing at least one program loop using the program start bias.. .
|Split block decoder for a nonvolatile memory device|
A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address.
|Nonvolatile memory devices and methods forming the same|
Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line.
|Programming based on controller performance requirements|
Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, comprising an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit..
|Memory cells, non-volatile memory arrays, methods of operating memory cells, methods of writing to and writing from a memory cell, and methods of programming a memory cell|
In one aspect, a method of operating a memory cell includes using different electrodes to change a programmed state of the memory cell than are used to read the programmed state of the memory cell. In one aspect, a memory cell includes first and second opposing electrodes having material received there-between.
|Nonvolatile memory device and method of performing forming the same|
A nonvolatile memory device including a control unit configured to read resistance value information for each of memory cells as initial resistance value information and store it temporarily before a voltage pulse for forming is applied, to set resistance value information as a threshold value serving as a target for completion of the forming, the resistance value information being obtained by multiplying the initial resistance value information by a predetermined coefficient, and to repeat application of the voltage pulse for forming and reading of the resistance value information until a resistance value indicated by the resistance value information on the memory cell becomes lower than a resistance value indicated by the threshold value.. .
|Cross-point variable resistance nonvolatile memory device and reading method for cross-point variable resistance nonvolatile memory device|
A cross-point variable resistance nonvolatile memory device comprises: a memory cell array; a column decoder and pre-charge circuit which pre-charges a selected word line to a first voltage in a period p1 among the period p1, a period p2, and a period s that are included in this order in a read operation of a memory cell; a low decoder driver which pre-charges a selected word line to the first voltage in the periods p1 and p2 and sets the selected word line to a third voltage different from the first voltage in the period s; a feedback controlled bit line voltage clamp circuit which sets the selected bit line to a second voltage in the periods p2 and s; and a sense amplifier which determines the resistance state in a memory cell at a cross-point of the selected word line and the selected bit line in the period s.. .
|Low cost high density nonvolatile memory array device employing thin film transistors and back to back schottky diodes|
An improved crosspoint memory array device comprising a plurality of memory cells, each memory cell being disposed at an intersection region of bit and word conductive lines, electrically coupled to one of the first conductive lines at a first terminal and to one of the second conductive lines at a second terminal, and comprising a controllable electrical resistance, wherein a back to back schottky diode is located between each memory cell and one of the said conductive lines, and wherein each conductive line is electrically coupled to at least two thin film transistors (tfts). The device is substantially produced in beol facilities without need of front end semiconductor production facilities, yet can be made with ultra high density and low cost..
|Non-volatile memory device and method for forming the same|
A method for forming a non-volatile memory device includes: (a) forming an isolation structure on a circuit-forming surface of a semiconductor substrate to define an array of cell forming regions; (b) forming a gate structure array including a plurality of gate structures disposed above the cell forming regions and each having a first side and a second side; (c) performing ion implantation to form drain regions and a common source region; and (d) forming drain contacts to the drain regions, and a common source contact to the common source region.. .
|Non-volatile memory device having adjustable read voltage, memory system comprising same, and method of operating same|
A nonvolatile memory device comprises a memory cell array comprising a selected page comprising multiple error correction code (ecc) units, and a voltage generation unit configured to generate a read voltage to read data from the selected page. Read voltage levels are set individually for the respective ecc units according to data detection results for each of the ecc units.
|Common hot spare for multiple raid groups|
A storage system assigns one or more large disks in a storage enclosure as a common dedicated hot spare that is used by multiple raid groups. Storage space equivalent to the smallest physical disk in a raid group is allocated on the common dedicated hot spare.
|Processing device and management board|
A processing device includes: casing; a processor in the casing; and a management board detachably mounted on the casing and manages the processor. The casing includes a memory storing therein first identification data to identify the casing.
|Tracking a lifetime of write operations to a non-volatile memory storage|
A method, device, and system are disclosed. In one embodiment method begins by incrementing a count of a total number of write operations to a non-volatile memory storage for each write operation to the non-volatile memory storage.
|Memory system and read reclaim method thereof|
A memory system includes a nonvolatile memory device including a first memory area formed of memory blocks which store n-bit data per cell and a second memory area formed of memory blocks which store m-bit data per cell, where n and m are different integers, and a memory controller configured to control the nonvolatile memory device. The memory controller is configured to execute a read operation, and to execute a read reclaim operation in which valid data of a target memory block of the second memory area is transferred to one or more memory blocks of the first memory area, the target memory block selected during the read operation.
|Systems and methods for nonvolatile memory performance throttling|
Systems and methods for nonvolatile memory (“nvm”) performance throttling are disclosed. Performance of an nvm system may be throttled to achieve particular data retention requirements.
|Apparatus and method for low power low latency high capacity storage class memory|
A method and a storage system are provided for implementing enhanced solid-state storage class memory (escm) including a direct attached dual in line memory (dimm) card containing dynamic random access memory (dram), and at least one non-volatile memory, for example, phase change memory (pcm), resistive ram (reram), spin-transfer-torque ram (stt-ram), and nand flash chips. An escm processor controls selectively allocating data among the dram, and the at least one non-volatile memory primarily based upon a data set size..
|Methods, devices and systems for physical-to-logical mapping in solid state drives|
A data storage device comprises a plurality of non-volatile memory devices storing physical pages, each stored at a predetermined physical location. A controller may be coupled to the memory devices and configured to access data stored in a plurality of logical pages (l-pages), each associated with an l-page number that enables the controller to logically reference data stored in the physical pages.
|Binding microprocessor to memory chips to prevent re-use of microprocessor|
A processor is provided that binds itself to a circuit such that the processor cannot be subsequently reused in other circuits. On a first startup of the processor, a memory segment of an external volatile memory device is read to obtain information prior to initialization of the memory segment.
|System and methodology for utilizing a portable media player|
A low-cost portable digital video player receives proprietary compressed data from a source such as a personal video recorder (pvr), and displays the data on an integral display. A rewritable non-volatile memory of the player stores the data and a media decoder of the player transforms and decompresses the data.
|Non-volatile memory with overwrite capability and low write amplification|
Providing for a non-volatile memory architecture having write and overwrite capabilities providing low write amplification to a storage system is described herein. By way of example, a memory array is disclosed comprising blocks and sub-blocks of two-terminal memory cells.
|Latent slow bit detection for non-volatile memory|
In accordance with at least one embodiment, a non-volatile memory (nvm) and method is disclosed for detecting latent slow erase bits. At least a portion of an array of nvm cells is erased with a reduced erase bias.
|Main memory system storing operating system program and computer system including the same|
A main memory system is provided which includes a nonvolatile memory including a first memory area designated to store an operating system program and a second memory area designated to store user data; and a memory controller configured to control the nonvolatile memory such that the operating system program is loaded onto the second memory area from the first memory area. The nonvolatile memory may be one of a phase change ram, a resistive ram, and a magnetic ram..
|Single-ended volatile memory access|
A memory includes an array of memory cells that form rows and columns. The rows include memory cell pairs.
|Non-volatile memory device|
A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a first variable resistance element and a first current steering element and a parameter generation circuit including a reference cell including a second variable resistance element and a second current steering element having the same current density-voltage characteristic as that of the first current steering element, wherein a conductive shorting layer for causing short-circuiting between the electrodes is formed on the side surfaces of the second variable resistance element.. .
|Cross point variable resistance nonvolatile memory device|
Each memory cell is formed at a different one of cross points of bit lines extending in an x direction and formed in a plurality of layers and word lines extending in a y direction. In a multilayer cross point structure in which a plurality of vertical array planes sharing the word lines are aligned in the y direction each for a group of bit lines aligned in a z direction, even and odd layer bit line selection switch elements switch connection and disconnection between a global bit line and the commonly-connected even layer bit line and the commonly-connected odd layer bit line, respectively.
|Volatile memory access via shared bitlines|
A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs.