|| List of recent Volatile Memory-related patents
| Apparatus and method for encoding data for storage in multi-level nonvolatile memory|
A controller for a nonvolatile memory includes an encoder and a decoder. The memory includes memory cells that each store data using more than two levels.
| Systems and methods to update reference voltages in response to data retention in non-volatile memory|
A data storage device includes non-volatile memory and a controller. The controller is configured to, at a first time, determine a first count of storage elements having threshold voltages within a voltage range that corresponds to a first reference voltage.
| Managing volatile file copies|
Persistent files are copied from persistent memory to volatile memory to yield volatile files. At least some requests to open for writing or to close to writing persistent files are redirected to the corresponding volatile files.
| Distributed procedure execution and file systems on a memory interface|
Nonvolatile memory (e.g., flash memory, solid-state disk) is included on memory modules that are on a dram memory channel. Nonvolatile memory residing on a dram memory channel may be integrated into the existing file system structures of operating systems.
| Storage control apparatus, data storage apparatus and method for storage control|
According to one embodiment, a storage control apparatus includes a first buffer controller and a second buffer controller. The first buffer controller is configured to store data of a first unit in each of data buffer regions, and the data of the first unit is transmitted from a host and written in a nonvolatile memory, or read from the nonvolatile memory and transmitted to the host.
| Orchestrating management operations among a plurality of intelligent storage elements|
An apparatus and associated methodology contemplating a data storage system having a group of processor-controlled intelligent storage elements (ises). Each ise in the group individually includes storage resources and a network interface.
| Systems and methods of configuring a mode of operation in a solid-state memory|
Disclosed herein is an architecture that pairs a controller with a nvm (non-volatile memory) storage system. The nvm storage system includes a bridge device that communicates with the controller.
| Apparatus and method for booting|
A method and device for a booting that can reduce a booting time is provided. The method includes loading a snapshot image from a non-volatile memory, setting an initialization of a device, decompressing the loaded snapshot image while the device is initialized, and loading another snapshot image from the non-volatile memory while decompressing the loaded snapshot image..
| Fault masking method for non-volatile memories|
A fault masking method is applied to a non-volatile memory array which includes a faulty cell and electrically connected to an address register providing a first address. The faulty cell can only output a fixed value.
| Method and system for reducing the size of nonvolatile memories|
Embodiments relate to system and methods including a plurality of nonvolatile memory elements wherein sets of least two nonvolatile memory elements each share one select element for selecting one of the nonvolatile memory elements of a particular one of the sets of nonvolatile memory elements for a read operation or a program operation.. .
| Method of storing data in nonvolatile memory device and method of testing nonvolatile memory device|
A method of storing data in a nonvolatile memory device comprises performing a program operation on target memory cells among multiple memory cells, performing a first verify operation to determine whether the target memory cells are in a program pass state or a program fail state, and as a consequence of determining that the target memory cells are in the program pass state, performing a second verify operation to determine whether the target memory cells exhibit a program error symptom.. .
| Semiconductor device|
A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a mos type first transistor section (3) used for information storage, and a mos type second transistor section (4) which selects the first transistor section.
| Nonvolatile memory and manipulating method thereof|
A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided.
| Memory system and method of operation thereof|
A method of operating a memory system including a non-volatile memory device and a memory controller controlling the non-volatile memory device, includes reading data from a memory cell array in a unit of a page which includes a plurality of sectors; performing error correction decoding on the read data in a unit of a sector of the page; selecting at least one target sector which includes at least one uncorrectable error and selecting at least one pass sector wherein all errors of the pass sector are correctable by the error correction decoding; inhibiting precharging of bit-lines connected to the at least one pass sector while precharging target bit lines connected to the at least one target sector; and performing a read retry operation for data in the at least one target sector.. .
| Non-volatile memory systems and methods|
A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage.
| Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution|
A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data states at which the memory cells may be read.. .
| Read circuit and non-volatile memory using the read circuit|
A read circuit includes a current load circuit configured to supply a load current from a power source to a first input and a second input; a first discharge circuit configured to discharge potential of the first and second inputs to a ground level; an equalization circuit configured to equalize the potential of the first and second inputs; a differential circuit configured to receive the first and second inputs as differential inputs, and to output a first output and a second read output as differential outputs; and a second discharge circuit configured to discharge potential of the first and second read outputs to the ground level.. .
| Nonvolatile memory device using variable resistive element and memory system having the same|
A nonvolatile memory device, which has an improved read reliability through a refresh operation, and a memory system, are provided. The nonvolatile memory device includes a resistive memory cell, a reference resistor corresponding to the resistive memory cell, a reference sense amplifier electrically connected to the reference resistor and configured to change a transition time of an output value of the reference resistor, and a refresh request signal generator configured to output the refresh request signal for the resistive memory cell when the transition time of an output value of the reference resistor is in a preset refresh requiring period..
| A method and device to augment volatile memory in a graphics subsystem with non-volatile memory|
Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (nvram).
| Pad structures and wiring structures in a vertical type semiconductor device|
Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position.
| Vertical type semiconductor devices|
A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines.
| Non-volatile memory structure and manufacturing method thereof|
A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ono) structure under the first gate, forming an oxide structure covering the ono structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.. .
| Non-volatile memory devices having reduced susceptibility to leakage of stored charges and methods of forming same|
Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode.
| Nonvolatile memory devices with aligned trench isolation regions|
A nonvolatile memory device includes a substrate, an elongate isolation region including a field insulation film disposed in a trench in the substrate, and a word line crossing the insulation region and including a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer. A first plane index of a bottom surface of the trench has a first interface trap density and a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density.
| Nonvolatile memory element, nonvolatile memory device, nonvolatile memory element manufacturing method, and nonvolatile memory device manufacturing method|
A nonvolatile memory element including: a first electrode; a second electrode; a variable resistance layer that is between the first electrode and the second electrode and includes, as stacked layers, a first variable resistance layer connected to the first electrode and a second variable resistance layer connected to the second electrode; and a side wall protecting layer that has oxygen barrier properties and covers a side surface of the variable resistance layer. The first variable resistance layer includes a first metal oxide and a third metal oxide formed around the first metal oxide and having an oxygen deficiency lower than that of the first metal oxide, and the second variable resistance layer includes a second metal oxide having an oxygen deficiency lower than that of the first metal oxide..
|Enhanced dynamic memory management with intelligent current/power consumption minimization|
A low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices is obtained. Data is copied from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower current/power consumption than the first set of volatile memory devices.
|Cryptographically secure authentication device, system and method|
An electronic device generates identifying values which are used in authenticating the electronic device. The device comprises an interface, a private key generator for generating a private key, a non-volatile memory for storing at least the private key, an index source, a hash engine, and a logical interconnection between the private key generator, the non-volatile memory, the index source, the hash engine and the interface.
|Hardware and file system agnostic mechanism for achieving capsule support|
Methods and apparatus relating to a hardware and file system agnostic mechanism for achieving capsule support are described. In one embodiment, content associate with a capsule are stored in a non-volatile memory prior to a cold reset.
|Method and system for data storage|
A system and method of storing data in a semiconductor-type non-volatile memory is described, where a physical storage address of data is made available to a user application such as a file system and where characteristics of the memory system that may be allocated on a physical or a logical basis to a user are separately characterizable as to performance, size, redundancy, or the like. A read request to the memory system may be serviced by accessing the physical address included in the read request rather than using a logical-to-physical address lookup in the memory system.
|Non-volatile configuration for serial non-volatile memory|
Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device..
|Maintaining i/o priority and i/o sorting|
Multiple variants of a data processing system, which maintains i/o priority from the time a process makes an i/o request until the hardware services that request, will be described. In one embodiment, a data processing system has one or more processors having one or more processor cores, which execute an operating system and one or more applications of the data processing system.
|Persistent data structures|
Apparatuses, systems, methods, and computer program products are disclosed for a persistent data structure. A method includes associating a logical identifier with a data structure.
|Persistent memory management|
Apparatuses, systems, methods, and computer program products are disclosed for persistent memory management. Persistent memory management may include providing a persistent data structure stored at least partially in volatile memory configured to ensure persistence of the data structure in a non-volatile memory medium.
|Test partitioning for a non-volatile memory|
Systems and methods are provided for testing a non-volatile memory, such as a flash memory. The non-volatile memory may be virtually partitioned into a test region and a general purpose region.
|Nonvolatile memory with split substrate select gates and heirarchical bitline configuration|
Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells.
|Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture|
A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate.
|Nonvolatile memory device and read method thereof|
A nonvolatile memory device is provided which includes a main area including main cells connected to word lines and main bit lines; a reference area including reference cells connected to the word lines and reference bit lines and programmed using the same write condition as that of the main area; a reference sense amplifier circuit configured to read data written at the reference area through the reference bit lines at a read operation; and control logic configured to control the reference sense amplifier circuit such that data written at the reference area is shifted with a weight scheme and then read, the data written at the reference area being used as a read reference value of the main area at a read operation.. .
|Near field communication enabled permanent rfid luggage tag|
An integral, one-piece, resiliently flexible, planar, reusable, programmable radio frequency identification (rfid) luggage tag has a planar flexible sheet core of microporous polymer material permanently and completely surrounding a first rfid transponder assembly. The first transponder assembly includes a programmable memory portion with space to store information externally programmed into the portion.
|Method of manufacturing a non-volatile memory|
The disclosure relates to a method of manufacturing vertical gate transistors in a semiconductor substrate, comprising implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors; forming, in the substrate, parallel trench isolations and second trenches perpendicular to the trench isolations, reaching the isolation layer, and isolated from the substrate by a first dielectric layer; depositing a first conductive layer on the surface of the substrate and in the second trenches; etching the first conductive layer to form the vertical gates of the transistors, and vertical gate connection pads between the extremity of the vertical gates and an edge of the substrate, while keeping a continuity zone in the first conductive layer between each connection pad and a vertical gate; and implanting doped regions on each side of the second trenches, to form drain regions of the transistors.. .
|Low temperature p+ polycrystalline silicon material for non-volatile memory device|
A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate.