 Patent Application Title |
Patent App Num. |
Date |
 Semiconductor memory having both volatile and non-volatile functionality and method of operating | 20130148422 | 20130613 |
 Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second locations and above a surface of the substrate and insulated from the surface by an insulating... |
| Fast startup hybrid memory module | 20130148457 | 20130613 |
 A memory device is provided comprising: a volatile memory device, a non-volatile memory device, a memory control circuit volatile memory controller coupled to the volatile memory device and non-volatile memory device, and a backup power source. The backup power source may be arranged to temporarily power the volatile memory devices and the memory control circuit upon a loss of power from the external power source. Additionally, a switch may serve to selectively couple: (a) a host memory bus to either the volatile memory device or non-volatile memory device; and (b) the volatile memory device to the non-volatile memory device. Upon reestablishment of power by an external power source from a power loss event, the memory control circuit is configured to restore data from the non-volatile memory... |
| Techniques for more efficient usage of memory-to-cpu bandwidth | 20130151567 | 20130613 |
 Techniques are provided for more efficiently using the bandwidth of the I/O path between a CPU and volatile memory during the performance of database operation. Relational data from a relational table is stored in volatile memory as column vectors, where each column vector contains values for a particular column of the table. A binary-comparable format may be used to represent each value within a column vector, regardless of the data type associated with the column. The column vectors may be compressed and/or encoded while in volatile memory, and decompressed/decoded on-the-fly within the CPU. Alternatively, the CPU may be designed to perform operations directly on the compressed and/or encoded column vector data. In addition, techniques are described that enable the CPU to perform vector processing operations on... |
| Techniques for maintaining column vectors of relational data within volatile memory | 20130151568 | 20130613 |
 Techniques are provided for more efficiently using the bandwidth of the I/O path between a CPU and volatile memory during the performance of database operation. Relational data from a relational table is stored in volatile memory as column vectors, where each column vector contains values for a particular column of the table. A binary-comparable format may be used to represent each value within a column vector, regardless of the data type associated with the column. The column vectors may be compressed and/or encoded while in volatile memory, and decompressed/decoded on-the-fly within the CPU. Alternatively, the CPU may be designed to perform operations directly on the compressed and/or encoded column vector data. In addition, techniques are described that enable the CPU to perform vector processing operations on... |
| High speed serial peripheral interface memory subsystem | 20130151751 | 20130613 |
 A memory subsystem is disclosed. The memory subsystem includes a serial peripheral interface (SPI) double data rate (DDR) volatile memory component, a serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component coupled to the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and a serial peripheral interface (SPI) double data rate (DDR) interface. The serial peripheral interface (SPI) double data rate (DDR) interface accesses the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and the serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component where data is accessed on leading and falling edges of a clock signal.
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| Lba bitmap usage | 20130151754 | 20130613 |
| Systems and methods are disclosed for logical block address (“LBA) bitmap usage for a system having non-volatile memory (“NVM”). A bitmap can be stored in volatile memory of the system, where the bitmap can store the mapping statuses of one or more logical addresses. By using the bitmap, the system can determine the mapping status of a LBA without having to access the NVM. In addition, the system can update the mapping status of a LBA with minimal NVM accesses. By reducing the number of NVM accesses, the system can avoid triggering a garbage collection process, which can improve overall system performance.
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| Method and apparatus for quick resumption | 20130151876 | 20130613 |
| When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed.
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| Method and apparatus for preventing unauthorized access to information stored in a non-volatile memory | 20130152206 | 20130613 |
| A communications device for ensuring secure data transfer provided having an interface device for controlling data transfer, an integrated circuit coupled to the interface device and having a processor, a non-volatile memory for storing at least program code for the processor, a volatile memory, an input pin and an output pin; and an electrical conductor which electrically connects the input pin and the output pin. The electrical conductor passes through an external portion of the enclosure, e.g., a slot, which allows a user to easily sever the electrical conductor. In operation, a portion of the program code detects when the electrical conductor is severed and causes the program code in the non-volatile memory to be erased, data transfer via the interface device to be disabled, and... |
| Single-ended volatile memory access | 20130141997 | 20130606 |
| A memory includes an array of memory cells that form rows and columns. The rows include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. For a read operation, a wordline drive circuit selects one memory cell of the pair, the selected memory cell being an addressed memory cell while the remaining cell is an unaddressed memory cell. In response to a wordline enable signal, a pass gate in the addressed memory cell couples the addressed memory cell via a complement bitline to an evaluation gate that resolves the data from the read operation. During the read operation, the unaddressed memory cell couples via another pass gate to a true bitline that... |
| Battery-less cache memory module with integrated backup | 20130142001 | 20130606 |
| A memory module is provided comprising a substrate having an interface to a host system, volatile memory, non-volatile memory, and a logic device. The logic device may receive the indicator of an external triggering event and copies data from the volatile memory devices to the non-volatile memory devices upon receipt of such indicator. When the indicator of the triggering event has cleared, the logic device restores the data from the non-volatile to the volatile memory devices. The memory module may include a passive backup power source (e.g., super-capacitor) that is charged by an external power source and temporarily provides power to the memory module to copy the data from volatile to non-volatile memory. A voltage detector within the memory module may monitor the voltage of an... |
| Dimm memory module reference voltage switching circuit | 20130135945 | 20130530 |
| “A non-volatile memory module includes a volatile memory circuit; an interface to a reference voltage source external to the module providing an external reference voltage to the volatile memory circuit by which the volatile memory circuit and external devices may communicate reliably at high speeds; an internal reference voltage generator; and a control circuit adapted to cause the volatile memory circuit to be decoupled from using the external reference voltage and coupled to using a reference voltage from the internal reference voltage generator upon the non-volatile memory module ceasing to draw power from an external power source.”
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| Memory systems | 20130138873 | 20130530 |
| Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile memory. The controller is configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory. The list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries. The controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to the list containing its maximum number of list entries and/or in response to an operation that would increase the number of list entries to a number equal to or greater than... |
| Image forming apparatus and power control method thereof | 20130138986 | 20130530 |
| An image forming apparatus includes a volatile memory and System-on-Chip (SoC) part. The SoC part includes an internal memory, a CPU for accessing the volatile memory in the normal mode; an interface part for receiving a external signal, and a control part for, when the interface part has no input during a first preset time, copying information stored to the volatile memory to the internal memory and converting to a first power saving mode to lower an operating frequency of the volatile memory and an operating frequency of the CPU, and when a normal mode switch signal is not input during a second preset time in the first power saving mode, controlling the CPU to access the information copied to the internal memory and converting to... |
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| Memory management system with power source and method of manufacture thereof | 20130128685 | 20130523 |
| A method of manufacture of the memory management system includes: fabricating a dual in-line memory module carrier; mounting a volatile memory device on the dual in-line memory module carrier; mounting a non-volatile memory on the dual in-line memory module carrier on a side opposite the volatile memory device; mounting an uninterruptible power supply on the dual in-line memory module carrier for maintaining a memory module power when a system power input decays; and mounting a controller logic integrated circuit on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply for copying data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects the decay of the system power input... |
| Information processing device and method | 20130132753 | 20130523 |
| An information processing device comprises a first memory, a second memory, data transfer circuitry, power gating circuitry, and a controller. The first memory comprises at least two volatile memory units The controller receives or generates a request for setting the information processing device into a reduced power mode; in response to the request, it selects specific memory units among the memory units; controls the data transfer circuitry to transfer data from the selected memory units to the second memory; and controls the power gating circuitry to power down the selected memory units.
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| Memory module, board assembly and memory system including the same, and method of operating the memory system | 20130120925 | 20130516 |
| Example embodiments include a memory module having a first volatile memory, a second volatile memory, a nonvolatile memory, and a controller configured to control an operation of the second volatile memory, and an operation of the nonvolatile memory. When first write data received from an external controller are written to the first volatile memory in a write operation, the controller receives and writes the first write data to the second volatile memory. The controller is configured to perform backup and restore operations using a buffer, the nonvolatile memory, the first volatile memory, and/or the second volatile memory. Example embodiments include a memory module having a first nonvolatile memory, a second nonvolatile memory, and a third nonvolatile memory, with corresponding backup and restore features. Example embodiments also... |
| Storage system logical block address de-allocation management and data hardening | 20130124777 | 20130516 |
| A bridge receives a power down command and in response converts the power down command to a data hardening command. The bridge issues the data hardening command to a solid state disk. In response to the data hardening command, data stored on the solid state disk is hardened. The hardening comprises writing data in volatile memory to non-volatile memory. The data that is hardened comprises user data and protected data. The data hardening command optionally comprises one or more of a flush cache command, a sleep command, and a standby immediate command.
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| Data restoration program, data restoration apparatus, and data restoration method | 20130124804 | 20130516 |
| A computer-readable recording medium stores a program that causes a computer capable of accessing a multicore processor equipped with volatile memories and a plurality of cores accessing the volatile memories, to execute a data restoration process. The data restoration process includes detecting a suspend instruction to any one of the cores in the multicore processor; and restoring, when the suspend instruction is detected, data stored in a volatile memory accessed by a core receiving the suspend instruction, the data being restored in a shared memory accessed by the cores in operation and based on parity data stored in the volatile memories accessed by the cores in operation other than the core receiving the suspend instruction.
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| Network security device and method | 20130125207 | 20130516 |
| The invention describes a method for hardening a security mechanism against physical intrusion and substitution attacks. A user establishes a connection between a network peripheral device and a network via a security mechanism. The security mechanism includes read only memory (ROM) that contains code that initiates operation of the mechanism and performs authentication functions. A persistent memory contains configuration information. A volatile memory stores user and device identification information that remains valid only for a given session and is erased thereafter to prevent a future security breach. A tamper-evident enclosure surrounds the memory elements, which if breached, becomes readily apparent to the user.
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| System controller, information processing system and method of saving and restoring data in the information processing system | 20130117518 | 20130509 |
| A system controller (1), which saves and restores data in a volatile memory (29A) in processing device (2A, 2B), is provided a non-volatile memory (12A) for provisional data and a non-volatile memory (12C) in a non-volatile area. The system controller (1) once saves the data in the non-volatile memory (12A) for the provisional data, and stores the data in the non-volatile memory (12A) for the provisional data to the non-volatile memory (12C) for formal data when it is found that the processing device (2A, 2B) has started by the provisional data in the non-volatile memory (12A) at a time of restoration. Therefore, even an abnormality occurs in the communication path or the memory for provisional data occurs the abnormality, it can be prevented to restore by... |
| Compact universal wireless adapter | 20130117580 | 20130509 |
| A universal wireless adapter, which includes a power source, a power management element, a main processing unit, at least two serial connections, a wireless transceiver coupled to one of the at least two serial connections, wherein the transceiver is operable according to IEEE Standards 802.11b/g/n, and is capable of operating in one of an infrastructure mode and an ad hoc mode. The adapter also includes a volatile memory chip and a single non-volatile memory chip. The adapter also includes a synchronous boost voltage converter, wherein the input voltage from the battery is boosted to a higher, second voltage output. The second of at least two serial connections is a Universal Serial Bus (USB) serial connection; and a display coupled to the main processing unit, and the... |
| Capacitor save energy verification | 20130111109 | 20130502 |
| A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.
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| Capacitor save energy verification | 20130111110 | 20130502 |
| A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.
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| Capacitor save energy verification | 20130111111 | 20130502 |
| A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.
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| Partitioning a memory into a high and a low performance partitions | 20130111180 | 20130502 |
| Examples disclose partitioning a volatile memory into a high performance partition and a low performance partition. Further the example discloses retrieving an application with a high performance data and a low performance data from a non-volatile memory to place the high and the low performance data in the high and low performance partitions, respectively. Additionally, the example also discloses receiving a request to decrease power and in response, reduce an amount of power to the high performance partition and maintaining an amount of power provided to the low performance partition.
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| Information processing device and management method of power saving mode | 20130097438 | 20130418 |
| In an information processing device, when shifting to a power saving mode, a volatile storage unit is controlled to continuously hold a program loaded to the volatile storage unit even in the power saving mode, and a logical value indicating the power saving mode is set to an input/output port of a third control unit. At time of activation, a second control unit determines if the logical value indicating the power saving mode has been set to the input/output port, and when the logical value has been set, recognizes the activation as a return from the power saving mode and executes the program held in the volatile memory, and when the logical value has not been set, recognizes the activation as a normal activation, loads the... |
| Memory unit, information processing device, and method | 20130097449 | 20130418 |
| A memory unit comprises at least two volatile memory elements, analyzing circuitry and power gate. The memory elements may for example be latches, flip-flops, or registers. Each of the memory elements has at least two different states including a predefined reset state. The analyzing circuitry generates a power-down enable signal in response to each of the memory elements being in its reset state. The power gate powers down the memory elements in response to the power-down enable signal. The memory elements may be arranged to assume their reset states upon powering up the memory unit.
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| Storage system, and data backup method and system restarting method of storage system | 20130097458 | 20130418 |
| In a storage system for performing data backup using a battery during blackout, when the blackout continues for a long time, problems such as the loss of volatile memory data due to the consumption of battery capacity and the difference in recovery time between controller units after power recovery occur during restarting of the system. The present invention solves the problems by selecting (a1) battery backup or (a2) saving of data in a nonvolatile device based on the battery capacity or setting of modes, and selecting (b1) inhibiting restart of the system or (b2) storing of data in the volatile memory to a nonvolatile memory means and performing access via write-through based on the remaining capacity of the battery when restarting the system after power recovery.... |
| Image forming apparatus and controlling method thereof | 20130088745 | 20130411 |
| An image forming apparatus includes an engine unit to execute an image forming job, a determination unit to repeatedly determine whether the image forming apparatus is in a standby state or not, based on whether the standby state to wait for execution of the image forming job is maintained for a predetermined time or not, and a controller to control the image forming apparatus to operate in a first power saving mode if it is determined that the image forming apparatus is in the standby state, wherein, in the first power saving mode, information stored in a volatile memory is copied to an internal memory and operation frequencies of a CPU, the volatile memory, and an intellectual property are lowered. Accordingly, power consumption in the standby... |
| Flash-dram hybrid memory module | 20130086309 | 20130404 |
| A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.
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| Prediction and cancellation of systematic noise sources in non-volatile memory | 20110016372 | 20110120 |
| Various embodiments of the invention pertain to a technique of recovering data from a portion of a non-volatile memory which was not reliably read because the number of read errors exceeded the ability of the ECC process to correct those errors. For each cell in that portion of memory, a quantized estimate is made of the amount of offset in the read reference voltage that is predicted to correct for any systematic noise that may have affected the reading of that cell. For each quantized offset, the read reference voltage is adjusted by that amount and data from the relevant cells is read. The combined results for all the cells are then processed through the ECC again.
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| Fault tolerant batch processing | 20110016354 | 20110120 |
| Among other aspects disclosed are a method and system for processing a batch of input data in a fault tolerant manner. The method includes reading a batch of input data including a plurality of records from one or more data sources and passing the batch through a dataflow graph. The dataflow graph includes two or more nodes representing components connected by links representing flows of data between the components. At least one but fewer than all of the components includes a checkpoint process for an action performed for each of multiple units of work associated with one or more of the records. The checkpoint process includes opening a checkpoint buffer stored in non-volatile memory at the start of processing for the batch. For each unit of... |
| Key storage device, biometric authentication device, biometric authentication system, key management method, biometric authentication method, and program | 20110016317 | 20110120 |
| Provided is a key storage device including a receiving unit for receiving package data that includes a template key for decrypting an encrypted template and an authentication key that is used for authentication performed with a terminal that uses the template key and the package data being in a data format that allows restoration only by the key storage device, a key information storage unit for restoring the template key and the authentication key, and for storing the template key and the authentication key in a tamper resistant non-volatile memory, a authentication unit for performing, in case a request for use of the template key is received from the terminal, authentication with the terminal by using authentication information that is based on the authentication key, and... |
| Managing backup device metadata in a high availability disk subsystem | 20110016260 | 20110120 |
| A system includes a data storage device, a controller coupled with the data storage device, a backup device coupled with the controller for backing up a modified portion of data and volatile memory metadata stored by the controller, and a backup power source for powering the controller. The controller includes a pre-specified region of volatile memory for storing backup device metadata for managing a modified portion of data, the metadata comprising one or more intents corresponding to modified data written back to the data storage device. The controller is configured to invalidate the one or more intents. During a restore operation, the controller is configured to store the backup device metadata in the pre-specified region of volatile memory when a charge on the backup power source... |
| Method and system for addressing a plurality of ethernet controllers integrated into a single chip which utilizes a single bus interface | 20110016245 | 20110120 |
| A method for processing network data is disclosed and may include receiving data via a single bus interface to which each of a plurality of Ethernet controllers are coupled, where the Ethernet controllers are integrated within a single chip. A particular one of the integrated Ethernet controllers may be identified based on information within the received data. The particular one of the integrated Ethernet controllers may be granted access to a shared resource within the single chip. The access to the shared resource may be granted using at least one semaphore register within the shared resource. The particular one of the integrated Ethernet controllers may be granted access to the single bus interface. The information may include a bus identifier, a bus device identifier and/or a... |
| Print apparatus and method of controlling printer | 20110016139 | 20110120 |
| A print apparatus includes a non-volatile memory retaining stored content even when power is not supplied to the print apparatus, the non-volatile memory having areas for a plurality of data, key codes specifying each of the plurality of data, and the amounts each indicating the length of each of the plurality of data; and a storage unit receiving a first command and information that follows the first command from a host device, and storing data included in the information, a key code specifying the data, and the amount indicating the length of the data in the non-volatile memory.
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| Secure removable card and a mobile wireless communication device | 20110014948 | 20110120 |
| A removable card for use with a mobile wireless communication device has a processor and a non-volatile memory, connected to the processor. The removable card has electrical connections for connecting to a mobile wireless communicating device for use by a user to access a common carrier network to access a network of interconnected computer networks (“Internet”). The card comprises a processor and a non-volatile memory connected to the processor. The non-volatile memory has two portions: a first portion and a second portion. The first portion is accessible by the provider of the common carrier network with the processor restricting access thereto by the user. The second portion is accessible by the provider of the common carrier network and with the processor granting access thereto to the... |
| Method of fabricating non-volatile memory device | 20110014759 | 20110120 |
| A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming... |
| Non-volatile semiconductor storage device | 20110013461 | 20110120 |
| For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
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| Dynamically adjustable erase and program levels for non-volatile memory | 20110013460 | 20110120 |
| Degradation of non-volatile storage elements is reduced by adaptively adjusting erase-verify levels and program-verify levels. The number of erase pulses, or the highest erase pulse amplitude, needed to complete an erase operation is determined. When the number, or amplitude, reaches a limit, the erase-verify level is increased. As the erase-verify level is increased, the number of required erase pulses decreases since the erase operation can be completed more easily. An accelerating increase in the degradation is thus avoided. One or more program-verify levels can also be increased in concert with changes in the erase-verify level. The one or more program-verify levels can increase by the same increment as the erase-verify level to maintain a constant threshold voltage window between the erased state and a programmed state,... |
| Method of programming/erasing the nonvolatile memory | 20110013459 | 20110120 |
| A method for programming/erasing a nonvolatile memory uses the multi-stage pulses to program/erase the memory so as to reduce the slow program/erase bit issue. The method applies a first predetermined voltage bias to a memory cell for a predetermined number of times. Each time the voltage bias is applied to the memory cell the memory is verified against a criterion. If the verification failed after the predetermined number of times applying the first predetermined voltage bias, a second predetermined voltage bias is applied to program/erase the nonvolatile memory. If the verification failed after applying the second predetermined voltage bias, a third predetermined voltage bias is applied to program/erase the nonvolatile memory.
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| Nonvolatile memory devices and programming methods thereof in which a program inhibit voltage is changed during programming | 20110013457 | 20110120 |
| Provided are nonvolatile memory devices and programming methods thereof. A non-volatile memory device is programmed by performing a plurality of programming loops on memory cells in a memory cell array and changing a program inhibit voltage applied to bit lines of the memory cells that have completed programming while performing the plurality of programming loops.
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| Non-volatile memory serial core architecture | 20110013455 | 20110120 |
| A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing... |
| Nonvolatile memory device including circuit formed of thin film transistors | 20110013453 | 20110120 |
| A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.
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| Non-volatile memory device with both single and multiple level cells | 20110013451 | 20110120 |
| A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions.
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| Method for adaptive setting of state voltage levels in non-volatile memory | 20110013450 | 20110120 |
| A method in which non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages... |
| Semiconductor integrated circuit device for driving liquid crystal display | 20110012906 | 20110120 |
| The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.
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| Test partitioning for a non-volatile memory | 20110010698 | 20110113 |
| Systems and methods are provided for testing a non-volatile memory, such as a flash memory. The non-volatile memory may be virtually partitioned into a test region and a general purpose region. A test application may be stored in the general purpose region, and the test application can be executed to run a test of the memory locations in the test region. The results of the test may be stored in the general purpose region. At the completion of the test, the test results may be provided from the general purpose region and displayed to a user. The virtual partitions may be removed prior to shipping the electronic device for distribution.
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| Memory system | 20110010606 | 20110113 |
| A memory system that can efficiently relieve a large number of defective bits with a small number of redundant bits is provided in a Flash-EEPROM nonvolatile memory. A memory system according to an embodiment of the present invention comprises a Flash-EEPROM memory in which a plurality of memory 5 having a floating gate or a charge trapping layer and capable of electrically erasing and writing data are arranged; a control circuit that controls a cache memory and the Flash-EEPROM memory; and an interface circuit that communicates with outside, wherein a plurality of group data and a plurality of flag data for storing presence of inversion of all bits of respective group data are stored in a memory area of the Flash-EEPROM memory.
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| Method for controlling storage system having multiple non-volatile memory units and storage system using the same | 20110010512 | 20110113 |
| A method for controlling a storage system and the storage system using this method are disclosed. In the storage system, at least two memory units share an I/O bus. The shared I/O bus transfers information for each memory unit to execute an operation. The operation has at least one high priority cycle and at least one low priority cycle. When a low priority cycle is overlapped with a high priority cycle, the low priority cycle is suspended, and the high priority cycle is operated first. After the high priority cycle is finished, the suspended low priority cycle is then resumed. By doing so, the shared I/O bus may be used by one memory unit during a busy cycle for another memory unit, during which the latter... |
| Storage system, method of controlling storage system, and method of controlling control apparatus | 20110010499 | 20110113 |
| A storage system including a storage, has a first power supplier for supplying electronic power, a second power supplier for supplying electronic power when the first power supplier not supplying electronic power to the storage system, a cache memory for storing data sent out from a host, a non-volatile memory for storing data stored in the cache memory, and a controller for writing the data stored in the cache memory into the non-volatile memory when the second supplier supplying electronic power to the storage system, for stopping the writing and for deleting data stored in the non-volatile memory so until a free space volume of the non-volatile memory being not less than a volume of the data stored in the cache memory when the first supplier... |
| Optimized page programming order for non-volatile memory | 20110010484 | 20110113 |
| During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host... |
| Nonvolatile memory device made of resistance material and method of fabricating the same | 20110008945 | 20110113 |
| A nonvolatile memory device using a resistance material and a method of fabricating the same are provided. The nonvolatile memory device includes a switching element, and a data storage part electrically connected to the switching element. In the data storage part, a lower electrode is connected to the switching element, and an insulating layer is formed on the lower electrode to a predetermined thickness. The insulating layer has a contact hole exposing the lower electrode. A data storage layer is filled in the contact hole and the data storage layer is formed of transition metal oxide. An upper electrode is formed on the insulating layer and the data storage layer.
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| Semiconductor device and a method of manufacturing the same | 20110008943 | 20110113 |
| The present invention provides a technology capable of reducing an area occupied by a nonvolatile memory while improving the reliability of the nonvolatile memory. In a semiconductor device, the structure of a code flash memory cell is differentiated from that of a data flash memory cell. More specifically, in the code flash memory cell, a memory gate electrode is formed only over the side surface on one side of a control gate electrode to improve a reading speed. In the data flash memory cell, on the other hand, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode. By using a multivalued memory cell instead of a binary memory cell, the resulting data flash memory cell can have... |
| Electronic equipment system and semiconductor integrated circuit controller | 20110007595 | 20110113 |
| An electronic equipment system includes a semiconductor integrated circuit having a nonvolatile memory storing information on a characteristic of the semiconductor integrated circuit; and a controller configured to control the semiconductor integrated circuit. The controller has a function of adjusting an access parameter to the semiconductor integrated circuit based on the information stored in the nonvolatile memory.
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| Current cancellation for non-volatile memory | 20110007581 | 20110113 |
| A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.
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| Nonvolatile memory devices and program methods thereof in which a target verify operation and a pre-pass verify operation are performed simultaneously using a common verify voltage | 20110007571 | 20110113 |
| Provided are nonvolatile memory devices and program methods thereof. A nonvolatile memory device provides a program voltage to a selected word line and performs a program verify operation. The nonvolatile memory device controls a bit line voltage of the next program loop according to the program verification result. In the program verification operation, a target verify voltage is used as a pre-verify voltage. The nonvolatile memory device controls the bit line voltage of the next program loop according to the program verification result, thus making it possible to reduce the threshold voltage distribution of a memory cell. Also, the nonvolatile memory device uses the target verify voltage as the pre-verify voltage, thus making it possible to increase the program verification speed.
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| Nonvolatile memory device, system, and related methods of operation | 20110007563 | 20110113 |
| A method of reading a nonvolatile memory device comprises measuring threshold voltage distributions of a plurality of memory cells, combining the measured threshold voltage distributions, and determining local minimum points in the combined threshold voltage distributions to determine read voltages for a predetermined group of memory cells.
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| Non-volatile memory cell with non-ohmic selection layer | 20110007551 | 20110113 |
| A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold.
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| Hierarchical cross-point array of non-volatile memory | 20110007548 | 20110113 |
| A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.
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| Information processing apparatus and wake-up control method | 20090327769 | 20091231 |
| According to one embodiment, an information processing apparatus includes devices including functions of generating wake-up signals, a controller which returns the apparatus to the power-on status in response to wake-up signals, and a first nonvolatile memory which stores information indicating whether the functions are enabled. The devices initializes such that the function is enabled if the information of the first nonvolatile memory has indicated that the function has been enabled when the power supply is started. The controller includes a second nonvolatile memory which stores information indicating devices to which power should be continuously supplied in the power-off status. The controller starts the power supply to the devices indicated that the power supply should be continued by the information of the second nonvolatile memory when the... |
| Power over ethernet reclassification | 20090327766 | 20091231 |
| A power over Ethernet (PoE) system has a reclassification functionality. The illustrative PoE system comprises a powered device (PD) and a power sourcing equipment (PSE) communicatively coupled to the PD. A classification identification component coupled to the PD encodes a classification value. A classification identification component can typically be implemented as a classification resistor, although any other suitable component such as a capacitor, inductor, register, or other structure or method can otherwise be implemented. The PoE system can further comprise a reclassification register in a non-volatile memory that stores a value indicative of a new classification state and a new classification identifier and a power switch that powers the powered device to a classification voltage. A PD controller is coupled to the powered device that reads... |
| Encrypting data on a non-volatile memory | 20090327759 | 20091231 |
| A non-volatile memory, such as a NAND memory, may be encrypted by reading source blocks, writing to destination blocks, and then erasing the source blocks. As part of the encryption sequence, a power fail recovery procedure, using sequence numbers, is used to reestablish a logical-to-physical translation table for the destination blocks.
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| Secure portable data transport & storage system | 20090327743 | 20091231 |
| A portable data transport device that provides security to data stored therein, and is configured to communicate data with a host computer for securing and transporting data. The portable data transport device includes a first processor and a biometric identification system. Upon successful biometric identification of an enrolled user, the first processor permits mounting of the data transport device to a host computer. However, prior to the commencement of read/write operations, cross-checking of stored identification codes of components of the portable data transport device occurs, including the use of a hash function. If any identifier does not match, no read/write data operations are permitted. The portable data transport device includes a file security program that includes a DLL encryption/decryption program having a self-check feature. Upon self... |
| System and method to accelerate access to network data using a networking unit accessible non-volatile storage | 20090327683 | 20091231 |
| In some embodiments, the invention involves a network controller having a pattern matching unit to identify whether boot file requested from a network accessible storage device for booting are stored locally in non-volatile memory accessible to the network controller. When required boot files are stored locally, the locally stored files are sent to the processor to boot the operating system. In an embodiment, retrieved boot files are automatically cached by the network controller in the accessible non-volatile memory. In other embodiments, a service operates to ensure coherency between locally store boot files and the boot filed stored on the network accessible storage. In another embodiment, data other than boot files may be stored and retrieved from the non-volatile memory. Other embodiments are described and claimed.
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| Storage capacity status | 20090327595 | 20091231 |
| In one embodiment of the present invention, a memory device is disclosed to include memory organized into blocks, each block having a status associated therewith and all of the blocks of the nonvolatile memory having collectively a capacity status associated therewith and a display for showing the capacity status even when no power is being applied to the display.
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| Read-only memory device with securing function and accessing method thereof | 20090327593 | 20091231 |
| The present invention provides a memory device and a method for accessing the memory device thereof. The memory device comprises an address encoding selector for selecting one of plurality of encoding circuits which encodes a first address into a second address, and a data decoding selector for selecting one of plurality of decoding circuits which decodes a first data corresponding to the second address into a second data and a non-volatile memory, coupled to address encoding selector and the data decoding selector, for storing the first data. The method for accessing the memory device comprises encoding a first address into a second address by an address encoding selector, and decoding a first data corresponding to the second address into a second data by a data decoding... |
| Table journaling in flash storage devices | 20090327589 | 20091231 |
| A method of table journaling in a flash storage device comprising a volatile memory and a plurality of non-volatile data blocks is provided. The method comprises the steps of creating a first copy in a first one or more of the plurality of non-volatile data blocks of an addressing table stored in the volatile memory, writing transaction log data to a second one or more of the plurality of non-volatile data blocks, and updating the first copy of the addressing table based on changes to the addressing table stored in the volatile memory after the second one or more of the plurality of non-volatile data blocks have been filled with transaction log data.
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| Personalization of portable data storage media | 20090327587 | 20091231 |
| In a method for the personalization of portable data carriers (700) into a non-volatile memory (350) of the data carrier (700) there are written personalization data (100,101,102), wherein the personalization at first is carried out as a virtual personalization (1000) in a virtual data carrier (500), then a memory image (250) is generated as a bit-true image of a memory (150) of the virtual data carrier (500) and finally the memory image (250) with the aid of its physical memory addresses is directly introduced into the memory (350) of the real data carrier (700). Here the personalization data (100, 101, 102) in addition to the initialization data (90) also comprise individualization data (110, 111, 112). Preferably, the introduction of the personalization data (100,101,102) into the data... |
| Banded indirection for nonvolatile memory devices | 20090327582 | 20091231 |
| Methods, apparatuses, and computer program products that enable banded indirection for nonvolatile memory devices, such as flash memory devices, are disclosed. One or more embodiments comprise a method for performing banded indirection when accessing data of a nonvolatile device. The methods comprise tracking fragmentation of a band of physical addresses of the nonvolatile memory device, storing a physical address of the band, and accessing data of a logical address of the band via the stored physical address based on the fragmentation of the band. Some embodiments comprise apparatuses for accessing data of nonvolatile devices using banded indirection. The embodiments comprise a nonvolatile memory element to store data, wherein the nonvolatile memory element has bands of physical addresses, a fragmentation detector to detect fragmentation of a band... |
| Flash sector seeding to reduce program times | 20090327578 | 20091231 |
| A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location of the data byte in an address translation table so the data byte may be accessed.
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| Controlled frequency core processor and method for starting-up said core processor in a programmed manner | 20090327569 | 20091231 |
| Embodiments of the invention relate to a driven-frequency processor core. It comprises at least one processor, a non-volatile memory comprising a startup program, a bridge interconnecting buses linking the various components of said processor core, an interface component. The non-volatile memory comprises at least two frequency-related configurations each corresponding to an operating mode of the buses and/or of the components of said processor core. The non-volatile memory comprises an item of information which makes it possible to determine which operating mode should be used, said item of information being read by the interface component so as to determine the chosen mode. The interface component generates one or more clock signals, the frequency of said generated clock signals corresponding substantially to that described by the configuration of... |
| Embedded system and hardware setting method | 20090327550 | 20091231 |
| An embedded system is provided, comprising a non-volatile memory, at least one slave unit and a master controller. The non-volatile memory comprises at least one hardware setting value and at least one identification number. All of the non-volatile memory, slave unit and the master controller are coupled to a bus. The master controller broadcasts an identification number through the bus to identify the non-volatile memory. Then, the master controller retrieves the slave identification numbers and the hardware setting values through the bus from the non-volatile memory.
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| Methods of fabricating nonvolatile memory devices | 20090325374 | 20091231 |
| Methods of fabricating nonvolatile memory devices are provided. An isolation layer is formed on a substrate. The substrate has a memory region and a well contact region and the isolation layer defines an active region of the substrate. A gate insulating layer is formed on the active region. The gate insulating layer is patterned to define an opening therein. The opening exposes at least a portion of the well contact region of the substrate and acts as a charge pathway for charges generated during a subsequent etch of the isolation layer. Related memory device are also provided.
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| Method for page- and block based scrambling in non-volatile memory | 20090323942 | 20091231 |
| A method and system for programming and reading data with reduced read errors in a memory device. In one approach, date to be written to the memory device is scrambled using a first pseudo random number which is generated based on a page of the memory device to which the data is to be written, to provide first scrambled data, which is scrambled using a second pseudo random number which is generated based on a block of the memory device to which the data is to be written. This avoids bit line-to-bit line and block-to-block redundancies which can result in read errors. The data may also be scrambled using a third pseudo random number that depends on a section within a page. Scrambling may also be... |
| Information-processing apparatus, device, and device setting control method | 20090323488 | 20091231 |
| According to one embodiment, an information processing apparatus includes one or more devices, a device control module which performs drive control of the one or more devices, and a nonvolatile memory. Each of the one or more devices includes a command reception module which receives from the device control module a command to cause the nonvolatile memory to store operation setting information, a setting module which performs, when the operation setting information has been stored in the nonvolatile memory at the time of power-on or resetting, operation setting based on the information, and an erasing module which erases the information stored in the nonvolatile memory after the setting means has completed the operation setting. The device control module includes a command issuing module which issues to... |
| Dual mode memory system for reducing power requirements during memory backup transition | 20090323452 | 20091231 |
| A controller of a memory system is configured to reduce power requirements during memory backup transition. When transitioning to backup mode, the memory system controller performs a number of power saving techniques. The controller may change a number of configuration settings in the volatile memory system, such as reducing output driver strength, increasing differential impedance, increasing on-die termination, disabling receiver input circuitry, and disconnecting the termination voltage network. The controller may also assert a hard reset to the storage controller system to significantly reduce the load and allow the voltage regulator to continue to provide power to the memory system for a longer period of time.
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| Data processing device and method of reading trimming data | 20090323440 | 20091231 |
| A data processing device according to the present invention comprises a nonvolatile memory and a trimming data read control circuit. The nonvolatile memory has a plurality of memory regions in which the same trimming data is stored. The trimming data read control circuit reads the trimming data from a random one of the plurality of memory regions.
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| Non-volatile memory device and program method thereof | 20090323431 | 20091231 |
| A method of programming a non-volatile memory device employing program loops. Each program loop comprises a programming operation and a subsequent plurality of verifying operations. The method includes preventing the next program loop based on the results of performing the plurality of verifying operations of a current program loop each verifying operation verifying whether the selected memory cell transistors are program-passed. The decision to re-program may be based on a program pass number of the memory cell transistors obtained as a result of the plurality of verifying operations of the current program loop.
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| Programming algorithm to reduce disturb with minimal extra time penalty | 20090323429 | 20091231 |
| Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all... |
| Methods, circuits and systems for reading non-volatile memory cells | 20090323423 | 20091231 |
| The present invention includes methods, circuits and systems for reading non-volatile memory (“NVM”) cells, including multi-level NVM cells. According to some embodiments of the present invention, there may be provided a NVM cell threshold voltage detection circuit adapted to detect an approximate threshold voltage associated with a charge storage region of a NVM cell, where the NVM cell may be a single or a multi-charge storage region cell. A decoder circuit may be adapted to decode and/or indicate the logical state of a NVM cell charge storage region by mapping or converting a detected approximate threshold voltage of the charge storage region into a logical state value.
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| Read disturb mitigation in non-volatile memory | 20090323412 | 20091231 |
| Read disturb is reduced in non-volatile storage. In one aspect, when a read command is received from a host for reading a selected word line, a word line which is not selected for reading is randomly chosen and its storage elements are sensed to determine optimized read compare levels for reading the selected word line. Or, a refresh operation may be indicated for the entire block based on an error correction metric obtained in reading the storage elements of the chosen word line. This is useful especially when the selected word line is repeatedly selected for reading, exposing the other word lines to additional read disturb. In another aspect, when multiple data states are stored, one read compare level is obtained from sensing, e.g., from a... |
| Capacitive discharge method for writing to non-volatile memory | 20090323393 | 20091231 |
| A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells.
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| Buried bit line anti-fuse one-time-programmable nonvolatile memory | 20090323388 | 20091231 |
| An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.− doped regions. Another N.sup.+ doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.− doped regions on the substrate. An anti-fuse is defined over the N.sup.+ doped region. Two insulator regions are deposited over the two P.sup.− doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse... |
| Round housings for virtual computing systems with stylesheets | 20090323271 | 20091231 |
| A computer system that has an outer shape that is round in outer cross-section. The computer housing can be formed of first and second housing parts that are each round in outer cross-section where one unscrews relative to another like taking the lid off a jar. The inside of the housing can store various kinds of nonvolatile memory and a processor. The user's entire processing environment may be stored within the memory and processor, and part of that environment may include stylesheet that represents specific styles of the user.
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| Image forming apparatus | 20090323120 | 20091231 |
| A reception controller receives print data. A volatile memory stores program information for performing image formation. An image forming unit forms an image based on the print data. An image formation controller receives the program information and controlling the image forming unit. A power supply stops supply of power to the volatile memory, image forming controller and image formation unit during supply power to the reception controller when a normal mode is switched to a power saving mode. An auxiliary volatile memory is supplied with power. An information saving path is for saving information in the volatile memory to the auxiliary volatile memory. In response to a detection of the switching from the power saving mode to the normal mode, the reception controller instructs the power... |
| Non-volatile memory device and method of fabricating the same | 20090321878 | 20091231 |
| Provided are a non-volatile memory device which can be extended in a stack structure and thus can be highly integrated, and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes: at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at the region in which the at least one first electrode crosses the at least one second... |
| Non-volatile memory device and method of fabricating the same | 20090321815 | 20091231 |
| A non-volatile memory device, including a substrate of a first conductivity type, the substrate including a plurality of wells of a second conductivity type, a plurality of memory cells in one of the plurality of wells of the second conductivity type, and a peripheral circuit including at least one first transistor of the second conductivity type on the substrate, and at least one second transistor of the first conductivity type in another one of the plurality of wells of the second conductivity type.
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| Vertical-type non-volatile memory device | 20090321816 | 20091231 |
| In a vertical-type non-volatile memory device, first and second single-crystalline semiconductor pillars are arranged to face each other on a substrate. Each of the first and second single-crystalline semiconductor pillars has a rectangular parallelepiped shape with first, second, third and fourth sidewalls. A first tunnel oxide layer, a first charge storage layer and a first blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the first single-crystalline semiconductor pillar. A second tunnel oxide layer, a second charge storage layer and a second blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the second single-crystalline semiconductor pillar. A word line makes contact with surfaces of both the first and second blocking dielectric layers. The word... |
| Memory cell transistors having bandgap-engineered tunneling insulator layers, non-volatile memory devices including such transistors, and methods of formation thereof | 20090321811 | 20091231 |
| A memory cell transistor comprises: an active region, the active region being elongated in a first direction of extension; a tunnel layer on the active region, the tunnel layer comprising a first tunnel insulating layer, a second tunnel insulating layer on the first tunnel insulating layer and a third tunnel insulating layer on the second tunnel insulating layer; a charge storage layer on the tunnel layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer, the control gate electrode being elongated in a second direction of extension that is transverse the first direction of extension, the active region having a first width in the second direction of extension, the second tunnel insulating layer having a second... |
| Variable resistance non-volatile memory cells and methods of fabricating same | 20080315174 | 20081225 |
| Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming a cup-shaped electrode on sidewalls of an opening in an insulation layer and through the opening on an ohmic layer that is stacked on a conductive structure. An insulation filling member is formed that at least partially fills an interior of the electrode. The insulation filling member is formed within a range of temperatures that is sufficiently low to not substantially change resistance of the ohmic layer. A variable resistivity material is formed on the insulation filling member and is electrically connected to the electrode.
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| Non-volatile memory devices and methods of fabricating the same | 20080315285 | 20081225 |
| Non-volatile memory devices and methods of fabricating the same are provided. The non-volatile memory devices may include a semiconductor substrate having a pair of sidewall channel regions extending from the semiconductor substrate and opposite to each other, and a floating gate electrode between the pair of sidewall channel regions and protruding from the semiconductor substrate. A control gate electrode may be formed on the semiconductor substrate and a portion of the floating gate electrode.
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| Dual-gate device and method | 20080315294 | 20081225 |
| A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if... |
| Compensated comparator for use in lower voltage, higher speed non-volatile memory | 20080315922 | 20081225 |
| Briefly, in accordance with one or more embodiments, an offset compensated comparator is capable of being utilized for higher speed, lower voltage use. The comparator comprises a cross-coupled latch comprising n type devices and p type devices. The threshold mismatch between n type devices is captured on capacitors coupled to the gates of the n type devices to capture the mismatch between the devices. After the threshold mismatch is captured, the comparator can be used as a typical cross coupled latch.
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| Security system control module | 20080316024 | 20081225 |
| A security system control module with a portable housing including a wireless receiver, control circuitry, nonvolatile memory, and a data connector. The receiver receives data transmissions from at least one wireless security device that monitors a condition of a premises in which the wireless security device is installed. The data connector exchanges data between the control circuitry and an external host device, and it also accepts from the external host device primary operating power for operating the wireless receiver, the control circuitry, and the nonvolatile memory. The control circuitry is adapted to process signals in accordance with a preprogrammed configuration file stored in the nonvolatile memory, the signals received via the wireless receiver from a wireless security device, and to communicate with an external computer located... |
| Video outputting apparatus and mounting method | 20080316190 | 20081225 |
| Disclosed is a video outputting apparatus including: a first display controlling section; and a second display controlling section for displaying predetermined image information during a period from a time when a power source is turned on to a time when the video information is displayed, wherein: the second display controlling section includes a reference clock generating circuit, a nonvolatile memory, and a controlling circuit including a plurality of external terminals for setting display setting information; the display setting information is set by a combination of setting of the plurality of external terminals; and the controlling circuit allows the displaying section to display the predetermined image information stored in the nonvolatile memory on a basis of the display setting information set by the plurality of external terminals... |
| Down-sampled image display | 20080316221 | 20081225 |
| A memory controller of an apparatus repeatedly retrieves a down-sampled file of a digitally captured image from a non-volatile memory for refresh of a raster display screen.
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| Method for changing the configuration of a media drive apparatus, computer readable medium, and media drive apparatus | 20080316650 | 20081225 |
| storing the value read from the removable storage medium in the non volatile memory of the media drive apparatus.
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| Method of making nonvolatile memory device containing carbon or nitrogen doped diode | 20080316795 | 20081225 |
| A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a silicon, germanium or silicon-germanium diode, doping the diode with at least one of nitrogen or carbon, and forming a second electrode over the at least one nonvolatile memory cell.
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| Method of making high forward current diodes for reverse write 3d cell | 20080316796 | 20081225 |
| A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell including a diode and a metal oxide antifuse dielectric layer over the first electrode, and forming a second electrode over the at least one nonvolatile memory cell. In use, the diode acts as a read/write element of the nonvolatile memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.
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| Nonvolatile memory device containing carbon or nitrogen doped diode | 20080316808 | 20081225 |
| A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration.
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| High forward current diodes for reverse write 3d cell | 20080316809 | 20081225 |
| A nonvolatile memory device includes at least one memory cell which comprises a diode and a metal oxide antifuse dielectric layer, and a first electrode and a second electrode electrically contacting the at least one memory cell. In use, the diode acts as a read/write element of the memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.
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| Memory unit | 20080316810 | 20081225 |
| A memory unit is provided herein. Two non-volatile devices are used to store a logic state of the memory unit into the non-volatile devices. Although a power supply for the memory unit is shut down, the non-volatile devices still keep the data stored therein. The present invention not only has an advantage of high speed operation of a static random access memory (SRAM), but also has a function for storing data of a non-volatile memory.
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| Methods of programming multilevel cell nonvolatile memory | 20080316815 | 20081225 |
| A memory system includes a first block in which data is stored with a low density and a second block in which data is stored with a high density. When data is received it is written to the first block, and in parallel some of the data is written to the second block, so that the second block is partially programmed. The second block is later fully programmed by copying additional data from the first block.
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| Systems for programming multilevel cell nonvolatile memory | 20080316816 | 20081225 |
| A memory system includes a first block in which data is stored with a low density and a second block in which data is stored with a high density. When data is received it is written to the first block, and in parallel some of the data is written to the second block, so that the second block is partially programmed. The second block is later fully programmed by copying additional data from the first block.
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| Method and system for programming non-volatile memory cells based on programming of proximate memory cells | 20080316817 | 20081225 |
| A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the proximate cells are verified by read, comparison, and, if necessary, reprogramming operations to compensate for charge added to proximate memory cells resulting from programming the row. In another example of the invention, a row of memory cells is programmed with charge levels that take into account the charge that will be added to the memory cells when proximate memory cells are subsequently programmed.
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| Non-volatile memory device and method of operating | 20080316818 | 20081225 |
| A non volatile memory device and method of operating including providing a verification voltage to a gate of a selected memory cell within multiple memory cells and providing a first pass voltage to a gate of a non-selected memory cell within the memory cells during a program verification operation; and providing a read voltage to the gate of the selected memory cell and providing a second pass voltage to the gate of the non-selected memory cell during a read operation. The second pass voltage is greater than the first pass voltage.
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| Non-volatile memory device and method of operating the same | 20080316824 | 20081225 |
| Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which... |
| Nonvolatile semiconductor device, system including the same, and associated methods | 20080316831 | 20081225 |
| A nonvolatile memory device is provided. The nonvolatile memory device includes a semiconductor substrate and memory cell units arranged in a matrix on the semiconductor substrate. Each of the memory cell units includes a tunnel insulation layer on the semiconductor substrate. A first memory gate and a second memory gate are disposed on the tunnel insulation layer. An isolation gate is disposed between the first and second memory gates. A word line covers the first memory gate, the second memory gate and the isolation gate. A method of forming the nonvolatile memory device is also provided.
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| Dual-gate device and method | 20080318380 | 20081225 |
| A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if... |
| Split gate type nonvolatile memory device and method of fabricating the same | 20080318406 | 20081225 |
| In a split gate type nonvolatile memory device and a method of fabricating the same. A supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level.
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| Method for achieving uniform chemical mechanical polishing in integrated circuit manufacturing | 20080318428 | 20081225 |
| A method for planarizing a surface in an integrated circuit manufacturing process provides a first film of a first material over a non-uniform surface, such as a surface including isolation trenches. The first material includes, for example, a polysilicon layer to be used to form floating gates in a non-volatile memory integrated circuit. A second film, which is a sacrificial film formed using a second material, such as silicon oxide, is then provided over the first film. Partial removal of the second film is carried out using chemical mechanical polishing until a portion of the first film is exposed using a first slurry that is selective to the first material. Thereafter, the remaining layer of the second film is removed, along with planarization of the surface,... |
| Nonvolatile memory card and configuration conversion adapter | 20080320206 | 20081225 |
| A nonvolatile memory card, including interface parts for plural kinds of memory cards; interface controllers corresponding to the interface parts for corresponding memory cards; and a switch configured to select a single one of the interface controllers.
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| High performance and endurance non-volatile memory based storage systems | 20080320209 | 20081225 |
| High performance and endurance non-volatile memory (NVM) based storage systems are disclosed. According to one aspect of the present invention, a NVM based storage system comprises at least one intelligent NVM device. Each intelligent NVM device includes a control interface logic and NVM. Logical-to-physical address conversion is performed within the control interface logic, thereby eliminating the need of address conversion in a storage system level controller. In another aspect, a volatile memory buffer together with corresponding volatile memory controller and phase-locked loop circuit is included in a NVM based storage system. The volatile memory buffer is partitioned to two parts: a command queue; and one or more page buffers. The command queue is configured to hold received data transfer commands by the storage protocol interface bridge,... |
| Nonvolatile memory control device, nonvolatile memory control method, and storage device | 20080320211 | 20081225 |
| According to an embodiment of the present invention is to increase the number of arbitrarily available physical blocks in a nonvolatile memory device. The device comprises a file system control section which analyzes a file allocation table (FAT) to identify an unused logical block, a logical/physical block address conversion table management section which uses a table of a logical/physical block address conversion table information section to obtain a first physical block corresponding to the unused logical block and releases the association between the first physical block and the unused logical block, and a physical block address information management section which registers the first physical block in a physical block address information section as an arbitrarily available second physical block.
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| Control device and control method of nonvolatile memory and storage device | 20080320212 | 20081225 |
| According to one embodiment, the control device according to an embodiment of the present invention, facilitates and speeds up averaging processing of the number of erases of a physical block (exchange processing of a physical block) of a nonvolatile memory. The device includes a file system control section that analyzes a file system of a nonvolatile memory and identifies a logical block of a read-only file, a logical/physical block address conversion table management section that obtains a first physical block corresponded to the logical block, and a physical block information management section that selects a second physical block that can be optionally used. Further, the device includes a physical block information modification section that moves data of the first physical block to the second physical block.
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| Control device of nonvolatile memory and control method thereof, and storage device | 20080320213 | 20081225 |
| According to one embodiment, the overall information processing time can be shortened. There are provided (1) a logical/physical block address conversion table information section that associates a logical block address of a logical address space with a physical block address of a nonvolatile memory device, (2) a physical block use state management section and a physical block erase count management section to read out erase count information from a physical block of which the logical block address and the physical block address are not associated, and a physical block that satisfies a predetermined condition set related to the erase count information is selected as a selected physical block, and (3) a logical/physical block address conversion table management section that registers a physical block address of the... |
| Executing i/o requests for a disk drive | 20080320217 | 20081225 |
| Executing I/O requests for a disk drive including receiving, by a device driver from a volume manager, a plurality of I/O requests; retrieving, from non-volatile memory by the device driver, information describing access times for storage locations on the disk drive; and executing, by the device driver, the I/O requests in a sequence, including identifying, in dependence upon the information describing access times for storage locations on the disk drive, the sequence for executing the I/O requests.
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| Method, system, and apparatus for encrypting, integrity, and anti-replay protecting data in non-volatile memory in a fault tolerant manner | 20080320263 | 20081225 |
| According to some embodiments, a method for providing encryption, integrity, and anti-replay protection of data in a fault tolerant manner is disclosed. A data blob and an anti-replay table blob are copied to a temporary storage region in a non-volatile memory. In an atomic operation, a status indicator is set and a monotonic counter is incremented after the data blob and the anti-replay table blob are copied to the temporary storage region. If a fault occurs while the status indicator is set, the data blob and the anti-replay table blob may be recovered from the temporary storage region.
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| Allocating disk space on a disk drive | 20080320266 | 20081225 |
| Allocating disk space on a disk drive, the disk drive controlled by a device driver and a volume manager, including receiving in the volume manager a request to allocate disk space for semi-sequential data access of structured data; retrieving, from non-volatile memory by the volume manager, information describing access times for storage locations on the disk drive; and allocating, by the volume manager in dependence upon the retrieved information, disk space for the structured data.
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| Personal radiation detector and method of operation of same | 20070295904 | 20071227 |
| A multipurpose, small-sized, ergonomic device determines and measures ionizing radiation and stores the obtained data for subsequent processing. An ionizing radiation detector is used as a sensing unit and is connected with a microcontroller by a converter. The device contains a nonvolatile memory for data arrangement and command set and an interface for connection with a computer. Measurements are carried out constantly, records are made periodically by the user setting. In the case of a value current or accumulated established criterion level excess, the device gives an alert signal and stores current value, not waiting for periodic write time. At connection with a computer, these data are automatically transferred to the computer and processed for identification and saving.
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| Nonvolatile memory cell with concentric phase change material formed around a pillar arrangement | 20070295948 | 20071227 |
| A memory cell comprises a first feature and a second feature. The second feature comprises a dielectric material and defines an opening at least partially overlying the first feature. A third feature is formed on the first feature and partially fills the opening in the second feature. What is more, a phase change material at least fills a volume between the second feature and the third feature. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to the memory cell.
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| Non-volatile memory device having four storage node films and methods of operating and manufacturing the same | 20070296033 | 20071227 |
| A nonvolatile memory device that may operate in a multi-bit mode and a method of operating and manufacturing the nonvolatile memory device are provided. The nonvolatile memory device may include a first source region and a first drain region that are respectively in first fin portions on both sides of a control gate electrode and respectively separated from the control gate electrode, a second source region and a second drain region that are respectively formed in second fin portions on both sides of the control gate electrode and respectively separated from the control gate electrode, first and second storage node layers that are formed with the control gate electrode therebetween and on the side of the first fin opposite to a buried insulating layer between first... |
| Image forming apparatus and image forming method | 20070296932 | 20071227 |
| An image forming apparatus includes an image data input unit configured to take in image data, an image data storing unit having a hard disk drive and a volatile memory for saving the image data inputted from the image data input unit, a mode selecting unit configured for a user to select one of a normal security mode and a high security mode as a security mode for the image data, and an image data output unit configured to output the image data saved in the image data storing unit, in a predetermined format. If the normal security mode is selected by the mode selecting unit, the image data is saved in the hard disk drive, and if the high security mode is selected, the image... |
| Circuit interrupter including nonvolatile memory storing cause-of-trip information | 20070297113 | 20071227 |
| A circuit breaker includes separable contacts, an operating mechanism structured to open and close the separable contacts, and a trip mechanism. The trip mechanism includes a sensor structured to sense current flowing through the separable contacts, a processor cooperating with the sensor to determine a plurality of different trip conditions responsive to the sensed current, a nonvolatile memory operatively associated with the processor, and a trip actuator cooperating with the processor and the operating mechanism to trip open the separable contacts responsive to one of the different trip conditions from the processor. The processor is structured to save in and retrieve from the nonvolatile memory cause-of-trip information for the different trip conditions including the one of the different trip conditions.
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| Mos based nonvolatile memory cell and method of operating the same | 20070297224 | 20071227 |
| A non-volatile memory cell formed on a sidewall of MOS transistor and method of operating the same are disclosed. The MOS based non-volatile memory cell is formed in the n-well and compatible with CMOS processes comprising a selecting gate, two ONO spacers, a p+ source/drain, and a p extended source region and an n extended drain. To program the cell, two strategies can be taken: (1) a band to band hot electron injection can be carried out and (2) channel hot hole induced hot electron injection. To read the nonvolatile cell, a reverse read is taken. In the reading process, the biased on the selecting gate has to make sure form a channel beneath selecting gate having its narrower end contacting with a the depletion boundary... |
| Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages | 20070297226 | 20071227 |
| A set of non-volatile storage elements undergoes initial programming, after which a reprogramming, with higher verify levels, is performed in non-real time, such as when a control enters a standby mode, when no other read or write tasks are pending. The reprogramming can program pages in the set one at a time, stopping at a page boundary when another read or write task is pending, and restarting when the control become available again. Status flags can be provided to identify whether a page and/or the set has completed the reprogramming. In another aspect, a higher pass voltage is applied to unselected word lines during the reprogramming. In another aspect, an error count is determined using a default set of read voltages, and an alternative set of... |
| Nonvolatile memory device | 20070297228 | 20071227 |
| A nonvolatile memory device implements a program routine followed by a program-verify routine when recording or modifying stored data. The nonvolatile memory device may include an array of memory cells for storing data, a sense node, and a gating circuit for selectively connecting a bitline of the array of memory cells to the sense node. The nonvolatile memory device may also include a page buffer coupled to the sense node. The page buffer may include a main latch for storing data to be written in the nonvolatile memory device, a cache latch for storing data supplied on an input line of the nonvolatile memory device to be transferred in the main latch through a source liner and a temporary static latch connected to the main latch... |
| Non-volatile memory structure | 20070297230 | 20071227 |
| A non-volatile memory array structure includes N bit lines, M first word lines, M×N first memory cells, a second word line, n repair circuits and a sense amplifier. The N bit lines and M first word lines are interlaced to control the M×N first memory cell. The second word line is placed across the n bit lines. Each of the repair circuits is electrically connected between the corresponding bit line and the sense amplifier. M and N are natural number.
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| Non-volatile memory structure | 20070297231 | 20071227 |
| A nonvolatile memory cell utilizes a programmable conductor random access memory (PCRAM) structure instead of a polysilicon layer for a floating gate. Instead of storing or removing electrons from a floating gate, the programmable conductor is switched between its low and high resistive states to operate the flash memory cell. The resulting cell can be erased faster and has better endurance than a conventional flash memory cell.
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| Non-volatile memory and method with bit line to bit line coupled compensation | 20070297234 | 20071227 |
| When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
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| Semiconductor memory device | 20070297236 | 20071227 |
| A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a data storage circuit configured to store data simultaneously read from or written into the memory cell array, the data constituting a collective processing unit; and a data state judgment circuit configured to sequentially judge the data states of multiple divided areas, which are obtained by dividing the collective processing unit.
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| Memory device with a nonvolatile memory array | 20070297239 | 20071227 |
| A memory device having a nonvolatile memory array, at least one driver for programming the memory array, which driver is connected to the memory array in order to drive a programming potential, and a drive circuit for controlling the at least one driver, wherein the drive circuit has at least one switch for switching a current as a function of the digital logic potential at the input and the drive circuit has a current-to-voltage converter connected to the output, which converter is designed to output a control potential depending on the switched current for driving the at least one driver.
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| System for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages | 20070297245 | 20071227 |
| A set of non-volatile storage elements undergoes initial programming, after which a reprogramming, with higher verify levels, is performed in non-real time, such as when a control enters a standby mode, when no other read or write tasks are pending. The reprogramming can program pages in the set one at a time, stopping at a page boundary when another read or write task is pending, and restarting when the control become available again. Status flags can be provided to identify whether a page and/or the set has completed the reprogramming. In another aspect, a higher pass voltage is applied to unselected word lines during the reprogramming. In another aspect, an error count is determined using a default set of read voltages, and an alternative set of... |
| Method for programming non-volatile memory using variable amplitude programming pulses | 20070297247 | 20071227 |
| Non-volatile storage elements are programmed using a series of voltage waveforms, where each waveform includes different portions with different amplitudes. For example, the amplitudes can vary as a decreasing staircase or ramp. Storage elements which are to be programmed to the highest level are programmed using the entire waveform, while storage elements which are to be programmed to intermediate and lower levels are programmed using different portions of the waveform. For example, the storage elements to be programmed to the intermediate level are programmed using the last two-thirds of each waveform, while the storage elements to be programmed to the lower level are programmed using the last one-third of each waveform. For these storage elements, programming is inhibited for a portion of the waveform by applying... |
| Nonvolatile memory, apparatus and method for determining data validity of the same | 20070297265 | 20071227 |
| A nonvolatile memory including a memory cell that stores data in a plurality of pages included in a block according to a voltage applied to a memory cell is provided. The nonvolatile memory includes a block that includes a first page including first data that stores data recorded by a user, and a second page including second data area that stores data recorded by a user, wherein the second page records count-information on states represented by a bit pair in the same position of the first data area and the second data area.
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| Control circuit for optoelectronic module with integrated temperature control | 20070297468 | 20071227 |
| A microprocessor is used to control the temperature of a laser emitter and thereby regulate the wavelength of optical signals from the laser. A serial interface in the microprocessor provides input and output lines to a host device, and temperature lookup tables are stored in nonvolatile memory. Control logic processes information stored in the memory as well as information on operating conditions of the laser emitter to precisely control the temperature of the laser emitter. A thermo-electric cooler adjusts the temperature of the laser emitter.
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| Non-volatile memory having three states and method for manufacturing the same | 20070298569 | 20071227 |
| Disclosed is a non-volatile memory having three data states and a method for manufacturing the same. The non-volatile memory includes a silicon substrate having a device separation film; a floating gate formed on the silicon substrate; a tunnel oxide film interposed between the silicon substrate and the floating gate below both ends of the floating gate; a ferroelectric substance interposed between the silicon substrate and the floating gate inside the tunnel oxide film; a diffusion barrier film enclosing the ferroelectric substance; a control gate formed on the substrate including the floating gate; a gate oxide film formed below the control gate; spacers formed on both lateral walls of the laminated floating gate and control gate including the tunnel oxide film and gate oxide film, respectively; and... |
| Single chip data processing device with embedded nonvolatile memory and method thereof | 20070298571 | 20071227 |
| A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors... |
| Link protocol control for serial protocols | 20070299999 | 20071227 |
| A state machine encoded in state machine instructions is stored in non-volatile memory, and loaded into volatile memory in a hardware engine for use by the hardware engine upon power up or reset. Storing the state machine for a phy reset sequence in non-volatile memory coupled to the hardware engine allows protocol modifications to the state machine to be performed in the non-volatile memory.
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| Using multiple non-volatile memory devices to store data in a computer system | 20070300007 | 20071227 |
| Provided are a method, system, and machine readable medium for using multiple non-volatile memory devices to store data in a computer system. Access to a first and second memory devices are managed. The first memory device has faster read access and slower write access relative to the second memory device and the second memory device has slower read access and faster write access relative to the first memory device. Write requests to the first memory device are cached in the second memory device.
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| Reconfigurable processor integrated circuit | 20070300047 | 20071227 |
| A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the... |
| Non-volatile semiconductor memory device | 20070300056 | 20071227 |
| A non-volatile semiconductor memory device includes a non-volatile memory element group having a first storage area which stores booting data and a second storage area to store storage addresses of the first storage area. The device further includes a detecting circuit which detects turn-ON of a power supply. The device further includes a register to which the storage address stored in the second storage area is read out and transferred from the non-volatile memory element group when the detecting circuit detects turn-ON of the power supply, and a control circuit which performs a control operation to output booting data stored in the first storage area and corresponding to the storage address transferred to the register after an initialization operation performed at the power supply turn-ON time... |
| Operating method of non-volatile memory device | 20070290273 | 20071220 |
| An operating method of non-volatile memory device is provided. The device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the channel region, a charge storage layer disposed on the insulating layer, a multi-layer tunneling dielectric structure on the charge storage layer, and a gate disposed on the multi-layer tunneling dielectric structure. A negative bias is supplied to the gate to inject electrons into the charge storage layer through the multi-layer tunneling dielectric structure by −FN tunneling so that the threshold voltage of the device is increased. A positive bias is supplied to the gate to inject holes... |
| Structure for a non-volatile memory device | 20070291526 | 20071220 |
| System for a memory device. An electronic device includes a non-volatile memory array. The non-volatile memory array includes a first transistor and a second transistor. The first and second transistors have a shared doped region. A first word line is formed along a first axis. The first word line includes a first gate electrode for the first transistor and a second gate electrode for the second transistor. The non-volatile memory array includes a bit line formed along a second axis. The first axis is perpendicular to the second axis. The bit line is electrically connected to the shared doped region.
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| Non-volatile memory device and method thereof | 20070291536 | 20071220 |
| A non-volatile memory device and method thereof are provided. The example non-volatile memory device may include a plurality of main cells, each of the plurality of main cells arranged at first intersection regions between one of a plurality of word lines and one of a plurality of main bit line pairs and a plurality of flag cells, each of the plurality of flag cells arranged at second intersection regions between one of the plurality of word lines and a plurality of flag bit line pairs, each of the plurality of flag cells configured to store page information in a manner such that page information associated with main cells corresponding to one of the main bit line pairs is stored in flag cells corresponding to more than... |
| Microprocessor boot-up controller, nonvolatile memory controller, and information processing system | 20070291537 | 20071220 |
| An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.
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| Clock synchronized non-volatile memory device | 20070291538 | 20071220 |
| A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on... |
| Microprocessor boot-up controller, nonvolatile memory controller, and information processing system | 20070291540 | 20071220 |
| A nonvolatile semiconductor memory controller has a plurality of word lines and a plurality of memory cells. Each memory cell is connected to a corresponding one of the word lines, and each memory cell has N threshold voltages, where N is a natural number of 4 or greater. The plurality of memory cells constitutes a plurality of pages, the same data is written in each of the pages when writing in the nonvolatile memory, and only part of the pages to which the same data is written is accessed when reading out the nonvolatile memory.
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| Programming method for nand flash | 20070291542 | 20071220 |
| A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells utilizing a drain-side self boost, modified drain-side self boost or local self boost process that increases the pass voltage (Vpass_high) on a word line on the source line side of a memory cells selected for programming to boost the voltage on the source of the adjacent blocking cell of the string. This drives the adjacent blocking cell further into cutoff and increases boosting by decreasing channel leakage to the source line during programming.
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| Processor circuit and method of allocating a logic chip to a memory chip | 20060289658 | 20061228 |
| A processor circuit includes a logic chip with a logic circuit and a non-volatile memory as well as a memory chip with a non-volatile memory. A key is stored in the non-volatile memory of the logic chip by using electronic fuses. Further, personalization information is stored, which signalizes that the logic chip is allocated to a memory chip. A chip identification encrypted with the key is stored in the memory chip at an ID memory area. During starting up the processor, it is first verified whether the encrypted logic chip identification stored in the memory chip is authentic or not. Thereby, a simple and inexpensive personalization of a memory chip to a logic chip can be obtain in order to ward off attacks with regard to... |
| Oxide epitaxial isolation | 20060289923 | 20061228 |
| Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming at least one first recess through the first oxide layer to the strained substrate, and forming at least one vertical epitaxial structure in the recess. A crystal lattice of the vertical epitaxial structure is aligned with a crystal lattice of the strained substrate.
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| Low power electrically alterable nonvolatile memory cells and arrays | 20060289924 | 20061228 |
| Nonvolatile memory cells having a conductor-filter system, a conductor-insulator system, and a charge-injection system are provided. The conductor-filter system provides band-pass filtering function, charge-filtering function, and mass-filtering function to charge-carriers flows. The conductor-insulator system provides Image-Force barrier lowering effect to collect charge-carriers. The charge-injection system includes the conductor-filter system and the conductor-insulator system, wherein the filter of the conductor-filter system contacts the conductor of the conductor-insulator system. Apparatus on cell architecture are provided for the nonvolatile memory cells. Additionally, apparatus on array architectures are provided for constructing the nonvolatile memory cells in memory array. Method on manufacturing such memory cells and array architectures are provided.
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| Non-volatile memory, manufacturing method and operating method thereof | 20060289925 | 20061228 |
| A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.
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| Non-volatile memory with hole trapping barrier | 20060289927 | 20061228 |
| A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control gate and a channel region of a transistor to trap positively charged holes. The multilayer charge trapping dielectric comprises two layers of dielectric having different band gaps such that holes are trapped at a barrier between the two layers.
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| Non-volatile memory devices and related methods | 20060289938 | 20061228 |
| A semiconductor device may include a semiconductor substrate having an active region on a surface thereof. First, second, and third gate lines may cross the active region of the semiconductor substrate, and the first, second, and third gate lines may be arranged in parallel across the active region, and the second gate line may be between the first and third gate lines. A first insulating layer may fill a space between the first and second gate lines on the active region, and the first insulating layer may be a layer of a first insulating material. First insulating spacers may be provided on opposing sidewalls of the third gate line and on a sidewall of the second gate line adjacent to the third gate line, and the... |
| Nonvolatile memory devices having a fin shaped active region and methods of fabricating the same | 20060289944 | 20061228 |
| A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer... |
| Method and apparatus for maintaining topographical uniformity of a semiconductor memory array | 20060289946 | 20061228 |
| A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer such as a floating gate. A dummy stack ring is formed around the memory array. An insulating layer is formed over the memory array. The dummy stack ring has a composition and height substantially the same as a composition and height of the gate stack to insure that a CMP of the insulating layer is uniform across the memory array.
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| Non-volatile memory, manufacturing and operating method thereof | 20060291281 | 20061228 |
| A non-volatile memory having a substrate, a select gate, a pair of charge storage layers, a pair of source/drain regions and a control gate is provided. At least a pair of trenches are formed in the substrate. The select gate is formed on the substrate between the pair of trenches. A pair of charge storage layers is formed on the sidewalls of the trenches next to the select gate. A pair of source/drain regions is formed in the substrate at the bottom of the trenches. The control gate is formed on the substrate to fill the trenches completely.
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| Non-volatile memory device having page buffer for verifying pre-erase | 20060291289 | 20061228 |
| Non-volatile memory devices have a page buffer that can verify pre-erase. A non-volatile memory device may include a cell array having a plurality of strings consisting of memory cells disposed at the intersection regions of bit lines and word lines, and a plurality of page buffers connected to the bit lines through a sensing line. Each of the plurality of page buffers may include a pre-erase detection unit that detects pre-erase in response to a signal of the sensing line in order to verify whether data programmed into the memory cells have been erased, a main erase detection unit that detects main erase in response to a signal of the sensing line in order to verify whether data programmed into the memory cells have been erased,... |
| Circuit and method for adaptive incremental step-pulse programming in a flash memory device | 20060291290 | 20061228 |
| Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g., ΔV1) and then, in response to... |
| Method for enhanced block management | 20060291304 | 20061228 |
| A method and apparatus is described herein for managing bad blocks/sectors in a nonvolatile memory. Upon detecting an input/output fault to a target block in a nonvolatile memory, the target block is remapped to a spare block, if the block is predicted as a bad block. Remapping is done for blocks used to store code both in serial execution code sequences and code sequences utilizing address translation. The remapping of bad blocks/sectors in nonvolatile memory allows nonvolatile memory in computer systems to be robust and resilient in handling bad blocks.
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| Finfets, nonvolatile memory devices including finfets, and methods of forming the same | 20060292781 | 20061228 |
| A FinFET includes a fin that is on a substrate and extends away from the substrate. A device isolation layer is disposed on the substrate on both sides of the fin. An insulating layer is between the fin and the substrate. The insulating layer is directly connected to the device isolation layer and has a different thickness than the device isolation layer. A gate electrode crosses over the fin. A gate insulating layer is between the gate electrode and the fin. Source and drain regions are on the fins and on opposite sides of the gate electrode. Related nonvolatile memory devices that include FinFETs and methods of making FinFETs and nonvolatile memory devices are also disclosed.
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| Method for the manufacture of a non-volatile memory device and memory device thus obtained | 20060292792 | 20061228 |
| The present invention relates to a method for processing of a non-volatile memory cell (50) which comprises a double gate stack and a single access gate. The method combines a way of processing an access gate with drain implant, separate from source implant, in a self-aligned manner. The method of the present invention does not require mask alignment sensitivity and makes it possible to implant self-aligned an extended drain for erasing of the memory device. Furthermore, the method provides a way of performing separately drain and source implant with different doping without the use of an additional mask.
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| Ono formation of semiconductor memory device and method of fabricating the same | 20060292800 | 20061228 |
| A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.
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| Method for manufacturing semiconductor device and non-volatile memory | 20060292850 | 20061228 |
| A method for manufacturing semiconductor device is provided. First, a substrate is provided. Then, a plurality of first gate lines disposed in parallel to each other and a first dummy gate line disposed in a direction perpendicular to the first gate lines are formed on the substrate. There is a first gap between the first dummy gate line and the first gate lines and there is a second gap between every pair of adjacent first gate lines. Thereafter, a second composite layer and a conductive layer are sequentially formed over the substrate. The conductive layer is etched back to form a plurality of second device structures that completely fills the second gaps. Then, the conductive layer in the first gap is removed.
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| Recovery of calibrated center steering position after loss of battery power | 20060293818 | 20061228 |
| The steering angle of a vehicle is monitored using position sensors of an electric motor of an electric power assisted steering (EPAS) system. A position of the electric motor corresponding to the straight-ahead, center position of the steering system is stored in non-volatile memory during a steering calibration procedure, such as an end-of-line calibration in a vehicle assembly plant. Following power loss due to a dead battery, a steering angle zeroing procedure performed in a vehicle stability control (VSC) system generates a center position with enough accuracy to be within one electrical cycle of the motor. The pre-stored electric motor position is then used to determine the electrical cycle where the center position was located, and accurate monitoring of steering angle is resumed.
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| Electronic commerce session management | 20060294203 | 20061228 |
| Methods and apparatuses for electronic session management are disclosed. In one embodiment, a user is connected to a server when initiating a session. Until a predetermined period of time passes without any activity from the user, the user is connected to the same server even if the initial connection with the server is broken. During that time, information related to the user is stored in volatile memory of the server. In one embodiment, a one or more searches are performed and the results of the searches are stored on the servers. When a user performs one of the searches the results are retrieved without repeating the searches. Thus, commonly performed searches can be provided in a more efficient manner as compared to performing the searches multiple... |
| Dram chip device well-communicated with flash memory chip and multi-chip package comprising such a device | 20060294295 | 20061228 |
| An SDRAM memory chip device comprises a non-volatile memory controller for operating a non-volatile memory, e.g., a NAND-flash, and a FIFO memory buffer. The FIFO memory buffer serves to operate background store and load operations between a FIFO buffer array and the non-volatile memory, while a host system such as a CPU exchanges data with the SDRAM work memory. The SDRAM memory chip device, therefore, has at least two additional pins as compared with conventional SDRAM standard for generating a set of additional commands. These commands are employed by the FIFO memory buffer to manage the data transfer between the FIFO buffer and each of the non-volatile memory and the volatile SDRAM memory. Two further pins reflecting the flash memory status provide appropriate issuance of load... |
| System and method for managing memory in a mobile device | 20060294304 | 20061228 |
| A system and method for managing memory in a mobile device to prevent the swapping out of sensitive data to non-volatile storage from a volatile memory, to provide enhanced security for the sensitive data. In one broad aspect, there is provided a method of managing memory in a mobile device comprising the steps of identifying one or more data objects stored in a volatile memory on the mobile device to be swapped out to a non-volatile storage component, determining objects marked as containing sensitive data, and retaining so-marked objects in the volatile memory of the mobile device.
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| Method to have fault resilient booting | 20060294353 | 20061228 |
| A method and apparatus is described herein for fault resilient booting of a platform. Upon booting the platform, any boot routines marked are skipped. A current boot routine to be executed in a boot sequence is registered in nonvolatile memory. An attempt to execute the current boot routine is made. If the attempt is successful, the next boot entry is determined and skipped or executed, based on whether it is marked. However, if the execution fails the current boot routine is marked and, upon subsequent execution of the boot sequence, skipped.
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| Security system for electronic device | 20060294364 | 20061228 |
| An antitheft system is provided for an electronic apparatus including a television receiver and a DVD recorder connected via an apparatus control line. The DVD recorder includes a non-volatile memory for previously storing a password. The television receiver includes a non-volatile memory for previously storing the password and a controller. The controller requests the DVD recorder to transmit the password stored in the non-volatile memory when the television receiver is activated or started up, and receives the password from the DVD recorder. The controller further compares the received password with the password stored in the non-volatile memory, and starts an operation of the television receiver when the passwords coincide with each other.
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| System and method of using a protected non-volatile memory | 20060294397 | 20061228 |
| The disclosure includes a system and method of using a processor and protected memory. In a particular embodiment, the system includes a processor, a volatile memory accessible to the processor, and a first nonvolatile memory accessible to the processor. The first nonvolatile memory includes a first portion of memory that is protected and is readable when a shield bit indicates an unshielded mode of operation, but is unreadable when the shield bit indicates a shielded mode of operation and a second portion of memory that is unprotected and that is readable regardless of the value of the shield bit. The system includes a second nonvolatile memory including data to be transferred to the volatile memory.
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| Data processing device, consumable information notification method, storage medium for storing computer-readable program, and program | 20060283933 | 20061221 |
| As useful information on a consumable component used in an image forming apparatus, a user of the image forming apparatus is notified at an appropriate timing that this moment is in a production discontinuation period of a consumable agent. Service information including a support period for a consumable component consumed along with image formation of a printer is stored in a nonvolatile memory. A CPU determines whether or not a toner low notification timing that is status information on the consumable component from the printer is in a consumable goods discontinuation timing that is set as a particular period of the support period. A content of consumable component information that an output device should be notified of is configured to be changed on the basis of... |
| Structure of a non-volatile memory device and operation method | 20060284234 | 20061221 |
| A nonvolatile memory device, including composite gate structures formed on a substrate in series along a bit line (BL) direction. Each of the composite gate structures has a first storage gate, a second storage gate, and a selection gate between the two storage gates. Each of the composite gate structures is respectively coupled to two world line (WL) connection terminals at the two storage gates and a selection terminal at the selection gate. Each of the storage gates corresponds to a memory bit cell. Multiple doped regions are in the substrate between the composite gate structures. A first selection doped region are formed in the substrate and coupled between a BL connection terminal and a first edge one of the composite gate structure. A second selection... |
| Back-side trapped non-volatile memory device | 20060284236 | 20061221 |
| Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of the present invention allow for direct tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention and reduces the possibility of damage to the channel/insulator interface. The direct tunneling program and efficient erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory device embodiments of the present invention are presented that are arranged in NOR or NAND memory architecture arrays. Memory cell embodiments of the present invention also allow... |
| Non-volatile two-transistor programmable logic cell and array layout | 20060284238 | 20061221 |
| A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
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| Structure of a non-volatile memory device and operation method | 20060284240 | 20061221 |
| A nonvolatile memory device includes composite gate structures formed on a substrate in series along a bit line direction. The composite gate structure has a first storage gate structure, a second storage gate structure, and a selection gate between the two storage gate structures. Each of the composite gate structures is respectively coupled to two world line connection terminals at the two storage gate structures and a selection terminal at the selection gate. Each of the storage gate structures corresponds to a memory bit cell. Multiple doped regions are in the substrate between the composite gate structures. A first selection doped region are formed in the substrate and coupled between a BL connection terminal and a first edge one of the composite gate structure. A second... |
| Nanocrystal non-volatile memory device and method of fabricating the same | 20060284241 | 20061221 |
| Non-volatile memory cells (e.g., EEPROM cells) utilize floating gate electrodes that are each defined by a plurality of spaced-apart semiconductor nanocrystals. Each of the memory cells includes a semiconductor substrate having a tunnel dielectric layer thereon. A plurality of semiconductor nanocrystals are provided on the tunnel dielectric layer. These plurality of semiconductor nanocrystals operate collectively as a floating gate electrode. Each of the semiconductor nanocrystals is encapsulated in a respective fluorinated dielectric layer. A control dielectric layer is provided on the plurality of semiconductor nanocrystals and an electrically conductive control electrode is provided on the control dielectric layer.
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| Non-volatile memory device having floating gate and methods forming the same | 20060284242 | 20061221 |
| A non-volatile memory device includes a device isolation layer disposed on a semiconductor substrate to define an active region, a floating gate disposed on the active region including a flat portion and a wall portion extending upwardly from an edge of the flat portion, a tunnel insulator interposed between the floating gate and the active region and a control gate electrode crossing over the active region and covering an inner side of the floating gate and at least a part of an outer side of the floating gate. The non-volatile memory device further includes a blocking insulator interposed between the control gate electrode and the floating gate.
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