|| List of recent Volatile Memory-related patents
| Virtual machine for processing medical data|
The present invention relates to a virtual machine (vm) for processing digital data, in particular medical data, by executing a digital data processing application program, in particular a medical data processing application program (medpap), the virtual machine (vm) being a simulation of a computer, a) the virtual machine (vm) comprising a volatile memory (vimstor) configured to comprise a storage space for temporary data (temp) for temporarily storing the digital data; b) the virtual machine (vm) being configured to be accessed by any virtual machine user activated on a virtual machine user list, wherein any activated maintenance virtual machine user is denied any permission regarding the storage space for temporary data (temp), wherein denying any permissions is performed by logging into the virtual machine (vm) as an administrator and setting corresponding options; c) wherein any administrator has been deactivated on the virtual machine user list, wherein deactivating any administrator has been performed by logging into the virtual machine (vm) as an administrator and setting corresponding options for each administrator in the virtual machine user list; d) wherein the virtual machine (vm) is in a state in which the administrator has been logged off after deactivating the administrator on the virtual machine user list.. .
| System and method for fuse enablement of a secure client hosted virtualization in an information handling system|
A client hosted virtualization system includes a processor to execute code, a non-volatile memory, and a switch. The memory includes code to implement a basic input/output system (bios) for the chvs, and code to implement a virtualization manager.
| Nonvolatile memory device and related read method using hard and soft decision decoding|
A storage device comprises a nonvolatile memory device comprising a plurality of memory cells, and an error correction circuit configured to receive primary data and secondary data from the nonvolatile memory device and to perform a hard decision decoding operation on the primary data and further configured to perform a soft decision decoding operation on the primary data based on the secondary data. The primary data is read from the plurality of memory cells in a hard decision read operation and the secondary data is read from memory cells programmed to a specific state from among the primary data..
| Storage device including non-volatile memory device and repair method|
Disclosed is a storage device which includes a nonvolatile memory device including a memory block a program order of which is adjusted regardless of an arrangement of memory cells, and a memory controller that performs address mapping to replace a bad page of the memory block with a normal page of the memory block.. .
| Semiconductor device and driving method thereof|
A data saving period control circuit; a power gating control circuit; and a data processing circuit including a general-purpose register, an error correction code storage register, and an error correction code circuit are included. The general-purpose register and the error correction code storage register each include a volatile memory unit and a nonvolatile memory unit.
| Tester hardware|
A server stores multiple configuration data. A tester hardware is configured to be capable of changing at least a part of its functions according to configuration data stored in rewritable nonvolatile memory, to supply a power supply voltage to a dut, to transmit a signal to the dut, and to receive a signal from the dut.
| Nonvolatile memory device and error correction methods thereof|
A data processing method is provided for processing data read from a nonvolatile memory. The data processing method includes receiving first bit data from the nonvolatile memory at a memory controller, and performing erasure decoding based on the first bit data and second bit data stored in the memory controller.
| Stress-based techniques for detecting an imminent read failure in a non-volatile memory array|
A technique for detecting an imminent read failure in a non-volatile memory array includes applying a bulk read stress to a plurality of cells of the non-volatile memory array and determining whether the plurality of cells exhibit an uncorrectable error correcting code (ecc) read during an array integrity check at a margin read verify voltage level subsequent to the bulk read stress. The technique also includes providing an indication of an imminent read failure for the plurality of cells when the plurality of cells exhibit the uncorrectable ecc read during the array integrity check.
| Semiconductor device and alarm device|
In the microcomputer in the alarm device, supply of power to a sensor portion or a cpu in a sensor is allowed or stopped by a power gate controlled by a power gate controller. In addition, a volatile memory portion and a nonvolatile memory portion are provided in the cpu, data of the volatile memory portion is stored in the nonvolatile memory portion before supply of power to the cpu is stopped, and the data of the nonvolatile memory portion is restored to the volatile memory portion after the supply of power to the cpu is resumed.
| Reintialization of a processing system from volatile memory upon resuming from a low-power state|
Boot configuration information is stored to a volatile memory of a processing system during a low-power state. When resuming from the low-power state, a processor device accesses configuration information for a memory controller from a non-volatile memory and restores the memory controller using the configuration information so as to permit access to the volatile memory.
| Central processing unit and driving method thereof|
A cache memory provided in the central processing unit is configured to include a data field which stores data in a main memory unit, a tag field which stores management information on data stored in the data field, and a valid bit which stores information about whether the data stored in the data field and the management information stored in the tag field are valid or invalid. Nonvolatile memory cells are used as memory cells which are components of the data field, the tag field, and the valid bit.
| Rapid recovery from loss of storage device cache|
Dirty data in a storage device is made current through rapid re-silvering, which uses a mirrored and up-to-date version of the dirty data from another storage device to recover the data. Because under rapid re-silvering cache metadata in volatile memory survives the failure of the cache, the cache metadata is used to determine which subset of data from the other storage device needs to be copied to the storage device being re-silvered.
| Memory management system and program|
To reduce power consumption of a computer or the like, a nonvolatile memory divided into a plurality of segments is applied to main memory used for virtual storage management. Thus, power supply even to a segment having a physical address that is being used can be stopped.
| Sub-block accessible nonvolatile memory cache|
Subject matter disclosed herein relates to sub-block accessible cache memory.. .
| Electronic control unit|
An electronic control unit (ecu) has a memory area in a non-volatile memory that stores a control program in a rewritable manner for controlling a predetermined control object. The ecu also has an operation unit for performing a process according to the control program stored in the memory and for performing a rewrite process to rewrite contents of the control program stored in the memory area when a predetermined rewrite condition is met.
| Power management architecture based on micro/processor architecture with embedded and external nvm|
A control unit for power supply circuits of points of load (pol) of an electronic system includes a means for autonomous customization by the customer-user of the original control program residing in the rom of the device, as well as configuration of control parameters of the pol. Microprocessor architecture of the device includes a dedicated logic block and a rewritable non-volatile memory coupled to the data bus of the device or to an auxiliary bus thereof, thus providing a means for software extension of the power supply circuits.
| Memory management device and method, and program|
There is provided a memory management device including a non-volatile memory that performs writing and reading of data on a per-page basis, and performs erasing on a per-block basis, and a control unit that manages a data process in the non-volatile memory by performing logical-physical translation on a per-translation unit (tu) basis, and performs a fold process. The control unit sets data of a physical tu corresponding to unnecessary logical tu information to be excluded from a copy target in the fold process based on the unnecessary logical tu information, the unnecessary logical tu information being notified of by a file system and representing a logical tu corresponding to a physical tu in which unnecessary data is physically written..
| Storage device having nonvolatile memory device and write method|
Disclosed is a method of writing data in a storage device including a nonvolatile memory device. The method includes receiving write data with a write request, detecting a number of free blocks, if the detected number of free blocks is less than a threshold value, allocating a log block only in accordance with a sub-block unit, but if the detected number of free blocks is not less than the threshold value, allocating the log block in accordance with one of the sub-block unit and a physical block unit, wherein the sub-block unit is smaller than the physical block unit..
| Usage of a flag bit to suppress data transfer in a mass storage system having non-volatile memory|
Systems and methods are disclosed for usage of a flag bit to suppress data transfer in a mass storage system having non-volatile memory (“nvm”). In some embodiments, a host of the system can issue queue-able trim commands by dispatching non-data transfer write commands to the nvm.
| Computer system having non-volatile memory and method of operating the computer system|
A computer system includes a central processing unit (cpu), a main memory including a non-volatile memory, and a memory reset controller controlling the main memory. If a memory reset command is input from outside, while the computer system is powered on/off, the memory reset controller deletes data stored in the main memory..
| Non-volatile memory device and method for fabricating the same|
A non-volatile memory device includes gate structures including first insulation layers that are alternately stacked with control gate layers over a substrate, wherein the gate structures extend in a first direction, channel lines that each extend over the gate structures in a second direction different from the first direction, a memory layer formed between the gate structures and the channel lines and arranged to trap charges by electrically insulating the gate structures from the channel lines, bit line contacts forming rows that each extend in the first direction and contacting top surfaces of the channel lines, source lines that each extend in the first direction and contact the top surfaces of the channel lines, wherein the source lines alternate with the rows of bit line contacts, and bit lines that are each formed over the bit line contacts and extend in the second direction.. .