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Volatile Memory patents



      
           
This page is updated frequently with new Volatile Memory-related patent applications. Subscribe to the Volatile Memory RSS feed to automatically get the update: related Volatile RSS feeds. RSS updates for this page: Volatile Memory RSS RSS


Apparatus and method for handling a message

Method and apparatus for reading data from non-volatile memory

Nonvolatile memory device and method of operating the same

Date/App# patent app List of recent Volatile Memory-related patents
08/21/14
20140237469
 Firmware metadata and migration in virtualized systems patent thumbnailFirmware metadata and migration in virtualized systems
A system and methods are disclosed for employing firmware metadata and migrating firmware in virtualized environments. In accordance with one example, a hypervisor that is executed by a computer system obtains an address of a firmware program stored in a non-volatile memory of the computer system.
08/21/14
20140237383
 Apparatus and method for handling a message patent thumbnailApparatus and method for handling a message
A system for handling automated messages from a travel supplier includes a messaging client configured to receive an automated message generated by a remote travel supplier. The message comprises a link to a web address for completing a travel action associated with the link.
08/21/14
20140237326
 Method and apparatus for reading data from non-volatile memory patent thumbnailMethod and apparatus for reading data from non-volatile memory
Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array.
08/21/14
20140237319
 Nonvolatile memory device and method of operating the same patent thumbnailNonvolatile memory device and method of operating the same
A nonvolatile memory device includes a nonvolatile memory, a buffer memory configured to store a plurality of read data transmitted from the nonvolatile memory, an error detection and correction circuit configured to detect an error in partial data of each of the plurality of read data and judging whether the partial data is correctable or not on the basis of the detected error, and a controller configured to analyze the uncorrectable partial data with respect to the plurality of read data to determine a representative value, and to transmit the representative value to the error detection and correction circuit. The plurality of read data is read through a read operation with respect to a same page..
08/21/14
20140237318
 Bandwidth optimization in a non-volatile memory system patent thumbnailBandwidth optimization in a non-volatile memory system
A method of bandwidth optimization in a non-volatile memory system includes: retrieving hard data bits; generating soft information from the hard data bits; applying a lossless compression to the soft information for calculating syndrome bits; and executing a low density parity check (ldpc) iterative decode on the hard data bits and the syndrome bits.. .
08/21/14
20140237315
 Method and system for improving data integrity in non-volatile storage patent thumbnailMethod and system for improving data integrity in non-volatile storage
A method for improving data integrity in a non-volatile memory system includes: accessing a non-volatile memory cell for retrieving hard data bits; generating soft information by capturing a reliability of the hard data bits; calculating syndrome bits by applying a lossy compression to the soft information; and generating a host data by executing a low density parity check (ldpc) iterative decode on the hard data bits and the syndrome bits.. .
08/21/14
20140237298
 Methods, systems, and computer readable media for early detection of potential flash failures using an adaptive system level algorithm based on flash program verify patent thumbnailMethods, systems, and computer readable media for early detection of potential flash failures using an adaptive system level algorithm based on flash program verify
Methods, systems, and computer readable media for early detection of potential flash failures using an adaptive system level algorithm based on nand program verify are disclosed. According to one aspect, a method for early detection of potential flash failures using an adaptive system level algorithm based on nand program verify includes performing a program verify operation after a write to a non-volatile memory, where the program verify mechanism reports a pass or fail based on an existing measurement threshold value, and dynamically adjusting the measurement threshold value used by subsequent program verify operations based on the results of previous program verify operations..
08/21/14
20140237286
 Memory system performing address mapping according to bad page map patent thumbnailMemory system performing address mapping according to bad page map
A memory system comprises a nonvolatile memory comprising a memory block having multiple pages, and a controller configured to control the nonvolatile memory to store data in the memory block according to a command and logical address received from an external source. The controller is configured to determine whether the logical address is currently mapped to a bad page of the memory block by referring to a bad page map, and as a consequence of determining that the logical address corresponds to the bad page, remaps the logical address to a different page and stores dummy data in the bad page..
08/21/14
20140237220
 Configuring a trusted platform module patent thumbnailConfiguring a trusted platform module
A method includes storing configuration data for a trusted platform module (tpm) in a pre-boot environment such as unified extensible firmware interface (uefi), reading the configuration data, and automatically configuring the tpm based upon the configuration data. The configuring includes storing values of tpm parameters in non-volatile memory of the tpm.
08/21/14
20140237190
 Memory system and management method therof patent thumbnailMemory system and management method therof
A memory system having multiple memory layers is provided. The memory system includes an upper memory layer and an intermediate memory layer comprising a first sub-memory consisting of a nonvolatile memory and a second sub-memory consisting of a volatile memory in a parallel structure positioned below the upper memory layer, and a memory management unit that controls operations of the upper memory layer and the intermediate memory layer.
08/21/14
20140237172
Imparting durability to a transactional memory system
A transactional memory system uses a volatile memory as primary storage for transactions. Data is selectively stored in a non-volatile memory to impart durability to the transactional memory system to allow the transactional memory system to be restored to a consistent state in the event of data loss to the volatile memory..
08/21/14
20140237169
Hot memory block table in a solid state storage device
Solid state storage devices and methods for populating a hot memory block look-up table (hblt) are disclosed. In one such method, an indication to an accessed page table or memory map of a non-volatile memory block is stored in the hblt.
08/21/14
20140237168
Mass storage controller volatile memory containing metadata related to flash memory storage
A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor.
08/21/14
20140237167
Apparatus and methods for peak power management in memory systems
Disclosed are apparatus and techniques for managing power in a memory system having a controller and nonvolatile memory array. In one embodiment, prior to execution of each command with respect to the memory array, a request for execution of such command is received with respect to the memory array.
08/21/14
20140237166
Higher-level redundancy information computation
Higher-level redundancy information computation enables a solid-state disk (ssd) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. Flash) memory elements during operation of an ssd.
08/21/14
20140237165
Memory controller, method of operating the same and memory system including the same
A memory controller controlling a nonvolatile memory device having a plurality of memory blocks as a data storage space includes an error detection and correction circuit and a reclaim control unit. The error detection and correction circuit receives data from a memory block and calculates a comparison result by comparing a bit error rate of the received data and a predetermined value.
08/21/14
20140237162
Non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer
A system includes a control processor, a non-volatile memory device interface, and a micro-sequencer. The control processor may be configured to receive commands and send responses via a command interface.
08/21/14
20140236911
Low level object version tracking using non-volatile memory write generations
A method for retrieving versioned data in a non-volatile memory is provided. The method includes: (1) receiving a read request for a data object, (2) in response to the request, determining, via an object table, whether one or more versions of the data object exist in memory, (3) in accordance with a determination that one or more versions exist in memory, obtaining, via the object table, a respective location where each of the one or more versions of the data object are stored, and (4) reading at least one of the one or more versions of the data object from the respective location into volatile memory..
08/21/14
20140235029
Bipolar multistate nonvolatile memory
Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states.
08/21/14
20140233621
Gsm/edge transmit power calibration and characterized digital predistortion calibration using multi-band multi-channel multi-chain sweep
A method and apparatus for characterized pre-distortion calibration is provided. The method begins with the selection of a number of devices to be characterized.
08/21/14
20140233339
Apparatus and method to reduce bit line disturbs
A non-volatile memory device comprising a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line; and at least an address decoder to provide a negative voltage to at least one non-accessed word line in said array when a programming or erasure voltage is provided along a shared bit line.. .
08/21/14
20140233337
Nonvolatile memory device and memory system including the same
A nonvolatile memory device includes a memory cell array; and a high voltage generator arranged to generate a high voltage to be supplied to the memory cell array. The high voltage generator includes a pump unit block having a plurality of pump units supplied with an external voltage and at least one of the pumps is engaged in pumping the external voltage to a higher, output, voltage, at a steady clock rate.
08/21/14
20140233329
Compensation scheme for non-volatile memory
Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell.
08/21/14
20140233327
Compensation scheme for non-volatile memory
Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell.
08/21/14
20140233326
Low-voltage current sense amplifer
In one embodiment, an integrated programmable device has a plurality of current sense amplifiers for reading data from non-volatile memory and a reference generator that provides common bias reference voltages to the sense amplifiers. The sense amplifiers can read data from the non-volatile memory at low power supply voltage levels (e.g., 750 mv) relative to the nominal supply level (e.g., 1.2v).
08/21/14
20140233319
Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate
A one-time programmable (otp) memory cell includes a dual date transistor and, in some embodiments, two transistors. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device.
08/21/14
20140233316
Memory system and programming method thereof
A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be the pre-pulse mode, applying a pre-pulse having a predetermined level to a string selection line connected with a gate of a string selection transistor of at least one unselected vertical string of the plurality of vertical strings for a particular time period; and performing a verification operation on the programmed memory cell.. .
08/21/14
20140233301
Resistive switching for non volatile memory device using an integrated breakdown element
A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device.
08/21/14
20140231953
Nand flash memory device
A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.. .
08/21/14
20140231900
Non-volatile memory
A non-volatile memory is provided. The non-volatile memory includes a oxide and polysilicon stack structure and charge storage layers.
08/21/14
20140231888
Magneto-electric voltage controlled spin transistors
The invention relates to a magneto-electric spin-fet including a gate film of chromia and a thin film of a conductive channel material which may be graphene, inp, gaas, gasb, pbs, mos2, ws2, mose2, wse2 and mixtures thereof. The chromia, or other magneto-electric, and conduction channel material are in intimate contact along an interface there between.
08/14/14
20140229774
Apparatus and method for determining an operating condition of a memory cell based on cycle information
A method populates a parameter set for dynamically adjusting an operating condition in a memory block of a non-volatile memory circuit. A desired condition limit is identified, and a first parameter is computed as a function of a first memory operation to be performed on the memory block.
08/14/14
20140229699
Out-of-order command execution in non-volatile memory
An apparatus includes a memory and storage circuitry. The storage circuitry is configured to receive at least one request causing execution of a sequence of memory commands in the memory, to identify that, although a first memory command appears in the sequence before a second memory command, the execution of the second memory command would improve a performance of the execution of the first memory command, and to execute the second memory command and then to execute the first memory command with the improved execution performance..
08/14/14
20140229663
Selectively programming data in multi-level cell memory
Devices, systems, methods, and other embodiments associated with accessing memory are described. In one embodiment, a method detects that a power quality associated with a volatile memory in a computing device meets a threshold value and in response thereto, reprogramming data from the volatile memory to a flash memory comprising multi-level cells.
08/14/14
20140229659
Thin translation for system access of non volatile semicondcutor storage as random access memory
A semiconductor chip is described having a controller having a point-to-point link interface and non volatile memory interfacing circuitry. The point-to-point link interface is to receive a command from a system that identifies a particular non volatile memory.
08/14/14
20140229654
Garbage collection with demotion of valid data to a lower memory tier
Method and apparatus for managing data in a memory. In accordance with some embodiments, a first tier of a multi-tier memory structure is arranged into a plurality of garbage collection units (gcus).
08/14/14
20140229615
Method of collecting information about test devices in a network
A method of collecting information about a plurality of test devices connected in a network is provided. The method includes: identifying routable network addresses within a plurality of the network addresses, and sending discovery packets to the plurality of routable network addresses, receiving responses from the test devices, obtaining the information about the test devices, and storing the information so as to associate, for each of the test devices, the test-device information with at least one of the routable network addresses.
08/14/14
20140229131
Retention-drift-history-based non-volatile memory read threshold optimization
An ssd controller dynamically adjusts read thresholds in an nvm to reduce errors due to device threshold voltage distribution shifts, thus improving performance, reliability, and/or cost of a storage sub-system, such as an ssd. A retention drift clock uses one or more reference pages (or ecc units or blocks) on one or more nvm die as read threshold over time/temperature references, and uses a function of those values as a measure of drift (over time/temperature).
08/14/14
20140227843
Method of manufacturing a semiconductor device
A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of misfet are formed in the peripheral circuit region.
08/14/14
20140227840
3d non-volatile memory device and method for fabricating the same
A non-volatile memory device having a string of a plurality of memory cells that are serially coupled, wherein the string of memory cells includes a plurality of second channels of a pillar type, a first channel coupling lower end portions of the plurality of the second channels with each other, and a plurality of control gate electrodes surrounding the plurality of the second channels.. .
08/14/14
20140227839
Method of manufacturing semiconductor device
Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a misfet is formed.
08/14/14
20140226426
Protection for system configuration information
Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (nvm), test cells associated with the nvm are read first.
08/14/14
20140226424
Memory device and corresponding reading method
An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with a respective main bit line.
08/14/14
20140226416
Erase operation with controlled select gate voltage for 3d non-volatile memory
An erase process for a 3d stacked memory device controls a drain-side select gate (sgd) and a source-side select gate (sgs) of a nand string. In one approach, sgd and sgs are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line.
08/14/14
20140226415
Non-volatile memory including bit line switch transistors formed in a triple-well
Non-volatile memory and methods of operating non-volatile memory reduce breakdown and leakage associated with bit line (bl) switch transistors. The bl switch transistors for a memory array are formed in a well that is electrically isolated from a well associated with the memory array.
08/14/14
20140226414
Group word line erase and erase-verify methods for 3d non-volatile memory
An erase operation for a 3d stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution.
08/14/14
20140226412
Data writing method, and memory control circuit unit and memory storage apparatus using the same
A data writing method for writing data into a memory cell of a rewritable non-volatile memory module, and a memory control circuit unit and a memory storage apparatus using the same area provided. The method includes recording a wear degree of the memory cell and detecting an operating temperature of the memory storage apparatus.
08/14/14
20140226409
Mixed voltage non-volatile memory integrated circuit with power saving
An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage and is generated by a voltage regulator that receives the first voltage.
08/14/14
20140226408
Nonvolatile memory device
According to one embodiment, a nonvolatile memory device includes a core unit and a peripheral circuit unit. The core unit is configured to be capable of storing data.
08/14/14
20140226406
Efficient smart verify method for programming 3d non-volatile memory
In a programming operation of a 3d stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined.
08/14/14
20140226403
Memory system and method of driving memory system using zone voltages
A method is provided for driving a nonvolatile memory device, including multiple strings, where each string is formed by penetrating plate-shaped word lines stacked on a substrate. The method includes configuring the word lines of a string in multiple zones based on zone configuration information, and applying zone voltages to the zones, respectively.
08/14/14
20140226400
Semiconductor device
According to one embodiment, a semiconductor device includes a nonvolatile memory, a volatile memory, and a controller. The controller is configured to transition a part of the volatile memory to a self-refresh mode when a request for stopping supplying of power to the nonvolatile memory is received..
08/14/14
20140226398
Systems and methods to update reference voltages of non-volatile memory
A data storage device includes non-volatile memory and a controller. The controller is configured to read first data from the non-volatile memory.
08/14/14
20140226397
Nonvolatile memory device and control method thereof
A vertical nonvolatile memory device which includes a plurality of cell strings formed in a direction intersecting with a substrate is provided. The vertical nonvolatile memory device is configured to apply a non-selection read voltage to at least one selection line connected to a cell string from among the plurality of cell strings.
08/14/14
20140226394
Integrated circuit, method for driving the same, and semiconductor device
An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided.
08/14/14
20140226390
Non-volatile memory system with reset control mechanism and method of operation thereof
A method of operation of a non-volatile memory system includes: providing a control field effect transistor having a source electrode and a body-tie electrode; coupling a resistive storage element to the source electrode; and opening a well switch coupled to the body-tie electrode for increasing a well voltage and resetting the resistive storage element by the source electrode floating on the well voltage.. .
08/14/14
20140226236
Linear recording device for executing optimum writing upon receipt of series of commands including mixed read and write commands and method and program thereof
A tape drive is provided, which executes an optimum writing method even when overwrite is intervened between mixed read and write operations. When an overwrite command is received while executing the mixed operations, which writes to a predetermined tape position, when a tape position to overwrite on is encountered before the append-written data ending position of the tape (tape eod), the overwritten tape position is regarded as the append-written data ending position of the tape (tape eod) to update the tape eod by the overwritten tape position.


Popular terms: [SEARCH]

Volatile Memory topics: Volatile Memory, Memory Cell, Nonvolatile Memory, Memory Cells, Memory Device, Semiconductor, Semiconductor Memory, Storage Device, Power Management, Display Panel, Logical Address, Redundancy, Distributed, Interleave, Common Source

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This listing is a sample listing of patent applications related to Volatile Memory for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Volatile Memory with additional patents listed. Browse our RSS directory or Search for other possible listings.
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