|| List of recent Transistors-related patents
| Method of fabricating fin fet and method of fabricating device|
In fin fet fabrication, side walls of a semiconductor fin formed on a substrate have certain roughness. Using such fins having roughness may induce variations in characteristics between transistors due to their shapes or the like.
| Method for operating a uwb device|
The method for operating a uwb device having at least one transmitting antenna and/or at least one receiving antenna comprises the following steps: controlling the transmitting antenna (12) or the receiving antenna (12′) with a control pulse signal (13,13′) having a sequence of substantially sinusoidal pulses of alternating polarity and differing amplitudes and particularly having the waveform of a fifth-order gaussian pulse signal, wherein the transmitting antenna (12) can be alternately supplied with current pulses of differing polarity and differing magnitude by switching on and off first electronic switch units (16) that are coupled to the transmitting antenna (12) and have resistances associated with the amplitudes of the pulses to be generated, wherein each first switch unit (16) has a specifiable, particularly equal, number of first switching transistors (18,19), each having substantially identical on-state resistance values (r), wherein the resistance of a first switch unit is adjusted either by using only one of the first switching transistors (18,19) or by using a plurality of first switching transistors (18,19) connected in parallel, and wherein the first switch units (16) are controlled sequentially according to a specifiable temporal schema and each for a control time interval of a predetermined length.. .
| Reference current distribution|
Example reference current distribution circuitry described herein include current mirrors having resistive elements of varying sizes between gate nodes of sense amplifier transistors along a voltage, distribution line. Examples of counter coupling capacitances which may be coupled to the gate nodes of sense amplifier transistors are also described..
| Line voltage boost system and method for non-volatile memory devices and memory devices and processor-based system using same|
The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array..
| Semiconductor memory device|
A semiconductor memory device includes: a plurality of word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements each having a first terminal connected to either one of the first and third bit lines; a plurality of active areas extending in a direction oblique to the first direction while intersecting with the first to third bit lines; a plurality of select transistors provided on the active areas and each having a gate connected to a corresponding one of the word lines, and a current path whose one end is connected to a second terminal of a corresponding one of the variable resistance elements; and a plurality of contact plugs each connecting the other end of the current path of a corresponding one of the select transistors to the second bit line, wherein each of the active areas includes two select transistors sharing a diffusion region, the variable resistance elements includes a first variable resistance element group and a second variable resistance element group, the first variable resistance element group including variable resistance elements aligned in the second direction below the first bit line, and each disposed between adjacent two of the word lines, the second variable resistance element group including variable resistance elements aligned in the second direction below the third bit line, and each disposed between adjacent two of the word lines, and the contact plugs are aligned in the second direction below the second bit line, and are each disposed between adjacent two of the word lines.. .
| Resistive memory device|
A resistive memory device includes memory cell array blocks, a reference cell array block, two first and second sink transistors, and a word line. Each of the memory cell array blocks includes a row line, and the reference cell array block includes a reference row line.
| Current balance control for non-interleaved parallel bridge circuits in power converter|
Systems and methods for reducing current imbalance between parallel bridge circuits used in a power converter of a power generation system, such as a wind driven doubly fed induction generator (dfig) system, are provided. The power converter can include a plurality of bridge circuits coupled in parallel to increase the output power capability of the system.
| Solid-state imaging device and electronic apparatus|
A solid-state imaging device includes a pixel region in which shared pixels which share pixel transistors in a plurality of photoelectric conversion portions are two-dimensionally arranged. The shared pixel transistors are divisionally arranged in a column direction of the shared pixels, the pixel transistors shared between neighboring shared pixels are arranged so as to be horizontally reversed or/and vertically crossed, and connection wirings connected to a floating diffusion portion, a source of a reset transistor and a gate of an amplification transistor in the shared pixels are arranged along the column direction..
| Display device with power source supply scan circuits conducting negative feedback and driving method thereof|
A display device includes a pixel array unit having pixels disposed in a matrix shape, each pixel including an electro-optical element, a write transistor for sampling and writing an input signal voltage, a holding capacitor for holding a signal voltage written by the write transistor, and a driver transistor for driving the electro-optical element in response to the signal voltage held in the holding capacitor. The display device further includes a scan circuit for selectively scanning each pixel in the pixel array unit at a row unit basis, and a plurality of power source supply scan circuits for selectively supplying a first potential and a second potential lower than the first potential to power supply line wired per each pixel row of the pixel array unit to supply current to the driver transistors, synchronously with scanning by the scan circuit..
| Ultra-low voltage-controlled oscillator with trifilar coupling|
The present disclosure relates to a device and method to reduce voltage headroom within a voltage-controlled oscillator by utilizing trifilar coupling or transformer feedback with a capacitive coupling technique. In some embodiments of trifilar coupling, a vco comprises cross-coupled single-ended oscillators, wherein the voltage of first gate within a first single-ended oscillator is separated from the voltage of a second drain within a second single-ended oscillator within the cross-coupled pair.
| High-gain low-noise preamplifier and associated amplification and common-mode control method|
A preamplifier includes a differential pair of transistors receiving a bias current having a differential input and a differential output, a first resistor coupled to a first differential output node, a first transistor having a current path coupled between the first resistor and a power supply, a second resistor coupled to the first differential output node, a second transistor having a current path coupled between the second resistor and the power supply, a third resistor coupled to a second differential output node, a third transistor having a current path coupled between the third resistor and the power supply, a fourth resistor coupled to the second differential output node, and a fourth transistor having a current path coupled between the fourth resistor and the power supply, wherein a source of the second and third transistors are coupled together.. .
| Power amplifiers with push-pull transistors, capacitive coupling for harmonic cancellation, and inductive coupling to provide differential output signals|
A differential power amplifier including a push-pull pair of transistors, a capacitance, a first inductance, and a second inductance. The push-pull pair of transistors includes first and second transistors.
| Output buffers|
An output buffer is provided. The output buffer is coupled to a first voltage source providing a first supply voltage and used for generating an output signal at an output terminal according to an input signal.
| Semiconductor device|
Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor.
| Thin film transistor substrate, method of inspecting the same, and display device including the same|
A thin film transistor substrate, includes: pixels disposed in a display area of the thin film transistor substrate and connected to gate lines and data lines; gate pad parts connected to first ends of the gate lines; first test transistors each being connected to a second end of a corresponding gate line of the gate lines; data pad parts connected to first ends of the data lines; and second test transistors each being connected to a second end of a corresponding data line of the data lines. The gate pad parts, the data pad parts, the first test transistors, and the second test transistors are disposed in a non-display area of the thin film transistor substrate.
| Functionalized zno or zno alloy films exhibiting high electron mobility|
Functionalized films are provided comprising a film of zno or zno alloy disposed over a supporting substrate and a layer of organic molecules comprising terminal carboxylic acid linkage groups, wherein the organic molecules are bound to a surface of the film of zno or zno alloy via the terminal carboxylic acid linkage groups. Thin film transistors comprising the functionalized films are also provided.
| Buck boost charging for batteries|
Disclosed is a battery charging circuit having several operating modes include boost and buck mode, and forward and reverse mode. A power train and a current sensing block may share power transistors thus reducing the number of space-consuming power devices in the circuit.
| Through silicon via device having low stress, thin film gaps and methods for forming the same|
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a tsv device having a “buffer zone” or gap layer between the tsv and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices.
| Half-bridge package with a conductive clip|
According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver ic. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver ic.
| Semiconductor devices|
Semiconductor devices include a first gate pattern provided on the first active region, a second gate pattern over the first active region, a third gate pattern over the second active region, and a fourth gate pattern over the second active region. The second gate pattern is parallel to the first gate pattern in a first direction.
| N/p boundary effect reduction for metal gate transistors|
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate.
| Fin field-effect transistors and fabrication method thereof|
A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate, and forming a plurality of fins with hard mask layers and an isolation structure.
| Semiconductor devices and methods of manufacture thereof|
Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (cmos) device includes a pmos transistor having at least two first gate electrodes comprising a first parameter, and an nmos transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter.
| Solid state imaging device and imaging apparatus|
A solid-state imaging device has, in a semiconductor substrate, plural pds arranged two-dimensionally and signal reading circuits which are formed as mos transistors and read out signals corresponding to charges generated in the respective pds. Microlenses for focusing light beams are formed over the respective pds.
| Strained silicon carbide channel for electron mobility of nmos|
A semiconductor is formed on a (110) silicon (si) substrate, with improved electron mobility. Embodiments include semiconductor devices having a silicon carbide (sic) portion in the nfet channel region.
| Gallium nitride devices|
Semiconductor structures comprising a iii-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance.
| High electron mobility transistors|
The present disclosure relates to a donor layer of bi-layer algan and associated method of fabrication within a high electron mobility transistor (hemt) configured to provide low-resistance ohmic source and drain contacts to reduce power consumption, while maintaining a high-mobility of a two-dimensional electron gas (2deg) within a channel of the hemt. The donor layer of bi-layer algan comprises a mobility-enhancing layer of alzga(1-z)n, a resistance-reducing layer of alxga(1-x)n disposed over the mobility-enhancing layer, wherein the ohmic source and drain contacts connect to the hemt.
| Quasi-surface emission vertical-type organic light-emitting transistors and method of manufacturing the same|
An organic light-emitting transistor may include a mesh-type source electrode having a plurality of apertures in an array pattern. The mesh-type source electrode may be located between the gate electrode and the drain electrode.
| Active matrix organic light emitting diode display having variable optical path length for microcavity|
An organic light emitting diode display includes an array of pixels on a substrate. Each pixel includes three sub-pixels that emits light of different wavelengths from each other.
| Three-dimensional quantum well transistor and fabrication method|
Three dimensional quantum well transistors and fabrication methods are provided. A quantum well layer, a barrier layer, and a gate structure can be sequentially formed on an insulating surface of a fin part.
|Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation|
Processes for making field effect transistors relax a buried stressor layer to induce strain in a silicon surface layer above the buried stressor layer. The buried stressor layer is relaxed and the surface layer is strained by implantation into at least the buried stressor layer, preferably on both sides of a portion of the surface layer that is to be stressed.
|Semiconductor device and manufacturing method thereof|
An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current.
|Thin film transistors formed by organic semiconductors using a hybrid patterning regime|
The present disclosure describes a process strategy for forming bottom gate/bottom contact organic tfts in cmos technology by using a hybrid deposition/patterning regime. To this end, gate electrodes, gate dielectric materials and drain and source electrodes are formed on the basis of lithography processes, while the organic semiconductor materials are provided as the last layers by using a spatially selective printing process..
|Method and apparatus for program and erase of select gate transistors|
Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells.
|String selection structure of three-dimensional semiconductor device|
A three-dimensional semiconductor device includes first and second selection lines stacked one on the other. An upper line horizontally crosses over the first and second selection lines.
|Selecting memory cells|
A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section.
An apparatus is provided. A differential pair of transistors is configured to receive a first differential signal having a first frequency, and a transformer, having a primary side and a secondary side is provided.
Exemplary embodiments are directed to systems, devices, and methods for enhancing a telescopic amplifier. An amplifier may include a differential pair of input transistors including at least one transistor configured to receive a first input and at least one other transistor configured to receive a second input.
|Amplifier with switchable common gate gain buffer|
An amplifier having a switchable common gate gain buffer is disclosed. In an exemplary embodiment, an apparatus includes a plurality of selectable gain channels that provide constant input impedance at a common input to receive an input signal and generate an output signal having at least one of selected gain and current characteristics.
|Switching device with resistive divider|
Embodiments provide a switching device including one or more field-effect transistors (fets). In embodiments, a resistive divider comprising a first resistor and a second resistor may be coupled with the fet at a position electrically between a gate terminal of the fet and a body terminal of the fet..
An object of one embodiment of the present invention to provide a latch circuit includes a level shifter and a buffer in which transistors each including a channel region formed in an oxide semiconductor film are connected in series. Thus, data can be held in the latch circuit even when power is not supplied..
A signal transmission system (10) includes a signal generator circuit (12); a signal regenerator circuit (14) coupled to the signal generator circuit by conductive lines (16, 18). The signal regenerator circuit receives input signals from the signal generator circuit on the conductive lines, and the regenerator circuit includes cascoded transistors (39, 41) and level-shifting circuits (26) coupled to the cascoded transistors.
|Current driver for led diodes|
A current driver for a string of leds includes a first series connection of a first transistor and a first resistance and a second series connection of a second transistor and a second resistance. The first and second series connections are coupled in parallel between the string of leds and a voltage reference.
|Enforcement of semiconductor structure regularity for localized transistors and interconnect|
A global placement grating (gpg) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the gpg is positioned to intersect each contact that interfaces with the chip level.
|Defect reduction for formation of epitaxial layer in source and drain regions|
The embodiments of mechanisms for forming source/drain (s/d) regions of field effect transistors (fets) described enable forming an epitaxially grown silicon-containing layer with reduced number of particles on surface of recesses. The described mechanisms also reduce the effect of the residual particles on the epitaxial growth.
|Power mosfets and methods for forming the same|
Power metal-oxide-semiconductor field-effect transistors (mosfets) and methods of forming the same are provided. A power mosfet may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape.
|Metal-programmable integrated circuits|
A metal-programmable integrated circuit may include an array of metal-programmable cells. Each cell may include multi-gate transistor structures in which multiple surfaces of a gate structure serve to control current flow through at least one channel structure.
|Bidirectional semiconductor device for protection against electrostatic discharges|
An integrated circuit is produced on a bulk semiconductor substrate in a given cmos technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate thyristors coupled in parallel and head-to-tail.
|Memories and methods of forming thin-film transistors using hydrogen plasma doping|
Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped polycrystalline silicon.
|Method and layout of an integrated circuit|
An integrated circuit layout includes a p-type active region, an n-type active region, a first metal connection, a second metal connection and a plurality of trunks. The plurality of trunks is formed substantially side-by-side, and in parallel with each other.
|Current generation architecture for an implantable stimulator device having coarse and fine current control|
Disclosed herein are current output architectures for implantable stimulator devices. Current source and sink circuitry is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking an amount of current to or from any one of the electrodes of the device.
|Long-term implantable silicon carbide neural interface device using the electrical field effect|
Field effect devices, such as capacitors and field effect transistors, are used to interact with neurons. Cubic silicon carbide is biocompatible with the neuronal environment and has the chemical and physical resilience required to withstand the body environment and does not produce toxic byproducts.
|Collections of laterally crystallized semiconductor islands for use in thin film transistors|
Collections of laterally crystallized semiconductor islands for use in thin film transistors and systems and methods for making same are described. A display device includes a plurality of thin film transistors (tfts) on a substrate, such that the tfts are spaced apart from each other and each include a channel region that has a crystalline microstructure and a direction along which a channel current flows.
|Organic light emitting display and manufacturing method thereof|
An organic light emitting display resulting in an improved aperture ratio and a manufacturing method thereof. The organic light emitting display that includes a plurality of pixels arranged between first and second substrates, each of said pixels includes a plurality of thin film transistors, an organic light emitting diode, and a capacitor.
|Semiconductor memory device|
According to one embodiment, a semiconductor memory device includes first hookup transistors connected to word lines, a first dummy hookup transistor connected to first dummy word line, and a second dummy hookup transistor connected to second dummy word line. A group of hookup transistors formed by the first hookup transistors, the first dummy hookup transistor, and the second dummy hookup transistor is aligned on either of one row and rows.
|Multi-port magnetic random access memory (mram)|
A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line.
|Dc/dc converter with iii-nitride switches|
A synchronous switch is interposed between the output and ground. The control switch and the synchronous switch comprise depletion-mode iii-nitride transistors.
|Image pickup apparatus, image pickup system and driving method of image pickup apparatus|
An image pickup apparatus of an embodiment includes pixel units each including a photoelectric conversion unit and an amplification transistor that outputs a signal based on an electric carrier generated by the photoelectric conversion unit, a first output line to which signals from first and other pixel units are output, and a second output line to which signals from second and other pixel units are output. A connection unit is arranged to control an electric connection between input nodes of the amplification transistors of the first and second pixel units is arranged.
|Backlight unit and display device having the same|
A backlight unit includes a power converter configured to generate a light source driving voltage in response to a voltage control signal, a plurality of light emitting diode strings, where each of the light emitting diode strings receives the light source driving voltage through a first terminal thereof, a plurality of transistors corresponding to the light emitting diode strings, where each of the transistors includes: a first electrode connected to a second terminal of a corresponding light emitting diode string thereof; a second electrode; and a control electrode, and a controller connected to the control electrode and the second electrode, where the controller outputs a plurality of current control signals to control electrodes of the transistors and generate the voltage control signal, where the controller generates an over-current detection signal when any one of the current control signals has a pulse width greater than a predetermined reference width.. .
A display apparatus has an image display unit having a plurality of arrayed pixel circuits, and an image signal compensation circuit compensating an image signal and outputs the compensated signal to the image display unit. Each of the pixel circuits has a compensating capacitor which compensates the threshold voltage of the driving transistor.
|Pixel, display device comprising the pixel and driving method of the display device|
A display device includes a data driver; a scan driver; a compensation control signal unit configured to reset voltages of data signals transmitted to a plurality of pixels during a previous frame at a current frame, and configured to generate and transmit a first control signal to compensate for threshold voltages of driving transistors of the pixels and a second control signal to control simultaneous light emission of the pixels; a power controller configured to control and supply the voltage levels of a first and second power source voltages; a display unit including the plurality of pixels coupled to corresponding data lines, scan lines, first control lines, second control lines, first voltage lines, and second voltage lines; and a timing controller configured to generate a plurality of data signals by processing external image signals and generate a plurality of driving control signals for controlling driving of the drivers.. .
|Monitoring system for detecting degradation of integrated circuit|
A monitoring system for detecting stress degradation of a semiconductor integrated circuit has an amplifier circuit and degradation test transistors. Multiplexers are provided that have an output coupled to a respective electrode of the degradation test transistor.
A power-supply apparatus according to an aspect includes an inductor, a transistor that supplies, in an on-state, a current to the input side of the inductor, a second transistor that becomes, when the first transistor is in an off-state, an on-state and thereby brings the input side of the inductor to a predetermined potential, a signal generation unit that generates voltage signals corresponding to a current flowing to the inductor, an amplifier that outputs a current according to the voltage signals, a converter that converts the current output from the amplifier into a voltage signal, and a control unit that controls the transistors based on a first feedback signal corresponding to the voltage on the output side of the inductor and the voltage signal, which is used as a second feedback signal.. .
|Transistors, semiconductor constructions, and methods of forming semiconductor constructions|
Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion.
|Stacked power semiconductor device using dual lead frame|
A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame.
|Semiconductor memory device|
A semiconductor memory device has a memory cell array having memory cells, each including first and second conduction type transistors, a peripheral circuit having the first and second conduction type transistors, a first conduction type memory cell array well region within the memory cell array region, a second conduction type memory cell array well region within the first conduction type memory cell array well region, a first conduction type peripheral circuit well region within the peripheral circuit region, a second conduction type peripheral circuit well region within the first conduction type peripheral circuit well region, and a second conduction type isolation region between the first conduction type memory cell array well region and the first conduction type peripheral circuit well region. At least a portion of first conduction type transistors of first conduction type transistors of the peripheral circuit is formed in the second conduction type isolation region..
|Semiconductor memory device|
A semiconductor memory device has a memory cell array with memory cells, each including first and second conduction type transistors, column-side peripheral circuits disposed with the same row-direction interval as the memory cells, a first conduction type well region formed within the memory cell array, a second conduction type well region formed within the first conduction type well region and is disposed separately in the row direction, a second conduction type well contact region disposed extending in the row direction among the memory cells, a first conduction type well contact region disposed extending in the column direction among the memory cells, a column-side peripheral contact region, a first conduction type back gate voltage line connecting to the first conduction type well region; and a second conduction type back gate voltage line connecting to the second conduction type well.. .
|Method of forming finfet of variable channel width|
Embodiments of present invention provide a method of forming a first and a second group of fins on a substrate; covering a top first portion of the first and second groups of fins with a first dielectric material; covering a bottom second portion of the first and second groups of fins with a second dielectric material, the bottom second portion of the first group and the second group of fins having a same height; exposing a middle third portion of the first and second groups of fins to an oxidizing environment to create an oxide section that separates the top first portion from the bottom second portion of the first and second groups of fins; and forming one or more fin-type field-effect-transistors (finfets) using the top first portion of the first and second groups of fins as fins under gates of the one or more finfets.. .
|Mos transistors and fabrication method thereof|
A method is provided for fabricating an mos transistor. The method includes providing a semiconductor substrate, and forming a gate structure having a gate dielectric layer and a gate metal layer on the semiconductor substrate.
|Cmos transistors, fin field-effect transistors and fabrication methods thereof|
A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and configuring a channel region along a first direction.
|Semiconductor devices including back-side integrated circuitry|
Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors.
|Transistor and fabrication method|
Transistors and fabrication methods are provided. A first sidewall can be formed on each sidewall of a gate structure.
|Methods and systems for point of use removal of sacrificial material|
A method of manufacturing a sensor, the method including forming an array of chemically-sensitive field effect transistors (chemfets), depositing a dielectric layer over the chemfets in the array, depositing a protective layer over the dielectric layer, etching the dielectric layer and the protective layer to form cavities corresponding to sensing surfaces of the chemfets, and removing the protective layer. The method further includes, etching the dielectric layer and the protective layer together to form cavities corresponding to sensing surfaces of the chemfets.
|Method of manufacturing a non-volatile memory|
The disclosure relates to a method of manufacturing vertical gate transistors in a semiconductor substrate, comprising implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors; forming, in the substrate, parallel trench isolations and second trenches perpendicular to the trench isolations, reaching the isolation layer, and isolated from the substrate by a first dielectric layer; depositing a first conductive layer on the surface of the substrate and in the second trenches; etching the first conductive layer to form the vertical gates of the transistors, and vertical gate connection pads between the extremity of the vertical gates and an edge of the substrate, while keeping a continuity zone in the first conductive layer between each connection pad and a vertical gate; and implanting doped regions on each side of the second trenches, to form drain regions of the transistors.. .
|Spad sensor circuit with biasing circuit|
A deep spad structure uses the substrate as the anode terminal of its multiplication p-n junction. A bias voltage for the spad (in excess of the spad's breakdown voltage) is coupled to the spad's cathode terminal.