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This page is updated frequently with new Transistors-related patent applications. Subscribe to the Transistors RSS feed to automatically get the update: related Transistors RSS feeds. RSS updates for this page: Transistors RSS RSS


Integrated circuit and semiconductor device including the same

Integrated circuit and semiconductor device including the same

Input/output circuit

Taiwan Semiconductor Manufacturing

Input/output circuit

Input/output circuit

Skyworks Solutions

Semiconductor devices and methods providing non-linear compensation of field-effect transistors


Date/App# patent app List of recent Transistors-related patents
08/27/15
20150244960 
 Mulitple gated pixel per readout patent thumbnailMulitple gated pixel per readout
A system for providing an improved image of daytime and nighttime scene for a viewer within a vehicle is provided herein. The system includes: a pixel array sensor having a fully masked gate-off capability at a single pixel level, wherein the pixel array sensor is provided with an inherent anti-blooming capability at the single pixel level; wherein each pixel is gated by a corresponding transfer gate transistor having high transfer gate efficiency.
Brightway Vision Ltd.


08/27/15
20150244366 
 Integrated circuit and semiconductor device including the same patent thumbnailIntegrated circuit and semiconductor device including the same
An integrated circuit (ic) includes at least one unit cell. The at least one unit cell includes a first bit circuit configured to process a first bit signal, a second bit circuit configured to process a second bit signal, a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage, and a second well biased to a second voltage that is different from the first voltage.

08/27/15
20150244360 
 Input/output circuit patent thumbnailInput/output circuit
A circuit includes a first power node configured to carry a voltage k·vdd, a second power node configured to carry a zero reference level, an output node, k p-type transistors serially coupled between the first power node and the output node, and k n-type transistors serially coupled between the second power node and the output node. Gates of the k p-type transistors are configured to receive biasing signals set at one or more voltage levels in a manner that one or more absolute values of source-gate voltages or absolute values of drain-gate voltages are equal to or less than vdd.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/27/15
20150244358 
 Semiconductor devices and methods providing non-linear compensation of field-effect transistors patent thumbnailSemiconductor devices and methods providing non-linear compensation of field-effect transistors
Semiconductor devices and methods are disclosed including switch circuitry providing improved switching performance. A semiconductor die includes a semiconductor substrate, at least one field-effect transistor (fet) formed on the semiconductor substrate, and a compensation circuit connected to a respective source of each of the at least one fet, the compensation circuit configured to compensate a non-linearity effect generated by the at least one fet..
Skyworks Solutions, Inc.


08/27/15
20150244355 
 Low-power offset-stored latch patent thumbnailLow-power offset-stored latch
A low-power offset-stored cmos latch includes, for example, a common current source that is arranged to provide a predetermined bias current for an offset storage phase and enable transistors that are arranged to couple a resolution bias current during a resolution period to a respective input pair device. The low-power offset-stored cmos latch optionally includes current scaling to provide a resolution bias current that is larger than the predetermined bias current of the offset storage phase..
Texas Instruments Incorporated


08/27/15
20150244332 
 Current mirror, control method, and image sensor patent thumbnailCurrent mirror, control method, and image sensor
There is provided a current mirror that includes at least one bias amplifier configured to adjust a gate line voltage by feeding currents to the gate line to make constant gate-source voltages of a plurality of fets (field effect transistors), the gate line connecting gates of the fets each being a load component in the current mirror.. .
Sony Corporation


08/27/15
20150244330 
 Amplifier apparatus and soft-start method thereof patent thumbnailAmplifier apparatus and soft-start method thereof
An amplifier apparatus includes a differential input pair, a current source, and a load. The differential input pair includes first and second transistors, and an auxiliary transistor.
Via Telecom Co., Ltd.


08/27/15
20150244322 
 Bias circuits and methods for stacked devices patent thumbnailBias circuits and methods for stacked devices
Embodiments of the present disclosure include a bias circuit for generating bias voltages to stacked transistors. In one embodiment, stacked transistors are coupled between an input transistor and an output node.
Qualcomm Incorporated


08/27/15
20150243916 
 Organic thin film transistors and methods of making the same patent thumbnailOrganic thin film transistors and methods of making the same
In one aspect, organic thin film transistors are described herein. In some embodiments, an organic thin film transistor comprises a source terminal, a drain terminal and a gate terminal; a dielectric layer positioned between the gate terminal and the source and drain terminals; and a vibrationally-assisted drop-cast organic film comprising small molecule semiconductor in electrical communication with the source terminal and drain terminal, wherein the transistor has a carrier mobility (μeff) of at least about 1 cm2/v·s..
Wake Forest University


08/27/15
20150243914 
 Organic semiconductor formulations patent thumbnailOrganic semiconductor formulations
Embodiments in accordance with the present invention relate generally to formulations for use in organic semiconductor layers of organic electronic devices, and more specifically in organic field effect transistors, to organic semiconductor layers prepared from such formulations, and to organic electronic devices and organic field effect transistors encompassing such organic semiconductor layers.. .
Merck Patent Gmbh


08/27/15
20150243906 

Acenaphthylene imide-derived semiconductors


Novel acenaphthylene imide-derived semiconductor materials, including small molecule compounds, polymers and oligomers. Also provided are methods for making the novel semiconductor materials and the use of the novel semiconducting materials in electronic or optoelectronic device.
University Of Washington Through Its Center For Commercialization


08/27/15
20150243887 

Semiconductor memory device and a manufacturing the same


A semiconductor memory device comprises a memory cell array. The memory cell array comprises a plurality of first wiring lines, a plurality of second wiring lines extending crossing the first wiring lines, and a plurality of memory cells disposed at intersections of the first and second wiring lines.
Kabushiki Kaisha Toshiba


08/27/15
20150243824 

Optical sensor having a light emitter and a photodetector assembly directly mounted to a transparent substrate


An optical sensor is described that includes a light emitter and a photodetector assembly directly attached to a transparent substrate. In one or more implementations, the optical sensor comprises at least one light emitter and a photodetector assembly (e.g., photodiodes, phototransistors, etc.).
Maxim Integrated Products, Inc.


08/27/15
20150243781 

Resurf semiconductor device charge balancing


Breakdown voltage bvdss is enhanced and on-resistance reduced in resurf devices, e.g., ldmos transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a fet whose source-drain couple the isolation wall and drift region and whose gate receives control voltage vc, or a resistor whose cross-section (x, y, z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall..
Freescale Semiconductor, Inc.


08/27/15
20150243777 

Semiconductor device


There is provided a semiconductor device having ldmos transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each ldmos transistor, the trench having a gate electrode partially embedded therein.
Renesas Electronics Corporation


08/27/15
20150243765 

Semiconductor structures with pair(s) of vertical field effect transistors, each pair having a shared source/drain region and methods of forming the structures


Disclosed are semiconductor structures and methods of forming the structures. The structures each comprise a pair of vertical fets.
International Business Machines Corporation


08/27/15
20150243744 

Semiconductor device


A semiconductor device includes a substrate and a plurality of transistors arranged on the substrate in an array. The transistor includes a first electrode, a plurality of second electrodes, and a gate electrode.
Delta Electronics, Inc.


08/27/15
20150243740 

Boron rich nitride cap for total ionizing dose mitigation in soi devices


A semiconductor-on-insulator (soi) structure that includes a cap layer composed of a boron-rich compound or doped boron nitride located between a top semiconductor layer and a buried insulator layer is provided. The cap layer forms a conductive path between the top semiconductor layer and the buried insulator layer in the soi structure to dissipate total ionizing dose (tid) accumulated charges, thus advantageously mitigating tid effects in fully depleted soi transistors..
International Business Machines Corporation


08/27/15
20150243734 

Methods of forming transistors


Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material.
Micron Technology, Inc.


08/27/15
20150243720 

Display backplane having multiple types of thin-film-transistors


There is provided a tft backplane having at least one tft with oxide active layer and at least one tft with poly-silicon active layer. In the embodiments of the present disclosure, at least one of the tfts implementing the circuit of pixels in the active area is an oxide tft (i.e., tft with oxide semiconductor) while at least one of the tfts implementing the driving circuit next to the active area is a ltps tft (i.e., tft with poly-si semiconductor)..
Lg Display Co., Ltd.


08/27/15
20150243719 

Display backplane having multiple types of thin-film-transistors


There is provided a tft backplane having at least one tft with oxide active layer and at least one tft with poly-silicon active layer. In the embodiments of the present disclosure, at least one of the tfts implementing the circuit of pixels in the active area is an oxide tft (i.e., tft with oxide semiconductor) while at least one of the tfts implementing the driving circuit next to the active area is a ltps tft (i.e., tft with poly-si semiconductor)..
Lg Display Co., Ltd.


08/27/15
20150243718 

Display backplane having multiple types of thin-film-transistors


There is provided a tft backplane having at least one tft with oxide active layer and at least one tft with poly-silicon active layer. In the embodiments of the present disclosure, at least one of the tfts implementing the circuit of pixels in the active area is an oxide tft (i.e., tft with oxide semiconductor) while at least one of the tfts implementing the driving circuit next to the active area is a ltps tft (i.e., tft with poly-si semiconductor)..
Lg Display Co., Ltd.


08/27/15
20150243689 

Thin film transistor substrate and display using the same


The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate, and a display using the same. A display includes a first thin film transistor including a poly crystalline semiconductor layer, a first gate electrode on the poly crystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor including a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed on the first gate electrode and the second gate electrode and under the oxide semiconductor layer..
Lg Display Co., Ltd.


08/27/15
20150243686 

Thin film transistor substrate and display using the same


The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate. A thin film transistor substrate includes a substrate; a first thin film transistor disposed on the substrate, the first thin film transistor including a poly crystalline semiconductor layer, a first gate electrode over the poly crystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor disposed on the substrate, the second thin film transistor including a second gate electrode, an oxide semiconductor layer over the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed over the first gate electrode and the second gate electrode and under the oxide semiconductor layer..
Lg Display Co., Ltd.


08/27/15
20150243679 

Display device


A display device in which the current load of wirings are distributed and display variations due to voltage drop are suppressed. An active matrix display device of the invention comprises a first current input terminal, a second current input terminal, and a plurality of current supply lines extending parallel to each other.
Semiconductor Energy Laboratory Co., Ltd.


08/27/15
20150243678 

Semiconductor device and electronic device


To provide a novel shift register. transistors 101 to 104 are provided.
Semiconductor Energy Laboratory Co., Ltd.


08/27/15
20150243668 

Non-volatile memory device


The present invention provides a non-volatile memory device using a memory transistor including an oxide semiconductor, capable of writing with low power consumption, without receiving an influence of deterioration of a selection transistor connected in series to the memory transistor. A memory cell 1 includes a memory transistor qm, and first and second selection transistors q1 and q2.
Sharp Kabushiki Kaisha


08/27/15
20150243664 

Integrated junction and junctionless nanotransistors


Semiconductor devices including a first transistor and a second transistor are integrated on a substrate. Each of the first and second transistors include a nano-sized active region including source and drain regions provided in respective end portions of the nano-sized active region and a channel forming region provided between the source and drain regions.

08/27/15
20150243645 

Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices


Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device..
Infineon Technologies Austria Ag


08/27/15
20150243563 

Integrated circuit having multiple threshold voltages


In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.. .
Globalfoundries Inc.


08/27/15
20150243562 

Semiconductor device and manufacturing method thereof


A semiconductor device is provided which includes an n-type semiconductor layer and a p-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers.
Renesas Electronics Corporation


08/27/15
20150243497 

Back-end transistors with highly doped low-temperature contacts


A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer.
International Business Machines Corporation


08/27/15
20150243367 

Shift register unit circuit, shift register, array substrate and display device


There are provided a shift register unit circuit, a shift register, an array substrate and a display device. The shift register unit circuit comprises: an input module configured to receive an input signal and output the input signal to a pulling-up node; an output module configured to receive the input signal and output a driving signal under a control of a first clock signal; a pulling-down module configured to pull down a potential at the pulling-up node and a signal output terminal under a control of a pulling-down node; a pulling-down control module configured to pull down the pulling-down node under a control of the input signal and pull up the pulling-down node under a control of a second clock signal; and a resetting module configured to reset the potential at the pulling-up node and the signal output terminal under a control of a resetting signal.
Hefei Boe Optoelectronics Technology Co., Ltd. Et Al.


08/27/15
20150243358 

Nonvolatile semiconductor memory device


A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.. .
Kabushiki Kaisha Toshiba


08/27/15
20150243349 

Amplifier


A circuit includes a plurality of first circuits, a selection circuit, and a second circuit. The selection circuit is configured to selectively couple a first circuit of the plurality of first circuits with the second circuit.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/27/15
20150243348 

Nonvolatile memory device


A nonvolatile memory device includes a word line, four or more bit lines, three or more mis transistors having gate nodes thereof connected to the word line, the n-th (n: positive integer) one of the mis transistors having two source/drain nodes thereof connected to the n-th and n+1-th ones of the bit lines, respectively, a sense circuit having two nodes and configured to amplify a difference between potentials of the two nodes, and a switch circuit configured to electrically couple the n-th and n+2-th ones of the bit lines to the two nodes of the sense circuit, respectively, and to electrically couple the n+1-th one of the bit lines to a fixed potential, for any numerical number n selected to detect single-bit data stored in the n-th and n+1-th ones of the mis transistors.. .
Nscore, Inc.


08/27/15
20150243237 

Shift register unit, gate driving circuit and display apparatus


The present disclosure relates to the technical field of display. Provided are a shift register unit, a gate driving circuit and a display apparatus, the shift register unit includes an inputting module, a first outputting module and a second outputting module.
Ordos Yaunsheng Optoelectronics Co., Ltd.


08/27/15
20150241902 

Integrated circuit with transistor array and layout method thereof


An integrated circuit includes a plurality of transistors. The transistors are electrically connected in series and with their respective gates tied together.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/27/15
20150241750 

Liquid crystal display


A liquid crystal includes: a gate line which extends substantially in a first direction, a step-down gate line which extends substantially in the first direction; a data line which extends substantially in a second direction and crosses the gate line; a first thin film transistor connected to the gate line and the data line; a second thin film transistor connected to the gate line and the data line; a third thin film transistor connected to the gate line and the second thin film transistor; a reference voltage line connected to the third thin film transistor; a fourth thin film transistor connected to the step-down gate line, the second thin film transistor and the third thin film transistor; and a pixel electrode including first, second and third subpixel electrodes connected to the first, second and third thin film transistors, respectively.. .
Samsung Display Co., Ltd.


08/27/15
20150241748 

Array substrate for liquid crystal display device and fabricating the same


A liquid crystal display device includes an array substrate and a color filter substrate, a plurality of gate lines and a plurality of data lines formed on the array substrate such that the gate lines and the data lines intersect each other to define a plurality of pixel regions, a plurality of thin film transistors formed at respective intersections of the gate lines and the data lines, a liquid crystal layer interposed between the array and color filter substrates, and a plurality of repair patterns formed on the first substrate. Each of the plurality of the repair patterns crosses a corresponding one of the data lines, and is along and adjacent to a corresponding one of the gate lines, such that the repair pattern includes protruding ends that protrude from the corresponding data line to repair a defect on the pixel regions..
Lg Display Co., Ltd.


08/27/15
20150241723 

Liquid crystal display device


A column for defining the interval between a tft substrate and an opposed substrate is formed at a crossing point between a drain line and a scanning line. At the crossing point where the column is formed, the drain line is formed to have a wider width to prevent light leakage.
Panasonic Liquid Crystal Display Co., Ltd.


08/27/15
20150241484 

Lossless over-current detection circuit for royer oscillators and push-pull converters


A circuit including over-current protection includes a voltage input, first and second switching transistors that are complementarily switched and that receive current from the voltage input, a first resistor, a first diode including a first anode and a first cathode, and a second diode including a second anode and a second cathode. The first anode and the second anode are connected to each other and are connected to the voltage input via the first resistor.
Murata Power Solutions


08/27/15
20150240350 

Array substrate, producing the same and display apparatus


An array substrate comprising display areas and non-display areas is provided. The non-display area comprises an area in which a plurality of gate lines and a plurality of data lines crossed to each other are located and an area in which thin film transistors are located, the gate lines and the data lines being formed by patterning metal film layers which are formed in the area by magnetron sputtering targets spaced to each other; and wherein a pad part is formed in an area of the non-display areas corresponding to the spacing areas between the targets, a sum of thickness of the metal film layer foamed in the areas corresponding to the spacing areas between the targets and the thickness of the pad part being equal to the thickness of the metal film layer formed in the areas facing the targets..
Hefei Xinsheng Optoelectronics Technology Co., Ltd


08/27/15
20150239258 

Optical print head and image forming apparatus


An optical print head performs optical writing onto target, and includes: current-driven light-emitting elements arranged in rows in a predetermined direction; driving transistors that are each electrically series-connected with the light-emitting elements in one-to-one correspondence, and each supply a driving current to a corresponding light-emitting element; a current control unit that controls, for each light-emitting element, a driving current amount in accordance with variation in light-emitting properties of the light-emitting element that indicate relation between the driving current amount and a light amount emitted by the light-emitting element; an application unit that, upon receiving electrical power supplied from an external power source, applies application voltage to circuits each consisting of a light-emitting element and a corresponding driving transistor; and a voltage control unit that suppresses variation in divided voltage applied to each driving transistor by controlling the application unit to apply increased application voltage of the driving current amount increases.. .
Konica Minolta, Inc.


08/20/15
20150237696 

Ac-powered led light engine


Ac led light engines powered directly from the ac power line contain circuitry of resistors, capacitors, diodes and transistors which enables a single string leds connected to series to efficiently produce light with a relatively low level of flicker as perceived by the human eye. The leds are driven by a current which is alternately capacitively-limited and resistively-limited.

08/20/15
20150237285 

Comparator, solid-state imaging device, electronic apparatus, and driving method


A solid-state imaging device that outputs a pixel signal having a signal level corresponding to charges generated by a photoelectric conversion includes a comparator. The comparator has a first amplifying unit with first and second transistors configured as a differential pair and provides a signal output by amplifying a difference of signals input to the gate electrodes of the first and second transistors.
Sony Corporation


08/20/15
20150237276 

Image sensor array with external charge detection circuitry


An image sensor may include an array of pixels that, do not include any source follower, reset, or addressing transistors, which helps to increase pixel well capacity, reduces or eliminates random telegraph signal (rts) noise, and reduces undesirable dark current. Charge to voltage conversion may be performed by charge detection circuitry that is external to the array of pixels.
Semiconductor Components Industries, Llc


08/20/15
20150236698 

Stability-enhanced physically unclonable function circuitry


A physically unclonable function circuit may include precharge circuitry that precharges an output. The precharge circuitry may include transistors of a first type such as n-type or p-type.
Altera Corporation


08/20/15
20150236695 

Multi-threshold flash ncl logic circuitry with flash reset


Multi-threshold flash null convention logic (ncl) includes one or more high threshold voltage transistors within a flash ncl gate to reduce power consumption due to current leakage by transistors of the ncl gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the ncl gate.
Wave Semiconductor, Inc.


08/20/15
20150236692 

Driving signal generating circuit and power semiconductor device driving apparatus including the same


There are provided a driving signal generating circuit and a power semiconductor device driving apparatus including the same. The driving signal generating circuit for generating driving signals provided to first and second transistors driving a power semiconductor device includes: a first driving signal generating unit generating a first driving signal including a high level signal and a low level signal and providing the first driving signal to a gate of the first transistor; a detecting unit detecting a detection voltage depending on a current flowing in the power semiconductor device; a second driving signal generating unit generating a second driving signal in inverse proportion to the detection voltage; and a switching unit performing a switching operation depending on the first driving signal to transfer the second driving signal to a gate of the second transistor..
Samsung Electro-mechanics Co., Ltd.


08/20/15
20150236691 

Switch controls


Switches for use in rf devices are provided that offer a better balance of power losses and switching times than switches of the prior art. Switches of the present invention comprise a stack of transistors controlled a symmetric bias network.
Acco


08/20/15
20150236596 

Dc-dc conversion circuit and method


According to the dc-dc conversion circuit and conversion method, variation of an input voltage is reflected by detecting a voltage at a secondary winding of a transformer, a reference voltage is adjusted by using the detected input voltage signal, a feedback voltage signal is compared with the reference voltage, a duty cycle control signal is adjusted according to a comparison result, and conduction and shutting-down of switching transistors are controlled according to the duty cycle control signal to adjust an output voltage of the dc-dc conversion circuit, so as to enable the output voltage to vary with the input voltage.. .
Huawei Technologies Co., Ltd.


08/20/15
20150236592 

Circuit device and electronic apparatus


Provided is a circuit device in which reduction of power consumption, reduction of the number of parts, and the like can be realized by eliminating the need for a sense resistor. The circuit device includes a bridge circuit, and a control circuit configured to compare a reference voltage vr and a detection voltage v2 (v1) set using the on-current and the on-resistance of at least one of a low-side transistor and a high-side transistor, output a detection result, control switching on and off of transistors in the bridge circuit, and perform switching from a charge period to a decay period..
Seiko Epson Corporation


08/20/15
20150236282 

Hybrid junction field-effect transistor and active matrix structure


Junction field-effect transistors including inorganic channels and organic gate junctions are used in some applications for forming high resolution active matrix displays. Arrays of such junction field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes..
International Business Machines Corporation


08/20/15
20150236145 

Semiconductor structures and methods for multi-level band gap energy of nanowire transistors to improve drive current


A semiconductor device is provided having a channel formed from a nanowire with multi-level band gap energy. The semiconductor device comprises a nanowire structure formed between source and drain regions.
Taiwan Semiconductor Manufacturing Company Limited


08/20/15
20150236141 

Bipolar transistor having collector with grading


This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at least one grading in the collector. One aspect of this disclosure is a bipolar transistor that includes a collector having a high doping concentration at a junction with the base and at least one grading in which doping concentration increases away from the base.
Skyworks Solutions, Inc.


08/20/15
20150236136 

Flash memory cell with floating gate with increased surface area


Provided are stacked gate floating gate transistors and split gate floating gate transistors having floating gates with respective upper surfaces that include upwardly extending pillars which are sharp, densely packed apices in some embodiments, and an increased surface area. The increased surface area enables lower erase voltages to be used and enables smaller device feature sizes, particularly for split gate floating gate transistors.
Wafertech, Llc


08/20/15
20150236122 

High electron mobility transistors having improved reliability


High electron mobility transistors (hemts) having improved i-v characteristics and reliability are provided. According to one embodiment, a selective implantation is performed to form a damage region in a gate-to-drain region of, for example, an iηal−n/gan hemt.
University Of Florida Research Foundation, Incorporated


08/20/15
20150236118 

Fabrication of field-effect transistors with atomic layer doping


Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared.
International Business Machines Corporation


08/20/15
20150236105 

Semiconductor device with vertical transistors having a surrounding gate and a work-function metal around an upper sidewall


A method of manufacturing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer, a first insulating film around the fin-shaped semiconductor layer, and a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A second step forms a gate insulating film around the pillar-shaped semiconductor layer, a gate electrode around the gate insulating film, and a gate line.
Unisantis Electronics Singapore Pte. Ltd.


08/20/15
20150236092 

Semiconductor structures and methods for multi-level work function and multi-valued channel doping of nanowire transistors to improve drive current


A semiconductor device with multi-level work function and multi-valued channel doping is provided. The semiconductor device comprises a nanowire structure and a gate region.
Taiwan Semiconductor Manufacturing Company Limited


08/20/15
20150236090 

Transistor with reducted parasitic


Parasitic thyristor action may be mitigated in semiconductor devices by placement of minority carrier traps, illustratively in the base(s) of bipolar transistors or the well of a cmos transistor pair. The minority carrier traps include adjacent n and p regions which may be connected by a conductor..
Nxp B.v.


08/20/15
20150236083 

Thin film transistor array


A thin film transistor array includes thin film transistors each including a gate electrode formed on an insulation substrate, a source electrode and a drain electrode formed on the gate electrode via a gate insulation film and a semiconductor layer formed on a portion of the gate electrode surrounded by at least the source electrode and the drain electrode; capacitors each including a capacitor electrode formed on the insulation substrate and a pixel electrode which is formed on the capacitor electrode via the gate insulation film and connected to the drain electrode, the capacitors and the thin film transistors being positioned in a matrix along a first direction and a second direction perpendicular to the first direction; and connection lines that connect semiconductor layers of the thin film transistors positioned in the first direction. The connection lines each have a width smaller than a width of the semiconductor layer..
Toppan Printing Co., Ltd.


08/20/15
20150236078 

Hybrid bipolar junction transistor


Bipolar junction transistors including inorganic channels and organic emitter junctions are used in some applications for forming high resolution active matrix displays. Arrays of such bipolar junction transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes..
International Business Machines Corporation


08/20/15
20150236062 

Radiographic imaging array fabrication process for metal oxide thin-film transistors with reduced mask count


Embodiments of radiographic imaging systems; radiography detectors and methods for using the same; and/or fabrication methods therefore can include radiographic imaging array that can include a plurality of pixels that each include a photoelectric conversion element coupled to a thin-film switching element. In certain exemplary embodiments, thin-film switching element is a metal oxide (e.g., a-igzo) tft manufactured using a reduce photolithography mask counts.
Carestream Health, Inc.


08/20/15
20150236056 

Array substrate and fabricating the same, and display device


The present invention discloses an array substrate and a manufacturing method for the same, and a display device. By adopting the manufacturing method for the array substrate provided by the embodiments of the present invention, via holes with relatively small hole sizes in a color resin layer are realized, so that the aperture ratio of pixels is improved.
Boe Technology Group Co., Ltd.


08/20/15
20150236055 

Array substrate and manufacturing the same, and display apparatus


Embodiments of the present invention provide an array substrate and a method of manufacturing the same, and a display apparatus. The array substrate includes: a substrate; thin film transistors, data lines, gate lines disposed on the substrate; an interlayer insulating layer, disposed below the pixel electrodes, and provided with insulating raised strips protruding in a thickness direction of the substrate towards a space between adjacent pixel electrodes, wherein a projection of each raised strip on the substrate is not overlapped with those of pixel electrodes adjacent thereto in the thickness direction.
Boe Technology Group Co., Ltd.


08/20/15
20150236040 

Diode biased body contacted transistor


Approaches for body contacted transistors are provided. A method of manufacturing a semiconductor structure includes forming a field effect transistor (fet) including a channel and a gate.
International Business Machines Corporation


08/20/15
20150236036 

Semiconductor device and methods of manufacturing and operating the same


A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.. .
Sk Hynix Inc.


08/20/15
20150236020 

Cmos transistors including gate spacers of the same thickness


A dielectric material layer is deposited on gate structures of first and second semiconductor material portions. The dielectric material layer is anisotropically etched to form a first gate spacer on a first semiconductor material portion, while being protected above the second semiconductor material portion.
International Business Machines Corporation


08/20/15
20150236019 

Cmos transistors including gate spacers of the same thickness


A dielectric material layer is deposited on gate structures of first and second semiconductor material portions. The dielectric material layer is anisotropically etched to form a first gate spacer on a first semiconductor material portion, while being protected above the second semiconductor material portion.
International Business Machines Corporation


08/20/15
20150236009 

Low voltage npn with low trigger voltage and high snap back voltage for esd protection


An area-efficient, low voltage esd protection device (200) is provided for protecting low voltage pins (229, 230) against esd events by using one or more stacked low voltage npn bipolar junction transistors, each formed in a p-type material with an n+ collector region (216) and p+ base region (218) formed on opposite sides of an n+ emitter region (217) with separate halo extension regions (220-222) formed around at least the collector and emitter regions to improve the second trigger or breakdown current (it2) and set the snapback voltage (vsb) and triggering voltage (vt1) at the desired level.. .
Freescale Semiconductor, Inc.


08/20/15
20150235904 

Integrated circuitry and methods of forming transistors


Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor.
Micron Technology, Inc.


08/20/15
20150235903 

Self-aligned iii-v mosfet fabrication with in-situ iii-v epitaxy and in-situ metal epitaxy and contact formation


A method for forming a transistor includes providing a patterned gate stack disposed on a iii-v substrate and having sidewall spacers formed on sides of the patterned gate stack, the iii-v substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including iii-v semiconductor material, and growing metal contacts on the grown raised source/drain regions.
International Business Machines Corporation


08/20/15
20150234401 

Temperature-compensated reference voltage system with very low power consumption based on an scm structure with transistors of different threshold voltages


A simple scm (self cascode mosfet) structure to generate a sub-1v reference voltage in the scm intermediate node. The structure requires only 2 transistors to create a temperature-compensated reference voltage.
Centro Nacional De Tecnologia Eletronica Avancada S.a.


08/20/15
20150232369 

Laser cutting of display glass compositions


The present invention relates to a laser cutting technology for cutting and separating thin substrates of transparent materials, for example to cutting of display glass compositions mainly used for production of thin film transistors (tft) devices. The described laser process can be used to make straight cuts, for example at a speed of >1 m/sec, to cut sharp radii outer corners (<1 mm), and to create arbitrary curved shapes including forming interior holes and slots.
Corning Incorporated


08/20/15
20150230720 

Flexible active matrix circuits for interfacing with biological tissue


High resolution active matrix nanowire circuits enable a flexible and stretchable platform for probing neural circuits. Fabrication of such circuits includes forming an array of transistors using a semiconductor-on-insulator substrate.
International Business Machines Corporation


08/13/15
20150229320 

Sample hold circuit, a/d converter, calibration the sample hold circuit, and circuit


There is provided a pipelined a/d converter in which plural stages stage 1 to stage n each including an mdac (i.e., multiplying da converter) are connected. The pipelined a/d converter is configured with a gain-amp (12) included in the mdac for the spm, mos transistors (mx1) and (mx2) as a differential pair having output ends connected to a sampling capacitor csi on a subsequent stage, mos transistors (my1) and (my2) as a load unit connected to the differential pair, a current source (i3) configured to supply a current to the mos transistors (mx1) and (mx2) as the differential pair, and current sources (i1) and (i2) configured to adjust the current flown across the mos transistors (my1) and (my2) as the load unit..
Asahi Kasei Microdevices Corporation


08/13/15
20150229308 

Transmitter having voltage driver and current driver


A circuit includes a first power node that carries a first supply voltage having a first voltage level and a second power node that carries a second supply voltage having a second voltage level less than the first voltage level. A voltage driver has a first plurality of transistors, an input node for an input signal, and an output node, and a current driver has a second plurality of transistors.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/13/15
20150229297 

High voltage driver using low voltage transistor


A high voltage driver may include: a low side switching unit including first to n-th n-channel metal oxide semiconductor (nmos) transistors; a high side switching unit including first and second to n-th p-channel mos (pmos) transistors; a voltage dividing unit dividing a voltage between the output terminal and the ground; a first constant voltage unit providing a constant voltage and a unidirectional signal path between a source and a gate of each of the first to n-th nmos transistors; a second constant voltage unit providing a constant voltage and a unidirectional signal path between a source and a gate of each of the first to n-th pmos transistors; a first charging unit providing a charged voltage to each of the gates of the second to n-th nmos transistors; and a second charging unit providing a charged voltage to each of the gates of the second to n-th pmos transistors.. .
Samsung Electro-mechanics Co., Ltd.


08/13/15
20150229293 

High-pass filter circuit and band-pass filter circuit


Two types of high-pass filter circuit and a band-pass filter circuit are provided. Both types of high-pass filter circuit include a capacitor configured to input an input signal, a resistor connected between an output terminal of the capacitor and a prescribed bias voltage, and a signal output circuit connected to the output terminal of the capacitor and configured to buffer-amplify the input signal for output.
Ricoh Company, Ltd.


08/13/15
20150229283 

Broadband amplifier


Parallel capacitors (5c and 5d) of impedance matching circuits (5) which are connected to two transistors (1), respectively, have their first ends connected to a ground through via holes (5e and 5f) that are used in common, respectively. Although a conventional circuit necessitates via holes by the number equal to the number of stages multiplied by the number of cells of the transistors (1) for an lpf type impedance matching circuit (3), the present circuit can halve the number of via holes of the lpf type impedance matching circuit (5), thereby being able to downsize the circuit..
Mitsubishi Electric Corporation


08/13/15
20150229275 

Semiconductor device having an amplifying circuit


A semiconductor device includes a voltage comparing circuit, an amplifying circuit and a control circuit. The voltage comparing circuit includes first and second transistors that are coupled in a differential manner to compare first and second input voltages.

08/13/15
20150229214 

Switching control of a bipolar transistor for dcdc power converters


The present document relates to direct current (dc) to dc power converters. In particular, the present document relates to dc to dc power converters which comprise one or more bipolar transistors as power switches.
Dialog Semiconductor Gmbh


08/13/15
20150229147 

Battery charge protection system


A system comprises a battery including one or more cells, an energy source, a load, and a battery protection circuit coupled to the battery, the energy source and the load. The circuit determines if the charge of each cell is at/above a predetermined, band gap supplied threshold voltage, which results in disconnecting of the battery from the energy source.

08/13/15
20150228903 

Process of surface modification of dielectric structures in organic electronic devices


The invention relates to a process of modifying the surface energy of dielectric structures, like for example dielectric layers or bank structures, in organic electronic (oe) devices, more specifically in organic field effect transistors (ofets).. .
Merck Patent Gmbh


08/13/15
20150228897 

Dose-controlled, floating evaporative assembly of aligned carbon nanotubes for use in high performance field effect transistors


High density films of semiconducting single-walled carbon nanotubes having a high degree of nanotube alignment are provided. Also provided are methods of making the films and field effect transistors (fets) that incorporate the films as conducting channel materials.
Wisconsin Alumni Research Foundation


08/13/15
20150228803 

Semiconductor device


The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures. In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode.
Semiconductor Energy Laboratory Co., Ltd.


08/13/15
20150228799 

Semiconductor device


A semiconductor device including an oxide semiconductor in which on-state current is high is provided. The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures.
Semiconductor Energy Laboratory Co., Ltd.


08/13/15
20150228783 

Field effect transistors employing a thin channel region on a crystalline insulator structure


A single crystalline dielectric layer is provided on an insulator layer including an amorphous dielectric material. The single crystalline dielectric layer can be patterned into various crystalline dielectric portions including dielectric fins, dielectric nanowires, and a dielectric fin-plate assembly.
International Business Machines Corporation


08/13/15
20150228777 

Silicon on insulator device with partially recessed gate


transistors having partially recessed gates are constructed on silicon-on-insulator (soi) semiconductor wafers provided with a buried oxide layer (box), for example, fd-soi and utbb devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles.
Stmicroelectronics, Inc.


08/13/15
20150228762 

Gate structure integration scheme for fin field effect transistors


In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor.
International Business Machines Corporation


08/13/15
20150228753 

Self aligned embedded gate carbon transistors


transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses.
International Business Machines Corporation


08/13/15
20150228748 

Multi-composition gate dielectric field effect transistors


A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion.
International Business Machines Corporation


08/13/15
20150228747 

Multiple thickness gate dielectrics for replacement gate field effect transistors


After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer.
International Business Machines Corporation


08/13/15
20150228743 

Fin field-effect transistors having controlled fin height


An apparatus includes a semiconductor substrate having a plurality of fins, wherein the plurality of fins includes a first group of fins and a second group of fins. The apparatus further includes a high fin density area on the semiconductor substrate including a first dielectric between the first group of fins in the high fin density area, said first dielectric having a first dopant concentration.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/13/15
20150228741 

Floating gate flash cell with extended floating gate


Provided is a floating gate flash cell and method for forming the same. The flash includes two floating gate transistors and a common source area therebetween.
Wafertech, Llc


08/13/15
20150228671 

Method of manufacturing a finfet device using a sacrificial epitaxy region for improved fin merge and finfet device formed by same


A method for manufacturing a fin field-effect transistor (finfet) device comprises forming a plurality of fins on a substrate, epitaxially growing a sacrificial epitaxy region between the fins, stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins, and forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors.. .
International Business Machines Corporation


08/13/15
20150228652 

Semiconductor device including nanowire transistors with hybrid channels


A semiconductor device is provided that includes an n-type field effect transistor including a plurality of vertically stacked silicon-containing nanowires located in one region of a semiconductor substrate, and a p-type field effect transistor including a plurality of vertically stacked silicon germanium alloy nanowires located in another region of a semiconductor substrate. Each vertically stacked silicon-containing nanowire of the n-type field effect transistor has a different shape than the shape of each vertically stacked silicon germanium alloy nanowire of the p-type field effect transistor..
International Business Machines Corporation


08/13/15
20150228645 

Semiconductor device and manufacturing


A semiconductor device includes a semiconductor substrate, and first and second transistors over the semiconductor substrate. Both the first and second transistors are p-type transistors or both the first and second transistors are n-type transistors.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/13/15
20150228643 

Diode-connected bipolar junction transistors and electronic circuits including the same


A diode-connected bipolar junction transistor includes a common collector region of a first conductivity, a common base region of a second conductivity disposed over the common collector region, and a plurality of emitter regions of the first conductivity disposed over the common base region, arranged to be spaced apart from each other, and arranged to have island shapes.. .
Sk Hynix Inc.


08/13/15
20150228636 

Layout of composite circuit elements


Physical layouts of ratioed circuit elements, such as transistors, are disclosed. Such layouts can maintain electrical characteristics of the ratioed circuit elements relative to one another in the presence of mechanical stresses applied to an integrated circuit, such as an integrated circuit encapsulated in plastic.
Analog Devices Global


08/13/15
20150228544 

Fin shape for fin field-effect transistors and forming


A fin field-effect transistor (finfet) and a method of forming are provided. A gate electrode is formed over one or more fins.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/13/15
20150228490 

Reduced threshold voltage-width dependency in transistors comprising high-k metal gate electrode structures


Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a p-channel transistor and an n-channel transistor after selectively forming a threshold adjusted semiconductor material for the p-channel transistor, while the active region of the n-channel transistor is still masked..
Globalfoundries Inc.


08/13/15
20150228480 

Method of manufacturing stacked nanowire mos transistor


Methods of manufacturing stacked nanowires mos transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate.
Institute Of Microelectronics, Chinese Academy Of Sciences


08/13/15
20150228357 

Stress balancing of circuits


Methods, systems, and structures for stress balancing field effect transistors subject to bias temperature instability-caused threshold voltage shifts. A method includes characterizing fatigue of a location in a memory array by skewing a bit line voltage of the location.
International Business Machines Corporation


08/13/15
20150228347 

Nonvolatile semiconductor memory device and data erase method thereof


A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, memory strings, drain side selection transistors, source side selection transistors, word lines, bit lines, a source line, a drain side selection gate line, a source side selection gate line, and a control circuit. The control circuit applies a first voltage to a selected bit line, thereby executing an erase operation on a selected memory string connected to the selected bit line, and the control circuit applies a second voltage to a non-selected bit line, thereby prohibiting the erase operation for the selected memory string connected to the non-selected bit line.
Kabushiki Kaisha Toshiba


08/13/15
20150228337 

Semiconductor memory device and control method thereof


A semiconductor memory device comprises: first lines disposed in a first direction perpendicular to a substrate and extending in a second direction parallel to the substrate; second lines disposed in the second direction and configured to extend in the first direction, the second lines intersecting the first lines; and memory cells disposed at intersections of the first lines and the second lines and each including a variable resistance element. Furthermore, a third line extends in a third direction orthogonal to the first and second directions.
Kabushiki Kaisha Toshiba


08/13/15
20150228324 

Semiconductor device


A low-power semiconductor device is provided. A memory device applicable to a multi-context programmable logic device (pld) includes at least memory cells the number of which is the same as the number of contexts.
Semiconductor Energy Laboratory Co., Ltd.


08/13/15
20150228322 

Nmos-offset canceling current-latched sense amplifier


A resistive memory sensing method includes sensing outputs of an offset-cancelling dual stage sensing circuit (ocds-sc) by an nmos offset-cancelling current latched sense amplifier circuit (noc-clsa). The noc-clsa is configured with a reduced input capacitance and a reduced offset voltage.
Qualcomm Incorporated


08/13/15
20150228225 

Display apparatus and display method


A display apparatus includes light-emission units, write transistors, drive transistors, and a plurality of gate drivers. The light-emission units each form a pixel and each configured to emit light by a drive current.
Sony Corporation




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