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This page is updated frequently with new Transistors-related patent applications. Subscribe to the Transistors RSS feed to automatically get the update: related Transistors RSS feeds. RSS updates for this page: Transistors RSS RSS


Method for forming deep trench isolation for rf devices on soi

Method for forming deep trench isolation for rf devices on soi

Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming…

Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming…

Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming…

Semiconductor device

Date/App# patent app List of recent Transistors-related patents
07/02/15
20150189711
 Led controller and method therefor patent thumbnailnew patent Led controller and method therefor
In an embodiment, an led controller is configured to form a charge transfer sequence to selectively enable led transistors of a plurality of led transistors that are configured for coupling in parallel with a plurality of leds. An embodiment may include that the led controller is configured to sequentially couple a charge capacitor to a gate-to-source capacitor of each led transistor of the plurality of led transistors to one of charge or to refresh the gate-to-source capacitor of a respective led transistor and to one of enable or re-enable the respective led transistor wherein the gate-to-source capacitor is a parasitic gate-to-source capacitor of the led transistor wherein the charge capacitor is sequentially coupled to the gate-to-source capacitor of each led transistor..
07/02/15
20150189207
 Protection layer in cmos image sensor array region patent thumbnailnew patent Protection layer in cmos image sensor array region
A semiconductor image sensor device having a conformal protective layer includes a semiconductor substrate a pixel-array region and a peripheral region. The conformal protective layer is disposed over a plurality of pixels having a photodiode and a plurality of transistors in the pixel-array region.
07/02/15
20150188536
 Method and system for reliable bootstrapping switches patent thumbnailnew patent Method and system for reliable bootstrapping switches
Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (mos) transistor having a pull-down path coupled to a gate terminal of the switching mos transistor. The pull-down path includes a diode-connected mos transistor coupled in parallel with a second mos transistor that couples the gate terminal of the switching mos transistor to ground via third and fourth mos transistors when the switching mos transistor is in an off state.
07/02/15
20150188520
 Semiconductor device patent thumbnailnew patent Semiconductor device
A semiconductor device that can operate normally with lower power consumption is provided. The semiconductor device includes a pair of first circuits which each include a first transistor and a second transistor capable of controlling the supply of a first signal to a gate of the first transistor, and a second circuit which is capable of generating a second signal which is to be supplied to a gate of the second transistor and which has a larger amplitude than the first signal.
07/02/15
20150188420
 Output voltage adjustable charge pump patent thumbnailnew patent Output voltage adjustable charge pump
A charge pump that uses a control unit of a chip to adjust the on/off status of power switches and capacitor boost switches of a change-over switch set, enabling input voltage to be boosted by selected capacitors to the desired voltage level subject to conduction and cutoff of selected transistors, and therefore a predetermined voltage level of output voltage can be provided to an internal working circuit of an electronic apparatus without changing the circuit layout of the chip and the package substrate that is packaged on the chip, and thus, the chip and the package substrate simply need to be verified once, eliminating further verification procedure and time prior to vending and saving much the cost.. .
07/02/15
20150188419
 Charge pump that allows change of output voltage by changing the wiring patent thumbnailnew patent Charge pump that allows change of output voltage by changing the wiring
A charge pump includes a chip and a package substrate packaged on the chip and installed in a circuit board. One of the 1st˜(x−y)th external pins of the package substrate is electrically connected to the (x−y)th input pin of the chip, and the other end of the same external pin is electrically connected to the input voltage of the circuit board.
07/02/15
20150188418
 Pumping circuit patent thumbnailnew patent Pumping circuit
A pumping circuit includes a cross-coupled charge pump circuit including first and second capacitors configured to pump an input voltage in response to a first clock signal and to an inverted first clock signal and a plurality of transistors configured to one of transfer the input voltage to the first and second capacitors and to transfer a pumping voltage to an output node, and a switching voltage supply circuit configured to supply switching voltages to gates of the plurality of transistors to enable the transfer of the input voltage and the pumping voltage.. .
07/02/15
20150188313
 Tie-off circuit with output node isolation for protection from electrostatic discharge (esd) damage patent thumbnailnew patent Tie-off circuit with output node isolation for protection from electrostatic discharge (esd) damage
Embodiments relate to electrostatic discharge (esd) protection. One embodiment includes a tie-off circuit including a multiple field effect transistors (fets), a first internal node, a second internal node, a first output node and a second output node.
07/02/15
20150187958
 Igzo devices with reduced electrode contact resistivity and methods for forming the same patent thumbnailnew patent Igzo devices with reduced electrode contact resistivity and methods for forming the same
Embodiments described herein provide indium-gallium-zinc oxide (igzo) devices, such as igzo thin-film transistors (tfts), and methods for forming such devices. A substrate is provided.
07/02/15
20150187956
 Igzo devices with increased drive current and methods for forming the same patent thumbnailnew patent Igzo devices with increased drive current and methods for forming the same
Embodiments described herein provide indium-gallium-zinc oxide (igzo) devices, such as igzo thin-film transistors (tfts), and methods for forming such devices. A substrate is provided.
07/02/15
20150187941
new patent

Transistor and forming the same


Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate can be provided.
07/02/15
20150187939
new patent

Metal gate transistor and tuning metal gate profile


A semiconductor device having arrays of metal gate transistors is fabricated by forming a number of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer, depositing a tensile ild layer between the dummy gate structures, stressing the tensile ild layer, removing at least the dummy gate material to form a number of trenches, and depositing a metal gate material in the trenches, which have a tapered profile.. .
07/02/15
20150187935
new patent

Semiconductor device including pillar transistors


A first pillar transistor and a second pillar transistor are arranged with no other pillar transistor therebetween, a distance between a first silicon pillar in the first pillar transistor and a second silicon pillar in the second pillar transistor is smaller than a distance between a third silicon pillar in a third pillar transistor and the first silicon pillar.. .
07/02/15
20150187924
new patent

Low sheet resistance gan channel on si substrates using inaln and algan bi-layer capping stack


transistors or transistor layers include an inaln and algan bi-layer capping stack on a 2deg gan channel, such as for gan mos structures on si substrates. The gan channel may be formed in a gan buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between gan and si.
07/02/15
20150187881
new patent

Contact resistance reduction in finfets


A semiconductor device having fin transistors includes a plurality of substantially parallel semiconductor fins formed over a substrate and a gate structure formed over the fins transversely to a longitudinal axis of the fins. Source and drain regions are formed on opposite sides of the gate structure and are merged with the fins by an epitaxially grown crystalline material between the fins in merged regions.
07/02/15
20150187878
new patent

Semiconductor device


To provide a semiconductor device including a transistor in which an oxide semiconductor is used and on-state current is high. In a semiconductor device including a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion, the first transistor and the second transistor have different structures.
07/02/15
20150187818
new patent

Light-emitting device


A light-emitting device capable of suppressing variation in luminance among pixels is provided. A light-emitting device includes a pixel and first and second circuits.
07/02/15
20150187794
new patent

Method for forming deep trench isolation for rf devices on soi


A semiconductor device includes a silicon-on-insulator (soi) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a soi substrate having shallow trench isolations (stis) and transistors formed within and on the second semiconductor substrate, respectively.
07/02/15
20150187778
new patent

Semiconductor device


A semiconductor storage device capable of performing low-voltage operation, reducing standby current, and decreasing memory size is provided. The semiconductor storage device is a semiconductor device including first to fourth transistors and a capacitor.
07/02/15
20150187775
new patent

Semiconductor device and driving the same


A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line.
07/02/15
20150187773
new patent

High mobility transistors


An integrated circuit containing an n-channel finfet and a p-channel finfet has a dielectric layer over a silicon substrate. The fins of the finfets have semiconductor materials with higher mobilities than silicon.
07/02/15
20150187772
new patent

Optimized layout for relaxed and strained liner in single stress liner technology


An integrated circuit and method with a single stress liner film and a stress relief implant where the distance of the stress relief implant to the transistors is adjusted for improved transistor performance.. .
07/02/15
20150187770
new patent

High mobility transistors


An integrated circuit containing an n-channel finfet and a p-channel finfet is formed by forming a first polarity fin epitaxial layer for a first polarity finfet, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finfet. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask.
07/02/15
20150187769
new patent

Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods


A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type.
07/02/15
20150187768
new patent

Poly gate extension design methodology to improve cmos performance in dual stress liner process flow


An integrated circuit and method with dual stress liners and with nmos transistors with gate overhang of active that is longer than the minimum design rule and with pmos transistors with gate overhang of active that are not longer than the minimum design rule.. .
07/02/15
20150187759
new patent

High sheet resistor in cmos flow


An integrated circuit containing cmos gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the nsd layers of the nmos transistors of the cmos gates and concurrently with the psd layers of the pmos transistors of the cmos gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the cmos gates. A process of forming an integrated circuit containing cmos gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the nsd layers of the nmos transistors of the cmos gates and concurrently with the psd layers of the pmos transistors of the cmos gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the cmos gates..
07/02/15
20150187747
new patent

Circuit with inter-layer vias and intra-layer coupled transistors


A circuit comprises a first layer comprising a first voltage line, a first transistor coupled with the first voltage line, a second transistor coupled with the first voltage line, and a first line coupling a drain of the first transistor with a gate of the second transistor. The circuit also comprises a second layer comprising a second voltage line, a third transistor coupled with the second voltage line, a fourth transistor coupled with the second voltage line, and a second line coupling a drain of the third transistor with a gate of the fourth transistor.
07/02/15
20150187659
new patent

High quality dielectric for hi-k last replacement gate transistors


A replacement metal gate transistor is formed with high quality gate dielectric under the high-k dielectric. The high quality gate dielectric is formed on the substrate at a temperature of at least 850° c.
07/02/15
20150187653
new patent

High-k / metal gate cmos transistors with tin gates


An integrated circuit with a thick tin metal gate with a work function greater than 4.85 ev and with a thin tin metal gate with a work function less than 4.25 ev. An integrated circuit with a replacement gate pmos tin metal gate transistor with a workfunction greater than 4.85 ev and with a replacement gate nmos tin metal gate transistor with a workfunction less than 4.25 ev.
07/02/15
20150187585
new patent

Dummy gate placement methodology to enhance integrated circuit performance


A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an integrated circuit.. .
07/02/15
20150187552
new patent

High voltage power supply filter


Systems, devices, circuits, and methods are provided for an improved mass spectrometry detection system that comprises at least one component that operates at a high voltage. A number of high voltage filters or circuits are provided for reducing noise from high voltage power supplies that produce positive and negative voltages.
07/02/15
20150187432
new patent

Shift register circuit, display panel, and electronic apparatus


Disclosed herein is a shift register circuit that is formed on an insulating substrate with thin film transistors having channels of the same conductivity type and includes shift stages, each of the shift stages including: a first thin film transistor; a second thin film transistor; a 3(1)-th thin film transistor; a 3(2)-th thin film transistor; a 4(1)-th thin film transistor; a 4(2)-th thin film transistor; a fifth thin film transistor; and a sixth thin film transistor.. .
07/02/15
20150187418
new patent

Metal line connection for improved rram reliability, semiconductor arrangement comprising the same, and manufacture thereof


An integrated circuit device includes an array of rram cells, an array of bit lines for the array of rram cells, and an array of source lines for the array of rram cells. Both the source lines and the bit lines are in metal interconnect layers above the rram cells.
07/02/15
20150187260
new patent

Organic light emitting display device


An organic light emitting display device including an emission unit and a pixel circuit unit. The emission unit includes an organic light emitting diode.
07/02/15
20150185754
new patent

Temperature and process compensated current reference circuits


A reference current path carries a reference current. A first transistor is coupled to the reference current path.
07/02/15
20150185565
new patent

Curved liquid crystal display


A curved liquid crystal display including a first substrate having a curved shape; a plurality of gate lines and data lines on the first substrate; a plurality of thin film transistors connected to the gate lines and data lines; a plurality of color filters on the thin film transistors; a plurality of pixel electrodes and common electrodes on the plurality of color filters, the plurality of pixel electrodes and common electrodes overlapping with each other with a first insulating layer therebetween; a second substrate having a curved shape, the second substrate facing the first substrate; vertical alignment layers on inner sides of the first substrate and the second substrate; and a liquid crystal layer between the vertical alignment layers, wherein liquid crystal molecules of the liquid crystal layer are aligned to be vertical to surfaces of the first substrate and the second substrate when an electric field is not formed.. .
07/02/15
20150185556
new patent

Liquid crystal display


A liquid crystal display includes: first and second substrates; a liquid crystal layer sandwiched between the first and second substrates and comprising a polymer network liquid crystal (pnlc) or a polymer dispersed liquid crystal (pdlc); a common electrode provided on the first substrate; transistors provided on the second substrate for respective pixels; a reflective film provided on the transistors; a color filter provided on the reflective film; and pixel electrodes provided on the color filter and electrically connected to drain electrodes of the respective transistors.. .
07/02/15
20150185531
new patent

Liquid crystal display panel, pixel structure and driving method thereof


The present disclosure relates to a liquid crystal display panel, a pixel structure and a driving method. The pixel structure comprise: a plurality of pixel areas formed by configuring a plurality of data lines and a plurality of scanning lines in a staggered manner; a plurality of pixel electrodes each configured on a corresponding pixel area; a plurality of common lines arranged in a manner of corresponding to the scanning lines respectively one by one, and each of the common lines is overlapped and coupled with the pixel electrode on each pixel area formed by the corresponding scanning line to form a storage capacitor; and a plurality of transistors, each of which is electrically connected with the pixel electrode, the scanning lines and the data lines on each pixel area respectively, wherein each common line is independently controlled in a manner of corresponding to each scanning line so as to eliminate the influence of a feed through voltage on a pixel electrode voltage.
06/25/15
20150181706

High voltage polymer dielectric capacitor isolation device


An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels.
Texas Instruments Incorporated
06/25/15
20150180473

Transistor devices operating with switching voltages higher than a nominal voltage of the transistor


A voltage selector circuit may be coupled to transistors to protect one or more inputs of the transistor from exceeding a safe operating range. In one example, a cross-coupled pair of transistors may be coupled to a gate of a transistor to select between a first voltage and a cascoded voltage that is a safe bias voltage.
Cirrus Logic, Inc.
06/25/15
20150180469

Circuit and body biasing


Various example embodiments are directed to methods and circuits for mitigation of on-resistance variation and signal attenuation in transistors due to body effects. In some embodiments, an apparatus includes a transistor configured to provide a data signal from a first one of the source or the drain to the other one of the source or the drain in response to a control signal provided to the gate.
Nxp B.v.
06/25/15
20150180466

Switching circuit and semiconductor module


A switching circuit includes first to (n+1)th input/output terminals and first to nth field-effect transistors (fets), for an integer n of two or more. When one of a source end and a drain end is referred to as a first end and another one is referred to as a second end, the first input/output terminal is electrically connected to the first ends of all of the first to nth fets.
Murata Manufacturing Co., Ltd.
06/25/15
20150180464

Circuit and body biasing


Various example embodiments are directed to methods and circuits for mitigation of on-resistance variation and signal attenuation in transistors due to body effects. In some embodiments, an apparatus includes a transistor configured to provide a data signal from a first one of the source or the drain to the other one of the source or the drain in response to a control signal provided to the gate.
Nxp B.v.
06/25/15
20150180452

Low leakage cmos cell with low voltage swing


A cmos cell incorporated on an integrated circuit including a pmos transistor and an nmos transistor. The current terminals of the pmos and nmos transistors are coupled in series between a lower voltage supply rail and a reference rail.
Freescale Semiconductor, Inc.
06/25/15
20150180424

High-gain low-noise preamplifier and associated amplification and common-mode control method


A preamplifier includes a differential pair of transistors receiving a bias current having a differential input and a differential output, a first resistor coupled to a first differential output node, a first transistor having a current path coupled between the first resistor and a power supply, a second resistor coupled to the first differential output node, a second transistor having a current path coupled between the second resistor and the power supply, a third resistor coupled to a second differential output node, a third transistor having a current path coupled between the third resistor and the power supply, a fourth resistor coupled to the second differential output node, and a fourth transistor having a current path coupled between the fourth resistor and the power supply, wherein a source of the second and third transistors are coupled together.. .
Aeroflex Colorado Springs Inc.
06/25/15
20150179957

Nickel complexes for flexible transistors and inverters


The ligands and counter-cations are selected to optimize properties, such as molecular alignment, film morphology, and molecular packaging. Described herein, the ligands can be 2,3-pyrazinedithiol (l1), 1,2-benzenedithol (l2) or 2,3-quinoxalinedithol (l3) and the counter-cations can be diquat (2,2′-ebpy) or methyl viologen (4,4′-mbpy).
06/25/15
20150179924

Magnetoresistive random access memory (mram) differential bit cell and use


A magnetoresistive random access memory (mram) bit cell includes a first magnetic tunnel junction (mtj) connected to a first data line. The mram bit cell further includes a second mtj connected to a second data line.
Taiwan Semiconductor Manufacturing Company, Ltd.
06/25/15
20150179822

Semiconductor device capable of reducing influences of adjacent word lines or adjacent transistors and fabricating method thereof


A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate.
Nanya Technology Corp.
06/25/15
20150179815

Quantum well igzo devices and methods for forming the same


Embodiments described herein provide indium-gallium-zinc oxide (igzo) devices, such as igzo thin-film transistors (tfts), and methods for forming such devices. A substrate is provided.
Intermolecular, Inc.
06/25/15
20150179787

Group iii-v semiconductor transistor and manufacturing the same


Provided are group iii-v semiconductor transistors and methods of manufacturing the same. The method includes forming a group iii-v semiconductor channel layer on a substrate, forming a gate insulating layer covering the group iii-v semiconductor channel layer, and forming a protection layer including sulfur between the group iii-v semiconductor channel layer and the gate insulating layer by annealing the substrate under a sulfur atmosphere..
Industry-university Cooperation Foundation Hanyang University Erica Campus
06/25/15
20150179778

Soi lateral bipolar transistors having surrounding extrinsic base portions


Lateral soi bipolar transistor structures are provided including an intrinsic base semiconductor material portion in which all surfaces of the intrinsic base not forming an interface with either a collector semiconductor material portion or an emitter semiconductor material portion, contain an extrinsic base semiconductor material portion. Each extrinsic base semiconductor material portion is of the same conductivity type as that of the intrinsic base semiconductor material portion, yet each extrinsic base semiconductor material portion has a higher dopant concentration than the intrinsic base semiconductor material portion.
International Business Machines Corporation
06/25/15
20150179773

Igzo devices with reduced threshhold voltage shift and methods for forming the same


Embodiments described herein provide indium-gallium-zinc oxide (igzo) devices, such as igzo thin-film transistors (tfts), and methods for forming such devices. A substrate is provided.
Intermolecular, Inc.
06/25/15
20150179757

Methods to characterize an embedded interface of a cmos gate stack


Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors.
Intermoleular, Inc.
06/25/15
20150179715

Organic light emitting diode array


The disclosure relates to an organic light emitting diode array. The organic light emitting diode array includes a number of thin-film transistors arranged to form an array, a first insulative layer, a plurality of first electrodes, a number of electroluminescent layers, a patterned second insulative layer, and at least one second electrode.
Hon Hai Precision Industry Co., Ltd.
06/25/15
20150179696

Photodetector circuit and semiconductor device


To provide a photodetector circuit capable of obtaining signals in different periods without being affected by characteristics of a photoelectric conversion element. The photodetector circuit has n signal output circuits (n is a natural number of 2 or more) connected to the photoelectric conversion element.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179684

High productivity combinatorial material screening for stable, high-mobility non-silicon thin film transistors


Methods for hpc techniques are applied to the processing of site-isolated regions (sir) on a substrate to form at least a portion of a tft device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor deposition, metal-based patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning.
Intermolecular, Inc.
06/25/15
20150179675

Display device and manufacturing the same


An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179674

Hard coating film and display device using the same


Disclosed is a display device that includes a display element including a plurality of thin film transistors; and a hard coating film on the display element, the hard coating film including: a base film; and a hard coating layer on the base film, the hard coating layer including a photo-curable resin composition and a plurality of porous particles.. .
Lg Display Co., Ltd.
06/25/15
20150179656

Ct-nor differential bitline sensing architecture


Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of memory transistors arranged electrically in serial is configured to control a gate voltage of a pass transistor.
Spansion Llc
06/25/15
20150179655

Static random access memory (sram) cells including vertical channel transistors and methods of forming the same


A static random access memory (sram) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor sram cell, wherein each of the transistors is configured as a vertical channel transistor.. .
Samsung Electronics Co., Ltd.
06/25/15
20150179654

Epitaxial source/drain differential spacers


A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over gates of both transistors, performing an epitaxial spacer anisotropic etch process to form epitaxial spacers on vertical surfaces adjacent to the first transistor gate and removing the epitaxial spacer layer from the second transistor gate, subsequently performing a source/drain etch process and a source/drain epitaxial process to form source/drain epitaxial regions in the substrate adjacent to the first and second gates, such that the first source/drain epitaxial regions are separated from the first gate by a lateral space which is at least 2 nanometers larger than a second lateral space separating the second source/drain epitaxial regions from the second gate. An integrated circuit formed by the recited process..
Texas Instruments Incorporated
06/25/15
20150179630

Esd protection circuit


An electrostatic discharge (esd) protection circuit is provided. The esd protection circuit includes a first nmos transistor coupled to a power line, a second nmos transistor coupled between the first transistor and a ground, a detection unit, providing a detection signal when an esd event occurs at the power line, and a trigger unit, turning on the second nmos transistor and the first nmos transistor in sequence in response to the detection signal, such that a discharge path is formed from the power line to the ground via the first and second nmos transistors.
Mediatek Inc.
06/25/15
20150179503

Mechanism for finfet well doping


The embodiments of mechanisms for doping wells of finfet devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions.
Taiwan Semiconductor Manufacturing Company, Ltd.
06/25/15
20150179264

Nonvolatile memory device and driving the same


A nonvolatile memory device includes a plurality of memory blocks, and a pass transistor array transmitting a plurality of drive signals to a selected memory block among the plurality of memory blocks in response to a block select signal. The pass transistor array includes high voltage transistors including one common drain and two sources formed in one active region and one of the plurality of drive signals transmitted to the common drain is transmitted to different memory blocks through the two sources..
Samsung Electronics Co., Ltd.
06/25/15
20150179243

Word line driving circuit


The word line driving circuit includes a plurality of first pull-down transistors connected in series and suitable for pull-down driving a control node in response to a plurality of address information signals, a driving signal output unit suitable for activating a word line driving signal when the control node is activated and deactivating the word line driving signal when a word line off signal is activated, a first pull-up transistor suitable for pull-up driving the control node when the word line driving signal is deactivated, and a clamping unit suitable for limiting the amount of current flowing to the first pull-up transistor.. .
Sk Hynix Inc.
06/25/15
20150179121

Liquid crystal display device


Disclosed is a liquid crystal display (lcd) device. The lcd device include first and second gate lines, data lines, a common electrode line formed between adjacent data lines and configured to perpendicularly cross the plurality of first and second gate lines and divide the plurality of pixel areas into first and second areas, first and second thin film transistors (tfts) formed between a corresponding first gate line and a second gate line adjacent to the corresponding first gate line, a protective layer configured to include a first contact hole and a second contact hole, a common electrode formed on the protective layer and coupled to the common electrode line through the first contact hole, an insulation layer formed on the protective layer to cover the common electrode and a pixel electrode formed on the insulation layer..
Lg Display Co., Ltd.
06/25/15
20150179101

Pixel circuit, display device including the same and driving the display device


A pixel circuit is capable of maintaining a display quality even in cases where an input transistor has a low mobility, or where it is impossible to take a sufficient selection period for each scanning line. A pixel circuit includes an organic el element (oled), transistors, and a capacitor.
Sharp Kabushki Kaisha
06/25/15
20150179095

Light emitting device and driving the same


The present invention specifies the characteristic of a driving transistor provided in a pixel and corrects a video signal to be inputted to the pixel based on the specification. As a result, a light emitting device and its driving method in which influence of fluctuation in characteristic among transistors is removed to obtain clear multi-gray scale are provided.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150177874

Apparatus for generating driving signal


There is provided an apparatus for generating a driving signal, the apparatus including: a first driving signal generation circuit generating a first driving signal; a second driving signal generation circuit generating a second driving signal, the second driving signal generation circuit including at least two transistors and a pulse generation unit; and a control unit controlling the first and second driving signal generation circuits so that they generate the first and second driving signals selectively.. .
Samsung Electro-mechanics Co., Ltd.
06/25/15
20150177869

Transcapacitive sensor using transmit on gate lines


Capacitive sensing is performed in an input device having an input sensor and associated display device using gate lines of the display device. A transmitter signal having a negative pulse is used to safely transmit a transcapacitive transmitter signal while not opening any of the access transistors in the display device..
Synaptics Incorporated
06/25/15
20150177796

Rotating voltage control


According to one embodiment, a system is provided that includes at least one power gated component and two or more power switch transistors configured to provide one or more conductive paths between a common power supply rail, the at least one power gated component, and a ground. The two or more power switch transistors each include a source terminal, a drain terminal, and a gate terminal configured to control current flow between the source and drain terminals.
International Business Machines Corporation
06/25/15
20150177772

Electronic circuit with self-calibrated ptat current reference and actuating the same


The electronic circuit with a self-calibrated ptat current reference includes a ptat current generator dependent on at least one integrated resistor for supplying a ptat output current. It further includes a reference current generator dependent on at least one switched capacitor resistor, for supplying a reference current.
The Swatch Group Research And Development Ltd
06/25/15
20150177438

Display having backlight with narrowband collimated light sources


A display has an array of display pixels formed from display layers such as one or more polarizer layers, a substrate on which an array of display pixel elements such as color filter elements and downconverter elements are formed, a liquid crystal layer, and a thin-film transistor layer that includes display pixel electrodes and display pixel thin-film transistors for driving control signals onto the display pixel electrodes to modulate light passing through the display pixels. A light source such as one or more laser diodes or light-emitting diodes may be used to generate light for the display.
Apple Inc.


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Transistors topics: Transistors, Semiconductor, Semiconductor Device, Integrated Circuit, High Speed, Photodiode, Memory Effect, Silicon Nitride, Enhancement, Ion Implant, Ion Channel, Interrupted, Reference Voltage, Semiconductor Devices, Semiconductor Substrate

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