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Transistors patents



      

This page is updated frequently with new Transistors-related patent applications.




Date/App# patent app List of recent Transistors-related patents
02/04/16
20160037595 
 Alternating-current high-voltage multi-segment partitioned light source driving device and method thereof patent thumbnailAlternating-current high-voltage multi-segment partitioned light source driving device and method thereof
The present invention discloses an alternating high-voltage multi-segment partitioned light source driving device and method thereof. The device includes a power source, a signal control module, n segment constant-current driving modules, n mos transistors and n segments of led lights, where n is a natural number greater than or equal to 2.
Shenzhen Puyi Lighting Technology Co., Ltd


02/04/16
20160036432 
 Wide input range, low output voltage power supply patent thumbnailWide input range, low output voltage power supply
This disclosure describes techniques for generating relatively low regulated power supply voltages over a relatively wide range of input voltages. The techniques for generating the regulated voltages may include using at least two different pass transistors to regulate an output voltage of a voltage regulator.
Texas Instruments Incorporated


02/04/16
20160036428 
 Fine-grained power gating in fpga interconnects patent thumbnailFine-grained power gating in fpga interconnects
Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a pmos transistor and an nmos transistor, where at least one input to the inverter stage is provided to the gates of the pmos and nmos transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the pmos transistor and places the pmos transistor in a cutoff mode of operation..
The Regents Of The University Of California


02/04/16
20160036399 
 Limiting driver for switch-mode power amplifier patent thumbnailLimiting driver for switch-mode power amplifier
A switch-mode rfpa driver includes first and second field-effect transistors (fets) arranged in a totem-pole-like configuration. The switch-mode rfpa driver operates to generate a switch-mode rfpa drive signal having a generally square-wave-like waveform from an input rf signal having a generally sinusoidal-like waveform.
Eridan Communications, Inc.


02/04/16
20160036397 
 Semiconductor amplifier circuit patent thumbnailSemiconductor amplifier circuit
According to one embodiment, a semiconductor amplifier circuit includes: a first amplifier circuit including first and second p-type transistors; a second amplifier circuit including first and second n-type transistors; and first to seventh current mirror circuits. The first and second current mirror circuits are connected to drains of the first and second p-type transistors.
Kabushiki Kaisha Toshiba


02/04/16
20160036396 
 Power amplifier, and  the same patent thumbnailPower amplifier, and the same
A power amplifier comprises a first inductor, a second inductor, a capacitor, a first mos transistor, a second mos transistor and a current source. The first and the second inductors are both connected to a first power supply.
Beken Corporation


02/04/16
20160036395 
 Apparatus and methods for overdrive protection of radio frequency amplifiers patent thumbnailApparatus and methods for overdrive protection of radio frequency amplifiers
Provided herein are apparatus and methods for overdrive protection of radio frequency (rf) amplifiers. In certain configurations, an rf amplifier includes a plurality of amplification stages and an overdrive detection circuit.
Skyworks Solutions, Inc.


02/04/16
20160036393 
 Linearized gate capacitance in power amplifiers patent thumbnailLinearized gate capacitance in power amplifiers
An apparatus includes: a plurality of amplification stages, each stage comprising a cascode transistor; and a bridge circuit coupled between gate terminals of cascode transistors in two adjacent stages of the plurality of amplification stages, the bridge circuit including a plurality of diodes.. .
Qualcomm Incorporated


02/04/16
20160036387 
 Output stage for class ab amplifier patent thumbnailOutput stage for class ab amplifier
The invention relates to a class ab amplifier for receiving an input current and generating an amplified output current and having first and second output transistors connected to provide the output current, wherein if the input current is less than a threshold the first output transistor is enabled and the second output transistor is disabled, and if the input current exceeds a threshold the second output transistor is enabled.. .
Snaptrack, Inc.


02/04/16
20160036382 
 Low power wide tuning range oscillator patent thumbnailLow power wide tuning range oscillator
A wide tuning range oscillator system uses multiple active cores with cross-coupled transistors and multiple tapped inductors having windings that can be connected to circuit nodes. These active cores are connected to a pair of symmetric tapping points and are switched on/off by biasing elements.
Texas Instruments Incorporated


02/04/16
20160036332 

Control apparatus, buck-boost power supply and control method


A control apparatus, a buck-boost power supply, and a control method that can control an output part comprising two primary switches which are n-type transistors without changing the switching frequency are provided. A control apparatus for a buck-boost power supply comprises: a pulse-width modulation (pwm) signal generator configured to generate a pwm signal having a pulse whose pulse width is based on an output voltage; a mode pulse signal generator configured to generate a mode pulse signal having a signal whose time period is based on at least one of an input voltage, a difference between an input voltage and the output voltage, and a difference between an input voltage and a voltage proportional to the output voltage; a first delayed signal generator configured to generate a first delayed signal having a pulse whose rising edge or falling edge is delayed for a first delay time from a rising edge or a falling edge of the pulse of the pwm signal; and an output controller configured to control an output part of the buck-boost power supply, based on the pwm signal, the mode pulse signal, and the first delayed signal, the output part comprising: two primary switches that are each an n-type transistor; a boost capacitor for driving the high-side switch of the primary switches; and two secondary switches that are each a transistor, wherein the output controller controls switching of the output part so that a first time period during which the high-side switch of the primary switches is off and the low-side switch of the primary switches is on is longer than or equal to the first delay time..
Spansion Llc


02/04/16
20160036330 

Apparatus and methods for integrated power converter with high bandwidth


A dc-dc power converter includes a switched inductor power converter and a parallel linear voltage regulator. Two transistors are positioned in the switched inductor power converter to periodically set a bridge voltage thereby producing a square wave with a fixed frequency and variable duty cycle.
Ferric Inc.


02/04/16
20160036007 

Light-emitting transistors with improved performance


Disclosed are light-emitting transistors having novel structures that can lead to enhanced device brightness, specifically, via incorporation of additional electrically insulating components that can favor charge localization and in turn, carrier recombination and exciton formation.. .
Polyera Corporation


02/04/16
20160035989 

Hybrid junction field-effect transistor and active matrix structure


Junction field-effect transistors including inorganic channels and organic gate junctions are used in some applications for forming high resolution active matrix displays. Arrays of such junction field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes..
International Business Machines Corporation


02/04/16
20160035891 

Stress in n-channel field effect transistors


A fin field-effect transistor (finfet) includes a gate stack on a surface of a semiconductor fin. The semiconductor fin may include a capping material and a stressor material.
Qualcomm Incorporated


02/04/16
20160035860 

Contact techniques and configurations for reducing parasitic resistance in nanowire transistors


Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nano-wire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor..
Intel Corporation


02/04/16
20160035855 

Organic-inorganic hybrid multilayer gate dielectrics for thin-film transistors


Disclosed are organic-inorganic hybrid self-assembled multilayers that can be used as electrically insulating (or dielectric) materials. These multilayers generally include an inorganic primer layer and one or more bilayers deposited thereon.

02/04/16
20160035847 

Gate with self-aligned ledged for enhancement mode gan transistors


An enhancement-mode gan transistor with reduced gate leakage current between a gate contact and a 2deg region and a method for manufacturing the same. The enhancement-mode gan transistor including a gan layer, a barrier layer disposed on the gan layer with a 2deg region formed at an interface between the gan layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer.
Efficient Power Conversion Corporation


02/04/16
20160035843 

Cmos in situ doped flow with independently tunable spacer thickness


A method for manufacturing a microelectronic device with transistors of different types having raised source and drain regions and different overlap regions.. .
Stmicroelectronics Inc


02/04/16
20160035841 

Multi-composition gate dielectric field effect transistors


A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion.
International Business Machines Corporation


02/04/16
20160035814 

Organic light emitting diode display and manufacturing the same


An organic light emitting device includes a switching transistor and a driving transistor. A semiconductor layer is commonly used by the switching and driving transistors.
Samsung Display Co., Ltd.


02/04/16
20160035801 

Flexible display device and fabricating the same


A flexible display device including a substrate; a driving element layer including a plurality of thin film transistors on the substrate; a display element layer including organic light-emitting diodes electrically connected to the thin film transistors on the driving element layer; a light transmissive layer on the display element layer and configured to adjust a neutral plane of the flexible display device to lie at the driving element layer and the display element layer when the flexible display device is bent; and a back plate film attached to a back side of the substrate and having a cut portion formed in a center region where the flexible display device is bent.. .
Lg Display Co., Ltd.


02/04/16
20160035789 

Method of manufacturing semiconductor device and semiconductor device having unequal pitch vertical channel transistors


A semiconductor device comprises a set of selection transistors, such as in a three-dimensional memory structure or stack having resistance change memory cells arranged along vertical bit lines. Each selection transistor has a non-shared control gate and a shared control gate.
Sandisk 3d Llc


02/04/16
20160035781 

Solid-state imaging device and electronic instrument


A solid-state imaging device including, a first semiconductor region of the first conduction type, a photoelectric conversion part having a second semiconductor region of the second conduction type formed in the region separated by the isolation dielectric region of the first semiconductor region, pixel transistors formed in the first semiconductor region, a floating diffusion region of the second conduction type which is formed in the region separated by the isolation dielectric region of the first semiconductor region, and an electrode formed on the first semiconductor region existing between the floating diffusion region and the isolation dielectric region and is given a prescribed bias voltage.. .
Sony Corporation


02/04/16
20160035762 

Methods for manufacturing rfid tags and structures formed therefrom


Radio frequency identification (rfid) tags and processes for manufacturing the same. The rfid device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors.
Thin Film Electronics, Asa


02/04/16
20160035757 

Semiconductor device


A semiconductor device capable of maintaining data during instantaneous power reduction or interruption. The semiconductor device includes first to sixth transistors.
Semiconductor Energy Laboratory Co., Ltd.


02/04/16
20160035753 

Complementary thin film transistor and manufacturing method thereof, array substrate, display apparatus


The present invention provides a complementary thin film transistor and a manufacturing method thereof, an array substrate and a display apparatus, relates to the field of manufacturing technology of thin film transistor, and can solve the problem that active layer materials of first and second thin film transistors in a complementary thin film transistor of the prior art have influence with each other. The manufacturing method of the present invention comprises steps of: forming a pattern comprising an active layer of a first thin film transistor and a protective layer on a base by a patterning process, and the protective layer is at least located above the active layer of the thin film transistor; and forming a pattern of an active layer of a second thin film transistor on the base subjected to above step by a patterning process.
Boe Technology Group Co., Ltd.


02/04/16
20160035743 

Field effect transistor (fet) with self-aligned contacts, integrated circuit (ic) chip and manufacture


Field effect transistors (fets), integrated circuit (ic) chips including the fets, and a method of forming the fets and ic. Fet locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (soi) wafer.
Globalfoundries Inc.


02/04/16
20160035736 

High endurance non-volatile memory cell


The present disclosure relates to a non-volatile memory cell structure, and an associated method. A non-volatile memory cell includes two transistors spaced apart from one another with floating gates connected together by a floating gate bridge.
Taiwan Semiconductor Manufacturing Co., Ltd.


02/04/16
20160035735 

Antifuse element utilizing non-planar topology


Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as finfet topology.
Intel Corporation


02/04/16
20160035727 

Cmos structure with beneficial nmos and pmos band offsets


A cmos structure with beneficial nmos and pmos band offsets is disclosed. A first silicon germanium layer is formed on a semiconductor substrate.
Globalfoundries Inc.


02/04/16
20160035725 

Tungsten gates for non-planar transistors


The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar nmos transistors, wherein an nmos work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar nmos transistor gate..
Intel Corporation


02/04/16
20160035724 

Tungsten gates for non-planar transistors


The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar nmos transistors, wherein an nmos work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar nmos transistor gate..
Intel Corporation


02/04/16
20160035722 

Semiconductor devices and structures


An integrated circuit device, including: a first layer including first transistors; and a second layer including second transistors overlaying the first layer, where the first transistors are facing down and the second transistors are facing up, and where the second layer includes a through layer via of less than 300 nm diameter.. .
Monolithic 3d Inc.


02/04/16
20160035721 

Common drain semiconductor device structure and method


In one embodiment, a common drain semiconductor device includes a substrate, having two transistors integrated therein. The substrate also includes a plurality of active regions on a major surface of the substrate.
Semiconductor Components Industries, Llc


02/04/16
20160035630 

Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures


One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the n-active region while masking the p-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the p-active region while masking the n-active region, forming an n-type transistor in and above the n-active region and forming a p-type transistor in and above the p-active region.. .
Globalfoundries Inc.


02/04/16
20160035431 

Three-dimensional nonvolatile memory and related read method designed to reduce read disturbance


A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively.
Samsung Electronics Co., Ltd.


02/04/16
20160035430 

Compact high speed sense amplifier for non-volatile memory with reduced layout area and power consumption


A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation.
Sandisk Technologies, Inc.


02/04/16
20160035426 

Bias to detect and prevent short circuits in three-dimensional memory device


In a three-dimensional stacked non-volatile memory device, a short circuit in a select gate layer is detected and prevented. A short circuit may occur when charges which are accumulated in select gate lines due to plasma etching, discharge through a remaining portion of the select gate layer in a short circuit path when the select gate lines are driven.
Sandisk Technologies, Inc.


02/04/16
20160035424 

Systems and methods for trimming control transistors for 3d nand flash


Control transistors and memory cells within 3d nand flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process. However, the resulting control transistors may initially have higher variability in threshold voltages, when compared to traditional gate-oxide-based control transistors.
Macronix International Co., Ltd.


02/04/16
20160035309 

Driver circuit incorporating level shift circuit


A level shift circuit includes first and second nmos transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth pmos transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth pmos transistor which is coupled between a gate of the third pmos transistor and the second output node, and has a gate coupled to the first output node, a sixth pmos transistor which is coupled between a gate of the fourth pmos transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth pmos transistors, respectively.. .
Renesas Electronics Corporation


02/04/16
20160035300 

Level shift circuit, gate driving circuit and display apparatus


Provided are a level shift circuit, a gate driving circuit and a display apparatus. The level shift circuit comprises a third transistor (m3), a fourth transistor (m4), a fifth transistor (m5), a sixth transistor (m6) and a seventh transistor (m0), the sources of the which transistors are connected to a dc power source (vdd) respectively, and the gates of which transistors are connected to an offset voltage terminal (vbias) respectively, wherein the drains of the third transistor (m3) and the fifth transistor (m5) are connected as a first output terminal (out1), the drains of the fourth transistor (m4) and the sixth transistor (m6) are connected as a second output terminal (out2); and a first transistor (m1) and a second transistor (m2), the gates of which transistors are both connected to an input signal terminal (vin), the sources of which transistors are both connected to the drain of the seventh transistor (m0), wherein the drain of the first transistor (m1) is connected to the first output terminal (out1), the drain of the second transistor (m2) is connected to the second output terminal (out2); a seventh transistor (m0), the source of the seventh transistor (m0) is connected to a reference ground (vss), and the gate of the seventh transistor (m0) is connected to the offset voltage terminal (bbias).
Beijing Boe Display Technology Co., Ltd.


02/04/16
20160035298 

Array substrate, driving the same, flexible display device and electronic equipment


The present disclosure provides an array substrate, which includes a flexible substrate and an array layer formed on the flexible substrate. The array layer includes: data lines, gate lines, thin film transistors and a driving unit.
Boe Technology Group Co., Ltd.


02/04/16
20160035283 

Display device


A display device includes dummy pixels adjacent to active pixels, and a controller to control pixel driving circuits in the active pixels and dummy driving circuits in the dummy pixels. The dummy driving circuit includes a pumping capacitor, and first and second transistors to connect an initialization voltage terminal to a dummy anode terminal.
Samsung Display Co., Ltd.


02/04/16
20160034629 

Method of converting between non-volatile memory technologies and system for implementing the method


A method of designing a charge trapping memory array includes designing a memory array layout. The memory array layout includes a first type of transistors; electrical connections between memory cells of the memory array layout; a first input/output (i/o) interface; and a charge pump.
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160033627 

Non-saturating receiver design and clamping structure for high power laser based rangefinding instruments


A non-saturating receiver design and clamping structure for high power laser rangefinders of especial utility with respect to pumped, monoblock lasers. The receiver comprises a photodiode and a transimpedance amplifier having at least first and second stages.
Kama-tech (hk) Limited


02/04/16
20160029999 

Intravascular ultrasound imaging apparatus, interface architecture, and manufacturing


Solid-state ultrasound imaging devices, systems, and methods are provided. Some embodiments of the present disclosure are particularly directed to compact and efficient ultrasound transducer scanner formed from a substantially cylindrical semiconductor substrate.
Volcano Corporation


01/28/16
20160028977 

Cmos image sensors with photogate structures and sensing transistors, operation methods thereof, and image processing systems including the same


Acmos image sensor includes a pixel array having a plurality of pixels. Each of the plurality of pixels includes: a photogate structure configured to be controlled based on a first gate voltage; and a sensing transistor including a charge pocket region formed in a substrate region, the sensing transistor being configured to be controlled based on a second gate voltage.

01/28/16
20160028410 

Delay cell, delay locked look circuit, and phase locked loop circuit


A delay cell includes a first transistor and a second transistor, at least one of which has a fully depleted silicon-on-insulator (fd-soi) structure. A first control voltage is applied to the body of the first transistor and a second control voltage is applied to the body of the second transistors in order to adjust the delay time of the delay cell.
Samsung Electronics Co., Ltd.


01/28/16
20160028398 

Nand gate circuit, display back plate, display device and electronic device


The nand gate circuit includes at least two input transistors, at least two pull-up modules and at least two input control transistors. A first electrode of each input transistor is connected to a second level output end via the pull-up module.
Boe Technology Group Co., Ltd.


01/28/16
20160028378 

Receiving circuit


A receiving circuit includes first input transistors of a first conductivity type including control terminals to which differential input signals are applied; load transistors of a second conductivity type connected between a first wiring to which a first voltage is supplied and first terminals of the first input transistors; second input transistors of the second conductivity type including control terminals to which the differential input signals are applied; a latch circuit connected between a second wiring to which a second voltage is supplied and first terminals of the second input transistors; and conversion transistors of the second conductivity type connected in parallel to the second input transistors, the conversion transistors including control terminals that are connected to output nodes to which the first input transistors and the load transistors are connected.. .
Socionext Inc.


01/28/16
20160028349 

Differential crystal oscillator circuit


A differential crystal oscillator circuit, including: first and second output terminals; a cross-coupled oscillation unit including first and second transistors cross-coupled to the first and second output terminals; first and second metal-oxide semiconductor field-effect transistor (mosfet) diodes, each mosfet diode including a resistor connected between gate and drain terminals, wherein the first mosfet diode couples to the first transistor to provide low-impedance load at low frequencies and high-impedance load at higher frequencies to the first transistor, wherein the second mosfet diode couples to the second transistor to provide low-impedance load at low frequencies and high-impedance load at higher frequencies to the second transistor; and a reference resonator coupled between the first and second output terminals to establish an oscillation frequency.. .
Qualcomm Incorporated


01/28/16
20160028341 

Systems and methods for zero common mode voltage


An electrical system includes a converter having an h-bridge. The h-bridge includes a first set of transistors electrically connected in series and a second set of transistors electrically connected in series.
Hamilton Sundstrand Corporation


01/28/16
20160028302 

Protection of switched capacitor power converter


Transient or fault conditions for a switched capacitor power converter are detected by measuring one or more of internal voltages and/or currents associated with switching elements (e.g., transistors) or phase nodes, or voltages or currents at terminals of the converter, and based on these measurements detect that a condition has occurred when the measurements deviate from a predetermined range. Upon detection of the condition fault control circuitry alters operation of the converter, for example, by using a high voltage switch to electrically disconnect at least some of the switching elements from one or more terminals of the converter, or by altering timing characteristics of the phase signals..
Arctic Sand Technologies, Inc.


01/28/16
20160028004 

Nanoporous metal-oxide memory


A nanoporous (np) memory may include a non-porous layer and a nanoporous layer sandwiched between the bottom and top electrodes. The memory may be free of diodes, selectors, and/or transistors that may be necessary in other memories to mitigate crosstalk.
William Marsh Rice University


01/28/16
20160027905 

Bipolar junction transistors and methods of fabrication


A structure, including a bipolar junction transistor and method of fabrication thereof, is provided herein. The bipolar junction transistor includes: a substrate including a substrate region having a first conductivity type; an emitter region over a first portion of the substrate region, the emitter region having a second conductivity type; a collector region over a second portion of the substrate region, the collector region having the second conductivity type; and, a base region overlie structure disposed over, in part, the substrate region.
Globalfoundries Inc.


01/28/16
20160027893 

Multiple thickness gate dielectrics for replacement gate field effect transistors


After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer.
International Business Machines Corporation


01/28/16
20160027835 

Imaging device, control imaging device, and pixel structure


An imaging device having phototransistors in photodetectors of pixels is disclosed. The imaging device includes an implanted electrode configured to separate the pixels, a first emitter disposed at a position adjacent to the implanted electrode, and a second emitter disposed such that a distance from the implanted electrode to the second emitter is longer than a distance from the implanted electrode to the first emitter..
Ricoh Company, Ltd.


01/28/16
20160027809 

Semiconductor device


A semiconductor device capable of retaining data for a long time is provided. The semiconductor device includes first to third transistors, a fourth transistor including first and second gates, first to third nodes, a capacitor, and an input terminal.
Semiconductor Energy Laboratory Co., Ltd.


01/28/16
20160027789 

Dummy gate structure for electrical isolation of a fin dram


Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy.
International Business Machines Corporation


01/28/16
20160027788 

Dynamic random access memory cell with self-aligned strap


After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures.
International Business Machines Corporation


01/28/16
20160027781 

Iii-v layers for n-type and p-type mos source-drain contacts


Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of mos transistors of a cmos device, where an intermediate iii-v semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance.
Intel Corporation


01/28/16
20160027776 

Densely spaced fins for semiconductor fin field effect transistors


A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.. .
International Business Machines Corporation


01/28/16
20160027664 

Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme


A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer.
International Business Machines Corporation


01/28/16
20160027514 

Nonvolatile memory device and programming method thereof


According to example embodiments, a nonvolatile memory device includes a plurality of cell strings on a horizontal semiconductor layer. Each of the cell strings including a plurality of memory cells stacked in a direction perpendicular to the horizontal semiconductor layer.

01/28/16
20160027506 

Resistive memory device capable of increasing sensing margin by controlling interface states of cell transistors


Memory systems can include a memory device having an array of nonvolatile memory cells therein, which is electrically coupled to a plurality of bit lines and a plurality of word lines. The nonvolatile memory cells may include respective nonvolatile resistive devices electrically coupled in series with corresponding cell transistors.

01/28/16
20160026749 

Integrated circuit layout design system and method


A method of generating a photo mask for use during fabrication of a semiconductor device includes; generating an initial layout design including critical circuit paths and non-critical circuit paths by shielding all gate line patterns used to implement transistors in the critical circuits and non-critical circuits, and thereafter generating a layout design from the initial layout design by selectively un-shielding a non-critical gate line pattern among the gate line patterns used to implement a gate of a non-critical transistor in a non-critical circuit, while retaining the shielding of all critical gate line patterns among the gate line patterns.. .

01/28/16
20160026207 

Power up body bias circuits and methods


An integrated circuit device can include at least a first body bias circuit configured to generate a first body bias voltage different from power supply voltages of the ic device; at least a first bias control circuit configured to set a first body bias node to a first power supply voltage, and subsequently enabling the first body bias node to be set to the first body bias voltage; and a plurality of first transistors having bodies connected to the first body bias node.. .
Mie Fujitsu Semiconductor Limited


01/28/16
20160025802 

Systems and methods for test circuitry for insulated-gate bipolar transistors


A driver circuit for testing a saturation level in an insulated gate bipolar transistor (“igbt”) includes a comparator having a first input coupled to a reference voltage and a second input coupled to a saturation test node, and a first transistor having a first current electrode coupled to the first input of the comparator, a second current electrode coupled to a supply voltage, and a control electrode coupled to a first output of a test circuit. The first output is associated with a test initiation function of an internal test process.

01/28/16
20160025800 

Systems and methods for test circuitry for insulated-gate bipolar transistors


A saturation edge detection circuit for testing a saturation level in an insulated gate bipolar transistor (“igbt”) includes a first input operable to receive an on signal, a second input coupled to an igbt driver circuit, and an output coupled to a control electrode of the igbt. The output indicates a change in a state of a saturation voltage associated with the igbt during operation of the igbt..

01/28/16
20160025675 

Method for electronic biological sample analysis


A biological sample analysis device includes a casing that encloses a biological sample delivery system hydraulically coupled to a sensor, wherein the sensor includes a plurality of graphene transistors and each transistor covalently bonds with a biomarker causing the electrical properties of the transistor to measurably change when the biomarker is exposed to corresponding antibodies within an infected biological sample.. .
Nanomedical Diagnostics, Inc.


01/21/16
20160021767 

Ferroelectric nanoshell devices


Disclosed herein are nanoscale devices comprising one or more ferroelectric nanoshells characterized as having an extreme curvature in at least one spatial dimension. Also disclosed are ferroelectric field effect transistors and metal ferroelectric metal capacitors comprising one or more ferroelectric nanoshells.
Drexel University


01/21/16
20160020780 

Method and system for a low input voltage low impedance termination stage for current inputs


A low input voltage low impedance termination stage for current inputs is disclosed and may include an output stage for an electrical circuit, the output stage including input cascode transistors and stacked output transistors, wherein a source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source. A current source may be coupled to the drain of the first of the input cascode transistors.
Maxlinear, Inc.


01/21/16
20160020768 

Digital circuits having improved transistors, and methods therefor


Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
Mie Fujitsu Semiconductor Limited


01/21/16
20160020767 

High speed complementary nmos lut logic


A programmable logic is provided that uses only nmos pass transistors to pass a true output signal to an internal true node and to pass a complement output signal to an internal complement node. The internal true and complement nodes are cross-coupled through pmos transistors so that the discharge of one of the internal true and complement nodes switches on a corresponding one of the cross-coupled pmos transistors to charge a remaining one of the internal true and complement nodes..
Lattice Semiconductor Corporation


01/21/16
20160020761 

Transmission circuit with leakage prevention circuit


A transmission circuit includes: a first transistor, having a source terminal coupled to a first reference voltage terminal of the transmission circuit and a drain terminal coupled to a first output terminal of the transmission circuit; a second transistor, having a source terminal coupled to a gate of the first transistor, and a drain terminal coupled to the first output terminal of the transmission circuit; and a third transistor, having a drain terminal coupled to the first output terminal of the transmission, a source terminal coupled to a second reference voltage terminal of the transmission, and a gate terminal for receiving a first input signal; wherein the first and second transistors are of a first conducting type, and the third transistor is of a second conducting type different from the first conducting type.. .
Realtek Semiconductor Corp.


01/21/16
20160020740 

Wideband low-power amplifier


An amplifier is provided that includes a differential pair of transistors configured to steer a tail current responsive to a differential input voltage. The amplifier also includes a transconductor that tranconducts high-frequency changes in the differential output voltage into a differential bias current conducted through the differential pair of transistors..
Qualcomm Incorporated


01/21/16
20160020698 

Voltage regulators with kickback protection


The subject matter of this document can be embodied in a method that includes a voltage regulator having an input terminal and an output terminal. The voltage regulator includes a high-side transistor between the input terminal and an intermediate terminal, and a low-side transistor between the intermediate terminal and ground.
Volterra Semiconductor Llc


01/21/16
20160020413 

Electronic devices using organic small molecule semiconducting compounds


Small organic molecule semi-conducting chromophores containing a halogen-substituted core structure are disclosed. Such compounds can be used in organic heterojunction devices, such as organic small molecule solar cells and transistors..
Next Energy Technologies Inc.


01/21/16
20160020335 

Transistors comprising doped region-gap-doped region structures and methods of fabrication


Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (feol) processing.
International Business Machines Corporation


01/21/16
20160020316 

Semiconductor device


A semiconductor device 100 includes a plurality of vertical transistors 50 provided to stand from a silicon substrate 1 and having a pillar lower diffusion layer 9 at their end portions on the silicon substrate 1 side, a metal contact plug 31 provided to stand from the silicon substrate 1 and connected to the pillar lower diffusion layer 9 of the plurality of vertical transistors 50, the plurality of vertical transistors 50 are uniformly arranged around the metal contact plug 31 and share the pillar lower diffusion layer 9 and the metal contact plug 31.. .
Ps4 Luxco S.a.r.l.


01/21/16
20160020304 

Interlayer dielectric for non-planar transistors


The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor..
Intel Corporaton


01/21/16
20160020284 

Reusable nitride wafer, making, and use thereof


Techniques for processing materials for manufacture of gallium-containing nitride substrates are disclosed. More specifically, techniques for fabricating and reusing large area substrates using a combination of processing techniques are disclosed.
Soraa, Inc.


01/21/16
20160020264 

Display device


Discussed is a display device, that may include a substrate divided into a display area and a non-display area except the display area, a first light shielding film formed in the display area, a second light shielding film formed in the non-display area, and oxide thin film transistors and organic light emitting diodes, which are formed on the first light shielding film, wherein the first light shielding film and the second light shielding film are spaced apart from each other.. .
Lg Display Co., Ltd.


01/21/16
20160020259 

Electroluminescent device and its manufacture method


An electroluminescent device and its manufacture method are disclosed. The electroluminescent device comprises a color film substrate (20) comprising a substrate (21) and a color filter layer, a boss layer (27), a first electrode (24), an organic electroluminescence layer (25) and a second electrode (26) disposed on the substrate (21); said color filter layer comprises a black matrix (221) and color blocks (222) separated by the black matrix (221); said boss layer (27) is disposed between said color filter layer and said first electrode (24), and the boss layer located above the color blocks (222) protrudes towards the side away from the substrate (21) to form a boss (271); said first electrode (24), said organic electroluminescence layer (25) and said second electrode (26) are disposed on the boss layer (27) orderly, and the second electrode (26) is located above said boss (271).
Boe Technology Group Co., Ltd.


01/21/16
20160020253 

Embedded non-volatile memory


The present invention is a method of incorporating a non-volatile memory into a cmos process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard cmos process (i) after the mos transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the mos transistors) and (ii) before the salicided contacts to those mos transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide).
Hgst, Inc.


01/21/16
20160020229 

Array substrate and fabricating the same, and display device


The present invention provides an array substrate comprising a plurality of data lines, a plurality of gate lines and a plurality of oxide thin film transistors, the plurality of data lines and the plurality of gate lines intersect with each other in different planes to divide the array substrate into a plurality of pixel units, in each of which the oxide thin film transistor is provided, the array substrate further comprises a metal oxide layer provided at least below a portion of the data line overlapping with the gate line, and an upper surface of the metal oxide layer is in contact with a lower surface of the data line. The present invention further provides a method for fabricating the array substrate and a display device comprising the array substrate..
Hefei Boe Optoelectronics Technology Co., Ltd.


01/21/16
20160020225 

Nonvolatile semiconductor memory device


A nonvolatile semiconductor memory device includes a plurality of memory strings including a plurality of memory transistors connected in series and a selection transistor disposed on either end of the plurality of memory transistors, which together form a memory cell. The memory transistors and the selection transistors each include a polysilicon layer formed on an insulating film as a channel region thereof.
Kabushiki Kaisha Toshiba


01/21/16
20160020217 

Semiconductor device


A semiconductor device includes a first vertical memory string connected to a common source line, a second vertical memory string connected to a bit line, a pipe transistor suitable for selectively connecting the first and second vertical memory strings based on a block selection signal, and a plurality of transistors suitable for selectively connecting local lines of the first and second vertical memory strings to corresponding global lines based on the block selection signal.. .
Sk Hynix Inc.


01/21/16
20160020213 

Methods of forming positioned landing pads and semiconductor devices including the same


A method of forming a dram can include forming a plurality of transistors arranged in a first direction on a substrate and forming a bit line structure that extends in the first direction, where the bit line structure being electrically coupled to the plurality of transistors at respective locations in the first direction. A plurality of first landing pads an be formed at alternating ones of the respective locations having a first position in a second direction on the substrate.
Samsung Electronics Co., Ltd.


01/21/16
20160020206 

Semiconductor device including a vertical gate-all-around transistor and a planar transistor


A semiconductor device includes a first transistor and a second transistor. Each of the first and second transistors includes a channel.
Taiwan Semiconductor Manufacturing Company Limited


01/21/16
20160020095 

Metal-induced crystallization of amorphous silicon in an oxidizing atmosphere


Techniques are provided for forming thin film transistors having a polycrystalline silicon active layer formed by metal-induced crystallization (mic) of amorphous silicon in an oxidizing atmosphere. In an aspect, a transistor device, is provided that includes a source region and a drain region formed on a substrate, and an active channel region formed on the substrate and electrically connecting the source region and the drain region.
The Hong Kong University Of Science And Technology


01/21/16
20160019973 

3d stacked memory array and determining threshold voltages of string selection transistors


This invention provides 3d stacked memory arrays and methods for determining threshold voltages of string selection transistors by lsmp (layer selection by multi-level permutation) for enabling to select layers regardless of the number or as many as possible by the limited numbers of threshold voltage states and ssls. Thus, this invention enables to maximize the degree of integrity of memory by minimizing the number of ssls and to select layers with no limitation of the number by considering a recent aspect ratio of the semiconductor etching process..
Seoul National University R&db Foundation


01/21/16
20160019938 

Latch circuit and semiconductor device including the same


A latch circuit includes: first to nth storage nodes where n is an even number equal to or more than four; and first to nth pairs of transistors, each of which comprises a pmos transistor and an nmos transistor coupled in series with each other through a corresponding node among the first to nth storage nodes. The pmos transistor is coupled to one of the storage nodes included in previous one of the pairs of transistors at a gate of the pmos transistor.
Sk Hynix Inc.


01/21/16
20160018935 

Array substrate and manufacturing method thereof, and touch display device


Embodiments of the present invention provide an array substrate and a manufacturing method thereof and a touch display device. The array substrate comprises multiple data lines, multiple gate lines and multiple thin film transistors.
Ordos Yuansheng Optoelectronics Co., Ltd.


01/21/16
20160018446 

Gate drive under-voltage detection


Gate drive faults are detected for an inverter which comprises a phase switch having an insulated gate, such as an igbt. A complementary transistor pair is adapted to receive a supply voltage and a pulse-width modulated (pwm) signal to alternately charge and discharge the insulated gate.
Ford Global Technologies, Llc


01/14/16
20160014363 

Solid-state imaging device and imaging apparatus


A solid-state imaging device includes: a plurality of unit cells each including at least one light receiving unit and an amplifying transistor which outputs an amplified signal corresponding to an amount of the signal charge photoelectrically converted by the light receiving unit; a plurality of vertical signal lines each for receiving an output signal from the amplifying transistor; a pixel power supply line for supplying a power supply voltage to the amplifying transistor; a plurality of constant current source transistors each connected to a different one of the vertical signal lines; and a bias circuit which controls an amount of current to be supplied to each of the constant current source transistors, based on a variation in the power supply voltage.. .
Panasonic Intellectual Property Management Co., Ltd.


01/14/16
20160014304 

Solid-state imaging device


A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell (30) includes two pixels (31) and (32).
Sony Corporation


01/14/16
20160013787 

Fully capacitive coupled input choppers


A method of differential signal transfer from a differential input vinp and vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having first through fourth chopper transistors, each having a source, a drain and a gate, the input chopper having vinp and vinn as a differential input, providing an output chopper, capacitively coupling a differential output voutp and voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed..
Maxim Integrated Products, Inc.


01/14/16
20160013776 

Level shift driver circuit capable of reducing gate-induced drain leakage current


A level shift driver circuit comprises a level shift circuit and a driver circuit. The driver circuit comprises a first and a second p-type transistors and a first and a second n-type transistors coupled in series.
Ememory Technology Inc.


01/14/16
20160013768 

Method and class ab audio amplifier output stage voltage protection


An output circuit for a class ab push-pull amplifier includes an upper cascode output stage and a lower cascode output stage. The upper cascode stage includes first and second pmos transistors connected in series between a positive power supply node and an output node, the first pmos transistor configured to receive a first complementary input signal.
Nuvoton Technology Corporation


01/14/16
20160013722 

Device for avoiding hard switching in resonant converter and related method


A control device controls a switching circuit for a converter. The switching circuit comprises a half-bridge having a high-side transistor and a low-side transistor.
Stmicroelectronics S.r.l.


01/14/16
20160013718 

Voltage boost circuit


A voltage boost circuit for edram using thin oxide field effect transistors (fets) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide fet during a pump phase.
International Business Machines Corporation


01/14/16
20160013409 

Radiation source and the operation thereof


The invention relates to a radiation source, comprising at least one semiconductor substrate, on which at least two field-effect transistors are formed, which each contain a gate electrode, a source contact, and a drain contact, which bound a channel, wherein the at least two field-effect transistors are arranged adjacent to each other on the substrate, wherein each field-effect transistor has exactly one gate electrode and at least one source contact and/or at least one drain contact is arranged between two adjacent gate electrodes, wherein a ballistic electron transport can be formed in the channel during operation of the radiation source. The invention further relates to a method for producing electromagnetic radiation having a vacuum wavelength between approximately 10 μm and approximately 1 mm..
Fraunhofer Gesellschaft Zur FÖrderung Der Angew. Forschung E.v.


01/14/16
20160013297 

Raised epitaxial ldd in mugfets and methods for forming the same


Embodiments include multiple gate field-effect transistors (mugfets) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (ldd) region.
Taiwan Semiconductor Manufacturing Company, Ltd.


01/14/16
20160013265 

Semiconductor device with field threshold mosfet for high voltage termination


This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality p-channel mosfets.

01/14/16
20160013264 

Electro-optical device, electronic apparatus, and drive circuit


There are provided an electro-optical device that includes a peripheral circuit which is resistant against static electricity and an electronic apparatus that includes the electro-optical device. A liquid crystal device that is used as an electro-optical device includes a pixel circuit, and a peripheral circuit that drives and controls the pixel circuit, and a data line drive circuit 101 that is used as the peripheral circuit includes resistors rs that are added in series to gates, sources, and drains of transistors 121, 123, 125, and 127 which are included in a first stage circuit and a final stage circuit of the data line drive circuit 101..
Seiko Epson Corporation


01/14/16
20160013260 

Organic light emitting display devices and methods of manufacturing organic light emitting display devices


An organic light emitting display device includes a substrate including a plurality of pixel regions and a plurality of transparent regions, thin film transistors disposed in the pixel regions, an insulation layer disposed on the thin film transistors, first electrodes electrically contacting the thin film transistors, a pixel defining layer including a black material disposed on the first electrodes, organic light emitting structures disposed on the pixel defining layer, and a second electrode disposed on the organic light emitting structures. The pixel defining layer may define an asymmetrical configuration of adjacent transparent regions disposed on opposing sides of corresponding pixel regions..
Samsung Display Co., Ltd.


01/14/16
20160013239 

Semiconductor device and manufacturing method therefor


Disclosed are a semiconductor device and a method for manufacturing the semiconductor device that is capable of adequately reducing the influence of inter-wiring capacitance even when a photoelectric conversion element is progressively miniaturized. A plurality of transfer transistors each include a photoelectric conversion element and a signal output section.
Renesas Electronics Corporation


01/14/16
20160013238 

Cmos image sensor


A cmos image sensor including a pixel including: a photodiode in series with a mos transistor between a first reference potential and a sense node; a mos transistor connecting the sense node to a second reference potential; and a third mos transistor assembled as a source follower between the sense node and a read circuit, wherein the oxide thickness of the third transistor is smaller than that of the first and second transistors, the voltage difference between the first and second reference potentials is greater than the maximum voltage capable of being applied between two terminals of the third transistor, and the body or drain region of the third transistor is connected to a third reference potential in the range between the first and second potentials.. .
Commissariat A I'energie Atomique Et Aux Energies Alternatives


01/14/16
20160013206 

Low leakage dual sti integrated circuit including fdsoi transistors


An integrated circuit, including: a utbox layer; a first cell, including: fdsoi transistors; a first sti separating the transistors; a first ground plane located beneath one of the transistors and beneath the utbox layer; a first well; a second cell, including: fdsoi transistors; a second sti separating the transistors; a second ground plane located beneath one of the transistors and beneath the utbox layer; a second well; a third sti separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third sti whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second stis.. .
Stmicroelectronics, Inc.


01/14/16
20160013205 

Dual sti integrated circuit including fdsoi transistors and manufacturing the same


An integrated circuit, including: a first cell, including: fdsoi transistors; a utbox layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first sti separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first sti; a second cell including a second well; a second sti separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.. .
Stmicroelectronics, Inc.


01/14/16
20160013179 

Semiconductor device


Reduction of the speed of switching between the drain electrodes of transistors and the cathode electrodes of diodes due to the inductances of lines coupling them is inhibited. Transistors and diodes are formed over a substrate.
Renesas Electronics Corporation


01/14/16
20160013106 

Non-planar transistors with replacement fins and methods of forming the same


A method includes forming a first semiconductor fin, and oxidizing surface portions of the first semiconductor fin to form a first oxide layer. The first oxide layer includes a top portion overlapping the first semiconductor fin and sidewall portions on sidewalls of the first semiconductor fin.
Taiwan Semiconductor Manufacturing Company, Ltd.




Transistors topics: Transistors, Semiconductor, Semiconductor Device, Integrated Circuit, High Speed, Photodiode, Memory Effect, Silicon Nitride, Enhancement, Ion Implant, Ion Channel, Interrupted, Reference Voltage, Semiconductor Devices, Semiconductor Substrate

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