|| List of recent Transistors-related patents
| Standard cells having transistors annotated for gate-length biasing|
Methods, layouts and chip design layouts that use annotations for communicating gate-length biasing amounts to post-layout tools are disclosed. One method includes receiving a chip design layout designed to includes select ones of a plurality of nominal cell layouts and an annotated cell layout.
| Method for manufacturing semiconductor device|
Electrical characteristics of transistors using an oxide semiconductor are greatly varied in a substrate, between substrates, and between lots, and the electrical characteristics are changed due to heat, bias, light, or the like in some cases. In view of the above, a semiconductor device using an oxide semiconductor with high reliability and small variation in electrical characteristics is manufactured.
| Solid-state imaging device, method of manufacturing same, and electronic apparatus|
A solid-state imaging device includes a plurality of photoelectric conversion units configured to receive light and generate signal charge, the plurality of photoelectric conversion units being provided in such a manner as to correspond to a plurality of pixels in a pixel area of a semiconductor substrate; and pixel transistors configured to output the signal charge generated by the photoelectric conversion units as electrical signals. Each of the pixel transistors includes at least a transfer transistor that transfers the signal charge generated in the photoelectric conversion unit to a floating diffusion corresponding to a drain.
| Sub-block disabling in 3d memory|
Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells.
| Memory system and memory access method|
Systems and methods of sequentially accessing memory cells in a nonvolatile memory device (nvm) are provided. The nvm has a plurality of strings and a common signal line coupled to the plurality of strings.
| Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors|
Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., nand-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines..
| Semiconductor memory device|
A semiconductor memory device comprises a memory string including first and second selection transistors, and first and second groups of memory cell transistors connected in series between the first and second selection transistors; a bit line and a source line respectively connected to the first and second selection transistors; first word lines respectively connected to gates of the memory cell transistors in the first group; second word lines respectively connected to gates of the memory cell transistors in the second group; first transfer transistors respectively connected to the first word lines; second transfer transistors respectively connected to the second word lines; and a control unit configured to apply a first control voltage to gates of the first transfer transistors and a second control voltage lower than the first control voltage to gates of the second transfer transistors when data is being written to memory cell transistors in the first group.. .
| Nonvolatile semiconductor memory device|
A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array having a plurality of memory cell transistors connected in series therein; a plurality of bit lines; and a control circuit for executing a read operation. The control circuit is configured capable of executing the read operation, the read operation charging the bit line and applying a read voltage to the control gate electrode of the memory cell transistor to determine whether the memory cell transistor is conductive and the bit line discharges or not.
| Semiconductor device and electronic device|
To provide a semiconductor device with such a new structure that the effect of variation in transistor characteristics can be reduced to achieve less variation in the output voltage of a memory cell. A memory cell includes a source follower (common drain) transistor for reading data held in a gate.
| Semiconductor memory device|
A memory cell array comprises first wiring lines, second wiring lines, and memory cells disposed at intersections thereof. A control circuit comprises a first power-supply line supplying a first voltage to selected ones of the first or second wiring lines, and first selection circuits connected between the first or second wiring lines and the first power-supply line, each first selection circuit comprising first and second transistors connected in series.
| Two-bit read-only memory cell|
A read-only memory (rom) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are connected to a first word line, and the gates of the second and fourth transistors are connected to a second word line.
| Semiconductor device|
A semiconductor device capable of maintaining data even after instantaneous power reduction or interruption. The semiconductor device includes first to sixth transistors.
| Semiconductor device|
A semiconductor device capable of maintaining data during instantaneous power reduction or interruption. The semiconductor device includes first to sixth transistors.
| Display device and electronic device|
Transistors each include a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer over the gate insulating layer, and a source electrode and a drain electrode over the oxide semiconductor layer. A driver circuit portion includes first to third wirings formed in the same step as the gate electrode, fourth to sixth wirings formed in the same step as the source electrode and the drain electrode, a seventh wiring formed in the same step as a pixel electrode, a first region where the second wiring intersects with the fifth wiring, and a second region where the third wiring intersects with the sixth wiring.
| Stereoscopic image display and method of manufacturing the same|
The present invention has been made in an effort to provide a stereoscopic image display comprising: a liquid crystal panel comprising a lower substrate and an upper substrate; rgb color filters positioned on a first surface of the upper substrate; thin film transistors positioned on a first surface of the lower substrate; a black matrix positioned on a second surface of the upper substrate; and a patterned retarder film for separating an image displayed on the liquid crystal panel, wherein at least one of the rgb color filters has a dummy part overlapping at least a portion of one or both of the other color filters.. .
| Amplifier stage|
A differential amplifier stage may include: a first transistor having a gate terminal; a second transistor having a gate terminal; and a voltage limiting circuit coupled to the gate terminals of the first and second transistors, wherein the voltage limiting circuit limits a gate voltage supplied to at least one of the gate terminals of the first and second transistors.. .
| High voltage switching circuits|
The preferred embodiments of the present invention use low voltage transistors to support high voltage switching circuits by connecting low voltage circuits in a stacking configuration. High voltage switching signals are divided into a plurality of small amplitude switching signals before sending into transformers, filters or other circuits.
| Vertical insulated-gate turn-off device having a planar gate|
An insulated gate turn-off (igto) device has a layered structure including a p+ layer (e.g., a substrate), an n-type layer, a p-type layer (which may be a p-well), n+ regions formed in the surface of the p-type layer, and insulated planar gates over the p-type layer between the n+ regions. The layered structure forms vertical npn and pnp transistors.
| Lateral insulated gate turn-off devices|
A lateral insulated gate turn-off (igto) device includes an n-type layer, a p-well formed in the n-type layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, at least one trenched gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, and an anode electrode electrically contacting the p+ type anode region. The structure forms a lateral structure of npn and pnp transistors, where the well forms the base of the npn transistor.
| Configurable time delays for equalizing pulse width modulation timing|
A plurality of pwm generators have user configurable time delay circuits for each pwm control signal generated therefrom. The time delay circuits are adjusted so that each of the pwm control signals arrive at their associated power transistors at the same time.
| Current mode logic latch|
A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor.
| Pre-charge circuit with reduced process dependence|
A pre-charging circuit, such as can be used to pre-charge a data bus, is presented that is largely process independent. A push-pull type of arrangement is used, where the output of the pre-charge circuit is initially connected to a supply level through one transistor, then connect to ground by another transistor.
| Pixel circuit, display device, and inspection method|
Checking failures in transistors including driving transistors, switching transistors, and sampling transistors before light emitting elements are formed in a display device. I-v characteristics including threshold voltage of the driving transistor 10c in one pixel circuit can be detected.
| Low dropout regulator|
A low dropout regulator comprises an output transistor (mpout) with a controlled section coupled between a first supply terminal (vs) and an output terminal (out), and a differential amplifier that comprises a feedback input (vfb) coupled to the output terminal (out), a reference input (vr) for receiving a reference voltage, an output (dout) connected to a control terminal of the output transistor (mpout), and at least one pair of input transistors (m1, m2, m1a, m2a, m1b, m2b). The input transistors (m1, m2, m1a, m2a, m1b, m2b) of each pair are commonly connected to a tail current source (iab, ia, ib) of the respective pair.
| Stress memorization in rmg finfets|
Transistors with memorized stress and methods for making such transistors. The methods include forming a transistor structure having a channel region, a source and drain region, and a gate dielectric; depositing a stressor over the channel region of the transistor structure, wherein the stressor provides a stress to the channel region; removing the stressor metal after the stress is memorized within the channel region; and depositing a work function metal over the channel region of the transistor structure, where the work function metal applies less stress to the channel region than the stress applied by the stressor.
| Power electronic device|
A device includes a first and second transistors integrated in first and second chips. Each chip has opposed rear and front surfaces, and further has a first conduction terminal and a control terminal on the front surface and a second conduction terminal on the rear surface.
| Semi conductor device having elevated source and drain|
Semiconductor layers on active areas for transistors in a memory cell region (region a) and a peripheral circuit region (region b) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region a do not come into contact with each other. Only semiconductor layer (10) in region b is also grown from the surface of a substrate which is exposed when only the surface of sti (2) in region b is drawn back, so that a facet (f) of the semiconductor layer 10 is formed outside the active area, followed by ion-implantation to form a high density diffusion layer (11) in region b.
| Embedded sonos based memory cells|
Memory cells including embedded sonos based non-volatile memory (nvm) and mos transistors and methods of forming the same are described. Generally, the method includes: forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric on the substrate and a charge-trapping layer on the tunneling dielectric; patterning the dielectric stack to form a gate stack of a nvm transistor of a memory device in a first region of the substrate while concurrently removing the dielectric stack from a second region of the substrate; and performing a gate oxidation process of a baseline cmos process flow to thermally grow a gate oxide of a mos transistor overlying the substrate in the second region while concurrently growing a blocking oxide overlying the charge-trapping layer.
| Field effect transistor with self-adjusting threshold voltage|
Methods for forming field effect transistors (fets) with improved on/off current ratios in addition to short charging times and the resulting devices are disclosed. Embodiments include forming a gate oxide layer above a channel region in a substrate, forming a partial self-adjusting threshold voltage layer above a drain-side end of the gate oxide layer, and forming a gate above the partial self-adjusting threshold voltage layer and the gate oxide layer..
| Fin field-effect transistors and fabrication method thereof|
A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate; and forming a plurality of fins on top of the semiconductor substrate.
| Methods of forming oxide thin film and electrical devices and thin film transistors using the methods|
Provided are a method of forming an oxide thin film and an electrical device and thin film transistor using the method. The method includes forming an oxide thin film on a substrate by applying a precursor solution; and performing a thermal treatment process on the substrate under a pressurized atmosphere using a gas at about 100° c.
| Metal-oxide semiconductor thin film transistors and methods of manufacturing the same|
According to example embodiments a tft includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a channel layer on the gate insulating layer, the channel layer including an indium-rich metal-oxide layer; a first electrode on one end of the channel layer; a second electrode on the other end of the channel layer; and a passivation layer on the channel layer between the first and second electrodes.. .
| Graphene heterostructure field effect transistors|
A field effect transistor includes a substrate, a first graphene (gr) layer on the substrate, a second graphene (gr) layer on the substrate, a fluorographene (grf) layer on the substrate and between the first and second graphene layers, a first ohmic contact on the first graphene layer, a second ohmic contact on the second graphene layer, a gate aligned over the fluorographene layer, and a gate dielectric between the gate and the fluorographene layer and between the gate and the first and second ohmic contacts.. .
| Integrated circuit devices and fabricating method thereof|
An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current.
| Generation of multiple diameter nanowire field effect transistors|
A system is provided and includes a wafer and a mask. The wafer includes a silicon-on-insulator (soi) structure disposed on a buried oxide (box) layer and has a first region with a first soi thickness and a second region with a second soi thickness, the first and second soi thicknesses being different from one another and sufficiently large such that respective pairs of soi pads connected via respective nanowires with different thicknesses are formable therein.
| High dynamic range pixel having a plurality of amplifier transistors|
A pixel cell for use in a high dynamic range image sensor includes a photodiode disposed in semiconductor material to accumulate charge in response to light incident upon the photodiode. A transfer transistor is disposed in the semiconductor material and is coupled between a floating diffusion and the photodiode.
| Image sensor with pixel units having mirrored transistor layout|
An image sensor includes a first pixel unit horizontally adjacent to a second pixel unit. Each pixel unit includes plurality of photodiodes and a shared floating diffusion region.
|Process for the preparation of polymers containing benzohetero [1,3] diazole units|
Process for the preparation of a polymer containing benzohetero[1,3]diazole. Units which comprises reacting at least one disubstituted benzohetero[1,3]diazole compound with at least one heteroaryl compound.
|Methodology and apparatus for tuning driving current of semiconductor transistors|
A method and apparatus for repairing transistors may include applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time. In this manner the transistor structure may be repaired or returned to operate at or near the original operating characteristics..
|Rolled-up, three-dimensional field-effect transistors and the use thereof in electronics, sensors and microfluidics|
Field-effect transistors include at least two thin layers of a semiconductor material and of an electrically conductive gate material that are rolled up together. These two layers are arranged separated from one another by one or multiple barrier layers and this rolled-up multi-layer structure is integratable as field-effect transistors in circuits and/or in microfluid systems as sensors for the detection of fluids..
|Amplifier for electrostatic transducers|
A class d audio amplifier which provides both an alternating signal and a dc bias voltage to an electrostatic transducer (9). The amplifier comprises an input module (1) for generating a modulated sequence of pulses in response to an input audio signal, and an output module (3) for amplifying the sequence of pulses, which includes high speed switching output transistors (4, 5).
|Row decoding circuit|
A row decoding circuit including row decoding blocks is provided. Each of the row decoding blocks includes row decoders.
|Nonvolatile semiconductor memory device|
A control circuit is configured to, during an erase operation, set a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage. The control circuit is configured to, during the erase operation, set a voltage difference between a voltage of a first line connected to an unselected cell unit and a voltage of a gate of a first transistor included in the unselected cell unit to a second voltage, the second voltage differing from the first voltage.
|Word-line driver for memory|
A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line.
|Nonvolatile semiconductor memory device|
A nonvolatile semiconductor memory device includes a memory cell, a bit line electrically connected to the memory cell, a sense amplifier that includes a first transistor having a first end electrically connected to the bit line, a second transistor electrically connected between a second end of the first transistor and ground, a third transistor electrically connected between a second end of the first transistor and a source line, and a controller configured to control the first, second, and third transistors after performing a program operation. After the program operation, the first and second transistors are turned on and then while the first transistor remains turned on, the second transistor is turned off and the third transistor is turned on..
|Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate|
A one-time programmable (otp) memory cell includes a dual date transistor and, in some embodiments, two transistors. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device.
|3d stacked nand flash memory array having ssl status check buildings for monitoring threshold voltages of string selection transistors and methods for monitoring and operating the same|
Disclosed is a 3d stacked nand flash memory array having ssl status check buildings for monitoring threshold voltages of string selection transistors, a monitoring method of threshold voltages of string selection transistors by the ssl status check buildings, and an operating method thereof.. .
|Flash memory device reducing layout area|
A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of select connection portions corresponding thereto are disposed in one common active region.
|Nonvolatile semiconductor memory|
A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.. .
|Integrated gate driver circuit and liquid crystal panel|
An integrated gate driver circuit includes a control circuit, a plurality of drive stages and a plurality of discharge transistors. The control circuit is configured to output a plurality of clock signals within a frame period and to output a discharge enabling signal within a blanking period of the frame period.
|Display circuitry with reduced pixel parasitic capacitor coupling|
A touch screen display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (tft) layer.
|Solid-state imaging device, manufacturing method thereof, and electronic apparatus|
A solid-state imaging device having a backside illuminated structure, includes: a pixel region in which pixels each having a photoelectric conversion portion and a plurality of pixel transistors are arranged in a two-dimensional matrix; an element isolation region isolating the pixels which is provided in the pixel region and which includes a semiconductor layer provided in a trench by an epitaxial growth; and a light receiving surface at a rear surface side of a semiconductor substrate which is opposite to a multilayer wiring layer.. .
|Scanner, electro-optical panel, electro-optical display device and electronic apparatus|
A scanner includes a plurality of unit circuits configured with transistors of a same conductivity type. In the scanner, the unit circuit constituting the scanner includes an output transistor that selectively outputs, to an output terminal of the unit circuit, a signal given from an outside.
|Display panel source line driving circuitry|
An electronic display system has a light transmissive panel, a region of display elements on the panel, and source lines coupled to the display elements. A demultiplexor circuit has multiple groups of pass gates.
|Compensation technique for luminance degradation in electro-luminance devices|
A method and system for compensation for luminance degradation in electro-luminance devices is provided. The system includes a pixel circuit having a light emitting device, a storage capacitor, a plurality of transistors, and control signal lines to operate the pixel circuit.
|Voltage generator, switch and data converter circuits|
A data converter can include a resistor network, a switch network connected to the resistor network and having a plurality of switch circuits, each with an nmos and a pmos switch transistor, and a voltage generator to generate a drive voltage for driving a gate of at least one of the nmos or pmos switch transistors of at least one of the switch circuits. The voltage generator can include first and second pairs of transistors, each pair having connected control terminals and being connected to a second nmos or pmos transistor, a first or second resistor, and the other pair of transistors.
|Power amplifier using differential structure|
Provided is a power amplifier which includes: a first transistor and a second transistor each having a first end connected to a first power source supplying a first voltage and to which signals having a same size but opposite polarities are input; a third transistor and a fourth transistor having first ends respectively connected to the first ends of the first transistor and the second transistor; and a fifth transistor having a first end connected to second ends of the third and fourth transistors and controlling oscillation of the third or fourth transistor.. .
A semiconductor device includes a first semiconductor chip which includes a first power supply terminal and into which a circuit block which is operated by a power supply voltage supplied to the first power supply terminal is integrated, a power circuit that includes switching transistors and supplies the power supply voltage to the first power supply terminal, and a dcdc control unit that is formed on the first semiconductor chip and generates a control signal for controlling the turning on and off of the switching transistors in response to an information signal from the circuit block and a voltage information signal corresponding to an output voltage from the power circuit.. .
|Circuit element including a layer of a stress-creating material providing a variable stress and method for the formation thereof|
A transistor includes a source region, a drain region, a channel region, a gate electrode and a layer of a stress-creating material. The stress-creating material provides a stress that is variable in response to a signal acting on the stress-creating material.
|Light emitting diode driver|
A driver circuit for driving light emitting diodes (leds). The driver circuit includes: a string of leds divided into n groups, the n groups of leds being electrically connected to each other in series, a downstream end of group m−1 being electrically connected to the upstream end of group m, where m is a positive number equal to or less than n.
The present invention generally relates to powering a switching controller of a switch mode power converter (smpc), and more particularly to a method of providing power to a switching controller of a smpc, to a charging circuit for supplying charge to a charge store for providing power to a switching controller of a smpc, and to an smpc comprising such a circuit. A method of providing power to a switching controller of a switch mode power converter (smpc), the smpc having: an inductive component having a winding coupled to receive power from an input to said smpc; a switching circuit comprising first and second switching transistors, said first transistor coupled in series between said winding and said second transistor; a switching controller to control switching of said second transistor; and a charge store to provide power to said switching controller, the method comprising: flow of current from said winding through said first transistor; and diverting said current through a conduction path to said charge store..
|Uni-directional transient voltage suppressor (tvs)|
A unidirectional transient voltage suppressor (tvs) device includes first and second npn transistors that are connected in parallel to each other. Each npn transistor includes a collector region, an emitter.
|Methods and apparatus of metal gate transistors|
Methods and devices for forming a contact over a metal gate for a transistor are provided. The device may comprise an active area, an isolation area surrounding the active area, and a metal gate above the isolation area, wherein the metal gate comprises a conductive layer.
|Transistors with isolation regions|
A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions.
|Magneto-electric voltage controlled spin transistors|
The invention relates to a magneto-electric spin-fet including a gate film of chromia and a thin film of a conductive channel material which may be graphene, inp, gaas, gasb, pbs, mos2, ws2, mose2, wse2 and mixtures thereof. The chromia, or other magneto-electric, and conduction channel material are in intimate contact along an interface there between.
|Collector-up bipolar junction transistors in bicmos technology|
Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate.
|Collector-up bipolar junction transistors in bicmos technology|
Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate.
|Methodology for fabricating isotropically recessed source regions of cmos transistors|
A field effect transistor device includes a buried oxide layer, a silicon layer above the buried oxide layer, an isotropically recessed source region, and a gate stack comprising a gate dielectric, a conductive material, and a spacer.. .
The inventors found out that in the case of performing a low gray scale display in which a very small amount of current is supplied to a light emitting element, variations in threshold voltages of driving transistors become notable since the gate-source voltage is low. In view of this, the invention provides a display device in which variations in the threshold voltages of the driving transistors are reduced even in the low gray scale display, and a driving method thereof.
The semiconductor device of the present invention comprises first and second transistors and first and second capacitors. One of source and drain electrodes of the first transistor is electrically connected to a first wiring, the other is electrically connected to a second wiring, and a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor and one of electrodes of the first capacitor.
|Remote doping of organic thin film transistors|
Organic electronic devices comprising “remotely” doped materials comprising a combination of at least three layers. Such devices can include “remotely p-doped” structures comprising: a channel layer comprising at least one organic semiconductor channel material; a dopant layer, which comprises at least one p-dopant material and optionally at least one organic hole transport material; and a spacer layer disposed between and in electrical contact with both the channel layer and the dopant layer, comprising an organic semiconducting spacer material; or alternatively can include “remotely n-doped” structures comprising a combination of at least three layers: a channel layer comprising at least one organic semiconductor channel material; a dopant layer which comprises at least one organic electron transport material doped with an n-dopant material; and a spacer layer disposed between and in electrical contact with the channel layer and the dopant layer, comprising an organic semiconducting spacer material.
|Low-mismatch and low-consumption transimpedance gain circuit for temporally differentiating photo-sensing systems in dynamic vision sensors|
The invention relates to a low-mismatch and low-consumption transimpedance gain circuit for temporally differentiating photo-sensing systems in dynamic vision sensors, which uses at least one photodiode and at least two in-series transistors, each of the transistors being connected in diode configuration and being positioned at the output of the photodiode. The output current from the photodiode flows through the drain-source channels of the transistors and the source of the last transistor in series is connected to a voltage selected from ground voltage, a constant voltage or a controlled voltage..