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Transistors patents



      

This page is updated frequently with new Transistors-related patent applications.




Date/App# patent app List of recent Transistors-related patents
06/16/16
20160173113 
 N-path cascode transistor output switch for a digital to analog converter patent thumbnailN-path cascode transistor output switch for a digital to analog converter
Techniques are provided for a switched output digital to analog converter employing an n-path cascode output switch. An example system may include a plurality of cascode transistors coupled in parallel to an output stage of a current mode digital to analog converter (dac) circuit.
Bae Systems Information And Electronic Systems Integration Inc.


06/16/16
20160173099 
 Electronic circuits patent thumbnailElectronic circuits
An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, fets, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first fet is connected to the first supply rail, the drain of the first fet and the source of the second fet are connected to the output terminal, the drain of the second fet is connected to the second supply rail, the gate of the third fet and the gate of the fourth fet are connected to the input terminal, the drain of the third fet is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third fet, and the second load is connected between the drain of the fourth fet and the second supply rail.
Pragmatic Printing Ltd


06/16/16
20160173098 
 Fast fall and rise time current mode logic buffer patent thumbnailFast fall and rise time current mode logic buffer
A current mode logic buffer includes a differential pair of input transistors comprising a first input transistor and a second input transistor, a first output load resistor coupled in series with the first input transistor, a second output load resistor coupled in series with the second input transistor, a first output at a first node between the first output load resistor and the first input transistor, a second output at a second node between the second output load resistor and the second input transistor, a first hold capacitor configured to provide a semi-constant voltage source to the first output via a first low-resistance path, and a second hold capacitor configured to provide a semi-constant voltage source to the second output via a second low-resistance path.. .
Samsung Display Co., Ltd.


06/16/16
20160173083 
 Circuits, methods, and systems with optimized operation of double-base bipolar junction transistors patent thumbnailCircuits, methods, and systems with optimized operation of double-base bipolar junction transistors
The present application teaches, among other innovations, methods and circuits for operating a b-tran (double-base bidirectional bipolar junction transistor). A base drive circuit is described which provides high-impedance drive to the base contact region on whichever side of the device is operating as the collector (at a given moment).
Ideal Power Inc.


06/16/16
20160173065 
 Half-power buffer and/or amplifier patent thumbnailHalf-power buffer and/or amplifier
Disclosed is a half-power buffer/amplifier. The half-power buffer/amplifier includes first and second amplifying blocks respectively corresponding to first and second channels, a first output buffer unit controlled by an output from the first amplifying block, and a second output buffer unit controlled by an output from the second amplifying block.
Dongbu Hitek Co., Ltd.


06/16/16
20160173036 
 Multiple range rf amplifier patent thumbnailMultiple range rf amplifier
An amplifier includes at least two amplification stages coupled in parallel. Each amplification stage includes at differential pair of amplifying mos transistors having gates connected to a first and second input nodes common to amplifying stages, and bulk regions connected to each other but insulated from bulk regions of the amplifying mos transistors of the other amplification stages.
Stmicroelectronics Sa


06/16/16
20160172984 
 Electric power conversion system patent thumbnailElectric power conversion system
An electric power conversion circuit and a control circuit are provided. The electric power conversion circuit includes a primary conversion circuit and a secondary conversion circuit.
Toyota Jidosha Kabushiki Kaisha


06/16/16
20160172970 
 Efficient voltage conversion patent thumbnailEfficient voltage conversion
An apparatus for providing on-chip voltage-regulated power includes a switched capacitor voltage conversion circuit that receives an elevated power demand signal and operates at a base rate when the elevated power demand signal is not active and at an elevated rate when the elevated power demand signal is active. The switched capacitor voltage conversion circuit comprises an auxiliary set of transistors that are disabled, when the elevated power demand signal is not active and enabled, when the elevated power demand signal is active.
International Business Machines Corporation


06/16/16
20160172562 
 Method for forming circuit-on-wire patent thumbnailMethod for forming circuit-on-wire
A method is provided for forming a circuit-on-wire (cow) assembly. The method forms a flexible line with a plurality of periodic alignment marks used as a guide to place cow devices overlying a surface of the flexible line.
Sharp Laboratories Of America, Inc.


06/16/16
20160172387 
 Ltps array substrate patent thumbnailLtps array substrate
An ltps array substrate includes a plurality of ltps thin-film transistors and a bottom transparent conductive layer, a protective layer, and a top transparent conductive layer. Each ltps thin-film transistor includes a substrate, a patternized light shield layer, a buffering layer, a patternized poly-silicon layer, a gate insulation layer, a gate electrode line and a common electrode line, an insulation layer, a drain electrode and a source electrode, and a planarization layer that are formed to sequentially stack on each other.
Shenzhen China Star Optoelectronics Technology Co., Ltd.


06/16/16
20160172386 

Copper-alloy barrier layers for metallization in thin-film transistors and flat panel displays


In various embodiments, electronic devices such as thin-film transistors incorporate electrodes featuring a conductor layer and, disposed below the conductor layer, a barrier layer comprising an alloy of cu and one or more refractory metal elements selected from the group consisting of ta, nb, mo, w, zr, hf, re, os, ru, rh, ti, v, cr, and ni.. .

06/16/16
20160172384 

Thin film transistor substrate and display


The invention provides a thin film transistor substrate includes: a substrate; and a plurality of transistors, wherein each of the transistors includes a gate electrode disposed on the substrate; a first diffusion barrier layer disposed on the substrate and covering an upper surface and a ring sidewall of the gate electrode; a gate insulating layer disposed on the first diffusion barrier layer; an active layer disposed on the gate insulating layer and over the gate electrode; a source electrode disposed on the substrate and electrically connected to the active layer; a drain electrode disposed on the substrate and electrically connected to the active layer; and a protective layer covering the source electrode and the drain electrode.. .
Innolux Corporation


06/16/16
20160172362 

Cmos transistors with identical active semiconductor region shapes


A disposable semiconductor material is deposited to form disposable semiconductor material portions on semiconductor fins. A first dielectric liner is deposited and patterned to form openings above a first set of disposable semiconductor material portions on a first semiconductor fin.
International Business Machines Corporation


06/16/16
20160172361 

Methods of forming field effect transistors having silicon-germanium source/drain regions therein


Methods of forming field effect transistors include selectively etching source and drain region trenches into a semiconductor region using a gate electrode as an etching mask. An epitaxial growth process is performed to fill the source and drain region trenches.

06/16/16
20160172280 

Power field-effect transistor (fet), pre-driver, controller, and sense resistor integration for multi-phase power applications


Techniques are described for integrating power field-effect transistors (fets), pre-drivers, controllers, and/or resistors into a common multi-chip package for implementing multi-phase bridge circuits. The techniques may provide a multi-chip package with at least two high-side (hs) fets and at least two low-side (ls) fets, and place the at least two hs fets or the at least ls fets on a common die.
Texas Instruments Incorporated


06/16/16
20160172047 

Semiconductor device and operating method thereof


A semiconductor device includes a memory array including memory blocks; and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the program loop is performed by controlling a target threshold voltage value of the selection transistors based on a difference between a cell current value of the selected memory block and a reference cell current value.. .
Sk Hynix Inc.


06/16/16
20160172036 

Memory cell with retention using resistive memory


Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: a memory element including cross-coupled cells having a first node and a second node; a first transistor coupled to the first node; a second transistor coupled to the second node; and a resistive memory element coupled to the first and second transistors..

06/16/16
20160172009 

Semiconductor device and electronic device


To provide a semiconductor device having large memory capacity and high reliability of data or a small-size semiconductor device having a small circuit area. A memory cell includes first and second data retention portions capable of storing multilevel data.
Semiconductor Energy Laboratory Co., Ltd.


06/16/16
20160171928 

Amoled pixel unit, driving the same, and display device


Provided are an amoled pixel unit, a method for driving the same, and a display device. The amoled pixel unit includes a compensating unit, a light emitting control unit, a driving transistor, a storage capacitor and an organic light emitting diode, wherein the compensating unit is switched on under the control of a signal on a scan line; the light emitting control unit is switched on under the control of a signal on a light emitting control line; an anode of the organic light emitting diode is connected to a second terminal of the storage capacitor, and a cathode of the organic light emitting diode receives a second power supply signal.
Boe Technology Group Co., Ltd.


06/16/16
20160170684 

Flash memories using minimum push up, multi-cell and multi-permutation schemes for data storage


Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed.
Texas A&m University System


06/16/16
20160170433 

Method and circuit for generating a proportional-to-absolute-temperature current source


A proportional-to-absolute-temperature (“ptat”) circuit includes a bias component; first, second, third, and fourth transistors; an output transistor; and a first resistive component. A first terminal of the bias component is coupled to a voltage supply node.
Freescale Semiconductor, Inc.


06/16/16
20160168635 

Integrated sensor arrays for biological and chemical analysis


The invention is directed to apparatus and chips comprising a large scale chemical field effect transistor arrays that include an array of sample-retaining regions capable of retaining a chemical or biological sample from a sample fluid for analysis. In one aspect such transistor arrays have a pitch of 10 μm or less and each sample-retaining region is positioned on at least one chemical field effect transistor which is configured to generate at least one output signal related to a characteristic of a chemical or biological sample in such sample-retaining region.
Life Technologies Corporation


06/09/16
20160165734 

Controllable constant current supply integrated circuits for driving dense arrays


A controllable current driver integrated circuit is provided. The controllable current driver includes a multitude of different current value output transistors digitally controlled and combined to provide a controllable current output.
4233999 Canada Inc.


06/09/16
20160165682 

Led driving circuit of multi-stage switch bulb lamp


An led driving circuit of a multi-stage switch bulb lamp includes a power modulation module having a first switch, a second switch, a first transistor, a second transistor, a first resistor, a second resistor, a third resistor and a fourth resistor. The first and second switches are respectively and serially connected to the first and second transistors, the first transistor is electrically connected to the second resistor, the other end of the second resistor is serially connected to the third resistor to form a reference voltage node and has a reference voltage, the first and second transistors are electrically connected to the reference voltage node, the other end of the third resistor is serially connected to the fourth resistor, and the second transistor is electrically connected to the third resistor.
Unity Opto Technology Co., Ltd.


06/09/16
20160165167 

Solid state imaging device and electronic apparatus


A solid state imaging device includes a pixel array unit in which color filters of a plurality of colors are arrayed with four pixels of vertical 2 pixels×horizontal 2 pixels as a same color unit that receives light of the same color, shared pixel transistors that are commonly used by a plurality of pixels are intensively arranged in one predetermined pixel in a unit of sharing, and a color of the color filter of a pixel where the shared pixel transistors are intensively arranged is a predetermined color among the plurality of colors. The present technology can be applied, for example, to a solid state imaging device such as a back-surface irradiation type cmos image sensor..
Sony Corporation


06/09/16
20160165163 

Imaging device


An object of the present invention is to reduce capacitance of a charge accumulation part (floating diffusion) of each pixel unit. In an imaging device, in addition to a plurality of first switching transistors for coupling a plurality of coupling wires extending in the column direction, a second switching transistor is provided between each of the coupling wires and a floating diffusion in each pixel unit.
Renesas Electronics Corporation


06/09/16
20160165162 

Solid-state imaging device and drive control the same


A cmos sensor has unit pixels each structured by a light receiving element and three transistors, to prevent against the phenomenon of saturation shading and the reduction of dynamic range. The transition time (fall time), in switching off the voltage on a drain line shared in all pixels, is given longer than the transition time in turning of any of the reset line and the transfer line.

06/09/16
20160165159 

Solid state image sensor with enhanced charge capacity and dynamic range


Certain aspects relate to imaging systems and methods for manufacturing imaging systems and image sensors. The imaging system includes a pixel array including a plurality of pixels, the pixels configured to generate a charge when exposed to light and disposed on a first layer.
Qualcomm Incorporated


06/09/16
20160164546 

Low noise, programmable gain current buffer


A current buffer used in a receiver arrangement includes a direct path mode and a mirror path mode. The direct path mode includes a plurality of first set of transistors and a plurality of first set of current sources turned on while all remaining transistors and current sources are turned off , during the direct path mode a current signal at an input node directly appears at an output node.
Mediatek Inc.


06/09/16
20160164534 

Load current compensation for analog input buffers


Systems and methods for load current compensation for analog input buffers. In various embodiments, an input buffer may include a first transistor (q1) having a collector terminal coupled to a power supply node and a base terminal coupled to a first input node (vinp); a second transistor (q2) having a collector terminal coupled to an emitter terminal of the first transistor (q1); a third transistor (q3) having an emitter terminal coupled to an emitter terminal of the second transistor (q2) and to a ground node, a collector terminal coupled to a current source (ibias), and a base terminal coupled the collector terminal and to a base terminal of the second transistor (q2); and a capacitor (c1) coupled to the base terminals of the second and third transistors (q2 and q3) and to a second input node (vinn), wherein the first and second input nodes (vinp and vinn) are differential inputs..
Texas Instruments Incorporated


06/09/16
20160164517 

High gain load circuit for a differential pair using depletion mode transistors


A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor.
Analog Devices, Inc.


06/09/16
20160164515 

Biasing scheme for high voltage circuits using low voltage devices


Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series.
Intel Corporation


06/09/16
20160164494 

Semiconductor device and adjusting impedance of output circuit


An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal.
Micron Technology, Inc.


06/09/16
20160164469 

Amplifier dynamic bias adjustment for envelope tracking


An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor..
Peregrine Semiconductor Corporation


06/09/16
20160164468 

Amplifier dynamic bias adjustment for envelope tracking


An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor..
Peregrine Semiconductor Corporation


06/09/16
20160164467 

Amplifying device and offset voltage correction method


A state wherein offset voltage is reduced can be maintained regardless of environmental fluctuation. A differential amplification unit has differential pair transistors, and amplifies a difference between input voltages.
Fuji Electric Co., Ltd.


06/09/16
20160164429 

Constant inrush current circuit for ac input power supply unit


A power supply circuit includes a rectifier module configured to rectify an input voltage and a capacitor including a first terminal coupled to the rectifier module. In addition, the power supply circuit includes first and second transistors.
Dell Products L.p.


06/09/16
20160164417 

Dc-dc converter module


A dc-dc converter module includes a module substrate on which switching transistors and a controller ic chip are mounted, stud terminals mounted on a surface of the module substrate, and an inductor attached to the stud terminals such that the inductor faces the module substrate. In a plan view, the switching transistors are arranged within an area where the inductor overlaps the module substrate, whereas at least a portion of the controller ic chip is arranged outside the area..
Panasonic Intellectual Property Management Co., Ltd.


06/09/16
20160164404 

Cold start dc/dc converter


A dc/dc converter comprising a first charge pump circuit including first mos transistors including first depletion mos transistors, an oscillating circuit connected to the charge pump circuit only at the gates of some at least of the first mos transistors, including the first depletion mos transistors.. .
Commissariat à I'energie Atomique Et Aux Energies Alternatives


06/09/16
20160164156 

Long-distance high-speed data and clock transmission


A non-linear impedance terminates a transmission line. The non-linear impedance may be implemented with a back-to-back connected inverter pair.
Broadcom Corporation


06/09/16
20160163862 

Epitaxial block layer for a fin field effect transistor device


Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (finfets) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of finfets; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate..
Globalfoundries Inc.


06/09/16
20160163856 

Vertical nanowire transistor with axially engineered semiconductor and gate metallization


Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer.
Intel Corporation


06/09/16
20160163823 

Semiconductor structure with multiple transistors having various threshold voltages


A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element.
Mie Fujitsu Semiconductor Limited


06/09/16
20160163813 

Metal contacts to group iv semiconductors by inserting interfacial atomic monolayers


Techniques for reducing the specific contact resistance of metal-semiconductor (group iv) junctions by interposing a monolayer of group v or group iii atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal—group iv semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (fet).
Acorn Technologies, Inc.


06/09/16
20160163811 

Vertical field effect transistors


Vertical field effect transistors (fets) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure.
International Business Machines Corporation


06/09/16
20160163802 

High resistance layer for iii-v channel deposited on group iv substrates for mos transistors


Techniques are disclosed for using a high resistance layer between a iii-v channel layer and a group iv substrate for semiconducting devices, such as metal-oxide-semiconductor (mos) transistors. The high resistance layer can be used to minimize (or eliminate) current flow from source to drain that follows a path other than directly through the channel.
Intel Corporation


06/09/16
20160163776 

Organic light-emitting diode (oled) display and manufacturing the same


An organic light-emitting diode (oled) display having thin film transistors (tfts) is disclosed. In one aspect, tfts of the oled display include a substrate and a first semiconductor layer formed over the substrate and including first channel, source, and drain regions and a lightly doped region between the first channel region and the first source and drain regions.
Samsung Display Co., Ltd.


06/09/16
20160163770 

Transparent organic light emitting display device and manufacturing the same


Disclosed is a transparent organic light-emitting display (oled) device having improved resolution by changing the layout of sub-pixel regions in a light-emitting area. The device comprises: a substrate having a plurality of pixels, each pixel including: a light emitting area including a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region; and a transmissive area through which external light passes, wherein the transmissive area is surrounded by edges of the first, second and third sub-pixel regions of the pixel; and an organic light-emitting element on thin film transistors in each of the sub-pixel regions, wherein the first sub-pixel region is arranged on a first line of the pixel extending in a first direction, the second sub-pixel region is arranged on a second line parallel to the first direction, and the third sub-pixel region is arranged on a third line extending in a second direction..
Lg Display Co., Ltd.


06/09/16
20160163759 

Pixel having two semiconductor layers, image sensor including the pixel, and image processing system including the image sensor


An image sensor having pixels that include two patterned semiconductor layers. The top patterned semiconductor layer contains the photoelectric elements of pixels having substantially 100% fill-factor.
Samsung Electronics Co., Ltd.


06/09/16
20160163746 

Display device and fabricating the same


A method of fabricating a display device including forming one or more thin-film transistors (“tfts”) each configured to include an active layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on a substrate. A storage capacitor including a first storage electrode and a second storage electrode overlapping the first storage electrode with the gate insulating layer interposed there between is also formed on the substrate.
Samsung Display Co., Ltd.


06/09/16
20160163745 

Organic light-emitting diode display with double gate transistors


An organic light-emitting diode display may have an array of pixels. Each pixel may have an organic light-emitting diode and thin-film transistor circuitry that controls current flow through the organic light-emitting diode.
Apple Inc.


06/09/16
20160163736 

Gate array for high-speed cmos and high-speed cmos ttl family


A system for implementing an integrated circuit(ic) is provided. The system includes one or more base layers.

06/09/16
20160163734 

Three-dimensional nonvolatile memory device, semiconductor system including the same, and manufacturing the same


A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection transistors and second selection transistors spaced apart from each other along the first vertical channel layer and the second vertical channel layer, a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, and a common source line formed over the second vertical channel layer.. .
Sk Hynix Inc.


06/09/16
20160163714 

Static random access memory (sram) bit cells with wordline landing pads split across boundary edges of the sram bit cells


Static random access memory (sram) bit cells with wordline landing pads split across boundary edges of the sram bit cells are disclosed. In one aspect, an sram bit cell is disclosed employing write wordline in second metal layer, first read wordline in third metal layer, and second read wordline in fourth metal layer.
Qualcomm Incorporated


06/09/16
20160163713 

Static random access memory (sram) bit cells with wordlines on separate metal layers for increased performance, and related methods


Static random access memory (sram) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an sram bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer.
Qualcomm Incorporated


06/09/16
20160163708 

Semiconductor device including transistors


A semiconductor device includes a semiconductor substrate having a first transistor region and a second transistor region, a first mosfet including a first gate insulating layer structure and a first gate electrode structure, and a second mosfet including a group iv compound semiconductor layer, a second gate insulating layer structure, and a second gate electrode structure. The first gate insulating layer structure and the first gate electrode structure are disposed on the first transistor region of the semiconductor substrate.
Samsung Electronics Co., Ltd.


06/09/16
20160163705 

Finfet work function metal formation


An improved method and structure for fabrication of replacement metal gate (rmg) field effect transistors is disclosed. P-type field effect transistor (pfet) gate cavities are protected while n work function metals are deposited in n-type field effect transistor (nfet) gate cavities..
Globalfoundries Inc.


06/09/16
20160163703 

Semiconductor device


A semiconductor device includes a first mos transistor and a second mos transistor of a second conductivity type. The first mos transistor includes a first main electrode connected to a first potential and a second main electrode connected to a second potential.
Mitsubishi Electric Corporation


06/09/16
20160163695 

Integrated circuit comprising group iii-n transistors monolithically integrated on a silicon substrate and a manufacturing thereof


An integrated circuit comprising a first iii-n transistor having a source region and a second iii-n transistor having a source region, both transistors being monolithically integrated on a common silicon substrate of a first doping type and separated from each-other by an isolation region, the substrate comprising underneath the first transistor a well of a first doping type electrically connected to the source region of the first transistor and comprising underneath the second transistor a well of a second doping type electrically connected to the source region of the second transistor, thereby forming a junction diode in the substrate between the sources of the first and the second transistor.. .
Imec Vzw


06/09/16
20160163691 

Esd protection device with improved bipolar gain using cutout in the body well


An integrated circuit includes an nmos scr in which a p-type body well of the nmos transistor provides a base layer for a vertical npn layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area.
Texas Instruments Incorporated


06/09/16
20160163685 

Tunable scaling of current gain in bipolar junction transistors


Methods for designing and fabricating a bipolar junction transistor. A predetermined size for a device region of the bipolar junction transistor is determined based on a given current gain.
Globalfoundries Inc.


06/09/16
20160163602 

Vertical field effect transistors


Vertical field effect transistors (fets) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure.
International Business Machines Corporation


06/09/16
20160163598 

Method of forming a bicmos semiconductor chip that increases the betas of the bipolar transistors


The betas of the bipolar transistors in a bicmos semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant..
Texas Instruments Incorporated


06/09/16
20160163441 

Actuator driver circuit


A circuit for driving an actuator including a closing coil and an opening coil, the circuit including a first electrical switch, a second electrical switch, a third electrical switch, a first diode, a second diode, a third diode, and a capacitor electrically connected to a second terminal of the third electrical switch. The circuit is structured such that controlling the state of the first, second, and third transistors causes current flowing through the circuit to flow through one of the closing coil and the opening coil and to not flow through the other of the closing coil and the opening coil..
Eaton Corporation


06/09/16
20160163379 

Circuits and methods for performance optimization of sram memory


In aspects of the present application, circuitry for storing data is provided including a static random access memory (sram) circuit operable to store data in an array of sram cell circuits arranged in rows and columns, each sram cell coupled to a pair of complementary bit lines disposed along the columns of sram cells circuits, and one or more precharge circuits in the sram memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the sram circuit is operable to cause coupling transistors within the sram circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the sram circuit, indicating a bitline precharge is to be performed..
Texas Instruments Incorporated


06/09/16
20160163357 

Semiconductor memory


A semiconductor memory including a memory cell array having a plurality of memory cells, a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array, and sense amplifiers which are disposed in plurality corresponding to the plurality of bit line pairs for amplifying a potential difference between the bit line pair in which the sense amplifier includes; precharging transistors each having a diffusion layer and precharging the bit line pair, and switching transistors each having a diffusion layer formed integrally with the diffusion layer of the precharging transistor for selectively connecting the plurality of the bit line pairs to a common bus line.. .
Renesas Electronics Corporation


06/09/16
20160163278 

Signal adjustment circuit


This disclosure provides systems, methods and apparatus for adjusting a voltage applied to a transistor based on a change in an electrical characteristic. In one aspect, a system includes an array of display elements each including an electrical element having a first terminal and a transistor.
Pixtronix, Inc.


06/09/16
20160162119 

Display to touch crosstalk compensation


A touch sensitive display capable of compensating for crosstalk in the display is disclosed. Crosstalk in display components can be reduced, eliminated, or otherwise compensated for by reducing or eliminating parasitic capacitances that cause the crosstalk.
Apple Inc.


06/09/16
20160161979 

Process skew resilient digital cmos circuit


A digital cmos circuit comprising at least one pull-up circuit arranged, when in an on-state, to switch an output node of the digital cmos circuit from a first voltage level to a second voltage level within a rising transition delay. The digital cmos circuit further comprises at least one pull-down circuit arranged, when in an on-state, to switch the voltage level of the output node of the digital cmos circuit from the second voltage level to the first voltage level within a falling transition delay.
Stichting Imec Nederland


06/09/16
20160161794 

Display device and manufacturing method thereof


According to an exemplary embodiment of the present system and method, a display device includes: a substrate including a plurality of pixel areas and a thin film transistor region; a plurality of thin film transistors formed on the substrate; a pixel electrode formed in each of the pixel areas and connected to a corresponding thin film transistor; a color filter layer formed on the pixel electrode to be spaced apart from the pixel electrode by a microcavity disposed in between; a plurality of connection microcavities formed in the thin film transistor region and connecting microcavities in a column; and a liquid crystal material filling the microcavities and the connection microcavities.. .
Samsung Display Co., Ltd.


06/02/16
20160156817 

Manufacturing imaging apparatus, imaging apparatus, and imaging system


A manufacturing method of an imaging apparatus includes a process of forming, on a same substrate, gate electrodes of multiple mos transistors forming pixel circuits and gate electrodes of multiple mos transistors forming peripheral circuits, and a process of forming, on the substrate, an insulating film covering the gate electrodes of the multiple mos transistors found in the pixel circuits and the gate electrodes of the multiple mos transistors found in the peripheral circuits. A thickness of the gate electrode of a first mos transistor in the multiple mos transistors found in the pixel circuits is 1.2 times or more a thickness of the gate electrode of a second mos transistor in the multiple mos transistors found in the peripheral circuits..
Canon Kabushiki Kaisha


06/02/16
20160156314 

Self-timed differential amplifier


The present invention provides a self-timed differential amplifier, including an amplifier unit, having a pair of read/write terminals, wherein data is read or written by a select line; a pair of precharge transistors, controlled by a control line; and a pair of cross-coupled transistors, controlled by a column select line. Moreover, a complementary differential amplifier is formed by the combination of the pair of precharge transistors and the pair of cross-coupled transistors.
Integrated Circuit Solution Inc.


06/02/16
20160156278 

Busbar locating component


A busbar locating component includes: one or more first attachments configured for attaching a busbar layer to the busbar locating component; one or more bays each configured to contain and position an assembly of transistors essentially perpendicular to the busbar layer for connection; and a plurality of slots, each slot configured to contain and position a busbar relative to the busbar layer for connection.. .
Tesla Motors, Inc.


06/02/16
20160156277 

Power device


An energy efficient apparatus includes a switching device, a frequency dependent reactive device, and a control element is provided. The switching device is coupled to a source of electrical power and includes a pair of transistors and is adapted to receive a control signal and to produce an alternating current power signal.

06/02/16
20160156268 

Dc-dc switching converter with enhanced switching between ccm and dcm operating modes


An electronic device includes first and second transistors coupled in series between first and second source voltage levels. An inductor is coupled between a node coupling the first and second transistors and a load.
Stmicroelectronics International N.v.


06/02/16
20160155983 

Organic light emitting diode display


An organic light emitting diode (oled) display is disclosed. In one aspect, the oled display includes a substrate, a plurality of transistors formed over the substrate and a passivation layer covering the transistors.
Samsung Display Co., Ltd.


06/02/16
20160155970 

Vertical organic light-emitting transistor and organic led illumination apparatus having the same


Provided are vertical-type organic light-emitting transistors and organic led illumination apparatuses. The organic led illumination apparatus includes gate electrode lines that are disposed parallel to each other with predetermined gaps on a substrate; a gate insulating layer covering the gate electrode lines on the substrate; a plurality of first electrode lines that are disposed to overlap or perpendicularly cross the gate electrode lines on the gate insulating layer; a first charge transport layer covering the first electrode lines on the gate insulating layer; a plurality of active layers arranged in a matrix array facing the first electrode lines on the first charge transport layer; a second charge transport layer covering the active layers on the first charge transport layer; and a plurality of second electrode lines that are perpendicularly disposed with respect to the first electrode lines and traverse the active layers on the second transport layer..
Samsung Electronics Co., Ltd.


06/02/16
20160155941 

Charge ordered vertical transistors


A vertical charge ordered transistor is disclosed. A thin charge ordered layer is employed as a tunnel barrier between two electrodes.
Drexel University


06/02/16
20160155925 

Method of forming a cmos-based thermoelectric device


An integrated circuit containing cmos transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the cmos transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements.
Texas Instruments Incorporated


06/02/16
20160155859 

Display device and electronic device


A display device including a pixel having a memory. The pixel includes at least a display element, a capacitor, an inverter, and a switch.
Semiconductor Energy Laboratory Co., Ltd.


06/02/16
20160155855 

Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors


A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel.
Micron Technology, Inc.


06/02/16
20160155830 

Compound semiconductor device


A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors.
Murata Manufacturing Co., Ltd.


06/02/16
20160155829 

Transistors and methods of forming transistors


Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions.
Micron Technology, Inc.


06/02/16
20160155827 

Method for producing a thin film transistor


A method for producing a thin film transistor includes forming a transistor prototype on a substrate. The transistor prototype includes two transparent electrodes adapted to form a source and a drain of a thin film transistor.
National Sun Yat-sen University


06/02/16
20160155826 

Method for fabricating fin field effect transistors


A method of fabricating a fin field effect transistor (finfet) includes providing a substrate having a first fin and a second fin extending above a substrate top surface, wherein the first fin has a top surface and sidewalls and the second fin has a top surface and sidewalls. The method includes forming an insulation layer between the first and second fins.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/02/16
20160155804 

Method of fabricating fin-field effect transistors (finfets) having different fin widths


Provided are methods of forming field effect transistors. The method includes preparing a substrate with a first region and a second region, forming fin portions on the first and second regions, each of the fin portions protruding from the substrate and having a first width, forming a first mask pattern to expose the fin portions on the first region and cover the fin portions on the second region, and changing widths of the fin portions provided on the first region..
Samsung Electronics Co., Ltd.


06/02/16
20160155800 

Fabricating stacked nanowire, field-effect transistors


Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along its sidewalls, and the cut mask spacer overlying the sidewall spacer; defining a stack structure by cutting through the multiple layers using the cut mask spacer and gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the other layer(s) of the multiple layers to selectively expose, in part, end surfaces of the other layer(s)..
Globalfoundries Inc.


06/02/16
20160155763 

Monolithic integration techniques for fabricating photodetectors with transistors on same substrate


Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing pds and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues..
Artilux, Inc


06/02/16
20160155741 

Semiconductor device with fin field effect transistors


A semiconductor device includes a substrate with a nmos region and a pmos region, a device isolation layer on the substrate to define active fins, and gate patterns on the substrate to have a length direction crossing the active fins, wherein the device isolation layer includes diffusion brake regions between respective pairs of the active fins, the diffusion brake regions being disposed adjacent to each other in a width direction of the gate patterns, and wherein a width of the diffusion brake region in the nmos region is different from a width of the diffusion brake region in the pmos region.. .

06/02/16
20160155492 

Novel finfet 6t sram cell structure


A static memory circuit includes a pull-up transistor, a pull-down transistor, a pass-gate transistor associated with the pull-up and pull-down transistors, and first and second word lines electrically insulated from each other. The pass-gate transistor includes a number of fins and a gate electrode having a number of first and second gates, each one of the gates is disposed on one of the fins, the first gates are connected to the first word line, and the second gates are connected to the second word line.
Semiconductor Manufacturing International (shanghai) Corporation


06/02/16
20160155422 

Gate driving unit, gate driving circuit and driving method thereof, and display device


A gate driving unit, a gate driving circuit, a driving method thereof, and a display device are disclosed. The gate driving unit includes first to eighth transistors, a first capacitor and a second capacitor.
Tianma Micro-electronics Co., Ltd.


06/02/16
20160155377 

Display device and drive method therefor


A monitor line electrically connectable with sources of drive transistors and positive electrodes of electro-optical elements is provided. A drive method includes a step of detecting the characteristics of a drive transistor, a step of detecting the characteristics of an electro-optical element, a step of storing characteristics data obtained on the basis of a result of the detection of the characteristics, as correction data for correcting a video signal, and a step of correcting the video signal on the basis of the correction data.
Sharp Kabushiki Kaisha


06/02/16
20160153840 

Inverter and ring oscillator with high temperature sensitivity


The invention provides an inverter. The inverter includes a first converter and a second converter.
Mediatek Inc.


05/26/16
20160150620 

Visible and nonvisible light bulb driver and system


An electronic lighting system with a driver for providing light from visible light bulbs and non-visible light bulbs, including from infrared, ultraviolet, led and fluorescent lamps of multiple sizes and wattages, having power factor correction, surge protection, current sensing, current adjustment feedback, and dimming system. There are transformers dedicated to particular lamp receptacles that include interloper diodes and resistor sets that fine tune the functioning of the driver sensing loads.

05/26/16
20160150175 

Global shutter image sensor pixels having improved shutter efficiency


An image sensor may be provided with an array of image sensor pixels formed on a substrate having front and back surfaces. Each pixel may have a photodiode that receives light through the back surface, a floating diffusion node, a charge transfer gate, and first and second reset transistor gates.
Semiconductor Components Industries, Llc


05/26/16
20160150169 

Image sensor pixels having p-channel source follower transistors and increased photodiode charge storage capacity


An image sensor may include image sensor pixels formed on a substrate. Each pixel may have a photodiode, a floating diffusion node, and charge transfer gate.
Semiconductor Components Industries, Llc


05/26/16
20160149578 

Low voltage differential signaling (lvds) driving circuit


An lvds (low voltage differential signaling) driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, and a bias driver. The first transistor is coupled between a supply voltage and a first node.
Via Alliance Semiconductor Co., Ltd.


05/26/16
20160149576 

Low voltage differential signaling (lvds) driving circuit


An lvds (low voltage differential signaling) driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, and a bias driver. The first transistor is coupled between a supply voltage and a first node.
Via Alliance Semiconductor Co., Ltd.


05/26/16
20160149567 

Semiconductor device and electronic device


In a configuration including a first circuit for retaining a plurality of analog voltages and a second circuit capable of reading one of the analog voltages as a digital signal, correct data can be read even when characteristics of transistors in the first and second circuits vary with the temperature change. A reference voltage is applied to a gate of a transistor in the second circuit whose threshold voltage varies with the temperature change, and a corrected reference voltage is generated by adding a threshold voltage variation of the transistor in the second circuit to the reference voltage.
Semiconductor Energy Laboratory Co., Ltd.


05/26/16
20160149558 

Effective biasing active circulator with rf choke concept


A multi-port active circulator where each of plurality of fet transistors has (i) a gate connected to an associated port of the multi-port active circulator via a capacitor of an associated one of a plurality of first rf chokes, each of the first rf chokes being connected to a gate of an associated fet transistor of said plurality of transistors, the associated port of said associated fet transistor and to a power supply bias connection; (ii) a source connected to a common point; and (iii) a drain connected to the gate of the same fet transistor by a feedback circuit and connected to the gate of a neighboring fet transistor via a capacitor of one of a plurality of second rf chokes, each of which coupling gates and drains of neighboring fet transistors via capacitors thereof and being connected to another power supply bias connection.. .
Hrl Laboratories, Llc


05/26/16
20160149486 

Input-output circuits


A circuit comprises a first circuit and a second circuit. The first circuit is configured to operate at a first-circuit supply voltage value, and to generate a first reference voltage value based on a voltage rated for transistors in a second circuit.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/26/16
20160149054 

Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts


An approach to forming a semiconductor structure for a vertical field effect transistor with a controlled gate overlap. The approach includes forming on a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a first dielectric layer.
International Business Machines Corporation


05/26/16
20160149051 

Transistors incorporating small metal elements into doped source and drain regions


Metal quantum dots are incorporated into doped source and drain regions of a mosfet array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions.
Stmicroelectronics, Inc.


05/26/16
20160149050 

Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels


An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer..
International Business Machines Corporation


05/26/16
20160149041 

Semiconductor devices and finfets


Semiconductor devices and fin field effect transistors (finfets) are disclosed. In some embodiments, a representative semiconductor device includes a group iii material over a substrate, the group iii material comprising a thickness of about 2 monolayers or less, and a group iii-v material over the group iii material..
Taiwan Semiconductor Manufacturing Company, Ltd.


05/26/16
20160149038 

Facet-free strained silicon transistor


The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors.
Stmicroelectronics, Inc.


05/26/16
20160149020 

Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels


An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer..
International Business Machines Corporation


05/26/16
20160149017 

Gate spacers and methods of forming


Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/26/16
20160149015 

Recessing rmg metal gate stack for forming self-aligned contact


Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (fets) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation.
Globalfoundries Inc.




Transistors topics: Transistors, Semiconductor, Semiconductor Device, Integrated Circuit, High Speed, Photodiode, Memory Effect, Silicon Nitride, Enhancement, Ion Implant, Ion Channel, Interrupted, Reference Voltage, Semiconductor Devices, Semiconductor Substrate

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