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 Imaging device, monitoring device, and electronic appliance patent thumbnailnew patent Imaging device, monitoring device, and electronic appliance
A highly accurate imaging device or a highly accurate imaging device capable of detecting differences is provided. A configuration including a circuit in which variation in threshold voltage among amplifier transistors of pixels is corrected is employed.
Semiconductor Energy Laboratory Co., Ltd.


 Image device, image system, and control  image device patent thumbnailnew patent Image device, image system, and control image device
An image device transfers charges of a previous frame from the holding units to the amplification units, during a read-out period of each frame, the read-out period includes a period in which a plurality of overflow transistors are in an on-state and a first period in which a plurality of photoelectric conversion units accumulate charges, and, during a second period following the first period, the plurality of photoelectric conversion units of the plurality of pixels accumulate charges while the plurality of holding units of the plurality of pixels hold the charges accumulated during the first period. During the first and second periods, each of the plurality of pixels performs a plurality of times of charge transfers from the photoelectric conversion unit to the holding unit.
Canon Kabushiki Kaisha


 Self resetting latch patent thumbnailnew patent Self resetting latch
An apparatus includes first and second input transistors receiving respective first and second input signals, and a feedback circuit coupled to the first and second input transistors. The first and second input transistors provide first and second nodes with first and second currents according to values of the first and second input signals, respectively, when the feedback circuit is turned on.
Marvell International Ltd.


 Feed-forward bias circuit patent thumbnailnew patent Feed-forward bias circuit
A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for pvt variations in the other circuit. In some aspects, the feed-forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions.
Qualcomm Incorporated


 Radio frequency circuitr having an integrated harmonic filter and a radio frequency circuit having transistors of different threshold voltages patent thumbnailnew patent Radio frequency circuitr having an integrated harmonic filter and a radio frequency circuit having transistors of different threshold voltages
An integrated circuit that includes a die with an active radio frequency (rf) unit embedded thereon; a first port for receiving an output signal from the active rf unit; a harmonic filter that comprises a first harmonic filter inductor; and a first rf inductive load that is electrically coupled to the first port and is magnetically coupled to the first harmonic filter inductor.. .
Dsp Group Ltd.


 Low power circuit for amplifying a voltage without using resistors patent thumbnailnew patent Low power circuit for amplifying a voltage without using resistors
A resistor-less amplifying circuit includes a plurality of resistor-less cells. Each cell includes a plurality of mos transistors.
Freescale Semiconductor, Inc.


 Method of manufacturing organic light emitting display device patent thumbnailnew patent Method of manufacturing organic light emitting display device
An organic light emitting display device having high transmittance with respect to external light and a method of manufacturing the same. The organic light emitting display device includes a substrate; a plurality of pixels formed on the substrate, each of the pixels including a first region that emits light and a second region that transmits external light; a plurality of thin film transistors disposed in the first region of each pixel; a plurality of first electrodes disposed in the first region of each pixel and electrically connected to the thin film transistors, respectively; a second electrode formed opposite to the plurality of first electrodes and comprising a plurality of transmission windows corresponding to the second regions; and an organic layer formed between the first electrodes and the second electrode.
Samsung Display Co., Ltd.


 Monolithic integration techniques for fabricating photodetectors with transistors on same substrate patent thumbnailnew patent Monolithic integration techniques for fabricating photodetectors with transistors on same substrate
Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing pds and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues..
Artilux, Inc.


 Contacts for highly scaled transistors patent thumbnailnew patent Contacts for highly scaled transistors
A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain(s/d) regions, a channel between the first and second s/d regions, a gate engaging the channel, and a contact feature connecting to the first s/d region.
Taiwan Semiconductor Manufacturing Co., Ltd.


 Strained stacked nanowire field-effect transistors (fets) patent thumbnailnew patent Strained stacked nanowire field-effect transistors (fets)
A method for manufacturing a semiconductor device comprises epitaxially growing a plurality of silicon layers and compressively strained silicon germanium (sige) layers on a substrate in a stacked configuration, wherein the silicon layers and compressively strained sige layers are alternately stacked on each other starting with a silicon layer on a bottom of the stacked configuration, patterning the stacked configuration to a first width, selectively removing a portion of each of the silicon layers in the stacked configuration to reduce the silicon layers to a second width less than the first width, forming an oxide layer on the compressively strained sige layers of the stacked configuration, wherein forming the oxide layer comprises fully oxidizing the silicon layers so that portions of the oxide layer are formed in place of each fully oxidized silicon layer, and removing part of the oxide layer while maintaining at least part of the portions of the oxide layer formed in place of each fully oxidized silicon layer, wherein the compressively strained sige layers are anchored to one another and a compressive strain is maintained in each of the compressively strained sige layers.. .
International Business Machines Corporation


new patent

Display apparatus and manufacturing the same

A display apparatus includes a substrate having a plurality of pixel areas, and a pixel circuit including a storage capacitor and a plurality of thin film transistors (tfts) which are disposed in each pixel area. At least one of the plurality of tfts includes a semiconductor layer disposed on the substrate and including a first ion impurity, a source area and a drain area, which are spaced apart from each other, have a first depth from a surface of the semiconductor layer, and include a second ion impurity, a gate electrode disposed on the semiconductor layer between the source area and the drain area, and a bias wiring electrically connected to the semiconductor layer and disposed adjacent to at least one of the source area and the drain area..
Samsung Display Co., Ltd.

new patent

Hybrid bipolar junction transistor

Bipolar junction transistors including inorganic channels and organic emitter junctions are used in some applications for forming high resolution active matrix displays. Arrays of such bipolar junction transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes..
International Business Machines Corporation

new patent

Pixel array, display panel and display device

The present invention provides a pixel array, a display panel and a display device, and the pixel array includes a plurality of gate lines and a plurality of data lines intersecting and insulated from each other, and a plurality of pixel units defined by the plurality of gate lines and the plurality of data lines intersecting each other. Each of the plurality of pixel units includes a thin-film transistor and a strip-shaped electrode, the strip-shaped electrodes of two adjacent pixel units in a same column have different inclination directions, the thin-film transistors of the two adjacent pixel units are in inclination angle regions of the two adjacent pixel units, respectively, and the inclination angle region is a region corresponding to a position at which extending directions of the strip-shaped electrode and the gate line intersect to form an acute angle in a pixel unit..
Beijing Boe Optoelectronics Technology Co., Ltd.

new patent

Integrated circuit composed of tunnel field-effect transistors and manufacturing same

The present invention provides an integrated circuit formed of tunneling field-effect transistors that includes a first tunneling field-effect transistor in which one of a first p-type region and a first n-type region operates as a source region and the other one operates as a drain region; and a second tunneling field-effect transistor in which one of a second p-type region and a second n-type region operates as a source region and the other one operates as a drain region, the first and second tunneling field-effect transistors being formed in one active region to have the same polarity, the first p-type region and the second n-type region being formed adjacently, the adjacent first p-type region and second n-type region being electrically connected through metal semiconductor alloy film.. .
National Institute Of Advanced Industrial Science And Technology

new patent

Electrostatic discharge (esd) robust transistors and related methods

An electrostatic discharge robust semiconductor transistor (transistor) includes a semiconductor substrate of a first conductivity type, a substrate contact region of the first conductivity type coupled with the semiconductor substrate, a source region of a second conductivity type, a channel region of the second conductivity type, a gate region of the first conductivity type, a drain region having a first drain region of the first conductivity type and a second drain region of the second conductivity type, and an electrical conductor coupled over the second drain region and a portion of the first drain region. A portion of the first drain region not covered by the electrical conductor forms a resistive electrical ballast region configured to protect the transistor from electrostatic discharge (esd) induced voltage pulses.
Semiconductor Components Industries, Llc

new patent

Semiconductor device

Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction, each of which has a plurality of transistors.
Renesas Electronics Corporation

new patent

Method of fabricating a transistor channel structure with uniaxial strain

Method for creation of stressed channel structure transistors wherein at least one amorphising ion implantation of the surface layer of a substrate of the semiconductor-on-insulator type is carried out through openings in a mask, so as to render zones of the surface layers amorphous and to induce relaxation of a zone intended to form a channel and located between the zones that have been rendered amorphous, the relaxation being carried out in a direction orthogonal to that in which it is intended that the channel current flows.. .
Commissariat A L'energie Atomique Et Aux Energies Alternatives

new patent

Memory device

According to one embodiment, a memory device includes a string unit including a plurality of memory cell transistors which are connected in series, a first select transistor connected to a first end of the plurality of memory cell transistors, and a second select transistor connected to a second end of the plurality of memory cell transistors; and a bit line connected to the first select transistor.. .
Kabushiki Kaisha Toshiba

new patent

Semiconductor memory device

A semiconductor memory device includes a first block having a first memory cell and a second block having a second memory cell, first and second word lines respectively connected to the first and second memory cells, first and second select transistors having first ends respectively connected to the first and second word lines, a first circuit configured to apply a voltage to the first word line, and to control a gate voltage of the second select transistor, a second circuit configured to apply a voltage to the second word line, and to control a gate voltage of the first select transistor, first and second wirings respectively connected to second ends of the first and second select transistors, a third circuit configured to apply a voltage to the first wiring, and a fourth circuit configured to apply a voltage to the second wiring.. .
Kabushiki Kaisha Toshiba

new patent

Structure and a sram circuit

The present disclosure provides an integrated circuit formed in a semiconductor substrate. The integrated circuit includes a first static random access memory (sram) cell having a first cell size; and a second sram cell having a second cell size greater than the first cell size.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Shift register, gate driving circuit, display screen and driving the display screen

A shift register, a gate driving circuit, a display screen and a method for driving the display screen are proposed. A first and/or a second node control unit are incorporated.
Ordos Yuansheng Optoelectronics Co., Ltd.

new patent

Display device

A display device includes: a display panel including a plurality of gate lines on a substrate, a plurality of data lines crossing the gate lines, and a plurality of pixels, each of the pixels being coupled to one of the gate lines and to one of the data lines; a data driver configured to output data signals through a plurality of channel terminals; and a line selector configured to transmit the data signals to a plurality of data line blocks, each of the data line blocks including a plurality of data lines, wherein the line selector includes a plurality of thin-film transistors, and at least two of the thin-film transistors have different sizes.. .
Samsung Display Co., Ltd.

new patent

Display panel structure

A display panel includes a gate integrated circuit, a number of scan lines extending from the gate integrated circuit for transmitting scan signals, a source integrated circuit, a number of data lines extending from the source integrated circuit for transmitting data signals, a number of pixel electrodes for receiving the scan signals and the data signals, and a number of transistors each electrically coupled to a corresponding scan line, a corresponding data line, and a corresponding pixel electrode. The transistors each include a gate electrode, a source electrode, and a drain electrode.
Century Technology (shenzhen) Corporation Limited

new patent

Electromechanical systems device with segmented electrodes and thin film transistors for increasing stable range

This disclosure provides systems, methods, and apparatus for electromechanical systems (ems) devices with a plurality of electrically isolated electrode segments each connected to a distinct thin film transistor (tft), where a plurality of tfts drive the ems device by applying a common voltage to the plurality of electrode segments. The plurality of tfts can be configured to allow each electrode segment to have its own voltage during actuation.
Qualcomm Mems Technologies, Inc.

Radio frequency circuitr having an integrated harmonic filter and a radio frequency circuit having transistors of different threshold voltages

An integrated circuit that includes a die with an active radio frequency (rf) unit embedded thereon; a first port for receiving an output signal from the active rf unit; a harmonic filter that comprises a first harmonic filter inductor; and a first rf inductive load that is electrically coupled to the first port and is magnetically coupled to the first harmonic filter inductor.. .
Dsp Group Ltd.

Low noise amplifier circuit

An amplifier for converting a single-ended input signal to a differential output signal. The amplifier comprises a first transistor, a second transistor, a third transistor and a fourth transistor.
Telefonaktiebolaget Lm Ericsson (publ)

Dc/dc converter and switching power supply

A dc/dc converter has: a soft-start circuit generating a soft-start input voltage increasing gradually; an error amplifier generating an error signal by comparing an output voltage or a feedback voltage with a reference voltage or the soft-start input voltage, whichever is lower; a variable current generator generating a variable current proportional to the soft-start input voltage or a soft-start output voltage; a constant current source generating a bias current; an oscillator generating a rectangular-wave signal whose frequency varies linearly with a soft-start current which is the sum of the variable current and the bias current; a slope circuit generating a slope signal based on the rectangular-wave signal; a pwm comparator generating a pwm signal based on the error signal and the slope signal; and a control circuit switching transistors alternately based on the pwm signal. Through switching operation of the transistors, an input voltage is converted into the output voltage..
Rohm Co., Ltd.

Low power dc-dc converter

A dc-dc converter comprises an oscillator and a charge pump, to ensure operation at low voltage. The oscillator comprises one or more source degenerated transistors comprising a degeneration impedance located between a source of the transistor and a ground connection.
Dialog Semiconductor (uk) Limited

Doping-induced carrier density modulation in polymer field-effect transistors

A method of fabricating an organic field effect transistor (ofet), including forming a source contact, a drain contact, and a gate connection to a channel comprising semiconducting polymers, wherein the gate connection applies a field to the semiconductor polymers across a dielectric layer to modulate conduction along the semiconducting polymers between the source contact and the drain contact; and treating the semiconducting polymers, wherein the treating includes a chemical treatment that controls a carrier density, carrier mobility, threshold voltage, and/or contact resistance of the ofet.. .
The Regents Of The University Of California

Embedded sige process for multi-threshold pmos transistors

An integrated circuit and method having a first pmos transistor with extension and pocket implants and with sige source and drains and having a second pmos transistor without extension and without pocket implants and with sige source and drains. The distance from the sige source and drains to the gate of the first pmos transistor is greater than the distance from the sige source and drains to the gate of the second pmos transistor and the turn on voltage of the first pmos transistor is at least 50 mv higher than the turn on voltage of the second pmos transistor..
Texas Instruments Incorporated

Integrated circuits having tunnel transistors and methods for fabricating the same

Integrated circuits including tunnel transistors and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes forming a lower source/drain region in and/or over a semiconductor substrate.
Globalfoundries Singapore Pte. Ltd.

Tunneling field effect transistors with a variable bandgap channel

Tunneling field effect transistors (tfets) including a variable bandgap channel are described. In some embodiments, one or more bandgap characteristics of the variable bandgap channel may be dynamically altered by at least one of the application or withdrawal of a force, such as a voltage or electric field.

Support for long channel length nanowire transistors

A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component.
International Business Machines Corporation

Hybrid high electron mobility transistor and active matrix structure

Hybrid high electron mobility field-effect transistors including inorganic channels and organic gate barrier layers are used in some applications for forming high resolution active matrix displays. Arrays of such high electron mobility field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes.
International Business Machines Corporation

Imaging device, operating the same, module, and electronic device

An imaging device which can perform imaging with a global shutter system and in which transistors are shared by pixels is provided. The imaging device includes first and second photoelectric conversion elements and first to sixth transistors.
Semiconductor Energy Laboratory Co., Ltd.

Monolithic integration techniques for fabricating photodetectors with transistors on same substrate

Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing pds and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues..
Artilux, Inc.

Cell structure in intergrated circuits for eco at upper metal layer and forming spare cell structure

An integrated circuit includes a functional cell, and a spare gate cell configured to change or add a function of the functional cell in response to an engineering change order (eco). The spare gate cell includes transistors configured as a decoupling capacitor before the eco, and the spare gate cell is configured to change into an eco cell including an interconnection metal line pattern disposed in the decoupling capacitor after the eco..
Samsung Electronics Co., Ltd.

Semiconductor memory

According to one embodiment, a semiconductor memory 100 includes a memory cell array 100a composed of a plurality of sram cells 10 including nmos transistors and pmos transistors, and a bias circuit 100b connected to a ground gnd1 or power supply voltage vdd1 of the memory cell array 100a. The bias circuit 100b includes nmos transistors 121, 122, 133 and 134 that are same as the nmos transistors of the sram cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, and pmos transistors 111 and 112 that are same as the pmos transistors of the sram cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion.
Kabushiki Kaisha Toshiba

High-voltage transistor having shielding gate

A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region..
Kabushiki Kaisha Toshiba

Semiconductor device including transistors having different threshold voltages

A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a first tin layer to contact the first high-dielectric layer, and a first gate metal on the first tin layer, the second gate stack includes a second high-dielectric layer, a second tin layer to contact the second high-dielectric layer, and a second gate metal on the second tin layer, the third gate stack includes a third high-dielectric layer, a third tin layer to contact the third high-dielectric layer, and a third gate metal on the third tin layer, and the fourth gate stack includes a fourth high-dielectric layer, a fourth tin layer to contact the fourth high-dielectric layer, and a fourth gate metal on the fourth tin layer, the first through fourth thicknesses of the tin layers being different.. .
Samsung Electronics Co., Ltd.

Electrostatic discharge protection circuit

In the disclosure, an electrostatic discharge (esd) protection circuit is coupled between a first power rail and a second power rail to discharge any esd stress. The esd protection circuit includes a detection circuit, a triggering circuit, and a dual silicon controlled rectifier (dscr) device.
Novatek Microelectronics Corp.

Lateral-diode, vertical-scr hybrid structure for high-level esd protection

A lateral p-n diode in the center of and surrounded by a vertical silicon-controlled rectifier (scr) forms an electro-static-discharge (esd) protection structure. The lateral p-n diode has a cross-shaped p+ diode tap with four rectangles of n+ diode regions in each corner of the cross.
Hong Kong Applied Science & Technology Research Institute Company Limited

Methods of forming cmos based integrated circuit products using disposable spacers

Disclosed herein is a method of forming a cmos integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material..
Globalfoundries Inc.

Integrated circuitry and methods of forming transistors

Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor.
Micron Technology, Inc.

Split gate embedded flash memory and forming the same

Provided is a split-gate embedded flash memory cell and method for forming the same. The flash memory cell includes split-gate transistors in which the control gate is aligned with respect to the floating gate without the use of a photolithographic patterning operation to pattern the material from which the control gates are formed.
Wafertech, Llc

Memory device

A memory device according to one embodiment includes cell transistors; and a controller which is configured to write data in a first page and a second page and read data from the first and second pages, and when the controller writes data in the second page of the cell transistors with data written in the first page, reads data from the first page, uses a first value or a second value for a first parameter based on the read data, and uses a third value or a fourth value for a second parameter based on the read data.. .
Kabushiki Kaisha Toshiba

Cam design for bit string lookup

In one embodiment, a programming content addressable memory (cam) comprising at least one match line, the at least one match line being preloaded to high, and being logically or-ed for all selector lines the at least one match line being inverted to low upon a match result the at least one match line comprising transistors and grounding which are activated only when a stored data value and a corresponding selector line evaluate to 1 and the corresponding selector line having a logical and with the stored data value, wherein the programming cam is implemented as a bit indexed explicit replication (bier) table. Related apparatus, systems and methods are also described..
Cisco Technology, Inc.

Memory device

According to one embodiment, a memory device includes first and second memory cells including first and second transistors, respectively, and third and fourth transistors. First and second memory cells include first and second variable resistance elements, respectively.
Kabushiki Kaisha Toshiba

Method for the characterization and monitoring of integrated circuits

A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state.
International Business Machines Corporation

Substrate bias circuit and biasing a substrate

A substrate bias circuit and method for biasing a substrate are provided. A substrate bias circuit includes a first voltage source, a second voltage source, a diode coupled between the first voltage source and the second voltage source, and a plurality of transistors, each transistor in the plurality of transistors having a substrate terminal.
Freescale Semiconductor, Inc.

Method and an active negative-capacitor circuit to cancel the input capacitance of comparators

A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator.
Tensorcom, Inc.

Self-feedback control circuit

A self-feedback control circuit is connected to a controller area network bus for controlling a high-level output and a low-level output, comprising a controller area network driving circuit and a replica circuit. The replica circuit is connected in parallel with the controller area network driving circuit and comprises an upper feedback path and a lower feedback path.
Amazing Microelectronic Corp.

Harmonic mixer having two transistors driven complimentarily

A harmonic mixer that suppresses the degradation of the conversion efficiency is disclosed. That harmonic mixer includes an input transmission line, an output transmission line, and two transistors connected in parallel between the input transmission line and the output transmission line.
Sumitomo Electric Industries, Ltd.



Transistors topics:
  • Transistors
  • Semiconductor
  • Semiconductor Device
  • Integrated Circuit
  • High Speed
  • Photodiode
  • Memory Effect
  • Silicon Nitride
  • Enhancement
  • Ion Implant
  • Ion Channel
  • Interrupted
  • Reference Voltage
  • Semiconductor Devices
  • Semiconductor Substrate


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