|| List of recent Transistors-related patents
|Method of making a dynamic random access memory array|
The present invention is related to microelectronic technologies, and discloses specifically a method of making a dynamic random access memory (dram) array. The dram array uses vertical mos field effect transistors as array devices for the dram, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical mos field effect transistor array devices.
|Novel dual-tone resist formulations and methods|
Dual tone photoresist formulations comprising a photoacid generator are described and employed in fabrication techniques, including methods of making structures on substrates, and more particularly, methods of making electronic devices (e.g. Transistors and the like) on flexible substrates wherein two patterns are formed simultaneously in one layer of photoresist..
An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation.
|Methods for fabricating display structures|
An electronic device display may have a color filter layer and a thin film transistor layer. A layer of liquid crystal material may be interposed between the color filter layer and the thin film transistor layer.
|Liquid crystal display device and manufacturing method thereof|
Provided is a liquid crystal display device including: gate lines formed in a first direction on a second transparent substrate; data lines formed in a second direction; first transparent common electrodes; a protective insulating film; transparent pixel electrodes arranged in the first direction and the second direction and formed so as to be opposed to the first transparent common electrodes on a surface of the protective insulating film; thin film transistors connected to the transparent pixel electrodes; a second transparent common electrode formed on the surface of the protective insulating film; and a liquid crystal layer formed on the protective insulating film, the transparent pixel electrodes, and the second transparent common electrode. The second transparent common electrode covers the gate lines and the data lines through intermediation of the protective insulating film..
|Pixel array substrate|
A pixel array substrate includes a substrate, a plurality of thin-film transistors disposed on the substrate, a first insulating layer covering the thin-film transistors and the substrate, a common electrode disposed on the first insulating layer, a second insulating layer covering the first insulating layer and the common electrode, and a plurality of pixel electrodes disposed on the second insulating layer. Each thin-film transistor includes a drain electrode.
|Digital-to-analog converter circuit and display driver|
Provided first and second reference voltage set wherein the first reference voltage set includes a part or all of reference voltages of the second reference voltage set, and a decoder including first and second sub-decoder sections that select q reference voltages from first and second reference voltage sets according to upper bits of the input digital signal and transfer the so selected reference voltages to the first to qth nodes, and third and fourth sub-decoder sections that select first and second voltages from the q reference voltages transferred to the first to qth nodes according to lower bits of the input digital signal and transfer the so selected voltages to the first to pth nodes. The first and third sub-decoder sections are made up of first conductivity type transistors, whilst the second and fourth sub-decoder sections are made up of second conductivity type transistors.
A display device includes: a pixel array unit with pixel circuits disposed in matrix form, the pixel circuit including a driving transistor, an electro-optic element, a storage-capacitor, and a sampling transistor, with the electro-optic element emitting light by generating a driving current based on information stored in the storage-capacitor at the driving transistor to be applied to the electro-optic element; and a control unit, of which the output stage includes a buffer transistor, to output a pulse signal for driving the pixel array unit from the buffer transistor; wherein the pixel array unit and the control unit are formed with long laser beam irradiation to be scanned in the vertical direction; and with the control unit, buffer transistors for outputting a pulse signal for sampling to an input video signal to each signal line are arrayed in a column in the longitudinal direction of the laser beam irradiation.. .
|Current-steering digital-to-analog converter with cancellation of dynamic distortion|
A digital to analog converter includes a first switch, a second switch, and a driver module. The first switch includes a first differential pair of transistors connected to first inputs to receive digital data for conversion to analog data based on a clock signal output by a clock, and first outputs to output the analog data.
|Method for low power low noise input bias current compensation|
Low power low noise input bias current compensation for an amplifier input stage is provided by recycling the tail current of the differential pair transistors. A local amplifier regulates the tail current and buffers the base current of the tail current transistor, which is mirrored back to the input transistors to provide input bias current compensation..
|Circuit with a plurality of bipolar transistors and method for controlling such a circuit|
A circuit includes a bipolar transistor circuit including a first node, a second node, and a plurality of bipolar transistors coupled in parallel between the first node and the second node. The circuit further includes a drive circuit configured to switch on a first group of the plurality of bipolar transistors, the first group including a first subgroup and a second subgroup and each of the first subgroup and the second subgroup including one or more of the bipolar transistors.
The present invention relates to a tristate gate (1000, 2000) comprising an output port (1400) and at least two transistors (1200, 1300; 2200, 2300), each having at least a first and a second gate, configured such that a high-impedance value (z) on the output port is set by controlling the threshold voltage of at least one of the transistors.. .
|Light emitting diode module|
A light emitting diode module includes a light emitting unit and a light emitting diode circuit. The light emitting diode circuit includes four transistors and a storage capacitor.
|Hybrid plasma-semiconductor transistors, logic devices and arrays|
A hybrid plasma semiconductor device has a thin and flexible semiconductor base layer. An emitter region is diffused into the base layer forming a pn-junction.
|Transistors having features which preclude straight-line lateral conductive paths from a channel reqion to a source/drain reqion|
Some embodiments include transistors having a channel region under a gate, having a source/drain region laterally spaced from the channel region by an active region, and having one or more dielectric features extending through the active region in a configuration which precludes any straight-line lateral conductive path from the channel region to the source/drain region. The dielectric features may be spaced-apart islands in some configurations.
|Transistors with an extension region having strips of differing conductivity type|
A transistor includes a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.. .
|Densely packed standard cells for integrated circuit products, and methods of making same|
One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively.
|Non-planar transitor fin fabrication|
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the doping of fins within non-planar transistors, wherein a conformal blocking material layer, such as a dielectric material, may be used to achieve a substantially uniform doping throughout the non-planar transistor fins..
|Innovative approach of 4f2 driver formation for high-density rram and mram|
Some embodiments of the present disclosure relate to a memory array comprising memory cells having vertical gate-all-around (gaa) selection transistors. In some embodiments, the memory array has a source region disposed within an upper surface of a semiconductor body, and a semiconductor pillar of semiconductor material extending outward from the upper surface of the semiconductor body and having a channel region and an overlying drain region.
|Memory device having stitched arrays of 4 f+hu 2 +l memory cells|
A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts..
|Integrated circuitry and methods of forming transistors|
Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor.
|Non-volatile memory, writing method for the same, and reading method for the same|
A non-volatile memory of an embodiment includes a plurality of memory cells, each of the memory cells including a plurality of transistors including a first to fourth transistors, a first non-volatile element, a second non-volatile element, a first node, and a second node, the first and second transistors being connected in series with the first non-volatile element, the third and fourth transistors being connected in series with the second non-volatile element, the first node being disposed between the first and second transistors, the second node being disposed between the third and fourth transistors, gates of the first and third transistors being connected to one of first wiring lines, a gate of the second transistor being connected to the second node, a gate of the fourth transistor being connected to the first node, the first transistor being connected between one of second wiring lines and the first node.. .
|Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode|
A semiconductor device includes a gate electrode structure of a transistor, the gate electrode structure being positioned above a semiconductor region and having a gate insulation layer that includes a high-k dielectric material, a metal-containing cap material positioned above the gate insulation layer, and a gate electrode material positioned above the metal-containing cap material. A bottom portion of the gate electrode structure has a first length and an upper portion of the gate electrode structure has a second length that is different than the first length, wherein the first length is approximately 50 nm or less.
A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor.
|Signal processing device|
A plurality of writing transistors are connected in series, and a gate of a pass transistor, an input terminal of an inverter, or the like is directly or indirectly connected to each connection portion of the writing transistors. For example, a signal processing device includes first to third pass transistors, one semiconductor layer, and first to third wirings that overlap with the semiconductor layer and do not overlap with each other.
|Tft with insert in passivation layer or etch stop layer|
Embodiments disclosed herein generally relate to thin film transistors with one or more trenches to control the threshold voltage and off-current and methods of making the same. In one embodiment, a semiconductor device can include a substrate comprising a surface with a thin film transistor formed thereon, a first passivation layer formed over the thin film transistor, a trench formed within the first passivation layer and a second passivation layer formed over the first passivation layer and within the trench..
|Low-resistivity p-type gasb quantum wells for low-power electronic devices|
A semiconductor device including a heterostructure having at least one low-resistivity p-type gasb quantum well is provided. The heterostructure includes a layer of inwal1−was on a semi-insulating (100) inp substrate, where the inwal1−was is lattice matched to inp, followed by an alasxsb1−x buffer layer on the inwal1−was layer, an alasxsb1−x spacer layer on the buffer layer, a gasb quantum well layer on the spacer layer, an alasxsb1−x barrier layer on the quantum well layer, an inyal1−ysb layer on the barrier layer, and an inas cap.
|Non-volatile memory having 3d array of read/write elements with vertical bit lines and select devices and methods thereof|
A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them.
|Embedded non-volatile memory|
The present invention is a method of incorporating a non-volatile memory into a cmos process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard cmos process (i) after the mos transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the mos transistors) and (ii) before the salicided contacts to those mos transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide).
|Methods and apparatus to form thin film nanocrystal integrated circuits on ophthalmic devices|
This invention discloses methods and apparatus to form thin film nanocrystal integrated circuit transistors upon three dimensionally formed insert devices. In some embodiments, the present invention includes incorporating the three dimensional surfaces with thin film nanocrystal integrated circuit based thin film transistors, electrical interconnects and energization elements into an insert for incorporation into ophthalmic lenses.
|Methods and apparatus for all digital multi-level outphasing using bandwidth reduction|
For use in a transmitter in a wireless network, a transmitter apparatus is configured for digital multi-level outphasing. The apparatus includes a bandwidth reduction (bwr) modulator block configured to receive a phase modulated carrier and reduce a bandwidth of the phase modulated carrier using amplitude modulation.
|Semiconductor device including memory cell having charge accumulation layer|
A semiconductor device includes mos transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The mos transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively.
|Semiconductor memory device and system having the same|
A semiconductor memory device includes a first dummy transistor coupled to a bit line, a first select transistor formed where a first selection line surrounds a vertical channel layer, a second dummy transistor coupled to a common source line, a second select transistor formed where a second selection line surrounds the vertical channel layer, and main cell transistors coupled between the first and second select transistors.. .
|Circuit for reverse biasing inverters for reducing the power consumption of an sram memory|
Cmos integrated circuits with very low consumption when idle, and notably the sram volatile memories, are provided. The inverters of the circuit are made up of an nmos transistor and a pmos transistor.
|Nonvolatile semiconductor memory device|
A nonvolatile semiconductor memory device includes: a memory cell array having a plurality of memory cells arranged in a matrix; a reference bit line; a reference source line; at least one reference cell including first and second transistors serially connected between these lines; a reference word line connected to the gate of the first transistor; and a reference driver circuit configured to control the gate voltage of the second transistor.. .
|Ophthalmic device with thin film anocrystal integrated circuits on ophthalmic devices|
This invention discloses methods and apparatus to form thin film nanocrystal integrated circuit transistors upon three-dimensionally formed insert pieces. In some embodiments, the present invention includes incorporating the three-dimensional surfaces with thin film nanocrystal integrated circuit based thin film transistors, electrical interconnects, and energization elements into an insert piece for incorporation into ophthalmic device.
|Pixel and organic light emitting display device using the same|
A pixel for a display panel includes an organic light emitting diode and two driving transistors. The first driving transistor supplies current from a first power source to the organic light emitting diode based on a voltage applied to a first node.
|Pixel of an organic light emitting display device and organic light emitting display device|
A pixel of an organic light emitting display device includes a first capacitor, second capacitor, and a number of transistors. The first capacitor stores an emission data voltage from a data line.
|Display unit, display panel, and method of driving the same, and electronic apparatus|
A display unit (1) includes a light-emitting device (13) and a pixel circuit (12) in each pixel (11), and a drive section (20) configured to drive the pixel circuit (12). The pixel circuit (12) includes a drive transistor (tr1) configured to drive the light-emitting device (13), and a write transistor (tr2) configured to control application of a signal voltage corresponding to an image signal to a gate of the drive transistor (tr1).
|Display apparatus incorporating varying threshold voltage transistors|
This disclosure provides systems, methods and apparatus for controlling pixels of a display apparatus. An apparatus including a plurality of pixels can be controlled by a control matrix.
|Method and system for providing automatic gate bias and bias sequencing for field effect transistors|
A feedback gate bias circuit for use in radio frequency amplifiers to more effectively control operation of ldfet, ganfet, gaasfet, and jfet type transistors used in such circuits. A transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device to device variations.
|Metal-oxide-semiconductor (mos) voltage divider with dynamic impedance control|
Metal-oxide-semiconductor (mos) voltage divider with dynamic impedance control. In some embodiments, a voltage divider may include two or more voltage division cells, each voltage division cell having a plurality of metal-oxide-semiconductor (mos) transistors, a least one of the plurality of mos transistors connected to a signal path and at least another one of the plurality of mos transistors connected to a control path, the voltage division cell configured to provide a voltage drop across the signal path based upon a control signal applied to the control path..
An object is to prevent malfunction of a power device. In a semiconductor device for driving a power device for power supply, a buffer circuit and a level-shift circuit are configured by transistors having the same conductivity type.
|Light emitting diode driver|
A driver circuit for driving light emitting diodes (leds). The driver circuit includes a string of leds divided into n groups and the n groups of leds is electrically connected to each other in series, where a downstream end of group m−1 is electrically connected to the upstream end of group m.
|Pixel circuit and display device|
A pixel circuit able to prevent a spread of the terminal voltages of drive transistors inside a panel and in turn able to reliably prevent deterioration of uniformity, wherein a source of a tft serving as a drive transistor is connected to an anode of a light emitting element, a drain is connected to a power source potential, a capacitor is connected between a gate and source of the tft, and a source potential of the tft is connected to a fixed potential through a tft serving as a switch transistor and wherein pixel circuit lines are connected by an upper line and bottom line and are arranged in parallel with pixel circuit power source voltage lines so as not to have intersecting parts.. .
|Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle|
Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region.
|Semiconductor device and method for forming the same|
A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a peripheral region including the first region, the second region, and a third region; a second active region defined by the device isolation film contained in the semiconductor substrate of the third region; a buried metal layer buried in the recess; a first conductive layer formed over the semiconductor substrate of the first region; and a second conductive layer formed over the semiconductor substrate of the second region, wherein the first conductive layer or the second conductive layer is formed over the semiconductor substrate of the third region. A three-dimensional dual gate is formed in a peripheral region, such that performance or throughput of transistors is maximized even in the peripheral region..
|Structure and method for reducing floating body effect of soi mosfets|
The present invention generally relates to a semiconductor structure and method, and more specifically, to a structure and method for reducing floating body effect of silicon on insulator (soi) metal oxide semiconductor field effect transistors (mosfets). An integrated circuit (ic) structure includes an soi substrate and at least one mosfet formed on the soi substrate.
A semiconductor device includes a transistor array, including first transistors and second transistors. Gate electrodes of the first transistors are disposed in first trenches in a first main surface of a semiconductor substrate, and gate electrodes of the second transistors are disposed in second trenches in the first main surface.
A switching component includes a control element and an integrated circuit. The integrated circuit includes a first transistor element and a second transistor element electrically connected in parallel to the first transistor element.
|Stacked carbon-based fets|
Methods and systems for forming stacked transistors. Such methods include forming a lower channel layer on a substrate; forming a pair of vertically aligned gate regions over the lower channel layer; forming a pair of vertically aligned source regions and a pair of vertically aligned drain regions on the lower channel material, each pair separated by an insulator; forming an upper channel material over the source regions, drain regions, and gate regions; and providing electrical access to the source, drain, and gate regions..
|Thin film transistor substrate and display apparatus|
A thin film transistor (tft) substrate comprises a substrate, a plurality of pixel electrodes, a gate layer, an active layer, a first source layer and a second source layer, and a drain layer. The pixel electrodes are disposed on the substrate.
A semiconductor device includes a first insulating film formed on a memory cell region of the semiconductor substrate, a first polysilicon layer formed on the first insulating film, and memory cell transistors formed on the first polysilicon layer, each including a charge storage layer, an inter-electrode insulating film and a control gate electrode. The semiconductor device further includes a laminated structure formed on a peripheral circuit region of the semiconductor substrate that includes a second insulating film, a second polysilicon layer, a third insulating film, a third polysilicon layer, a fourth insulating film formed from the same material as a material of the inter-electrode insulating film, and a first electrode formed from the same material as a material of the control gate electrode.
A display device comprising including a plurality of pixels arranged in the shape of a matrix above a substrate, and a plurality of thin film transistors arranged corresponding to each of the plurality of pixel having an organic el layer, the device comprising; a planarized film covering the thin film transistor and a wire connected with the thin film transistor; a reflecting layer formed above the planarized film; a light path length expanded layer covering the reflecting layer; and a pixel transparent electrode formed above the light path length expanded layer.. .
A display device includes a thin film transistor substrate including transistors each controlling the amount of light emission of each pixel and a counter substrate arranged to be placed over the thin film transistor substrate. The thin film transistor substrate includes an insulating substrate as a base material, a circuit layer including the transistors formed on the insulating substrate, an organic layer interposed between two electrodes, and an organic insulating layer arranged between the circuit layer and the organic layer and formed of an organic insulating material formed thicker in each pixel region than in an inter-pixel region..
|Pixel circuit and display apparatus using the same|
A pixel circuit includes one organic light emitting diode, five first transistors and two capacitors. The first and third transistors have terminals coupled to a first voltage.
|Organic light emitting diode display|
A display includes a switching transistor connected to a scan line and data line, a driving transistor connected to the switching transistor, a storage capacitor between a voltage line and the driving transistor, and an organic light emitting diode connected to the driving transistor. The data line and voltage line are at different layers, and the data line and a gate electrode of the driving transistor are at different layers.
|Organic light emitting display|
An organic light emitting diode (“oled”) display includes: a substrate including a plurality of pixel areas; a plurality of switching transistors and a plurality of driving transistors on the substrate; and an organic light emitting element respectively connected to a switching transistor and a driving transistor among the plurality of switching transistors and the plurality of driving transistors. The driving transistor includes a semiconductor which overlaps a plurality of adjacent pixel areas..
|Non-volatile semiconductor memory device|
A non-volatile semiconductor memory device includes a plurality of series-coupled fixed resistance elements, a plurality of reference cell transistors, and reference word lines coupled to gates of the reference cell transistors, a first reference data line coupled to one end of a resistance path in which a plurality of fixed resistance elements are arranged, and a second reference data line coupled in common to one ends of the reference cell transistors. The other end of each of the reference cell transistors is coupled to one of coupling points of the fixed resistance elements or the other end of the resistance path..
|Transistors, memory cells and semiconductor constructions|
Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate.
|Diketopyrrolopyrrole polymers for use in organic semiconductor devices|
The present invention relates to polymers (i), or (ii), and their use as organic semiconductor in organic devices, especially in organic photovoltaics (solar cells) and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties.
|System and methods for memory expansion|
This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel.
|Methods of fabricating quantum well field effect transistors having multiple delta doped layers|
Methods of fabricating quantum well field effect transistors are provided. The methods may include forming a first barrier layer including a first delta doped layer on a quantum well layer and forming a second barrier layer including a second delta doped layer selectively on a portion of the first barrier layer in a first region of the substrate.
|Semiconductor device and high-frequency module|
Reduction of intermodulation distortion in a high-frequency switch is achieved. A semiconductor device (1) includes an antenna terminal (ant_lb), plural external terminals (rx_lb, tx_lb, trx_lb, term_lb), plural first high-frequency switches (101 to 104), and plural control terminals.
|Reduced stress high voltage word line driver|
Exemplary embodiments of the present invention disclose a method and system for asserting a voltage transition from a low voltage to a high voltage with a voltage difference between the low and high voltages on a word line with a word line driver logic that is composed of thin-oxide mos transistors, wherein the thin-oxide mos transistors experience less than the voltage difference on the word line between any two of a source, a drain, and a gate. In a step, charging the word line from the low voltage to an intermediate voltage level.
|Pixel circuit, display device, and method of driving pixel circuit|
A pixel circuit, display device, and method of driving a pixel circuit enabling source-follower output with no deterioration of luminance even with a change of the current-voltage characteristic of the light emitting element along with elapse, enabling a source-follower circuit of n-channel transistors, and able to use an n-channel transistor as an el drive transistor while using current anode-cathode electrodes, wherein a source of a tft 111 as a drive transistor is connected to an anode of a light emitting element 114, a drain is connected to a power source potential vcc, a capacitor c111 is connected between a gate and source of the tft 111, and a source potential of the tft 111 is connected to a fixed potential through a tft 113 as a switching transistor.. .
|Image display device and method of controlling pixel circuit|
A pixel circuit includes a first transistor coupled to a light emitting element, a first capacitor coupled to the first transistor, a second transistor coupled to the first capacitor, a third transistor coupled between the second transistor and a data line; and a second capacitor having a first electrode coupled between the second and third transistors. The first transistor controls an amount of current supplied to the light emitting element based on a first data voltage while a second data voltage is stored in the second capacitor.
|Touch-sensor-embedded display panel, display device provided therewith, and method for driving touch-sensor-embedded display panel|
A driving pixel (21) is constituted by: a thin film transistor (t1); a pixel electrode (epix1); a driving common electrode (com1); and a liquid crystal capacitance (clc1) which is formed between the pixel electrode (epix1) and the driving common electrode (com1). A sensing pixel (22) is constituted by a thin film transistor (t2), a pixel electrode (epix2), a sensing common electrode (com2), and a liquid crystal capacitance (clc2) which is formed between the pixel electrode (epix2) and the sensing common electrode (com2).
|Complementary metal oxide semiconductor power amplifier|
An rf power amplifier circuit is disclosed. A driver amplifier stage includes a first set of a plurality of amplifier transistors in a cascode configuration, a driver amplifier stage input, and a driver amplifier stage output.
|Inductive load power switching circuits|
Power switching circuits including an inductive load and a switching device are described. The switches devices can be either low-side or high-side switches.
|Boost capacitor sharing architecture for power supply active balancing systems|
An apparatus includes multiple first channels configured to be coupled to a first boost capacitor and multiple second channels configured to be coupled to a second boost capacitor. Each channel includes a transistor switch and a gate driver configured to drive the transistor switch.
|Metal contacts to group iv semiconductors by inserting interfacial atomic monolayers|
Techniques for reducing the specific contact resistance of metal-semiconductor (group iv) junctions by interposing a monolayer of group v or group iii atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group iv semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (fet).
|Trench isolation structures and methods for bipolar junction transistors|
Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate.
|Bipolar junction transistors with self-aligned terminals|
Device structures, fabrication methods, and design structures for a bipolar junction transistor. A semiconductor material layer is formed on a substrate and a mask layer is formed on the semiconductor material layer.
|Semiconductor device and manufacturing method of the same|
The present invention provides a semiconductor device which suppresses a short circuit and a leakage current between a semiconductor film and a gate electrode generated by a break or thin thickness of a gate insulating film in an end portion of a channel region of the semiconductor film, and the manufacturing method of the semiconductor device. Plural thin film transistors which each have semiconductor film provided over a substrate continuously, conductive films provided over the semiconductor film through a gate insulating film, source and drain regions provided in the semiconductor film which are not overlapped with the conductive films, and channel regions provided in the semiconductor film existing under the conductive films and between the source and drain regions.
|Semiconductor-on-insulator integrated circuit with reduced off-state capacitance|
An integrated circuit assembly comprises an insulating layer, a semiconductor layer, a handle layer, a metal interconnect layer, and transistors. The insulating layer has a first surface, a second surface, and a hole extending from the first surface to the second surface.
|Self-aligned contacts for replacement metal gate transistors|
Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface of the gate, depositing an insulating layer above the semiconductor device, and planarizing the insulating layer using the blocking region as a planarization stop.
|Hemt transistors consisting of (iii-b)-n wide bandgap semiconductors comprising boron|
An electronic hemt transistor structure comprises a heterojunction formed from a first layer, called a buffer layer, of a first wide bandgap semiconductor material, and a second layer of a second wide bandgap semiconductor material, with a bandgap width eg2 larger than that eg1 of the first material, and a two-dimensional electron gas flowing in a channel confined in the first layer under the interface of the heterojunction. The first layer furthermore comprises a layer of a bgan material under the channel, with an average boron concentration of at least 0.1%, improving the electrical performance of the transistor.
|Avalanche energy handling capable iii-nitride transistors|
A semiconductor device includes a gan fet with an overvoltage clamping component electrically coupled to a drain node of the gan fet and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the gan fet.
|Display and method for manufacturing display|
A display includes a pixel array part with pixels that each have at least one transistor whose conduction state is controlled by a drive signal input to a control terminal, and a scanner including a plurality of buffers that are formed of transistors. The buffers correspond to a pixel arrangement and output a drive signal to the control terminals of the transistors of the pixels.