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 Image sensor pixels having dual gate charge transferring transistors patent thumbnailnew patent Image sensor pixels having dual gate charge transferring transistors
An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a floating diffusion node, and a charge transferring transistor.
Semiconductor Components Industries, Llc


 Bootstrapping circuit and unipolar logic circuits using the same patent thumbnailnew patent Bootstrapping circuit and unipolar logic circuits using the same
Exemplary embodiments of the present disclosure are directed to a bootstrapping module and logic circuits utilizing the bootstrapping module to compensate for a weak high condition. The bootstrapping module can be implemented using transistors have a single channel type that is the same as the channel type of transistors utilized in the logic circuits such that a truly unipolar circuit can be realized while addressing the weak high problem of such unipolar circuits..
Yale University


 Power-on reset circuit with reset transition based on vt patent thumbnailnew patent Power-on reset circuit with reset transition based on vt
A power-on-reset (por) circuit is suitable for use in an integrated circuit including at least one cmos logic block that includes pmos and nmos transistors respectively characterized by threshold voltages vtp and vtn, the cmos circuitry operable with a power supply voltage vdd. The por circuit is operable to transition between a por_active state and a por_inactive state, including outputting a corresponding por_state signal.
Texas Instruments Incorporated


 Voltage follower circuit to mitigate gain loss caused by finite output impedance of transistors patent thumbnailnew patent Voltage follower circuit to mitigate gain loss caused by finite output impedance of transistors
Methods and circuits for maximizing gain of a voltage follower circuit are provided. The method includes using a nmos voltage replica generation circuit, a pmos voltage replica generation circuit, a npn bjt voltage replica generation circuit, a n-channel jfet voltage replica generation circuit, a p-channel jfet voltage replica generation circuit and a pnp bjt voltage replica generation circuit.
Signalchip Innovations Private Limited


 Lc-tank oscillator having intrinsic low-pass filter patent thumbnailnew patent Lc-tank oscillator having intrinsic low-pass filter
An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two p-type transistors and two n-type transistors. Source electrodes of the two p-type transistors are coupled to a supply voltage, and gate electrodes of the two p-type transistors are coupled to the two output terminals, respectively.
Mediatek Inc.


 Device and  reducing switching losses in power transistors patent thumbnailnew patent Device and reducing switching losses in power transistors
A device including a first and second monitoring unit, the first monitoring unit detecting a first voltage potential and the second monitoring unit detecting a second voltage potential, the monitoring units comparing the first voltage potential and the second voltage potential to the value of the supply voltage and activate a control unit as a function of the comparisons, the control unit determining a switching point in time of a second power transistor, and an arrangement being present which generates current when the second power transistor is being switched on, the current changing the first voltage potential, and the control unit activates a first power transistor when the first voltage potential has the same value as the supply voltage, so that the first power transistor is de-energized.. .
Robert Bosch Gmbh


 Vertical-type organic light-emitting transistors with reduced leakage current and  fabricating the same patent thumbnailnew patent Vertical-type organic light-emitting transistors with reduced leakage current and fabricating the same
A vertical-type organic light-emitting transistor for reducing the off-state leakage current to improve the current and on-off ratio includes a gate electrode, a lower semiconductor layer disposed on the gate electrode, a source electrode disposed on the lower semiconductor layer, and a source insulation film disposed on the source electrode and covering top and sides of the source electrode, wherein the lower semiconductor layer is configured such that an electric charge is injected into the lower semiconductor layer from the source electrode when voltage is applied to the gate electrode.. .
Seoul National University R&db Foundation


 Display backplane, manufacturing method thereof and display device patent thumbnailnew patent Display backplane, manufacturing method thereof and display device
The present invention provides a display backplane and a manufacturing method thereof, as well as a display device. The display backplane comprising: a substrate; an array of organic light emitting elements and an array of transistors for driving and controlling the array of organic light emitting elements formed on the substrate; and a heat insulation layer formed between the array of organic light emitting elements and the array of transistors, wherein the heat insulation layer is provided with a heat insulation layer via hole, through which the array of transistors is connected with the array of organic light emitting elements.
Boe Technology Group Co., Ltd.


 Gate-all-around field effect transistors with horizontal nanosheet conductive channel structures for mol/inter-channel spacing and related cell architectures patent thumbnailnew patent Gate-all-around field effect transistors with horizontal nanosheet conductive channel structures for mol/inter-channel spacing and related cell architectures
A gate-all-around (gaa) field effect transistor (fet) can include a horizontal nanosheet conductive channel structure having a width in a horizontal direction in the gaa fet, a height that is perpendicular to the horizontal direction, and a length that extends in the horizontal direction, where the width of the horizontal nanosheet conductive channel structure defines a physical channel width of the gaa fet. First and second source/drain regions can be located at opposing ends of the horizontal nanosheet conductive channel structure and a unitary gate material completely surrounding the horizontal nanosheet conductive channel structure..
Samsung Electronics Co., Ltd.


 High doped iii-v source/drain junctions for field effect transistors patent thumbnailnew patent High doped iii-v source/drain junctions for field effect transistors
A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a iii-v material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped iii-v material between doped iii-v materials, the doped iii-v materials including a dopant in an amount in a range from about le18 to about le20 atoms/cm3 and contacting the epitaxial contacts.. .
Stmicroelectronics, Inc.


new patent

Vertical power transistor with thin bottom emitter layer and dopants implanted in trenches in shield area and termination rings

Various improvements in vertical transistors, such as igbts, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer.
Maxpower Semiconductor, Inc.

new patent

Production of transistor arrays

A method of producing a transistor array, comprising an array of addressing conductors each providing the source electrodes of a respective set of transistors and at least part of a conductive connection between a respective driver terminal and said source electrodes; wherein the method comprises: forming a conductor layer on a support; and displacing a plurality of portions of said conductor layer relative to other portions of said conductor layer to create from said conductor layer at least (i) said array of addressing conductors and an array of drain conductors at said first level, (ii) conductor element islands in transistor channel regions at a second level, and (iii) one or more further conductor elements at a third level.. .
Flexenable Limited

new patent

Semiconductor device

A plurality of pixel regions are aligned in a matrix in a semiconductor substrate, and each of the plurality of pixel regions includes an active region, two photoelectric conversion elements, two floating capacitance regions, and a first transistor. Each of the plurality of pixel regions includes two transfer transistors each having each of the two photoelectric conversion elements and each of the two floating capacitance regions.
Renesas Electronics Corporation

new patent

Sensors including complementary lateral bipolar junction transistors

An integrated radiation sensor for detecting the presence of an environmental material and/or condition includes a sensing structure and first and second lateral bipolar junction transistors (bjts) having opposite polarities. The first lateral bjt has a base that is electrically coupled to the sensing structure and is configured to generate an output signal indicative of a change in stored charge in the sensing structure.
International Business Machines Corporation

new patent

Semiconductor device

At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor device

A semiconductor device with a small number of transistors is provided. The semiconductor device includes a first transistor, a second transistor, a third transistor, a first wiring, and a second wiring.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Integrated circuits and devices with interleaved transistor elements, and methods of their fabrication

A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the ic, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row.
Freescale Semiconductor, Inc.

new patent

Complementary soi lateral bipolar transistors with backplate bias

A method for fabricating a complementary bipolar junction transistor (bjt) integrated structure. The method includes forming a first backplate in a monolithic substrate below a first buried oxide (box) layer.
International Business Machines Corporation

new patent

Digital circuit and manufacturing a digital circuit

According to one embodiment, a method for manufacturing a digital circuit is described comprising forming a modified rs master latch with an output for outputting an output signal comprising forming two field effect transistors which are virtually identical wherein the two formed field effect transistors are connected to each other in an rs latch type configuration and the respective threshold voltages of the two field effect transistors are set to be different from each other so that the output signal of the modified rs master latch in response to an rs latch forbidden input transition has a predetermined defined logic state, forming an rs slave latch having a set input and a reset input and connecting the set input or the reset input of the rs-slave latch to the output of the modified rs master latch.. .
Infineon Technologies Ag

new patent

Complementary metal-oxide-semiconductor field-effect transistor and method thereof

This invention application provides a complementary metal-oxide-semiconductor field-effect transistor and method thereof. The transistor comprises a semiconductor substrate, a n-type field-effect transistor positioned in the semiconductor substrate, and a p-type field-effect transistor positioned in the semiconductor substrate and spaced apart the n-type field-effect transistor.
Zing Semiconductor Corporation

new patent

Sram cell for interleaved wordline scheme

In some embodiments, the present disclosure relates to a static random access memory (sram) device. The sram device includes a plurality of sram cells arranged in a plurality of rows and a plurality of columns, wherein respective sram cells include respective pairs of complementary data storage nodes to store respective data states.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Pixel circuit and display device

A pixel circuit able to prevent a spread of the terminal voltages of drive transistors inside a panel and in turn able to reliably prevent deterioration of uniformity, wherein a source of a tft serving as a drive transistor is connected to an anode of a light emitting element, a drain is connected to a power source potential, a capacitor is connected between a gate and source of the tft, and a source potential of the tft is connected to a fixed potential through a tft serving as a switch transistor and wherein pixel circuit lines are connected by an upper line and bottom line and are arranged in parallel with pixel circuit power source voltage lines so as not to have intersecting parts.. .
Sony Corporation

new patent

Display device

A display device includes a display panel including data lines, gate lines crossing the data lines, and pixels arranged in a matrix form, a touch screen which is embedded in the display panel or is installed on the display panel, a data driving circuit supplying a data voltage to the data lines, a gate driving circuit supplying a gate pulse to the gate lines, and a touch sensing circuit which supplies a driving signal to lines of the touch screen and senses a touch input. The gate driving circuit alternately drives pull-down transistors connected in parallel to one gate line.
Lg Display Co., Ltd.

Level shift circuit, semiconductor device, and battery supervisory apparatus

According to one embodiment, a level shift circuit includes a first transistor, a second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor and eighth transistor. The level shift circuit also includes a first capacitance element, a second capacitance element, third capacitance element and fourth capacitance element.
Kabushiki Kaisha Toshiba

Operation of double-base bipolar transistors with additional timing phases at switching transitions

Methods and systems for operating a double-base bidirectional power bipolar transistor. Two timing phases are used to transition into turn-off: one where each base is shorted to its nearest emitter/collector region, and a second one where negative drive is applied to the emitter-side base to reduce the minority carrier population in the bulk substrate.
Ideal Power Inc.

Switching circuit

In one embodiment, a switching circuit includes a first switch comprising one or more transistors operably coupled in series with a first terminal, wherein each of the one or more transistors has a corresponding diode, a drain of each of the one or more transistors being operably coupled to a cathode of the corresponding diode; and a second switch comprising one or more transistors operably coupled in series with a second terminal, wherein each of the one or more transistors has a corresponding diode, a drain of each of the one or more transistors being operably coupled to a cathode of the corresponding diode; wherein a source of the one or more transistors of the first switch is operably coupled to a source of the one or more transistors of the second switch.. .
Reno Technologies, Inc.

Five-level inverter and application circuit of the same

A five-level inverter and its application circuit are provided. The five-level inverter is enabled to output multiple levels of voltage by controlling different conduction combinations of first, second, third, fourth, fifth, sixth, seventh, and eighth switch transistors, as well as a clamping capacitor.
Sungrow Power Supply Co., Ltd.

Switching circuit and power supply circuit provided therewith

A high-withstand-voltage normally-on transistor and a low-withstand-voltage normally-off transistor are connected in series, and diodes are provided in reverse parallel to the transistor. A gate terminal of the transistor is connected to a source terminal of the transistor, and a gate driving circuit that outputs a control signal to a gate terminal of the transistor is provided.
Sharp Kabushiki Kaisha

Organic semiconducting compounds and related optoelectronic devices

The present teachings relate to new organic semiconducting compounds and their use as active materials in organic and hybrid optical, optoelectronic, and/or electronic devices such as photovoltaic cells, light emitting diodes, light emitting transistors, and field effect transistors. The present compounds can provide improved device performance, for example, as measured by power conversion efficiency, fill factor, open circuit voltage, field-effect mobility, on/off current ratios, and/or air stability when used in photovoltaic cells or transistors.
Polyera Corporation

Transistors and methods of forming transistors

Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions.
Micron Technology, Inc.

Transistor that employs collective magnetic effects thereby providing improved energy efficiency

A device or class of devices that provides a mechanism for controlling charge current flow in transistors that employs collective magnetic effects to overcome voltage limitations associated with single-particle thermionic emission as in conventional mosfets. Such a device may include two or more magnetic stacks with an easy-in-plane ferromagnetic film sandwiched between oppositely magnetically oriented perpendicular magnetization anisotropy (pma) ferromagnets.
Board Of Regents, The University Of Texas System

Metal-oxide-semiconductor field-effect phototransistors based on single-crystalline semiconductor thin films

Mosfet phototransistors, methods of operating the mosfet phototransistors and methods of making the mosfet phototransistors are provided. The phototransistors have a buried electrode configuration, which makes it possible to irradiate the entire surface areas of the radiation-receiving surfaces of the phototransistors..
Wisconsin Alumni Research Foundation

Decoupling finfet capacitors

A semiconductor device including field-effect transistors (finfets) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors.
Taiwan Semiconductor Manufacturing Company, Ltd.

Iii-n material structure for gate-recessed transistors

Iii-n transistors with recessed gates. An epitaxial stack includes a doped iii-n source/drain layer and a iii-n etch stop layer disposed between a the source/drain layer and a iii-n channel layer.
Intel Corporation

Surface treatment and passivation for high electron mobility transistors

A high electron mobility transistor (hemt) and a method of forming the same are disclosed. The method includes epitaxially growing a first iii-v compound layer and epitaxially growing a second iii-v compound layer over the first iii-v compound layer, wherein a first native oxide layer is formed on the second iii-v compound layer.
Taiwan Semiconductor Manufacturing Company, Ltd.

Forming replacement low-k spacer in tight pitch fin field effect transistors

A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure.
Stmicroelectronics, Inc.

Tuned semiconductor amplifier

Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device.
Macom Technology Solutions Holdings, Inc.

Tuned semiconductor amplifier

Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device.
M/a-com Technology Solutions Holdings, Inc.

Apparatus and methods for forming a modulation doped non-planar transistor

Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed, which may include forming a modulation doped heterostructure, comprising forming an active portion having a first bandgap and forming a delta doped portion having a second bandgap..
Intel Corporation

Mtj memory array subgrouping method and related drive circuitry

Embodiments of the present disclosure generally relate to data storage systems, and more particularly, to a she-mram device. The she-mram device includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads.
Hgst Netherlands B.v.

Light-emitting device

A light-emitting device capable of suppressing variation in luminance among pixels is provided. A light-emitting device includes a pixel and first and second circuits.
Semiconductor Energy Laboratory Co., Ltd.

Method for fabricating contacts to non-planar mos transistors in semiconductor device

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure on a first region and a second fin-shaped structure on a second region; forming a plurality of first gate structures on the first fin-shaped structure, a plurality of second gate structures on the second fin-shaped structure, and an interlayer dielectric (ild) layer around the first gate structures and the second gate structures; forming a patterned mask on the ild layer; and using the patterned mask to remove all of the ild layer from the first region and part of the ild layer from the second region for forming a plurality of first contact holes in the first region and a plurality of second contact holes in the second region..
United Microelectronics Corp.

Systems and methods for filtering and computation using tunnelling transistors

An electrical circuit is disclosed that comprises plurality of tunneling field-effect transistors (tfets) arranged in a diffusion network matrix having a plurality of nodes wherein, for each of the tfets that is not on an end of the matrix, a drain of the tfet is electrically coupled with the source of at least one of the other tfets at a node of the matrix and a source of the tfet is electrically coupled with the drain of at least one of the other tfets at another node of the matrix. The electrical circuit further comprises a plurality of capacitors, wherein a respective one of the plurality of capacitors is electrically coupled with each node that includes the source of at least one tfet and the drain of at least one tfet.
University Of Notre Dame Du Lac

Forming replacement low-k spacer in tight pitch fin field effect transistors

A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure.
Stmicroelectronics, Inc.

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a plurality of memory blocks. The semiconductor memory device also includes a block decoder configured to output a block select signal for selecting at least one memory block of the plurality of memory blocks to at least one block word line of a plurality of word lines, and a connecting circuit including a plurality of pass transistors configured to electrically connect global lines to local lines of a plurality of memory cells included in the plurality of memory blocks in response to the block select signal.
Sk Hynix Inc.

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a memory cell array including a plurality of memory cells, connecting circuits including pass transistors coupled between global word lines and the plurality of memory cells, an address decoder coupled to block word lines coupled to gates of the pass transistors and the global word lines, and a control logic controlling the address decoder and applying a voltage pulse to the global word lines and the block word lines according to an operation state of the semiconductor memory device.. .
Sk Hynix Inc.

Nonvolatile memory

A nonvolatile memory of an embodiment includes: first through fifth wirings; and a memory cell including: a first circuit including a first magnetoresistive element and a first select transistor, the first magnetoresistive element and the first select transistor being electrically connected in series, the first magnetoresistive element including a first reference layer, a first storage layer, and a first nonmagnetic layer between the first reference layer and the first storage layer; a second circuit including a second magnetoresistive element and a second select transistor, the second magnetoresistive element and the second select transistor being electrically connected in series, the second magnetoresistive element including a second reference layer, a second storage layer, and a second nonmagnetic layer between the second reference layer and the second storage layer; a third circuit including first and second transistors; and a fourth circuit including third and fourth transistors.. .
Kabushiki Kaisha Toshiba

Voltage regulator with dropout detector and bias current limiter and associated methods

A voltage regulator includes an input terminal to receive an input voltage, an output terminal to supply an output voltage, a power transistor, a differential amplifier, a driver, a dropout detector and a bias current limiter. The differential amplifier provides a drive signal based on a difference between a voltage reference and a feedback signal corresponding to the output voltage.
Stmicroelectronics Design And Application S.r.o.

Display device

A display device comprises spacers provided between a first substrate and a second substrate, wherein the first substrate includes: seats each of which holds the spacers, respectively; data lines; gate lines; thin film transistors; pixel electrodes corresponding to pixel regions; a common electrode facing the pixel electrodes; and common wirings being electrically connected to the common electrode, and each of the common wirings includes a bent part detouring around at least one of the seats.. .
Panasonic Liquid Crystal Display Co., Ltd.

Chemically-sensitive field effect transistors, systems, and methods for manufacturing and using the same

This invention concerns chemically-sensitive field effect transistors (fets) are preferably fabricated using semiconductor fabrication methods on a semiconductor wafer, and in preferred embodiments, on top of an integrated circuit structure made using semiconductor fabrication methods. The instant chemically-sensitive fets typically comprise a conductive source, a conductive drain, and a channel composed of a one-dimensional (1d) or two-dimensional (2d) transistor material, which channel extends from the source to the drain and is fabricated using semiconductor fabrication techniques on top of a wafer.
Agilome, Inc.

Controlling the provision of power to one or more devices

Systems and methods are described herein for provisioning power to a power consumption device in a depowered state (e.g., a device not consuming current such as standby current). Aspects discussed herein relate to controlling a detector, switches, and/or an outlet such as a smart outlet.
Comcast Cable Communications, Llc

Solid-state imaging device and camera system

A solid-state imaging device and a camera system are disclosed. The solid-state imaging device includes a pixel unit and a pixel signal readout circuit.
Sony Corporation

Power amplifier module

A power amplifier module includes an amplifier transistor and a bias circuit. A first power supply voltage based on a first operation mode or a second power supply voltage based on a second operation mode is supplied to the amplifier transistor.
Murata Manufacturing Co., Ltd.

Semiconductor device

A semiconductor device includes an h-bridge driver. The h-bridge driver includes a first island on which a first power transistor and a second power transistor are mounted; a second island on which a third power transistor and a fourth power transistor are mounted; a third island on which a control circuit and a protection power transistor are mounted, the control circuit being configured to control the first, second, third and fourth power transistors, wherein the third island is allocated between the first island and the second island..
Renesas Electronics Corporation

Power source management method and power source

A power source management method and a power source are provided. The method includes: comparing a feedforward control signal with a feedback control signal by using a logic control circuit, outputting the signals after the comparison, and performing matching, to obtain control signals of switching transistors of a full-bridge topology circuit; and adjusting the control signals of the switching transistors of the full-bridge topology circuit by using the logic control circuit, so that operating duty cycles of two bridge arms on a primary side match, are symmetric within one switch period of the logic control circuit, or match for a long time, to prevent transformer biasing.
Huawei Technologies Co., Ltd

Soft current switching power supply

Embodiments of the present invention provide improved techniques and devices for reducing transformer commutation distortion caused by large load currents. Traditional power supplies which have two or more phases typically commutate a transformer during the end of each phase.
Keithley Instruments, Inc.



Transistors topics:
  • Transistors
  • Semiconductor
  • Semiconductor Device
  • Integrated Circuit
  • High Speed
  • Photodiode
  • Memory Effect
  • Silicon Nitride
  • Enhancement
  • Ion Implant
  • Ion Channel
  • Interrupted
  • Reference Voltage
  • Semiconductor Devices
  • Semiconductor Substrate


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