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Transistors patents

      

This page is updated frequently with new Transistors-related patent applications.




 Photoelectric conversion device and image-pickup apparatus patent thumbnailnew patent Photoelectric conversion device and image-pickup apparatus
In a photoelectric conversion device, groups of unit pixels are arranged in a well, where each of the unit pixels includes photoelectric conversion elements, an amplifier transistor, and transfer transistors. The photoelectric conversion device includes a line used to supply a voltage to the well, a well-contact part used to connect the well-voltage-supply line to the well, and transfer-control lines used to control the transfer transistors.
Canon Kabushiki Kaisha


 Bottom-gate thin-body transistors for stacked wafer integrated circuits patent thumbnailnew patent Bottom-gate thin-body transistors for stacked wafer integrated circuits
An integrated circuit die may include bottom-gate thin-body transistors. The bottom-gate thin-body transistors may be formed in a thinned-down substrate having a thickness that is defined by shallow trench isolation structures that provide complete well isolation for the transistors.
Semiconductor Components Industries, Llc


 Method and system for optoelectronic receivers utilizing waveguide heterojunction phototransistors integrated in a cmos soi wafer patent thumbnailnew patent Method and system for optoelectronic receivers utilizing waveguide heterojunction phototransistors integrated in a cmos soi wafer
A method and system for optoelectronic receivers utilizing waveguide heterojunction phototransistors (hpts) integrated in a wafer are disclosed and may include receiving optical signals via optical fibers operably coupled to a top surface of the chip. Electrical signals may be generated utilizing hpts that detect the optical signals.
Luxtera, Inc.


 Semiconductor device patent thumbnailnew patent Semiconductor device
According to one embodiment, a semiconductor device includes: a first circuit including a first transistor, a second transistor, the first and second transistors being capable of receiving first and second signals, respectively; a second circuit including a third transistor and a fourth transistor, a gate and one end of the third transistor being connected to one end of the first transistor, the fourth transistor being capable of receiving the first signal, one end of the fourth transistor being connected to the other end of the third transistor; and a third circuit configured to charge or discharge a node being connected to the one end of the first transistor according to the first signal.. .
Kabushiki Kaisha Toshiba


 Drive device patent thumbnailnew patent Drive device
A drive device for controlling a power switching element includes: an on-side circuit that performs an on operation of the power switching element; and an off-side circuit that performs an off operation of the power switching element. The on-side circuit or the off-side circuit includes: multiple main mos transistors; a sense mos transistor that define a drain current of each main mos transistor; and a sense current control circuit that controls a drain current of the sense mos transistor to be constant; and a switch circuit that is connected to the gate of each main mos transistor, and controls each main mos transistor to turn on and off so as to switch a gate current in the power switching element..
Denso Corporation


 Method and system for a pseudo-differential low-noise amplifier at ku-band patent thumbnailnew patent Method and system for a pseudo-differential low-noise amplifier at ku-band
Methods and systems for a pseudo-differential low-noise amplifier at ku-band may comprise a low-noise amplifier (lna) integrated on a semiconductor die, where the lna comprises differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may comprise: a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors.
Maxlinear, Inc.


 Connect/disconnect module for use with a battery pack patent thumbnailnew patent Connect/disconnect module for use with a battery pack
There are disclosed herein various implementations of a connect/disconnect module for use with a battery pack. The connect/disconnect module includes a charge/discharge current path including multiple transistors having a first safe operating area (soa), and a pre-charge current path coupled across the charge/discharge current path.
Infineon Technologies Americas Corp.


 Semiconductor device and  manufacturing the same patent thumbnailnew patent Semiconductor device and manufacturing the same
A semiconductor device includes a silicon substrate and a detection element and p-type and n-type mos transistors, which are arranged on the silicon substrate, wherein the detection element includes a semiconductor layer, electrodes, and a schottkey barrier disposed therebetween, the semiconductor layer is arranged just above a layer having the same composition and height as those of an impurity diffusion layer in the source or drain of the p-type or n-type mos transistor, a region, in the silicon substrate, having the same composition and height as those of a channel region, in the silicon substrate, just below a gate oxide film of the p-type mos transistor or the n-type mos transistor, or a region, in the silicon substrate, having the same composition and height as those of a region just below a field oxide film disposed between the p-type and the n-type mos transistor.. .
Canon Kabushiki Kaisha


 Non-planar transistors and methods of fabrication thereof patent thumbnailnew patent Non-planar transistors and methods of fabrication thereof
The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar transistors in order to form the source/drain structures from the non-planar transistor fins or to replace the non-planar transistor fins with appropriate materials to form the source/drain structures.. .
Intel Corporation


 Three dimensional monolithic ldmos transistor patent thumbnailnew patent Three dimensional monolithic ldmos transistor
A three dimensional monolithic ldmos transistor implements a drain structure vertically disposed above a level of the structure that includes a drain connection of the transistor. Displacing the drain structure vertically, out of the plane or level of the gate and source/drain connections, creates a three dimensional structure for the transistor.
Broadcom Corporation


new patent

High mobility strained channels for fin-based nmos transistors

Techniques are disclosed for incorporating high mobility strained channels into fin-based nmos transistors (e.g., finfets such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used.
Intel Corporation

new patent

Field-effect transistors with body dropdowns

A field-effect transistor (fet) includes, a first drain, a second drain, a body and a gate region. The gate region has a length, and is configured and arranged to create, in response to a gate voltage, a channel that is in the body, between the first and second drains, and along the length of the gate region.
Nxp B.v.

new patent

Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation

Semiconductor-oxide-containing gate dielectrics can be formed on surfaces of semiconductor fins prior to formation of a disposable gate structure. A high dielectric constant (high-k) dielectric spacer can be formed to protect each semiconductor-oxide-containing gate dielectric.
International Business Machines Corporation

new patent

Semiconductor memory device including slimming structure

Disclosed is a semiconductor memory device, including: a slimming structure extended from a cell structure in a direction parallel to the semiconductor substrate, the cell structure having a plurality of cell transistors stacked over a semiconductor substrate; vertical insulating materials extended in a direction crossing the semiconductor substrate and configured to divide the cell structure and the slimming structure into a plurality of memory blocks; contact plugs passing through the vertical insulating materials, respectively, within an area in which the slimming structure is formed; and junctions formed within the semiconductor substrate under the vertical insulating materials, in which the junctions are coupled to the contact plugs, respectively.. .
Sk Hynix Inc.

new patent

Process for producing mos transistors having a larger channel width from an soi and in particular fdsoi substrate, and corresponding integrated circuit

An integrated circuit includes a substrate with an isolation region that bounds a zone. A transistor includes a concave semiconductor region that is supported by the isolation region in a first direction and has a concavity turned to face towards the zone.
Stmicroelectronics (crolles 2) Sas

new patent

Method for local isolation between transistors produced on an soi substrate, in particular an fdsoi substrate, and corresponding integrated circuit

An integrated circuit may include an soi substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first mos transistors and also first dummy gate regions.
Stmicroelectronics (crolles 2) Sas

new patent

Dual display technologies display

A display device comprising an organic light emitting diode (oled) display; and an electrophoretic display (epd). The oled display and the epd share a common backplane, the common backplane comprising thin-film transistors (tfts) of the oled display and tfts of the epd thereon..
Sony Mobile Communications Inc.

new patent

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and oxide thin-film transistors

A method of fabricating a logic element, the method includes forming a p-type nanomaterial thin film transistor on a substrate, forming a n-type metal oxide thin film transistor on the substrate, and connecting the p-type nanomaterial thin film transistor to the n-type metal oxide thin film transistor to form the logic element. The logic element is a hybrid complementary logic element..
University Of Southern California

new patent

Embedded non-volatile memory

The present invention is a method of incorporating a non-volatile memory into a cmos process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard cmos process (i) after the mos transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the mos transistors) and (ii) before the salicided contacts to those mos transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide).
Hgst, Inc.

new patent

Compact reram based pfga

A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line.
Microsemi Soc Corporation

new patent

Semiconductor device, finfet transistor and fabrication method thereof

The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure..
Semiconductor Manufacturing International (shanghai) Corporation

new patent

Semiconductor device

A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor device and driving semiconductor device

The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Switching device for switching radio frequency signals

The invention relates to a switching device for switching radio frequency signals. The switching devices comprises at least a first field effect transistor that comprises a first source node, a first gate node and a first drain node, wherein the first gate node is arranged between a first drain region and a first source region on a semiconductor substrate.
Rohde & Schwarz Gmbh & Co. Kg

new patent

Method and structure for formation of replacement metal gate field effect transistors

Embodiments of the present invention provide a process that maintains a “keep cap” metal nitride layer on pfet devices within a cmos structure. The keep cap metal nitride layer is in place while an n-type work function metal is formed on the nfet devices within the cmos structure.
Globalfoundries Inc.

new patent

Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme

A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer.
International Business Machines Corporation

new patent

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes memory units each includes a first transistor, memory cell transistors, and a second transistor serially coupled between first and second ends. A memory cell transistor of each memory unit has its gate electrode coupled to each other.
Kabushiki Kaisha Toshiba

new patent

Content addressable memory cells, memory arrays and methods of forming the same

A content addressable memory cell is provided that includes plurality of transistors having a minimum feature size f, and a plurality of memory elements coupled to the plurality of transistors. The content addressable memory cell occupies an area of between 18f2 and 36f2..
Sandisk Technologies Llc

new patent

Semiconductor storage device

The disclosed invention provides a semiconductor storage device that creates no trouble, independently of power-on sequence. A semiconductor storage device includes a first power supply for the memory cells, a second power supply which is turned on independently of the first power supply and provided for a peripheral circuit which is electrically coupled to the memory cells, and a word line level fixing circuit for fixing the level of the word lines, which operates in accordance with turn-on of the first power supply.
Renesas Electronics Corporation

new patent

Dual-port static random-access memory cell

The present disclosure provides a static random access memory (sram) cell comprising first, second, and third fins defined in various well regions. The fins are spaced from each other along a first direction and extend lengthwise generally along a second direction perpendicular to the first direction.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Semiconductor device suppressing bti deterioration

Disclosed herein is a device includes a command generation circuit that activates first and second command signals, an internal circuit that includes a plurality of transistors that are brought into a first operation state when at least one of the first and second command signals is activated, and an output gate circuit that receives a first signal output from the internal circuit, the output gate circuit being configured to pass the first signal when the second command signal is deactivated and to block the first signal when the second command signal is activated.. .
Micron Technology, Inc.

new patent

Semiconductor device and operating method thereof

A semiconductor device includes memory blocks including a plurality of strings in which memory cells are coupled between select transistors; a peripheral circuit suitable for erasing or programming the select transistors and the memory cells, which are included in a selected memory block among the memory blocks; and a control circuit suitable for controlling the peripheral circuit to erase the select transistors and the memory cells, increasing a threshold voltage of the select transistors within a range below an erase level, and increasing the threshold voltage of the select transistors up to a program level.. .
Sk Hynix Inc.

new patent

Gate driving circuit and oled display device

The present invention provides a gate driving circuit and an oled display device. The gate driving circuit comprises multiple stages of shift registers, each stage shift register is connected to an inverter; the shift register provides a first signal and a second signal for the inverter; the inverter receives the first signal and the second signal and generates a light emitting signal according to the first signal and the second signal and input the light emitting signal to the light emitting device; the inverter comprises at least two current amplification units and an external pull-down unit; each current amplification unit comprises a pull-up module, a pull-up hold module, an internal pull-down module and a driving transistor.
Boe Technology Group Co., Ltd.

new patent

Data driver, organic light emitting display panel, organic light emitting display device, and driving organic light emitting display device

The present exemplary embodiments relate to measurement of a characteristic of a driving transistor and sensing driving therefor. Provided are a data driver, an organic light emitting display panel, an organic light emitting display device, and a driving method thereof which are capable of measuring characteristics of a driving transistor even at a data voltage which is not so high within a short sensing time by simultaneously sensing the characteristics of the driving transistors for two or more sub pixels, among a plurality of sub pixels commonly connected to the sensing lines, while measuring characteristics (for example, a threshold voltage or a mobility) of the driving transistor..
Lg Display Co., Ltd.

new patent

High-speed latch circuits by selective use of large gate pitch

An apparatus for storing data includes a latch circuit comprising a first set of transistors that propagate an input signal to an output signal and a second set of transistors that do not propagate the input signal of the latch circuit to the output signal wherein a gate pitch for the first set of transistors is substantially greater than a gate pitch for the second set of transistors. Also disclosed herein, a method for improving circuit performance includes receiving an electronic representation of a plurality of latching circuits associated with a design file and increasing transistor gate pitch for selected transistors of the plurality of latching circuits, wherein the selected transistors comprise transistors that propagate an input signal to an output signal.
International Business Machines Corporation

new patent

Selective power gating to extend the lifetime of sleep fets

A power-gating array configured to power gate a logic block includes multiple zones of sleep field-effect transistors (fets). A zone controller coupled to the power-gating array selectively enables a certain number of zones within the array depending on the voltage drawn by the logic block.
Nvidia Corportion

new patent

Current-mode bandgap reference with proportional to absolute temperature current and zero temperature coefficient current generation

In a current-mode bandgap reference integrated circuit: a bandgap voltage generator is configured to generate a bandgap voltage, a zero-temperature coefficient current generator configured to generate a zero-temperature coefficient current, and a proportional to absolute temperature current generator configured to generate a proportional to absolute temperature current. The integrated circuit includes a first pair of bipolar junction transistors (bjt) comprising a first bjt and a second bjt.
Synaptics Incorporated

new patent

Display device

A display device includes a first substrate. A first gate line is disposed on the first substrate.
Samsung Display Co., Ltd.

new patent

Method for using an accurate adjustable high-frequency phase-detector

The method determines an input phase differential (Δφ) between two input signals. A phase detector is provided that has pairs of transistors and a first impedance (r1) connected to a first branch carrying a first signal (iout_left) and a second impedance (r2) connected to a second branch carrying a second signal (iout_right).
Catena Holding B.v.

new patent

Capsule endoscope

A capsule endoscope includes a flexible substrate which is integrally formed by disposing an illumination substrate section, a first wiring substrate section, an imaging element substrate, a second wiring substrate section, and a signal-processing substrate section in a row in sequence and an illumination control circuit which includes an illumination control signal output unit and an illumination driving unit, wherein the light-emitting elements are leds, wherein the illumination driving unit is disposed on the imaging element substrate section or the illumination substrate section, and wherein the illumination driving unit includes a transistor array which is formed by a plurality of transistors, the plurality of transistors corresponding to each of the light-emitting elements provided in the illumination unit and generating illumination currents in accordance with the illumination control signal.. .
Olympus Corporation

Semiconductor device

A semiconductor device includes a 2-input nand decoder and an inverter that have six mos transistors arranged in a line. The mos transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar.
Unisantis Electronics Singapore Pte. Ltd.

Method and system for linearizing a radio frequency power amplifier

A method and system for linearizing a radio frequency power amplifier (rfpa) is disclosed. The method comprises calibrating signals in the rfpa to linearize the rfpa, using at least one of a first signal, a second signal, a third signal, and a fourth signal.
Signalchip Innovations Private Limited

Transistor package, amplification circuit including the same, and forming transistor

A transistor package according to one exemplary embodiment includes main transistors and a sub-transistor placed in the same package as the main transistors and having a smaller size than the main transistors. It is thereby possible to provide a transistor package with more versatility capable of forming various types of doherty amplification circuits such as a doherty amplification circuit with auto-biasing function and an extended doherty amplification circuit with desired operating characteristics, an amplification circuit including the same, and a method of forming a transistor..
Nec Corporation

Low temperature poly silicon thin film transistors (ltps tfts) and tft substrates

A ltps tft and a tft substrate are disclosed. The ltps tft includes: a substrate; a first gate arranged on the substrate; a polysilicon layer arranged on the substrates, and the polysilicon layer covers the first gate, wherein the polysilicon layer comprises a source area, a drain area, and a trench area formed between the source area and the drain area; a second gate arranged on the polysilicon layer; wherein when the ltps tft has been driven, the first gate and the second gate are respectively applied with a first voltage and a second voltage, and a polarity of the first voltage is opposite to the polarity of the second voltage.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Silicon-containing, tunneling field-effect transistor including iii-n source

Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and iii-n source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors.
International Business Machines Corporation

Transistor arrangement including power transistors and voltage limiting means

A transistor arrangement in a semiconductor body comprises a power transistor with at least two transistor cells, each transistor cell arranged in a semiconductor fin of the semiconductor body and with a voltage limiting device with at least two device cells. Each device cell is arranged adjacent a transistor cell in the semiconductor fin of the respective transistor cell and the voltage limiting device is separated from the power transistor by a dielectric layer..
Infineon Technologies Dresden Gmbh

Non-planar iii-n transistor

transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls.
Intel Corporation

Compound semiconductor device

A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors.
Murata Manufacturing Co., Ltd.

Transistor with charge enhanced field plate structure and method

transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102).
Freescale Semiconductor, Inc.

Semiconductor devices including field effect transistors and methods of fabricating the same

A semiconductor device includes a fin structure on a substrate, device isolation patterns on the substrate at opposite sides of the fin structure, a gate electrode intersecting the fin structure and the device isolation patterns, a gate dielectric pattern between the gate electrode and the fin structure and between the gate electrode and the device isolation patterns, and gate spacers on opposite sidewalls of the gate electrode, wherein, on each of the device isolation patterns, a bottom surface of the gate dielectric pattern is at a higher level than bottom surfaces of the gate spacers.. .
Samsung Electronics Co., Ltd.

Oled display device and manufacture method thereof

The present invention provides an oled display device and a manufacture method thereof, and the oled display device comprises a first substrate (100), a second substrate (200) spaced and oppositely located with the first substrate (100), a plurality of thin film transistors (101) located at an inner surface of the first substrate (100), a transparent anode (201) located at an inner surface of the second substrate (200), a plurality of partition walls (202) located on the transparent anode (201), transmission holes (203) formed among the partition walls (202), an organic layer (204) located on the transparent anode (201) and in the transmission holes (203), a metal cathode (205) located on the organic layer (204) and the partition walls (202), and the metal cathode (205) is electrically connected to a drain of the thin film transistor (101). The oled display device possesses a high aperture ratio and high transmittance.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Semiconductor device and structure

A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.. .
Monolithic 3d Inc.

Method for manufacturing solid-state image pickup apparatus, solid-state image pickup apparatus, and image pickup system including the same

A method for manufacturing a solid-state image pickup apparatus includes forming a first insulating film over a substrate after forming a gate electrode of a first transfer transistor and a gate electrode of a second transfer transistor, forming a second insulating film on the first insulating film, forming a first structure and a second structure on side surfaces of the gate electrodes of the first and second transfer transistors, respectively, via the first insulating film by etching the second insulating film in such a manner that the first insulating film remains on a semiconductor region of a photoelectric conversion unit and a semiconductor region of a charge holding unit, and forming a light shielding film that covers the gate electrode of the first transfer transistor, the semiconductor region of the charge holding unit, and the gate electrode of the second transfer transistor.. .
Canon Kabushiki Kaisha

Ltps array substrate

An ltps array substrate includes a plurality of ltps thin-film transistors and a bottom transparent conductive layer, a protective layer, and a top transparent conductive layer. Each ltps thin-film transistor includes a substrate, a patternized light shield layer, a buffering layer, a patternized poly-silicon layer, a gate insulation layer, a gate line, and a common electrode line, an insulation layer, a drain and a source, and a planarization layer that are formed to sequentially stack on each other.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Integrated structure comprising neighboring transistors

An integrated structure includes a first mos transistor with a first controllable gate region overlying a first gate dielectric and a second mos transistor neighboring the first mos transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric.
Stmicroelectronics (rousset) Sas

Device comprising a plurality of fdsoi static random-access memory bitcells and operation thereof

A device including a plurality of static random-access memory (sram) bitcells arranged in rows and columns, wherein the sram bitcells comprise fully depleted silicon-on-insulator field effect transistors (fdsoi-fets). The fdsoi-fets comprise p-channel-pull-up-transistors, wherein each p-channel-pull-up-transistor comprises a back gate.
Globalfoundries Inc.

Complementary bipolar sram

A complementary lateral bipolar sram device and method of operating. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state.
International Business Machines Corporation

Scan driving circuit and nor gate logic operation circuit thereof

The disclosure is related to a scan driving circuit for an oxide semiconductor thin film transistor and the nor gate logic operation circuit thereof. The nor gate logic operation circuit includes a first invertor and a second invertor applied in the pull down holding circuit of the goa circuit, and a plurality of transistors.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Shift register unit, gate driving circuit and display device

The present invention discloses a shift register unit, employed for providing a gate voltage to a nth pixel of a liquid crystal display, and comprising first to third p-type transistors, and gates of the first, second p-type transistors respectively receive gate voltages of n-2th, n-2th pixels, and first end of the first, second p-type transistors respectively receive first and second input signals, and both second ends of the first and second p-type transistors are coupled to a gate of the third p-type transistor; the gate voltages of the n-2th, n-2th pixels are respectively employed to control on-off of the first and second p-type transistors, and to make the first input signal on-off the third p-type transistor; n is a nature number larger than 2; a first end of the third p-type transistor is coupled to a first clock signal or a second clock signal, and a second end is employed as being a voltage output end to be coupled to the nth pixel. The present invention can diminish the dimension of the frame of liquid crystal display.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Scan driving circuit for oxide semiconductor thin film transistors

The present invention provides a scan driving circuit for oxide semiconductor thin film transistors, a pull-down holding circuit part (600) employed of the circuit comprises a first pull-down holding module (601) and a second pull-down holding module (602) which is capable of extending the lifetime of the circuit; the first pull-down holding module (601) comprises a first main inverter and a first auxiliary inverter with introducing a constant low voltage level (dcl); the second pull-down holding module (602) comprises a second main inverter and a second auxiliary inverter with introducing a constant low voltage level (dcl); setting the constant low voltage level (dcl)<the second negative voltage level (vss2)<the first negative voltage level (vss1), the influence of electrical property of the oxide semiconductor thin film transistors to the scan driving circuit, particularly the bad function due to the electric leakage issue, can be prevented to ensure that the pull-down holding circuit part (600) can be normally pulled down in the functioning period and at higher voltage level in a non-functioning period to effectively maintain the first node (q(n)) and the output end (g(n)) at low voltage level.. .
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Scan driving circuit for oxide semiconductor thin film transistors

The present invention provides a scan driving circuit for oxide semiconductor thin film transistors, a pull-down holding circuit part (600) employed in the scan driving circuit for the oxide semiconductor thin film transistors comprises a main inverter and an auxiliary inverter. By introducing a constant low voltage level (dcl) and setting the constant low voltage level (dcl)<the second negative voltage level (vss2)<the first negative voltage level (vss1), the influence of electrical property of the oxide semiconductor thin film transistors to the scan driving circuit, particularly the bad function due to the electric leakage issue, can be prevented to ensure that the pull-down holding circuit part (600) can be normally pulled down in the functioning period and at higher voltage level in a non-functioning period to effectively maintain the first node (q(n)) and the output end (g(n)) at low voltage level..
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Scan driving circuit for oxide semiconductor thin film transistors

The present invention provides a scan driving circuit for oxide semiconductor thin film transistors, a pull-down holding circuit part (600) employed in the scan driving circuit for the oxide semiconductor thin film transistors comprises a main inverter and an auxiliary inverter. By introducing a constant low voltage level (dcl) and setting the constant low voltage level (dcl)<the second negative voltage level (vss2)<the first negative voltage level (vss1), the influence of electrical property of the oxide semiconductor thin film transistors to the scan driving circuit, particularly the bad function due to the electric leakage issue, can be prevented to ensure that the pull-down holding circuit part (600) can be normally pulled down in the functioning period and at higher voltage level in a non-functioning period to effectively maintain the first node (q(n)) and the output end (g(n)) at low voltage level..
Shenhen China Star Optoelectronics Technology Co., Ltd.

Goa circuit of ltps semiconductor tft

The present invention provides a goa circuit of ltps semiconductor tft, employed for forward-backward bidirectional scan transmission, comprising a plurality of goa units which are cascade connected, and n is set to be a positive integer and an nth goa unit utilizes a plurality of n-type transistors and a plurality of p-type transistors and comprises a transmission part (100), a transmission control part (200), an information storage part (300), a data erase part (400), an output control part (500) and an output buffer part (600). The transmission gate is employed to perform the former-latter level transferring signal, and the nor gate logic unit and the nand gate logic unit are employed to convert the signals, and the sequence inverter and the inverter are employed to save and transmit the signals to solve the issues that the stability of the circuit is poor, and the power consumption is larger as concerning the ltps with single type tft elements, and the problem of tft leakage of the single type goa circuit to optimize the performance of the circuit.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Amoled pixel circuit

The present invention provides an amoled pixel circuit. The third thin film transistor (t3) are located between the first, the second thin film transistors (t1, t2), and the control line (control) is employed to input the control signal for controlling on and off of the third thin film transistor (t3), and thus controlling the amoled pixel circuit to measure the drive current with the current measurement circuit (1) and correcting the signal voltage with the signal voltage drive circuit (2), or displaying normally.
Shenzhen China Star Optoelectronics Technology Co.



Transistors topics:
  • Transistors
  • Semiconductor
  • Semiconductor Device
  • Integrated Circuit
  • High Speed
  • Photodiode
  • Memory Effect
  • Silicon Nitride
  • Enhancement
  • Ion Implant
  • Ion Channel
  • Interrupted
  • Reference Voltage
  • Semiconductor Devices
  • Semiconductor Substrate


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