Images List Premium Download Classic

Transistors

Transistors-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


loading
Multiple linear regulation
Fairchild Korea Semiconductor, Ltd.
December 07, 2017 - N°20170354002

A circuit comprises an amplifier and a plurality of channels, the plurality of channels including respective transistors. The respective transistors of the channels control respective magnitudes of respective currents of the channels according to an output of the amplifier. The respective transistors of the plurality of channels may be included in an auto-commutated circuit. A first light emitting diode (led) ...
Semiconductor device including buffer circuit
Micron Technology, Inc.
December 07, 2017 - N°20170353183

A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. ...
Method and circuitry to soft start high power charge pumps
Intersil Americas Llc
December 07, 2017 - N°20170353105

A method to soft start a charge pump circuit according to embodiments includes enabling switching for a plurality of power transistors, selecting a first switching control signal from a plurality of switching control signals for the selected plurality of power transistors, slowly ramping up a plurality of bootstrap supply voltages associated with the selected plurality of power transistors, driving a ...
Transistors Patent Pack
Download 1475+ patent application PDFs
Transistors Patent Applications
Download 1475+ Transistors-related PDFs
For professional research & prior art discovery
inventor
  • 1475+ full patent PDF documents of Transistors-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Vertical field effect transistors with bottom source/drain epitaxy
International Business Machines Corporation
December 07, 2017 - N°20170352742

A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with ...
Novel embedded shape sige for strained channel transistors
Stmicroelectronics, Inc.
December 07, 2017 - N°20170352741

An integrated circuit die includes a silicon substrate. Pmos and nmos transistors are formed on the silicon substrate. The carrier mobilities of the pmos and nmos transistors are increased by introducing tensile stress into the channel regions of the nmos transistors and compressive stress into the channel regions of the pmos transistors. Tensile stress is introduced by including a region ...
Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
Cypress Semiconductor Corporation
December 07, 2017 - N°20170352732

A memory is described. Generally, the memory includes a number of non-planar multigate transistors, each including a channel of semiconducting material overlying a surface of a substrate and electrically connecting a source and a drain, a tunnel dielectric layer overlying the channel on at least three sides thereof, and a multi-layer charge-trapping region overlying the tunnel dielectric layer. In one ...
Transistors Patent Pack
Download 1475+ patent application PDFs
Transistors Patent Applications
Download 1475+ Transistors-related PDFs
For professional research & prior art discovery
inventor
  • 1475+ full patent PDF documents of Transistors-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Display device
Lg Electronics Inc.
December 07, 2017 - N°20170352714

A display device includes at least one light-emitting element configured to emit blue light, a red conversion layer disposed on an upper or lower portion of the at least one light-emitting element and including a red light-emitting quantum dot, a green conversion layer disposed on the upper or lower portion of the at least one light-emitting element and including a ...
Bottom pinned sot-mram bit structure and method of fabrication
Western Digital Technologies, Inc.
December 07, 2017 - N°20170352702

Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a sot-mram chip architecture. The sot-mram chip architecture includes a plurality of leads, a plurality of memory cells, and a plurality of transistors. The leads may be made of a material having large spin-orbit coupling strength and high electrical resistivity. Each lead ...
Method and device for finfet sram
Semiconductor Manufacturing International (beijing) Corporation
December 07, 2017 - N°20170352668

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of the trenches; forming a high-k dielectric layer on the interface ...
Self-aligned vertical transistor with local interconnect
International Business Machines Corporation
December 07, 2017 - N°20170352625

A metallization scheme for vertical field effect transistors (fets) is provided. By forming lower-level local interconnects connecting source regions located at bottom portions of semiconductor fins, and upper-level interconnects connecting adjacent metal gates located along sidewalls of channel regions of the semiconductor fins, electrical connections to the source regions and the metal gates can be provided through the lower-level local ...
Low resistance dual liner contacts for fin field-effect transistors (finfets)
International Business Machines Corporation
December 07, 2017 - N°20170352597

A semiconductor device includes first and second gate structures on a substrate respectively corresponding to an n-type and a p-type transistor, a first source/drain on the substrate corresponding to the n-type transistor, a second source/drain on the substrate corresponding to the p-type transistor, a first contact trench over the first source/drain and adjacent the first gate structure, ...
Methods of forming one or more covered voids in a semiconductor substrate, methods of forming ...
Micron Technology, Inc.
December 07, 2017 - N°20170352580

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
Methods of forming one or more covered voids in a semiconductor substrate, methods of forming ...
Micron Technology, Inc.
December 07, 2017 - N°20170352579

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
Transistors Patent Pack
Download 1475+ patent application PDFs
Transistors Patent Applications
Download 1475+ Transistors-related PDFs
For professional research & prior art discovery
inventor
  • 1475+ full patent PDF documents of Transistors-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Redundancy in a display comprising autonomous pixels
Microsoft Technology Licensing, Llc
December 07, 2017 - N°20170352321

A display comprises a plurality of autonomous pixels on a substrate. Each autonomous pixel comprises a display element, a sensing element and a control element. The sensing element is arranged to detect an external stimulus and the control element is arranged to generate, entirely within the autonomous pixel, a control signal to drive the display element based, at least in ...
Display device
Joled Inc.
December 07, 2017 - N°20170352314

Pixel circuits each include a write transistor having a gate electrode connected to a write control line, one of a drain electrode and a source electrode connected to a data line for transmitting data voltage corresponding to luminance of the pixel circuit, and the other of the drain electrode and the source electrode connected to a gate electrode of a ...
Integrated circuit manufacturing process for aligning threshold voltages of transistors
Marvell World Trade Ltd.
December 07, 2017 - N°20170351802

In some implementations, a method of fabricating an integrated circuit includes obtaining first data for a first chip containing a first version of the integrated circuit, determining that a transistor should be coupled with another transistor, selecting one or more masks for coupling the transistor with the other transistor to adjust the threshold voltage of the transistor, obtaining second data ...
Biosensor for electrical detection of a nucleotide sequence
International Business Machines Corporation
December 07, 2017 - N°20170350855

The present invention relates generally to the field of microelectronics, and more particularly to a structure and method of forming a biosensor having a nucleotide attracting surface formed to reduce false detection of nucleotides and enabling electrical detection of nucleotides. The biosensor may include an analyte-affinity layer on an upper surface of a substrate. A conductive layer may extend a ...
Molecular detection apparatus and molecular detection method
Kabushiki Kaisha Toshiba
December 07, 2017 - N°20170350854

A molecular detection apparatus according to an embodiment includes: a distributor which ionizes a target containing substances to be detected, applies voltage to ionized substances, and extracts the substances to be detected according to a time-of-flight based on the speed; a detector which detects the substance to be detected dropped from the distributor; and a discriminator which discriminates the substance ...
Image sensors with led flicker mitigaton global shutter pixles
Semiconductor Components Industries, Llc
December 07, 2017 - N°20170350755

An image sensor may include one or more pixels having a charge steering structure that may selectively route charge from a photodiode to increase the dynamic range of the pixel. The charge steering structure may be a coupled gate structure that routes overflow charge to a voltage supply and to one or more integrating storage structures during an exposure period. ...
Logic circuit, semiconductor device, electronic component, and electronic device
Semiconductor Energy Laboratory Co., Ltd.
November 30, 2017 - N°20170346489

A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is diode-connected, and a capacitor. The dynamic logic circuit includes a second output node. The first transistor and transistors in the dynamic logic circuit have an n-type conductivity or a p-type conductivity. The first ...
Radio-frequency switch having dynamic gate bias resistance, body contact, and compensation circuit
Skyworks Solutions, Inc.
November 30, 2017 - N°20170346482

Radio-frequency (rf) switch circuits having switchable transistor coupling for improved switching performance. An rf switch system includes at least one field-effect transistor (fet) disposed between first and second nodes, each fet having a gate and body. A switchable resistive coupling circuit is connected to each of the respective gates. A switchable resistive grounding circuit is connected to each of the ...
Loading