|| List of recent Transistors-related patents
| High frequency module|
Provided is a high frequency module capable of reducing the imd. During the transmission/reception operation based on w-cdma, control signals vswcc, vtrxcc are output as hi signals from a control logic.
| Tetracene tetracarboxylic diimides and their preparation|
A new family of tetracene tetracarboxylic diimides is provided. These ones can made by reacting a 9-stannafluorene with a tetrabromo compound including a tetracene tetracarboxylic diimide core.
| Negative audio signal voltage protection circuit and method for audio ground circuits|
Self-grounded circuitry (10) includes a signal channel conducting an output voltage (vout1). A charge pump (2) powered by a reference voltage (vdd) produces a control voltage (vcp).
| Method and apparatus for program and erase of select gate transistors|
Techniques are provided for programming select gate transistors in connection with the programming of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells.
| Semiconductor device|
Disclosed is a semiconductor device, including: an active region defined in a shape extended in at least four different directions in a semiconductor substrate; and gates of first to fourth transistors formed on extended portions of the active region, respectively, in which the first to fourth transistors share one junction area.. .
| Semiconductor memory device and method for driving the same|
In a conventional dram, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line mbl_m.
| System and a method for designing a hybrid memory cell with memristor and complementary metal-oxide semiconductor|
The embodiments herein relates to a hybrid non-volatile memory cell system and architecture for designing integrated circuits. The system comprises cmos access transistor connected to a memristor which stores a data based on a resistance.
| Class-ab amplifier, motor device, magnetic disk storage device, and electronic apparatus|
A class-ab amplifier has upper side and lower side transistors, a linear driver, upper side and lower side idlers, upper side and lower side detection current generators, and an off driver. The upper side and lower side idlers bias upper side and lower side gate voltages by generating upper side and lower side bias currents so as to turn on the upper side and the lower side transistors at the same time in the crossover region between an input voltage and a reference voltage respectively.
| Display panel and method of manufacturing the same|
A display panel includes a substrate including a plurality of thin-film transistors thereon, a plurality of gate lines respectively connected to a thin film transistor and disposed on the substrate, a color filter layer disposed on the substrate and the gate lines, a black matrix disposed on the color filter and overlapped with the gate lines, and a hole defined in the black matrix and exposing the color filter layer, a first electrode disposed on the color filter and electrically connected to the thin-film transistor and an image displaying layer disposed on the first electrode.. .
| Solid-state imaging device, driving method of solid-state imaging device, and electronic apparatus|
A solid-state imaging device includes a first chip including a plurality of pixels, each pixel including a light sensing unit generating a signal charge responsive to an amount of received light, and a plurality of mos transistors reading the signal charge generated by the light sensing unit and outputting the read signal charge as a pixel signal, a second chip including a plurality of pixel drive circuits supplying desired drive pulses to pixels, the second chip being laminated beneath the first chip in a manner such that the pixel drive circuits are arranged beneath the pixels formed in the first chip to drive the pixels, and a connection unit for electrically connecting the pixels to the pixel drive circuits arranged beneath the pixels.. .
| Solid-state imaging device and camera system|
A solid-state imaging device and a camera system are disclosed. The solid-state imaging device includes a pixel unit and a pixel signal readout circuit.
| Low noise voltage controlled oscillator|
An enhanced negative resistance voltage controlled oscillator (vco) circuit is provided, in which a parallel connection of a capacitor and a resistor configured to provide frequency-dependent transconductance is present across source nodes of a first pair of field effect transistors in which gate nodes and drain nodes are cross-coupled. The source nodes of the first pair of field effect transistors are electrically shorted to drain nodes of a second pair of field effect transistors of which the gate nodes are electrically shorted to the gate nodes of the first pair of field effect transistors.
| Mid-band psrr circuit for voltage controlled oscillators in phase lock loop|
A circuit generates a compensation signal that can remove noise in a vco introduced by a supply signal (i.e., supply-side noise). The circuit includes two transistors connected in series.
| Efficient voltage doubler|
A charge pump circuit using a voltage doubler-type of circuitry for generating an output voltage is described. An output generating stage uses a voltage double structure, except that the transistors in each leg are not cross-coupled to the other leg, but instead are controlled by an auxiliary section.
| Method and system for delta double sampling|
An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair.
| Wireless lighting control|
In a group of associated luminaires, a master luminaire may receive control signals from an external controller, such as over a set (pair) of wires (input leads), and will pass these signals wirelessly (via signaling leds and phototransistors) to slave luminaires. Hence, the slave luminaires need not have input leads or control wires extending therefrom.
| Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods|
At least nine linear-shaped conductive structures (lcs's) are positioned in accordance with a first pitch. Five of the at least nine lcs's collectively form three transistors of a first transistor type and three transistors of a second transistor type.
| Mos device assembly|
A mos device assembly having at least two transistors, each transistor having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor.
| Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures|
A method includes forming a layer of silicon-carbon on an n-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon and on the p-active region, masking the n-active region, forming a layer of a second semiconductor material on the first semiconductor material in the p-active region and forming n-type and p-type transistors. A device includes a layer of silicon-carbon positioned on an n-active region, a first layer of a first semiconductor positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on a p-active region, a layer of a second semiconductor material positioned on the second layer of the first semiconductor material, and n-type and p-type transistors..
| Semiconductor device|
The semiconductor device includes a power element which is in an on state when voltage is not applied to a gate, a switching field-effect transistor for applying first voltage to the gate of the power element, and a switching field-effect transistor for applying voltage lower than the first voltage to the gate of the power element. The switching field-effect transistors have small off-state current..
| Process for the production of electrically semiconducting or conducting metal-oxide layers having improved conductivity|
The invention relates to a process for the production of electrically semiconducting or conducting metal-oxide layers having improved conductivity which is suitable, in particular, for the production of flexible thin-film transistors, to metal-oxide layers produced thereby, and to the use thereof for the production of electronic components.. .
|Input/output cell design for thin gate oxide transistors with restricted poly gate orientation|
An input/output circuit layout has a first section in which first transistors having a thicker gate oxide are located and a second section in which second transistors having a thinner gate oxide are located. Due to process technology constraints, the gates of all of the second transistors are oriented in a single common direction.
|Synapse array, pulse shaper circuit and neuromorphic system|
A synapse array based on a static random access memory (sram), a pulse shaper circuit, and a neuromorphic system are provided. The synapse array includes a plurality of synapse circuits.
|Chemical sensor array having multiple sensors per well|
In one embodiment, a device is described. The device includes a material defining a reaction region.
|Methods for fabricating improved bipolar transistors|
Bipolar transistors and methods for fabricating bipolar transistors are provided. In one embodiment, the method includes the step or process of providing a substrate having therein a semiconductor base region of a first conductivity type and first doping density proximate an upper substrate surface.
|Method for forming a low resistivity tungsten silicide layer for metal gate stack applications|
Tungsten silicide layers can be used in cmos transistors in which the work function of the tungsten silicide layers can be tuned for use in pmos and nmos devices. A co-sputtering approach can be used in which silicon and tungsten are deposited on a high dielectric constant gate dielectric layer.
|Copper-alloy barrier layers for metallization in thin-film transistors and flat panel displays|
In various embodiments, electronic devices such as thin-film transistors incorporate electrodes featuring a conductor layer and, disposed below the conductor layer, a barrier layer comprising an alloy of cu and one or more refractory metal elements selected from the group consisting of ta, nb, mo, w, zr, hf, re, os, ru, rh, ti, v, cr, and ni.. .
|Insulated gate bipolar transistors including current suppressing layers|
An insulated gate bipolar transistor (igbt) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type.
|Semiconductor device and electronic unit|
Thin-film transistors and techniques for forming thin-film transistors (tft). In some embodiments, there is provided a method of forming a tft, comprising forming a body region of the tft comprising an organic semiconducting material, and forming a protective layer comprising an organic insulating material.
|Thermal control of droplets by nanoscale field effect transistors|
Provided herein are methods and devices for rapidly and accurately heating fluid droplets surrounded by a gas-phase medium, such as air. Sub-nanoliter fluid droplets can be rapidly heated by nanoscale field effect transistors via microwave heating by an applied ac voltage to the fet.
|Differential temperature sensor with sensitivity set by current-mirror and resistor ratios without limiting dc bias|
A differential on-chip temperature sensor circuit can be implemented in a standard complementary metal-oxide-semiconductor (cmos) process using pnp transistors. A pair of transistors have collector currents that are sensitive to voltage, both directly and due to saturation currents.
|Nonvolatile semiconductor memory device and method of operating the same|
A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array having a plurality of electrically rewritable memory transistors arranged therein; and a control unit configured to govern control that repeats a voltage application operation and a step-up operation, the voltage application operation applying an applied voltage to a selected memory transistor to change a threshold voltage at which the selected memory transistor is conductive, and the step-up operation, in the case where a threshold voltage of the selected memory transistor has not changed to a desired value, raising the applied voltage by an amount of a certain step-up value. The control unit is configured to control the step-up operation to monotonically decrease the step-up value as the number of times of the voltage application operations increases..
|Structure and method for adjusting threshold voltage of the array of transistors|
A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate.
|Short-circuit protection structure|
A short-circuit protection structure comprises first and second high-voltage transistors, a control circuit, a first current sampling resistor for the first transistor and a second current sampling resistor for the second transistor. The control circuit controls switching period and duty cycle of the first transistor and the second transistor, a drain terminal of the first transistor is connected to a drain terminal of the second transistor, a source terminal of the first transistor is connected to the first current sampling resistor, and a source terminal of the second transistor is connected to the second current sampling resistor; a gate terminal of the first transistor and a gate terminal of the second transistor are connected to a driver stage of the control circuit.
|Transient protection filter circuit that minimizes the effects of thermal runaway|
Commonly, a transient protection filter circuit is integrated between power sources and the circuits that follow to suppress voltage transients. Pre-existing transient protection filters are implemented such that when a transient is detected, transistors in the path become linear regulators.
|Enhanced charge device model clamp|
A circuit for electrostatic discharge (esd) protection is disclosed. The circuit includes multiple transistors that are selectively turned on during an esd event.
|Active matrix substrate, liquid crystal panel, liquid crystal display device, liquid crystal display unit, and television receiver|
An active matrix substrate is arranged such that each pixel region includes two pixel electrodes, each data signal line extends in a column direction, each column of pixel regions is associated with two data signal lines, one pixel electrode of the pixel region included in the column of pixel regions is connected to one of the two data signal lines via a transistor that is connected to a scanning signal line, the other pixel electrode of the pixel region is connected to the other one of the two data signal lines via a transistor that is connected to another scanning signal line, and one of pixel electrodes included in one of two adjacent pixel regions of the column and one of pixel electrodes included in the other one of the two adjacent pixel regions of the column are connected to an identical scanning signal line via respective transistors.. .
|Method of generating pixel array layout for image sensor and layout generating system using the method|
A method of generating a pixel array layout for an image sensor (wherein the image sensor includes a plurality of unit pixels, and each of the plurality of unit pixels includes a plurality of transistors) includes forming each unit pixel to include a shallow trench isolation (sti). The sti is between a deep trench isolation (dti) area and one of a p-well region and source and drain regions of each transistor.
|Display device including touch sensor and manufacturing method thereof|
The present disclosure relates to a display device including a touch sensor and a manufacturing method thereof, and more particularly, to a display device including a touch sensor using a piezoelectric material and a manufacturing method thereof. The display device includes a first substrate, wherein a plurality of thin film transistors are disposed on the first substrate; a second substrate disposed facing the first substrate; a plurality of piezoelectric elements disposed on the second substrate; and a first sensing electrode overlapping the piezoelectric elements, the first sensing electrode being configured to transfer a sensing voltage generated as a result of pressure applied to the piezoelectric elements..
|Pixel driving method of a display panel and display panel thereof|
A pixel driving method of a display panel is disclosed. The display panel includes a plurality of scan lines, data lines and pixels.
|El display device and production method therefor|
An el display device includes an el display panel including a plurality of pixels each having an el element. Each of the pixels has: driving transistor that supplies a current to el element; first switching transistor; and second switching transistors that supply video signals to the pixel.
Provided is a switch circuit capable of reliably controlling the transmission or interruption of a voltage of from gnd to vdd to an internal circuit even when a positive or negative voltage is input to an input terminal. By adding pmos transistors to nmos transistors constituting the switch circuit and controlling gates of the pmos transistors by a voltage of the input terminal, the transmission or interruption of the voltage of from gnd to vdd can be reliably controlled..
|Frequency doubler and related method of generating an oscillating voltage|
A frequency doubling device suitable to generate an output terminal voltage oscillating at a differential frequency double the frequency of the input differential voltage, includes a first differential pair of p-type transistors and a second differential pair of n-type transistors controlled by the differential input voltage, as well as an lc oscillator including a lc resonant dipole through which the absorbed current is forced by two differential pairs of transistors.. .
|Capacitive charge pump|
One or more charge pumps may be used to amplify the output voltage from a chemically-sensitive pixel that comprises one or more transistors. A charge pump may include a number of track stage switches, a number of boost phase switches and a number of capacitors.
|Power supply circuit|
Power supply circuit includes a voltage converting circuit and a comparing circuit. The voltage converting circuit includes a pwm controller and a plurality of transistors connected therewith.
|Diagnosis of over-current conditions in bipolar motor controllers|
A circuit for controlling a load current through a coil is connected to an output port of a transistor h-bridge that includes two low side transistors and two high side transistors. A current sense circuit is coupled to the h-bridge and configured to provide a representation of the load current provided by the output port.
|System and driving method for light emitting device display|
A light emitting device display, its pixel circuit and its driving technique is provided. The pixel includes a light emitting device and a plurality of transistors.
|Semiconductor device and radio communication device|
A radio communication device includes a power amplifier having a semiconductor device formed with a plurality of unit transistors. Base electrodes of the unit transistors are connected with each other by a base line, and an input capacitor is connected to the base line such that the input capacitor is commonly and electrically connected to the base electrodes of a plurality of the unit transistors..
|Metal gate transistor and method for forming the same|
Various embodiments provide metal gate transistors and methods for forming the same. In an exemplary method, a substrate having a top surface and a back surface can be provided.
|Semiconductor structure having column iii-v isolation regions|
A semiconductor structure provided having: a dielectric; a non-column iii-v doped semiconductor layer disposed over the dielectric; and an isolation barrier comprising column iii-v material disposed vertically through the semiconductor layer to the dielectric. In one embodiment, the semiconductor layer is silicon and has cmos transistors disposed in the semiconductor layer above a first region of the dielectric and a iii-v transistor disposed above a different region of the dielectric.
|Lateral double diffusion metal-oxide-semiconductor (ldmos) transistors and fabrication method thereof|
A lateral double diffusion metal-oxide-semiconductor (ldmos) transistor is provided. The ldmos transistor includes a semiconductor substrate having a well region and a drain region in the well region.
|Pmos transistors and fabrication methods thereof|
A method is provided for fabricating a pmos transistor. The method includes providing a semiconductor substrate; and forming gate structures on a surface of the semiconductor substrate.
|Organic light-emitting display device|
An organic light-emitting display device is provided. The organic light-emitting display device includes: a substrate; a display unit on the substrate and includes a plurality of driving thin film transistors (tfts) and a plurality of organic light-emitting diodes (oleds); and a sealing layer to cover the display unit which includes a first sealing layer that is formed of at least one inorganic layers to cover the plurality of oleds and a second sealing layer that is formed of at least one inorganic layers and at least one organic layers to enclose the plurality of oleds..
|Radiation imaging apparatus and radiation imaging system|
A radiation imaging apparatus comprises a conversion element and a transistor. A drive unit performs a reset operation at a plurality of times, by supplying a conducting voltage to gates of the transistors, successively, one row by one row, an operation of stopping the supplying of the conducting voltage responsive to detecting the irradiation of the radiation to perform an accumulation operation and, after the reset operation, a read out operation.
|Systems and methods for semiconductor voltage drop analysis|
Methods and systems are provided for computing ir drop, i.e., voltage drop, in a semiconductor device. The method includes generating a modeling element corresponding to the plurality of transistors.
|Methods for fabricating semiconductor devices|
A semiconductor device can include a first substrate and conductive patterns on the first substrate, where the conductive patterns are disposed in stacks vertically extending from the substrate. An active pillar can be on the first substrate vertically extend from the first substrate throughthe conductive patterns to provide vertical string transistors on the first substrate.
|Method for forming radio frequency device|
A method for forming a radio frequency device is provided. The method may include: providing a semiconductor-on-insulator layer, which comprises a back substrate, a buried oxide layer and a top semiconductor layer, where a plurality of transistors and an interlayer dielectric layer covering the plurality of transistors are formed on a surface of the top semiconductor layer; providing a temporary supporting layer having a smooth surface, and adhering a surface of the interlayer dielectric layer to the temporary supporting layer; removing the back substrate to expose the buried oxide; providing a high resistivity substrate, and adhering the high resistivity substrate to the buried oxide layer; and removing the temporary supporting layer to expose the surface of the interlayer dielectric layer after the high resistivity substrate and the buried oxide layer is adhered.
|Lateral bipolar transistors having partially-depleted intrinsic base|
A bipolar junction transistor (bjt) and method for fabricating such. The transistor includes an emitter region, a collector region, and an intrinsic-base region.
|Spacer stress relaxation|
A known problem when manufacturing transistors is the stress undesirably introduced by the spacers into the transistor channel region. In order to solve this problem, the present invention proposes an ion implantation aimed at relaxing the stress of the spacer materials.
A controller for a memory device having a bit line, a source line, and a plurality of strings of memory cell transistors connected between the bit line and the source line, is configured to update first and second values for each string when read and write operations are carried out on the strings, the first value for a first string being updated when a read or write operation is carried out on a memory cell transistor of the first string and the second value being updated when a read or write operation is carried out on a memory cell transistor of a second string that is different from the first string.. .
|Driving method of semiconductor device|
In a memory cell including first to third transistors, the potential of a bit line is set to vdd or gnd when data is written through the first transistor. In a standby period, the potential of the bit line is set to gnd.
|Display panel and display apparatus|
An embodiment of the present invention provides a display panel including a first substrate; a device layer disposed on the first substrate, wherein the device layer includes a plurality of thin-film transistors and the thin-film transistor includes a gate electrode; a gate insulating layer disposed on the first substrate and covering the gate electrode; a source electrode disposed on the gate insulating layer; a transparent conductive layer disposed on the gate insulating layer and overlapping and electrically connecting the source electrode; a pixel electrode; an active layer electrically connecting the transparent conductive layer and the pixel electrode; a second substrate disposed on the first substrate; and a display medium between the first substrate and the second substrate.. .
|Organic light emitting display device and method of driving the same|
An organic light emitting display device includes pixels, a scan driver, a memory configured to store pixel data containing information indicative of threshold voltages and mobilities of first transistors in the pixels, a timing controller configured to modify one or more bits of first data to generate second data, the first data modified in response to the pixel data, a data driver configured to generate data signals based on the second data, and a control driver configured to supply a first control signal to a first control line commonly coupled to the pixels and a second control signal to a second control line, wherein each of the pixels is configured to store a data signal of a current frame and to emit light corresponding to a data signal of a previous frame.. .
|Reducing floating node leakage current with a feedback transistor|
This disclosure provides circuits and methods for reducing sub-threshold leakage currents discharging floating nodes. In one aspect, feedback from a floating node is provided to a feedback transistor configured to bias other nodes such that leakage through turned-off transistors is reduced.
|Reducing touch pixel coupling|
A touch screen to reduce touch pixel coupling. In some examples, the touch screen can include a first display pixel and a second display pixel in a row of display pixels, where the first display pixel can be configurable to be decoupled from the second display pixel during at least a touch sensing phase of the touch screen.
|Pixel and organic light emitting display device using the same|
A pixel includes a plurality of organic light emitting diodes, each of which including a cathode electrode coupled to a second power source, a pixel circuit coupled to a scan line and to a data line, the pixel circuit configured to control current supplied from a first power source to the organic light emitting diodes corresponding to a data signal supplied to the data line, and first transistors between the pixel circuit and respective ones of the organic light emitting diodes, the first transistors configured to be turned on or to be turned off when a low emission control signal is supplied to a first emission control line, wherein a scan signal supplied to the scan line is a first voltage, and wherein the low emission control signal is a second voltage that is different than the first voltage.. .
The present disclosure relates to a power amplifier, the power amplifier comprising a first amplifier including at least two first transistors whose sources are commonly connected to form a common source, a second amplifier including at least two second transistors whose gates are commonly connected to form a common gate, the at least two second transistors being connected to the at least two first transistors in a cascode structure; and a bias supplier configured to apply to the common gate of the second amplifier a bias voltage that changes in response to an input and output power.. .
The present disclosure relates to a power amplifier, the power amplifier including a first amplifier configured to form a common source by allowing sources of a plurality of first transistors to be commonly connected, a second amplifier configured to form a common source by allowing sources of a plurality of second transistors to be commonly connected and to be respectively connected in a cascode structure to the plurality of first transistors of the first amplifier, and a controller configured to be connected to a common gate node to short-circuit second harmonic impedance of the common gate.. .
|Self-healing technique for high frequency circuits|
A self-healing monolithic integrated includes an electronic circuit having a plurality of transistors. At least one sensor is disposed within and electrically coupled to the electronic circuit and configured to sense a performance metric of the electronic circuit.
|Power management during wakeup|
A circuit comprises a first set of first transistors and a second set of transistors. The first transistors are configured to be turned on in a sequential manner.
|Length-of-diffusion protected circuit and method of design|
A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors.
|Semiconductor layout structure and testing method thereof|
A semiconductor layout structure and a testing method thereof are disclosed. The semiconductor layout structure includes a device under test (dut), a first testing pad, a second testing pad and a plurality of third testing pads.