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Transistors patents



      
           
This page is updated frequently with new Transistors-related patent applications. Subscribe to the Transistors RSS feed to automatically get the update: related Transistors RSS feeds. RSS updates for this page: Transistors RSS RSS


Nanoshell, method of fabricating same and uses thereof

Tower Semiconductor

Nanoshell, method of fabricating same and uses thereof

Hybrid three-level t-type converter for power applications

Eaton

Hybrid three-level t-type converter for power applications

Hybrid three-level t-type converter for power applications

University-industry FoundationYonsei University

Hydrogen surface-treated graphene, formation method thereof and electronic device comprising the same

Date/App# patent app List of recent Transistors-related patents
04/23/15
20150113492
 Sram layouts patent thumbnailnew patent Sram layouts
Roughly described, the cell layout in an sram array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area.
Synopsys, Inc.
04/23/15
20150113345
 Scan flip-flop and associated method patent thumbnailnew patent Scan flip-flop and associated method
Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors.
Taiwan Semiconductor Manufacturing Co., Ltd.
04/23/15
20150111373
 Reducing gate height variation in rmg process patent thumbnailnew patent Reducing gate height variation in rmg process
A method of forming transistors is provided. The method includes forming a plurality of transistor structures to have a plurality of dummy gates on a substrate.
International Business Machines Corporation
04/23/15
20150111358
 Carrier mobility in surface-channel transistors, apparatus made therewith, and systems containing same patent thumbnailnew patent Carrier mobility in surface-channel transistors, apparatus made therewith, and systems containing same
A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a pmos or an nmos device.
04/23/15
20150111337
 Phenanthro[9,10-b]furan polymers and small molecules for electronic applications patent thumbnailnew patent Phenanthro[9,10-b]furan polymers and small molecules for electronic applications
Phenanthro[9,10-b]furan polymers and small molecules for electronic applications. The present invention relates to polymers comprising a repeating unit of the formula (i), (ii), (viii), (ix) and compounds of formula (viii), or (ix), wherein y, y15, y16 and y17 are independently of each other a group of formula (i), or (ii), and their use as organic semiconductor in organic electronic devices, especially in organic photovoltaics and photodiodes, or in a device containing a diode and/or an organic field effect transistor.
Basf Se
04/23/15
20150110706
 Hydrogen surface-treated graphene, formation method thereof and electronic device comprising the same patent thumbnailnew patent Hydrogen surface-treated graphene, formation method thereof and electronic device comprising the same
The present invention relates to hydrogen surface-treated graphene, a formation method thereof, and an electronic device including the same. The graphene according to one exemplary embodiment of the present invention can be useful in preparing hydrogen surface-treated graphene having a band gap using simple methods through indirect hydrogen plasma treatment.
University-industry Foundation, Yonsei University
04/23/15
20150109858
 Memory device and column decoder for reducing capacitive coupling effect on adjacent memory cells patent thumbnailnew patent Memory device and column decoder for reducing capacitive coupling effect on adjacent memory cells
A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of even local bit lines and a plurality of odd local bit lines.
Winbond Electronics Corp.
04/23/15
20150109851
 Memory device and access method patent thumbnailnew patent Memory device and access method
A memory device includes multiple bit lines extending in a first direction, multiple word lines extending in a second direction crossing the first direction, and multiple memory cells each coupled to corresponding two word lines and corresponding two bit lines. Each memory cell includes a memory element configured to store information on the basis of changes in resistance and two select transistors.
Sony Corporation
04/23/15
20150109705
 Method and associated  performing electrostatic discharge protection patent thumbnailnew patent Method and associated performing electrostatic discharge protection
A method for performing electrostatic discharge (esd) protection and an associated apparatus are provided, where the method is applied to an electronic device, and the method includes: utilizing a trigger source formed with a plurality of metal oxide semiconductor field effect transistors (mosfets) to trigger a discharge operation, where the gate and the drain of any mosfet within the plurality of mosfets are electrically connected to each other, causing the mosfet to be utilized as a two-terminal component, and the mosfets that are respectively utilized as two-terminal components are connected in series; and utilizing an esd apparatus to perform the discharge operation in response to the trigger of the trigger source, in order to perform esd protection on the apparatus.. .
04/23/15
20150109554
 Thin film transistor array panel and liquid crystal display including the same patent thumbnailnew patent Thin film transistor array panel and liquid crystal display including the same
A thin film transistor array panel includes: first to third gate lines extending in one direction and parallel to each other; a data line insulated from and intersecting the first to third gate lines; a first thin film transistor connected to the first gate line and the data line; a second thin film transistor connected to the second gate line and an output terminal of the first thin film transistor; a third thin film transistor connected to the third gate line and the data line; a fourth thin film transistor connected to the second gate line and an output terminal of the third thin film transistor; and first to fourth sub-pixel electrodes respectively connected to the first to fourth thin film transistors.. .
Samsung Display Co., Ltd.
04/23/15
20150109277
new patent

Pixel driving circuit and display device


The present disclosure provides a pixel driving circuit and a display device, the pixel driving circuit includes: a control unit; a capacitor; a first transistor; a second transistor; a third transistor and a fourth transistor. The present disclosure can effectively compensate the variation of the threshold voltage of the drive thin film transistor by controlling the thin film transistors, thus prevent nonuniform brightness of a screen due to nonuniform current, and extend lifespan of the screen..
Everdisplay Optronics (shanghai) Limited
04/23/15
20150109072
new patent

System and a tunable capacitance circuit


A tunable capacitance circuit comprises a plurality of varactor transistors which are coupled in series. An antenna tuner comprises such a tunable capacitance circuit..
Infineon Technologies Ag
04/23/15
20150108960
new patent

Switching circuits for extracting power from an electric power source and associated methods


An integrated circuit chip includes a first input port, a first output port, and first and second transistors electrically coupled in series across the first input port. The second transistor is also electrically coupled across the first output port and is adapted to provide a path for current flowing through the first output port when the first transistor is in its non-conductive state.
Volterra Semiconductor Corporation
04/23/15
20150108958
new patent

Hybrid three-level t-type converter for power applications


Three-level t-type power converters include a totem-pole arrangement of first and second wide bandgap field effect transistors, which are electrically connected in common at an output node of the converter. A pair of power transistors is provided along with a totem-pole arrangement of first and second capacitors.
Eaton Corporation
04/23/15
20150108589
new patent

Embedded interlevel dielectric barrier layers for replacement metal gate field effect transistors


A semiconductor structure may be formed by forming a sacrificial gate above a substrate covered by a hard mask, depositing a first interlevel dielectric (ild) layer above the sacrificial gate, recessing the first ild layer to a thickness less than the height of the sacrificial gate, depositing an etch barrier layer above the first ild layer, depositing a second ild layer above the etch barrier layer, planarizing the second ild layer and the etch barrier layer to expose the hard mask using the hard mask as a planarization stop, removing the hard mask and sacrificial gate to form a gate cavity, forming a replacement metal gate in the gate cavity, removing the second ild layer, and planarizing the replacement metal gate using the etch barrier layer as a planarization stop. A supplementary electrode layer may be formed above the replacement metal gate prior to planarizing the replacement metal gate..
International Business Machines Corporation
04/23/15
20150108583
new patent

Densely packed standard cells for integrated circuit products, and methods of making same


One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively.
Globalfoundries Inc.
04/23/15
20150108580
new patent

Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices


One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures..
Globalfoundries Inc.
04/23/15
20150108576
new patent

Method for fabricating nmos and pmos transistors on a substrate of the soi, in particular fdsoi, type and corresponding integrated circuit


An integrated circuit includes an nmos transistor and a pmos transistor on different regions of an sot substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate.
Stmicroelectronics (crolles 2) Sas
04/23/15
20150108558
new patent

Scalable integrated mim capacitor using gate metal


According to one embodiment, a scalable integrated mim capacitor in a semiconductor die includes a high-k dielectric segment over a substrate and a metal segment over the high-k dielectric segment, where the metal segment forms a capacitor terminal of the integrated mim capacitor. The capacitor further includes a filler laterally separating consecutive capacitor terminals, where the filler can be used as a capacitor dielectric of the integrated mim capacitor.
Broadcom Corporation
04/23/15
20150108554
new patent

Advanced forming method and structure of local mechanical strained transistor


Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a mos transistor.
Taiwan Semiconductor Manufacturing Company, Ltd.
04/23/15
20150108548
new patent

Base profile of self-aligned bipolar transistors for power amplifier applications


According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region.
International Business Machines Corporation
04/23/15
20150108545
new patent

Fin field effect transistors including multiple lattice constants and methods of fabricating the same


A field effect transistor (fet) structure may include a fin on a substrate having a first lattice constant and at least two different lattice constant layers on respective different axially oriented surfaces of the fin, wherein the at least two different lattice constant layers each comprise lattice constants that are different than the first lattice constant and each other.. .
Samsung Electronics Co., Ltd.
04/23/15
20150108541
new patent

Semiconductor device


A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of igbts (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an igbt located at an extreme end in the one direction and an igbt located more centrally than the igbt located at the extreme end.
Renesas Electronics Corporation
04/23/15
20150108479
new patent

Thin-film transistors incorporated into three dimensional mems structures


This disclosure provides systems, methods and apparatus for forming electromechanical systems (ems) displays where the area of a substrate occupied by a pixel circuit can be reduced if portions of the pixel circuit can be built in three dimensions. In some aspects, certain ems displays can incorporate structures that are substantially normal to the surface of a substrate.
Pixtronix, Inc.
04/23/15
20150108478
new patent

Semiconductor device and manufacturing the same


An object is to provide a method for manufacturing a highly reliable semiconductor device including thin film transistors which have stable electric characteristics and are formed using an oxide semiconductor. A method for manufacturing a semiconductor device includes the steps of: forming an oxide semiconductor film over a gate electrode with a gate insulating film interposed between the oxide semiconductor film and the gate electrode, over an insulating surface; forming a first conductive film including at least one of titanium, molybdenum, and tungsten, over the oxide semiconductor film; forming a second conductive film including a metal having lower electronegativity than hydrogen, over the first conductive film; forming a source electrode and a drain electrode by etching of the first conductive film and the second conductive film; and forming an insulating film in contact with the oxide semiconductor film, over the oxide semiconductor film, the source electrode, and the drain electrode..
Semiconductor Energy Laboratory Co., Ltd.
04/23/15
20150108437
new patent

Organic light-emitting display apparatus


An organic light-emitting display apparatus includes an emission pixel in a display area and a spare pixel circuit in a repair area outside the display area. The emission pixels includes a plurality of sub emission pixels each including a driving unit for generating a driving current corresponding to input data signals and an emission device for emitting light by using the driving current.
Samsung Display Co., Ltd.
04/23/15
20150108425
new patent

Nanoshell, fabricating same and uses thereof


A method of fabricating a nanoshell is disclosed. The method comprises coating a nanometric core made of a first material by a second material, to form a core-shell nanostructure and applying non-chemical treatment to the core-shell nanostructure so as to at least partially remove the nanometric core, thereby fabricating a nanoshell.
Tower Semiconductor Ltd.
04/23/15
20150108422
new patent

Double patterning method to form sub-lithographic pillars


A method and resulting structure, is disclosed to fabricate vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a at least one dimension below the minimum lithographical resolution, f, of the lithographic technique employed. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars..
Micron Technology, Inc.
04/16/15
20150104918

Facilitating fabricating gate-all-around nanowire field-effect transistors


Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s).
Globalfoundries Inc.
04/16/15
20150104915

Memory cell with decoupled channels


A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor.
Globalfounderies Singapore Pte. Ltd.
04/16/15
20150103577

Semiconductor memory with sense amplifier


In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.. .
Renesas Electronics Corporation
04/16/15
20150103218

Solid-state imaging device and camera system


A solid-state imaging device and a camera system are disclosed. The solid-state imaging device includes a pixel unit and a pixel signal readout circuit.
Sony Corporation
04/16/15
20150103069

Array substrate, 3d display device and driving the same


The present invention provides an array substrate, a 3d display device and a driving method for the same, and belongs to the field of 3d display. Wherein, the array substrate comprises: a substrate, and 2n rows of pixel units being arranged on the substrate in a matrix form, the array substrate further comprises gate lines corresponding to the pixel units in each row, and each of the gate lines is connected to the gate electrodes of thin film transistors in corresponding pixel units, wherein the gate line corresponding to pixel units in the (2k−1)th row of pixel units or the gate line corresponding to the 2kth row receives the gate scanning signal in a predetermined time period, wherein k is a natural number which is not less than 1 and not greater than n..
Boe Technology Group Co., Ltd.
04/16/15
20150103061

Pixel circuit and display device


A pixel circuit able to prevent a spread of the terminal voltages of drive transistors inside a panel and in turn able to reliably prevent deterioration of uniformity, wherein a source of a tft serving as a drive transistor is connected to an anode of a light emitting element, a drain is connected to a power source potential, a capacitor is connected between a gate and source of the tft, and a source potential of the tft is connected to a fixed potential through a tft serving as a switch transistor and wherein pixel circuit lines are connected by an upper line and bottom line and are arranged in parallel with pixel circuit power source voltage lines so as not to have intersecting parts.. .
Sony Corporation
04/16/15
20150103060

Display device


A display device includes: a pixel array unit with pixel circuits disposed in matrix form, the pixel circuit including a driving transistor, an electro-optic element, a storage-capacitor, and a sampling transistor, with the electro-optic element emitting light by generating a driving current based on information stored in the storage-capacitor at the driving transistor to be applied to the electro-optic element; and a control unit, of which the output stage includes a buffer transistor, to output a pulse signal for driving the pixel array unit from the buffer transistor; wherein the pixel array unit and the control unit are formed with long laser beam irradiation to be scanned in the vertical direction; and with the control unit, buffer transistors for outputting a pulse signal for sampling to an input video signal to each signal line are arrayed in a column in the longitudinal direction of the laser beam irradiation.. .
Sony Corporation
04/16/15
20150102990

Gate driving circuit, and array substrate and display panel thereof


The present invention relates to a gate driving circuit, and an array substrate and a display panel thereof, wherein gate driving circuit includes multi-level gate driving units. A gate driving unit of each level comprises a starting unit, an energy storage unit, a pull-up unit, a first pull-down unit, a second pull-down unit and a third pull-down unit, wherein the second pull-down unit is coupled to the energy storage unit and a gate line, and configured to intermittently generate a second control signal based on a driving voltage, a clock pulse signal and a second reference voltage, and to pull the driving voltage and a gate signal on the gate line down to the second reference voltage.
Shenzhen China Star Optoelectronics Technology Co. Ltd.
04/16/15
20150102851

Method, control unit and switching device for switching a cycle in a power transistor circuit


A method for switching a cycle in a power transistor circuit is created, especially in a parallel circuit of power transistors. The method includes the step of specifying a switching time difference and the switching of the power transistors of two switching times which are separate from one another by use of the switching time difference..
Continental Automotive Gmbh
04/16/15
20150102850

Decoupling circuit and semiconductor integrated circuit


A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) pmos transistors each having a first gate electrode, and j (j is an integer of 0 or more) pmos transistors each having a second gate electrode.
Renesas Electronics Corporation
04/16/15
20150102849

Level-shift circuits compatible with multiple supply voltage


A level-shift circuit, receiving a supply voltage and a input signal, includes a pre-stage voltage conversion circuit and a post-stage voltage conversion circuit. The pre-stage voltage conversion circuit includes a first voltage protection module generating an inner conversion voltage and a first voltage conversion module converting the input signal into a pre-stage output signal according to the inner conversion voltage.
Via Alliance Semiconductor Co., Ltd.
04/16/15
20150102847

Semiconductor circuit and semiconductor system


An example embodiment discloses a flip-flop including a first inverter configured to invert first data, first and second transistors connected to each other in series and configured to receive the inverted first data and a first clock, respectively, a third transistor and a first gate configured to perform a logic operation on the first data and the first clock, the third transistor configured to receive an output of the logic operation. The second transistor and the third transistor are connected to a first node..
04/16/15
20150102840

Cascoded comparator with dynamic biasing for column parallel single slope adcs


Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal.
Sk Hynix Inc.
04/16/15
20150102839

Low power inverter circuit


A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively.
Freescale Semiconductor, Inc.
04/16/15
20150102826

Design structures and methods for extraction of device channel width


Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths..
Globalfoundries Inc.
04/16/15
20150102792

Voltage regulator and control method thereof


A voltage regulator and a control method thereof are provided to dynamically adjust an output voltage. The voltage regulator comprises a plurality of switching transistors and a control circuit.
Industrial Technology Research Institute
04/16/15
20150102735

Gate driving circuit, and array substrate and display panel using the same


The present invention relates to a gate driving circuit, and a array substrate and a display using the same. The gate driving circuit comprises multiple-stage gate driving units, and each gate driving unit includes: an actuating unit configured to transmit an actuation signal; an energy storage unit configured to execute a charging process under the action of the actuation signal to output a driving voltage; a pull-up unit, a first pull-down unit, a second pull-down unit and a third pull-down unit operating under the action of the driving voltage, wherein a third pull-down unit pulls the driving voltage down to a second reference voltage to apply a reverse bias voltage to the gate-source and/or the gate-drain of transistors in the gate driving circuit, such that the threshold voltage of respective transistors under positive offset can offset reversely, thus effectively eliminating adverse effects of a threshold voltage offset phenomenon of the transistors on the gate driving circuit and improving the operation reliability of the gate driving circuit as well as the array substrate and the display panel thereof..
Shenzhen China Star Optoelectronics Technology Co., Ltd.
04/16/15
20150102423

Method for finfet sram ratio tuning


A semiconductor device and method of forming the same include a substrate having a plurality of memory cells formed thereon. A memory cell includes pass-gate transistors, pull-up transistors, and pull-down transistors.
Semiconductor Manufacturing International (shanghai) Corporation
04/16/15
20150102421

Semiconductor device


A semiconductor device having an sram which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions..
Renesas Electronics Corporation
04/16/15
20150102413

Semiconductor device


Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction..
04/16/15
20150102387

High electron mobility transistors with minimized performance effects of microcracks in the channel layers


In hemts based on iii-nitrides epitaxial films or gaas, algaas and ingaas epitaxial films, unwanted microcracks are often formed in the composite epitaxial layers in the channel region during fabrication and operation. These microcracks are caused by strain or stresses due to lattice mismatch and thermal expansion coefficient differences between materials and substrate's.
04/16/15
20150101556

Glow time control device


The present invention relates to a glow time control device (100) for controlling glow rods (206-209) in a vehicle (200). The glow time control device (100) comprises a control unit (ic1), at least two power transistors (t1, t4) and a protective circuit (t6, t7).
Volkswagen Aktiengesellschaft
04/09/15
20150100939

Semiconductor device burn-in stress method and system


Burn-in (bi) stress using stress patterns with pin-specific power characteristics. A control device for each conductive pathway from bi board (bib) contacts to device under test (dut) connectors/contacts can adjust power delivered to a respective connector/contact responsive to a controller.
International Business Machines Corporation
04/09/15
20150099340

Methods for preventing oxidation damage during finfet fabrication


Embodiments of the present invention provide improved methods for fabricating field effect transistors such as finfets. Stressor regions are used to increase carrier mobility.
Globalfoundries Inc.
04/09/15
20150099332

Resin composition, substrate and manufacturing electronic device


Provided are a resin composition and a substrate that are capable of being used for producing an electronic device including thin-film transistors having an excellent switching property. The resin composition contains an aromatic polyamide and a solvent dissolving the aromatic polyamide.
Sumitomo Bakelite Company Limited
04/09/15
20150099330

Glass wafers for semiconductors fabrication processes and methods of making same


The present disclosure is directed to the use of glass wafers as carriers, interposers, or in other selected applications in which electronic circuitry or operative elements, such as transistors, are formed in the creation of electronic devices. The glass wafers generally include a glass having a coefficient of thermal expansion equal to or substantially equal to a coefficient of thermal expansion of semiconductor silicon, an indexing feature, and a coating on at least a portion of one face of the glass..
Corning Incorporated
04/09/15
20150098274

Cell array with a manufacturable select gate for a nonvolatile semiconductor memory device


A three-dimensional integrated circuit non-volatile memory array includes a memory array with first and second nand memory cell string stacks having opposite orientations, where each nand memory cell string includes a plurality of transistors and a source line contact connected in series between a bit line and string extension region which extends from the source line contact and past a first self-aligned ssl gate electrode located on a peripheral end of the nand memory cell string, and also includes a string select transistor formed with a second self-aligned ssl connected in series between the bit line and the plurality of transistors, where the first and second self-aligned ssl gate electrodes are shared between adjacent nand memory cell strings having opposite orientations.. .
Conversant Ip Management Inc.
04/09/15
20150098039

Transparent display device and manufacturing method thereof


Discussed are a transparent display device and a manufacturing method thereof, which may reduce diffraction grating. The transparent display device includes gate lines and data lines formed on a substrate and crossing each other with a gate insulator film interposed therebetween to define pixel areas, common lines formed on the substrate and being parallel to the gate lines, thin film transistors formed in the respective pixel areas, pixel electrodes connected to the thin film transistors, and common electrodes connected to the common lines and alternating with the pixel electrodes.
Lg Display Co., Ltd.
04/09/15
20150097824

Semiconductor device, display panel and electronic apparatus


A semiconductor device includes a plurality of thin film transistors of a single channel formed on an insulating substrate, and a buffer circuit including an outputting stage; a first inputting stage; a second inputting stage; a seventh thin film transistor; and an eighth thin film transistor.. .
Sony Corporation
04/09/15
20150097762

Pixel and organic light emitting display using the same


A pixel includes an organic light emitting diode, a first transistor, and a second transistor. The first transistor establishes a first current path between a first node coupled to a first power source and a second node coupled to the organic light emitting diode.
Samsung Display Co., Ltd.
04/09/15
20150097630

Method and device for managing the time transition of a cmos logic circuit as a function of temperature


A method includes generation of a first current proportional to absolute temperature and formation of a second current representative of the temperature variation of the threshold voltages of the transistors of the inverter and limited to a fraction of the first current. This fraction is less than one.
Stmicroelectronics (rousset) Sas
04/09/15
20150097621

Capacitance minimization switch


A cmos transmission gate that is compensated for lost current to parasitic capacitance. Parasitic capacitance current is detected by an amplifier and fed back in-phase to the input of the cmos transmission gate with the gain of the amplifier set to avoid circuit instability.
Dialog Semiconductor Gmbh
04/09/15
20150097619

Amplifier


An amplifier includes two input terminals to receive a differential, two-tone transmission signal; two output terminals; a coil having terminals connected with the input terminals respectively, and a center tap; a first transistor having the gate connected with one terminal of the coil, and the output terminal connected with one output terminal; a second transistor having the gate connected with the other terminal of the coil, end the output terminal connected with the other output terminal; a diode having a terminal connected with the center tap; and a bias circuit connected with the other terminal of the diode to output a gate voltage to turn on the first and second transistors. The diode adjusts the terminal voltage depending on a signal level of a double harmonic wave of the transmission signal supplied to the terminal of the diode from the center tap..
Fujitsu Semiconductor Limited
04/09/15
20150097612

Level shifter of driving circuit and operating method thereof


A level shifter applied in a driving circuit of a display is disclosed. The level shifter includes a first stage of level shifting unit and a second stage of level shifting unit and used to convert an input voltage signal with low voltage level into an output voltage signal with high voltage level.
Raydium Semiconductor Corporation
04/09/15
20150097610

Method and system for delta double sampling


An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair.
Life Technologies Corporation
04/09/15
20150097596

Cascoded comparator with dynamic biasing for column parallel single slope adcs


Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal.
Sk Hynix Inc.
04/09/15
20150097539

Systems and methods for real-time inductor current simulation for a switching converter


A switching converter having a high-side switching transistor and a low-side switching transistor and an inductor, having a circuit for generating a simulated waveform representing a sawtooth inductor current waveform. A circuit for monitoring and voltage at a switch node between the high-side and low-side transistors to determine a time during which the inductor current is increasing and a time during which the inductor current is decreasing wherein voltage across the low-side transistor when it is conducting represents a first portion of the simulated sawtooth inductor current waveform.
Texas Instruments Incorporated
04/09/15
20150097252

Simplified gate-first hkmg manufacturing flow


When forming field effect transistors according to the gate-first hkmg approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in formation of a metal silicide layer on the surface of the gate electrode and of the source and drain regions of the transistor. The present disclosure improves the manufacturing flow by skipping the gate cap removal process.
Globalfoundries Inc.
04/09/15
20150097178

Display device and electronic apparatus


A display device in which variations in luminance due to variations in characteristics of transistors are reduced, and image quality degradation due to variations in resistance values is prevented. The invention comprises a transistor whose channel portion is formed of an amorphous semiconductor or an organic semiconductor, a connecting wiring connected to a source electrode or a drain electrode of the transistor, a light emitting element having a laminated structure which includes a pixel electrode, an electro luminescent layer, and a counter electrode, an insulating layer surrounding an end portion of the pixel electrode, and an auxiliary wiring formed in the same layer as a gate electrode of the transistor, a connecting wiring, or the pixel electrode.
Semiconductor Energy Laboratory Co., Ltd.
04/02/15
20150095868

Method of converting between non-volatile memory technologies and system for implementing the method


A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (i/o) interface, a first type of charge pump, and an i/o block.
Taiwa Semiconductor Manufacturing Company, Ltd.
04/02/15
20150093878

Finfet fabrication method


Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finfets). Sacrificial regions are formed on a semiconductor substrate.
Global Foundries Inc.
04/02/15
20150093871

Enhanced stress memorization technique for metal gate transistors


A method of manufacturing a semiconductor device includes forming a dummy gate structure on a semiconductor substrate, forming sidewall spacers, and forming heavily doped source/drain regions. After removing the spacers, a stress material layer is formed over the dummy gate structure.
Semiconductor Manufacturing International (beijing) Corporation
04/02/15
20150093868

Integrated circuit devices including finfets and methods of forming the same


Integrated circuit devices including fin field-effect transistors (finfets) and methods of forming the same are provided. The methods may include forming a fin-shaped channel region including germanium on a substrate and forming a source/drain region adjacent the channel region on the substrate.
04/02/15
20150093861

Method for the formation of cmos transistors


An soi substrate includes first and second active regions separated by sti structures and including gate stacks. A spacer layer conformally deposited over the first and second regions including the gate stacks is directionally etched to define sidewall spacers along the sides of the gate stacks.
Stmicroelectronics, Inc.


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Transistors topics: Transistors, Semiconductor, Semiconductor Device, Integrated Circuit, High Speed, Photodiode, Memory Effect, Silicon Nitride, Enhancement, Ion Implant, Ion Channel, Interrupted, Reference Voltage, Semiconductor Devices, Semiconductor Substrate

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