|| List of recent Transistors-related patents
|Diketopyrrolopyrrole polymers for use in organic semiconductor devices|
The present invention relates to polymers comprising one or more (repeating) unit(s) of the formula (i) which are characterized in that ar1 and ar1′ are independently of each other are an annulated (aromatic) heterocyclic ring system, containing at least one thiophene ring, which may be optionally substituted by one, or more groups, and their use as organic semiconductor in organic devices, especially in organic photovoltaics (solar cells) and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties.
|Semiconductor device and method of fabricating the same|
A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor.
|Symmetric blocking transient voltage suppressor (tvs) using bipolar npn and pnp transistor base snatch|
A symmetrical blocking transient voltage suppressing (tvs) circuit for suppressing a transient voltage includes an npn transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage.
|Polymers based on benzodiones|
The present invention relates to polymers comprising one or more (repeating) unit(s) of the formula (i), and compounds of formula (iii), wherein y, y15, y16 and y17 are independently of each other a group of formula (a), (b) or (c) and their use as ir absorber, organic semiconductor in organic devices, especially in organic photovoltaics and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers and compounds according to the invention can have excellent solubility in organic solvents and excellent film-forming properties.
|Method and system for an analog crossbar architecture|
Methods and systems for an analog crossbar may comprise, in a wireless device comprising a receiver path with an analog crossbar: receiving a digital signal comprising a plurality of channels; amplifying the received signal; converting the amplified signal to an analog signal; separating the analog signal into a plurality of separate channels; routing the plurality of separate channels to desired signal paths utilizing the analog crossbar; and converting the routed plurality of separate channels to a plurality of digital signals. The analog crossbar may comprise an array of complementary metal-oxide semiconductor (cmos) transistors.
|Pulse signal output circuit and shift register|
An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors.
|Peripheral viewing system for a vehicle|
A peripheral viewing system for a vehicle includes a pair of digital cameras, each positioned on the exterior of the vehicle proximately positioned where a side view mirror would typically be mounted. An additional digital camera is mounted on the vehicle roof immediately adjacent the top edge of the rear window.
|Power amplifier circuit based on a cascode structure|
A power amplifier circuit based on a cascode structure and to be powered by a power source voltage, e.g. A battery, said circuit comprising—a first transistor having a grid, source and drain terminal; said first transistor being connected in a common source mode;—a second grid source transistor having grid, source and drain terminal, said second transistor being connected in common grid mode;—a biasing circuit for biasing said first transistor and said second transistor.
|Semiconductor device having a complementary field effect transistor|
A method for controlling power supply current in a cmos circuit, the method including applying a first predetermined voltage to a diode connected n-channel replica transistor, the n-channel replica transistor operating in weak inversion, applying a first substrate voltage to the substrate of the n-channel replica transistor so that the current flowing in the n-channel replica transistor equals a first predetermined target current, and applying the first substrate voltage to substrates of n-channel transistors in the cmos circuit. .
|Comparator and clock signal generation circuit|
A comparator used in a clock signal generation circuit has first and second input transistors coupled to input signals of the comparator. First and second hysteresis transistors are coupled between the input transistors and an output stage of the comparator, and apply hysteresis to a comparison of the input signals.
|Pulse generation circuit and semiconductor device|
Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every m rows.
|Voltage level shifter circuit, system, and method for high speed applications|
A level shifting circuit includes a first inverter including a pair of transistors of opposite conductivity type, the first inverter adapted to receive an input signal in a first voltage domain and further including at least one additional transistor driven by a voltage in a second voltage domain. A second inverter is coupled in series with the first inverter and operable to generate an output signal in the second voltage domain.
|Apparatus and methods for voltage converter bypass circuits|
Apparatus and methods for voltage converter bypass circuits are provided. In one embodiment, a voltage conversion system includes a bypass circuit and a voltage converter including an inductor and a plurality of switches configured to control a current through the inductor.
|Digital circuit having correcting circuit and electronic apparatus thereof|
Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (vdd, vss); correcting circuits (34, 36) connected between an input terminal (in) inputted with an input signal and control terminals (gates) of the first transistors; capacitors (c2, c3) connected between the control terminals and the input terminal; diode-connected second transistors (35, 37) that are provided between nodes (n5, n6) between the capacitors and the control terminals and the power supply potentials and have the substantially same threshold voltage as the first transistors; and switches (sw2, sw3) connected in series with the second transistors.. .
|Electrical devices with graphene on boron nitride|
Methods of forming and resulting devices are described that include graphene devices on boron nitride. Selected methods of forming and resulting devices include graphene field effect transistors (gfets) including boron nitride..
|Transistors, methods of forming transistors and display devices having transistors|
A transistor, a display device, and associated methods, the transistor including a substrate; an active layer pattern disposed on the substrate, the active layer pattern including silicon and graphene; a gate insulating layer disposed on the active layer pattern; a gate electrode disposed on the gate insulating layer; an insulating interlayer covering the active layer pattern and the gate electrode; and a source electrode and a drain electrode in contact with the active layer pattern.. .
Nanoparticles, methods of manufacture, devices comprising the nanoparticles, methods of their manufacture, and methods of their use are provided herein. The nanoparticles and devices having photoabsorptions in the range of 1.7 μm to 12 μm and can be used as photoconductors, photodiodes, phototransistors, charge-coupled devices (ccd), luminescent probes, lasers, thermal imagers, night-vision systems, and/or photodetectors..
|Design structure for stacked cmos circuits|
An automated method of modifying a semiconductor chip design includes creating a timing analysis of said semiconductor chip design, identifying a pluraility of gates in said semiconductor chip design which have either too fast a rising edge or falling edge, for each gate in said plurality of gates adding a stacked transistor to provide delay to the rising or falling edge of the gate. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure includes a cmos device having a first transistor with a first input, a pair of stacked transistors having a second input, and an output..
|Bulk fin-field effect transistors with well defined isolation|
A computer program storage product includes instructions for forming a fin field-effect-transistor. The instructions are configured to perform a method.
|Sige sram butted contact resistance improvement|
The present disclosure relates to a method for fabricating a butted a contact arrangement configured to couple two transistors, wherein an active region of a first transistor is coupled to a gate of a second transistor. The gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active region of the first transistor and an isolation layer formed about the first transistor.
|Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features|
Systems and methods are disclosed for providing selective threshold voltage characteristics via use of mos transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer.
|Sense amplifier circuit and semiconductor device|
A single-ended sense amplifier circuit of the invention comprises first and second mos transistors and first and second precharge circuits. The first mos transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second mos transistor whose gate is connected to the sense node amplifies the signal via the first mos transistor.
|Non-volatile memory device having vertical structure and method of operating the same|
A non-volatile memory device having a vertical structure includes a nand string having a vertical structure. The nand string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells.
|Select gate materials having different work functions in non-volatile memory|
In a 3d stacked non-volatile memory device, multiple smaller drain-end selected gate (sgd) transistors replace one larger sgd transistor. The sgd transistors have different work functions in their control gates so that, during a programming operation, a discontinuous channel potential is created in an inhibited nand string.
|Adjusting control gate overdrive of select gate transistors during programming of non-volatile memory|
In a 3d stacked non-volatile memory device, multiple smaller drain-end selected gate (sgd) transistors replace one larger sgd transistor. The sgd transistors have different control gate overdrive voltages so that, during a programming operation, a discontinuous channel potential is created in an inhibited nand string.
|8t sram cell with one word line|
An integrated circuit with sram cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and one passgate transistor may be variously configured to a separate read data line and write data line, or a combined data line, in different embodiments.
|Comparator, solid-state imaging device, electronic apparatus, and driving method|
A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a first condenser that is disposed between a gate electrode of the first transistor and a reference signal supply unit; a second condenser that is disposed between a gate electrode of the second transistor and a pixel signal wiring; a third transistor that connects a connection point of the gate electrode of the first transistor and the first condenser to the pixel signal wiring; and a fourth transistor that connects a connection point of the gate electrode of the second transistor and the second condenser to the pixel signal wiring.. .
|Pixel circuit and driving method and display device thereof|
A pixel circuit includes an oled, a driving transistor, first and second transistors, a storage capacitor and a coupling capacitor. The oled includes an anode and a cathode connected to a first voltage source.
|Pixel circuit and driving method and display device thereof|
A pixel circuit includes an oled, a driving transistor, first and second transistors, a storage capacitor and a coupling capacitor. The oled includes an anode and a cathode connected to a first voltage source.
|Organic light emitting display device having repaired pixel and pixel repairing method thereof|
An organic light emitting display device employing organic light emitting diodes (oleds) is disclosed. One aspect includes a plurality of pixels positioned at intersection portions of scan lines and data lines, each having an organic light emitting diode and a pixel circuit driving the organic light emitting diode; a scan driver supplying a scan signal to the scan lines and supplying an emission control signal to an emission control line coupled to the pixels; and a data driver supplying a data signal to the data lines.
|Multigate resonant channel transistor|
An embodiment includes an oscillator comprising an amplifier formed on a substrate; a multiple gate resonant channel array, formed on the substrate, including: (a) transistors including fins, each of the fins having a channel between source and drain nodes, coupled to common source and drain contacts; and (b) common first and second tri-gates coupled to each of the fins and located between the source and drain contacts; wherein the fins mechanically resonate at a first frequency when one of the first and second tri-gates is periodically activated to produce periodic downward forces on the fins. Other embodiments include a non planar transistor with a channel between the source and drain nodes and a tri-gate on the fin; wherein the fin mechanically resonates when the first tri-gate is periodically activated to produce periodic downward forces on the fin.
|High-speed cmos ring voltage controlled oscillator with low supply sensitivity|
High-speed cmos ring voltage controlled oscillators with low supply sensitivity have been disclosed. According to one embodiment, a cml ring oscillator comprises a cml negative impedance compensation circuit comprising two cross coupled transistors and a resistor connected to the two transistors for resistive biasing and a cml interpolating delay cell connected in parallel with the cml negative impedance compensation.
|Folded cascode amplifier circuit|
A folded cascode amplifier circuit includes: an input stage having a pair of transistors and configured to output a positive phase intermediate signal and an opposite phase intermediate signal; a cascode amplification stage having pairs of transistors connected in multiple stages, to which the positive phase intermediate signal and the opposite phase intermediate signal are supplied, and which is configured to output a positive phase output signal and an opposite phase output signal, which are differential signals; a first capacitor connected between a signal line of the positive phase intermediate signal and a signal line of the opposite phase output signal; and a second capacitor connected between a signal line of the opposite phase intermediate signal and a signal line of the positive phase output signal.. .
|Amplification circuit, source driver, electrooptical device, and electronic device|
An amplification circuit that can reduce an area without using transistors with a high withstand voltage. The amplification circuit (100) includes: an operational amplifier with a first input terminal connected to a reference node; a first capacitor (ca1) provided between a first node and the reference node; a second capacitor (ca2) provided between a second node and the reference node; a switch element (sw1) provided between the first node and an input node of an input voltage; a switch element (sw2) provided between the first node and a supply node of a first analog reference voltage; a switch element (sw3) provided between the second node and an output node of an output voltage; a switch element (sw4) provided between the second node and a supply node of a second analog reference voltage; and a switch element (sw5) provided between the output node of the output voltage and the reference node..
|Radio-frequency power amplifier|
A device for radio-frequency power amplification having a switching arrangement is provided. The switching arrangement is configured to amplify, during operation, a radio-frequency input signal that is present at a signal input and has a low input power, and to provide, during continuous wave (cw) operation, a continuous output signal at an output.
|Semiconductor device with a current sampler and a start-up structure|
A semiconductor device with a current sampler and a start-up structure, comprises first, second and third high-voltage transistors, and a resistor, wherein: a drain terminal of the first transistor is respectively connected to a drain terminal of the second transistor, a drain terminal of the third transistor and one end of the resistor; a source terminal of the first transistor is grounded, and a gate terminal of the first transistor is connected to a gate terminal of the second transistor; the other end of the resistor is connected to a gate terminal of the third transistor; wherein the resistor is wound and formed in a common voltage withstand region of the first transistor, the second transistor and the third transistor, or in a voltage withstand region of the first transistor only, or in the voltage withstand region of the third transistor only.. .
|High voltage inverter utilizing low voltage oxide mofset devices|
An inverter circuit includes an input stage and an output stage, each including pairs of complementary transistors having low-voltage oxides. The transistors within the input stage are configured to receive the input signal and to provide control voltages in response to input signal voltage variations.
|Low power clock gating circuit|
A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors for receiving at least the logic enable signal and generating a first output; a second plurality of transistor for receiving at least the first output and generating a second output; a third plurality of transistors for receiving at least the second output and an inverted second output; and an and gate circuit, for receiving the second output and generating the clock enable signal when the logic enable signal is at logic 1. One transistor of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors, respectively, receives the clock input signal at its gate..
|Field-programmable gate array|
An fpga has a number of clbs, each clb having a number of cabs (10, 110, 210, 310, 410). Each cab (10, 110, 210, 310, 410) comprises: a number of configurable transistors (20, 120, 220, 320, 420) each comprising one or more useable transistors m and a number of switching transistors; and, configuration circuitry comprising a number of switching transistors.
|Magnetic resonance imaging with switched-mode current-source amplifier having gallium nitride field effect transistors for parallel transmission in mri|
Example systems, apparatus, circuits, and other embodiments described herein concern parallel transmission in mri. One example apparatus includes at least two enhanced mode gallium nitride (egan) based field effect transistors (fets) that are connected by a coil that includes an lc (inductance-capacitance) leg.
|Dc decoupled current measurement|
A circuit arrangement for measuring a load current provided to a load via a first load terminal of a load transistor is disclosed. In accordance with one example of the invention, the circuit arrangement includes a sense transistor coupled to the load transistor to provide a sense current representing the load current at a first load terminal of the sense transistor.
|Cascode semiconductor device|
A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration: wherein the first field effect transistor is a depletion mode transistor; and wherein the second field effect transistor comprises a first source to gate capacitance and a second additional source to gate capacitance connected in parallel to the first source to gate capacitance. A power factor correction (pfc) circuit comprising the semiconductor device.
|Circuit and method for independent control of series connected light emitting diodes|
Described herein is a circuit and method for independent control of series connected light emitting diodes (leds). The circuit includes a first light emitting diode (led) connected in series with a second led.
|Semiconductor-on-insulator integrated circuit with interconnect below the insulator|
An integrated circuit assembly comprises an insulating layer, a semiconductor layer, a handle layer, a metal interconnect layer, and transistors. The insulating layer has a first surface, a second surface, and a hole extending from the first surface to the second surface.
|Tid hardened and single even transient single event latchup resistant mos transistors and fabrication process|
A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material.
|Mos transistor and fabrication method|
Mos transistors and fabrication methods are provided. An exemplary mos transistor includes a gate structure formed on a semiconductor substrate.
|Photoelectric conversion apparatus, imaging apparatus using the same, and manufacturing method thereof|
A photoelectric conversion apparatus includes: an active matrix-type tft array substrate on which photoelectric conversion elements and thin film transistors are arranged in a matrix shape, wherein the photoelectric conversion element connects with a drain electrode via a contact hole opened through a first interlayer insulation film provided above the thin film transistor, wherein a data line and a bias line are connected with the source electrode and the photoelectric conversion element via respective contact holes opened through the second interlayer insulation, and wherein at least a part of the photoelectric conversion element is fixed to have a shape different from a normal pixel between pixels adjacent to each other in an extending direction of the gate line, and an electrical connection between the photoelectric conversion element and the data line is cut off in the transistor of the pixel having the different shape.. .
|Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods|
A first linear-shaped conductive structure (lcs) forms gate electrodes (ge's) of a first transistor of a first transistor type and a first transistor of a second transistor type. A second lcs forms a ge of a second transistor of the first transistor type.
|Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods|
A first linear-shaped conductive structure (lcs) forms a gate electrode (ge) of a first transistor of a first transistor type. A second lcs forms a ge of a first transistor of a second transistor type.
|Power device chip and method of manufacturing the power device chip|
According to example embodiments, a power device chip includes a plurality of unit power devices classified into a plurality of sectors, a first pad and a second pad. At least one of the first and second pads is divided into a number of pad parts equal to a number of the plurality of sectors.
|Surge protection circuit for power mosfets used as active bypass diodes in photovoltaic solar power systems|
A protection circuit for metal-oxide-semiconductor field-effect transistors (mosfets) that are used as active bypass diodes in photovoltaic solar power systems is disclosed. The protection circuit comprises, a detection circuit for detecting the start of a surge event, a switch disposed to connect the mosfet's drain to it's gate in response to the start of the surge, a diode in series with the switch, a bistable circuit for keeping the switch closed during the surge, and a means of resetting the bistable circuit after the surge..
|Group iii-n transistors on nanoscale template structures|
A iii-n semiconductor channel is formed on a iii-n transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the iii-n epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness.
|Active matrix solid state light display|
An exemplary active matrix solid state light display includes a substrate, a plurality of solid state lighting elements and a plurality of thin film transistors. A buffer layer is formed on the substrate.
|Flip-chip solid state light display|
An exemplary flip-chip solid state light display includes a substrate, a plurality of solid state lighting elements and a plurality of thin film transistors; the solid state lighting elements and the thin film transistors are located on the substrate, and the solid state lighting elements each are adjacent to one respective thin film transistor. The solid state lighting elements each are a light emitting diode, and are mounted on the substrate by a way of flip-chip.
|Organic light emitting device display and manufacturing method thereof|
Provided is an organic light emitting display including a pixel circuit unit prepared over a substrate and comprising a plurality of thin film transistors (tfts), and an organic light emitting device or diode (oled) electrically connected to the pixel circuit unit. The pixel circuit unit and the oled are connected through a repair unit comprising a semiconductor material, in order to facilitate easy repair..
|Compound tunneling field effect transistor integrated on silicon substrate and method for fabricating the same|
Compound tunneling field effect transistors integrated on a silicon substrate are provided with increased tunneling efficiency and an abrupt band slope by forming a source region with a material having a bandgap at least 0.4 electron volts (ev) narrower than that of silicon to increase a driving current (on current) by forming a channel region with a material having almost no difference in lattice constant from a source region and having a high electron mobility at least 5 times higher than silicon. On/off current ratio simultaneously is increased by forming a drain region with a material having a bandgap at least as wide as a channel region material to restrain off current.
|Extreme high mobility cmos logic|
A cmos device includes a pmos transistor with a first quantum well structure and an nmos device with a second quantum well structure. The pmos and nmos transistors are formed on a substrate..
|Method and system for a feedback transimpedance amplifier with sub-40khz low-frequency cutoff|
A system for a feedback amplifier with sub-40khz low-frequency cutoff is disclosed and may include amplifying electrical signals received via coupling capacitors utilizing an amplifier having feedback paths comprising source followers and feedback resistors. Gate terminals of the source followers may be coupled to output terminals of the amplifier circuit.
|Comparator, solid-state imaging device, electronic apparatus, and driving method|
A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a third transistor that connects the first transistor to a power source voltage; a fourth transistor that connects the second transistor to the power source voltage; a fifth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the third transistor; and a sixth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the fourth transistor.. .
|Spatial orientation of the carbon nanotubes in electrophoretic deposition process|
A new method of electrophoretic nanotube deposition is proposed wherein individual nanotubes are placed on metal electrodes which have their length significantly exceeding their width, while the nanotube length is chosen to be close to that of the metal electrode. Due to electrostatic attraction of individual nanotube to the elongated electrode, every nanotube approaching the electrode is deposited along the electrode, since such an orientation is energetically favorable.
|Semiconductor memory with sense amplifier|
In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.. .
|Nonvolatile semiconductor memory device|
A nonvolatile semiconductor memory device according to an embodiment includes a memory string having a plurality of electrically rewritable memory transistors connected in series therein. The memory string includes a first semiconductor layer including a columnar portion extending in a perpendicular direction to a substrate; a tunnel insulating film formed surrounding a side surface of the columnar portion; a charge storage film formed surrounding the tunnel insulating film; a block insulating film formed surrounding the charge storage film; and a plurality of first conductive layers formed surrounding the block insulating film and disposed with a certain spacing along the perpendicular direction.
|Resistance change memory|
According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals.
|Electric power conversion system|
An electric power conversion system includes: a primary electric power conversion circuit including a primary coil connected to a connection point between a plurality of transistors; a secondary electric power conversion circuit configured similarly to the primary electric power conversion circuit and including a secondary coil corresponding to the primary coil; and a control circuit controlling transfer of electric power between the primary and secondary electric power conversion circuits. The control circuit executes feedforward control for setting one of an on/off ratio of a terminal voltage signal of the primary coil and an on/off ratio of a terminal voltage signal of the secondary coil, in response to at least one of fluctuations in voltage ratio between both waveforms and fluctuations in phase symmetry between both waveforms, when the terminal voltage waveform of the primary coil and the terminal voltage waveform of the secondary coil are different from each other..
|Method for driving display device|
A method for driving a display device in which characteristics of a transistor including an oxide semiconductor can approximately be recovered to characteristics before deterioration is provided. In the method for driving the display device, by which images are displayed with the use of a plurality of frame periods, the display device is driven so that a voltage of 20 v or higher can be applied to a gate of a transistor, which is a driving element, for 1 millisecond or longer in a period, in which any one of scan lines is selected, in each frame period.
|Display apparatus and electronic equipment|
A plurality of pixel circuits provided in a display apparatus respectively include light-emitting elements oled, first transistors that supply driving currents to the light-emitting elements, second transistors that turn on and off connection between data lines and gates of the first transistors, and third transistors. The display apparatus has first holding capacitors that are respectively inserted and connected midway on the plurality of data lines and shift levels of driving voltages of the first transistors, and holding capacitors that respectively hold potentials of the plurality of data lines.
A display device in which the current load of wirings are distributed and display variations due to voltage drop are suppressed. An active matrix display device of the invention comprises a first current input terminal, a second current input terminal, and a plurality of current supply lines extending parallel to each other.
|Electronic biasing circuit for constant transconductance|
An electronic biasing circuit provides a dc bias voltage to a circuit to be biased. The biasing circuit has a first transistor and a second transistor.
|Semiconductor device and trimming method for the same|
According to one embodiment, a semiconductor device includes a termination circuit and a controller. The termination circuit includes a first resistor connected to an external connection terminal, a plurality of first transistors of a first conductive type connected in parallel between the first resistor and a voltage source, a second resistor connected to the external connection terminal, and a plurality of second transistors of a second conductive type connected in parallel between the second resistor and ground.