|| List of recent Transistors-related patents
|Process for the preparation of polymers containing benzohetero [1,3] diazole units|
Process for the preparation of a polymer containing benzohetero[1,3]diazole. Units which comprises reacting at least one disubstituted benzohetero[1,3]diazole compound with at least one heteroaryl compound.
|Methodology and apparatus for tuning driving current of semiconductor transistors|
A method and apparatus for repairing transistors may include applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time. In this manner the transistor structure may be repaired or returned to operate at or near the original operating characteristics..
|Rolled-up, three-dimensional field-effect transistors and the use thereof in electronics, sensors and microfluidics|
Field-effect transistors include at least two thin layers of a semiconductor material and of an electrically conductive gate material that are rolled up together. These two layers are arranged separated from one another by one or multiple barrier layers and this rolled-up multi-layer structure is integratable as field-effect transistors in circuits and/or in microfluid systems as sensors for the detection of fluids..
|Amplifier for electrostatic transducers|
A class d audio amplifier which provides both an alternating signal and a dc bias voltage to an electrostatic transducer (9). The amplifier comprises an input module (1) for generating a modulated sequence of pulses in response to an input audio signal, and an output module (3) for amplifying the sequence of pulses, which includes high speed switching output transistors (4, 5).
|Row decoding circuit|
A row decoding circuit including row decoding blocks is provided. Each of the row decoding blocks includes row decoders.
|Nonvolatile semiconductor memory device|
A control circuit is configured to, during an erase operation, set a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage. The control circuit is configured to, during the erase operation, set a voltage difference between a voltage of a first line connected to an unselected cell unit and a voltage of a gate of a first transistor included in the unselected cell unit to a second voltage, the second voltage differing from the first voltage.
|Word-line driver for memory|
A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line.
|Nonvolatile semiconductor memory device|
A nonvolatile semiconductor memory device includes a memory cell, a bit line electrically connected to the memory cell, a sense amplifier that includes a first transistor having a first end electrically connected to the bit line, a second transistor electrically connected between a second end of the first transistor and ground, a third transistor electrically connected between a second end of the first transistor and a source line, and a controller configured to control the first, second, and third transistors after performing a program operation. After the program operation, the first and second transistors are turned on and then while the first transistor remains turned on, the second transistor is turned off and the third transistor is turned on..
|Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate|
A one-time programmable (otp) memory cell includes a dual date transistor and, in some embodiments, two transistors. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device.
|3d stacked nand flash memory array having ssl status check buildings for monitoring threshold voltages of string selection transistors and methods for monitoring and operating the same|
Disclosed is a 3d stacked nand flash memory array having ssl status check buildings for monitoring threshold voltages of string selection transistors, a monitoring method of threshold voltages of string selection transistors by the ssl status check buildings, and an operating method thereof.. .
|Flash memory device reducing layout area|
A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of select connection portions corresponding thereto are disposed in one common active region.
|Nonvolatile semiconductor memory|
A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.. .
|Integrated gate driver circuit and liquid crystal panel|
An integrated gate driver circuit includes a control circuit, a plurality of drive stages and a plurality of discharge transistors. The control circuit is configured to output a plurality of clock signals within a frame period and to output a discharge enabling signal within a blanking period of the frame period.
|Display circuitry with reduced pixel parasitic capacitor coupling|
A touch screen display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (tft) layer.
|Solid-state imaging device, manufacturing method thereof, and electronic apparatus|
A solid-state imaging device having a backside illuminated structure, includes: a pixel region in which pixels each having a photoelectric conversion portion and a plurality of pixel transistors are arranged in a two-dimensional matrix; an element isolation region isolating the pixels which is provided in the pixel region and which includes a semiconductor layer provided in a trench by an epitaxial growth; and a light receiving surface at a rear surface side of a semiconductor substrate which is opposite to a multilayer wiring layer.. .
|Scanner, electro-optical panel, electro-optical display device and electronic apparatus|
A scanner includes a plurality of unit circuits configured with transistors of a same conductivity type. In the scanner, the unit circuit constituting the scanner includes an output transistor that selectively outputs, to an output terminal of the unit circuit, a signal given from an outside.
|Display panel source line driving circuitry|
An electronic display system has a light transmissive panel, a region of display elements on the panel, and source lines coupled to the display elements. A demultiplexor circuit has multiple groups of pass gates.
|Compensation technique for luminance degradation in electro-luminance devices|
A method and system for compensation for luminance degradation in electro-luminance devices is provided. The system includes a pixel circuit having a light emitting device, a storage capacitor, a plurality of transistors, and control signal lines to operate the pixel circuit.
|Voltage generator, switch and data converter circuits|
A data converter can include a resistor network, a switch network connected to the resistor network and having a plurality of switch circuits, each with an nmos and a pmos switch transistor, and a voltage generator to generate a drive voltage for driving a gate of at least one of the nmos or pmos switch transistors of at least one of the switch circuits. The voltage generator can include first and second pairs of transistors, each pair having connected control terminals and being connected to a second nmos or pmos transistor, a first or second resistor, and the other pair of transistors.
|Power amplifier using differential structure|
Provided is a power amplifier which includes: a first transistor and a second transistor each having a first end connected to a first power source supplying a first voltage and to which signals having a same size but opposite polarities are input; a third transistor and a fourth transistor having first ends respectively connected to the first ends of the first transistor and the second transistor; and a fifth transistor having a first end connected to second ends of the third and fourth transistors and controlling oscillation of the third or fourth transistor.. .
A semiconductor device includes a first semiconductor chip which includes a first power supply terminal and into which a circuit block which is operated by a power supply voltage supplied to the first power supply terminal is integrated, a power circuit that includes switching transistors and supplies the power supply voltage to the first power supply terminal, and a dcdc control unit that is formed on the first semiconductor chip and generates a control signal for controlling the turning on and off of the switching transistors in response to an information signal from the circuit block and a voltage information signal corresponding to an output voltage from the power circuit.. .
|Circuit element including a layer of a stress-creating material providing a variable stress and method for the formation thereof|
A transistor includes a source region, a drain region, a channel region, a gate electrode and a layer of a stress-creating material. The stress-creating material provides a stress that is variable in response to a signal acting on the stress-creating material.
|Light emitting diode driver|
A driver circuit for driving light emitting diodes (leds). The driver circuit includes: a string of leds divided into n groups, the n groups of leds being electrically connected to each other in series, a downstream end of group m−1 being electrically connected to the upstream end of group m, where m is a positive number equal to or less than n.
The present invention generally relates to powering a switching controller of a switch mode power converter (smpc), and more particularly to a method of providing power to a switching controller of a smpc, to a charging circuit for supplying charge to a charge store for providing power to a switching controller of a smpc, and to an smpc comprising such a circuit. A method of providing power to a switching controller of a switch mode power converter (smpc), the smpc having: an inductive component having a winding coupled to receive power from an input to said smpc; a switching circuit comprising first and second switching transistors, said first transistor coupled in series between said winding and said second transistor; a switching controller to control switching of said second transistor; and a charge store to provide power to said switching controller, the method comprising: flow of current from said winding through said first transistor; and diverting said current through a conduction path to said charge store..
|Uni-directional transient voltage suppressor (tvs)|
A unidirectional transient voltage suppressor (tvs) device includes first and second npn transistors that are connected in parallel to each other. Each npn transistor includes a collector region, an emitter.
|Methods and apparatus of metal gate transistors|
Methods and devices for forming a contact over a metal gate for a transistor are provided. The device may comprise an active area, an isolation area surrounding the active area, and a metal gate above the isolation area, wherein the metal gate comprises a conductive layer.
|Transistors with isolation regions|
A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions.
|Magneto-electric voltage controlled spin transistors|
The invention relates to a magneto-electric spin-fet including a gate film of chromia and a thin film of a conductive channel material which may be graphene, inp, gaas, gasb, pbs, mos2, ws2, mose2, wse2 and mixtures thereof. The chromia, or other magneto-electric, and conduction channel material are in intimate contact along an interface there between.
|Collector-up bipolar junction transistors in bicmos technology|
Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate.
|Collector-up bipolar junction transistors in bicmos technology|
Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate.
|Methodology for fabricating isotropically recessed source regions of cmos transistors|
A field effect transistor device includes a buried oxide layer, a silicon layer above the buried oxide layer, an isotropically recessed source region, and a gate stack comprising a gate dielectric, a conductive material, and a spacer.. .
The inventors found out that in the case of performing a low gray scale display in which a very small amount of current is supplied to a light emitting element, variations in threshold voltages of driving transistors become notable since the gate-source voltage is low. In view of this, the invention provides a display device in which variations in the threshold voltages of the driving transistors are reduced even in the low gray scale display, and a driving method thereof.
The semiconductor device of the present invention comprises first and second transistors and first and second capacitors. One of source and drain electrodes of the first transistor is electrically connected to a first wiring, the other is electrically connected to a second wiring, and a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor and one of electrodes of the first capacitor.
|Remote doping of organic thin film transistors|
Organic electronic devices comprising “remotely” doped materials comprising a combination of at least three layers. Such devices can include “remotely p-doped” structures comprising: a channel layer comprising at least one organic semiconductor channel material; a dopant layer, which comprises at least one p-dopant material and optionally at least one organic hole transport material; and a spacer layer disposed between and in electrical contact with both the channel layer and the dopant layer, comprising an organic semiconducting spacer material; or alternatively can include “remotely n-doped” structures comprising a combination of at least three layers: a channel layer comprising at least one organic semiconductor channel material; a dopant layer which comprises at least one organic electron transport material doped with an n-dopant material; and a spacer layer disposed between and in electrical contact with the channel layer and the dopant layer, comprising an organic semiconducting spacer material.
|Low-mismatch and low-consumption transimpedance gain circuit for temporally differentiating photo-sensing systems in dynamic vision sensors|
The invention relates to a low-mismatch and low-consumption transimpedance gain circuit for temporally differentiating photo-sensing systems in dynamic vision sensors, which uses at least one photodiode and at least two in-series transistors, each of the transistors being connected in diode configuration and being positioned at the output of the photodiode. The output current from the photodiode flows through the drain-source channels of the transistors and the source of the last transistor in series is connected to a voltage selected from ground voltage, a constant voltage or a controlled voltage..
|Amplifier and wireless communication device|
In a power amplifier including an amplifier circuit unit for high power mode and an amplifier circuit unit for low power mode provided in parallel thereto between input and output of the amplifier and where, when one amplifier circuit unit is in an operating state, the other amplifier circuit unit is in a non-operating state, a cross-coupled capacitor is provided between a drain of one of two transistors in output side and a gate of the other transistor in the amplifier circuit unit for high power mode, and a series circuit where a switch and a capacitor are coupled in series is coupled between a drain of the transistor of output side in the amplifier circuit unit for low power mode and a ground, the switch being in a conducting state in high power mode operation and being in a non-conducting state in low power mode operation.. .
|Body-biased switching device|
Embodiments provide a switching device including one or more field-effect transistors (fets). In embodiments, a body-bias circuit may derive a bias voltage based on a radio frequency signal applied to a switch field-effect transistor and apply the bias voltage to the body terminal of the switch field-effect transistor..
|Shallow trench isolation integration methods and devices formed thereby|
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a tsv device having a “buffer zone” or gap layer between the tsv and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices.
|Methods of forming multiple n-type semiconductor devices with different threshold voltages on a semiconductor substrate|
One illustrative method disclosed herein involves forming an integrated circuit product comprised of first and second n-type transistors formed in and above first and second active regions, respectively. The method generally involves performing a common threshold voltage adjusting ion implantation process on the first and second active regions, forming the first and second transistors, performing an amorphization ion implantation process to selectively form regions of amorphous material in the first active region but not in the second active region, after performing the amorphization ion implantation process, forming a capping material layer above the first and second transistors and performing a re-crystallization anneal process to convert at least portions of the regions of amorphous material to a crystalline material.
|Second-order input intercept point (iip2) calibration method of a mixer in a wireless communication system and the mixer using the same|
A mixer included in a receiver of a wireless communication system is provided. The mixer includes a switching unit including a plurality of transistors receiving a radio frequency (rf) signal and a local oscillation (lo) signal, and outputting a baseband signal, and a voltage controller outputting a voltage control signal controlling a body voltage of at least one transistor from among the plurality of transistors to thereby control a threshold voltage of the at least one transistor..
|Memory device word line drivers and methods|
Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors.
|Current mode sense amplifier with passive load|
Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance..
|Non-volatile memory including bit line switch transistors formed in a triple-well|
Non-volatile memory and methods of operating non-volatile memory reduce breakdown and leakage associated with bit line (bl) switch transistors. The bl switch transistors for a memory array are formed in a well that is electrically isolated from a well associated with the memory array.
|Signal transmission circuit|
A signal transmission circuit includes an isolation circuit, first and second grounded gate circuits, first and second mos transistors, and a comparator. The isolation circuit such as a thin-film transformer outputs complementary first and second output signals, based on an input signal.
|Analog to digital converter for solid-state image pickup device|
There is provided a solid-state image pickup device including adcs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node.
|Light emitting device, method of driving a light emitting device, element substrate, and electronic equipment|
A display device capable of obtaining a constant luminance without being influenced by temperature change is provided as well as a method of driving the display device. A current mirror circuit composed of a first transistor and a second transistor is provided in each pixel.
A flip-flop circuit has a master latch circuit and a slave latch circuit. In the flip-flop circuit, the master latch circuit and the slave latch circuit share at least a pair of transistors.
|Output slew rate control|
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a dram output driver on a die.
|Pseudo-inverter circuit with multiple independent gate transistors|
The invention relates to a a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (g1p, g1n) and a second (g2p, g2n) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (g2p, g2n).. .
A voltage converter is disclosed. The voltage converter includes a constant on time signal generator, a first and second transistors, an inductor, a feedback circuit and a ripple injection circuit.
|Receiving circuit, semiconductor device, and sensor device|
A receiving circuit (10) includes an amplifier (15) which amplifies receiving signals (sp, sn) of a piezoelectric sensor (2), and a plurality of transistors (11a, 11b) or (12a, 12b), which are connected in parallel to between one end of the piezoelectric sensor (2) and one end of the amplifier (15), and are turned on with phase shift when switching is performed to receiving operations.. .
|Apparatus for transceiver signal isolation and voltage clamp and methods of forming the same|
An apparatus for transceiver signal isolation and voltage clamp from transient electrical events includes a bi-directional protection device comprising a bipolar pnpnp device assembly, a first parasitic pnpn device assembly, and a second parasitic pnpn device assembly. The bipolar pnpnp device assembly includes an npn bi-directional bipolar transistor, a first pnp bipolar transistor, and a second pnp bipolar transistor, and is configured to receive a transient voltage signal through first and second pads.
|Semiconductor device, method of manufacturing the same, and signal transmitting/receiving method using the semiconductor device|
A semiconductor device includes a semiconductor chip including a main surface, an internal circuit including a plurality of transistors, formed on the main surface, a bonding pad electrically connected to the internal circuit, formed on the main surface, an inductor for communicating an external device in a non-contact manner, formed on the main surface, and a seal ring formed along an outer peripheral edge of the semiconductor chip to surround the internal circuit and the bonding pad in a plan view. The inductor has a configuration to surround the internal circuit and the bonding pad in the plan view and along the seal ring.
|Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry|
In accordance with the invention, an improved image sensor comprises an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques.
|Carbon nanostructure device fabrication utilizing protect layers|
Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.. .
|Electronic device including a nonvolatile memory structure having an antifuse component|
An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include a substrate, an access transistor, a read transistor, and an antifuse component. Each of the access and read transistors can include source/drain regions at least partly within the substrate, a gate dielectric layer overlying the substrate, and a gate electrode overlying the gate dielectric layer.
|Embedded nvm in a hkmg process|
A process integration is disclosed for fabricating complete, planar non-volatile memory (nvm) cells (110) prior to the formation of high-k metal gate electrodes for cmos transistors (212, 213) using a planarized dielectric layer (26) and protective mask (28) to enable use of a gate-last hkmg cmos process flow without interfering with the operation or reliability of the nvm cells.. .
|Semiconductor constructions, dram arrays, and methods of forming semiconductor constructions|
The invention includes methods for utilizing partial silicon-on-insulator (soi) technology in combination with fin field effect transistor (finfet) technology to form transistors particularly suitable for utilization in dynamic random access memory (dram) arrays. The invention also includes dram arrays having low rates of refresh.
|Integrated half-bridge circuit with low side and high side composite switches|
There are disclosed herein various implementations of an integrated half-bridge circuit with low side and high side composite switches. In one exemplary implementation, such an integrated half-bridge circuit includes a iii-n body including first and second iii-n field-effect transistors (fets) monolithically integrated with and situated over a first group iv fet.
|Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer|
An soi wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (box) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed.
|Vertical gallium nitride transistors and methods of fabricating the same|
A vertical gallium nitride transistor according to an exemplary embodiment of the present invention includes a semiconductor structure including a first semiconductor layer of a first conductivity-type having a first surface and sidewalls, a second semiconductor layer of the first conductivity-type surrounding the first surface and the sidewalls of the first semiconductor layer, and a third semiconductor layer of a second conductivity-type disposed between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer separating the first and second semiconductor layers from each other.. .
|System on chip with embedded security module|
An embedded security module includes a security processor, volatile and non-volatile memory, and an interface. The security processor includes transistors formed in one or more semiconductor layers of a semiconductor die, and implements one or more security-related functions on data and/or code accessed by the security processor.
|Multiple voltage identification (vid) power architecture, a digital synthesizable low dropout regulator, and apparatus for improving reliability of power gates|
Described is an apparatus comprising: first and second processing cores; and a pcu which is operable to: generate a first vid for an off-die regulator external to the apparatus, the first vid resulting in a first power supply for the first processing core; and generate a second vid different from the first vid, the second vid resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an adc to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors..
|Coupled heteroaryl compounds via rearrangement of halogenated heteroaromatics followed by oxidative coupling (electron withdrawing groups)|
The inventions disclosed and described herein relate to new and efficient generic methods for making a wide variety of compounds having har—z-har tricyclic cores, wherein har is an optionally substituted five or six membered heteroaryl ring, and hal is a halogen, and z is a bridging radical, such as s, sc, nr5, c(o), c(o)c(o), si(r5)2, so, so2, pr5, br5, c(r5)2 or p(o)r5 and both har are covalently bound to one another. The synthetic methods employ a “base-catalyzed halogen dance” reaction to prepare a metallated compound comprising a five or six membered heteroaryl ring comprising a halogen atom, and then oxidatively coupling the reactive intermediate compound.
|High freuency semiconductor switch and wireless device|
A high frequency semiconductor switch has a first terminal, second terminals, a first through fet group, second through fet groups and a shunt fet group. The first through fet group has first field effect transistors connected serially with each other.
|Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same|
Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor.
|Method for fabricating complementary tunneling field effect transistor based on standard cmos ic process|
Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard cmos ic process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ulsi) circuits. In the method, an intrinsic channel and body region of a tfet are formed by means of complementary p-well and n-well masks in the standard cmos ic process to form a well doping, a channel doping and a threshold adjustment by implantation.
|Programming select gate transistors and memory cells using dynamic verify level|
Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation.
|Program and read methods of memory devices using bit line sharing|
A program method of a nonvolatile memory device includes loading first word line data to be stored in first memory cells connected to a first word line and second word line data to be stored in second memory cells connected to a second word line; setting up upper bit lines according to the first word line data; turning off bit line sharing transistors after the upper bit lines are set up; setting up lower bit lines according to the second word line data; performing a first program operation on the first memory cells using the upper bit lines; turning on the bit line sharing transistors; and performing a second program operation on the second memory cells using the lower bit lines. The bit line sharing transistors electrically connect the upper bit lines and the lower bit lines in response to a bit line sharing signal..
|High power converter with low power transistors connected in parallel|
A system for converting a first electric voltage into a second electric voltage, comprising: at least two input terminals and two output terminals; and switching members disposed between the terminals, which can convert the first voltage into the second voltage. At least one switching member comprises at least two arms connected in parallel and each arm includes an electronic switch that can be controlled such as to occupy either an on-state or an off-state, said switch comprising a control electrode and two conduction electrodes that conduct current in the on-state.
|Shift register circuit, display panel, and electronic apparatus|
Disclosed herein is a shift register circuit that is formed on an insulating substrate with thin film transistors having channels of the same conductivity type and includes shift stages, each of the shift stages including: a first thin film transistor; a second thin film transistor; a 3(1)-th thin film transistor; a 3(2)-th thin film transistor; a 4(1)-th thin film transistor; a 4(2)-th thin film transistor; a fifth thin film transistor; and a sixth thin film transistor.. .
|Rf switches having increased voltage swing uniformity|
Radio-frequency (rf) switch circuits are disclosed providing uniform voltage swing across a transmit switch for improved device performance. A switching circuit includes a switch having field effect transistors (fets) defining an rf signal path between the input port and the output port, the switch configured to be capable of being in a first state corresponding to the input and output ports being electrically connected so as to allow passage of the rf signal therebetween, and a second state corresponding to the input and output ports being electrically isolated.
|Semiconductor device and clock data recovery system including the same|
A semiconductor device includes a latch circuit. The latch circuit includes a sampling section that latches a differential input signal applied from a differential input node to the gates of a differential pair of transistors, a common adjusting section that adjusts a common potential of the differential input signal by adjusting based on a current control signal the amount of current that is drawn from the differential input node, and a common control section that controls the current control signal so that the differential pair of transistors operate in a saturated region, and supplies the controlled current control signal to the common adjusting section..