|| List of recent Transistors-related patents
|Parasitic capacitance extraction for finfets|
A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of fin field-effect transistors (finfets).
|Method of converting between non-volatile memory technologies and system for implementing the method|
A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (i/o) interface, a first type of charge pump, and an i/o block.
|Audio accessory circuitry and method compatible with both msft mode and digital communication mode|
An audio accessory key detection system (40) includes a host circuit (2-3) coupled to communicate via a microphone line (7) with an accessory circuit (3-3) in either a msft mode or a digital communication mode. Depletion mode transistors (44-1,2,3) in the accessory circuit are coupled between keys (15-1,2,3) of the accessory circuit, respectively.
|Liquid crystal display device and electronic device including the same|
A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor.
|Voltage mode driver circuit for n-phase systems|
System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an n-phase polarity encoded transmitter when the transmission lines would otherwise be undriven.
|Programming select gate transistors and memory cells using dynamic verify level|
Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation.
|Method and apparatus for program and erase of select gate transistors|
Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells.
|Semiconductor memory device|
According to one embodiment, a memory cell, a word line, and a peripheral circuit are provided. In the memory cell, a ferroelectric film is provided for a gate insulating film.
|Memory devices with different sized blocks of memory cells and methods|
In an embodiment, each block of a plurality of blocks includes a respective plurality of strings of memory cells, where each of the plurality of strings of a block is coupled to a respective select transistor, and wherein each of the select transistors coupled to the plurality of strings of the block is coupled to a common first select line. The plurality of blocks includes n block sizes, where n may be an integer greater than or equal to three.
|Dual-port sram systems|
Schematic circuit designs for a dual-port sram cell are disclosed, together with various layout schemes for the dual-port sram cell. The dual-port sram cell comprises a storage unit and a plurality of partial dummy transistors connected to the outputs of the storage unit.
|Electric power conversion system|
An electric power conversion system includes: a primary electric power conversion circuit including primary right and left arms; a secondary electric power conversion circuit including secondary right and left arms; and a control circuit controlling transfer of electric power between the primary and secondary electric power conversion circuits by magnetically coupling a primary coil to a secondary coil. The control circuit sets an interphase difference in switching between right and left arm lower transistors in the primary electric power conversion circuit and an interphase difference in switching between right and left arm lower transistors in the secondary electric power conversion circuit on the basis of off times of the primary and secondary electric power conversion circuits such that a phase difference between terminal voltage waveforms of the primary and secondary coils is 0 and duty ratios of the terminal voltage waveforms are equal to each other..
|Solid-state imaging device and camera system|
A solid-state imaging device includes a pixel array unit having a plurality of pixels arranged in a matrix form which perform a photoelectric conversion, a pixel signal readout unit having a logic unit and performing a readout of a pixel signal from the pixel array unit, a regulator, a first circuit section, a second circuit section, and a stacked structure in which the first and second circuit sections are bonded, wherein the first circuit section has the pixel array unit disposed therein, and wherein the second circuit section has at least the logic unit and the regulator disposed therein, wherein the regulator includes a reference voltage generation, a plurality of output stage transistors, and an operational amplifier comparing the reference voltage and a commonized output voltage, and an output path of the output stage transistors are connected to a single node, and then is fed back to the operational amplifier.. .
The invention relates to digital-to-analog converters for converting current. The converter includes a pair of differential branches with two transistors controlled by a digital register activated at a clock frequency, and two resistive loads receiving the currents of the differential branches to produce a differential electrical signal representing the analog result of the conversion.
|Multi-power mode reference clock with constant duty cycle|
A power management apparatus and method for maintaining a substantially constant duty cycle of a reference clock signal in a multi-power oscillator, includes a first output power transistor in electrical parallel with a series arrangement of a second output power transistor and a switch, and a crystal oscillator capacitively coupled to a common gate of the first and second output power transistors, wherein a level of the reference clock signal power output is a normal power level when the switch is open and the level of the reference clock signal power output is a higher power level when the switch is closed to operate the second output power transistor in parallel with the first output power transistor.. .
|Rf switch gate control|
In one implementation, a switching circuit includes a pass switch including group iii-v, for example iii-nitride, transistors coupled between an input of the switching circuit and an output of the switching circuit. The switching circuit further includes a shunt switch configured to ground the input of the switching circuit while the pass switch is disabled.
|Gilbert mixer with negative gm to increase nmos mixer conversion|
A cross coupled nmos transistors providing a negative gm transistor feedback allows a mixer to saturate at a reduced input signal swing voltage when compared to a conventional mixer allowing the mixer to enter into the current mode operation at a reduced signal input voltage range. The linearity of the baseband signal path can be traded against the mixer gain and is improved if the signal swing in the baseband signal path is reduced.
|Low voltage level shifter for low power applications|
A level shifter circuit for low power applications that can shift the level of a digital signal that is below the threshold voltage of output transistors. The level shifter uses core transistors in the input stage and includes an intermediate stage that limits the voltage applied to the drain of the core transistors.
|Electronic control circuit comprising power transistors and method for monitoring the service life of the power transistors|
The disclosure relates to an electronic control circuit for an electric device, in particular designed as a commutation electric system of an ec motor, having a plurality of power transistors which are controlled in an operating mode for controlling the device. An additional, similar, non-charged reference transistor in the operating mode of the power transistors is arranged or formed together with the power transistors on a common support or substrate.
|Using synchronous converter in asynchronous mode to prevent current reversal during battery charging|
Efficiency of a switch mode power supply (smps) is optimized by operating the smps in an asynchronous mode when current being supplied therefrom is less than a certain current value and operating the smps in a synchronous mode when the current being supplied therefrom is equal to or greater than the certain current value. When the smps is operating in the synchronous mode high-side and low-side power transistors alternately turn on and off.
|Secure method of cutting off the power supply of an electric motor and corresponding device|
A device is provided for controlling and supplying power to a multi-phase electric motor powered by a main battery. The device includes an electronic power module, a drive module, and a monitoring unit.
|Light emitting diode driver|
A driver circuit for driving light emitting diodes (leds). The driver circuit includes: a string of leds divided into n groups, the n groups of leds being electrically connected to each other in series, a downstream end of group m-1 being electrically connected to the upstream end of group m, where m is a positive number equal to or less than n.
|Layout structure of standard cell, standard cell library, and layout structure of semiconductor integrated circuit|
In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively.
|Method of forming a cmos structure having gate insulation films of different thicknesses|
The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of mos transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These mos transistors include tunnel-current increased mos transistors at least one of which is for use in constituting a main circuit of the device.
|Gate security feature|
An anti-counterfeiting security circuit is incorporated into an authentic integrated circuit device to induce failure in a counterfeited integrated circuit device by forming the security circuit (e.g., 21, 31, 41, 51) with one or more operatively inert high-k metal gate transistors (e.g., hkmg pmos 112) having switched or altered work function metal layers (82) where the security circuit defines a first electrical function with the one or more operatively inert high-k metal gate transistors and defines a second different electrical function if the one or more operatively inert high-k metal gate transistors were instead fabricated as operatively functional high-k metal gate transistors of the first polarity type with a work function metal layer of the first polarity type, the security circuit would define a second different electrical function.. .
|Fin shape for fin field-effect transistors and method of forming|
A fin field-effect transistor (finfet) and a method of forming are provided. A gate electrode is formed over one or more fins.
|Electronic device including a schottky contact|
An electronic device can include a semiconductor layer having a primary surface, and a schottky contact comprising a metal-containing member in contact with a horizontally-oriented lightly doped region within the semiconductor layer and lying adjacent to the primary surface. In an embodiment, the metal-containing member lies within a recess in the semiconductor layer and contacts the horizontally-oriented lightly doped region along a sidewall of the recess.
|Engineered source/drain region for n-type mosfet|
Integrated circuit devices with field effect transistors have source and drain regions that include a first and a second layer. The first layer is formed below the plane of the channel region.
|Laterally diffused metal oxide semiconductor transistors for radio frequency power amplifiers|
Embodiments of laterally diffused metal oxide semiconductor (ldmos) transistors are provided. An ldmos transistor includes a substrate having a source region, channel region, and a drain region.
|Schottky and mosfet+schottky structures, devices, and methods|
Power devices which include trench schottky barrier diodes and also (preferably) trench-gate transistors. Isolation trenches flank both the gate regions and the diode mesas, and have an additional diffusion below the bottom of the isolation trenches.
|Semiconductor devices comprising floating gate transistors and methods of forming such semiconductor devices|
Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions.
|Self-aligned contacts for replacement metal gate transistors|
Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface of the gate, depositing an insulating layer above the semiconductor device, and planarizing the insulating layer using the blocking region as a planarization stop.
|High mobility, thin film transistors using semiconductor/insulator transition-metaldichalcogenide based interfaces|
Electronic devices and methods of forming an electronic device are disclosed herein. An electronic device may include a first 2d atomic crystal layer; a second 2d atomic crystal layer disposed atop the first 2d atomic crystal layer; and an interface comprising van-der-waals bonds between the first 2d atomic crystal layer and the second 2d atomic crystal layer.
|Silicon-germanium fins and silicon fins on a bulk substrate|
A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is formed over a second region of the first silicon-germanium alloy layer.
|Driver for normally on iii-nitride transistors to get normally-off functionality|
A semiconductor device includes a depletion mode gan fet and an integrated driver/cascode ic. The integrated driver/cascode ic includes an enhancement mode cascoded nmos transistor which is connected in series to a source node of the gan fet.
|Switching device of active display device and method of driving the switching device|
Example embodiments are directed to a switching device of an active display device and a method of driving the switching device, such that electrical reliability of the active display device is improved. The switching device of the active display device includes a plurality of thin film transistors (tfts) that are connected in series.
|Thin-film transistor active device and method for manufacturing same|
The present invention provides a thin-film transistor active device and a method for manufacturing the device. The thin-film transistor active device includes a substrate and a plurality of thin-film transistors formed on the substrate.
|Quantum dots, rods, wires, sheets, and ribbons, and uses thereof|
Described are znxcd1-xsyse1-y/znszse1-z core/shell nanocrystals, cdte/cds/zns core/shell/shell nanocrystals, optionally ally doped zn(s,se,te) nano- and quantum wires, and sns quantum sheets or ribbons, methods for making the same, and their use in biomedical and photonic applications, such as sensors for analytes in cells and preparation of field effect transistors.. .
|Monolithic three dimensional integration of semiconductor integrated circuits|
A three-dimensional integrated circuit comprising top tier nanowire transistors formed on a bottom tier of cmos transistors, with inter-tier vias, intra-tier vias, and metal layers to connect together the various cmos transistors and nanowire transistors. The top tier first begins as lightly doped regions on a first wafer, with an oxide layer formed over the regions.
|Engine ignition shutdown module|
An engine ignition shutdown module includes a voltage regulator circuit connected to a key switch, and a pair of isolated mosfet driver circuits connected to the voltage regulator circuit. Each mosfet driver circuit charges a capacitor while the key switch is in a run position and the interlock switches are closed, and each capacitor discharges through a resistor for a time delay period once the key switch is moved from the run position to an off position or at least one of the interlock switches are opened.
|Erase for 3d non-volatile memory with sequential selection of word lines|
An erase operation for a 3d stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a nand string to pre-charge a channel to a level which is sufficient to create gate-induced drain leakage at the select gate transistors.
|Semiconductor memory device|
A semiconductor memory device includes a string of memory cell transistors that are connected to each other in series. A selection transistor is connected between one end of the string of the memory cell transistors and one of a source line and a bit line.
|Memory architecture and cell design employing two access transistors|
Some embodiments include an improved memory array architecture and memory cell design. In one of such embodiments, a memory cell may comprise a memory element to store a logic state and two access transistors coupled to the memory element to access the logic state of the memory element.
|Pixel circuit, display device, and method of driving pixel circuit|
A pixel circuit, display device, and method of driving a pixel circuit enabling source-follower output with no deterioration of luminance even with a change of the current-voltage characteristic of the light emitting element along with elapse, enabling a source-follower circuit of n-channel transistors, and able to use an n-channel transistor as an el drive transistor while using current anode-cathode electrodes, wherein a source of a tft 111 as a drive transistor is connected to an anode of a light emitting element 114, a drain is connected to a power source potential vcc, a capacitor c111 is connected between a gate and source of the tft 111, and a source potential of the tft 111 is connected to a fixed potential through a tft 113 as a switching transistor.. .
|Pulse generator circuit|
A pulse generator circuit is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors that operate as a diode and resistor, respectively.
|Architecture for vbus pulsing in udsm processes|
Architecture for vbus pulsing in an ultra deep sub micron (udsm) process for ensuring usb-otg (on the go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from vbus in said charging circuit.
|Noise canceling current mirror circuit for improved psr|
A current mirror circuit provides a current to drive a load. A noise cancelling circuit is provided to keep the load current constant in spite of variations in the supply voltage.
|Low supply voltage bandgap reference circuit and method|
A circuit and method for a bandgap voltage reference operating at 1 volt or below is disclosed, wherein the operational amplifier (a1) drives resistors (r2, r3) only so that both the flicker noise contribution and the process sensitivity due to the conventional metal oxide semiconductor (mos) devices used as a current mirror within the proportional-to-absolute-temperature (ptat) loop are eliminated. Two symmetric resistive divider pairs formed by (r1a/r1b, r2a/r2b) are inserted to scale down both the base-emitter voltages (veb1, veb2) of bipolar transistors (q1, q2) and the ptat current (iptat) so that an output reference voltage (vref) becomes scalable.
|Semiconductor device, method of manufacturing thereof, signal transmission/reception method using such semiconductor device, and tester apparatus|
A semiconductor device includes a substrate, an internal circuit including a plurality of transistors provided over the substrate, an insulating film provided over the substrate, a bonding pad provided over the insulating film, an inductor being formed in the insulating film, the inductor carrying out a signal transmission/reception to/from an external device in a non-contact manner by an electromagnetic induction and being electrically coupled to the internal circuit. The inductor includes a first conducting layer, and the bonding pad includes a second conducting layer.
|Metal gate structure for semiconductor devices|
Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum..
|Tunnel junction field effect transistors having self-aligned source and gate electrodes and methods of forming the same|
Methods of forming a transistor include providing a semiconductor epitaxial structure including a channel layer and barrier layer on the channel layer, forming a gate electrode on the barrier layer, etching the semiconductor epitaxial structure using the gate electrode as an etch mask to form a trench in the semiconductor epitaxial structure, and depositing a source metal in the trench. The trench extends at least to the channel layer, and the source metal forms a schottky junction with the channel layer.
|Channel sige removal from pfet source/drain region for improved silicide formation in hkmg technologies without embedded sige|
When forming sophisticated p-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed.
|Transistor with embedded strain-inducing material formed in cavities formed in a silicon/germanium substrate|
When forming sophisticated semiconductor devices including n-channel transistors with strain-inducing embedded source and drain semiconductor regions, n-channel transistor performance may be enhanced by selectively growing embedded pure silicon source and drain regions in cavities exposing the silicon/germanium layer of a si/sige-substrate, wherein the silicon layer of the si/sige-substrate may exhibit a strong bi-axial tensile strain. The bi-axial tensile strain may improve both electron and hole mobility..
|Jfet devices with increased barrier height and methods of making same|
Devices for providing transistors with improved operating characteristics are provided. In one example, a system includes a processor and a memory device.
An object of one embodiment of the disclosed invention is to provide a semiconductor device having a novel structure in which stored data can be held even when power is not supplied and the number of times of writing is not limited. The semiconductor device is formed using an insulating layer formed over a supporting substrate and, over the insulating layer, a highly purified oxide semiconductor and single crystal silicon which is used as a sililcon on insulator (soi).
|Field effect transistor devices|
A memcapacitor device includes a pair of opposing conductive electrodes. A semiconductive material including mobile dopants within a dielectric and a mobile dopant barrier dielectric material are received between the pair of opposing conductive electrodes.
|Grown nanofin transistors|
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (spe) process is performed to crystallise the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth.
|Standard cells having transistors annotated for gate-length biasing|
Methods, layouts and chip design layouts that use annotations for communicating gate-length biasing amounts to post-layout tools are disclosed. One method includes receiving a chip design layout designed to includes select ones of a plurality of nominal cell layouts and an annotated cell layout.
|Method for manufacturing semiconductor device|
Electrical characteristics of transistors using an oxide semiconductor are greatly varied in a substrate, between substrates, and between lots, and the electrical characteristics are changed due to heat, bias, light, or the like in some cases. In view of the above, a semiconductor device using an oxide semiconductor with high reliability and small variation in electrical characteristics is manufactured.
|Solid-state imaging device, method of manufacturing same, and electronic apparatus|
A solid-state imaging device includes a plurality of photoelectric conversion units configured to receive light and generate signal charge, the plurality of photoelectric conversion units being provided in such a manner as to correspond to a plurality of pixels in a pixel area of a semiconductor substrate; and pixel transistors configured to output the signal charge generated by the photoelectric conversion units as electrical signals. Each of the pixel transistors includes at least a transfer transistor that transfers the signal charge generated in the photoelectric conversion unit to a floating diffusion corresponding to a drain.
|Sub-block disabling in 3d memory|
Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells.
|Memory system and memory access method|
Systems and methods of sequentially accessing memory cells in a nonvolatile memory device (nvm) are provided. The nvm has a plurality of strings and a common signal line coupled to the plurality of strings.
|Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors|
Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., nand-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines..
|Semiconductor memory device|
A semiconductor memory device comprises a memory string including first and second selection transistors, and first and second groups of memory cell transistors connected in series between the first and second selection transistors; a bit line and a source line respectively connected to the first and second selection transistors; first word lines respectively connected to gates of the memory cell transistors in the first group; second word lines respectively connected to gates of the memory cell transistors in the second group; first transfer transistors respectively connected to the first word lines; second transfer transistors respectively connected to the second word lines; and a control unit configured to apply a first control voltage to gates of the first transfer transistors and a second control voltage lower than the first control voltage to gates of the second transfer transistors when data is being written to memory cell transistors in the first group.. .
|Nonvolatile semiconductor memory device|
A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array having a plurality of memory cell transistors connected in series therein; a plurality of bit lines; and a control circuit for executing a read operation. The control circuit is configured capable of executing the read operation, the read operation charging the bit line and applying a read voltage to the control gate electrode of the memory cell transistor to determine whether the memory cell transistor is conductive and the bit line discharges or not.
|Semiconductor device and electronic device|
To provide a semiconductor device with such a new structure that the effect of variation in transistor characteristics can be reduced to achieve less variation in the output voltage of a memory cell. A memory cell includes a source follower (common drain) transistor for reading data held in a gate.
|Semiconductor memory device|
A memory cell array comprises first wiring lines, second wiring lines, and memory cells disposed at intersections thereof. A control circuit comprises a first power-supply line supplying a first voltage to selected ones of the first or second wiring lines, and first selection circuits connected between the first or second wiring lines and the first power-supply line, each first selection circuit comprising first and second transistors connected in series.
|Two-bit read-only memory cell|
A read-only memory (rom) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are connected to a first word line, and the gates of the second and fourth transistors are connected to a second word line.
A semiconductor device capable of maintaining data even after instantaneous power reduction or interruption. The semiconductor device includes first to sixth transistors.
A semiconductor device capable of maintaining data during instantaneous power reduction or interruption. The semiconductor device includes first to sixth transistors.
|Display device and electronic device|
Transistors each include a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer over the gate insulating layer, and a source electrode and a drain electrode over the oxide semiconductor layer. A driver circuit portion includes first to third wirings formed in the same step as the gate electrode, fourth to sixth wirings formed in the same step as the source electrode and the drain electrode, a seventh wiring formed in the same step as a pixel electrode, a first region where the second wiring intersects with the fifth wiring, and a second region where the third wiring intersects with the sixth wiring.
|Stereoscopic image display and method of manufacturing the same|
The present invention has been made in an effort to provide a stereoscopic image display comprising: a liquid crystal panel comprising a lower substrate and an upper substrate; rgb color filters positioned on a first surface of the upper substrate; thin film transistors positioned on a first surface of the lower substrate; a black matrix positioned on a second surface of the upper substrate; and a patterned retarder film for separating an image displayed on the liquid crystal panel, wherein at least one of the rgb color filters has a dummy part overlapping at least a portion of one or both of the other color filters.. .
A differential amplifier stage may include: a first transistor having a gate terminal; a second transistor having a gate terminal; and a voltage limiting circuit coupled to the gate terminals of the first and second transistors, wherein the voltage limiting circuit limits a gate voltage supplied to at least one of the gate terminals of the first and second transistors.. .
|High voltage switching circuits|
The preferred embodiments of the present invention use low voltage transistors to support high voltage switching circuits by connecting low voltage circuits in a stacking configuration. High voltage switching signals are divided into a plurality of small amplitude switching signals before sending into transformers, filters or other circuits.
|Vertical insulated-gate turn-off device having a planar gate|
An insulated gate turn-off (igto) device has a layered structure including a p+ layer (e.g., a substrate), an n-type layer, a p-type layer (which may be a p-well), n+ regions formed in the surface of the p-type layer, and insulated planar gates over the p-type layer between the n+ regions. The layered structure forms vertical npn and pnp transistors.
|Lateral insulated gate turn-off devices|
A lateral insulated gate turn-off (igto) device includes an n-type layer, a p-well formed in the n-type layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, at least one trenched gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, and an anode electrode electrically contacting the p+ type anode region. The structure forms a lateral structure of npn and pnp transistors, where the well forms the base of the npn transistor.
|Configurable time delays for equalizing pulse width modulation timing|
A plurality of pwm generators have user configurable time delay circuits for each pwm control signal generated therefrom. The time delay circuits are adjusted so that each of the pwm control signals arrive at their associated power transistors at the same time.
|Current mode logic latch|
A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor.
|Pre-charge circuit with reduced process dependence|
A pre-charging circuit, such as can be used to pre-charge a data bus, is presented that is largely process independent. A push-pull type of arrangement is used, where the output of the pre-charge circuit is initially connected to a supply level through one transistor, then connect to ground by another transistor.