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Transistors patents

      

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 Audio accessory circuitry and method compatible with both msft mode and digital communication mode patent thumbnailnew patent Audio accessory circuitry and method compatible with both msft mode and digital communication mode
An audio accessory key detection system (40) includes a host circuit (2-3) coupled to communicate via a microphone line (7) with an accessory circuit (3-3) in either a msft mode or a digital communication mode. Depletion mode transistors (44-1,2,3) in the accessory circuit are coupled between keys (15-1,2,3) of the accessory circuit, respectively.
Texas Instruments Incorporated


 Method for manufacturing a digital circuit and digital circuit patent thumbnailnew patent Method for manufacturing a digital circuit and digital circuit
A method for manufacturing a digital circuit is described including forming a plurality of field effect transistor pairs, connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal and setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition.. .
Infineon Technologies Ag


 Low noise amplifier patent thumbnailnew patent Low noise amplifier
A low noise amplifier includes: first and seventh transistors configured to respectively receive first and second input signals; second, third, and fifth transistors connected to the first transistor; eighth, ninth, and eleventh transistors connected to the seventh transistor; a third resistive element; fourth and tenth transistors respectively connected to the third and ninth transistors; sixth and twelfth transistors respectively connected to second and first output terminals; and first and second resistive elements.. .
Socionext Inc.


 System and  reconfigurable phase shifter and mixer patent thumbnailnew patent System and reconfigurable phase shifter and mixer
An analog circuit for generating a periodic signal at a selected phase, including one or more phase interpolators that receive orthogonal differential rf signals and a pair of differential gain signals. The differential in-phase rf signal is applied at respective gates of tail transistors, and a first differential gain signal is applied across gates of a transistor pair coupled to each of the tail transistors.
Texas Instruments Incorporated


 Adaptive dc-dc converter patent thumbnailnew patent Adaptive dc-dc converter
A voltage converter includes a high side transistor, a low side transistor coupled to the high side transistor at a switching node, and an inductor coupled to the switching node and providing an output node. A controller is provided that is coupled to the high side transistor and the low side transistor.
Texas Instruments Incorporated


 Charging circuit patent thumbnailnew patent Charging circuit
A charging circuit that charges a capacitor using the power that is output from a power supply, includes: first and second pnp-type transistors; first and second resistors; and a current path maintaining unit, wherein the power supply is connected to the emitter terminal of the first pnp-type transistor, the first resistor is connected between the emitter terminal and the base terminal of the first pnp-type transistor, the capacitor is connected to the collector terminal of the second pnp-type transistor, the second resistor is connected between the collector and base terminals of the second pnp-type transistor, the base terminal and the collector terminal of the first pnp-type transistor are respectively connected to the emitter terminal and the base terminal of the second pnp-type transistor, and the current path maintaining unit is provided between the collector terminal of the first pnp-type transistor and the emitter terminal of the second pnp-type transistor.. .
Aisin Seiki Kabushiki Kaisha


 Flexible organic transistors with controlled nanomorphology patent thumbnailnew patent Flexible organic transistors with controlled nanomorphology
An organic device, including semiconducting polymers processed from a solution cast on one or more dielectric layers on a substrate; and electrical contacts to the semiconducting polymers, wherein the substrate and the one or more dielectric layers are flexible and the semiconducting polymers are aligned. The one or more dielectric layers can increase mobility of the semiconducting polymers and/or alignment of the semiconducting polymers with one or more of the nanogrooves in the dielectric layers..
The Regents Of The University Of California


 Iii-n transistors with enhanced breakdown voltage patent thumbnailnew patent Iii-n transistors with enhanced breakdown voltage
Techniques related to iii-n transistors having enhanced breakdown voltage, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a hardmask having an opening over a substrate, a source, a drain, and a channel between the source and drain, and a portion of the source or the drain disposed over the opening of the hardmask..
Intel Corporation


 Support for long channel length nanowire transistors patent thumbnailnew patent Support for long channel length nanowire transistors
A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component.
International Business Machines Corporation


 Semiconductor device patent thumbnailnew patent Semiconductor device
A semiconductor device that is suitable for miniaturization is provided. The semiconductor device has a plurality of different transistors, active layers of the plurality of transistors are each an oxide semiconductor, and in the plurality of transistors, field-effect mobility of a transistor whose channel length is maximum and field-effect mobility of a transistor whose channel length is minimum are substantially constant.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Liquid crystal display device and electronic device

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Ultra high density thin film transistor substrate having low line resistance structure and manufacturing the same

A display device is described that has reduced resistance in one or more of the gate, common, data electrical lines that control the operation of the pixels of the display device. Reduced resistance is achieved by forming additional metal and/or metal-alloy layers on the gate, common, and/or data lines in such a manner so that the cross-sectional area of those lines is increased.
Lg Display Co., Ltd.

new patent

Semiconductor device and manufacturing semiconductor device

A semiconductor device having a high degree of freedom of layout has a first part ar1, in which a plurality of p-type wells pw and n-type wells nw are alternately arranged to be adjacent to each other along an x-axis direction. A common power feeding region (arp2) for the plurality of wells pw is arranged on one side so as to interpose the ar1 in a y-axis direction, and a common power feeding region (arn2) for the plurality of wells nw is arranged on the other side.
Renesas Electronics Corporation

new patent

Support for long channel length nanowire transistors

A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component.
International Business Machines Corporation

new patent

Apparatuses, methods, and systems for dense circuitry using tunnel field effect transistors

Embodiments include apparatuses, methods, and systems for a circuit to shift a voltage level. The circuit may include a first inverter that includes a first transistor coupled to pass a low voltage signal and a second inverter coupled to receive the low voltage signal.
Intel Corporation

new patent

Circuits for driving data lines

A circuit includes: a first data line; a second data line; a write driver including first and second transistors; a first switch connected in series with the first transistor to form a first series-connected pair; a second switch in series with the second transistor to form a second series-connected pair; and a level shifter which includes the first and second transistors. The first series-connected pair is coupled between a first voltage node and the first data line.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Static random access memory unit structure and static random access memory layout structure

A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect.
United Microelectronics Corp.

new patent

Display unit, display panel, and driving the same, and electronic apparatus

A display unit (1) includes a light-emitting device (13) and a pixel circuit (12) in each pixel (11), and a drive section (20) configured to drive the pixel circuit (12). The pixel circuit (12) includes a drive transistor (tr1) configured to drive the light-emitting device (13), and a write transistor (tr2) configured to control application of a signal voltage corresponding to an image signal to a gate of the drive transistor (tr1).
Joled Inc.

new patent

Goa circuit module, testing the same, display panel and display apparatus

The present disclosure provides a gate on array (goa) circuit module, comprising: a plurality of thin film transistors (tfts), each comprising a gate layer and a gate insulation layer laminated on a substrate, a plurality of vias each provided in the gate insulation layer to expose a portion of the gate layer, and a plurality of first transparent conductive portions each corresponding to one of the plurality of vias, each of the plurality of the first transparent conductive portions being provided at its corresponding via, electrically isolated from the gate layer, and constructed to be electrically connectable to the portion of the gate layer as exposed by its corresponding via by means of welding. The present disclosure also provides a method for testing the goa circuit module, a display panel comprising the goa circuit module and a display apparatus..
Hefei Boe Optoelectronics Technology Co., Ltd.

new patent

Sputtering target, manufacturing sputtering target, and forming thin film

There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured.
Semiconductor Energy Laboratory Co., Ltd.

Imaging device and electronic apparatus

Imaging devices and electronic apparatuses with one or more shared pixel structures are provided. The shared pixel structure includes a plurality of photoelectric conversion devices or photodiodes.
Sony Corporation

Crowbar current elimination

In one embodiment, an inverter generates an inverted clock signal using (i) first p-type and n-type transistors connected in cascode between supply and ground nodes and (ii) control circuitry receiving different phase-offset input clock signals that ensure that the cascode-connected transistors are never even partially on at the same time, thereby preventing crowbar current from occurring through the cascode-connected devices. In one implementation, the control circuitry has two p-type transistors and two n-type transistors configured to receive three phase-offset input clock signals to prevent crowbar current in the inverter.
Lattice Semiconductor Corporation

Programmable delay circuit including hybrid fin field effect transistors (finfets)

Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finfet) comprising a first gate corresponding to a first control fet, and a second gate corresponding to a first default fet, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins.
International Business Machines Corporation

Programmable delay circuit including hybrid fin field effect transistors (finfets)

Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finfet) comprising a first gate corresponding to a first control fet, and a second gate corresponding to a first default fet, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins.
International Business Machines Corporation

Level converter circuit

A level conversion circuit includes: first p-ch and n-ch transistors and second p-ch and n-ch transistors respectively connected in series between first and second power sources; third and fourth p-ch transistors respectively connected between the gates of the second and first p-ch transistors and the drain of the first and second p-ch transistors; and fifth and sixth p-ch transistors respectively connected between the gates of the second and first p-ch transistors and a third power source, wherein differential input signals are applied to the gates of the first and second n-ch transistors, a bias voltage is applied to the gates of the third and fourth p-ch transistors, the gate of the fifth and sixth p-ch transistors are respectively connected to connection nodes of the first p-ch and n-ch transistors the second p-ch and n-ch transistors.. .
Socionext Inc.

Start-up circuit for bandgap reference

A start-up circuit for a bandgap reference circuit include an operational amplifier and a diode coupled to a second input terminal of the operational amplifier. The circuit includes a first current branch including a first transistor and a second transistor in series, for generating a first current in response to an output voltage at an output terminal of the operational amplifier and a second current branch including a third transistor and a fourth transistor in series, for generating a second current in response to the output voltage.
Sk Hynix Memory Solutions Inc.

Dc-dc converter, and solar power controller and mobile body using same

A dc-dc converter includes a transformer, a switching circuit provided on the primary side of the transformer, and a rectifier circuit provided on the secondary side of the transformer. The rectifier circuit includes a first rectifier part that is serially connected body of a first transistor and a second transistor having a first electrode connected to a second electrode of the first transistor.
Sharp Kabushiki Kaisha

Floating evaporative assembly of aligned carbon nanotubes

High density films of semiconducting single-walled carbon nanotubes having a high degree of nanotube alignment are provided. Also provided are methods of making the films and field effect transistors (fets) that incorporate the films as conducting channel materials.
Wisconsin Alumni Research Foundation

Large area contacts for small transistors

A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint.
Stmicroelectronics, Inc.

Increased contact area for finfets

A method for forming fin field effect transistors includes epitaxially growing source and drain (s/d) regions on fins, the s/d regions including a diamond-shaped cross section and forming a dielectric liner over the s/d regions. A dielectric fill is etched over the s/d regions to expose a top portion of the diamond-shaped cross section.
Global Foundries U.s. 2 Llc.

Structure to enable titanium contact liner on pfet source/drain regions

A semiconductor structure is provided that includes non-metal semiconductor alloy containing contact structures for field effect transistors (fets), particularly p-type fets. Notably, each non-metal semiconductor alloy containing contact structure includes a highly doped epitaxial semiconductor material directly contacting a topmost surface of a source/drain region of the fet, a titanium liner located on the highly doped epitaxial semiconductor material, a diffusion barrier liner located on the titanium liner, and a contact metal portion located on the diffusion barrier liner..
International Business Machines Corporation

Sion gradient concept

Embodiments of the present disclosure generally relate to methods and devices for use of low temperature polysilicon (ltps) thin film transistors in liquid crystal display (lcd) and organic light-emitting diode (oled) displays.. .
Applied Materials, Inc.

Vertical-type semiconductor devices and methods of manufacturing the same

In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated..
Samsung Electronics Co., Ltd.

Systems and methods for integrating different channel materials into a cmos circuit by using a semiconductor structure having multiple transistor layers

A method includes providing a first substrate having first and second regions, fabricating over the first region of the first substrate a channel of a first transistor, providing a second substrate over the second region of the first substrate, fabricating over the second substrate a channel of a second transistor, and forming gates respectively and simultaneously over the channels of the first and second transistors.. .
Taiwan Semiconductor Manufacturing Company Limited

Low power semiconductor transistor structure and fabrication thereof

A structure and method of fabrication thereof relate to a deeply depleted channel (ddc) design, allowing cmos based devices to have a reduced σvt compared to conventional bulk cmos and can allow the threshold voltage vt of fets having dopants in the channel region to be set much more precisely. The ddc design also can have a strong body effect compared to conventional bulk cmos transistors, which can allow for significant dynamic control of power consumption in ddc transistors.
Mie Fujitsu Semiconductor Limited

Integrated device having multiple transistors

An integrated device includes a semiconductor well formed in an epitaxial layer, and a guard ring formed in the epitaxial layer and surrounding the semiconductor well. The semiconductor well and the guard ring include a type of semiconductor different from that of the epitaxial layer.
O2micro, Inc.

Self-aligned barrier and capping layers for interconnects

An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, cr, or v containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper.
President And Fellows Of Harvard College

Vertical channel transistors fabrication process by selective subtraction of a regular grid

A grid comprising a first set of grid lines and a second set of grid lines is formed on a substrate using a first lithography process. At least one of the first set of grid lines and the second set of grid lines are selectively patterned to define a vertical device feature using a second lithography process..
Intel Corporation

Dual non-volatile memory cell comprising an erase transistor

The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.. .
Stmicroelectronics (rousset) Sas

Nonvolatile memory device

A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device.

Address decoding circuitry

Various implementations described herein are directed to an integrated circuit for address decoding. The integrated circuit may include an input circuit configured to provide an encoded address via multiple address lines.
Arm Limited

In-cell type display device

A display device includes: a first substrate including a touch region for sensing a touch and a peripheral area surrounding the touch region; a second substrate facing the first substrate; thin film transistors positioned on the first substrate; pixel electrodes connected to the thin film transistors; common electrodes arranged to transmit a common voltage; sensing wires connected to the common electrodes and arranged to transmit a detection signal for sensing a touch; and a transparent electrode layer positioned on a first surface of the second substrate, the transparent electrode layer having a portion overlapping the peripheral area, and having at least one opening positioned over the touch region.. .
Samsung Display Co., Ltd.

Self-capacitance in-cell touch screen and manufacturing the same, liquid crystal display

A self-capacitance in-cell touch screen including a glass array substrate, thin film transistors disposed on the substrate, and pixel electrodes electrically connected with the thin film transistors, a planarizing layer between the pixel electrodes and the thin film transistors. The transparent touch control sensing electrode, a first insulation layer, a second insulation layer, and a metal connection line are disposed on the planarizing layer in sequence.
Wuhan China Star Optoelectronics Technology Co., Ltd.

Array substrate and manufacturing method thereof

An array substrate and a manufacturing method thereof are provided. The method has steps of: forming a black matrix layer having a plurality of black matrixes on a substrate; forming a switch array layer having a plurality of thin-film transistors on the black matrix layer; forming a color resist layer having a plurality of color resists on the switch array layer; and forming a transparent conductive layer on the color resist layer..
Shenzhen China Star Optoelectronics Technology Co. Ltd.

Ion sensor based on differential measurement, and production method

Ion sensor based on differential measurement comprising an isftet-refet pair wherein the refet is defined by a structure composed of an isfet covered by a microreservoir where an internal reference solution is contained. The sensor comprises a first and a second ion-selective field effect transistor, an electrode, a substrate on the surface whereof are integrated the two transistors, connection tracks and the electrode and a structure adhered on the first ion-selective field effect transistor which creates a microreservoir on the gate of said first transistor, with the microreservoir having a microchannel which connects the microreservoir with the exterior and the microreservoir being filled with the reference solution..
Consejo Superior De Investigaciones CientÍficas (csic)

Method for globally resetting the pixels in a matrix image sensor

Matrix image sensors with active pixels comprise a photodiode and transistors in each pixel, with at least one transistor for commanding the reset of a charge storage zone (photodiode or floating diffusion). To avoid reset potential value errors in large matrices, when a global reset is desired for all the matrix, the falling edge of the reset command signal is shifted in time before progressively staggered signals are applied to the reset command lines.
Pyxalis

Logic circuit, semiconductor device, electronic component, and electronic device

The drive capability of a logic circuit is improved. The logic circuit includes a first output node, a dynamic logic circuit, a diode-connected first transistor, and a capacitor.
Semiconductor Energy Laboratory Co., Ltd.

Logic circuit, processing unit, electronic component, and electronic device

A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors.
Semiconductor Energy Laboratory Co., Ltd.

High voltage input stage using low voltage transistors

A structure for high voltage input stage for deep submicron is provided that does not include native devices. This structure is able to maintain high speed functionality without jeopardizing device reliability or dc (direct current) power consumption.
Broadcom Corporation

Ultra-low voltage temperature threshold detector

An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A threshold detector selectively applies either a first voltage or second voltage to the doped well region based on whether the temperature of the semiconductor substrate is above or below a threshold temperature..
Stmicroelectronics International N.v.

Amplifier arrangement

An amplifier arrangement is presented, comprising a first differential stage (ds1) comprising at least two transistors (m1, m1′) having a first threshold voltage (vth1), at least a second differential stage (ds2) comprising at least two transistors (m3, m3′) having a second threshold voltage different from the first threshold voltage, at least one of the transistors of the first and second differential stage (ds1, ds2), respectively, has a control input commonly coupled to an input of the amplifier arrangement, at least one transistor (m1) of the first differential stage and one transistor (m3) of the second differential stage are arranged in a common current path, which is coupled to an output of the amplifier arrangement.. .
Ams Ag

System and a voltage controlled oscillator

In accordance with an embodiment, a voltage controlled oscillator (vco) includes a vco core having a plurality of transistors and a varactor circuit that has a first end coupled to emitter terminals of the vco core and a second end coupled to a tuning terminal. The varactor circuit includes a capacitance that increases with increasing voltage applied to the tuning terminal with respect to the emitter terminals of the vco core..
Infineon Technologies Ag

Diketopyrrolopyrrole polymers for use in organic semiconductor devices

The present invention relates to polymers comprising one or more (repeating) unit(s) of the formula (i) which are characterized in that ar1 and ar1′ are independently of each other are an annulated (aromatic) heterocyclic ring system, containing at least one thiophene ring, which may be optionally substituted by one, or more groups, and their use as organic semiconductor in organic devices, especially in organic photovoltaics (solar cells) and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties.
Basf Se

Transistors and methods for making them

A semiconductor composition which comprises a soluble polyacene semiconductor and a polymeric semiconducting binder the binder having a permittivity greater than 3.4 at 000 hz. The charge mobility of the semiconducting binder when measured in a pure state is greater than 10−7 cm2/vs and more preferably greater than 10−6 cm2/vs.
Neudrive Limited

Bipolar transistor having collector with doping spike

This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base.
Skyworks Solutions, Inc.

Organic light-emitting diode display

An organic light-emitting diode (oled) display is disclosed. In one aspect, the display includes a substrate including a display area configured to display an image and the display area includes first and second regions.
Samsung Display Co., Ltd.

Thin-film transistor substrate and display device comprising the same

A thin-film transistor substrate and a display device comprising the same are provided which can improve display quality by reducing or preventing deterioration of the characteristics of thin-film transistors. The thin-film transistor substrate comprises thin-film transistors on a lower protective metal layer.
Lg Display Co., Ltd.

Logic elements comprising carbon nanotube field effect transistor (cntfet) devices and methods of making same

Inverter circuits and nand circuits comprising nanotube based fets and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type.
Nantero, Inc.

Image sensor device with first and second source followers and related methods

An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode.
Stmicroelectronics (crolles 2) Sas

Image sensor device with first and second source followers and related methods

An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode.
Stmicroelectronics (crolles 2) Sas

Solid-state image pickup device, image pickup system using solid-state image pickup device, and manufacturing solid-state image pickup device

In a solid-state image pickup device including a pixel that includes a photoelectric conversion portion, a carrier holding portion, and a plurality of transistors, the solid-state image pickup device further includes a first insulating film disposed over the photoelectric conversion portion, the carrier holding portion, and the plurality of transistors, a conductor disposed in an opening of the first insulating film and positioned to be connected to a source or a drain of one or more of the plurality of transistors, and a light shielding film disposed in an opening or a recess of the first insulating film and positioned above the carrier holding portion.. .
Canon Kabushiki Kaisha

Semiconductor device and manufacturing method thereof

An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided.
Semiconductor Energy Laboratory Co., Ltd.

Modular interconnects for gate-all-around transistors

A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical gaa fets. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods.
Stmicroelectronics, Inc.

Semiconductor device including dummy metal

A semiconductor device may include a plurality of dummy wirings formed on a substrate at different vertical levels and electrically floated and a plurality of dummy contact plugs each electrically connected between two adjacent dummy wirings of the plurality of dummy wiring of the plurality of dummy wirings. No dummy wiring of the plurality of dummy wirings is electrically connected to a terminal of any one of a plurality of transistors included in the substrate..
Samsung Electronics Co., Ltd.

Stacked short and long channel finfets

An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk.
Stmicroelectronics, Inc.

Finfet devices and methods of forming

In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin.
Taiwan Semiconductor Manufacturing Company, Ltd.

Mosfet devices with asymmetric structural configurations introducing different electrical characteristics

First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a well region within the substrate having the first-type dopant, a first body region within the well region having a second-type dopant and a first source region within the first body region and laterally offset from the well region by a first channel.
Stmicroelectronics, Inc.



Transistors topics:
  • Transistors
  • Semiconductor
  • Semiconductor Device
  • Integrated Circuit
  • High Speed
  • Photodiode
  • Memory Effect
  • Silicon Nitride
  • Enhancement
  • Ion Implant
  • Ion Channel
  • Interrupted
  • Reference Voltage
  • Semiconductor Devices
  • Semiconductor Substrate


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