|| List of recent Transistors-related patents
| Integrated circuit devices including finfets and methods of forming the same|
Integrated circuit devices including fin field effect transistors (finfets) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin.
Samsung Electronics Co., Ltd.
| Fabrication methods facilitating integration of different device architectures|
Circuit fabrication methods are provided which include, for example: providing one or more gate structures disposed over a substrate structure, the substrate structure including a first region and a second region; forming a plurality of u-shaped cavities extending into the substrate structure in the first region and the second region thereof, where at least one first cavity of the plurality of u-shaped cavities is disposed adjacent in one gate structure in the first region; and expanding the at least one first cavity further into the substrate structure to at least partially undercut the one gate structure, without expanding at least one second cavity of the plurality of u-shaped cavities, where forming the plurality of u-shaped cavities facilitates fabricating the circuit structure. In one embodiment, the circuit structure includes first and second transistors, having different device architectures, the first transistor having a higher mobility characteristic than the second transistor..
| Methods of forming gated devices|
Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction.
Micron Technology, Inc.
| Electronic eyeglasses and manufacture thereto|
A system and methods for recognizing certain eye or eyelid gestures such as by opening or closing of eyelid or movement of the pupil as signals to trigger certain predesigned desired events. An embodiment comprises of electronic glasses placed in front of the eye to recognize certain eye or eyelid gestures as signals to control an electronic device such as a chair for the special needs, or tvs or car system or some video games.
| Memory circuitry using write assist voltage boost|
Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12.
| Method and system for improving the radiation tolerance of floating gate memories|
A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors.
United States Of America As Represented By The Secretary Of The Navy
| Non-volatile semiconductor device|
A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop that includes an erase operation and a verifying operation. The control circuit increases an erasing voltage in accordance with the number of times the erasing loop is repeated..
Kabushiki Kaisha Toshiba
| Power conversion circuit and controlling direct current-alternating current circuit|
A power conversion circuit includes: an ac-dc circuit, a direct current-alternating current dc-ac circuit, and a first filter capacitor. The dc-ac circuit includes: a third bridge arm, a fourth bridge arm, a first inductor, a second inductor, a first switch transistor, and a second switch transistor, a second end of the first inductor is connected to a first end of the first switch transistor, a second end of the first switch transistor is connected to the direct current bus, a first end of the second inductor is connected to a connection point of two switch transistors included by the fourth bridge arm, a second end of the second inductor is connected to a first end of the second switch transistor, and a second end of the second switch transistor is connected to the direct current bus..
Huawei Technologies Co., Ltd.
| Forward converter with self-driven bjt synchronous rectifier|
An ac-to-dc converter circuit includes dc-to-dc converter that in turn includes a secondary side circuit. The secondary side circuit includes a secondary winding, a pair of bipolar transistor-based self-driven synchronous rectifiers, a pair of current splitting inductors, and an output capacitor.
| Liquid crystal display and panel therefor|
A thin film transistor array panel is provided, which includes: gate lines formed on an insulating substrate; data lines insulated from the gate lines and intersecting the gate lines; first pixel electrodes disposed on pixel areas defined by intersections of the gate lines and the data lines; first thin film transistors, each having three terminals connected to one of the gate lines, one of the data lines, and one of the first pixel electrodes; second pixel electrodes disposed on the pixel areas and capacitively coupled to the first pixel electrodes; and second thin film transistors, each having three terminals connected to a previous gate line, a storage electrode line or one of the data lines, and one of the second pixel electrodes.. .
Pixel unit, pixel array structure and display device
The present invention discloses a pixel unit, a pixel array structure and a display device, to solve the problem that horizontal stripes may occur between adjacent rows in a conventional pseudo dual-domain pixel display. The pixel unit of the present invention comprises a first pixel unit and a second pixel unit arranged adjacent to each other and have a shape of a parallelogram.
Shanghai Avic Optoelectronics Co., Ltd.
Liquid crystal display device
A liquid crystal display device includes: pixel electrodes arranged in respective sub-pixels arrayed in a matrix, plural image signal lines extending in a column direction of the matrix, and supplied with image signals, pixel transistors which are switches arranged in the respective sub-pixels, and supply the image signals to the pixel electrodes, and scanning signal lines extending in a row direction of the matrix, and control conduction of the pixel transistors. The pixel electrodes aligned in a direction along which the image signal lines extend are connected to either of two adjacent image signal lines with six sub-pixels as one period.
Japan Display Inc.
High dynamic range image sensor read out architecture
A method of controlling a pixel array includes reading out image data from pixel cells of a row i of the of the pixel array with second transfer control signals that are coupled to be received by transfer transistors included in the pixels cells of the row of the of the pixel array that is being read out. Exposure times for pixel cells are independently controlled in other rows of the pixel array that are not being read out with first transfer control signals coupled to be received by transfer transistors included in the pixel cells in the other rows of the of the pixel array that are not being read out while the image data is read out from the pixel cells of row i of the pixel array..
Omnivision Technologies, Inc.
Semiconductor device and display device utilizing the same
A source-drain voltage of one of two transistors connected in series becomes quite small in a set operation (write signal), thus the set operation is performed to the other transistor. In an output operation, two transistors operate as a multi-gate transistor, therefore, a current value can be small in the output operation.
Semiconductor Energy Laboratory Co., Ltd.
Oscillator buffer and calibrating the same
A buffering circuit for buffering an oscillator signal. The buffering circuit includes a plurality of pmos and nmos transistor pairs connected in parallel, each pair having connected gate terminals and connected drain terminals forming an inverter circuit, each pair arranged for receiving via a direct coupling an oscillator signal at its gate terminal, and each pair further being connected with an additional pmos and nmos transistor.
Stichting Imec Nederland
A high-precision oscillator includes a voltage reference module which includes multiple measured field effect transistors and arranged for detecting process corners for the measured field effect transistors to generate a reference voltage containing process corner information of the measured field effect transistors, a compensation current generating module which is arranged for receiving the reference voltage, making a temperature compensation for the reference voltage, and generating a compensation current which includes both the process compensation and temperature compensation, and a ring oscillator which is arranged for receiving the compensation current and outputting a clock with stable frequency. The high-precision oscillator designs the process compensation and the temperature compensation separately, which are adjustable due to one of them will not be influenced by the other; and frequency of its outputted clock is not influenced by process and temperature, thereby precision of the outputted clock is improved..
Ipgoal Microelectronics (sichuan) Co., Ltd.
Input clamping structure for sound quality improvement in car-radio class-ab power amplifier design
A clamping circuit for a class ab amplifier includes a reference voltage circuit, four npn darlington transistors having inputs coupled to the reference voltage circuit, and outputs for providing four clamped voltages and a split npn darlington transistor having an input coupled to the reference voltage circuit, and four separate outputs for providing four ac ground voltages.. .
Stmicroelectronics (shenzhen) R&d Co. Ltd
Rail-to-rail line driver using differential cascode bootstraping
Aspects of rail-to-rail line drivers using differential cascode bootstrapping are described. In one embodiment, a differential line driver includes first and second differential driver output legs.
Current source array
A silicon on insulator current source array includes input control for receiving a control voltage, a first reference input for receiving a first reference voltage, and a second reference input for receiving a second reference voltage. A chain of several silicon on insulator mos transistors, of the same type, have control electrodes all connected to the input control, first conduction electrodes are all connected to the first reference input, and second conduction electrodes are respectively connected to the second reference input through several load circuits respectively configured to be traversed by several currents when the several transistors are on upon application of the control voltage on the input control.
University Of Twente
A mixer includes a first node to which an intermediate frequency (if) signal is input; first and second transistors that respectively have control terminals supplied with local signals having mutually opposite phases and output terminals connected to the first node; a first filter that is connected between the output terminal of the second transistor and the first node and suppresses passage of the if signal; a second node to which the if signal is input; third and fourth transistors that respectively have control terminals supplied with local signals having mutually opposite phases and output terminals connected to the second node; a second filter that is connected between the output terminal of the fourth transistor and the second node and suppresses passage of the if signal; and a combiner combining a signal output from the first node and a signal output from the second node.. .
Sumitomo Electric Device Innovations, Inc.
Cmos logarithmic current generator and generating a logarithmic current
A cmos logarithmic current generator includes current mode circuitry having a design principle based on a taylor's series expansion that approximates an exponential function. A mosfet circuit provides a function generator core cell having a biasing current ib.
King Fahd University Of Petroleum And Minerals
Self-adjustable current source control circuit for linear regulators
A self-adjustable current source control circuit utilizes a replica output stage, a sink current source that generates a reference current, and a negative feedback circuit to generate a sink current between a linear regulator output terminal and ground only when a load circuit connected to the linear regulator is in a low power consuming state. The replica output stage includes an 1:n scaled replica of the linear regulator's nmos (or npn) output stage transistor, and the negative feedback circuit utilizes two pmos (or pnp) negative feedback transistors having the same n:1 size ratio and connected as a common gate amplifier, whereby one of the two negative feedback transistors turns on to draw the desired sink current from the regulator output terminal only when the load current falls below n times the reference current (i.e., only the load current is drawn through the output stage transistor during high load current conditions)..
Tower Semiconductor Ltd.
Current limit control with constant accuracy
The present document relates to a current sensing and/or control circuit with reduced sensing errors. A current control circuit for controlling a load current into an electronic device is described.
Dialog Semiconductor Gmbh
Floating body contact circuit improving esd performance and switching speed
Embodiments of systems, methods, and apparatus for improving esd performance and switching time for semiconductor devices including metal-oxide-semiconductor (mos) field effect transistors (fets), and particularly to mosfets fabricated on semiconductor-on-insulator (“sot”) and silicon-on-sapphire (“sos”) substrates.. .
Peregrine Semiconductor Corporation
Insulation wall between transistors on soi
An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.. .
Stmicroelectronics (crolles 2) Sas
Cnt-based sensors: devices, processes and uses thereof
Disclosed herein are methods of preparing and using doped mwnt electrodes, sensors and field-effect transistors. Devices incorporating doped mwnt electrodes, sensors and field-effect transistors are also disclosed..
Heterojunction bipolar transistors with an airgap between the extrinsic base and collector
Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base.
International Business Machines Corporation
Gallium nitride devices
Semiconductor structures comprising a iii-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance.
International Rectifier Corporation
Current aperture vertical electron transistors with ammonia molecular beam epitaxy grown p-type gallium nitride as a current blocking layer
A current aperture vertical electron transistor (cavet) with ammonia (nh3) based molecular beam epitaxy (mbe) grown p-type gallium nitride (p-gan) as a current blocking layer (cbl). Specifically, the cavet features an active buried magnesium (mg) doped gan layer for current blocking purposes.
The Regents Of The University Of California
Tft substrate and repairing the same
A thin film transistor (tft) substrate includes; a substrate; a plurality of scan lines, disposed on the substrate; a plurality of data lines, disposed across the scan lines; a scan line insulting layer disposed between the scan lines and the data lines; a plurality of thin film transistors, each of thin film transistors disposed on an intersection of each scan line and each data, line; a data line insulting layer, disposed on a top surface of the scan line insulting layer and used to cover the data lines; and a common electrode, disposed on the data line insulting a layer, and comprising a plurality of positioning through holes, wherein the positioning through holes expose the data line insulting layer, and are located right above the data lines.. .
Chunghwa Picture Tubes, Ltd.
Method for fabricating fin field effect transistors
A method of fabricating a fin field effect transistor (finfet) includes providing a substrate having a first fin and a second fin extending above a substrate top surface, wherein the first fin has a top surface and sidewalls and the second fin has a top surface and sidewalls. The method includes forming an insulation layer between the first and second fins.
Techniques for ion implantation of non-planar field effect transistors
A method of forming a fin field effect transistor (finfet) device includes forming a fin structure on a substrate, the substrate comprising a semiconductor material and forming a replacement gate cavity comprising an exposed portion of the fin structure and a sidewall portion adjacent the exposed portion, wherein the exposed portion of the fin structure defines a channel region. The method further includes performing at least one implant into the exposed portion of the fin structure..
Non-volatile memory device employing semiconductor nanoparticles
Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer.
Dithienobenzofuran polymers and small molecules for electronic application
The present invention relates to polymers comprising a repeating unit of the formula (i), and compounds of formula (viii), or (ix), wherein y, y15, y16 and y17 are independently of each other a group of formula (i), and their use as organic semiconductor in organic electronic devices, especially in organic photovoltaics and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers and compounds according to the invention can have excellent solubility in organic solvents and excellent film-forming properties.
Diketopyrrolopyrrole polymers and small molecules
The present invention relates to polymers, comprising a repeating unit of the formula (i), and compounds of formula (ii), wherein y, y15, y16 and y17 are independently of each other a group of formula (a) characterized in that the polymers and compounds comprise silicon-containing solubilizing side chains and their use as organic semiconductor in organic devices, especially in organic photovoltaics and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers and compounds according to the invention can have excellent solubility in organic solvents and excellent film-forming properties.
Photo detector consisting of tunneling field-effect transistors and the manufacturing method thereof
The present invention belongs to the technical field of optical interconnection and relates to a photo detector, in particular to a photo detector consisting of tunneling field-effect transistors.. .
Shift register unit, driving method, gate driving circuit and display device
There is provided a shift register unit and driving method thereof, a gate driving circuit and display device. By setting the voltage stabilizing capacitor (c) connected to the pull-up node (p), the shift register unit utilizes the voltage stabilizing capacitor (c2) to stabilize the potential at the pull-up node (p), so as to make the signal output from the shift register unit more stable; and at the same time, uses a very small quantity of transistors and capacitors to compose the shift register unit, so that the wiring area of the gate driving circuit is greatly reduced to provide a technical support for the design of a liquid crystal display device with a narrower frame.
Semiconductor memory device
A semiconductor memory device includes a string of memory cell transistors that are connected to each other in series. A selection transistor is connected between one end of the string of the memory cell transistors and one of a source line and a bit line.
A voltage controller is provided that is connected to a voltage inducing circuit which is connected to a static random-access memory (sram) cell. The voltage controller comprises a voltage clamping circuit and a pull up circuit.
Electrical power converter
This description relates to an electrical power converter including a series connection of two transistors, and provides a technology for suppressing increase in electrical current flowing through the transistors when the two transistors are turned on at the same time for some defective reason. An electrical power converter disclosed herein includes a series connection of a first transistor and a second transistor.
Reversible matrix converter circuit
A reversible matrix converter circuit is provided with n levels per phase including n conversion arms exhibiting on one side n ends for generating or receiving respectively n intermediate dc voltage levels, and exhibiting on another side n ends linked at a common point of ac signal input or output. The circuit includes: —two external arms linked respectively to the highest level of positive voltage and to the lowest level of negative voltage, these two external arms each having a single igbt transistor or two power transistors, linked by their emitter, —two igbt power transistors, linked in series by their emitter on each of the n-1 internal arms, —filtering capacitors disposed respectively between the n intermediate voltage levels..
Organic light emitting display and driving method thereof
An organic light emitting display includes a plurality of pixels and a compensation unit. Each of the pixels includes a driving transistor to control an amount of current supplied to a corresponding organic light emitting diode.
Analog data transmitter applied in lcd apparatus and operating method thereof
An analog data transmitter applied in a lcd apparatus includes an output pad, a channel operational amplifier, an initial switch, an auxiliary switch module, and a detection unit. The detection unit selectively starts a first switch unit or a second switch unit of the auxiliary switch module according to a pulse width modulation corresponding to a data conversion amplitude of an output data signal outputted from the output pad.
Three-mode high-speed level up shifter circuit
Embodiments of the present invention disclose a level up shifter circuit. The level up shifter circuit further includes two field effect transistors connected in series and a control circuit.
Wide range core supply compatible level shifter circuit
A level shifter circuit is implemented with dual gate fully depleted silicon-on-insulator (fdsoi) technology. By enhancing the performance of the nmos and devices within the level shifting circuit, the vt of the dual gate fdsoi nmos transistors is lowered without a need for additional control circuitry.
Compensated temperature variable resistor
A front-end circuit for measurement devices, for example oscilloscopes or digitizers, may implement dc gain compensation using a programmable variable resistance. A mos transistor may be configured and operated as a linear resistor with the ability to self-calibrate quickly, while compensating for temperature variations.
Bipolar transistor frequency doublers at millimeter-wave frequencies
Frequency multipliers include a pair of transistors each connected to a common impedance through a respective collector impedance formed from a transmission line. Each transmission line has a length between about one quarter and about one eighth of a wavelength of an input signal frequency and is tuned to produce a large impedance at a collector of the respective transistor at the input signal frequency.
Multi-gate high voltage device
A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and insulating structure between the gate and the drain as well as method for using the same is provided in this disclosure. The high breakdown voltage transistors in the device together are in an elliptical shape.
Output switching circuit
An output switching circuit includes a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output s terminal at a connection node between the first and second transistors; a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and a drive pulse generating unit that generates first drive pulses for driving the first transistor and second drive pulses for driving the second transistor in accordance with the comparison signal.. .
Semiconductor device including gate structure for threshold voltage modulation in transistors and fabricating the same
A method for fabricating a semiconductor device includes forming an nmos region and a pmos region in a substrate, forming a first stack layer including a first gate dielectric layer and a first work function layer that is disposed over the first gate dielectric layer and contains aluminum, over the pmos region of the substrate, forming a second stack layer including a second gate dielectric layer, a threshold voltage modulation layer that is disposed over the second gate dielectric layer and contains lanthanum, and a second work function layer that is disposed over the threshold voltage modulation layer, over the nmos region of the substrate, and annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer and a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer, respectively.. .
Dual gate fd-soi transistor
Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (fd-soi) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate fd-soi transistors with enhanced switching performance.
In one embodiment, a semiconductor device includes a semiconductor substrate, and first and second transistors of first and second conductivity types on the substrate. The first transistor includes a first gate electrode on the substrate, a first source region of the second conductivity type and a first drain region of the first conductivity type disposed to sandwich the first gate electrode, and a first channel region of the first or second conductivity type disposed between the first source region and the first drain region.
Tuck strategy in transistor manufacturing flow
When forming field effect transistors with a semiconductor alloy layer, e.g., sige, embedded in the source/drain regions, a strategy called tucking has been developed in order to improve formation of the semiconductor alloy layer. An improved tucking strategy is hereby proposed, wherein the interface between the isolation region and the active region is not straight, but it rather defines an indentation, so that the active region protrudes into the isolation region in correspondence to the indentation.
Display device and terminal device
To provide a plural-viewpoint display device having an image separating optical element such as a lenticular lens or a parallax barrier, which is capable of arranging thin film transistors and wirings while achieving substantially trapezoid apertures and high numerical aperture, and to provide a driving method thereof, a terminal device, and a display panel. A neighboring pixel pair arranged with a gate line interposed therebetween is connected to the gate line placed between the pixels, each of the pixels configuring the neighboring pixel pair is connected to the data line different from each other, and each of the neighboring pixel pairs neighboring to each other in an extending direction of the gate lines is connected to the gate line different from each other..
Organic light emitting display panel and organic light emitting display device including the same
Discussed is an organic light emitting display panel. The organic light emitting display panel includes a plurality of unit pixels which each include first to third sub-pixels having different colors.
Inducing localized strain in vertical nanowire transistors
A device includes a semiconductor substrate and a vertical nano-wire over the semiconductor substrate. The vertical nano-wire includes a bottom source/drain region, a channel region over the bottom source/drain region, and a top source/drain region over the channel region.
Electromagnetic type retarder
An electromagnetic type retarder includes a stator having spaced, circularly arranged magnetic coils forming multi-phase connections and a steel rotor surrounding the stator and rotated according to the rotation of a tire; a control device; and a driving device including at least two transistors opened and closed by a drive pulse from the control device, respectively. The multi phase connections are formed by the magnetic coils, the magnetic coils of each phase are connected with capacitors to form a resonance circuit, respectively, and each of the transistors is connected in series to at least two phase connections.
Methods of forming gate structures with multiple work functions and the resulting products
One illustrative method disclosed herein includes removing sacrificial gate structures for nmos and pmos transistors to thereby define nmos and pmos gate cavities, forming a high-k gate insulation layer in the nmos and pmos gate cavities, forming a lanthanide-based material layer on the high-k gate insulation layer in the nmos and pmos gate cavities, performing a heating process to drive material from the lanthanide-based material layer into the high-k gate insulation layer so as to thereby form a lanthanide-containing high-k gate insulation layer in each of the nmos and pmos gate cavities, and forming gate electrode structures above the lanthanide-containing high-k gate insulation layer in the nmos and pmos gate cavities.. .
Organic light emitting diode display and manufacturing the same
An organic light emitting diode (oled) display and a method for manufacturing the same are described. An exemplary embodiment provides an oled display including: a substrate including a plurality of pixel areas; a light emitting unit including an organic light emitting diode and a plurality of first thin film transistors, the light emitting unit being formed in each of the plurality of pixel areas; and a sensor unit including a photosensor and a plurality of second thin film transistors, the sensor unit being formed in at least some of the plurality of pixel areas.
Samsung Display Co., Ltd.
Nanostructured organic materials and a process for the preparation thereof
The invention disclosed nanostructured organic materials and a process for the preparation thereof. Further the present invention herein provides nanostructured organic material comprising divalent zinc metal complex of n,n′-di-(phenyl-3,5 dicarboxylic acid)-perylene-3,4,9,10-tetracarboxylic acid diimide doped with hydrazine hydrate, which exhibits increased charge carrier mobility at low operating voltage at atmospheric condition useful in organic field effect transistors (ofets)..
Council Of Scientific And Induistrial Research
Semiconductor memory device
A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor..
Kabushiki Kaisha Toshiba
Semiconductor storage apparatus
A semiconductor memory device, including a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells coupled to the plurality of word lines and the plurality of pairs of bit lines, a plurality of sense amplifiers each coupled between a corresponding pair of bit lines, a plurality of first driver transistors coupled between the plurality of sense amplifiers and a first power supply line, a plurality of second driver transistors coupled between the plurality of sense amplifiers and a second power supply line, a pair of common data lines, and a plurality of column selection gates each coupled between the corresponding pair of bit lines and the pair of common data lines, wherein the number of the first driver transistors is more than the number of the second driver transistor.. .
Renesas Electronics Corporation
Solid-state imaging device, driving the same, and electronic apparatus
A solid-state imaging device includes a pixel array unit in which a plurality of imaging pixels configured to generate an image, and a plurality of phase difference detection pixels configured to perform phase difference detection are arranged, each of the plurality of phase difference detection pixels including a plurality of photoelectric conversion units, a plurality of floating diffusions configured to convert charges stored in the plurality of photoelectric conversion units into voltage, and a plurality of amplification transistors configured to amplify the converted voltage in the plurality of floating diffusions.. .
Image pickup apparatus having photoelectric conversion function
An image pickup apparatus that makes it possible to achieve both high picture quality and a wide dynamic range is provided. Each pixel unit included in the image pickup apparatus includes: four photodiodes; four transfer transistors; a charge storage portion (four floating diffusions) for storing electric charges generated at the photodiodes; an amplification transistor; a select transistor; and a reset transistor.
Renesas Electronics Corporation
Organic light emitting display device and driving the same
A pixel includes a driving transistor, an organic light emitting diode, a first transistor, and the second transistor. The driving transistor includes a gate electrode coupled to a first node, a first electrode coupled to a second node, and a drain electrode coupled to a third node.
Samsung Display Co., Ltd.
Display with hybrid progressive-simultaneous drive pattern
A display may have an array of organic light-emitting diode display pixels. Each display pixel may have a light-emitting diode that emits light under control of a drive transistor.
An integrated circuit is provided. A standard cell includes a plurality of pmos transistors and a plurality of nmos transistors.
Voltage regulating circuit
In various embodiments, a circuit is provided including a supply terminal, a logic circuit, an inverter and a control transistor which may include a body region, first and second source/drain regions, a gate insulating region having a layer thickness and a gate region. The first source/drain region may be coupled to the supply terminal.
Infineon Technologies Ag
Low voltage and high driving charge pump
The present disclosure relates to a charge pump circuit having one or more voltage multiplier circuits that enable generation of an output signal having a higher output voltage. In one embodiment, the charge pump circuit comprises a nmos transistor having a drain connected to a supply voltage and a source connected to a chain of diode connected nmos transistors coupled in series.
Taiwan Semiconductor Manufacturing Co., Ltd.
Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor.
Semiconductor Energy Laboratory Co., Ltd.
Programmable logic circuit architecture using resistive memory elements
A programmable logic circuit architecture using resistive memory elements. The proposed circuit architecture uses the conventional island-based field programmable gate array (fpga) architecture, but with novel integration of cmos-compatible resistive memory elements that can be programmed efficiently.
The Regents Of The University Of California
Bandgap circuit with temperature correction
A temperature corrected voltage bandgap circuit is provided. The circuit includes first and second diode connected transistors.
Dolpan Audio, Llc
Charge and discharge signal circuit and dc-dc converter
A charge and discharge signal circuit includes: high side transistors connected in series; low side transistors connected in series; high side drive circuits; low side drive circuits; and a drive signal generation circuit, wherein each drive circuit includes: a level shifter; a capacitor switch string connected in series, being connected in parallel with the transistor; and a drive part, to which an output of the level shifter is supplied, at least one pair of neighboring ones of the level shifters are commonly formed, and two neighboring ones of the drive parts receive a same output from the common shifters.. .
Bipolar junction transistors with self-aligned terminals
Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor.
International Business Machines Corporation
Method and gate structure for threshold voltage modulation in transistors
A method of fabricating a semiconductor device. A substrate (pmos/nmos regions) is prepared.
Sk Hynix Inc.
Light-emitting device and manufacturing the same
An object is to improve reliability of a light-emitting device. A light-emitting device has a driver circuit portion including a transistor for a driver circuit and a pixel portion including a transistor for a pixel over one substrate.
Semiconductor Energy Laboratory Co., Ltd.
Integrated circuit devices including strained channel regions and methods of forming the same
Integrated circuit devices including strained channel regions and methods of forming the same are provided. The integrated circuit devices may include enhancement-mode field effect transistors.
Samsung Electronics Co., Ltd.
Semiconductor device and structure
A device, including: a first layer including first transistors and a second layer including second transistors, where at least one of the first transistors is self-aligned to one of the second transistors, where the second transistors are horizontally oriented transistors, and where the second layer includes a plurality of resistive-random-access memory (rram) cells, the memory cells including the second transistors.. .
Monolithic 3d Inc.
Arrays of memory cells and methods of forming an array of vertically stacked tiers of memory cells
An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers.
Micron Technology, Inc.