|| List of recent Transistors-related patents
| Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation|
Processes for making field effect transistors relax a buried stressor layer to induce strain in a silicon surface layer above the buried stressor layer. The buried stressor layer is relaxed and the surface layer is strained by implantation into at least the buried stressor layer, preferably on both sides of a portion of the surface layer that is to be stressed.
| Semiconductor device and manufacturing method thereof|
An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current.
| Thin film transistors formed by organic semiconductors using a hybrid patterning regime|
The present disclosure describes a process strategy for forming bottom gate/bottom contact organic tfts in cmos technology by using a hybrid deposition/patterning regime. To this end, gate electrodes, gate dielectric materials and drain and source electrodes are formed on the basis of lithography processes, while the organic semiconductor materials are provided as the last layers by using a spatially selective printing process..
| Method and apparatus for program and erase of select gate transistors|
Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells.
| String selection structure of three-dimensional semiconductor device|
A three-dimensional semiconductor device includes first and second selection lines stacked one on the other. An upper line horizontally crosses over the first and second selection lines.
| Selecting memory cells|
A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section.
| Frequency multiplier|
An apparatus is provided. A differential pair of transistors is configured to receive a first differential signal having a first frequency, and a transformer, having a primary side and a secondary side is provided.
| Hybrid amplifier|
Exemplary embodiments are directed to systems, devices, and methods for enhancing a telescopic amplifier. An amplifier may include a differential pair of input transistors including at least one transistor configured to receive a first input and at least one other transistor configured to receive a second input.
| Amplifier with switchable common gate gain buffer|
An amplifier having a switchable common gate gain buffer is disclosed. In an exemplary embodiment, an apparatus includes a plurality of selectable gain channels that provide constant input impedance at a common input to receive an input signal and generate an output signal having at least one of selected gain and current characteristics.
| Switching device with resistive divider|
Embodiments provide a switching device including one or more field-effect transistors (fets). In embodiments, a resistive divider comprising a first resistor and a second resistor may be coupled with the fet at a position electrically between a gate terminal of the fet and a body terminal of the fet..
| Semiconductor device|
An object of one embodiment of the present invention to provide a latch circuit includes a level shifter and a buffer in which transistors each including a channel region formed in an oxide semiconductor film are connected in series. Thus, data can be held in the latch circuit even when power is not supplied..
| Transmission system|
A signal transmission system (10) includes a signal generator circuit (12); a signal regenerator circuit (14) coupled to the signal generator circuit by conductive lines (16, 18). The signal regenerator circuit receives input signals from the signal generator circuit on the conductive lines, and the regenerator circuit includes cascoded transistors (39, 41) and level-shifting circuits (26) coupled to the cascoded transistors.
| Current driver for led diodes|
A current driver for a string of leds includes a first series connection of a first transistor and a first resistance and a second series connection of a second transistor and a second resistance. The first and second series connections are coupled in parallel between the string of leds and a voltage reference.
| Enforcement of semiconductor structure regularity for localized transistors and interconnect|
A global placement grating (gpg) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the gpg is positioned to intersect each contact that interfaces with the chip level.
| Defect reduction for formation of epitaxial layer in source and drain regions|
The embodiments of mechanisms for forming source/drain (s/d) regions of field effect transistors (fets) described enable forming an epitaxially grown silicon-containing layer with reduced number of particles on surface of recesses. The described mechanisms also reduce the effect of the residual particles on the epitaxial growth.
| Power mosfets and methods for forming the same|
Power metal-oxide-semiconductor field-effect transistors (mosfets) and methods of forming the same are provided. A power mosfet may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape.
| Metal-programmable integrated circuits|
A metal-programmable integrated circuit may include an array of metal-programmable cells. Each cell may include multi-gate transistor structures in which multiple surfaces of a gate structure serve to control current flow through at least one channel structure.
| Bidirectional semiconductor device for protection against electrostatic discharges|
An integrated circuit is produced on a bulk semiconductor substrate in a given cmos technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate thyristors coupled in parallel and head-to-tail.
| Memories and methods of forming thin-film transistors using hydrogen plasma doping|
Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped polycrystalline silicon.
|Method and layout of an integrated circuit|
An integrated circuit layout includes a p-type active region, an n-type active region, a first metal connection, a second metal connection and a plurality of trunks. The plurality of trunks is formed substantially side-by-side, and in parallel with each other.
|Current generation architecture for an implantable stimulator device having coarse and fine current control|
Disclosed herein are current output architectures for implantable stimulator devices. Current source and sink circuitry is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking an amount of current to or from any one of the electrodes of the device.
|Long-term implantable silicon carbide neural interface device using the electrical field effect|
Field effect devices, such as capacitors and field effect transistors, are used to interact with neurons. Cubic silicon carbide is biocompatible with the neuronal environment and has the chemical and physical resilience required to withstand the body environment and does not produce toxic byproducts.
|Collections of laterally crystallized semiconductor islands for use in thin film transistors|
Collections of laterally crystallized semiconductor islands for use in thin film transistors and systems and methods for making same are described. A display device includes a plurality of thin film transistors (tfts) on a substrate, such that the tfts are spaced apart from each other and each include a channel region that has a crystalline microstructure and a direction along which a channel current flows.
|Organic light emitting display and manufacturing method thereof|
An organic light emitting display resulting in an improved aperture ratio and a manufacturing method thereof. The organic light emitting display that includes a plurality of pixels arranged between first and second substrates, each of said pixels includes a plurality of thin film transistors, an organic light emitting diode, and a capacitor.
|Semiconductor memory device|
According to one embodiment, a semiconductor memory device includes first hookup transistors connected to word lines, a first dummy hookup transistor connected to first dummy word line, and a second dummy hookup transistor connected to second dummy word line. A group of hookup transistors formed by the first hookup transistors, the first dummy hookup transistor, and the second dummy hookup transistor is aligned on either of one row and rows.
|Multi-port magnetic random access memory (mram)|
A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line.
|Dc/dc converter with iii-nitride switches|
A synchronous switch is interposed between the output and ground. The control switch and the synchronous switch comprise depletion-mode iii-nitride transistors.
|Image pickup apparatus, image pickup system and driving method of image pickup apparatus|
An image pickup apparatus of an embodiment includes pixel units each including a photoelectric conversion unit and an amplification transistor that outputs a signal based on an electric carrier generated by the photoelectric conversion unit, a first output line to which signals from first and other pixel units are output, and a second output line to which signals from second and other pixel units are output. A connection unit is arranged to control an electric connection between input nodes of the amplification transistors of the first and second pixel units is arranged.
|Backlight unit and display device having the same|
A backlight unit includes a power converter configured to generate a light source driving voltage in response to a voltage control signal, a plurality of light emitting diode strings, where each of the light emitting diode strings receives the light source driving voltage through a first terminal thereof, a plurality of transistors corresponding to the light emitting diode strings, where each of the transistors includes: a first electrode connected to a second terminal of a corresponding light emitting diode string thereof; a second electrode; and a control electrode, and a controller connected to the control electrode and the second electrode, where the controller outputs a plurality of current control signals to control electrodes of the transistors and generate the voltage control signal, where the controller generates an over-current detection signal when any one of the current control signals has a pulse width greater than a predetermined reference width.. .
A display apparatus has an image display unit having a plurality of arrayed pixel circuits, and an image signal compensation circuit compensating an image signal and outputs the compensated signal to the image display unit. Each of the pixel circuits has a compensating capacitor which compensates the threshold voltage of the driving transistor.
|Pixel, display device comprising the pixel and driving method of the display device|
A display device includes a data driver; a scan driver; a compensation control signal unit configured to reset voltages of data signals transmitted to a plurality of pixels during a previous frame at a current frame, and configured to generate and transmit a first control signal to compensate for threshold voltages of driving transistors of the pixels and a second control signal to control simultaneous light emission of the pixels; a power controller configured to control and supply the voltage levels of a first and second power source voltages; a display unit including the plurality of pixels coupled to corresponding data lines, scan lines, first control lines, second control lines, first voltage lines, and second voltage lines; and a timing controller configured to generate a plurality of data signals by processing external image signals and generate a plurality of driving control signals for controlling driving of the drivers.. .
|Monitoring system for detecting degradation of integrated circuit|
A monitoring system for detecting stress degradation of a semiconductor integrated circuit has an amplifier circuit and degradation test transistors. Multiplexers are provided that have an output coupled to a respective electrode of the degradation test transistor.
A power-supply apparatus according to an aspect includes an inductor, a transistor that supplies, in an on-state, a current to the input side of the inductor, a second transistor that becomes, when the first transistor is in an off-state, an on-state and thereby brings the input side of the inductor to a predetermined potential, a signal generation unit that generates voltage signals corresponding to a current flowing to the inductor, an amplifier that outputs a current according to the voltage signals, a converter that converts the current output from the amplifier into a voltage signal, and a control unit that controls the transistors based on a first feedback signal corresponding to the voltage on the output side of the inductor and the voltage signal, which is used as a second feedback signal.. .
|Transistors, semiconductor constructions, and methods of forming semiconductor constructions|
Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion.
|Stacked power semiconductor device using dual lead frame|
A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame.
|Semiconductor memory device|
A semiconductor memory device has a memory cell array having memory cells, each including first and second conduction type transistors, a peripheral circuit having the first and second conduction type transistors, a first conduction type memory cell array well region within the memory cell array region, a second conduction type memory cell array well region within the first conduction type memory cell array well region, a first conduction type peripheral circuit well region within the peripheral circuit region, a second conduction type peripheral circuit well region within the first conduction type peripheral circuit well region, and a second conduction type isolation region between the first conduction type memory cell array well region and the first conduction type peripheral circuit well region. At least a portion of first conduction type transistors of first conduction type transistors of the peripheral circuit is formed in the second conduction type isolation region..
|Semiconductor memory device|
A semiconductor memory device has a memory cell array with memory cells, each including first and second conduction type transistors, column-side peripheral circuits disposed with the same row-direction interval as the memory cells, a first conduction type well region formed within the memory cell array, a second conduction type well region formed within the first conduction type well region and is disposed separately in the row direction, a second conduction type well contact region disposed extending in the row direction among the memory cells, a first conduction type well contact region disposed extending in the column direction among the memory cells, a column-side peripheral contact region, a first conduction type back gate voltage line connecting to the first conduction type well region; and a second conduction type back gate voltage line connecting to the second conduction type well.. .
|Method of forming finfet of variable channel width|
Embodiments of present invention provide a method of forming a first and a second group of fins on a substrate; covering a top first portion of the first and second groups of fins with a first dielectric material; covering a bottom second portion of the first and second groups of fins with a second dielectric material, the bottom second portion of the first group and the second group of fins having a same height; exposing a middle third portion of the first and second groups of fins to an oxidizing environment to create an oxide section that separates the top first portion from the bottom second portion of the first and second groups of fins; and forming one or more fin-type field-effect-transistors (finfets) using the top first portion of the first and second groups of fins as fins under gates of the one or more finfets.. .
|Mos transistors and fabrication method thereof|
A method is provided for fabricating an mos transistor. The method includes providing a semiconductor substrate, and forming a gate structure having a gate dielectric layer and a gate metal layer on the semiconductor substrate.
|Cmos transistors, fin field-effect transistors and fabrication methods thereof|
A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and configuring a channel region along a first direction.
|Semiconductor devices including back-side integrated circuitry|
Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors.
|Transistor and fabrication method|
Transistors and fabrication methods are provided. A first sidewall can be formed on each sidewall of a gate structure.
|Methods and systems for point of use removal of sacrificial material|
A method of manufacturing a sensor, the method including forming an array of chemically-sensitive field effect transistors (chemfets), depositing a dielectric layer over the chemfets in the array, depositing a protective layer over the dielectric layer, etching the dielectric layer and the protective layer to form cavities corresponding to sensing surfaces of the chemfets, and removing the protective layer. The method further includes, etching the dielectric layer and the protective layer together to form cavities corresponding to sensing surfaces of the chemfets.
|Method of manufacturing a non-volatile memory|
The disclosure relates to a method of manufacturing vertical gate transistors in a semiconductor substrate, comprising implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors; forming, in the substrate, parallel trench isolations and second trenches perpendicular to the trench isolations, reaching the isolation layer, and isolated from the substrate by a first dielectric layer; depositing a first conductive layer on the surface of the substrate and in the second trenches; etching the first conductive layer to form the vertical gates of the transistors, and vertical gate connection pads between the extremity of the vertical gates and an edge of the substrate, while keeping a continuity zone in the first conductive layer between each connection pad and a vertical gate; and implanting doped regions on each side of the second trenches, to form drain regions of the transistors.. .
|Spad sensor circuit with biasing circuit|
A deep spad structure uses the substrate as the anode terminal of its multiplication p-n junction. A bias voltage for the spad (in excess of the spad's breakdown voltage) is coupled to the spad's cathode terminal.
|Methods for forming bipolar transistors|
Methods are provided for forming a device that includes merged vertical and lateral transistors with collector regions of a first conductivity type between upper and lower base regions of opposite conductivity type that are ohmically coupled via intermediate regions of the same conductivity type and to the base contact. The emitter is provided in the upper base region and the collector contact is provided in outlying sinker regions extending to the thin collector regions and an underlying buried layer.
|Display device and method for manufacturing the same|
An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor.
|Enhanced optical gain and lasing in indirect gap semiconductor thin films and nanostructures|
Structures and methodologies to obtain lasing in indirect gap semiconductors such as ge and si are provided and involves excitonic transitions in the active layer comprising of at least one indirect gap layer. Excitonic density is increased at a given injection current level by increasing their binding energy by the use of quantum wells, wires, and dots with and without strain.
|Hybrid power devices and switching circuits for high power load sourcing applications|
A hybrid switching circuit includes first and second switching devices containing first and second unequal bandgap semiconductor materials. These switching devices, which support parallel conduction in response to first and second control signals, are three or more terminal switching devices of different type.
|High power density off-line power supply|
A power supply is provided, the power supply including a filter stage configured to receive an ac input voltage, a bridge circuit configured to rectify the filtered ac input voltage, an ac/dc converter, and a dc/dc converter. The ac/dc converter includes a primary transistor and an auxiliary circuit including an auxiliary transistor and configured to convert the rectified ac input voltage to a first dc output voltage, wherein the primary transistor and the auxiliary transistor are at least one of gallium nitride (gan) transistors or silicon carbide (sic) transistors.
To provide a plural-viewpoint display device having an image separating optical element such as a lenticular lens or a parallax barrier, which is capable of arranging thin film transistors and wirings while achieving substantially trapezoid apertures and high numerical aperture, and to provide a driving method thereof, a terminal device, and a display panel. A neighboring pixel pair arranged with a gate line interposed therebetween is connected to the gate line placed between the pixels, each of the pixels configuring the neighboring pixel pair is connected to the data line different from each other, and each of the neighboring pixel pairs neighboring to each other in an extending direction of the gate lines is connected to the gate line different from each other..
|Liquid crystal display|
A liquid crystal display (lcd) includes thin film transistors (tfts) respectively coupled to different gate lines and to a pixel electrode and a direction control electrode, and to which different gate-off voltages are respectively applied. Alternatively, a reduced gate voltage is applied to the pixel electrode tft according to a coupling capacitance.
|Liquid crystal display|
A liquid crystal display includes: a first insulation substrate; a plurality of color filters positioned on the first insulation substrate; a plurality of gate lines and a plurality of data lines positioned on the plurality of color filters; a plurality of thin film transistors positioned on the plurality of color filters and connected to the plurality of gate lines and the plurality of data lines; a plurality of pixel electrodes connected to the plurality of thin film transistors; a second insulation substrate facing the first insulation substrate; a liquid crystal layer positioned between the first insulation substrate and the second insulation substrate; and a backlight unit positioned behind the second insulation substrate, wherein the thin film transistors are not formed on the second insulation substrate and anti-glare elements are provided in front of at least one of the data lines and gate lines for respectively reducing or preventing the reflection of ambient light to a user from the data lines or the gate lines respectively.. .
|Thin film transistor substrate and liquid crystal display including the thin film transistor substrate|
A thin film transistor substrate a display area that includes pixels connected to gate lines and data lines crossing the gate lines, a non-display area disposed adjacent to the display area, data pads disposed in the non-display area and each being connected to a first end of a corresponding data line of the data lines, first transistors disposed in the non-display area and each being connected to a second end of the corresponding data line of the data lines, os pads connected to the second end of the data lines, and repair lines disposed in the non-display area along a vicinity of the display area and arranged while interposing the first transistors therebetween. The os pads are overlapped with the first transistors and the repair lines..
|Method for driving liquid crystal panel, method for testing flicker and liquid crystal display apparatus|
A method for driving a liquid crystal panel, a method for testing flicker and a liquid crystal display apparatus are disclosed. They relate to the technical field of liquid crystal display.
|Display device with binary mode amoled pixel pattern|
An amoled display panel comprising a plurality of color elements in each pixel with each of the color elements comprising a discrete plurality of illuminating units associated with a plurality of transistors operating in a binary mode. The plurality of illuminating units have different sizes in accordance with 2n size, where n is the illuminating unit's number.
|Amplifier dynamic bias adjustment for envelope tracking|
An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor..
|Cascode bias of power mos transistors|
There is disclosed a driver circuit for a power amplifier of class d type having a segmented architecture with at least one current branch which can be powered down in a low power mode of operation of the circuit. The branch comprising a switch with a cascode mos transistor, the circuit further comprises a bias circuitry adapted for dynamically generating a dynamic bias control signal so as to cause the cascode mos transistor of the switch to be ‘off’ in the low power mode..
|Hybrid digital/analog power amplifier|
The invention may be embodied in radio frequency power amplifier (rf-pa) predriver circuits employing a hybrid analog/digital rf architecture including a resynchronizing digital-to-analog convertor to drive an efficient high-power output stage suitable for driving standard high power amplifier (hpa) output devices. The hybrid analog/digital rf architecture retains the advantages of high digital content integration found in conventional class-s architecture, while relaxing the performance requirements on the output transistors and on the bitstream generator.
|Switch architecture at low supply voltages|
A sampled cmos switch includes first and second nmos devices in series between input and output nodes. The first and second nmos devices are activated by a sample signal.
|Driver circuit for driving power transistors|
A driver circuit for driving a power transistor includes a converter having a first transistor and a second transistor coupled in series between a supply node and a reference node. The converter is configured to receive a first signal and in response thereto generate a second signal for selectively controlling status of the power transistor.
|Multi-gate high voltage device|
A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and insulating structure between the gate and the drain as well as method for using the same is provided in this disclosure. The high breakdown voltage transistors in the device together are in an elliptical shape.
|Nanoscale wires, nanoscale wire fet devices, and nanotube-electronic hybrid devices for sensing and other applications|
The present invention generally relates to nanotechnology, including field effect transistors and other devices used as sensors (for example, for electrophysiological studies), nanotube structures, and applications. Certain aspects of the present invention are generally directed to transistors such as field effect transistors, and other similar devices.
|High yield complementary metal-oxide semiconductor x-ray detector|
A digital x-ray detector includes a scintillator that is configured to absorb radiation emitted from an x-ray radiation source and to emit light photons in response to the absorbed radiation. The detector also includes a complementary metal-oxide-semiconductor (cmos) light imager that is configured to absorb the light photons emitted by the scintillator.
|X-ray detector having improved noise performance|
Exemplary embodiments are directed to imagining detectors and methods of fabricating the imagining detectors for use in medical imagining systems. In exemplary embodiments, a detector for an imaging device include a continuous unpatterned photoelectric material that forms a portion of a photosensor and an electrode disposed with respect to the photoelectric material to form an anode or cathode of the photosensor.
|High performance isolated vertical bipolar junction transistor and method for forming in a cmos integrated circuit|
A cmos integrated circuit containing an isolated n-channel demos transistor and an isolated vertical pnp transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel demos transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well.
|Geometric regularity in fin-based multi-gate transistors of a standard cell library|
A method of optimizing a layout of an integrated circuit formed using fin-based cells of a standard cell library is provided. The method includes arranging cell rows of different track heights having standard cells.
|Transistors with wrapped-around gates and methods for forming the same|
A device includes a substrate, a semiconductor strip over the substrate, a gate dielectric wrapping around the semiconductor strip, and a gate electrode wrapping around the gate dielectric. A dielectric region is overlapped by the semiconductor strip.
|Low cost transistors|
An integrated circuit containing an analog mos transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions.
|Field effect transistor|
Field effect transistors are provided. An active region protrudes from a substrate and a gate electrode is provided on the active region.
A power device possesses a built-in fuse function and can continue to normally operate after a short circuit failure. The power device includes a plurality of output cells, a plurality of bonding wires provided corresponding to the output cells, and a control terminal driving circuit.