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This page is updated frequently with new Transistors-related patent applications. Subscribe to the Transistors RSS feed to automatically get the update: related Transistors RSS feeds. RSS updates for this page: Transistors RSS RSS


Electrostatic discharge device gate biasing for a transmitter

Amlogic

Electrostatic discharge device gate biasing for a transmitter

Predictive and reactive control of secondary side synchronous rectifiers in forward converters

Linear Technology

Predictive and reactive control of secondary side synchronous rectifiers in forward converters

Predictive and reactive control of secondary side synchronous rectifiers in forward converters

Comsys Ab

Switch protection i auxiliary resonant circuit


Date/App# patent app List of recent Transistors-related patents
07/23/15
20150208480 
 Light-emitting device, electronic equipment, and  producing light-emitting device patent thumbnailLight-emitting device, electronic equipment, and producing light-emitting device
A light-emitting apparatus includes a first light-emitting device, a second light-emitting device, and a device driving portion having drive transistors. The first light-emitting device includes a first electrode, first light-emitting unit, second electrode, second light-emitting unit, and third electrode.
Idemitsu Kosan Co., Ltd.


07/23/15
20150207526 
 Electrostatic discharge device gate biasing for a transmitter patent thumbnailElectrostatic discharge device gate biasing for a transmitter
A transmitter, comprises: a first branch for providing a positive output having a first set of serially-connected transistors; a second branch for providing a negative output having a second set of serially-connected transistors; and a biasing circuit, wherein the biasing circuit generates a first biasing voltage and a second biasing voltage as a function of the positive output, the negative output, and a predefined threshold voltage, and wherein the first biasing voltage, the second biasing voltage, and a differential input signal drive the first set of serially-connected transistors and the second set of serially-connected transistors.. .
Amlogic Co., Ltd.


07/23/15
20150207423 
 Predictive and reactive control of secondary side synchronous rectifiers in forward converters patent thumbnailPredictive and reactive control of secondary side synchronous rectifiers in forward converters
A forward converter has a primary side containing a pwm controller for controlling switching of a power switch and has a secondary side coupled to the primary side via a transformer. The secondary side includes a forward transistor and a catch transistor.
Linear Technology Corporation


07/23/15
20150207408 
 Switch protection i auxiliary resonant circuit patent thumbnailSwitch protection i auxiliary resonant circuit
A resonant power converter comprising electrical safety components comprising a combination of a diodes and a zener diodes coupled between dc conductors and an auxiliary switching circuit, the diodes being adapted to hinder the current from flowing from the auxiliary switching circuit to the negative dc conductor, and the zener diodes being adapted to allow current to flow from the negative dc conductor to the auxiliary switching circuit when the potential difference between the negative dc conductor and the phase conductor is above a threshold voltage. The zener diodes being selected such that the threshold voltage of the zener diodes is below the maximum blocking voltage of the transistors..
Comsys Ab


07/23/15
20150207033 
 Nanopyramid sized opto-electronic structure and  manufacturing of same patent thumbnailNanopyramid sized opto-electronic structure and manufacturing of same
Aspects of the invention provide methods and devices. In one embodiment, the invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, leds and transistors.
Glo Ab


07/23/15
20150207015 
 Apparatus and  optically initiating collapse of a reverse biased p-type-n-type junction patent thumbnailApparatus and optically initiating collapse of a reverse biased p-type-n-type junction
An optical method of collapsing the electric field of an innovatively fabricated, reverse-biased pn junction causes a semiconductor switch to transition from a current blocking mode to a current conduction mode in a planar electron avalanche. This switch structure and the method of optically initiating the switch closure is applicable to conventional semiconductor switch configurations that employ a reverse-biased pn junction, including, but not limited to, thyristors, bipolar transistors, and insulated gate bipolar transistors..
Applied Physical Electronics, L.c.


07/23/15
20150206965 
 High performance finfet patent thumbnailHigh performance finfet
A finfet is described having first, second, and third pluralities of fins with gate structures and source and drain regions formed on the fins so that pmos transistors are formed on the first plurality of fins, nmos transistors are formed on the second plurality and pmos transistors are formed on the third plurality. In one embodiment, the first and second pluralities of fins are made of strained silicon; and the third plurality of fins is made of a material such as germanium or silicon germanium that has a higher hole mobility than strained silicon.
Altera Corporation


07/23/15
20150206957 
 Low-temperature fabrication of nanomaterial-derived metal composite thin films patent thumbnailLow-temperature fabrication of nanomaterial-derived metal composite thin films
Disclosed are new methods of fabricating nanomaterial-derived metal composite thin films via solution processes at low temperatures (<400° c.). The present thin films are useful as thin film semiconductors, thin film dielectrics, or thin film conductors, and can be implemented into semiconductor devices such as thin film transistors and thin film photovoltaic devices..
Polyera Corporation


07/23/15
20150206949 
 Transistors and fabrication methods thereof patent thumbnailTransistors and fabrication methods thereof
A method is provided for fabricating transistors. The method includes providing a substrate; and forming at least one dummy gate structure having a dummy gate dielectric layer and a dummy gate electrode layer on the substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/23/15
20150206947 
 Normally-off junction field-effect transistors and application to complementary circuits patent thumbnailNormally-off junction field-effect transistors and application to complementary circuits
A junction field-effect transistor (jfet) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such jfet devices.. .
International Business Machines Corporation


07/23/15
20150206933 

Light emitting apparatus and electronic device


There is provided a light emitting apparatus provided with a pixel circuit which is provided with a plurality of transistors including a first transistor and a light emitting element in which a current is supplied by the first transistor, in which, in at least one of the plurality of transistors, a wiring is connected to a gate electrode at a position overlapping a channel region in plan view.. .
Seiko Epson Corporation


07/23/15
20150206931 

Organic light-emitting diode display with bottom shields


A display may have an array of organic light-emitting diode display pixels. Each display pixel may have a light-emitting diode that emits light under control of a drive transistor.
Apple Inc.


07/23/15
20150206930 

Light-emitting device wtih oxide thin film transistors and manufacturing method thereof


The present disclosure disclosed a light-emitting device with thin film transistors, comprising: a substrate and a substrate insulating layer formed thereon; a gate electrode, a source electrode, and a drain electrode. The gate electrode is arranged on the substrate insulating layer, and a gate insulating layer is formed between the gate electrode and the electrodes of the source and the drain.
Shenzhen China Star Optoelectronics Technology Co., Ltd.


07/23/15
20150206929 

Light-emitting element display device


A light-emitting element display device includes a substrate, one or a plurality of thin film transistors, a light-emitting element, a first electrode, and a second electrode. The substrate includes an insulating material.
Japan Display Inc.


07/23/15
20150206906 

Memories and methods of forming thin-film transistors using hydrogen plasma doping


Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped polycrystalline silicon.
Micron Technology, Inc.


07/23/15
20150206890 

Cell layout for sram finfet transistors


An sram array and method of making is disclosed. Each sram cell comprises two pull-up (pu), two pass-gate (pg), and two pull-down (pd) finfets.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206888 

Static random access memory and fabrication methods thereof


A method for fabricating a static random access memory is provided. The method includes providing a semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/23/15
20150206885 

Dummy gate structure for electrical isolation of a fin dram


Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy.
International Business Machines Corporation


07/23/15
20150206884 

Dynamic random access memory cell with self-aligned strap


After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures.
International Business Machines Corporation


07/23/15
20150206878 

Implementing buried fet below and beside finfet on bulk substrate


A method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with added device drive strength with buried field effect transistors (fets) below and beside a traditional finfet on a bulk substrate, and a design structure on which the subject circuit resides are provided. Buried field effect transistors (fets) are formed on either side and under the traditional finfet.
International Business Machines Corporation


07/23/15
20150206876 

Fin field effect transistors having heteroepitaxial channels


Disposable gate structures are formed over semiconductor material portions, and source and drain regions can be formed in the semiconductor material portions. After formation of a planarization dielectric layer, one type of disposable gate structure can be removed selective to at least another type of disposable gate structure employing a patterned hard dielectric mask layer.
International Business Machines Corporation


07/23/15
20150206762 

Methods and systems for point of use removal of sacrificial material


A method of manufacturing a sensor, the method including forming an array of chemically-sensitive field effect transistors (chemfets), depositing a dielectric layer over the chemfets in the array, depositing a protective layer over the dielectric layer, etching the dielectric layer and the protective layer to form cavities corresponding to sensing surfaces of the chemfets, and removing the protective layer. The method further includes, etching the dielectric layer and the protective layer together to form cavities corresponding to sensing surfaces of the chemfets.
Life Technologies Corporation


07/23/15
20150206594 

Fuse circuit with test mode


During a program operation of a fuse cell of a fuse circuit, all of a group of select transistors of a fuse cell are made conductive to program the fuse cell. During a test operation of a fuse cell of the fuse circuit, less than all of the group of select transistors are made conductive so that current less than a programming current flows through the fuse cell..

07/23/15
20150206588 

Semiconductor device


A semiconductor device has a smaller area. That is, in a row selection decoder including mos transistors, which selectively connect a plurality of selection signal lines to row selection lines of nand flash memories having an sgt structure, the mos transistors are formed on a planar silicon layer that is formed on a substrate, and each have a structure such that a drain, a gate, and a source are disposed in the vertical direction and the gate surrounds a silicon pillar.
Unisantis Electronics Singapore Pte. Ltd.


07/23/15
20150206587 

Methods and apparatuses with vertical strings of memory cells and support circuitry


Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate.
Micron Technology, Inc.


07/23/15
20150206578 

Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail sram memories


In one embodiment, a self-timed, dual-rail sram includes a self-timing circuit having a logic gate that is powered by voltage vdd and configured to receive a fire-sense-amplifier timing signal and to produce a vdd-domain sense-amplifier-enable signal soelv. The self-timing circuit includes an inverting level-shifter having complementary n-type and p-type transistors connected in series between voltage vdda and ground.
Lsi Corporation


07/23/15
20150206570 

Circuit and spin-torque mram bit line and source line voltage regulation


Circuitry and a method for regulating voltages applied to magnetoresistive bit cells of a spin-torque magnetoresistive random access memory (st-mram) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the ends of the selected bit cells are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed.
Everspin Technologies, Inc.


07/23/15
20150206488 

Gate driver on array (goa) circuit and display panel with same


The present invention provides a gate driver on array (goa) circuit and a display panel with the goa circuit. The driver circuit includes multiple stages of gate driver units and multiple stages of supplementary gate driver units connected in cascade, in which the nth stage gate driver unit includes a driving unit (42) and a pull-down unit (44) and the mth stage supplementary gate driver unit includes a supplementary driving unit (52) and a supplementary pull-down unit (54).
Shenzhen China Star Optoelectronics Technology Co., Ltd.


07/23/15
20150205904 

Placing transistors in proximity to through-silicon vias


Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by tsv's near transistors. The physical relationship between the tsv and nearby transistors can be taken into account when characterizing a circuit.
Synopsys, Inc.


07/16/15
20150200634 

Device for balancing the rise and fall slew-rates of an operational amplifier


An amplifier includes a pair of transistors connected in a differential stage, and a bias current source connected to a common node of the differential stage. A slew-rate compensation circuit is configured to derive from the common node a dynamic compensation current during a phase in which the voltage of the common node varies..
Stmicroelectronics (grenoble 2) Sas


07/16/15
20150200632 

Hysteresis comparator circuit having differential input transistors with switched bulk bias voltages


A first signal received at a first transistor is compared to a second signal received at a second transistor taking into account a hysteresis value to generate a comparison output. At least one of the first and second transistors has a floating bulk.
Stmicroelectronics International N.v.


07/16/15
20150200539 

Transient voltage suppressor


The invention provides a voltage regulator including a transient voltage suppressor. The transient voltage suppressor includes n first transistors and n semiconductor units.
Sumpro Electronics Corporation


07/16/15
20150200374 

Dopant for a hole conductor layer for organic semiconductor components, and use thereof


The invention relates to novel metal-organic materials for hole injection layers in organic electronic components. For example, in light-emitting components such as organic light diodes (oled) or organic light-emitting electrochemical cells (oleec) or organic field effect transistors or organic solar cells or organic photo detectors.
Osram Opto Semiconductors Gmbh


07/16/15
20150200301 

Pulsed laser anneal process for transistors with partial melt of a raised source-drain


A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth.
Intel Corporation


07/16/15
20150200298 

Modified tunneling field effect transistors and fabrication methods


Tunneling field effect transistors and fabrication methods thereof are provided, which include: obtaining a gate structure disposed over a substrate structure; and providing a source region and a drain region within the substrate structure separated by a channel region, the channel region underlying, at least partially, the gate structure, and the providing including: modifying the source region to attain a narrowed source region bandgap; and modifying the drain region to attain a narrowed drain region bandgap, the narrowed source region bandgap and the narrowed drain region bandgap facilitating quantum tunneling of charge carriers from the source region or the drain region to the channel region. Devices including digital modulation circuits with one or more tunneling field effect transistor(s) are also provided..
Globalfoundries Inc.


07/16/15
20150200295 

Drain extended mos transistors with split channel


A circuit including both drain-extended metal-oxide-semiconductor (demos) and low-voltage metal-oxide-semiconductor (lv_mos) devices and methods of manufacturing the same are provided. In one embodiment, demos device includes a first channel, a gate, a second channel, and a drain extension, wherein the second channel is split into a first portion and a second portion, and wherein the first portion of the second channel stops under the gate and is spaced away from the drain extension.
Cypress Semiconductor Corporation


07/16/15
20150200289 

Tunneling field effect transistor


The inventive concepts provide tunneling field effect transistors. The tunneling field effect transistor includes a source region, a drain region, a channel region, and a pocket region.
Samsung Electronics Co., Ltd.


07/16/15
20150200288 

Tunneling field effect transistor


Tunneling field effect transistors are provided. The tunneling field effect transistor includes a source region, a drain region, and a channel region disposed between the source region and the drain region.

07/16/15
20150200287 

Doped gallium nitride high-electron mobility transistor


Embodiments include high electron mobility transistors (hemts) comprising a substrate and a barrier layer including a doped component. The doped component may be a germanium doped layer or a germanium doped pulse.
Triquint Semiconductor, Inc.


07/16/15
20150200270 

Field effect transistors for high-performance and low-power applications


When forming semiconductor devices comprising high performance or low-power field effect transistors, the threshold voltage of the transistors is adjusted by the halo implantation and the source and drain regions are defined by a single implantation step. Thus, the number of process steps is reduced, whereas the electrical characteristics, such as leakage level, and performance of the transistors are maintained compared to conventional transistors..
Globalfoundries Inc.


07/16/15
20150200256 

Group iii nitride articles having nucleation layers, transitional layers, and bulk layers


Group iii (al, ga, in)n single crystals, articles and films useful for producing optoelectronic devices (such as light emitting diodes (leds), laser diodes (lds) and photodetectors) and electronic devices (such as high electron mobility transistors (hemts)) composed of iii-v nitride compounds, and methods for fabricating such crystals, articles and films.. .
Kyma Technologies, Inc.


07/16/15
20150200215 

Light sensing integrated circuit and manufacturing sensing integrated circuit


A manufacturing method of a sensing integrated circuit including the following acts. A plurality of transistors are formed.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/16/15
20150200207 

Display circuitry with improved transmittance and reduced coupling capacitance


A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (tft) layer.
Apple Inc.


07/16/15
20150200194 

Method of manufacturing a semiconductor device


A method of manufacturing a semiconductor device is provided. The method includes forming a fin structure on a semiconductor substrate and forming a well region in the semiconductor substrate by ion implantation so as to form transistors.
Semiconductor Manufacturing International (shanghai) Corporation


07/16/15
20150200184 

Full bridge rectifier module


A full bridge rectifier includes four bipolar transistors, each of which has an associated parallel diode. A first pair of inductors provides inductive current splitting and thereby provides base current to/from one pair of the bipolar transistors so that the collector-to-emitter voltages of the bipolar transistors are low.
Ixys Corporation


07/16/15
20150200139 

Epitaxial channel with a counter-halo implant to improve analog gain


Some embodiments of the present disclosure relate to an implant that improves long-channel transistor performance with little to no impact on short-channel transistor performance. To mitigate dibl, both long-channel and short-channel transistors on a substrate are subjected to a halo implant.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/16/15
20150200014 

Controlling dummy word line bias during erase in non-volatile memory


A technique for erasing non-volatile memory such as a nand string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate.
Sandisk Technologies Inc.


07/16/15
20150198850 

Liquid crystal display device


In a liquid crystal display device, a plurality of pixel electrodes respectively connected to a plurality of source bus lines are arranged along an extension direction of the source bus line, the pixel electrodes being alternately displaced to one side and then the other in an arrangement direction of the plurality of source bus lines. Thin film transistors each include a semiconductor layer containing a source portion, a channel portion and a drain portion, and a gate electrode formed using a portion of the gate bus line.
Sharp Kabushiki Kaisha


07/16/15
20150198826 

Display panel


A display panel is provided. The display panel includes a first substrate, a second substrate, a liquid crystal layer, a plurality of thin film transistors, a plurality of metal wires, a protection layer, a first alignment layer, and a plurality of agglomerates.
Innolux Corporation


07/16/15
20150198654 

Non-planar field effect transistor test structure and lateral dielectric breakdown testing method


Disclosed are test structures and methods for non-planar field effect transistors. The test structures comprise test device(s) on an insulator layer.
International Business Machines Corporation


07/16/15
20150198642 

Measurement of bonding resistances


Disclosed is a method for determining a contact resistance of an h bridge including four transistors, each transistor having a point of connection to two neighboring transistors, a bond being produced in each case between a connection point lying between two transistors and an access terminal. The method includes: acting on the open/closed state of the transistors of the bridge so that the transistors on either side of the connection point corresponding to the access terminal are open; applying a determined voltage to an access terminal; determining the current flowing through the bond corresponding to the access terminal; grounding an access terminal neighboring the access terminal if this neighboring access terminal is not already connected to ground; and measuring the voltage at the other neighboring access terminal..
Continental Automotive Gmbh


07/09/15
20150195000 

Circuits having switches providing increased voltage swing uniformity


Circuits are disclosed providing uniform voltage swing across transmit switches for improved device performance. An integrated circuit (ic) formed on a die includes a switch having one or more field effect transistors (fets) defining an rf signal path between an input port and an output port, each fet having a body node, and the switch being configured to be capable of being in on and off states.
Skyworks Solutions, Inc.


07/09/15
20150194977 

Semiconductor integrated circuit device


The semiconductor integrated circuit device includes a t-type switch circuit ts[k] that is between an input port a[k] and an input terminal ain of an analog/digital conversion circuit and that includes first, second, and third pmos transistors mp1, mp2, and mpc, and first, second, and third nmos transistors mn1, mn2, and mnc; and a fourth pmos transistor mpu for pre-charging the input terminal ain to a power supply voltage vcca. In detecting the presence or absence of a disconnection from the input port a[k] to a signal input terminal vint[k], first, the input terminal ain is pre-charged to the power supply voltage vcca via the fourth pmos transistor mpu and also the second nmos transistor mn2 and the second pmos transistor mp2 are turned on, and the first nmos transistor mn1, the first pmos transistor mp1, the third pmos transistor mpc, and third the nmos transistor mnc are turned off..
Renesas Electronics Corporation


07/09/15
20150194957 

Semiconductor device with buffer and replica circuits


A semiconductor device, includes an input buffer, first and second pmos transistors serially interconnected between a first power supply node and an output node of the input buffer. First and second nmos transistors are serially interconnected between a second power supply node and the output node of the input buffer.
Ps4 Luxco S.a.r.l.


07/09/15
20150194954 

Circuit for generating bias current


A circuit for generating a bias current is provided, including: a loop unit, which includes a first current mirror structure constituted by a first pmos transistor and a second pmos transistor, and a second current mirror structure constituted by a first nmos transistor and a second nmos transistor, where the first and second nmos transistors operate in a sub-threshold region; an output unit, adapted to output the bias current; and an amplifying unit, which includes a first input terminal and an output terminal, where the first input terminal is connected with a source of the first nmos transistor or a source of the second nmos transistor, and the output terminal is connected with gates of both the first and the second pmos transistors. The bias current output from the circuit may be not sensitive to temperatures..
Shanghai Huahong Grace Semiconductor Manufacturing Corporation


07/09/15
20150194952 

Active matrix panel, detection apparatus and detection system


An active matrix panel includes a gate line connected to control electrodes of a plurality of transistors; and a drive circuit supplying the gate line with a conducting voltage and a non-conducting voltage. The drive circuit includes a shift register including a plurality of shift register unit circuits connected to each other, and a demultiplexer including a plurality of demultiplexer unit circuits into which output signals of the shift register unit circuits are input.
Canon Kabushiki Kaisha


07/09/15
20150194915 

H-bridge shoot-through avoidance


An h-bridge uses a diode or other level shifter between the gates of two transistors in series. The level shifter enforces a sufficient voltage separation between the gates to ensure that both transistors cannot be turned on at the same time.
Makerbot Industries, Llc


07/09/15
20150194900 

Power converter with modulated secondary-side synchronous rectification


A power converter includes a power transformer, primary-side circuitry connected between a power source and a primary coil, and secondary-side circuitry connected between secondary coil(s) and a load to generate an output voltage and load current for a load. The secondary-side circuitry includes (i) an output inductor, (ii) one or more power transistors, and (iii) control circuitry generating switching signals to operate the power transistors as synchronous rectifiers.
Bel Fuse (macao Commercial Offshore) Limited


07/09/15
20150194893 

Power management multi-chip module with separate high-side driver integrated circuit die


A packaged device includes a first die, a second die, and specially spaced and positioned sets of package terminals. The first die includes a pulse-width modulator (pwm), a processor, a timer, high-side drivers, low-side drivers, and a fault protection circuit.
Active-semi, Inc.


07/09/15
20150194803 

Electrical circuit for cutting off an electric power supply comprising transistors and fuses having redundant logic


The invention relates to an electric circuit suitable for cutting off an electric power supply of an electric device, the circuit including an electrical device and a supply voltage source of the electrical device, also having as inputs at least two discrete electrical signals, the values of which condition the cutting off of the electric power supply of the device, the electric circuit being characterised in that same includes: at least two modules for cutting of the electric power supply connected between the voltage source and the electrical device, each module tar cutting off the electric power supply being controlled in accordance with the values of the discrete electrical signals; and at least two modules for comparing discrete electrical signals in parallel, in which at least one of the modules for cutting off the electric power supply is controlled by the outputs of the modules for comparing discrete signals.. .
Sagem Defense Securite


07/09/15
20150194606 

High mobility polymer thin-film transistors with capillarity-mediated self-assembly


Embodiments of the invention include methods and materials for preparing organic semiconducting layers, for example one used in an organic semiconductor device including a substrate with a nanostructured surface and a polymeric semiconductor film overlying the nanostructured surface. Aspects of the invention use capillary action to modulate polymer chain self-assembly on a surface and unidirectional alignment at a critical buried interface where charge carriers migrate between a dielectric and the polymer.
The Regents Of University Of California


07/09/15
20150194603 

Methods of fabricating memory devices


Provided is a method of fabricating a memory device. The method includes defining a cell region and a driving region on a substrate, forming driving transistors on the driving region, forming a first bit line in the cell region, a first unit memory cell disposed on an upper surface of the first bit line, a word line disposed on upper surfaces of the first unit memory cells, and a second unit memory cell disposed on an upper surface of the word line, forming a planarization layer configured to fill between the second unit memory cells, and including second bit line grooves on the upper surfaces of the first bit lines, bit line contact vias in the second bit line grooves, floating electrode grooves on upper surfaces of ends of the word lines, and a first floating contact via and a second floating contact via in each of the floating electrode grooves, simultaneously forming second bit lines in the second bit line grooves, bit line contact electrodes in the bit line contact vias, floating electrodes in the floating electrode grooves, first floating contact electrodes in the first floating contact vias, and second floating contact electrodes in the second floating contact vias..
Samsung Electronics Co., Ltd.


07/09/15
20150194510 

Self-aligned emitter-base-collector bipolar junction transistors with a single crystal raised extrinsic base


Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer.
International Business Machines Corporation


07/09/15
20150194505 

Manufacture of a variation resistant metal-oxide-semiconductor field effect transistor (mosfet)


Variation resistant metal-oxide-semiconductor field effect transistors (mosfets) are manufactured using a high-k, metal-gate ‘channel-last’ process. A cavity is formed between spacers formed over a well area having separate drain and source areas, and then a recess into the well area is formed.
Gold Standard Simulations Ltd.


07/09/15
20150194496 

Contact resistance reduction in finfets


A semiconductor device having fin transistors includes a plurality of substantially parallel semiconductor fins formed over a substrate and a gate structure formed over the fins transversely to a longitudinal axis of the fins. Source and drain regions are formed on opposite sides of the gate structure and are merged with the fins by an epitaxially grown crystalline material between the fins in merged regions.
Stmicroelectronics, Inc.


07/09/15
20150194446 

Display device and driving method thereof


To provide a display device and a driving method thereof, where variations in the threshold voltage of transistors can be compensated and thus variations in luminance of light-emitting elements can be suppressed. In a first period, initialization is performed; in a second period, a voltage based on the threshold voltage of a first transistor is held in first and second storage capacitors; in a third period, a voltage based on a video signal voltage and the threshold voltage of the first transistor is held in the first and second storage capacitors; and in a fourth period, voltages held in the first and second storage capacitors are applied to a gate terminal of the first transistor to supply a current to a light-emitting element, so that the light-emitting element emits light.
Semiconductor Energy Laboratory Co., Ltd.


07/09/15
20150194443 

Display circuitry with reduced metal routing resistance


A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (tft) layer.
Apple Inc.


07/09/15
20150194439 

Embedded nvm in a hkmg process


A process integration is disclosed for fabricating complete, planar non-volatile memory (nvm) cells (110) prior to the formation of high-k metal gate electrodes for cmos transistors (212, 213) using a planarized dielectric layer (26) and protective mask (28) to enable use of a gate-last hkmg cmos process flow without interfering with the operation or reliability of the nvm cells.. .
Freescale Semiconductor, Inc.


07/09/15
20150194431 

Static random access memory cell and forming method thereof


A sram cell and a forming method thereof are provided. The sram cell includes: a pull-up transistor, a pull-down transistor, a pass gate transistor, a tensile stress film which covers the pull-up transistor and the pull-down transistor, and an interlayer dielectric isolating layer which covers the tensile stress film and the pass gate transistor.
Shanghai Huahong Grace Semiconductor Manufacturing Corporation


07/09/15
20150194428 

Method of manufacturing semiconductor device with offset sidewall structure


A method of manufacturing a semiconductor device with nmos and pmos transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits.
Renesas Electronics Corporation


07/09/15
20150194417 

Snapback inhibiting clamp circuitry for mosfet esd protection circuits


Circuit configurations and related methods are disclosed that may be implemented to protect circuitry from adverse effects of transistor snapback that may occur during esd events. The circuitry and methods may be implemented as part of distributed esd rail clamping circuitry that includes esd circuit elements that are coupled to power nodes or supply rails and not to signal nodes or signal pads of the circuitry in a manner that reduces parasitic loading on signal pads to reduce or substantially eliminate nmos and/or pmos transistor snapback occurrence, while at the same time providing rail-clamping capability during occurrence of esd events.
Silicon Laboratories Inc.


07/09/15
20150194416 

Single-chip field effect transistor (fet) switch with silicon germanium (sige) power amplifier and methods of forming


Various embodiments include field effect transistors (fets) and methods of forming such fets. One method includes: forming a first set of openings in a precursor structure having: a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide; a silicon germanium (sige) layer overlying the silicon substrate; a silicon layer overlying the sige layer; a second oxide overlying the silicon layer; and a sacrificial layer overlying the second oxide, wherein the first set of openings each expose the silicon substrate; undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a trench corresponding with each of the first set of openings; passivating exposed surfaces of at least one of the sige layer or the silicon layer in the first set of openings; and at least partially filling each trench with a dielectric..
International Business Machines Corporation


07/09/15
20150194369 

Semiconductor package with conductive clips


One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (ic) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadfirame and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections..
International Rectifier Corporation


07/09/15
20150194216 

Semiconductor storage device


A semiconductor storage device includes a plurality of memory cell transistors that are connected to each other in series, a plurality of word lines that are connected to the plurality of memory cell transistors, and a control circuit. The control circuit applies a first potential to a selected one of the plurality of word lines.
Kabushiki Kaisha Toshiba


07/09/15
20150194207 

Method and screening memory cells for disturb failures


Embodiments include a method comprising: receiving a first voltage; and while testing a memory cell: modifying the first voltage to generate a second voltage that is different from the first voltage; and performing a first read operation on the memory cell, based on applying (i) the second voltage to an array of transistors of the memory cell and (ii) the first voltage to the memory cell.. .
Marvell World Trade Ltd.


07/09/15
20150194093 

Display device, laying out light emitting elements, and electronic device


Disclosed herein is a display device in which light emitting elements of a plurality of colors including a light emitting element emitting blue light are formed in each pixel on a substrate on which a transistor is formed for each sub-pixel, and a plurality of pixels formed with sub-pixels of the plurality of colors as a unit are arranged in a form of a matrix, wherein relative positional relation between transistors of sub-pixels of respective light emission colors including blue light and a light emitting section of a light emitting element emitting the blue light is laid out such that distances between the transistors of the sub-pixels of the respective light emission colors including the blue light and the light emitting section of the light emitting element emitting the blue light are equal to each other for the respective colors.. .
Sony Corporation


07/09/15
20150194092 

Pixel driving unit and driving method thereof, and pixel circuit


The present disclosure relates to a technical field of display, and more particularly, to a pixel driving unit and a driving method thereof, as well as a pixel circuit comprising the pixel driving unit; the pixel driving unit comprises a driving sub-circuits and a control sub-circuit, wherein the control sub-circuit is connected to a data line, and the driving sub-circuits are connected to the control sub-circuit. In the process of driving the light emitting device, the pixel driving unit can effectively eliminate the nonuniformity due to the threshold voltage of the driving transistor and a phenomenon of image sticking due to the threshold voltage drift, avoid a problem of nonuniform brightness of the active matrix oled due to the difference of the threshold voltages of the driving transistors thereof between the light emitting devices of different pixel driving units of the active matrix oled, and improve the driving effect of the pixel driving unit with respect to the light emitting device, and further improve the quality of the active matrix oled..
Boe Technology Group Co., Ltd.


07/09/15
20150194089 

Cascode driver circuit


This disclosure provides systems, methods, and apparatus for providing a cascode driver circuit for providing positive and negative polarities of two or more voltages at an output node. The voltages provided by the cascode driver circuit can be used to provide voltages to various interconnects and terminals of the display apparatus.
Pixtronix, Inc.


07/09/15
20150192634 

Display apparatus including dummy display element for tft testing


This disclosure provides systems, methods and apparatus for a display apparatus including dummy display elements that can be switched between being coupled to a test bus and a drive bus. When connected to the drive bus, the circuit components, including thin-film transistors, of the dummy display element experience exposure to typical operating loads.
Pixtronix, Inc.


07/09/15
20150191817 

Precursors and methods for atomic layer deposition of transition metal oxides


Methods are provided herein for forming transition metal oxide thin films, preferably group ivb metal oxide thin films, by atomic layer deposition. The metal oxide thin films can be deposited at high temperatures using metalorganic reactants.
Asm International N.v.


07/02/15
20150189711 

Led controller and method therefor


In an embodiment, an led controller is configured to form a charge transfer sequence to selectively enable led transistors of a plurality of led transistors that are configured for coupling in parallel with a plurality of leds. An embodiment may include that the led controller is configured to sequentially couple a charge capacitor to a gate-to-source capacitor of each led transistor of the plurality of led transistors to one of charge or to refresh the gate-to-source capacitor of a respective led transistor and to one of enable or re-enable the respective led transistor wherein the gate-to-source capacitor is a parasitic gate-to-source capacitor of the led transistor wherein the charge capacitor is sequentially coupled to the gate-to-source capacitor of each led transistor..
Semiconductor Components Industries, Llc


07/02/15
20150189207 

Protection layer in cmos image sensor array region


A semiconductor image sensor device having a conformal protective layer includes a semiconductor substrate a pixel-array region and a peripheral region. The conformal protective layer is disposed over a plurality of pixels having a photodiode and a plurality of transistors in the pixel-array region.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/02/15
20150188536 

Method and system for reliable bootstrapping switches


Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (mos) transistor having a pull-down path coupled to a gate terminal of the switching mos transistor. The pull-down path includes a diode-connected mos transistor coupled in parallel with a second mos transistor that couples the gate terminal of the switching mos transistor to ground via third and fourth mos transistors when the switching mos transistor is in an off state.
Maxlinear, Inc.


07/02/15
20150188520 

Semiconductor device


A semiconductor device that can operate normally with lower power consumption is provided. The semiconductor device includes a pair of first circuits which each include a first transistor and a second transistor capable of controlling the supply of a first signal to a gate of the first transistor, and a second circuit which is capable of generating a second signal which is to be supplied to a gate of the second transistor and which has a larger amplitude than the first signal.
Semiconductor Energy Laboratory Co., Ltd.


07/02/15
20150188420 

Output voltage adjustable charge pump


A charge pump that uses a control unit of a chip to adjust the on/off status of power switches and capacitor boost switches of a change-over switch set, enabling input voltage to be boosted by selected capacitors to the desired voltage level subject to conduction and cutoff of selected transistors, and therefore a predetermined voltage level of output voltage can be provided to an internal working circuit of an electronic apparatus without changing the circuit layout of the chip and the package substrate that is packaged on the chip, and thus, the chip and the package substrate simply need to be verified once, eliminating further verification procedure and time prior to vending and saving much the cost.. .
Egalax_empia Technology Inc.


07/02/15
20150188419 

Charge pump that allows change of output voltage by changing the wiring


A charge pump includes a chip and a package substrate packaged on the chip and installed in a circuit board. One of the 1st˜(x−y)th external pins of the package substrate is electrically connected to the (x−y)th input pin of the chip, and the other end of the same external pin is electrically connected to the input voltage of the circuit board.
Egalax_empia Technology Inc.


07/02/15
20150188418 

Pumping circuit


A pumping circuit includes a cross-coupled charge pump circuit including first and second capacitors configured to pump an input voltage in response to a first clock signal and to an inverted first clock signal and a plurality of transistors configured to one of transfer the input voltage to the first and second capacitors and to transfer a pumping voltage to an output node, and a switching voltage supply circuit configured to supply switching voltages to gates of the plurality of transistors to enable the transfer of the input voltage and the pumping voltage.. .
Sk Hynix Inc.


07/02/15
20150188313 

Tie-off circuit with output node isolation for protection from electrostatic discharge (esd) damage


Embodiments relate to electrostatic discharge (esd) protection. One embodiment includes a tie-off circuit including a multiple field effect transistors (fets), a first internal node, a second internal node, a first output node and a second output node.
International Business Machines Corporation


07/02/15
20150187958 

Igzo devices with reduced electrode contact resistivity and methods for forming the same


Embodiments described herein provide indium-gallium-zinc oxide (igzo) devices, such as igzo thin-film transistors (tfts), and methods for forming such devices. A substrate is provided.
Intermolecular Inc.


07/02/15
20150187956 

Igzo devices with increased drive current and methods for forming the same


Embodiments described herein provide indium-gallium-zinc oxide (igzo) devices, such as igzo thin-film transistors (tfts), and methods for forming such devices. A substrate is provided.
Intermolecular Inc.


07/02/15
20150187941 

Transistor and forming the same


Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate can be provided.
Semiconductor Manufacturing International (shanghai) Corporation


07/02/15
20150187939 

Metal gate transistor and tuning metal gate profile


A semiconductor device having arrays of metal gate transistors is fabricated by forming a number of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer, depositing a tensile ild layer between the dummy gate structures, stressing the tensile ild layer, removing at least the dummy gate material to form a number of trenches, and depositing a metal gate material in the trenches, which have a tapered profile.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


07/02/15
20150187935 

Semiconductor device including pillar transistors


A first pillar transistor and a second pillar transistor are arranged with no other pillar transistor therebetween, a distance between a first silicon pillar in the first pillar transistor and a second silicon pillar in the second pillar transistor is smaller than a distance between a third silicon pillar in a third pillar transistor and the first silicon pillar.. .
Ps4 Luxco S.a.r.l.


07/02/15
20150187924 

Low sheet resistance gan channel on si substrates using inaln and algan bi-layer capping stack


transistors or transistor layers include an inaln and algan bi-layer capping stack on a 2deg gan channel, such as for gan mos structures on si substrates. The gan channel may be formed in a gan buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between gan and si.

07/02/15
20150187881 

Contact resistance reduction in finfets


A semiconductor device having fin transistors includes a plurality of substantially parallel semiconductor fins formed over a substrate and a gate structure formed over the fins transversely to a longitudinal axis of the fins. Source and drain regions are formed on opposite sides of the gate structure and are merged with the fins by an epitaxially grown crystalline material between the fins in merged regions.
Stmicroelectronics, Inc.


07/02/15
20150187878 

Semiconductor device


To provide a semiconductor device including a transistor in which an oxide semiconductor is used and on-state current is high. In a semiconductor device including a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion, the first transistor and the second transistor have different structures.
Semiconductor Energy Laboratory Co., Ltd.


07/02/15
20150187818 

Light-emitting device


A light-emitting device capable of suppressing variation in luminance among pixels is provided. A light-emitting device includes a pixel and first and second circuits.
Semiconductor Energy Laboratory Co., Ltd.


07/02/15
20150187794 

Method for forming deep trench isolation for rf devices on soi


A semiconductor device includes a silicon-on-insulator (soi) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a soi substrate having shallow trench isolations (stis) and transistors formed within and on the second semiconductor substrate, respectively.
Semiconductor Manufacturing International (shanghai) Corporation


07/02/15
20150187778 

Semiconductor device


A semiconductor storage device capable of performing low-voltage operation, reducing standby current, and decreasing memory size is provided. The semiconductor storage device is a semiconductor device including first to fourth transistors and a capacitor.
Semiconductor Energy Laboratory Co., Ltd.


07/02/15
20150187775 

Semiconductor device and driving the same


A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line.
Semiconductor Energy Laboratory Co., Ltd.


07/02/15
20150187773 

High mobility transistors


An integrated circuit containing an n-channel finfet and a p-channel finfet has a dielectric layer over a silicon substrate. The fins of the finfets have semiconductor materials with higher mobilities than silicon.
Texas Instruments Incorporated


07/02/15
20150187772 

Optimized layout for relaxed and strained liner in single stress liner technology


An integrated circuit and method with a single stress liner film and a stress relief implant where the distance of the stress relief implant to the transistors is adjusted for improved transistor performance.. .
Texas Instruments Incorporated


07/02/15
20150187770 

High mobility transistors


An integrated circuit containing an n-channel finfet and a p-channel finfet is formed by forming a first polarity fin epitaxial layer for a first polarity finfet, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finfet. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask.
Texas Instruments Incorporated


07/02/15
20150187769 

Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods


A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type.
Tela Innovations, Inc.


07/02/15
20150187768 

Poly gate extension design methodology to improve cmos performance in dual stress liner process flow


An integrated circuit and method with dual stress liners and with nmos transistors with gate overhang of active that is longer than the minimum design rule and with pmos transistors with gate overhang of active that are not longer than the minimum design rule.. .
Texas Instruments Incorporated


07/02/15
20150187759 

High sheet resistor in cmos flow


An integrated circuit containing cmos gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the nsd layers of the nmos transistors of the cmos gates and concurrently with the psd layers of the pmos transistors of the cmos gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the cmos gates. A process of forming an integrated circuit containing cmos gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the nsd layers of the nmos transistors of the cmos gates and concurrently with the psd layers of the pmos transistors of the cmos gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the cmos gates..
Texas Instruments Incorporated


07/02/15
20150187747 

Circuit with inter-layer vias and intra-layer coupled transistors


A circuit comprises a first layer comprising a first voltage line, a first transistor coupled with the first voltage line, a second transistor coupled with the first voltage line, and a first line coupling a drain of the first transistor with a gate of the second transistor. The circuit also comprises a second layer comprising a second voltage line, a third transistor coupled with the second voltage line, a fourth transistor coupled with the second voltage line, and a second line coupling a drain of the third transistor with a gate of the fourth transistor.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/02/15
20150187659 

High quality dielectric for hi-k last replacement gate transistors


A replacement metal gate transistor is formed with high quality gate dielectric under the high-k dielectric. The high quality gate dielectric is formed on the substrate at a temperature of at least 850° c.
Texas Instruments Incorporated


07/02/15
20150187653 

High-k / metal gate cmos transistors with tin gates


An integrated circuit with a thick tin metal gate with a work function greater than 4.85 ev and with a thin tin metal gate with a work function less than 4.25 ev. An integrated circuit with a replacement gate pmos tin metal gate transistor with a workfunction greater than 4.85 ev and with a replacement gate nmos tin metal gate transistor with a workfunction less than 4.25 ev.
Texas Instruments Incorporated


07/02/15
20150187585 

Dummy gate placement methodology to enhance integrated circuit performance


A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an integrated circuit.. .
Texas Instruments Incorporated


07/02/15
20150187552 

High voltage power supply filter


Systems, devices, circuits, and methods are provided for an improved mass spectrometry detection system that comprises at least one component that operates at a high voltage. A number of high voltage filters or circuits are provided for reducing noise from high voltage power supplies that produce positive and negative voltages.
Dh Technologies Development Pet. Ltd.


07/02/15
20150187432 

Shift register circuit, display panel, and electronic apparatus


Disclosed herein is a shift register circuit that is formed on an insulating substrate with thin film transistors having channels of the same conductivity type and includes shift stages, each of the shift stages including: a first thin film transistor; a second thin film transistor; a 3(1)-th thin film transistor; a 3(2)-th thin film transistor; a 4(1)-th thin film transistor; a 4(2)-th thin film transistor; a fifth thin film transistor; and a sixth thin film transistor.. .
Sony Corporation


07/02/15
20150187418 

Metal line connection for improved rram reliability, semiconductor arrangement comprising the same, and manufacture thereof


An integrated circuit device includes an array of rram cells, an array of bit lines for the array of rram cells, and an array of source lines for the array of rram cells. Both the source lines and the bit lines are in metal interconnect layers above the rram cells.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/02/15
20150187260 

Organic light emitting display device


An organic light emitting display device including an emission unit and a pixel circuit unit. The emission unit includes an organic light emitting diode.
Lg Display Co., Ltd.




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Transistors topics: Transistors, Semiconductor, Semiconductor Device, Integrated Circuit, High Speed, Photodiode, Memory Effect, Silicon Nitride, Enhancement, Ion Implant, Ion Channel, Interrupted, Reference Voltage, Semiconductor Devices, Semiconductor Substrate

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