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Transistors patents



      
           
This page is updated frequently with new Transistors-related patent applications. Subscribe to the Transistors RSS feed to automatically get the update: related Transistors RSS feeds. RSS updates for this page: Transistors RSS RSS


Circuit for clamping current in a charge pump

Conversant Intellectual Property Management

Circuit for clamping current in a charge pump

Gan transistors with polysilicon layers for creating additional components

Efficient Power Conversion

Gan transistors with polysilicon layers for creating additional components

Gan transistors with polysilicon layers for creating additional components

Nxp B.v.

Rf power device

Date/App# patent app List of recent Transistors-related patents
01/29/15
20150031313
 Single differential-inductor vco with implicit common-mode resonance patent thumbnailnew patent Single differential-inductor vco with implicit common-mode resonance
A circuit for a single differential-inductor oscillator with common-mode resonance may include a tank circuit formed by coupling a first inductor with a pair of first capacitors; a cross-coupled transistor pair coupled to the tank circuit; and one or more second capacitors coupled to the tank circuit and the cross-coupled transistors. The single differential-inductor oscillator may be configured such that a common mode (cm) resonance frequency (fcm) associated with the single differential-inductor oscillator is at twice a differential resonance frequency (fd) associated with the single differential-inductor oscillator..
Broadcom Corporation
01/29/15
20150031194
 Method for designing antenna cell that prevents plasma induced gate dielectric damage in semiconductor integrated circuits patent thumbnailnew patent Method for designing antenna cell that prevents plasma induced gate dielectric damage in semiconductor integrated circuits
An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor.
Taiwan Semiconductor Manufacturing Co., Ltd.
01/29/15
20150031180
 Vertical channel transistor with self-aligned gate electrode and  fabricating the same patent thumbnailnew patent Vertical channel transistor with self-aligned gate electrode and fabricating the same
A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.. .
Sk Hynix Inc.
01/29/15
20150031178
 Method of cmos manufacturing utilizing multi-layer epitaxial hardmask films for improved gate spacer control patent thumbnailnew patent Method of cmos manufacturing utilizing multi-layer epitaxial hardmask films for improved gate spacer control
An integrated circuit containing pmos transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is carbon-containing silicon nitride formed using a hydrocarbon reagent.
Texas Instruments Incorporated
01/29/15
20150031177
 Method of cmos manufacturing utilizing multi-layer epitaxial hardmask films for improved epi profile patent thumbnailnew patent Method of cmos manufacturing utilizing multi-layer epitaxial hardmask films for improved epi profile
An integrated circuit containing pmos transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent.
Texas Instruments Incorporated
01/29/15
20150029791
 Nonvolatile semiconductor memory device patent thumbnailnew patent Nonvolatile semiconductor memory device
A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit..
Kabushiki Kaisha Toshiba
01/29/15
20150029783
 Method of detecting transistors mismatch in a sram cell patent thumbnailnew patent Method of detecting transistors mismatch in a sram cell
The present invention provides a method of detecting the transistor mismatch in a sram cell. The sram cell comprises two pass-gate transistors and a bi-stable circuit including two pull up transistors and two pull down transistors.
Shanghai Huali Microelectronics Corporation
01/29/15
20150029769
 Systems, circuits, devices, and methods with bidirectional bipolar transistors patent thumbnailnew patent Systems, circuits, devices, and methods with bidirectional bipolar transistors
Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (btrans) for switching. Four-terminal three-layer btrans provide substantially identical operation in either direction with forward voltages of less than a diode drop.
Ideal Power, Inc.
01/29/15
20150029638
 Polyimides as dielectrics patent thumbnailnew patent Polyimides as dielectrics
Polyimides derived from a primary aromatic diamine and aromatic dianhydride mono-mer moieties, wherein one or more of said moieties contain at least one substituent on the aromatic ring selected from propyl and butyl, especially from isopropyl, isobutyl, tert.butyl, show good solubility and are well suitable as dielectric material in electronic devices such as capacitors and organic field effect transistors.. .
Basf Se
01/29/15
20150029426
 Liquid crystal display and driving method thereof patent thumbnailnew patent Liquid crystal display and driving method thereof
The present invention relates to a liquid crystal display and a driving method thereof. The liquid crystal display of the present invention includes a pixel electrode including: a first subpixel electrode, a second subpixel electrode, and a third subpixel electrode electrically separated from each other; a first thin film transistor connected to the first subpixel electrode; a second thin film transistor connected to the second subpixel electrode; a third thin film transistor connected to the third subpixel electrode; a fourth thin film transistor connected to the second subpixel electrode and the third subpixel electrode; a first gate line connected to the first to third thin film transistors; a second gate line connected to the fourth thin film transistor; a data line connected to the first and second thin film transistors; and a storage electrode line connected to the third thin film transistor..
Samsung Display Co., Ltd.
01/29/15
20150029174
new patent

Scanning circuit and display device


A display device including a scanning circuit formed using single conductivity type thin-film transistors suppresses threshold changes in the thin-film transistors forming the scanning circuit by controlling a circuit for maintaining an internal node of the unit circuits forming the scanning circuit at a constant potential is controlled by a clock signal or a pulse signal having a smaller amplitude than the amplitude of an output signal.. .
Nlt Technologies, Ltd.
01/29/15
20150029169
new patent

Scan lines driver and organic light emmiting display device using the same


In a scan lines driver that is used for driving scan lines of an organic light emitting diodes (oled) display, a large voltage drop can develop between the gate or source of one of its transistors and the corresponding drain during a scan signal outputting period. This large voltage drop can excessively stress the one transistor.
Samsung Display Co., Ltd.
01/29/15
20150029049
new patent

Electronic circuit


An electronic circuit includes: a pair of first transistors in which a first control signal is inputted to at least one of a first control terminal; a comparator circuit that sets electric potentials of a pair of differential output terminals based on an electric current flowing through the pair of first transistors; second transistors that are coupled in series in a path between an electric power source and a node from at least one of the pair of differential output terminals and between the corresponding pair of first transistors, and having a second control terminals to which a second control signal is inputted; first switches that are respectively coupled in series to the second transistors in the path and that are turned on in synchronization with a clock signal; and a generation circuit that generates the second control signal based on the clock signal.. .
Fujitsu Limited
01/29/15
20150028955
new patent

Rf power device


In rf power transistors, the current distribution along edges of the transistor die may be uneven leading to a loss in efficiency and in the output power obtained, resulting in degradation in performance. When multiple parallel dies are placed in a package, distribution effects along the vertical dimension of the dies are more pronounced.
Nxp B.v.
01/29/15
20150028953
new patent

Scalable periphery for digital power control


A scalable periphery digital power control arrangement is presented. The scalable periphery digital power control arrangement comprises a plurality of pmos transistors connected in parallel, where the plurality of transistors is operatively coupled to a voltage source.
Peregrine Semiconductor Corporation
01/29/15
20150028952
new patent

Programmable multi-gain current amplifier


The programmable multi-gain current amplifier circuitry includes a pair of mos transistors setting the voltage at x terminal to zero using negative feedback formed by a third mos transistor. Input resistance is in the range of few tens of ohms.
King Fahd University Of Petroleum And Minerals
01/29/15
20150028939
new patent

Circuit for clamping current in a charge pump


A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors.
Conversant Intellectual Property Management Inc.
01/29/15
20150028936
new patent

Semiconductor device and display device


A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (t1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (t2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (t1). A gate terminal of the transistor (t2) is connected to the source terminal of the transistor (t2).
Sharp Kabushiki Kaisha
01/29/15
20150028930
new patent

Variable delay element


A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit.
Stmicroelectronics International N.v.
01/29/15
20150028927
new patent

Low power master-slave flip-flop


A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode.
Nvidia Corporation
01/29/15
20150028923
new patent

High efficiency gate drive circuit for power transistors


An improved gate drive circuit is provided for a power device, such as a transistor. The gate driver circuit may include: a current control circuit; a first secondary current source that is used to control the switching transient during turn off of the power transistor and a second secondary current source that is used to control the switching transient during turn on of the power transistor.
Aisin Aw Co. Ltd.
01/29/15
20150028920
new patent

Multiplexer, look-up table and fpga


The present invention relates to a multiplexer comprising at least a first input and a second input and one output connected to the first input via a first pass gate and to the second input via a second pass gate, wherein the first pass gate comprises at least a first double-gate transistor, and the second pass gate comprises at least a second double-gate transistor, and each of the first and second double-gate transistors has a first gate controlled based on a first control signal and a second gate controlled based on a second control signal. The invention further relates to a look-up table and a and an fpga based on the multiplexer..
Soitec
01/29/15
20150028847
new patent

Puf method using and circuit having an array of bipolar transistors


A method of identifying a component by a response to a challenge is disclosed, the component comprising an array of bipolar transistors connectable in parallel so as to have a common collector contact, a common emitter contact and a common base contact, the challenge comprising a value representative of a total collector current value, the method comprising: receiving the challenge; supplying the total collector current to the common collector contact; detecting instability in each of a group of the transistors; and determining the response in dependence on the group. A circuit configured to operate such a method is also disclosed..
Nxp B.v.
01/29/15
20150028841
new patent

Dc/dc converter


A dc/dc converter has an active energy store, such as an inductance, which can be periodically charged and discharged by one or more semiconductor switches, such as transistors. To avoid voltage overshoot, an rcd element is provided for at least one semiconductor switch, wherein a capacitor and a diode of the rcd element are connected in series, and a resistor of the rcd element can be connected either in parallel with the diode or disconnected from the diode by a switch.
Siemens Aktiengesellschaft
01/29/15
20150028829
new patent

Envelope tracking power supply with direct connection to power source


A communication device, such as a smart phone, includes an envelope tracking power supply. The envelope tracking power supply is configured for direct connection to a supply voltage.
Broadcom Corporation
01/29/15
20150028766
new patent

Pixel circuit and driving the same


The present disclosure relates to a field of display technology, and particularly to a pixel circuit and a method for driving the same. The pixel circuit includes a driving sub-circuit, a resetting sub-circuit, and a charging sub-circuit, wherein the driving sub-circuit includes a driving transistor, a first transistor, a third transistor, a first storage capacitor and a second storage capacitor; the resetting sub-circuit discharges the first storage capacitor and the second storage capacitor under the control of a first scan signal outputted from the first scan signal line; and the charging sub-circuit includes a fifth transistor and a sixth transistor.
Boe Technology Group Co., Ltd
01/29/15
20150028681
new patent

Multi-level output cascode power stage


A power stage to generate an output voltage at one of a high reference voltage, an intermediate reference voltage and a low reference voltage, including a first switch stage connecting the output terminal to the high reference voltage, comprising a pair of transistors connected in series along their source-to-drain paths, a first transistor coupled to the output terminal and having its gate biased at the intermediate voltage, a second transistor having a gate that receives a first stage control signal that varies between the high reference voltage and the intermediate reference voltage, a second switch stage connecting the output terminal to the intermediate reference voltage, having a gate that receives a second stage control signal that varies among the high reference voltage, intermediate reference voltage and low reference voltage, a third switch stage connecting the output terminal to the low reference voltage, having a pair of transistors connected in series along their source-to-drain paths, a first transistor coupled to the output terminal and having its gate biased at the intermediate voltage, a second transistor having a gate that receives a third stage control signal that varies between the intermediate reference voltage and the low reference voltage.. .
Analog Devices Technology
01/29/15
20150028404
new patent

Semiconductor device with isolation insulating layer containing air gap


A semiconductor device having a solid-state image sensor which can prevent inter-pixel crosstalk more reliably. The device includes: a semiconductor substrate having a main surface; a first conductivity type impurity layer located over the main surface of the substrate; a photoelectric transducer including a first conductivity type impurity region and a second conductivity type impurity region which are joined to each other over the first conductivity type impurity layer; and transistors which configure a unit pixel including the photoelectric transducer and are electrically coupled to the photoelectric transducer.
Renesas Electronics Corporation
01/29/15
20150028384
new patent

Gan transistors with polysilicon layers for creating additional components


A gan transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The gan device includes an epi structure and an insulating material disposed over epi structure.
Efficient Power Conversion Corporation
01/29/15
20150028346
new patent

Aluminum nitride based semiconductor devices


Semiconductor structures and techniques are described which enable forming aluminum nitride (ain) based devices by confining carriers in a region of ain by exploiting the polar nature of ain materials. Embodiments of ain transistors utilizing polarization-based carrier confinement are described..
Massachusetts Institute Of Technology
01/29/15
20150028339
new patent

Semiconductor device, display device, and electronic device


A semiconductor device including: one or more pieces of first wiring having a main wiring section and a bifurcation wiring section; one or a plurality of pieces of second wiring having a trunk wiring section and a plurality of branch wiring sections within a gap region between the main wiring section and the bifurcation wiring section; one or a plurality of transistors each divided and formed into a plurality of pieces, the plurality of branch wiring sections individually functioning as a gate electrode and the one or plurality of transistors having a source region formed within the main wiring section and within the bifurcation wiring section and having a drain region formed between the plurality of branch wiring sections; and one or a plurality of pieces of third wiring electrically connected to the drain region of the one or plurality of transistors.. .
C/o Japan Display West Inc.
01/29/15
20150028328
new patent

Display device


A non-breakable display device, electronic appliance, or lighting device is provided. A bendable display device in which a first flexible substrate and a second flexible substrate provided with transistors overlap each other with a bonding layer therebetween is fabricated.
Semiconductor Energy Laboratory Co., Ltd.
01/29/15
20150028309
new patent

Light-emitting element display device


A light-emitting element display device includes: a thin film transistor substrate including transistors respectively controlling the amounts of light emission of a plurality of sub-pixels arranged in a display region; and a color filter substrate arranged to overlap with the thin film transistor substrate. The thin film transistor substrate includes a light-emitting organic layer covering the entire display region and emitting light in respective light-emitting regions in the plurality of sub-pixels, an insulating bank formed of an insulating material around each of the light-emitting regions, including an inclined surface being closer to the color filter substrate according to increasing in thickness with increasing distance from the light-emitting region, and a fluorescent layer formed on the inclined surface and excited by light of the light-emitting region to thereby emit light..
Japan Display Inc.
01/29/15
20150028278
new patent

Nonvolatile memory transistor and device including the same


Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element.
01/22/15
20150024577

Semiconductor device and manufacturing semiconductor device


A manufacturing method of a semiconductor device in which the threshold is corrected is provided. In a semiconductor device including a plurality of transistors each includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more.
Semiconductor Energy Laboratory Co., Ltd.
01/22/15
20150024570

Scaling of bipolar transistors


Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor..
International Business Machines Corporation
01/22/15
20150024567

Defect reduction for formation of epitaxial layer in source and drain regions


The embodiments of mechanisms for forming source/drain (s/d) regions of field effect transistors (fets) described enable forming an epitaxially grown silicon-containing layer with reduced number of particles on surface of recesses. The described mechanisms also reduce the effect of the residual particles on the epitaxial growth.
Taiwan Semiconductor Manufacturing Company, Ltd.
01/22/15
20150023121

Memory refresh methods, memory section control circuits, and apparatuses


Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits.
Micron Technology, Inc.
01/22/15
20150023106

Adaptive erase recovery for non-volatile memory (nvm) systems


Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (nvm) cells within nvm systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of nvm block(s) being erased and operating temperature.
01/22/15
20150023105

Memory cell comprising first and second transistors and methods of operating


Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series..
Zeno Semiconductor, Inc.
01/22/15
20150023087

Semiconductor memory


A semiconductor memory includes a memory cell array having a plurality of memory cells, a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array, and a sense amplifiers which are disposed in plurality corresponding to the plurality of bit line pairs for amplifying a potential difference between the bit line pair, in which the sense amplifier has precharging transistors each having a diffusion layer and precharging the bit line pair, and switching transistors having a diffusion layer formed integrally with the diffusion layer of the precharging transistors for selectively connecting the plurality of bit line pairs to a common bus line.. .
Renesas Electronics Corporation
01/22/15
20150023086

Multiport memory cell having improved density area


A mutltiport memory cell having improved density area is disclosed. The memory cell includes a data storing component, a first memory access component coupled to a first side of the data storing component, a second memory access component coupled to a second side of the data storing component, first and second bit lines coupled to the first memory access component, first and second bit lines coupled to the second memory access component, first and second write lines coupled to the first memory access component and first and second write lines coupled to the second memory access component.
Soft Machines, Inc.
01/22/15
20150022923

Driver current control apparatus and methods


Apparatus and methods disclosed herein implement steady-state and fast transient electronic current limiting through power transistors, including power transistors used as pass elements associated with general purpose drivers. Embodiments herein prevent excessive steady-state current flow through one or more driver pass elements and/or through load elements in series with the pass element(s) via a current sensing and driver preamplifier feedback loop.
Texas Instruments Deutschland Gmbh
01/22/15
20150022751

Driving arranging turn-on order of gate lines for liquid crystal display device and related device


A driving method for a liquid crystal display (lcd) device is disclosed. The lcd device includes a plurality of data lines and a plurality of thin film transistors (tfts).
Au Optronics Corp.
01/22/15
20150022491

Touch sensor and methods of making same


The present disclosure relates to a touch sensor and touch sensitive display having a plurality of first and second conductive lines arranged substantially orthogonally with a sensing material to sense a change in capacitance between them. The first and second conductive lines and the sensing material defining an array of sensitive transistors..
01/22/15
20150022429

Display device and driving method thereof


A display device is disclosed. In one aspect, the display device includes a display panel including a plurality of pixels, and a data driver including a plurality of data output unit buffers electrically connected to a plurality of data lines electrically connected to the pixels.
Samsung Display Co., Ltd.
01/22/15
20150022428

Shift register circuit


A shift register circuit for driving an oled display panel is provided. The shift register circuit includes a plurality of circuit stages connected in series.
Au Optronics Corp.
01/22/15
20150022282

Semiconductor device and adjusting impedance of output circuit


An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal.
Micron Technology, Inc.
01/22/15
20150022266

Folded cascode amplifier


Exemplary embodiments are directed to systems, devices, and methods for enhancing an amplifier. An amplifier may include a first cascode circuit including a first transistor and a second transistor.
Qualcomm Incorporated
01/22/15
20150022264

Sense amplifier offset voltage reduction


A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier.
Qualcomm Incorporated
01/22/15
20150022256

Radio-frequency switches having gate bias and frequency-tuned body bias


Radio-frequency (rf) switch circuits are disclosed providing improved switching performance. An rf switch system includes a plurality of field-effect transistors (fets) connected in series between first and second nodes, each fet having a gate and a body.
Skyworks Solutions, Inc.
01/22/15
20150022245

Parallel transistor circuit controller


A method for controlling a circuit control system. Currents are sensed at outputs of transistors in the circuit control system.
The Boeing Company
01/22/15
20150022211

Detection circuit for display panel


The present disclosure provides a detection circuit for a display panel, comprising: a shorting bar, with connection lines for introducing a test signal or a control signal arranged thereon; a transistor array, the gates of which are connected to the connection lines for introducing the control signal, wherein the connection lines for introducing the test signal are connected with the data lines or the scanning lines of the display panel via the sources and the drains of transistors, under the control signal, and a component, arranged between the gates of the transistor array and the shorting bar, for further reducing or increasing a voltage or current of the gates so that the transistor array can be cut off reliably when the control signal is a signal enabling the transistor array to be cut off. The detection circuit can further reduce the channel length of the thus being advantageous for the design of the narrow frame..
Shenzhen China Star Optoelectronics Technology Co., Ltd.
01/22/15
20150021738

Bipolar junction transistors with an air gap in the shallow trench isolation


Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate.
International Business Machines Corporation
01/22/15
20150021704

Finfet work function metal formation


An improved method and structure for fabrication of replacement metal gate (rmg) field effect transistors is disclosed. P-type field effect transistor (pfet) gate cavities are protected while n work function metals are deposited in n-type field effect transistor (nfet) gate cavities..
Globalfoundries Inc.
01/22/15
20150021699

Fin field effect transistors having multiple threshold voltages


A high dielectric constant (high-k) gate dielectric layer is formed on semiconductor fins including one or more semiconductor materials. A patterned diffusion barrier metallic nitride layer is formed to overlie at least one channel, while not overlying at least another channel.
International Business Machines Corporation
01/22/15
20150021698

Intrinsic channel planar field effect transistors having multiple threshold voltages


Intrinsic channels one or more intrinsic semiconductor materials are provided in a semiconductor substrate. A high dielectric constant (high-k) gate dielectric layer is formed on the intrinsic channels.
International Business Machines Corporation
01/22/15
20150021695

Epitaxial block layer for a fin field effect transistor device


Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (finfets) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of finfets; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate..
Globalfoundries Inc.
01/22/15
20150021693

Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer


When forming transistors with deuterium enhanced gate dielectrics and strained channel regions, the manufacturing processes of strain-inducing dielectric material layers formed above the transistors may be employed to efficiently introduce and diffuse the deuterium to the gate dielectrics. The incorporation of deuterium into the strain-inducing dielectric material layers may be accomplished on the basis of a deposition process in which deuterium is present in the process environment during deposition.
Globalfoundries Inc.
01/22/15
20150021687

Semiconductor structure and forming the semiconductor structure with deep trench isolation structures


The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation structures laterally surround the transistors in the array.
Texas Instruments Incorporated
01/22/15
20150021614

Controlled on and off time scheme for monolithic cascoded power transistors


A semiconductor device includes a depletion mode gan fet cascoded with an enhancement mode nmos transistor. A gate of the gan fet is electrically coupled to a source of the nmos transistor through a gate network.
Texas Instruments Incorporated
01/22/15
20150021609

Semiconductor apparatus with multiple tiers, and methods


Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors.
Micron Technology, Inc.
01/22/15
20150021595

Electro static discharge protection circuit and electronic device having the same


An electro static discharge (esd) protection circuit including a signal transmission line coupled to an external input terminal, the esd protection circuit including: a first power line coupled to a high voltage power supply; a second power line coupled to a low voltage power supply; a plurality of first oxide thin film transistors coupled in parallel between the first power line and the signal transmission line, the first oxide thin film transistors being diode-connected; and a plurality of second oxide thin film transistors coupled in parallel between the signal transmission line and the second power line, the second oxide thin film transistors being diode-connected.. .
Samsung Display Co., Ltd.
01/15/15
20150017767

Method for producing a semiconductor device having sgts


In a method for producing a semiconductor device, si pillars that include i-layers, n+ regions that serve as lower impurity regions, n+ regions and a p+ region that serve as upper impurity regions, and i-layers are formed by using sio2 layers as an etching mask. Thus, surrounding gate mos transistors (sgts) are produced in which the upper impurity regions and the lower impurity regions respectively function as impurity layers constituting a source or a drain of the sgts formed in upper portions and lower portions of the si pillars..
Unisantis Electronics Singapore Pte. Ltd.
01/15/15
20150017762

Display device and manufacturing the same


An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor.
Semiconductor Energy Laboratory Co., Ltd.
01/15/15
20150017746

Methods of forming a semiconductor device


A method of forming a semiconductor device includes forming a first transistor and a second transistor on a substrate, monitoring processes of forming the first and second transistors to find an error and performing an additional ion implantation process to form a low-concentration dopant region or a halo region on the first transistor or the second transistor corresponding to a found error.. .
Samsung Electronics Co., Ltd.
01/15/15
20150017743

Memory devices and methods of fabricating the same


Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages..
Samsung Electronics Co., Ltd.
01/15/15
20150016770

Three-dimensional electronic photonic integrated circuit fabrication process


A device and the process for creating a three-dimensional electronic photonic circuit is disclosed. The process includes fabricating a standard high performance integrated circuit on a high resistivity silicon or a silicon-on-insulator substrate up to and including the passivation layer on top of transistors.
Bae Systems Information & Electronics Systems Integration Inc.
01/15/15
20150016585

Semiconductor device


A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor.
Semiconductor Energy Laboratory Co., Ltd.
01/15/15
20150016183

Sense amplifier with transistor threshold compensation


One embodiment provides, in a sense amplifier for an electronic memory array in which a selected memory cell drives a developing voltage differential according to a logic state of the memory cell, a method to store the logic state. The method includes poising source voltages of first and second transistors at levels offset, respectively, by threshold voltages of the first and second transistors.
Nvidia Corporation
01/15/15
20150016176

Memory storage circuit and driving memory storage circuit


A memory storage circuit includes a volatile memory portion, a control portion, and a non-volatile memory portion. The volatile memory portion includes a first node and a second node to store a pair of complementary logic data.
Industrial Technology Research Institute
01/15/15
20150016004

Over-current protection circuit


A circuit protecting the components of a power circuit against passing an over-current is connected to an enable terminal of a pulse width modulation (pwm) controller of a power supply circuit on a motherboard, protecting the field effect transistors (fets) of a first power circuit of the power supply circuit. The protecting circuit includes a first protection circuit.
Hon Hai Precision Industry Co., Ltd.


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Transistors topics: Transistors, Semiconductor, Semiconductor Device, Integrated Circuit, High Speed, Photodiode, Memory Effect, Silicon Nitride, Enhancement, Ion Implant, Ion Channel, Interrupted, Reference Voltage, Semiconductor Devices, Semiconductor Substrate

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