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 Solid-state imaging device and  driving solid-state imaging  device patent thumbnailnew patent Solid-state imaging device and driving solid-state imaging device
A solid-state imaging device includes a pixel including a photoelectric conversion element, an accumulation unit accumulating charges generated by the photoelectric conversion element, a reset unit resetting the accumulation unit at a voltage of equal to or more than 4.05 v, and an amplifier transistor amplifying and outputting a signal corresponding to amount of accumulated charges, a vertical output line connected to the pixel, a current source circuit including first to third transistors flowing a constant current through the vertical output line, and a voltage setting circuit respectively setting the gate voltages of the first to third transistors to a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage and lower than the power supply voltage so as to set the drain-source voltage of each of the first to third transistors to equal to or less than 1.75 v.. .
Canon Kabushiki Kaisha


 Dynamic impedance control for input/output buffers patent thumbnailnew patent Dynamic impedance control for input/output buffers
A system and method of performing off chip drive (ocd) and on-die termination (odt) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions.
Conversant Intellectual Property Management Inc.


 Driver for normally on iii-nitride transistors to get normally-off functionality patent thumbnailnew patent Driver for normally on iii-nitride transistors to get normally-off functionality
A semiconductor device includes a depletion mode gan fet and an integrated driver/cascode ic. The integrated driver/cascode ic includes an enhancement mode cascoded nmos transistor which is connected in series to a source node of the gan fet.
Texas Instruments Incorporated


 Semiconductor switch patent thumbnailnew patent Semiconductor switch
In an embodiment, semiconductor switch includes first switches switching conduction between input-output nodes and a common node. One of the first switches includes a plurality of first transistors connected in series between an input and output node and the common node.
Kabushiki Kaisha Toshiba


 Dead time control patent thumbnailnew patent Dead time control
Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors.
Peregrine Semiconductor Corporation


 Level shifter patent thumbnailnew patent Level shifter
Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors.
Peregrine Semiconductor Corporation


 Power device patent thumbnailnew patent Power device
An energy efficient apparatus includes a switching device, a frequency dependent reactive device, and a control element is provided. The switching device is coupled to a source of electrical power and includes a pair of transistors and is adapted to receive a control signal and to produce an alternating current power signal.
Advanced Charging Technologies, Llc


 Power conversion circuit system patent thumbnailnew patent Power conversion circuit system
The present invention provides a power conversion circuit system in which a circulating current can be reduced by accurately detecting the circulating current, to thereby improve efficiency in power conversion. The power conversion circuit system includes a power conversion circuit composed of a primary conversion circuit having left and right arms and a secondary conversion circuit having left and right arms, and a control circuit for controlling switching of switching transistors in the primary and secondary conversion circuits.
Toyota Jidosha Kabushiki Kaisha


 Hybrid organic/inorganic eutectic solar cell patent thumbnailnew patent Hybrid organic/inorganic eutectic solar cell
A semiconductor assembly including substantially non-crystalline substrate having a predetermined softening point, a textured buffer layer deposited on said substrate, a polymer film deposited on said buffer layer, and an inorganic or silicon inorganic film deposited on said polymer film. The buffer layer, polymer film, and inorganic or silicon inorganic film are each deposited at a respective deposition temperature that is below the softening point of the substrate.
Solar-tectic Llc


 Semiconductor device patent thumbnailnew patent Semiconductor device
One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Forming highly conductive source/drain contacts in iii-nitride transistors


In one embodiment, a method for fabricating a iii-nitride transistor on a iii-nitride semiconductor body is disclosed. The method comprises etching dielectric trenches in a field dielectric overlying gate, source, and drain regions of the iii-nitride semiconductor body, and thereafter forming a gate dielectric over the gate, source and drain regions.
Infineon Technologies Americas Corp.


new patent

Process for producing, from an soi and in particular an fdsoi type substrate, transistors having gate oxides of different thicknesses, and corresponding integrated circuit


An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate.
Stmicroelectronics (crolles 2) Sas


new patent

Heterogeneous pocket for tunneling field effect transistors (tfets)


Embodiments of the disclosure described herein comprise a tunneling field effect transistor (tfet) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to in crease a current through the tfet transistor when a voltage applied to the gate is above a threshold voltage..
Intel Corporation


new patent

Output capacitance reduction in power transistors


Technologies are described for reduction of an output capacitance of a transistor. In some examples, spacing of source-to-drain metallization may be increased and a sealed air-gap may be employed in an elongated trench in the drain region to reduce a dielectric constant of a portion of the body region and thereby the output capacitance of the transistor.
Empire Technology Development Llc


new patent

Field effect transistors and methods of forming same


Semiconductor devices and methods of forming the same are provided. A template layer is formed on a substrate, the template layer having a recess therein.
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Organic light-emitting display apparatus including a shield layer and manufacturing the same


An organic light-emitting display apparatus including a shield layer and a method of manufacturing the same are provided. The organic light-emitting display apparatus includes a substrate having a display area and a peripheral area surrounding the display area.
Samsung Display Co., Ltd.


new patent

Semiconductor device including memory cell array and power supply region


A semiconductor device having an sram which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions..
Renesas Electronics Corporation


new patent

Field-effect transistors having transition metal dichalcogenide channels and methods of manufacture


A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins.
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Transistors patterned with electrostatic discharge protection and methods of fabrication


High-voltage semiconductor devices with electrostatic discharge (esd) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first s/d contacts and a plurality of second s/d contacts associated with the common gate(s).
Globalfoundries Inc.


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new patent

Semiconductor device


A semiconductor device includes a first memory block and a second memory block in a cell region and a first transistor and a second transistor, respectively corresponding to the first and second memory blocks, in a pass transistor region located below the cell region, wherein each of the first and second transistors includes: a first gate electrode coupled to the first memory block and a second gate electrode coupled to the second memory block.. .
Sk Hynix Inc.


new patent

Metathesis polymers as dielectrics


Oxacycloolefinic polymers as typically obtained by metathesis polymerization using ru-catalysts, show good solubility and are well suitable as dielectric material in electronic devices such as capacitors and organic field effect transistors.. .
Basf Se


new patent

Memory refresh methods, memory section control circuits, and apparatuses


Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits.
Micron Technology, Inc.


new patent

Nonvolatile memory devices and storage devices including nonvolatile memory devices


The inventive concepts relate to nonvolatile memory devices. The nonvolatile memory devices may include a memory cell array, and a page buffer circuit connected to the memory cell array through bit lines.
Samsung Electronics Co., Ltd.


new patent

Gate driving circuit and display module


A gate driving circuit for providing a scan signal to a lcd panel is disclosed. The gate driving circuit includes at least one positive level shifter, at least one negative level shifter, a pair of p-type transistor and an n-type transistor.
Sitronix Technology Corp.


new patent

Organic light emitting diode display device and driving method thereof


An oled display device is disclosed which includes: a display panel configured with pixels which each include an organic light emitting diode and a driving transistor applying a driving current to the organic light emitting diode; a gate driver connected to the pixels through gate lines; a data driver configured to apply a sensing voltage to the pixels through data lines in a sensing mode and enable a sensing current to flow through each of the driving transistors; a sensing driver configured to sense threshold voltages opposite the driving currents which flow through the driving transistors; and a brightness compensation circuit configured to derive negatively shifted degrees of threshold voltages of the driving transistors from the sensed threshold voltages, detect a bright-defected pixel on the basis of the negatively shifted degrees, and generate a compensation gray value for the bright-defected pixel.. .
Lg Display Co., Ltd.


new patent

Addressing of groups of transistors in a matrix arrangement


A device comprising an array of transistors; wherein the device comprises an array of first conductors providing either the gate electrodes or the source electrodes for the transistors, and an array of second conductors providing the other of the gate electrodes and the source electrodes for the transistors; wherein the first conductors include conductors that are each associated with a respective group of n rows of the array of transistors; and wherein the columns of transistors include columns of transistors that are associated with a respective set of n second conductors of the array of second conductors, and each second conductor in each set of n second conductors is associated with a respective set of 1/n transistors in the respective column of transistors; wherein n is greater than 1.. .
Flexenable Limited


new patent

Organic light-emitting diode display with pulse-width-modulated brightness control


A display may have an array of pixels arranged in rows and columns. Display driver circuitry may load data into the pixels via data lines that extend along the columns.
Apple Inc.


new patent

Optimizing interconnect designs in low-power integrated circuits (ics)


Aspects disclosed in the detailed description include optimizing interconnect designs in low-power integrated circuits (ics). In this regard, in one aspect, functional blocks having substantially correlated power utilization patterns are grouped into a power-related cluster to share a sleeping cell, thus leading to a reduced number of sleep transistors and a simplified interconnect design in a low-power ic.
Qualcomm Incorporated


new patent

Nonvolatile semiconductor memory device


A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.. .
Kabushiki Kaisha Toshiba


new patent

Pixel structure and liquid crystal panel


A pixel structure and a liquid crystal panel are disclosed. The pixel structure comprises a data line (1), a pixel electrode (3), a gate line (2), and at least two thin film transistors (4, 5) connected in series between the pixel electrode (3) and the data line (1).
Beijing Boe Display Technology Co., Ltd.


new patent

A accumulating and measuring a slowly varying electrical charge


A system for measuring electrical charge, comprising a capacitance detector (110) connected to a charge integrator (120) being an operational amplifier with capacitance (cf) feedback (130), wherein the input stage (121) of the charge integrator (120) comprises a pair of symmetrically connected complementary jfet transistors (t1, t2), the gates of which are connected to the input of the charge integrator (120), characterized in that an n-type transistor (t1) of the complementary pair of transistors (t1,t2) has its drain connected to a voltage regulating system (122).. .
Uniwersyiet Jagiellonski


new patent

Liquid crystal display device


Provided is a liquid crystal display device including first and second opposing substrates, a liquid crystal layer containing a liquid crystal composition between the first and second substrates, thin-film transistors disposed on the first substrate, and pixel electrodes that are driven by the transistors and that are made of a transparent conductive material. Each thin-film transistor includes a gate electrode, an oxide semiconductor layer disposed over the gate electrode with an insulating layer therebetween, and source and drain electrodes electrically connected to the oxide semiconductor layer.
Dic Corporation


new patent

Driving circuit for driving a capacitive load


A drive circuit for driving a capacitive load is provided. The drive circuit includes a modulation circuit that generates a modulated signal by pulse-modulating a source signal through self-oscillation; a pair of transistors that include a high-side transistor and a low-side transistor and amplify the modulated signal to generate an amplified modulated signal; and a low-pass filter that includes a capacitor and smoothes the amplified modulated signal to generate a drive signal which is applied to the capacitive load, wherein the shortest distance between a low-side transistor and the capacitor is shorter than a shortest distance between the high-side transistor and the capacitor..
Seiko Epson Corporation


Solid-state imaging device


A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell includes two pixels.
Sony Corporation


Dual-loop programmable and dividerless clock generator for ultra low power applications


A programmable clock generator is provided which is particularly suitable for low power applications. The programmable clock generator is comprised of: an oscillator circuit that generates an output signal whose frequency is set by a control signal, two feedback loops for controlling output frequency and a loop select that selects which feedback loop is operational at a given time.
The Regents Of The University Of Michigan


Programmable logic device


A pld in which a configuration memory is formed using a nonvolatile memory with a small number of transistors and in which the area of a region where the configuration memory is disposed is reduced is provided. Further, a pld that is easily capable of dynamic reconfiguration and has a short startup time is provided.
Semiconductor Energy Laboratory Co., Ltd.


Compact reram based fpga


A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line.
Microsemi Soc Corporation


Semiconductor switch


A semiconductor switch includes a plurality of metal-oxide-semiconductor field effect transistors (mosfets) and a pad. The mosfets are connected in series between a first node and a second node.
Kabushiki Kaisha Toshiba


Transistors configured for gate overbiasing and circuits therefrom


An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (i/o) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the i/o node.
Qualcomm Incorporated


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High-speed latch circuits by selective use of large gate pitch


An apparatus for storing data includes a latch circuit comprising a first set of transistors that propagate an input signal to an output signal and a second set of transistors that do not propagate the input signal of the latch circuit to the output signal wherein a gate pitch for the first set of transistors is substantially greater than a gate pitch for the second set of transistors. Also disclosed herein, a method for improving circuit performance includes receiving an electronic representation of a plurality of latching circuits associated with a design file and increasing transistor gate pitch for selected transistors of the plurality of latching circuits, wherein the selected transistors comprise transistors that propagate an input signal to an output signal.
International Business Machines Corporation


Power supply circuit and control method thereof


According to one embodiment, a power supply circuit comprises a high-side switch having a plurality of switching transistors connected in parallel and a low-side switch having a plurality of switching transistors connected in parallel. The circuit has a control circuit that causes the high-side switch and the low-side switch to alternately turn on/off.
Kabushiki Kaisha Toshiba


Buck/boost circuit that charges and discharges multi-cell batteries of a power bank device


A power bank device has a single circuit topology involving a dc-to-dc converter and four transistors so that this single topology can be used both to charge battery cells with a regulated current in a charging step-up boost mode and to drive a regulated voltage onto a power bank voltage output node in a discharging step-down buck mode. In one example, the circuit includes a first transistor coupled to conduct current between a battery voltage node and a switch node sw, a second transistor coupled to conduct current between the sw node and a ground node, and third and fourth transistors coupled in series to conduct current between a voltage input node and the voltage output node.
Active-semi, Inc.


Esd protection system, apparatus, and method with adjustable trigger voltage decoupled from dc breakdown voltage


Systems, methods, and apparatus for esd protection with adjustable trigger voltage decoupled from dc breakdown voltage for semiconductor devices including field effect transistors (fets), and particularly to metal-oxide-semiconductors (mosfets) fabricated on silicon-on-insulator (“soi”) and silicon-on-sapphire (“sos”) substrates are described. The apparatus and method are configured to change reverse biased drain junctions which in turn can control the dc breakdown voltage and the trigger voltage..
Peregrine Semiconductor Corporation


Photo-patternable gate dielectrics for ofet


Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors..
Corning Incorporated


Integrated phase change switch


Various methods and devices that involve phase change material (pcm) switches are disclosed. An exemplary integrated circuit comprises an active layer with a plurality of field effect transistor (fet) channels for a plurality of fets.
Qualcomm Switch Corp.


Semiconductor device


To provide a semiconductor device including a transistor in which an oxide semiconductor is used and on-state current is high. In a semiconductor device including a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion, the first transistor and the second transistor have different structures.
Semiconductor Energy Laboratory Co., Ltd.


Source/drain regions for fin field effect transistors and methods of forming same


A method for forming a semiconductor device includes forming a fin extending upwards from a semiconductor substrate and forming a sacrificial layer on sidewalls of a portion of the fin. The method further includes forming a spacer layer over the sacrificial layer and recessing the portion of the fin past a bottom surface of the sacrificial layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


Semiconductor structure including backgate regions and the formation thereof


A semiconductor structure includes a semiconductor substrate, a plurality of transistors and an electrically insulating layer provided between the substrate and the plurality of transistors, and a trench isolation structure including a portion between a first and a second island of the semiconductor structure and extending into the substrate to a first depth. The substrate includes a bottom region having a first type of doping and extending at least to a second depth greater than the first depth, and a deep well region having a second type of doping and extending to a third depth greater than the first depth and smaller than the second depth.
Globalfoundries Inc.


Nonvolatile memory transistor and device including the same


Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element.
Samsung Electronics Co., Ltd.


Techniques for forming contacts to quantum well transistors


Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in iii-v and sige/ge material systems.
Intel Corporation


Thin-substrate double-base high-voltage bipolar transistors


B-tran bipolar power transistor devices and methods, using a drift region which is much thinner than previously proposed double-base bipolar transistors of comparable voltage. This is implemented in a high-bandgap semiconductor material (preferably silicon carbide).
Ideal Power Inc.


Complementary tunneling fet devices and forming the same


Described is an apparatus forming complementary tunneling field effect transistors (tfets) using oxide and/or organic semiconductor material. One type of tfet comprises: a substrate; a doped first region, formed above the substrate, having p-type material selected from a group consisting of group iii-v, iv-iv, and iv of a periodic table; a doped second region, formed above the substrate, having transparent oxide n-type semiconductor material; and a gate stack coupled to the doped first and second regions.
Intel Corporation


Display device


A non-breakable display device, electronic appliance, or lighting device is provided. A bendable display device in which a first flexible substrate and a second flexible substrate provided with transistors overlap each other with a bonding layer therebetween is fabricated.
Semiconductor Energy Laboratory Co., Ltd.


Resistive memory array and fabricating method thereof


The present disclosure provides a method of fabricating a resistive memory array. In one embodiment, a method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure..
Taiwan Semiconductor Manufacturing Co., Ltd.


Semiconductor memory device, semiconductor device, and manufacturing the same


According to one embodiment, a semiconductor memory device includes a plurality of first wirings, second wirings, a plurality of memory cells, selection gate transistors, and a third wiring. The first wirings are disposed in a first direction along a surface of a substrate and in a second direction intersecting with the surface of the substrate.
Kabushiki Kaisha Toshiba


Image sensor with buried-channel drain (bcd) transistors


A charge-coupled device (ccd) image sensor is provided. The ccd image sensor may include an array of photosensors that transfer charge to multiple vertical ccd shift registers, which then in turn transfer the charge to a horizontal ccd shift register.
Semiconductor Components Industries, Llc


Array substrate, manufacturing method thereof and display apparatus


An array substrate, a manufacturing method thereof and a display apparatus are provided. The array substrate includes thin-film transistors (tfts) and conductive electrodes; the tft includes a gate electrode, a source electrode, a drain electrode and an active layer; the source electrode and the drain electrode are arranged in the same layer and at two ends of the active layer and at least directly partially contact the upper surface or the lower surface of the active layer; and the conductive electrode is directly disposed on the electrode.
Boe Technology Group Co., Ltd.


Semiconductor memory device and production method thereof


A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction.
Kabushiki Kaisha Toshiba


Electrostatic discharge protection device


An electrostatic discharge (esd) protection device is disclosed including at least an npn transistor and a pnp transistor coupled between a first node and a second node, wherein the esd protection device may be configured to sink current from the first node to the second node in response to an esd event. The transistors may be coupled such that a collector of the npn may be coupled to the first node.
Sofics Bvba


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Semiconductor device


Provided is a semiconductor device, including: a power element; and a heat sensing element configured to detect a temperature of the power element, in which part of transistors forming the power element are deformed in order that the heat sensing element can accurately detect a temperature of the power element, thereby being capable of arranging the heat sensing element close to a heat generating source.. .
Sii Semiconductor Corporation


Semiconductor device with transistor local interconnects


A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate.
Globalfoundries Inc.


Packaging solutions for devices and systems comprising lateral gan power transistors


Packaging solutions for large area, gan die comprising one or more lateral gan power transistor devices and systems are disclosed. Packaging assemblies comprise an interposer sub-assembly comprising the lateral gan die and a leadframe.
Gan Systems Inc.


Packaging solutions for devices and systems comprising lateral gan power transistors


Packaging solutions for devices and systems comprising lateral gan power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof in the packaging assembly, a gan die, comprising one or more lateral gan power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling.
Gan Systems Inc.


Reducing or eliminating pre-amorphization in transistor manufacture


A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer.
Mie Fujitsu Semiconductor Limited


Semiconductor memory device


A semiconductor memory device includes a plurality of memory cell transistors electrically connected in series, a bit line electrically connected to a first end of the memory cell transistors, a source line and a well region electrically connected to a second end of the memory cell transistors, and first and second selection transistors electrically connected in series between the second end of the memory cell transistors and the source line. During programming of a selected memory cell transistor, a first voltage is applied to the source line and the well region, and to a gate of the first selection transistor, and a second voltage smaller than the first voltage is applied to a gate of the second selection transistor..
Kabushiki Kaisha Toshiba


Semiconductor memory device


A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit line.
Kabushiki Kaisha Toshiba


Semiconductor memory device and memory system


A semiconductor memory device includes: a first string unit including first and second memory cell transistors; a second string unit including third and fourth memory cell transistors; a first word line coupled to gates of the first and third memory cell transistors; and a second word line coupled to gates of the second and fourth memory cell transistors. When the first string unit is selected and the first word line is selected, a first voltage is applied.
Kabushiki Kaisha Toshiba


Method for integrating non-volatile memory cells with static random access memory cells and logic transistors


A method of making a semiconductor device is described. The method comprises depositing a first polysilicon layer in a non-volatile memory (nvm) region and a logic region of a substrate.
Freescale Semiconductor, Inc.


Semiconductor device and driving the same


A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line.
Semiconductor Energy Laboratory Co., Ltd.


Display device


A display device includes an image display area that includes pixels sectioned by scanning signal lines and video signal lines, first scanning connection lines connected to scanning signal lines, first thin film transistors, first selection signal lines, second thin film transistors, second selection signal lines, and a scanning signal drive circuit connected to the first scanning connection lines, the first selection signal lines, and the second selection signal lines, wherein the scanning signal drive circuit sequentially supplies a pulse signal to the first scanning connection lines in a selection period in which a gate-on voltage is applied to the one of the first selection signal lines, and the scanning signal drive circuit applies a gate-off voltage to the one of the second selection signal lines corresponding to the one of the first selection signal lines to which the gate-on voltage is applied.. .
Panasonic Liquid Crystal Display Co., Ltd.


Display device


A display apparatus includes an image display region having pixels sectioned by scanning signal lines and video signal lines, scanning connecting lines, thin film transistors, selection signal lines connected to gate electrodes of the thin film transistors, plural ones of the thin film transistors connected to different ones of the scanning connecting lines being connected to one of the selection signal lines; and a scanning signal drive circuit. The scanning signal drive circuit performs a normal scanning mode in which pulse signals are supplied in turn to plural ones of the scanning connecting lines connected to the one of the selection signal lines, and in the normal scanning mode, a fall timing of the gate-on voltage differs from a fall timing of a last one of the pulse signals supplied to the plural ones of the scanning connecting lines during the selection period..
Panasonic Liquid Crystal Display Co., Ltd.


Gate driver control circuit


A method for operating a gate driver that is driving pixel transistors of a display panel, is described. An internal start pulse is produced in response to an external start pulse and in accordance with a system clock, wherein the internal start pulse is input to a first cell of a gate driver shift register whose outputs are coupled to level shifting output stages that are driving the rows of pixel transistors of the display panel.
Apple Inc.


Pixel driving circuit, driving method, array substrate and display apparatus


A pixel driving circuit and a driving method thereof, and an array substrate are provided. The pixel driving circuit includes a data line (data), a gate line (gate), a first power supply line (elvdd), a second power supply line (elvss), a reference signal line (ref), a light emitting device (d), a driving transistor (t7), a storage capacitor (c1), a reset unit, a data writing unit, a compensating unit and a light emitting control unit.
Boe Technology Group Co., Ltd.


Pixel driving circuit, driving method thereof and display apparatus


There is provide a pixel driving circuit, and the pixel driving circuit comprises a driving transistor(dtft), organic light emitting diode(oled) connected with the driving transistor(dtft), a first to a fourth switch transistors(t1˜t4) and a storage capacitor(cs). There is provide a driving method for the pixel driving circuit, and it comprises charging the storage capacitor(cs); discharging the storage capacitor(cs), so that a voltage difference exists between voltages at two terminals of the storage capacitor(cs); changing the data voltage(vdata), so that the voltages at the two terminals of the storage capacitor(cs) vary as same as variations in the data voltage(vdata); and driving the organic light emitting diode(oled) to emit light.
Beijing Boe Optoelectronics Technology Co., Ltd.


Display device and electronic apparatus


Provided is an active matrix display device using an organic el panel including: a plurality of pixel circuits each including an organic light emitting diode arranged in a pixel region of the organic el panel and a plurality of transistors configured to drive the organic light emitting diode; a plurality of scanning lines arranged along a first direction in the organic el panel; and a plurality of data lines arranged along a second direction that is orthogonal to the first direction. In at least one set of pixel circuits that are adjacent in the first direction, gate electrodes and impurity diffusion regions of the plurality of transistors have an axisymmetric layout.
Seiko Epson Corporation


Pixel circuit for increasing accuracy of current sensing


A pixel circuit for increasing accuracy of current sensing of an organic light-emitting diode (oled) display is disclosed. In one aspect, the pixel circuit includes an oled, a driving circuit, and first to third transistors.
Samsung Display Co., Ltd.


Display panel


A display panel is disclosed. In one aspect, the display panel includes a display unit including a plurality of pixels, an inspection circuit configured to apply a first inspection voltage to the display unit based on a first control signal, a pad portion electrically connected to the inspection circuit and configured to supply the first inspection voltage and the first control signal to the inspection circuit, and at least one external inspection line electrically connected between the inspection circuit and the pad portion.
Samsung Display Co., Ltd.


Pixel circuit, display panel and display apparatus


Provided is a pixel circuit, a display panel and a display apparatus. The pixel circuit comprises a pixel compensation module, a light emitting module and a touch detection module; the pixel compensation module comprises first to fifth switch units, a pixel driving unit and an energy storage unit; and the touch detection module comprises a detection sub-module and an output sub-module.
Beijing Boe Optoelectronics Technology Co., Ltd.


Integrated circuit with transistor array and layout method thereof


A current mirror circuit includes a first current mirror leg and a second current mirror leg. The first current mirror leg is configured with n stages of first transistors coupled in series and with their respective gates tied together.
Taiwan Semiconductor Manufacturing Co., Ltd.


Display device


To reduce the area of a portion where a plurality of transistors are provided in a region around a display region and to reduce the area of the region around the display region, a display device includes a first transistor and a second transistor each as a transistor, and the transistor includes a connection wiring that electrically connects a semiconductor film and a source-drain electrode to each other via an opening portion provided in an insulating film. The first transistor and the second transistor are adjacent to each other, and there is a clearance between an end portion, on the side of the second transistor, of the connection wiring in the first transistor and an end portion, on the side of the second transistor, of the opening portion in the first transistor..
Japan Display Inc.


Semiconductor device


When normal operation is detected by a self-interruption signal source and a first transistor is on, if an on-signal is inputted to an in terminal, a second transistor is turned on and a third transistor is turned off. Accordingly, an igbt is turned on.
Fuji Electric Co., Ltd.


D/a conversion circuit


A d/a converter is configured to output tri-level potentials from an output terminal. A high potential terminal and the output terminal are connected through a p-type mos transistor.
Denso Corporation


Three input comparator


A three input voltage comparator provides termination of a pulse width modulation (pwm) output in a switched mode power supply. Shutdown of the pwm signal occurs when a sense current from the switching transistors exceeds either or both of the limit and error current references.
Microchip Technology Incorporated


Current sensing using capacitor voltage ripple in hybrid capacitor/inductor power converters


A dc-to-dc power converter includes a power stage, an output stage and a ripple magnitude detector. The power stage includes a plurality of transistors, an energy transfer capacitor coupled between at least two of the transistors, and a switch node.
Texas Instruments Incorporated


Ge energy power conversion technology ltd


A switch module includes a collector connection, an emitter connection, and a gate connection. The switch module includes a plurality of parallel connected switching elements, e.g., insulated-gate bipolar transistors, each having a collector electrode electrically connected to the collector connection, an emitter electrode electrically connected to the emitter connection, and a gate electrode electrically connected to the gate connection.
Ge Energy Power Conversion Technology Ltd


Method of manufacturing an integrated circuit having field effect transistors including a peak in a body dopant concentration


An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first fet and a second fet.
Infineon Technologies Ag


Fin field-effct transistors


A method for fabricating fin field-effect transistors includes providing a semiconductor substrate; and forming a plurality of fins on a surface of the semiconductor substrate. The method also includes forming dummy gates formed over side and top surfaces of the fins; forming a precursor material layer with a surface higher than top surfaces of the fins to cover the dummy gates and the semiconductor substrate; performing a thermal annealing process to convert the precursor material layer into a dielectric layer having a plurality of voids; and planarizing the dielectric layer to expose the top surfaces of the dummy gates.
Semiconductor Manufacturing International (shanghai) Corporation


Die including a high voltage capacitor


According to an embodiment of the invention there may be provided a die that may include a first capacitor layer that comprises (a) a first capacitor conductive plate, and (b) a first capacitor layer dielectric material that partially surrounds the first capacitor conductive plate; a first conductor; an intermediate metal layer that comprises (a) an intermediate metal layer conductor that is made of copper, and (b) an intermediate metal layer dielectric material that partially surrounds the intermediate metal layer conductor; wherein the first conductor is positioned between a substrate of the die and the intermediate metal layer; a redistribution layer that comprises (a) a redistribution layer conductor that is electrically coupled to an interface pad of the die, (b) a second capacitor conductive plate, and (c) a redistribution layer dielectric material that partially surrounds the redistribution layer conductor and the second capacitor conductive plate; wherein a certain portion of the intermediate metal layer dielectric material is positioned between the first and second capacitor conductive plates; wherein at least the certain portion of the intermediate metal layer dielectric material, the first capacitor conductive plate and the second capacitor conductive plate form a high voltage capacitor; and wherein the intermediate metal layer conductor is configured to supply power to a group of transistors of the die while the first conductor is configured to supply power only to a sub-group of the transistors of the die.. .
Tower Semiconductor Ltd.


A display panel


A display panel which can avoid rc delay is provided. The display panel comprises photosensitive transistors, data lines electrically connected with source electrodes of the photosensitive transistors, first electrodes electrically connected with drain electrodes of the photosensitive transistors, and light emitting diodes, wherein the photosensitive transistors are arranged in rows the direction of which is perpendicular to the extension direction of the data lines, and the light emitting diodes are arranged in rows, each row of light emitting diodes are arranged along the direction perpendicular to the extension direction of the data lines, and are used for simultaneously turning on all of the photosensitive transistors in a corresponding row..
Beijing Boe Display Technology Co., Ltd.


Semiconductor device and manufacturing semiconductor device


According to one embodiment, a semiconductor device includes a pair of selection gate transistors arranged on a semiconductor layer, and memory cell transistors arranged on the semiconductor layer between the pair of selection gate transistors. The memory cell transistors are connected to each other in series such that every two adjacent ones of the memory cell transistors share a source/drain region.
Kabushiki Kaisha Toshiba


Cmos compatible resonant interband tunneling cell


A semiconductor device includes a first diode connected transistor of a first conductivity type and a second diode connected transistor of a second conductivity type connected in series, each of the first and second diode connected transistors being configured to exhibit negative differential resistance in response to an applied voltage. The first drain and first source regions of the first diode connected transistor include dopants of the first conductivity type at degenerate dopant concentration levels and a gate of the first diode connected transistor has a work function that corresponds to that of the semiconductor containing dopants of the second conductivity type.

Sram memory cell and sram memory


Various embodiments provide semiconductor structures and their fabrication methods. An sram memory cell can include at least one semiconductor structure, and an sram memory can include at least one sram memory cell.
Semiconductor Manufacturing International Corp.


Stacked half-bridge package


According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver ic. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver ic.
Infineon Technologies Americas Corp.


Time domain ramp rate control for erase inhibit in flash memory


When performing an erase on a flash type non-volatile memory with a nand type of structure, techniques are presented for inhibiting erase on selected word lines, select lines of programmable select transistors, or some combination of these. The voltage along the selected control lines are initially ramped up by the level on a corresponding input line, but then have their voltage raised to an erase inhibit level by capacitive coupling with the well structure.
Sandisk Technologies, Inc.


Multiport memory cell having improved density area


A multiport memory cell having improved density area is disclosed. The memory cell includes a data storing component, a first memory access component coupled to a first side of the data storing component, a second memory access component coupled to a second side of the data storing component, first and second bit lines coupled to the first memory access component, first and second bit lines coupled to the second memory access component, first and second write lines coupled to the first memory access component and first and second write lines coupled to the second memory access component.
Soft Machines, Inc.


Improved sram storage unit based on dice structure


The present invention provides an improved sram memory cell based on a dice structure, which comprises following structures: four inverter structures formed through arranging pmos transistors and nmos transistors in series, wherein the part between the drains of a pmos transistor and an nmos transistor serves as a storage node; each storage node controls the gate voltage of an nmos transistor of the other inverter structure and of a pmos transistor of another inverter structure; a transmission structure consisting of four nmos transistors, whose source, gate and drain are respectively connected with a bit line/bit bar line, a word line and a storage node. The use of an improved sram memory cell based on a dice structure not only avoids such defects as small static noise margin and being prone to transmission error facing the traditional cell structures consisting of 6 transistors, but also resolves the problem that the current sram storage cells based on a dice structure can easily be affected by the electrical level of storage nodes.
Institute Of Microelectronics, Chinese Academy Of Sciences


Electronic circuit, scanning circuit, display device, and electronic circuit life extending method


To provide an electronic circuit and the like capable of extending the life greatly even when the transistors constituting the electronic circuit have property fluctuation. The electronic circuit includes switching-target circuits and a switching circuit for switching the switching-target circuits to an operating state from a stop state.
Nlt Technologies, Ltd.


Pixel circuit and driving a pixel circuit


A pixel circuit includes a first pixel and a second pixel. The first pixel includes a first transistor to control current to a first light emitter and a second transistor to connect the first light emitter to first reset power.
Samsung Display Co., Ltd.


Memory controlling nonvolatile memory


According to one embodiment, a nonvolatile memory system includes a memory including a first memory and a second memory, the first memory including memory strings, the memory strings including memory cell transistors connected in series; and a memory controller which compresses a failure string position information of the first memory, which stores the compressed failure string position information in the second memory, and which decompresses the compressed failure string position information stored in the second memory.. .
Kabushiki Kaisha Toshiba


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Bipolar junction transistor-based temperature sensors


Temperature sensors using bipolar junction transistors are provided. Examples of the disclosed sensors minimize effects of ir drop and have improved accuracy.
Qualcomm Incorporated


Mid-infrared photodetectors


Nanoparticles, methods of manufacture, devices comprising the nanoparticles, methods of their manufacture, and methods of their use are provided herein. The nanoparticles and devices having photoabsorptions in the range of 1.7 μm to 12 μm and can be used as photoconductors, photodiodes, phototransistors, charge-coupled devices (ccd), luminescent probes, lasers, thermal imagers, night-vision systems, and/or photodetectors..
The University Of Chicago


Precursors and methods for atomic layer deposition of transition metal oxides


Methods are provided herein for forming transition metal oxide thin films, preferably group ivb metal oxide thin films, by atomic layer deposition. The metal oxide thin films can be deposited at high temperatures using metalorganic reactants.
Asm International N.v.




Transistors topics:
  • Transistors
  • Semiconductor
  • Semiconductor Device
  • Integrated Circuit
  • High Speed
  • Photodiode
  • Memory Effect
  • Silicon Nitride
  • Enhancement
  • Ion Implant
  • Ion Channel
  • Interrupted
  • Reference Voltage
  • Semiconductor Devices
  • Semiconductor Substrate


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