|| List of recent State Machine-related patents
| Methods and systems to detect an evasion attack|
A method and system to detect an evasion attack are provided. The system may include a repository to store signature fragments that together constitute an attack signature, an interceptor to intercept a data packet associated with a network connection, a string-matching module to determine whether the payload of the data packet includes any of the stored signature fragments thereby identifying a match, a responder to perform a prevention action in response to the match, and a detector to detect that a size of the data packet is less than a size threshold.
| Methods and circuits for disrupting integrated circuit function|
Methods and circuits for disrupting integrated circuit function. The circuits include finite state machines connected to memory arrays.
| Transmission filtering processor architecture|
A processor for filtering message traffic between communication systems may include an input buffer storing an input message and an output buffer. The processor may also include a memory interface communicatively coupled to a filter rule table that includes message filter rules for verifying input messages received by the input buffer and build output message rules for constructing output messages based on the input messages received by the input buffer.
|Dual or multiple sim standby and active using a single digital baseband|
An apparatus comprises two or more sim card connectors in a communication system configured to operate according to a plurality of communication protocols and coupled to at least one processor (610) for processing communication signals, a control unit (632) configured to generate a control signal to select a communication path (629-1, 629-2, 631-1, 631-2, 645-1, 647-1, 647-2) dedicated to an associated sim card connector, and a switch (630) responsive to the control signal to switch the communication signals received from or transmitted to any one of the two or more sim card connectors using the selected communication path. An apparatus comprises a plurality of radio frequency integrated circuit rfics (640-1, 640-2) coupled to a plurality of rf interfaces of a digital baseband (600) of a communication apparatus, the plurality of rfics includes a programmable state machine that executes programmed instructions to perform write to the rfics, thereby enabling rf control..
|Virtual link aggregation using state machine|
Physical links between an access switch and a pair aggregation switches are aggregated into a virtual link aggregation group (vlag). Each aggregation switch is a local switch to itself and a remote switch to the other aggregation switch.
|Instruction for fast zuc algorithm processing|
Vector instructions for performing zuc stream cipher operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first vector instruction to perform an update to a liner feedback shift register (lfsr), and receives a second vector instruction to perform an update to a state of a finite state machine (fsm), where the fsm receives inputs from re-ordered bits of the lfsr.
|Instruction for accelerating snow 3g wireless security algorithm|
Vector instructions for performing snow 3g wireless security operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first operand of the first instruction specifying a first vector register that stores a current state of a finite state machine (fsm).
|Single wire serial interface master module and method thereof for sampling data information|
The present invention discloses a single wire serial interface (ssi) master module, including: a sample delay controlling unit, configured to send a delay instruction; the state machine unit, configured to wait, according to the delay instruction, for a delay period starting from a moment when an ssi master module completes sending the last bit of address information in a read operation frame, and then send a sample control signal to a selector unit; the selector unit, configured to enable a transmission channel with a sampling unit after receiving the sample control signal; and the sampling unit, configured to sample data information from an ssi slave module. In the present invention, the state machine unit delays sending the sample control signal, and the sampling unit is controlled to delay sampling the data information, which avoids a data reception error caused by slow discharging of an io pad..
|Methods and systems of using boosted decision stumps and joint feature selection and culling algorithms for the efficient classification of mobile device behaviors|
Methods and systems for classifying mobile device behavior include configuring a server use a large corpus of mobile device behaviors to generate a full classifier model that includes a finite state machine suitable for conversion into boosted decision stumps and/or which describes all or many of the features relevant to determining whether a mobile device behavior is benign or contributing to the mobile device's degradation over time. A mobile device may receive the full classifier model and use the model to generate a full set of boosted decision stumps from which a more focused or lean classifier model is generated by culling the full set to a subset suitable for efficiently determining whether mobile device behavior are benign.
|Facility for message-based conversations|
A method and associated apparatus for maintaining the state of a message conversation across separate message exchanges to/from a wireless device includes receiving a message m1 from a wireless device in connection with a message conversation, ascertaining, from message m1, a key, based on the key, obtaining through a repository (a) the identity of a finite state machine (fsm) and (b) a plurality of attributes for the fsm including a current state of the fsm, based on the current state of the fsm, and the definition of the fsm, determining (a) a next state of the fsm and (b) an action corresponding to the next state of the fsm, performing the action corresponding to the next state of the fsm; and sending a message m2 to the wireless device, wherein message m2 is configured to further the message conversation.. .
|Lock state machine operations upon stp data captures and shifts|
Operating a state machine includes enabling operation of the state machine upon receiving a signal indicating a change from operation of a test access port to a scan test port. The process maintains the state machine in an idle 1 state while receiving a scan test port capture signal and transitions the state machine to an idle 2 state when receiving a scan test port shift signal.
|System and method for multi-modality workflow management using hierarchical state machines|
A multi-modality medical system having a computing system communicatively coupled to a medical instrument is provided. An acquisition control activity module is configured to control acquisition of medical data from a patient with the medical instrument and a business logic state machine having a first data acquisition state and a first data review state and being operable to utilize the acquisition control activity module to control acquisition of medical data from the patient with the medical instrument while in the first data acquisition state, and being configured to convert the medical data into images representative of portions of the patient while in the first data acquisition state.
|Protocol for allocating upstream slots over a link in a point-to-multipoint communication system|
A system for controlling a contention state for a communication link between a base station controller and customer premises equipment in point-to-multipoint communication. The contention state is controlled using a state machine, which includes a grant pending absent state in which a unicast request slot is maintained open for use by the customer premises equipment.
|High speed digital transient waveform detection system and method for use in an intelligent electronic device|
A system and a method is provided for the detection and capture, and in particular for an ultra high speed detection and capture, of transients in input voltages by an intelligent electronic device. The system and method detects transients for input voltages in either phase to phase or phase to neutral measurements and permits a user to set threshold levels for detecting transients in input voltages.
|Method and system to view and analyze state model transition on host/semiconductor equipment for 300mm standards|
The embodiments herein disclose a method and system to view and analyze state model transition on host/equipment for 300 mm standards. A state transition module is developed for effectively viewing and analyzing state model transition occurring on the host/equipment using 300 mm standards.
|Validating operation of system-on-chip controller for storage device using programmable state machine|
A system-on-chip includes a storage controller, a read channel integrated circuit, a programmable state machine controller, a switching circuit, a buffer memory, and an interface to access the buffer memory. The switching circuit connects the storage controller or the programmable state machine controller to the read channel integrated circuit.
|Adaptive private network with geographically redundant network control nodes|
Systems and techniques are described which improve performance, reliability, and predictability of networks. Geographically diverse network control nodes (ncns) are provided in an adaptive private network (apn) to provide backup ncn operations in the event of a failure.
|Interfacing dynamic hardware power managed blocks and software power managed blocks|
A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (ic) may include a number of power manageable functional units.
|Apparatus, system, and method for enhanced reporting and processing of network data|
An apparatus includes microcode controlled state machines, data reduction logic, and push logic. At least one of the microcode controlled state machines is configured to generate first statistical data measured over time intervals of a first time granularity based on network data included in each of multiple data flows traversing the at least one of the microcode controlled state machines.
|Managing states of location determination|
A mobile device can be in multiple states of location determination. In each state, the mobile device can use a distinct subsystem to determine a location.
|Offload processing interface|
Disclosed are various embodiments providing offload processing circuitry of a network switch. The offload processing circuitry receives an administrative packet from a network switch, the offload processing circuitry being communicatively coupled to a network switch via an ethernet interface.
|Methods and systems to traverse graph-based networks|
Methods and systems to translate input labels of arcs of a network, corresponding to a sequence of states of the network, to a list of output grammar elements of the arcs, corresponding to a sequence of grammar elements. The network may include a plurality of speech recognition models combined with a weighted finite state machine transducer (wfst).
|Tractor communication/control and select fire perforating switch simulations|
Apparatus and methods for controlling and communicating with one or more tools in a downhole tool string including a tractor, an auxiliary tractor tool, a logging tool, a safety sub, a release mechanism, a unit containing sensors for monitoring downhole conditions, a setting tool, and a perforating gun. Control and communication are accomplished by sending signals from the surface to control switches in the control units on the tool, with redundant switches for safety, to state machines in the respective control units, each state machine returning a signal verifying switch status to the surface.
|Digital second-order cdr circuits|
A method for performing a clock and data recovery includes providing data and a clock; determining early/late values of the data to generate a first-order phase code using the data and the clock; and accumulating first-order phase codes retrieved from different finite state machine (fsm) cycles to generate a second-order phase code. A plurality of candidate total phase codes is generated from the second-order phase code.
|System and method for robust personalization of speech recognition|
Personalization of speech recognition while maintaining privacy of user data is achieved by transmitting data associated with received speech to a speech recognition service and receiving a result from the speech recognition service. The speech recognition service result is generated from a general purpose speech language model.
|Integrated approach for visual dialing|
A business can register a finite state machine with a server. This finite state machine can express a tree structure of menus.
|Optical link handshake techniques and configurations|
Embodiments of the present disclosure provide optical link handshake techniques and configurations. In one embodiment, an optical module includes a laser driver corresponding with a channel of the optical module, a signal detector corresponding with the channel, and a link handshake state machine configured to control the laser driver to generate a connect pulse of a link handshake process to test an optical link between the channel and a corresponding channel of another optical module and monitor the signal detector to detect a connect pulse from the another optical module.
|System and method adopting a reliable stop-and-wait hybird automatic repeat request protocol|
A communication system and a method for transferring data are provided. The method is implemented in a communication system having first and second network devices.
|Receive diversity control in td-scdma|
In a td-scdma user equipment (ue) with multiple receive chains, receive diversity may be implemented where multiple receive chains may simultaneously activate to perform reception on downlink signals. Receive diversity may be enabled when single chain reception provides undesired results and when receive diversity will not impact power consumption too much.
|Semiconductor integrated circuit|
A state machine; a bist circuit including a test pattern generator and an expected value comparison circuit; a state monitoring circuit configured to monitor whether or not a state of the state machine is a specific state; and a transition request detection circuit configured to detect a transition request signal from the specific state to a next state, are held. When the state monitoring circuit decides that the state of the state machine is the specific state, the state machine outputs a signal indicating the specific state as a state output of the state machine, and the bist circuit performs a test of the state machine.
|Speculative tablewalk promotion|
A method includes performing a speculative tablewalk. The method includes performing a tablewalk to determine an address translation for a speculative operation and determining whether the speculative operation has been upgraded to a non-speculative operation concurrently with performing the tablewalk.
|Systems and methods for reducing energy usage|
A system for detecting individual appliance energy loads from a building composite load profile includes an electric meter to capture building composite load profile; a detector coupled to the meter to detect transitions in the load profile to determine an appliance state machine for each appliance; a clusterizer to detect clusters of patterns in the load profile; and an analyzer coupled to the detector to receive the transitions and appliance state machines from the detector, the analyzer matching each transition to a predetermined appliance state machine to disaggregate the building composite load profile into individual appliance energy loads.. .
|Biomimetic controller for increased dexterity prosthesis|
A sliding mode biomimetic (bsm) controller for a prosthetic device, such as a prosthetic hand, includes an input classification component that receives electromyogram (egm) signals from two or more electromyogram (egm) sensors that are positioned on an amputee's body. The input classification component compares the egm input signals based on predetermined activation threshold values and identifies an input class to determine the amputee's intended movement of the prosthetic device.
|Dynamic state machine|
In certain embodiments, a method includes receiving, using one or more processors, a trigger expression. The method may include processing, using the one or more processors, the trigger expression, the trigger expression comprising a first one or more terms comprising a first one or more fields, to generate a reduced trigger expression.
|Semiconductor device and detection method thereof|
A semiconductor device and a detection method thereof are provided. The semiconductor device includes a resistor terminal, a dummy pull up driver, a comparator and a detection state machine.
|Automatic topology extraction and plotting with correlation to real time analytic data|
Systems and methods are disclosed for extracting a topology for an installation of a plurality of software components. The topology may be extracted from instantiating instructions for the components of the installation such as an application manifest, manifest tree, configuration scripts, source code, and the like.
|Distributed on-chip debug triggering|
A method and apparatus for distributed on-chip debug triggering is presented. A first bus includes a plurality of lines and a debugging state machine configurable to monitor the plurality of lines of the first bus.
|Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements|
The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred ic embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network.
|Configurable aircraft data acquisition and/or transmission system|
An aircraft data acquisition and/or transmission system comprises a memory having stored therein a first state machine configuration comprising a first allocation between a plurality of transition criteria objects stored in a first area of the memory and a plurality of state objects stored in a second area of the memory separate from the first area. A processor is coupled to the memory and at least one application executable by the processor causes a first data acquisition and/or transmission behavior in the aircraft by running the first state machine configuration, receives a second state machine configuration comprising a second allocation between the plurality of transition criteria objects and the plurality of state objects, and causes a second data acquisition and/or transmission behavior in the aircraft by running the second state machine configuration..
|Glitchless clock switching that handles stopped clocks|
An integrated circuit receives a first and second clock signal and a select signal that selects one of the clock signals. A glitchless switching circuit supplies an output clock signal according to which of the first and second clocks is selected by the select signal.
|Charger system, digital interface circuit and associated control method|
A charger system with a digital interface circuit, wherein the digital interface circuit has an n-bit control register, wherein n is a positive integer no less than 2, and wherein the n-bit register has a primary state machine, at a first portion of addresses of the control register, configured to instruct operation statuses of a system management bus host; and a secondary state machine, at a second portion of addresses of the control register, configured to instruct a data bit of transmission of a corresponding control instruction under each of the operation statuses of the system management bus host.. .
|State machine control of a debugger|
A debugger utilizes a finite state machine to control when execution of a software application is suspended. The finite state machine uses breakpoints as transitions that move the finite state machine from a start state to an acceptance state.
|Verification support computer product, apparatus, and method|
A non-transitory, computer-readable recording medium stores therein a verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition>the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in the test scenario group.. .
|Finite state machine method for test case generation and execution of communication protocols|
The technology disclosed relates to implementing a novel architecture of a finite state machine (abbreviated fsm) that can be used for testing. In particular, it can be used for testing communications devices and communication protocol behaviors..
|Multi-level run-length limited finite state machine with multi-penalty|
Techniques are described for constructing maximum transition run (mtr) modulation code based upon a multi-level (ml) run-length limited (rll) finite state machine (fsm) that implements different sets of penalties. A processor is configured to receive information from a hard disk drive (hdd) via a read channel and recover data from the hdd using mtr modulation code.
|Counter operation in a state machine lattice|
Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition.
|Monitoring energy consumption in optical access networks|
An optical access network comprises optical network units connected to a node. A monitoring unit determines information indicative of energy consumption at the optical network unit over a period of time.
|Receive diversity control in td-scdma|
In a td-scdma user equipment (ue) with multiple receive chains, receive diversity may be implemented where multiple receive chains may simultaneously activate to receive downlink signals. Receive diversity may be enabled when single chain reception provides undesired results and when receive diversity will not impact power consumption too much.
|Multi-level run-length limited finite state machine for magnetic recording channel|
A system is described for constructing maximum transition run modulation code based upon a multi-level run-length limited finite state machine. A processor is configured to receive information from a hard disk drive via a read channel and recover data from the hard disk drive using maximum transition run modulation code.
|Architected protocol for changing link operating mode|
In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed..
A finite state machine is provided that both serializes virtual gpio signals and deserializes virtual gpio signals responsive to cycles of an external clock. The finite state machine frames the serialized virtual gpio signals into frames each demarcated by a start bit and an end bit..
|On-chip hv and lv capacitors acting as the second back-up supplies for nvsram auto-store operation|
Two on-chip capacitors including one hv capacitor vppcap and one lv vcc capacitor vcccap are built over a nvsram memory chip as a back-up second power supplies for each nvsram cell, regardless of 1-poly, 2-poly, pmos or nmos flash cell structures therein. The on-chip hv and lv capacitors are preferably made from one or more mim or mip layers for achieving required capacitance.
|State machine based parsing algorithm on a data-status fifo with multiple banks|
In the l2 fifo architecture incoming frames are stored in a multi bank fifo to enable offloading the programmable real-time unit to do other tasks. The l2 fifo buffers data coming from the l1 fifo, reducing the polling time for received data.
|Implementing storage adapter performance control|
A method and controller for implementing storage adapter performance control, and a design structure on which the subject controller circuit resides are provided. The controller includes a performance state machine controlling the use of a performance path and a normal or error recovery path in a storage adapter firmware stack.
|Two-wire communication protocol engine|
In an example embodiment, a two-wire communication protocol engine manages control and data transmissions in a bi-directional, multi-node bus system where each node is connected over a twisted wire pair bus to another node. Some embodiments include a state machine that allows for synchronized updates of configuration data across the system, a distributed interrupt system, a synchronization pattern based on data coding used in the system, and data scrambling applied to a portion of the data transmitted over the twisted wire pair bus.
|Method and system for automating the editing of computer files|
The present invention is a method and system for automating repetitive user actions during the text editing operations of various computer files. Computer users may commonly perform some repetitive or patterned actions while editing text files such as scripts, or editing markup files like html or xml, or editing source code or even regular text files that contain tabular data or lists.