|| List of recent State Machine-related patents
| Determining relevant events in source code analysis|
In embodiments of determining relevant events in source code analysis, a computing device includes a key event manager that is implemented to traverse executable paths in source code of executable software instructions, log events along the executable paths in the source code, and determine a defect in the source code along an executable path in the source code. A state machine is implemented to traverse back through the logged events and determine relevant events that are associated with the defect in the source code.
| Instruction insertion in state machine engines|
State machine engines are disclosed, including those having an instruction insertion register. One such instruction insertion register may provide an initialization instruction, such as to prepare a state machine engine for data analysis.
| Results generation for state machine engines|
A state machine engine includes a storage element, such as a (e.g., match) results memory. The storage element is configured to receive a result of an analysis of data.
| Flash memory devices and controlling methods therefor|
A flash memory controller is provided. The flash memory controller includes a read/write unit, a state machine, a processing unit, and a reserve unit.
| Methods and systems for power management in a pattern recognition processing system|
A device includes a state machine. The state machine includes a plurality of blocks, where each of the blocks includes a plurality of rows.
| Cdr circuit and terminal|
Embodiments of the present invention disclose a cdr circuit and a terminal, where the cdr circuit is configured to perform clock synchronization in a terminal with eee function, and the cdr circuit includes: a phase detector, a first phase signal selector, a loop filter, a numerical controlled oscillator, a second phase signal selector, a phase signal generator, and a state machine. In the embodiments of the present invention, after the terminal enters a refresh state from a quiet state, the cdr circuit can implement clock synchronization with a peer end without waiting for the loop filter and the numerical controlled oscillator to be converged, but the phase signal generator generates a phase signal satisfying a preset clock synchronization condition, and the second phase signal selector selects the phase signal satisfying the preset clock synchronization condition as the phase selection signal of the cdr..
| Protection systems and methods for handling multiple faults and isolated nodes in interconnected ring networks|
The present disclosure provides protection systems and methods that provide a mechanism to identify/determine when an interconnection node has been isolated (i.e. When there is no connectivity between a pair of interconnection nodes), from a data path perspective.
| Fault tolerant integrated circuit architecture|
The exemplary embodiments provide a resilient integrated circuit. An exemplary ic comprises a plurality of composite circuit elements, a state machine element (sme), and a plurality of communication elements.
|Debugging multiple exclusive sequences using dsm context switches|
A system and method for efficiently debugging an integrated circuit with on-die hardware. A processor core includes an on-die debug state machine (dsm).
|Multiple clock domain debug capability|
An integrated circuit with debug capability includes a first packer and synchronizer to combine a multiple number of values of a first trigger signal received from a first circuit to form a first packed trigger signal and to output a synchronized first packed trigger signal in response to a trigger clock signal, the first trigger signal being synchronous with a first source clock signal, a first logic gate to provide a first output trigger signal indicative of whether any of the first multiple number of values of the first trigger signal in the first synchronized packed trigger signal is in a first state, and a debug state machine responsive to the first output trigger signal to selectively provide a first action signal.. .
|Match engine for detection of multi-pattern rules|
Methods, systems and computer program products are disclosed for detecting patterns in a data stream that match multi-pattern rules. One embodiment of the invention provides a method of recognizing a specified group of patterns in a data stream.
|Sequential state elements for triple-mode redundant state machines, related methods, and systems|
The disclosure relates generally to sequential state elements (sses), triple-mode redundant state machines (tmrsms), and methods and systems for testing triple-mode redundant pipeline stages (tmrpss) within the tmrsms using triple-mode redundant sses (tmrsses). The sses, tmrsms, tmrpss, and tmrsses may be formed as integrated circuits on a semiconductor substrate.
|Systems and methods for limiting user customization of task workflow in a condition based health maintenance system|
Systems and methods are provided for customizing workflow in a condition based health maintenance (“cbm”) system computing node. The computerized method comprises identifying a first standardized executable application module (“seam”), wherein the first seam is configured to generate a first event associated with particular data being processed by the first seam and identifying a second seam, wherein the second seam is configured to generate a subsequent event associated with the particular data processed by the first seam.
|Low power testing of very large circuits|
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths..
|System and method for sharing a communications link between multiple communications protocols|
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol.
|Optimized multi-level finite state machine with redundant dc nodes|
A method and system for eliminating/suppressing long transition runs over a communications channel is disclosed. The method may include providing modulation coding based on a multi-level finite state machine (ml-fsm) having a periodic structure, the periodic structure being defined by a predetermined number of time frames.
|Content search mechanism that uses a deterministic finite automata (dfa) graph, a dfa state machine, and a walker process|
An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a dfa graph but includes a command.
Mechanisms are provided for accelerated data deduplication. A data stream is received an input interface and maintained in memory.
|Method of diagnosing a starter relay failure using synchronized state machine|
A method and electrical system for detecting and compensating for a failure in a starter circuit that comprises first and second relays in a circuit path to a starter motor of a vehicle. The method and system determine if at least one of the first or second relays is in a closed position when it should be in an open position and disables a vehicle starter operation if it is determined that at least one of the first or second relays is in the closed position when it should be in the open position.
|Method of efficient blind scell activation|
An effective scell activation procedure is proposed to reduce the scell activation time. For carrier aggregation, a secondary cell (scell) needs to be configured and then activated before a ue can perform normal operation.
|Non-volatile memory and method with peak current control|
A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity.
|Providing multiple quiesce state machines in a computing environment|
An aspect includes a method for operating on translation look-aside buffers (tlbs) in a multiprocessor environment including a plurality of logical partitions as zones. The method includes concurrently receiving a first quiesce request from a first processor of a first zone to quiesce processors of a first set of zones including the first zone and receiving a second quiesce request from a second processor of a second zone to quiesce processors of a second set of zones including the second zone.
|Methods and systems for handling data received by a state machine engine|
A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed.
|Methods and systems for using state vector data in a state machine engine|
A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice.
|Methods and devices for programming a state machine engine|
A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice.
|System and method for facilitating comparison of radio frequency (rf) data signals transmitted by a device under test (dut) and received by a test system|
A system and method for facilitating comparison of radio frequency (rf) data signals transmitted by a device under test (dut) and received by a test system. A rf data signal received from a dut is analyzed to provide analysis data indicative of conformance of the dut operation with one or more applicable signal standards.
|Nand flash memory programming|
A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described..
|Automated web task procedures based on an analysis of actions in web browsing history logs|
Embodiments of the invention relate to generating automated web task procedures from an analysis of web history logs. One aspect of the invention concerns a method that comprises identifying sequences of related web actions from a web log, grouping each set of similar web actions into an action class, and mapping the sequences of related web actions into sequences of action classes.
|Approach for managing state transitions of a data connector|
A microprocessor within a processing unit is configured to manage to operation of a finite state machine (fsm) that, in turn, manages the operation of a data connector. The fsm may be a hardwired chip component that adheres to a communication protocol associated with the data connector.
|Flash memory controllers and error detection methods|
A flash memory controller includes a read/write unit, a state machine, a processing unit, and an auxiliary unit. The read/write unit is connected to a flash memory and performs a writing command or a reading command.
|Method and device for extracting data from a data stream travelling around an ip network|
In a phase of configuration, a state machine (20) is constructed with states and transitions configured according to at least one type of data to be extracted from a data stream travelling around an ip network. The transitions between states are activated by conditions defined as a function of rules of organization of the data of the stream according to an application layer protocol.
|Method and apparatus to control a power converter having a low loop bandwidth|
A controller for use in a power converter includes a comparator coupled to receive a signal representative of an output of the power converter. A counter is coupled to an output of the comparator to sample the output of the comparator a plurality of times within a period.
|Efficiently implementing a plurality of finite state machines|
An approach for processing data by a pipeline of a single hardware-implemented virtual multiple instance finite state machine (vmi fsm) is presented. Based on a current state and context of an fsm instance, an input token selected from multiple input tokens to enter a pipeline of the vmi fsm, and a status of an environment, a new state of the fsm instance is determined and an output token is determined.
|Interprocessor communications systems and methods|
A method, an apparatus, and a computer program product for communication within a wireless terminal. The method can be implemented using dedicated logic and managed and controlled by state machines and/or sequencers.
|Continuous application and decompression of test patterns and selective compaction of test responses|
A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test.
|Architected protocol for changing link operating mode|
In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed..
|System and method for providing a user interaction interface using a multi-touch gesture recognition engine|
Described herein are systems and methods for enabling a multi-touch gesture recognition engine, where gesture recognition can be made based on touch or motion detection. In accordance with an embodiment the system include a hardware input list delivered from the hardware sensor(s), a touchobject list delivered from the application(s)/os and logic to calculate and determine gestures based on mapping touchpoints from the sensor(s) with touchobjects from the application(s) in a time perspective.
|Differential clock signal generator|
Disclosed is a differential clock signal generator which processes a first differential clock signal using a combination of differential and non-differential components to generate a second differential clock signal. Specifically, the first differential clock signal is converted into a single-ended clock signal, which is used either by a finite state machine to generate two single-ended control signals or by a waveform generator to generate a single-ended waveform control signal.
|Method for protecting rtl ip core|
A method for protecting register transfer level (rtl) intellectual property (ip) core is provided, which converts an original rtl ip core to a target rtl ip core embedded with protection measures. The method includes: step s1, constructing a state machine whose mode is controllable against the original rtl ip core, the state machine has a normal mode appeared corresponding to the normal function of the ip core after the entry of a correct preset secret key value and a fuzzy mode appeared corresponding to the abnormal function of the ip core after the entry of wrong secret key value; step s2, revise the data flow of the rtl code in the original rtl ip core to obtain the fuzzy rtl code of the ip core; and step s3: combine the state machine and the fuzzy rtl code into the targeted rtl ip core.
|Method for controlling a state machine|
A method and a system for controlling a state machine are described. In the method, a script is used via which each arbitrary path in the state machine.
|Method for controlling a manufacturing execution system (mes)|
A method controls a manufacturing execution system (mes) in which one or more parameters of a predetermined manufacturing process executed in a production chain may deviate from a predetermined range. The method includes storing in a controller module of the mes predetermined ranges associated with parameters to be controlled and detecting parameter values in the manufacturing process and a deviation thereof outside a predetermined range.
|Methods, systems, and computer readable media for automatically generating a fuzzer that implements functional and fuzz testing and testing a network device using the fuzzer|
Methods, systems, and computer readable media for automatically generating a fuzzer for testing a network device using the fuzzer are disclosed. According to one method, a functional description of a network communications protocol finite state machine is received as input.
|Power management system for electronic circuit|
A power management circuit for managing power supplied to an electronic circuit by a core power supply. The electronic circuit includes digital and analog circuit domains and operates in power-on, run and standby modes.
|Multiply-and-accumulate operation in an implantable microcontroller|
The invention provides microprocessor extensions for cooperating with a sequential arithmetic-logic unit (alu) to execute a multiply-and-accumulate operation (mac). The alu performs a continuous sequence of accumulation instructions synchronously with a clock signal (clk1).
|Active cable management|
Disclosed is a method and state machine that configures a serial attached scsi (sas) controller. The insertion of a mini-sas hd cable is detected.
|Programmable regular expression and context free grammar matcher|
A regular expression matcher system, including: a deterministic finite state machine (dfsm); a ternary content addressable memory (tcam) matcher to compare a word stored at the tcam matcher to an input stream, wherein the word determines a state-to-state transition of the dfsm from a comparison result; a programmable logic connected to an output of the tcam matcher to identify a next state in the dfsm based on the comparison result; a state register to update a current state of the dfsm to the next state; and a collection data structure coupled to the tcam matcher and the programmable logic to store a sequence of required state transitions for the dfsm, wherein the programmable logic determines a next required state transition to be matched from the sequence.. .
|Control computer for an unmanned vehicle|
A control computer for an unmanned vehicle, including: a sensor interface for receiving sensor data from sensors of the vehicle, the sensor data including data values associated with movement of the vehicle; an actuator control interface for sending actuator data to control actuators of the vehicle, the actuators controlling parts of the vehicle associated with controlling movement of the vehicle; and a system management component for executing a state machine having states corresponding to one or more phases of the movement and for determining a transition between current one of the states and another of the states based on at least one condition associated with the transition, at least one condition being determined based on at least one of the sensor data, the actuator data and status of the computer.. .
A state machine gesture recognition algorithm for interpreting streams of coordinates received from a touch sensor. The gesture recognition code can be written in a high level language such as c and then compiled and embedded in a microcontroller chip, or cpu chip as desired.
|Universal charging detection device and universal charging detection method|
A universal charging detection device and a universal charging detection method are disclosed herein. The universal charging detection device is provided for a charger that can be electrically connected to an electronic device via a universal serial bus (usb).
|Method for using java servlets as a stack based state machine|
A client module downloaded by web browser from a server receives authentication information to open a smart card in a card reader and to initiate a secure network connection to a first server module running on a server. The client module calls a second server module running on the server.
|Embedded hardware state machine for context detection integrated with a sensor chip|
Hardware state machine is embedded with sensing element to generate movement context values and context information. Mobile device includes applications processor (ap), data storage, and sensor integrated circuit (ic) package.
|Integrated circuit device, electronic device and method for frequency detection|
An integrated circuit comprises a frequency detector. The frequency detector comprises a timer state machine unit operably couplable to a timer and arranged to receive an incoming carrier signal; determine whether the incoming carrier signal comprises a valid frequency; generate a valid carrier indication when the incoming carrier signal is determined as having a valid frequency; and adjust the timer between at least a first timing mode of operation and a second timing mode of operation of the frequency detector in response to the determination..
|Rule-based method for proving unsatisfiable conditions in a mixed numeric and string solver|
A method includes, by computing devices, analyzing numeric and string constraints associated with a software module that includes numeric and string variables and operations applying to specific variables for numeric or string results. The numeric constraints apply to specific numeric variables.
|Gather using index array and finite state machine|
Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements.
|Arbiter for asynchronous state machines|
An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal.
|Large-scale event evaluation using realtime processors|
Large-scale event processing systems are often designed to perform data mining operations by storing a large set of events in a massive database, applying complex queries to the records of the events, and generating reports and notifications. However, because such queries are performed on very large data sets, the processing of the queries often introduces a significant delay between the occurrence of the events and the reporting or notification thereof.
|Single transceiver for wireless peer-to-peer connections|
Data transfer in a communications network includes a first communication device including a transceiver; and an interface operatively connected to the first communication device, wherein the interface provides multiple operative connections for data transfer, wherein the multiple operative connections include a wlan connection adapted for communication with an access point that generates data exchange signals; and a p2p connection adapted for communication with a second communication device, wherein the transceiver is shared between the multiple operative connections. The first and second communication devices may include a wifi device.
|Flash memory controller|
An apparatus and method of managing the operation of a plurality of flash chips provides for a physical layer (phy) interface to a flash memory circuit having a plurality of flash chips having a common interface bus. The apparatus has a phy for controlling the voltages on the interface pins in accordance with a microprogrammable state machine.