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State Machine patents

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Date/App# patent app List of recent State Machine-related patents
 Architected protocol for changing link operating mode patent thumbnailnew patent Architected protocol for changing link operating mode
In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed..
 Virtual gpio patent thumbnailnew patent Virtual gpio
A finite state machine is provided that both serializes virtual gpio signals and deserializes virtual gpio signals responsive to cycles of an external clock. The finite state machine frames the serialized virtual gpio signals into frames each demarcated by a start bit and an end bit..
 On-chip hv and lv capacitors acting as the second back-up supplies for nvsram auto-store operation patent thumbnailnew patent On-chip hv and lv capacitors acting as the second back-up supplies for nvsram auto-store operation
Two on-chip capacitors including one hv capacitor vppcap and one lv vcc capacitor vcccap are built over a nvsram memory chip as a back-up second power supplies for each nvsram cell, regardless of 1-poly, 2-poly, pmos or nmos flash cell structures therein. The on-chip hv and lv capacitors are preferably made from one or more mim or mip layers for achieving required capacitance.
 State machine based parsing algorithm on a data-status fifo with multiple banks patent thumbnailState machine based parsing algorithm on a data-status fifo with multiple banks
In the l2 fifo architecture incoming frames are stored in a multi bank fifo to enable offloading the programmable real-time unit to do other tasks. The l2 fifo buffers data coming from the l1 fifo, reducing the polling time for received data.
 Implementing storage adapter performance control patent thumbnailImplementing storage adapter performance control
A method and controller for implementing storage adapter performance control, and a design structure on which the subject controller circuit resides are provided. The controller includes a performance state machine controlling the use of a performance path and a normal or error recovery path in a storage adapter firmware stack.
 Two-wire communication protocol engine patent thumbnailTwo-wire communication protocol engine
In an example embodiment, a two-wire communication protocol engine manages control and data transmissions in a bi-directional, multi-node bus system where each node is connected over a twisted wire pair bus to another node. Some embodiments include a state machine that allows for synchronized updates of configuration data across the system, a distributed interrupt system, a synchronization pattern based on data coding used in the system, and data scrambling applied to a portion of the data transmitted over the twisted wire pair bus.
 Method and system for automating the editing of computer files patent thumbnailMethod and system for automating the editing of computer files
The present invention is a method and system for automating repetitive user actions during the text editing operations of various computer files. Computer users may commonly perform some repetitive or patterned actions while editing text files such as scripts, or editing markup files like html or xml, or editing source code or even regular text files that contain tabular data or lists.
 Method and apparatus to generate platform correctable tx-rx patent thumbnailMethod and apparatus to generate platform correctable tx-rx
A programmable link training and status state machine is disclosed. The programmable finite state machine includes extra states, or shadow states, which are strategically used to debug a system design or to accommodate unexpected behavior, such as when the specifications of the design change.
 Receiver patent thumbnailReceiver
A receiver for receiving an rf signal transmitting a bit sequence representing a symbol is provided. The receiver includes an oscillator, a counter, at least one state machine and at least one correlator.
 Search unit to accelerate variable length compression/decompression patent thumbnailSearch unit to accelerate variable length compression/decompression
Systems and methods to accelerate compression and decompression with a search unit implemented in the processor core. According to an embodiment, a search unit may be implemented to perform compression or decompression on an input stream of data.
Circuits, systems, and methods for managing automatic gain control in quadrature signal paths of a receiver
A system provides closed-loop gain control in a wcdma mode and open loop control in an edge/gsm mode. Gain control is distributed across analog devices and a digital scaler in a wireless receiver.
Method and apparatus for quantifying characteristics of a received serial data stream
A data stream monitor includes an analog front end (afe) and a digital state machine. The afe receives recovered clock and data signals at a first rate.
Method and apparatus for test connectivity, communication, and control
Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ics and reduces the ic's power consumption during scan testing.
Safety system challenge-and-response using modified watchdog timer
Some embodiments of the present disclosure relate to a watchdog timer having an enhanced functionality that enables the watchdog timer to monitor a process flow of the microprocessor on a task-by-task basis that enables a simple output signal to be used to determine if the watchdog timer is malfunctioning. The watchdog timer has a state machine that increments a state variable from an initial value over a watchdog period.
Real-time priority-based media communication
Representative embodiments are disclosed of a real-time priority-based communication system and method for communicating media streams made up of multiple media message sub-streams, the communication system comprising a chunk configurator for dividing media message sub-streams into chunks, a state machine configured to translate between information regarding the media message sub-streams and the chunks and state associations to the information, the state associations written into a header for each of the chunks, a queue for holding the chunks waiting to be transmitted, and a processor for executing a scheduling algorithm, wherein the scheduling algorithm determines ones of the chunks in the queue to transmit next.. .
Link bundle co-routed vcat via rsvp message bundling
Multiple rsvp messages are used to separately signal components of co-routed vcat to enable the separate components to be implemented on different physical fibers of a link bundle. To enable the path messages to be handled as a group, the multiple path messages are grouped together and sent out in a rsvp bundle message.
Boolean logic in a state machine lattice
Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable boolean logic cell that may be programmed to perform various logic functions on a data stream.
Heater with energy-saving operations and method related thereto
A heater includes a heating unit that supports at least a high-power state, a low-power state and a stand-by state. A control circuitry of the heater implements a state machine to control the heating unit, with respective states in the state machine corresponding to power states in the heating unit.
Method of getting out from error entering into test mode in usb3.0 apparatus
The present invention discloses a method of getting out from error entering into test mode in usb3.0 apparatus, in which extra status states are inserted into the compliance mode in the original state diagram of the link training and status state machine of the conventional usb3.0 protocol. The inserting status states are to set up a timer, and go to power saving state u1, u2, or u3 or ss.disable state when timeout happens.
Peripheral trigger generator
A microcontroller includes a central processing unit (cpu); a plurality of peripheral units; and a peripheral trigger generator comprising a user programmable state machine, wherein the peripheral trigger generator is configured to receive a plurality of input signals and is programmable to automate timing functions depending on at least one of said input signals and generate at least one output signal.. .
System and method of controlling power delivery to a surgical instrument
A thermal surgical instrument having a system to control the delivery of power from an energy source to active element located on a tip. The system for controlling delivery to the tip may include a control algorithm which uses on or more measurements, such as tip current, swr, and rapid changes in reflected power, to manage power without affecting cutting efficacy, and in a manner that may be imperceptible by a surgeon.
Operation mode switching module and associated method
An operation mode switching module for a switching a near-field communication device between a sleep mode and a communication mode is provided. The operation mode switching module includes a driver, a detector, and a state machine.
Determining relevant events in source code analysis
In embodiments of determining relevant events in source code analysis, a computing device includes a key event manager that is implemented to traverse executable paths in source code of executable software instructions, log events along the executable paths in the source code, and determine a defect in the source code along an executable path in the source code. A state machine is implemented to traverse back through the logged events and determine relevant events that are associated with the defect in the source code.
Instruction insertion in state machine engines
State machine engines are disclosed, including those having an instruction insertion register. One such instruction insertion register may provide an initialization instruction, such as to prepare a state machine engine for data analysis.
Results generation for state machine engines
A state machine engine includes a storage element, such as a (e.g., match) results memory. The storage element is configured to receive a result of an analysis of data.
Flash memory devices and controlling methods therefor
A flash memory controller is provided. The flash memory controller includes a read/write unit, a state machine, a processing unit, and a reserve unit.
Methods and systems for power management in a pattern recognition processing system
A device includes a state machine. The state machine includes a plurality of blocks, where each of the blocks includes a plurality of rows.
Cdr circuit and terminal
Embodiments of the present invention disclose a cdr circuit and a terminal, where the cdr circuit is configured to perform clock synchronization in a terminal with eee function, and the cdr circuit includes: a phase detector, a first phase signal selector, a loop filter, a numerical controlled oscillator, a second phase signal selector, a phase signal generator, and a state machine. In the embodiments of the present invention, after the terminal enters a refresh state from a quiet state, the cdr circuit can implement clock synchronization with a peer end without waiting for the loop filter and the numerical controlled oscillator to be converged, but the phase signal generator generates a phase signal satisfying a preset clock synchronization condition, and the second phase signal selector selects the phase signal satisfying the preset clock synchronization condition as the phase selection signal of the cdr..
Protection systems and methods for handling multiple faults and isolated nodes in interconnected ring networks
The present disclosure provides protection systems and methods that provide a mechanism to identify/determine when an interconnection node has been isolated (i.e. When there is no connectivity between a pair of interconnection nodes), from a data path perspective.
Fault tolerant integrated circuit architecture
The exemplary embodiments provide a resilient integrated circuit. An exemplary ic comprises a plurality of composite circuit elements, a state machine element (sme), and a plurality of communication elements.
Debugging multiple exclusive sequences using dsm context switches
A system and method for efficiently debugging an integrated circuit with on-die hardware. A processor core includes an on-die debug state machine (dsm).
Multiple clock domain debug capability
An integrated circuit with debug capability includes a first packer and synchronizer to combine a multiple number of values of a first trigger signal received from a first circuit to form a first packed trigger signal and to output a synchronized first packed trigger signal in response to a trigger clock signal, the first trigger signal being synchronous with a first source clock signal, a first logic gate to provide a first output trigger signal indicative of whether any of the first multiple number of values of the first trigger signal in the first synchronized packed trigger signal is in a first state, and a debug state machine responsive to the first output trigger signal to selectively provide a first action signal.. .
Match engine for detection of multi-pattern rules
Methods, systems and computer program products are disclosed for detecting patterns in a data stream that match multi-pattern rules. One embodiment of the invention provides a method of recognizing a specified group of patterns in a data stream.
Sequential state elements for triple-mode redundant state machines, related methods, and systems
The disclosure relates generally to sequential state elements (sses), triple-mode redundant state machines (tmrsms), and methods and systems for testing triple-mode redundant pipeline stages (tmrpss) within the tmrsms using triple-mode redundant sses (tmrsses). The sses, tmrsms, tmrpss, and tmrsses may be formed as integrated circuits on a semiconductor substrate.
Systems and methods for limiting user customization of task workflow in a condition based health maintenance system
Systems and methods are provided for customizing workflow in a condition based health maintenance (“cbm”) system computing node. The computerized method comprises identifying a first standardized executable application module (“seam”), wherein the first seam is configured to generate a first event associated with particular data being processed by the first seam and identifying a second seam, wherein the second seam is configured to generate a subsequent event associated with the particular data processed by the first seam.
Low power testing of very large circuits
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths..
System and method for sharing a communications link between multiple communications protocols
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol.
Optimized multi-level finite state machine with redundant dc nodes
A method and system for eliminating/suppressing long transition runs over a communications channel is disclosed. The method may include providing modulation coding based on a multi-level finite state machine (ml-fsm) having a periodic structure, the periodic structure being defined by a predetermined number of time frames.
Content search mechanism that uses a deterministic finite automata (dfa) graph, a dfa state machine, and a walker process
An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a dfa graph but includes a command.
Accelerated deduplication
Mechanisms are provided for accelerated data deduplication. A data stream is received an input interface and maintained in memory.
Method of diagnosing a starter relay failure using synchronized state machine
A method and electrical system for detecting and compensating for a failure in a starter circuit that comprises first and second relays in a circuit path to a starter motor of a vehicle. The method and system determine if at least one of the first or second relays is in a closed position when it should be in an open position and disables a vehicle starter operation if it is determined that at least one of the first or second relays is in the closed position when it should be in the open position.
Method of efficient blind scell activation
An effective scell activation procedure is proposed to reduce the scell activation time. For carrier aggregation, a secondary cell (scell) needs to be configured and then activated before a ue can perform normal operation.
Non-volatile memory and method with peak current control
A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity.
Providing multiple quiesce state machines in a computing environment
An aspect includes a method for operating on translation look-aside buffers (tlbs) in a multiprocessor environment including a plurality of logical partitions as zones. The method includes concurrently receiving a first quiesce request from a first processor of a first zone to quiesce processors of a first set of zones including the first zone and receiving a second quiesce request from a second processor of a second zone to quiesce processors of a second set of zones including the second zone.
Methods and systems for handling data received by a state machine engine
A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed.
Methods and systems for using state vector data in a state machine engine
A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice.
Methods and devices for programming a state machine engine
A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice.
System and method for facilitating comparison of radio frequency (rf) data signals transmitted by a device under test (dut) and received by a test system
A system and method for facilitating comparison of radio frequency (rf) data signals transmitted by a device under test (dut) and received by a test system. A rf data signal received from a dut is analyzed to provide analysis data indicative of conformance of the dut operation with one or more applicable signal standards.
Nand flash memory programming
A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described..
Automated web task procedures based on an analysis of actions in web browsing history logs
Embodiments of the invention relate to generating automated web task procedures from an analysis of web history logs. One aspect of the invention concerns a method that comprises identifying sequences of related web actions from a web log, grouping each set of similar web actions into an action class, and mapping the sequences of related web actions into sequences of action classes.
Approach for managing state transitions of a data connector
A microprocessor within a processing unit is configured to manage to operation of a finite state machine (fsm) that, in turn, manages the operation of a data connector. The fsm may be a hardwired chip component that adheres to a communication protocol associated with the data connector.
Flash memory controllers and error detection methods
A flash memory controller includes a read/write unit, a state machine, a processing unit, and an auxiliary unit. The read/write unit is connected to a flash memory and performs a writing command or a reading command.
Method and device for extracting data from a data stream travelling around an ip network
In a phase of configuration, a state machine (20) is constructed with states and transitions configured according to at least one type of data to be extracted from a data stream travelling around an ip network. The transitions between states are activated by conditions defined as a function of rules of organization of the data of the stream according to an application layer protocol.
Method and apparatus to control a power converter having a low loop bandwidth
A controller for use in a power converter includes a comparator coupled to receive a signal representative of an output of the power converter. A counter is coupled to an output of the comparator to sample the output of the comparator a plurality of times within a period.
Efficiently implementing a plurality of finite state machines
An approach for processing data by a pipeline of a single hardware-implemented virtual multiple instance finite state machine (vmi fsm) is presented. Based on a current state and context of an fsm instance, an input token selected from multiple input tokens to enter a pipeline of the vmi fsm, and a status of an environment, a new state of the fsm instance is determined and an output token is determined.
Interprocessor communications systems and methods
A method, an apparatus, and a computer program product for communication within a wireless terminal. The method can be implemented using dedicated logic and managed and controlled by state machines and/or sequencers.
Continuous application and decompression of test patterns and selective compaction of test responses
A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test.
Architected protocol for changing link operating mode
In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed..
System and method for providing a user interaction interface using a multi-touch gesture recognition engine
Described herein are systems and methods for enabling a multi-touch gesture recognition engine, where gesture recognition can be made based on touch or motion detection. In accordance with an embodiment the system include a hardware input list delivered from the hardware sensor(s), a touchobject list delivered from the application(s)/os and logic to calculate and determine gestures based on mapping touchpoints from the sensor(s) with touchobjects from the application(s) in a time perspective.
Differential clock signal generator
Disclosed is a differential clock signal generator which processes a first differential clock signal using a combination of differential and non-differential components to generate a second differential clock signal. Specifically, the first differential clock signal is converted into a single-ended clock signal, which is used either by a finite state machine to generate two single-ended control signals or by a waveform generator to generate a single-ended waveform control signal.

Popular terms: [SEARCH]

State Machine topics: State Machine, Finite State Machine, Transistors, Data Structure, Accumulator, Data Structures, Conditional, Bit Stuffing, Memory Device, State Transition, Optimization Problem, Combinator, Frequency Detector, Computer Program, Data Storage

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This listing is a sample listing of patents related to State Machine for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for State Machine with additional patents listed. Browse our RSS directory or Search for other possible listings.

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