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Sram patents



      
           
This page is updated frequently with new Sram-related patent applications. Subscribe to the Sram RSS feed to automatically get the update: related Sram RSS feeds. RSS updates for this page: Sram RSS RSS


Circuit for reverse biasing inverters for reducing the power consumption of an sram memory

Circuit for reverse biasing inverters for reducing the power consumption of an sram memory

Bit cell with double patterened metal layer structures

Bit cell with double patterened metal layer structures

Bit cell with double patterened metal layer structures

Pre-charging bitlines in a static random access memory (sram) prior to data access for reducing leakage power, and…

Date/App# patent app List of recent Sram-related patents
11/13/14
20140334688
 Image processor patent thumbnailImage processor
An image processor includes an lsram accessible with a higher speed than a frame memory and configured to hold a second image in a predetermined range of a first image, an image production unit configured to read an image in a predetermined range of the second image from the lsram and produce a third image for rough search based on the read image, an msram accessible with a higher speed than the frame memory and configured to hold the third image produced by the image production unit, a search unit configured to read the third image from the msram and perform first motion search based on the third image, and a search unit configured to read a fourth image in a predetermined range of the second image from the lsram based on a search result by the search unit and perform second motion search that is more detailed than the first motion search based on the fourth image.. .
11/13/14
20140334226
 Circuit for reverse biasing inverters for reducing the power consumption of an sram memory patent thumbnailCircuit for reverse biasing inverters for reducing the power consumption of an sram memory
Cmos integrated circuits with very low consumption when idle, and notably the sram volatile memories, are provided. The inverters of the circuit are made up of an nmos transistor and a pmos transistor.
11/13/14
20140332967
 Bit cell with double patterened metal layer structures patent thumbnailBit cell with double patterened metal layer structures
An approach for providing sram bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge..
11/06/14
20140328113
 Pre-charging bitlines in a static random access memory (sram) prior to data access for reducing leakage power, and related systems and methods patent thumbnailPre-charging bitlines in a static random access memory (sram) prior to data access for reducing leakage power, and related systems and methods
Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (sram) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a sram data array of the sram.
11/06/14
20140327082
 Sram well-tie with an uninterrupted grated first poly and first contact patterns in a bit cell array patent thumbnailSram well-tie with an uninterrupted grated first poly and first contact patterns in a bit cell array
An integrated circuit containing an sram may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in sram cells. Strap rows of the sram containing well ties and/or substrate taps which have sram cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps..
10/30/14
20140322870
 Sram cell with different crystal orientation than associated logic patent thumbnailSram cell with different crystal orientation than associated logic
An integrated circuit containing logic transistors and an array of sram cells in which the logic transistors are formed in semiconductor material with one crystal orientation and the sram cells are formed in a second semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of sram cells in which the logic transistors are formed in a top semiconductor layer with one crystal orientation and the sram cells are formed in an epitaxial semiconductor layer with another crystal orientation.
10/30/14
20140321462
 Scalable and efficient flow-aware packet distribution patent thumbnailScalable and efficient flow-aware packet distribution
Techniques for efficiently distributing data packets in a network device are provided. In one embodiment, the network device can store a plurality of virtual ip addresses and a plurality of real server ip addresses in an sram-based table.
10/30/14
20140320482
 Liquid crystal display (lcd) device patent thumbnailLiquid crystal display (lcd) device
A lcd device includes pixels formed of column data lines and row scanning lines. The pixel includes a display element; a first switching unit that performs sampling on each frame data of an input video signal; a first holding unit that configures an sram, and holds sub frame data; a second switching unit that causes the sub frame data held in the first holding unit; and a second holding unit that configures a dram, and applies output data to the pixel electrode, a pixel control unit that performs an operation of repeating writing the sub frame data in the first holding unit, turning on the second switching units, and rewriting memory content of the second holding units; and a timing control unit.
10/30/14
20140320477
 Liquid crystal display device patent thumbnailLiquid crystal display device
Provided is a liquid crystal display device that includes: pixels, a pixel control unit, and a common voltage generation unit. The pixel includes: a display element; a first switching unit configured to sample each frame data; a first holding unit configured to form an sram, and to hold sub-frame data sampled; a second switching unit configured to output the sub-frame data; and a second holding unit configured to form a dram, and configured of which stored content is rewritten by the sub-frame data.
10/30/14
20140319609
 Finfet drive strength modification patent thumbnailFinfet drive strength modification
One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a sram cell formed from finfet transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved sram cell performance..
10/23/14
20140315363
6t sram architecture for gate-all-around nanowire devices
A memory device includes a first plurality of semiconductor nanowires tethered between landing pads and suspended over a substrate. A first gate electrode surrounds each of the first plurality of semiconductor nanowires, making them gate-all-around, (gaa) semiconductor nanowires.
10/23/14
20140313819
System on chip including dual power rail and voltage supply method thereof
A system on chip includes an sram. The sram includes at least one memory cell and a peripheral circuit accessing the at least memory cell.
10/23/14
20140313817
Sram core cell design with write assist
A static random access memory (sram) cell is disclosed. The sram cell includes a storage unit configured to store a data bit in a storage node.
10/23/14
20140312426
6t sram architecture for gate-all-around nanowire devices
A memory device includes a first plurality of semiconductor nanowires tethered between landing pads and suspended over a substrate. A first gate electrode surrounds each of the first plurality of semiconductor nanowires, making them gate-all-around (gaa) semiconductor nanowires.
10/16/14
20140307739
Systems and methods for accessing a multi-bank sram
A device may include multi-bank sram logic configured to receive an lookup result that includes a first number of addresses, parse each of the first number of addresses from the received lookup result, simultaneously provide at least one of the first number of parsed addresses to each of a first number of srams, simultaneously read data from each of the first number of srams and simultaneously transmit the read data from each of the first number of srams.. .
10/16/14
20140307503
Eight transistor soft error robust storage cell
A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes.
10/16/14
20140307501
Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers
A floating body sram cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body sram cell by a memory compiler for use in array design is provided..
10/09/14
20140304463
Systems and methods involving multi-bank, dual- or multi-pipe srams
Systems and methods are disclosed for increasing the performance of static random access memory (sram). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank srams, such as quad-b2 srams.
10/09/14
20140299941
Sram cell with reduced voltage droop
A mesh circuit for the vss supply voltage of a sram device is disclosed. Embodiments also provide a sram bitcell design comprising a vss mesh disposed in two different metal layers.
10/02/14
20140295630
Sige sram butted contact resistance improvement
The present disclosure relates to a method for fabricating a butted a contact arrangement configured to couple two transistors, wherein an active region of a first transistor is coupled to a gate of a second transistor. The gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active region of the first transistor and an isolation layer formed about the first transistor.
10/02/14
20140293682
Memory bitcell clusters employing localized generation of complementary bitlines to reduce memory area, and related systems and methods
Embodiments disclosed include memory bitcell clusters employing localized generation of complementary bitlines to reduce memory area. The memory bitcell clusters disclosed may be static random access memory (sram) used as central processing unit (cpu) register files.
10/02/14
20140293681
8t sram cell with one word line
An integrated circuit with sram cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and one passgate transistor may be variously configured to a separate read data line and write data line, or a combined data line, in different embodiments.
10/02/14
20140293679
Management of sram initialization
An embodiment of the current disclosure is directed to a static random access memory (sram) device, and a design structure for the sram device. The sram device may include one or more sram cells.
09/18/14
20140281341
Multiple, per sensor configurable fifos in a single static random access memory (sram) structure
A device includes one or more sensors, one or more processors, one or more sensors, and a memory. The memory has a first portion, a second portion, and a third portion.
09/18/14
20140281184
Mixed memory type hybrid cache
A hybrid cache includes a static random access memory (sram) portion and a resistive random access memory portion. Cache lines of the hybrid cache are configured to include both sram macros and resistive random access memory macros.
09/18/14
20140269137
Canary based sram adaptive voltage scaling (avs) architecture and canary cells for the same
A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank..
09/18/14
20140269114
Circuit for memory write data operation
A pulsed dynamic lcv circuit for improving write operations for sram. The pulsed dynamic lcv circuit includes voltage adjustment circuitry having a plurality of selectable reduced supply voltages and timing adjustment circuitry having a plurality of selectable logical state transition timings for adjustably controlling the voltage and timing of a transition from a selected reduced supply voltage back to a nominal supply voltage.
09/18/14
20140269041
Emulation of static random access memory (sram) by magnetic random access memory (mram)
A magnetic memory system includes a magnetic random access memory (mram) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (fifo) interface device coupled to the mram and including a plurality of fifos each of the magnetic memory banks is coupled to a respective one of the plurality of fifos, the fifo being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the mram is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks..
09/18/14
20140269021
Timing logic for memory array
Among other things, techniques and systems are provided for devising a schedule for performing read/write operations on a memory cell. A control signal is provided to timing logic.
09/18/14
20140269019
Dual-port static random access memory (sram)
In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters.
09/18/14
20140269016
Multiport memory with matching address control
A multiport sram has an array of cells, a first port, and a second port. During a period of different row addresses for the ports, the first port uses first word lines and first bit lines.
09/11/14
20140254293
High-speed memory write driver circuit with voltage level shifting features
Various aspects of a fast, energy efficient write driver capable of efficient operation in a dual-voltage domain memory architecture are provided herein. Specifically, various aspects of the write driver described herein combine a high speed driver with voltage level shifting capabilities that may be implemented efficiently in reducing use of silicon area while using lower power.
09/11/14
20140254249
Stable sram cell
Sram cells and sram cell arrays are described. In one embodiment, an sram cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value.
09/11/14
20140254248
Stable sram cell
Sram cells and sram cell arrays are described. In one embodiment, an sram cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value.
09/11/14
20140254246
Dual-port sram systems
Schematic circuit designs for a dual-port sram cell are disclosed, together with various layout schemes for the dual-port sram cell. The dual-port sram cell comprises a storage unit and a plurality of partial dummy transistors connected to the outputs of the storage unit.
09/11/14
20140252455
Structure and method for static random access memory device of vertical tunneling field effect transistor
The present disclosure provides one embodiment of a sram cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters. The pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (tfet) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel..
08/28/14
20140241089
Read assist circuit for an sram technical field
A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series.
08/28/14
20140241083
Read assist circuit for an sram technical field
A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series.
08/28/14
20140239999
Multiple-time configurable non-volatile look-up-table
Innovative non-volatile look-up-table (nv-lut) has been constructed by single gate logic non-volatile memory (sglnvm) devices processed with the standard cmos logic process. One of a pair of complementary sglnvm devices is always programmed to the high threshold voltage state and the other remains in the low threshold voltage state.
08/21/14
20140233303
Sram multiplexing apparatus
An sram multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank.
08/14/14
20140225201
Edge and strap cell design for sram array
Methodology enabling a reduction of edge and strap cell size, and the resulting device are disclosed. Embodiments include: providing first and second nw regions on a substrate; providing first and second rx regions on the first and second nw regions, respectively; providing a contact on the substrate connecting the first and second rx regions; and providing a dummy pc on the substrate connecting the first and second rx regions.
08/07/14
20140219011
Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features
A sectioned bit line of an sram memory device, an sram memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line.
08/07/14
20140219010
Semiconductor device
A logic circuit in a system lsi is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an sram circuit of the system lsi controls a substrate bias to reduce leakage current..
08/07/14
20140218770
Image processing apparatus and image processing method
In an image processing apparatus, fast error diffusion processing is performed without increasing the size of an error diffusion processing circuit, even in cases where the print data to be generated is 12 colors data or similarly large data. More specifically, with quantization by error diffusion, binarized image data for 12 colors is obtained by causing an image processing circuit that executes 6 colors quantization processing to operate twice.
07/31/14
20140215291
Systems and methods for error detection and correction in a memory module which includes a memory buffer
The present systems include a memory module containing a plurality of ram chips, typically dram, and a memory buffer arranged to buffer data between the dram and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words.
07/31/14
20140211581
Process variation skew in an sram column architecture
Aspects of the invention provide for a structure and method for determining a degree of process variation skew between a plurality of bit cells in a static random-access-memory (sram) column architecture. In one embodiment, a structure includes: a plurality of bit cells within a static random access memory (sram) column architecture; a digital-to-analog converter (dac) connected to the bit cells through a pair of multiplexers; and a pre-charge circuit connected to the bit cells through the pair of multiplexers, wherein the dac and the pre-charge circuit control and test the bit cells to determine a degree of process variation skew between each of the bit cells..
07/31/14
20140211578
Boosted read write word line
One or more techniques or systems for boosting a read word line (rwl) or a write word line (wwl) of a two port synchronous random access memory (sram) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a rwl, a wwl, or a read write word line (rwwl).
07/31/14
20140211548
Low power static random access memory
A bit line driver for a static random access memory (sram) cell including: a first voltage supply for supplying a first voltage; a second voltage supply for supplying a second voltage that is less than the first voltage; a write circuit to drive a bit line and an inverse bit line when writing to the sram cell; and a pre-charge circuit to pre-charge the bit line and the inverse bit line before reading the content of the sram cell. The bit line driver supplies a voltage less than the first voltage by a threshold voltage of one transistor to the bit line or the inverse bit line when the bit line driver drives the bit line or the inverse bit line to a high state..
07/31/14
20140211546
Static random access memories (sram) with read-preferred cell structures, write drivers, related systems, and methods
Static random access memories (sram) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the sram has a six transistor bit cell.
07/31/14
20140210561
Ring oscillator and semiconductor device
There are provided a ring oscillator having a plurality of delay circuits to be ring-connected. At least one of the plurality of delay circuits has a delay element formed in a layout region including the same layout shape as the layout shape of an sram cell, and a path circuit connected in parallel to the delay element.
07/24/14
20140204687
System and method for performing address-based sram access assists
A method and a system are provided for performing address-based memory access assist. An address is received for a memory access and a determination is made, based on the address, that access assist is enabled for at least one storage cell corresponding to the address.
07/24/14
20140204660
Memory having sense amplifier for output tracking by controlled feedback latch
In described embodiments, a memory circuit includes a static random access memory (sram) including n banks of memory cells, rows of m sense amplifiers, a controlled feedback latch storing a previous state of input data in a read cycle, a pull down select block coupled to the controlled feedback latch and the dummy sense amplifier, a dummy output latch coupled to the pull-down select block to store the read data, and a sram reset generation circuit coupled to the sense amplifier control circuits and the controlled feedback latch. The dummy output latch is a latch that is the same as a sense amplifier latch used in the local input/output circuit, thereby, no margin is involved between a reset of the sense amplifiers and the read data latched at the dummy output latch in the read cycle..
07/24/14
20140204658
Memory cell flipping for mitigating sram bti
An apparatus may comprise a memory cell configured to operate according to a voltage mode, a voltage controller coupled with the memory cell, wherein the voltage controller is configured to change the voltage mode of the memory cell between a low voltage mode and a high voltage mode, and a memory controller module coupled with the memory cell, wherein the memory controller is configured to invert a logic state stored in the memory cell based on the voltage mode.. .
07/24/14
20140204657
Sram voltage assist
The disclosure provides for an sram array having a plurality of wordlines and a plurality of bitlines, referred to generally as sram lines. The array has a plurality of cells, each cell being defined by an intersection between one of the wordlines and one of the bitlines.
07/17/14
20140201593
Efficient memory architecture for low density parity check decoding
A low density parity check (ldpc) decoder integrated on a single semiconductor substrate may comprise one or more arrays of first-type memory cells and one or more arrays of second-type memory cells. The ldpc decoder may be configured to store intrinsic messages in the array of first-type cells and to store extrinsic messages in the array of second-type cells.
07/17/14
20140198590
Multiport memory with matching address control
In a multiple port sram, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A second bit cell is coupled to the first and second word lines and a third and fourth bit line pair.
07/17/14
20140198562
Ten-transistor dual-port sram with shared bit-line architecture
A 10-transistor dual-port sram with shared bit-line architecture includes a first memory cell and a second memory cell. The first memory cell has a first storage unit, a first switch set, and a second switch set.
07/17/14
20140198561
Multiport memory with matching address and data line control
In a multiple port sram, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic.
07/10/14
20140191338
Semiconductor device and method for manufacturing same
In a region just below an access gate electrode in an sram memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region.
07/10/14
20140191330
Finfet and method of fabrication
An improved finfet and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon.
07/03/14
20140185369
Sense amplifier scheme for low voltage sram and register files
In at least one embodiment, a sense amplifier circuit includes a bit line, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the bit line and includes an nmos transistor coupled between a power node and the bit line.
07/03/14
20140185367
Sram bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter
Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch.
07/03/14
20140185366
Pre-charge tracking of global read lines in high speed sram
In embodiments of the invention, a memory circuit includes a static random access memory (sram), rows of m sense amplifiers, a global read precharge tracking control circuit controlling a precharge of global read lines, a sense amplifier output tracking circuit generating a reset sense amplifier signal for the sense amplifier control circuits, and a read delay circuit generating a trigger signal for the global read precharge tracking control circuit and the sense amplifier output tracking circuit and performing a fixed delay tracking of a read operation in a read cycle. A dummy global read line is coupled to the global read precharge tracking control circuit and returns from a half way to the top of the sram forming a tracking dummy global read line that determines a completion of the precharge of the global read lines before the sense amplifiers start discharging the global read lines in the read cycle..
07/03/14
20140185365
Dual-port sram connection structure
The present disclosure provides a static random access memory (sram) cell. The sram cell includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least two pull-down devices; at least four pass gate devices configured with the two cross-coupled inverters; at least two ports coupled with the at least four pass-gate devices for reading and writing; a first contact feature contacting first two pull-down devices (pd-11 and pd-12) of the first inverter; and a second contact feature contacting second two pull-down devices (pd-21 and pd-22) of the second inerter..
07/03/14
20140185364
Methods and apparatus for designing and constructing multi-port memory circuits
Static random access memory (sram) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6t) sram memory cell is proposed.
06/26/14
20140177349
Shared integrated sleep mode regulator for sram memory
Embodiments are described for a method for regulating sleep mode of a plurality of sub-banks in an sram array by isolating all of the sub-banks from a regulator upon access to at least one sub-bank that causes the accessed sub-bank to go to an operating voltage, and isolating the accessed sub-bank from non accessed sub-banks, while maintaining a sleep voltage on a load memory array and each of the sub-banks through the regulator; comparing a voltage on the non accessed sub-banks to a voltage output of the regulator; and providing a sleep voltage level to all of the sub-banks through the regulator when the voltage on the non accessed sub-banks is less than the sleep voltage.. .
06/26/14
20140177323
Bit-flipping in memories
Data stored in sram cells are periodically flipped e.g., before long idle periods. Operating the memories in both a ‘flipped’ mode and a ‘non-flipped’ mode helps cause the bias temperature instability (bti) degradation to be symmetric, thereby not degrading the static noise margin (snm) degradation of the cells.


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Sram topics: Random Access, Static Random Access Memory, Memory Cell, Semiconductor, Memory Cells, Transistors, Semiconductor Memory, Memory Device, Integrated Circuit, Robustness, Field Effect Transistor, Clamping Circuit, Internal Node, Implantation, Data Storage

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