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Date/App# patent app List of recent Sram-related patents
04/17/14
20140104960
 Methods and apparatus for designing and constructing high-speed memory circuits patent thumbnailnew patent Methods and apparatus for designing and constructing high-speed memory circuits
Static random access memory (sram) circuits are used in most digital integrated circuits to store digital data bits. Sram memory circuits are generally read by decoding an address, reading from an addressed memory cell using a set of bit lines, outputting data from the read memory cell, and precharging the bit lines for a subsequent memory cycle.
04/17/14
20140104946
 On-chip hv and lv capacitors acting as the second back-up supplies for nvsram auto-store operation patent thumbnailnew patent On-chip hv and lv capacitors acting as the second back-up supplies for nvsram auto-store operation
Two on-chip capacitors including one hv capacitor vppcap and one lv vcc capacitor vcccap are built over a nvsram memory chip as a back-up second power supplies for each nvsram cell, regardless of 1-poly, 2-poly, pmos or nmos flash cell structures therein. The on-chip hv and lv capacitors are preferably made from one or more mim or mip layers for achieving required capacitance.
04/17/14
20140103960
 Programmable logic device patent thumbnailnew patent Programmable logic device
To obtain a pld that achieves high-speed configuration capable of dynamic configuration, consumes less power, and has a short startup time and a pld that has a smaller number of transistors or a smaller circuit area than a pld using an sram as a configuration memory, a plurality of logic elements arranged in an array and a switch for selecting electrical connection between the logic elements are provided. The switch includes a first transistor including a multilayer film including an oxide layer and an oxide semiconductor layer, a node that becomes floating when the first transistor is turned off, and a second transistor in which electrical continuity between a source and a drain is determined based on configuration data held at the node..
04/17/14
20140103445
 Semiconductor sram structures and fabrication methods patent thumbnailnew patent Semiconductor sram structures and fabrication methods
Various embodiments provide semiconductor structures and their fabrication methods. An sram memory cell can include at least one semiconductor structure, and an sram memory can include at least one sram memory cell.
04/10/14
20140099758
 Sram devices utilizing strained-channel transistors and methods of manufacture patent thumbnailSram devices utilizing strained-channel transistors and methods of manufacture
A novel sram memory cell structure and method of making the same are provided. The sram memory cell structure comprises strained pmos transistors formed in a semiconductor substrate.
04/10/14
20140098596
 8-transistor dual-ported static random access memory patent thumbnail8-transistor dual-ported static random access memory
An 8-transistor sram (static random access memory) storage cell provides differential read bit lines that are precharged to a low voltage level for read operations. The 8-transistor storage cell provides separate ports for read and write operations, including differential read bit lines.
04/03/14
20140092696
 Power management domino sram bit line discharge circuit patent thumbnailPower management domino sram bit line discharge circuit
A domino static random access memory (sram) having one or more sram memory cells connected with a local bit line is disclosed. The sram may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line.
04/03/14
20140092675
 Two-port sram write tracking scheme patent thumbnailTwo-port sram write tracking scheme
A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit further includes a second transistor configured to pre-charge a read bit line connected to the at least two memory cells.
04/03/14
20140092674
 Circuits and methods of a self-timed high speed sram patent thumbnailCircuits and methods of a self-timed high speed sram
Circuits and methods for precisely self-timed sram memory are disclosed to track the wordline and/or bitline/bitline bar (bl/blb) propagation delays. At least one reference cell can be placed near the far end of a driver to drive a selected wordline or a reference wordline.
04/03/14
20140092673
 Memory cell patent thumbnailMemory cell
This invention relates generally to a memory cell. The embodiments of the present invention provide a sram cell and a sram cell array comprising such sram cell.
04/03/14
20140092672
Power management domino sram bit line discharge circuit
A domino static random access memory (sram) having one or more sram memory cells connected with a local bit line is disclosed. The sram may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line.
04/03/14
20140091396
Pass gate, semiconductor memory, and semiconductor device
According to one embodiment, a pass gate provided between a data holding unit of an sram cell and a bit line, includes a first tunnel transistor and a first diode connected in series between the data holding unit and the bit line, and a second tunnel transistor and a second diode connected in series between the data holding unit and the bit line and connected in parallel to the first tunnel transistor and the first diode. Gate electrodes of the first tunnel transistor and the second tunnel transistor are connected to a word line.
03/27/14
20140085978
Method and architecture for improving defect detectability, coupling area, and flexibility of nvsram cells and arrays
Several preferred embodiments of 1s1f 16t nvsram, 1s1f 20t nvsram, 1s2f 22t nvsram, 1s2f 14t nvsram cells are proposed, regardless of 1-poly, 2-poly, pmos or nos flash cell structures. Two separate sourcelines for the paired flash strings are also proposed for easy adding ability for the nvsram circuit to detect the marginally erased vt0 and marginally programmed vt1 of the paired flash cell.
03/20/14
20140078819
Static random access memory cell with single-sided buffer and asymmetric construction
Balanced electrical performance in a static random access memory (sram) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors.
03/20/14
20140078817
Integrated circuits with sram cells having additional read stacks and methods for their fabrication
Integrated circuits that include sram cells having additional read stacks and methods for their fabrication are provided. In accordance with one embodiment a method for fabricating such an integrated circuit includes forming a plurality of sram cells in and on a semiconductor substrate, each of the plurality of sram cells including a read pull down transistor and a read pass gate transistor.
03/20/14
20140078806
Channel hot carrier tolerant tracking circuit for signal development on a memory sram
An embodiment of the invention discloses an electronic device for reducing degradation in nmos circuits in a tracking circuit. A first multiplexer selects, based on n bits from a row address in a memory array, which tracking circuit from a group of 2n tracking circuits will be used to provide a signal develop time for a memory cell in the memory array using a dummy word line signal.
03/20/14
20140077380
Bit cell with double patterned metal layer structures
An approach for providing sram bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof.
03/13/14
20140071736
Testing signal development on a bit line in an sram
An embodiment of the invention discloses a method for testing a memory cell in an sram. The number of dummy memory cells on a single dummy word line used to drive the dummy bit lines is selected.
03/13/14
20140071735
Initializing dummy bits of an sram tracking circuit
An embodiment of the invention discloses a method for writing concurrently a binary logical value to one or more dummy memory cells in a dummy bit line pair. A diode is electrically connected between a power supply and the positive power supply line connected to the dummy memory cells.
03/13/14
20140070212
Semiconductor device having capability of generating chip identification information
A semiconductor device having a capability of generating chip identification information includes: an sram macro having a plurality of memory cells arranged in rows and columns; a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.. .
03/06/14
20140068145
Sram handshake
Various exemplary embodiments relate to an integrated circuit including: a rf interface; a wired interface connectable to a host; a volatile memory having a first block and a last block configured to store data transferred between the rf interface and the wired interface; and a memory controller configured to detect when the last block of the volatile memory has been written and to indicate that the volatile memory is ready to read. Various exemplary embodiments relate to a method performed by a tag including: determining that data is to be received on the first interface; blocking the second interface; writing data from the first interface to a volatile memory; detecting that the last block of the volatile memory has been written; unblocking the second interface; indicating that data is available for reading; blocking the first interface; and reading data from the volatile memory to the second interface..
03/06/14
20140063986
Sram local evaluation and write logic for column selection
An sram includes a first sram column having first sram cells and a first local evaluation logic coupled to a global bit line and a second sram column having second sram cells and a second local evaluation logic coupled to the same global bit line. The first sram column is selected with a first write line and the second sram column is selected with a second write line..
03/06/14
20140063920
Static random access memory that initializes to pre-determined state
A static random access memory (sram) is provided for establishing an initialization state. The sram connects to a plurality of signal lines including a bit line and an inverse bit line.
03/06/14
20140063919
Multiple-port sram device
A method for providing a sram cell having a dedicated read port separated from a write port includes providing a first and a second bit-line placed in parallel forming a complementary bit-line pair for the dedicated read port, and providing a third and a fourth bit-line placed in parallel forming a complementary bit-line pair for the write port. The method further includes providing a positive voltage supply line disposed between a first and a second ground line placed in parallel, providing a first and a second metal line adjacently flanking and in parallel to the first bit-line, and providing a third and a fourth metal line adjacently flanking and in parallel to the second bit-line to provide a new sram cell structure having a balanced read and write operation speed and an improved noise margin..
03/06/14
20140063918
Control circuit of sram and operating method thereof
A control circuit of sram and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit.
03/06/14
20140063916
Sram local evaluation logic for column selection
An sram includes a first sram column having first sram cells and a first local evaluation logic coupled to a global bit line and a second sram column having second sram cells and a second local evaluation logic coupled to the same global bit line. The first sram column is selected with a first column select line and the second sram column is selected with a second column select line..
03/06/14
20140061809
Semiconductor device
There is provided a semiconductor device comprising, at least one sram cell, wherein the sram cell includes a pull-up transistor, a pull-down transistor, and a pass-gate transistor, and an inversion-layer thickness (tinv) of a gate stack of the pass-gate transistor is different from tinv of a gate stack of the pull-up transistor and tinv of a gate stack of the pull-down transistor.. .
03/06/14
20140061808
Pass gate and semiconductor storage device having the same
According to an embodiment, a semiconductor storage device includes an sram cell. The sram cell includes first and second transfer gates each comprising a pass gate.
02/27/14
20140056050
Memory cell and memory
In various embodiments, a memory cell and a memory are provided. The memory cell comprises a static random access memory (sram) cell including a reset-set (rs) flip-flop and a read only memory (rom) cell being connected (or coupled) to the sram cell to set logic states of internal latch nodes of the rs flip-flop when the rom cell is triggered.
02/27/14
20140054716
Sram cells with dummy insertions
A device includes a first pull-up transistor, a second pull-up transistor, and a dummy gate electrode between the first and the second pull-up transistors. The first and the second pull-up transistors are included in a first static random access memory (sram) cell..
02/20/14
20140052954
System translation look-aside buffer with request-based allocation and prefetching
A system tlb accepts translation prefetch requests from initiators. Misses generate external translation requests to a walker port.
02/20/14
20140052898
Method for mapping management
A method for mapping management is disclosed. The steps of the method comprises sending data from a host; programming a host data a non-volatile storage device; updating a mapping address to a physical entry to logical (pe2l) mapping table stored in a sram; updating a physical entry (pe) status table; checking if the pe2l mapping table is full; if no, loop to the step of programming a non-violate storage device; if yes, remove invalid entries in the pe2l mapping table and update the pe status table, and then run next step; transferring part of the pe2l mapping table to a logical to physical (l2p) mapping table stored in the non-volatile storage device; and programming the l2p mapping table to the non-volatile storage device and looping to the step of removing invalid entries in the pe2l mapping table and updating the pe status table..
02/20/14
20140050033
Memory cell assembly including an avoid disturb cell
A memory array assembly and a method for performing a write operation without disturbing data stored in other sram cells are provided. The memory array assembly comprises a plurality of sram cells, a plurality of avoid-disturb cells, a plurality of sense amplifiers and a plurality of write drivers.
02/20/14
20140050025
Low-voltage fast-write pmos nvsram cell
This invention discloses a low-voltage fast-write 12t or 14t pmos nvsram cell structure which comprises a 6t lv sram cell and one pairs of two 3t or 4t hv pmos flash strings. Due to reverse threshold voltage definition of pmos and nmos flash cell, this pmos nvsram cell has the advantage over the nmos nvsram cell to have the same data polarity between sram and flash pairs during the data writing operation.
02/20/14
20140050017
Device comprising a plurality of static random access memory cells and method of operation thereof
A method comprises writing data to one or more static random access memory (sram) cells. Writing data to the one or more sram cells comprises applying a first data signal to at least one bit line electrically connected to the one or more sram memory cells, electrically disconnecting at least one of a first power supply terminal and a second power supply terminal of each of the one or more sram cells from a power supply and applying a word line signal to a word line electrically connected to the one or more sram cells.
02/13/14
20140047284
Combo static flop with full test
A sram (static random access memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit.
02/13/14
20140043925
Ddr psram and data writing and reading methods thereof
A double data rate pseudo sram (ddr psram) is provided. The ddr psram includes a data receiver, a memory and an address decoder.
02/13/14
20140043922
Method of providing write recovery protection in psram and related device
A method of operating a psram includes selecting a bit on a word line of the psram, keeping the word line on for a first predetermined duration after selecting the bit, writing a data into the bit in response to a write command, and keeping the word line on for a second predetermined duration after the write command ends.. .
02/13/14
20140043889
Time processing method and circuit for synchronous sram
A timing processing method and a circuit for a synchronous sram are provided. The method includes: directly inputting an address signal to a wordline decoder for logic decoding; generating various signals by setting various devices in terms of timing; and performing sensitive amplification on data that is input by a memory cell array and is selected by a bitline, and then outputting the data, that is, generating a data output signal.
02/13/14
20140043888
Method of operating psram and related memory device
The latency of a psram is set according to its current state when receiving an external command. If the psram is not executing a specific operation or has completed the specific operation while meeting corresponding timing parameters, the psram is configured to execute the external command with a first latency.
02/13/14
20140042551
Sram integrated circuits with buried saddle-shaped finfet and methods for their fabrication
Sram ics and methods for their fabrication are provided. One method includes depositing photoresist on a first oxide layer overlying a silicon substrate, forming a pattern of locations, using said photoresist, for the formation of two inverters, each having a pull up transistor, a pull down transistor, and a pass gate transistor on said oxide layer.
02/06/14
20140036609
Testing retention mode of an sram array
An embodiment of the invention discloses a method for testing the retention mode of an array of sram cells. A data pattern is written to the array.
02/06/14
20140036581
Sense amplifier for static random access memory
A sense amplifier for a static random access memory (sram) is described. In one embodiment, a first pass gate transistor is driven by a bit line true associated with an sram cell.
02/06/14
20140036579
Sense amplifier
Embodiments of the invention provide a sense amplifier, a sram chip comprising the sense amplifier and a method of performing read operation on the sram chip. The sense amplifier according to embodiments of the invention comprises an additional driving assist portion, which further takes a global data bus as input, the driving assist portion is configured to enable the sense amplifier to provide assisted driving for other sense amplifiers.
02/06/14
20140036578
Sram read preferred bit cell with write assist circuit
Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node.
02/06/14
20140035056
Sram cell connection structure
A static random access memory (sram) cell includes a first pull-up transistor and a second pull-up transistor, and a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor. A conductive feature includes a first leg having a first longitudinal direction, wherein the first leg interconnects a drain of the first pull-up transistor and a drain of the first pull-down transistor.
01/30/14
20140029333
Five transistor sram cell
A five transistor static random-access-memory (sram) cell is disclosed which can be made part of an sram array to provide an improved reduction in size. The cell includes two cross-coupled inverters, each having two complementary transistors, and an n-channel transistor switch connected to a bit line (bl) and a word line (wl).
01/30/14
20140027851
Body contacts for fet in soi sram array
Contact with a floating body of an fet in soi may be formed in a portion of one of the two diffusions of the fet, wherein the portion of the diffusion (such as n−, for an nfet) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body fets, wherein the diffusion does not extend all the way to box, hence the linked body (such as p−) extends under the diffusion where the contact is being made.
01/30/14
20140027839
Sram devices and methods of manufacturing the same
Example embodiments relate to an sram device and a method of manufacturing the same. The sram device may include first transistors operating in a horizontal direction and second transistors that are disposed on the first transistors to operate in a vertical direction.
01/23/14
20140025974
Information processing apparatus, server and method of controlling the same
A periodic update time is saved on an sram 213 and an auto-shutdown time is saved on the sram 213. When the saved auto-shutdown time is reached, if the periodic update time is set to a time that is after auto-shutdown, a shutdown is not performed, a return time is set to a time that is before the periodic update time, and a sleep mode is entered.
01/23/14
20140022858
Method of controlling a refresh operation of psram and related device
A plurality of refresh requests are generated at a predetermined period shorter than the longest time during which a psram is able to retain a data without being refreshed. For two consecutive first and second refresh requests, the second refresh request is ignored if the interval between the first and the second refresh requests is not larger than a predetermined duration.
01/16/14
20140019678
Disk subsystem and method for controlling memory access
In a prior art disk subsystem formed by duplicating a shared memory (sm) in a dram (first area) and a sram (second area) having a higher speed than the dram, the data stored in the sram cannot be switched collectively while maintaining access to the sm, so that the access performance was deteriorated. According to the present invention, when there is a change in setting of data stored in a second area (sram), a data corresponding to the setting after the change is stored from a first area (dram) of a slave surface side sm to the second area (sram), and the setting of data of the second area (sram) is changed.
01/16/14
20140016403
Semiconductor memory device
In a loadless 4t-sram constituted using vertical-type transistor sgts, a small sram cell area is realized. In a static memory cell constituted using four mos transistors, the mos transistors are sgts formed on a bulk substrate in which the drains, gates, and sources are arranged in the vertical direction.
01/16/14
20140016402
Sram bit cell with reduced bit line pre-charge voltage
An sram bit cell comprises a first inverter including a pmos transistor and an nmos transistor, and a second inverter including a pmos transistor and an nmos transistor. The first and second inverters are cross-coupled to each other.
01/16/14
20140016400
Word line driver circuits and methods for sram bit cell with reduced bit line pre-charge voltage
A memory device comprising a plurality of static random access memory (sram) bit cells, and a word line driver coupled to provide a word line signal to the bit cells. The word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted, and the word line signal is coupled between a positive supply voltage (vdd) and a supply voltage below ground (vn)..
01/09/14
20140013039
Adaptive memory system for enhancing the performance of an external computing device
An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., static random access memory or sram), a second memory type (e.g., dynamic random access memory or dram), a third memory type (e.g., flash), an internal bus system, and an external bus interface.
01/09/14
20140010032
Read-current and word line delay path tracking for sense amplifier enable timing
A static random-access memory (sram) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write sram cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells.
01/09/14
20140010001
Semiconductor device having memory cell with electrostatic capacitance circuit
A capacitance coupled to a memory node and a word line of an sram cell provides an electrostatic capacitance between the memory node and the word line. The capacitance has a first electrostatic capacitance when the word line is in a nonselective state (usually a low level) and the memory node retains a high level; the capacitance has a second electrostatic capacitance which is smaller than the first electrostatic capacitance when the word line is in the nonselective state (usually the low level) and the memory node retains the low level..
01/09/14
20140010000
Apparatus and method for improving power delivery in a memory, such as, a random access memory
Embodiments of an apparatus and method to improve power delivery including a pre-charge circuit that may include a first voltage supply rail configured to provide a first voltage amount to perform a first phase of a pre-charge of a bit line and a second voltage supply rail configured to provide a second voltage amount to perform a second phase of the pre-charge of the bit line are described herein. In embodiments, the pre-charge circuit may be a pre charge circuit for a static random-access memory (sram) memory cell..
01/09/14
20140008793
Semiconductor device
To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an lcd driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an lcd driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but srams (internal circuits) are arranged..
01/02/14
20140005967
Methods and systems for characterizing and identifying electronic devices
The present disclosure provides a method and a system for characterizing and identifying an electronic device using a physical fingerprint. In one aspect, the characterizing method includes determining the physical fingerprint of a test device using selected memory cells of an sram array in the test device, and storing data associated with the physical fingerprint in a database.
01/02/14
20140003136
Transistor with reduced charge carrier mobility and associated methods
One or more embodiments relate to a method comprising: raising a potential of a first bit line and a second bit line; switching on a first n-channel access transistor coupled between the first bit line and a first node of a first inverter; switching on a second n-channel access transistor coupled between the second bit line and a second node of a second inverter; and reading a static random access memory (sram) cell including the first inverter and the second inverter by sensing a potential on the first bit line and a potential on the second bit line.. .
01/02/14
20140003135
Sram bitcell implemented in double gate technology
An sram bitcell includes first and second cmos inverters connected as a latch defining a true node and a complement node. The bitcell further includes true and complement bitline nodes.
01/02/14
20140003133
Sram layouts
Roughly described, the cell layout in an sram array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area.
01/02/14
20140002199
Ring oscillator and semiconductor device
A ring oscillator includes a plurality of ring-connected delay circuits. At least one of the plurality of delay circuits has an sram cell and a path circuit connected in parallel to the sram cell.
01/02/14
20140001601
Method of reducing current leakage in a device and a device thereby formed
A method of reducing current leakage in unused circuits performed during semiconductor fabrication and a semiconductor device or integrated circuit thereby formed. The method involves modifying a characteristic of at least one idle circuit that is unused in a product variant, to inhibit the circuit and reduce current leakage therefrom upon powering as well as during operation.
12/26/13
20130343136
Sram with buffered-read bit cells and its testing
An sram with buffered-read bit cells is disclosed (figs. 1-6).
12/26/13
20130341726
Mos transistor, formation method thereof, and sram memory cell circuit
Various embodiments provide an mos transistor, a formation method thereof, and an sram memory cell circuit. An exemplary mos transistor can include a semiconductor substrate including a first groove on one side of a gate structure and a second groove on the other side of the gate structure.
12/26/13
20130341642
Mos transistor, fabrication method thereof, and sram memory cell circuit
Various embodiments provide an mos transistor, a formation method thereof, and an sram memory cell circuit. An exemplary mos transistor can include a channel region including an asymmetric stressing layer having a stress gradually varied from a compressive stress to a tensile stress or from a tensile stress to a compressive stress from a first end of the channel region adjacent to a source region to a second end of the channel region adjacent to a drain region.
12/19/13
20130339588
System on chip with reconfigurable sram
A system on chip includes a random access memory, a read-only memory, and a processor. The processor is configured to, during a development phase of the system on chip, read program code from the random access memory and execute the program code.


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Sram topics: Random Access, Static Random Access Memory, Memory Cell, Semiconductor, Memory Cells, Transistors, Semiconductor Memory, Memory Device, Integrated Circuit, Robustness, Field Effect Transistor, Clamping Circuit, Internal Node, Implantation, Data Storage

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