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Sram

Sram-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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NEW Signal timing alignment based on a common data strobe in memory devices configured for stacked ...
Iii Holdings 2, Llc
January 18, 2018 - N°20180019012

Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, rerams, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a dram is adjusted based on the spid of that device. In ...
NEW Vehicle-mounted control device, program writing device, program generating device and program
Hitachi Automotive Systems, Ltd.
January 18, 2018 - N°20180018164

The present invention provides a vehicle-mounted control device, a program writing device, a program generating device, and a program, which are capable of quickly and easily carrying out reprogramming. An ecu 300 is provided with: a microcomputer 301, an sram 302, a flash memory 303, and a communication device 305. The flash memory 303 is configured from a plurality of blocks and stores older versions of ...
Stable and reliable finfet sram with improved beta ratio
Globalfoundries Inc.
January 11, 2018 - N°20180012895

Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of ...
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Dual-port sram connection structure
Taiwan Semiconductor Manufacturing Company, Ltd.
January 11, 2018 - N°20180012650

The present disclosure provides a static random access memory (sram) cell. The sram cell includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least two pull-down devices; at least four pass gate devices configured with the two cross-coupled inverters; at least two ports coupled with the at least four pass-gate ...
Static random access memory (sram) assist circuit
Globalfoundries Inc.
January 11, 2018 - N°20180012648

The present disclosure relates to semiconductor structures and, more particularly, to a static random access memory assist circuit and methods of implementation and manufacture. The structure includes at least one static random access memory (sram) cell and a read assist circuit structured to apply a negative voltage to the at least one sram cell upon asserting of a wordline of ...
Methods, apparatus and system for providing nmos-only memory cells
Globalfoudries Inc.
January 11, 2018 - N°20180012647

At least one method, apparatus and system disclosed involves a memory device having a memory cell comprising nmos only transistors. An sram bit cell comprises a first pass gate (pg) nmos transistor coupled to a first bit line signal and a word line signal; a second pg nmos transistor coupled to a second bit line signal and the word line ...
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Sense amplifier in low power and high performance sram
Texas Instruments Incorporated
January 04, 2018 - N°20180005693

A static random access memory (sram) includes an array of storage cells and a first sense amplifier. The array of storage cells is arranged as rows and columns. The rows correspond to word lines and the columns correspond to bit lines. The first sense amplifier includes a first transistor and a second transistor. The first sense amplifier is configured to ...
Within-die special oscillator for tracking sram memory performance with global process variation, voltage and temperature
Qualcomm Incorporated
January 04, 2018 - N°20180004689

An apparatus includes a memory, a timing circuit configured to emulate a first operation of the memory to activate a second operation of the memory, a sensor configured to emulate a portion of the timing circuit, and a controller configured to adjust an operating parameter of the memory based on the sensor emulating the portion of the timing circuit. A ...
Method for performing multiple enrollments of a physically uncloneable function
Nxp B.v.
January 04, 2018 - N°20180004444

A data processing system having a puf and method for providing multiple enrollments, or instantiations, of the puf are provided. A puf segment includes a plurality of sram cells on an integrated circuit. A puf response from the puf segment is used to create a first activation code and a first puf key. A second puf key may be created ...
Physical unclonable function using augmented memory for challenge-response hashing
The Regents Of The University Of Michigan
December 28, 2017 - N°20170373862

A technique is presented for performing a physical unclonable function (puf) using an array of sram cells. The technique can be viewed as an attempt to read multiple cells in a column at the same time, creating contention that is resolved according to process variation. An authentication challenge is issued to the array of sram cells by activating two or ...
Static random-access memory (sram) cell array
United Microelectronics Corp.
December 28, 2017 - N°20170373073

A static random-access memory (sram) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each pg (pass-gate) finfet shares at least one of the active fins with a pd (pull-down) finfet, and at least one ...
Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can ...
December 28, 2017 - N°20170372794

A semiconductor device that has a normal mode of operation and a test mode of operation and can include: a first circuit that generates at least one assist signal having an assist enable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access ...
Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can ...
December 28, 2017 - N°20170372793

A method of operating a semiconductor device that has a normal mode of operation and a test mode of operation, can include: generating at least one assist signal in the normal mode of operation wherein, when the at least one assist signal has a first assist logic level, the at least one assist signal alters a read operation or a ...
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Semiconductor devices, circuits and methods for read and/or write assist of an sram circuit ...
December 28, 2017 - N°20170372776

A semiconductor device can include a voltage detector circuit configured to generate a first potential that is essentially proportional to a first power supply potential and to provide a first and second voltage window signal by comparing the first potential to a first and second reference potential. The voltage window signals indicate voltage windows in which the first power supply ...
Semiconductor devices, circuits and methods for read and/or write assist of an sram circuit ...
December 28, 2017 - N°20170372775

A method of operating a semiconductor device powered by a first power supply potential can include: generating an assist signal with an enable logic level in response to a voltage window detection circuit indicating the first power supply potential is in a first voltage window at a lower end of an operating range of the semiconductor device and generating the ...
Semiconductor devices, circuits and methods for read and/or write assist of an sram circuit ...
December 28, 2017 - N°20170372774

A semiconductor device powered by a first power supply potential, can include a voltage detector circuit coupled to receive the first power supply potential and configured to provide at least one voltage window signal, the at least one voltage window signal indicating a predetermined voltage window in which the first power supply potential is located; an assist control circuit configured ...
Semiconductor devices, circuits and methods for read and/or write assist of an sram circuit ...
December 28, 2017 - N°20170372773

A method of operating a semiconductor device that is powered by a first power supply potential can include detecting a change in at least one voltage window signal, the voltage window signal indicates a predetermined voltage window in which a potential of the first power supply potential is located; latching the at least one voltage window signal to provide at ...
Ring oscillator built from sram cells interconnected via standard cell-interface
Marvell World Trade Ltd.
December 21, 2017 - N°20170365332

An integrated circuit (ic) includes a memory, circuit interconnections and control logic. The memory includes multiple standard-library static random access memory (sram) cells disposed on a substrate of the ic in multiple first layers, so that access to a respective sram cell to read and write data is through a cell-interface. The circuit interconnections, fabricated in one or more second ...
Design/technology co-optimization platform for high-mobility channels cmos technology
International Business Machines Corporation
December 21, 2017 - N°20170364623

Embodiments of the present invention may provide the capability to design sram cells may be designed that is compatible with the requirements of ingaas integration by selective epitaxy in sio2 cavities without sacrificing density and area scaling. In an embodiment of the present invention, a computer-implemented method for designing a hybrid integrated circuit may comprise receiving data representing a layout ...
Sram arrays and methods of manufacturing same
Taiwan Semiconductor Manufacturing Company, Ltd.
December 14, 2017 - N°20170358343

An embodiment static random access memory (sram) array includes a first sram mini array having a first plurality of functional sram cells in a first column of the sram array. Each of the first plurality of functional sram cells share a first bit line (bl). The sram array further includes a second sram mini array having a second plurality of ...
Method and device for finfet sram
Semiconductor Manufacturing International (beijing) Corporation
December 07, 2017 - N°20170352668

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of the trenches; forming a high-k dielectric layer on the interface ...
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