|| List of recent Sram-related patents
| Sram handshake|
Various exemplary embodiments relate to an integrated circuit including: a rf interface; a wired interface connectable to a host; a volatile memory having a first block and a last block configured to store data transferred between the rf interface and the wired interface; and a memory controller configured to detect when the last block of the volatile memory has been written and to indicate that the volatile memory is ready to read. Various exemplary embodiments relate to a method performed by a tag including: determining that data is to be received on the first interface; blocking the second interface; writing data from the first interface to a volatile memory; detecting that the last block of the volatile memory has been written; unblocking the second interface; indicating that data is available for reading; blocking the first interface; and reading data from the volatile memory to the second interface..
| Sram local evaluation and write logic for column selection|
An sram includes a first sram column having first sram cells and a first local evaluation logic coupled to a global bit line and a second sram column having second sram cells and a second local evaluation logic coupled to the same global bit line. The first sram column is selected with a first write line and the second sram column is selected with a second write line..
| Static random access memory that initializes to pre-determined state|
A static random access memory (sram) is provided for establishing an initialization state. The sram connects to a plurality of signal lines including a bit line and an inverse bit line.
| Multiple-port sram device|
A method for providing a sram cell having a dedicated read port separated from a write port includes providing a first and a second bit-line placed in parallel forming a complementary bit-line pair for the dedicated read port, and providing a third and a fourth bit-line placed in parallel forming a complementary bit-line pair for the write port. The method further includes providing a positive voltage supply line disposed between a first and a second ground line placed in parallel, providing a first and a second metal line adjacently flanking and in parallel to the first bit-line, and providing a third and a fourth metal line adjacently flanking and in parallel to the second bit-line to provide a new sram cell structure having a balanced read and write operation speed and an improved noise margin..
| Control circuit of sram and operating method thereof|
A control circuit of sram and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit.
| Sram local evaluation logic for column selection|
An sram includes a first sram column having first sram cells and a first local evaluation logic coupled to a global bit line and a second sram column having second sram cells and a second local evaluation logic coupled to the same global bit line. The first sram column is selected with a first column select line and the second sram column is selected with a second column select line..
| Semiconductor device|
There is provided a semiconductor device comprising, at least one sram cell, wherein the sram cell includes a pull-up transistor, a pull-down transistor, and a pass-gate transistor, and an inversion-layer thickness (tinv) of a gate stack of the pass-gate transistor is different from tinv of a gate stack of the pull-up transistor and tinv of a gate stack of the pull-down transistor.. .
| Pass gate and semiconductor storage device having the same|
According to an embodiment, a semiconductor storage device includes an sram cell. The sram cell includes first and second transfer gates each comprising a pass gate.
|Memory cell and memory|
In various embodiments, a memory cell and a memory are provided. The memory cell comprises a static random access memory (sram) cell including a reset-set (rs) flip-flop and a read only memory (rom) cell being connected (or coupled) to the sram cell to set logic states of internal latch nodes of the rs flip-flop when the rom cell is triggered.
|Sram cells with dummy insertions|
A device includes a first pull-up transistor, a second pull-up transistor, and a dummy gate electrode between the first and the second pull-up transistors. The first and the second pull-up transistors are included in a first static random access memory (sram) cell..
|System translation look-aside buffer with request-based allocation and prefetching|
A system tlb accepts translation prefetch requests from initiators. Misses generate external translation requests to a walker port.
|Method for mapping management|
A method for mapping management is disclosed. The steps of the method comprises sending data from a host; programming a host data a non-volatile storage device; updating a mapping address to a physical entry to logical (pe2l) mapping table stored in a sram; updating a physical entry (pe) status table; checking if the pe2l mapping table is full; if no, loop to the step of programming a non-violate storage device; if yes, remove invalid entries in the pe2l mapping table and update the pe status table, and then run next step; transferring part of the pe2l mapping table to a logical to physical (l2p) mapping table stored in the non-volatile storage device; and programming the l2p mapping table to the non-volatile storage device and looping to the step of removing invalid entries in the pe2l mapping table and updating the pe status table..
|Memory cell assembly including an avoid disturb cell|
A memory array assembly and a method for performing a write operation without disturbing data stored in other sram cells are provided. The memory array assembly comprises a plurality of sram cells, a plurality of avoid-disturb cells, a plurality of sense amplifiers and a plurality of write drivers.
|Low-voltage fast-write pmos nvsram cell|
This invention discloses a low-voltage fast-write 12t or 14t pmos nvsram cell structure which comprises a 6t lv sram cell and one pairs of two 3t or 4t hv pmos flash strings. Due to reverse threshold voltage definition of pmos and nmos flash cell, this pmos nvsram cell has the advantage over the nmos nvsram cell to have the same data polarity between sram and flash pairs during the data writing operation.
|Device comprising a plurality of static random access memory cells and method of operation thereof|
A method comprises writing data to one or more static random access memory (sram) cells. Writing data to the one or more sram cells comprises applying a first data signal to at least one bit line electrically connected to the one or more sram memory cells, electrically disconnecting at least one of a first power supply terminal and a second power supply terminal of each of the one or more sram cells from a power supply and applying a word line signal to a word line electrically connected to the one or more sram cells.
|Combo static flop with full test|
A sram (static random access memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit.
|Ddr psram and data writing and reading methods thereof|
A double data rate pseudo sram (ddr psram) is provided. The ddr psram includes a data receiver, a memory and an address decoder.
|Method of providing write recovery protection in psram and related device|
A method of operating a psram includes selecting a bit on a word line of the psram, keeping the word line on for a first predetermined duration after selecting the bit, writing a data into the bit in response to a write command, and keeping the word line on for a second predetermined duration after the write command ends.. .
|Time processing method and circuit for synchronous sram|
A timing processing method and a circuit for a synchronous sram are provided. The method includes: directly inputting an address signal to a wordline decoder for logic decoding; generating various signals by setting various devices in terms of timing; and performing sensitive amplification on data that is input by a memory cell array and is selected by a bitline, and then outputting the data, that is, generating a data output signal.
|Method of operating psram and related memory device|
The latency of a psram is set according to its current state when receiving an external command. If the psram is not executing a specific operation or has completed the specific operation while meeting corresponding timing parameters, the psram is configured to execute the external command with a first latency.
|Sram integrated circuits with buried saddle-shaped finfet and methods for their fabrication|
Sram ics and methods for their fabrication are provided. One method includes depositing photoresist on a first oxide layer overlying a silicon substrate, forming a pattern of locations, using said photoresist, for the formation of two inverters, each having a pull up transistor, a pull down transistor, and a pass gate transistor on said oxide layer.
|Testing retention mode of an sram array|
An embodiment of the invention discloses a method for testing the retention mode of an array of sram cells. A data pattern is written to the array.
|Sense amplifier for static random access memory|
A sense amplifier for a static random access memory (sram) is described. In one embodiment, a first pass gate transistor is driven by a bit line true associated with an sram cell.
Embodiments of the invention provide a sense amplifier, a sram chip comprising the sense amplifier and a method of performing read operation on the sram chip. The sense amplifier according to embodiments of the invention comprises an additional driving assist portion, which further takes a global data bus as input, the driving assist portion is configured to enable the sense amplifier to provide assisted driving for other sense amplifiers.
|Sram read preferred bit cell with write assist circuit|
Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node.
|Sram cell connection structure|
A static random access memory (sram) cell includes a first pull-up transistor and a second pull-up transistor, and a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor. A conductive feature includes a first leg having a first longitudinal direction, wherein the first leg interconnects a drain of the first pull-up transistor and a drain of the first pull-down transistor.
|Five transistor sram cell|
A five transistor static random-access-memory (sram) cell is disclosed which can be made part of an sram array to provide an improved reduction in size. The cell includes two cross-coupled inverters, each having two complementary transistors, and an n-channel transistor switch connected to a bit line (bl) and a word line (wl).
|Body contacts for fet in soi sram array|
Contact with a floating body of an fet in soi may be formed in a portion of one of the two diffusions of the fet, wherein the portion of the diffusion (such as n−, for an nfet) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body fets, wherein the diffusion does not extend all the way to box, hence the linked body (such as p−) extends under the diffusion where the contact is being made.
|Sram devices and methods of manufacturing the same|
Example embodiments relate to an sram device and a method of manufacturing the same. The sram device may include first transistors operating in a horizontal direction and second transistors that are disposed on the first transistors to operate in a vertical direction.
|Information processing apparatus, server and method of controlling the same|
A periodic update time is saved on an sram 213 and an auto-shutdown time is saved on the sram 213. When the saved auto-shutdown time is reached, if the periodic update time is set to a time that is after auto-shutdown, a shutdown is not performed, a return time is set to a time that is before the periodic update time, and a sleep mode is entered.
|Method of controlling a refresh operation of psram and related device|
A plurality of refresh requests are generated at a predetermined period shorter than the longest time during which a psram is able to retain a data without being refreshed. For two consecutive first and second refresh requests, the second refresh request is ignored if the interval between the first and the second refresh requests is not larger than a predetermined duration.
|Disk subsystem and method for controlling memory access|
In a prior art disk subsystem formed by duplicating a shared memory (sm) in a dram (first area) and a sram (second area) having a higher speed than the dram, the data stored in the sram cannot be switched collectively while maintaining access to the sm, so that the access performance was deteriorated. According to the present invention, when there is a change in setting of data stored in a second area (sram), a data corresponding to the setting after the change is stored from a first area (dram) of a slave surface side sm to the second area (sram), and the setting of data of the second area (sram) is changed.
|Semiconductor memory device|
In a loadless 4t-sram constituted using vertical-type transistor sgts, a small sram cell area is realized. In a static memory cell constituted using four mos transistors, the mos transistors are sgts formed on a bulk substrate in which the drains, gates, and sources are arranged in the vertical direction.
|Sram bit cell with reduced bit line pre-charge voltage|
An sram bit cell comprises a first inverter including a pmos transistor and an nmos transistor, and a second inverter including a pmos transistor and an nmos transistor. The first and second inverters are cross-coupled to each other.
|Word line driver circuits and methods for sram bit cell with reduced bit line pre-charge voltage|
A memory device comprising a plurality of static random access memory (sram) bit cells, and a word line driver coupled to provide a word line signal to the bit cells. The word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted, and the word line signal is coupled between a positive supply voltage (vdd) and a supply voltage below ground (vn)..
|Adaptive memory system for enhancing the performance of an external computing device|
An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., static random access memory or sram), a second memory type (e.g., dynamic random access memory or dram), a third memory type (e.g., flash), an internal bus system, and an external bus interface.
|Read-current and word line delay path tracking for sense amplifier enable timing|
A static random-access memory (sram) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write sram cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells.
|Semiconductor device having memory cell with electrostatic capacitance circuit|
A capacitance coupled to a memory node and a word line of an sram cell provides an electrostatic capacitance between the memory node and the word line. The capacitance has a first electrostatic capacitance when the word line is in a nonselective state (usually a low level) and the memory node retains a high level; the capacitance has a second electrostatic capacitance which is smaller than the first electrostatic capacitance when the word line is in the nonselective state (usually the low level) and the memory node retains the low level..
|Apparatus and method for improving power delivery in a memory, such as, a random access memory|
Embodiments of an apparatus and method to improve power delivery including a pre-charge circuit that may include a first voltage supply rail configured to provide a first voltage amount to perform a first phase of a pre-charge of a bit line and a second voltage supply rail configured to provide a second voltage amount to perform a second phase of the pre-charge of the bit line are described herein. In embodiments, the pre-charge circuit may be a pre charge circuit for a static random-access memory (sram) memory cell..
To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an lcd driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an lcd driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but srams (internal circuits) are arranged..
|Methods and systems for characterizing and identifying electronic devices|
The present disclosure provides a method and a system for characterizing and identifying an electronic device using a physical fingerprint. In one aspect, the characterizing method includes determining the physical fingerprint of a test device using selected memory cells of an sram array in the test device, and storing data associated with the physical fingerprint in a database.
|Transistor with reduced charge carrier mobility and associated methods|
One or more embodiments relate to a method comprising: raising a potential of a first bit line and a second bit line; switching on a first n-channel access transistor coupled between the first bit line and a first node of a first inverter; switching on a second n-channel access transistor coupled between the second bit line and a second node of a second inverter; and reading a static random access memory (sram) cell including the first inverter and the second inverter by sensing a potential on the first bit line and a potential on the second bit line.. .
|Sram bitcell implemented in double gate technology|
An sram bitcell includes first and second cmos inverters connected as a latch defining a true node and a complement node. The bitcell further includes true and complement bitline nodes.
Roughly described, the cell layout in an sram array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area.
|Ring oscillator and semiconductor device|
A ring oscillator includes a plurality of ring-connected delay circuits. At least one of the plurality of delay circuits has an sram cell and a path circuit connected in parallel to the sram cell.
|Method of reducing current leakage in a device and a device thereby formed|
A method of reducing current leakage in unused circuits performed during semiconductor fabrication and a semiconductor device or integrated circuit thereby formed. The method involves modifying a characteristic of at least one idle circuit that is unused in a product variant, to inhibit the circuit and reduce current leakage therefrom upon powering as well as during operation.
|Sram with buffered-read bit cells and its testing|
An sram with buffered-read bit cells is disclosed (figs. 1-6).
|Mos transistor, formation method thereof, and sram memory cell circuit|
Various embodiments provide an mos transistor, a formation method thereof, and an sram memory cell circuit. An exemplary mos transistor can include a semiconductor substrate including a first groove on one side of a gate structure and a second groove on the other side of the gate structure.
|Mos transistor, fabrication method thereof, and sram memory cell circuit|
Various embodiments provide an mos transistor, a formation method thereof, and an sram memory cell circuit. An exemplary mos transistor can include a channel region including an asymmetric stressing layer having a stress gradually varied from a compressive stress to a tensile stress or from a tensile stress to a compressive stress from a first end of the channel region adjacent to a source region to a second end of the channel region adjacent to a drain region.
|System on chip with reconfigurable sram|
A system on chip includes a random access memory, a read-only memory, and a processor. The processor is configured to, during a development phase of the system on chip, read program code from the random access memory and execute the program code.
|Method for reading out multiple sram blocks with different column sizing in stitched cmos image senor|
A stitched image sensor array on a semiconductor substrate with identical blocks that have wherein said first configuration includes enable inputs, which vary a function of the block depending on the connection to the enable inputs. The enable inputs can set an sram to receive different numbers of inputs..
A well voltage supply cell includes third gate electrode group (including a third gate electrode corresponding to a first gate electrode) located symmetrically to first gate electrode group (including the first gate electrode constituting an access transistor) of a first sram cell, fourth gate electrode group (including a fourth gate electrode corresponding to a second gate electrode) located symmetrically to second gate electrode group (including the second gate electrode constituting an access transistor) of a second sram cell. A p-type impurity diffusion region located on a p well between the third gate electrode and the fourth gate electrode located opposite to each other, a first n-type impurity diffusion region located on the side of the third gate electrode closer to the first sram cell, and a second n-type impurity diffusion region located on the side of the fourth gate electrode closer to the second sram cell..
The sram memory cell includes a metal wiring line having a titanium or tantalum film in a bottom layer, and a via having a tungsten plug. The via is arranged on the metal line following a layout rule which permits the misalignment.
|Sige sram butted contact resistance improvement|
The present disclosure relates to a device and method for fabricating a semiconductor memory device arrangement comprising a butted a contact arrangement configured to couple two transistors, wherein an active area of a first transistor is coupled to an active gate of a second transistor. The active gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active area of the first transistor and an isolation layer formed about the first transistor.
|Semiconductor memory device and method for word line decoding and routing|
The invention discloses a semiconductor memory device and a method for word line decoding and routing. The present invention relates generally to semiconductor memory field, problems solved by the invention is that, to improve the quality of word line signals results in routing congestion.
|Semiconductor integrated circuit device|
A semiconductor integrated circuit device that detects an operation error of an sram caused by a device variation fluctuating with time is provided. In the sram, a memory cell has a transfer mos transistor whose gate is connected to a word line.
|Static random-access memory cell array with deep well regions|
An integrated circuit including a complementary metal-oxide-semiconductor (cmos) static random access memory (sram) with periodic deep well structures within the memory cell array. The deep well structures are contacted by surface well regions of the same conductivity type (e.g., n-type) in the memory cell array, forming two-dimensional grids of both n-type and p-type semiconductor material in the memory cell array area.
|Method for reading out multiple sram blocks with different column sizing in stitched cmos image sensor|
A controlling console for moving elements such as trusses and winches. A console body has a display screen, and a processor which is programmed to produce an output screen on the display screen which accepts controls for controlling at least one movable device.
|In-place resynthesis and remapping techniques for soft error mitigation in fpga|
In-place resynthesis for static memory (sram) based field programmable gate arrays (fpgas) toward reducing sensitivity to single event upsets (seus). Resynthesis and remapping are described which have a low overheard and improve fpga designs without the need of rerouting luts of the fpga.
|Threshold voltage measurement device|
A threshold voltage measurement device is disclosed. The device is coupled to a 6t sram.
To provide a semiconductor device with high reliability in operation, in which data in a volatile memory can be saved to a non-volatile memory. For example, the semiconductor device includes an sram provided with first and second data storage portions and a non-volatile memory provided with third and fourth data storage portions.
|Semiconductor device and driving method of semiconductor device|
To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an sram provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions.
|Static random access memory (sram) cell and method for forming same|
An embodiment is a method for forming a static random access memory (sram) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell connection and a second linear intra-cell connection.
|Butted contact shape to improve sram leakage current|
The present disclosure relates to an sram memory cell. The sram memory cell has a semiconductor substrate with an active area and a gate region positioned above the active area.
|Low-voltage fast-write nvsram cell|
This invention discloses several embodiments of a low-voltage fast-write nvsram cells, made of either of a 2-poly floating-gate type flash cell or a 1-poly charge-trapping sonos or monos flash cell with improvement by adding a bridge circuit. This bridge circuit is preferably inserted between each lv 6t sram cell and each hv flash cell that comprises one paired complementary flash strings.
|Reducing power in sram using supply voltage control|
An embodiment of the invention provides a method for decreasing power in a static random access memory (sram). A first voltage is applied between latch sourcing and latch sinking supply lines for columns of memory cells that are column addressed during a read cycle.
|Structure for finfets|
An sram array is formed by a plurality of finfets formed by fin lines. Each fin line is formed in a substrate, wherein a bottom portion of the fin line is enclosed by an isolation region and an upper portion of the fin line protrudes above a top surface of the isolation region.
|Semiconductor memory device and fabrication process thereof|
A sram includes a first cmos inverter of first and second mos transistors connected in series, a second cmos inverter of third and fourth mos transistors connected in series and forming a flip-flop circuit together with the first cmos inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third mos transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element.. .
|Implementing supply and source write assist for sram arrays|
A method and circuit for implementing write assist for static random access memory (sram) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a write driver including a common bit line supply node, and a common bit line source node.
|Low noise memory array|
A method of operating a memory circuit compatible with dynamic random access memories (dram) and static random access memories (sram) is disclosed. The method includes selecting a word line (708) connected to a row of memory cells in response to a plurality of row address signals and selecting a plurality of columns (706,710) of memory cells in response to a plurality of column address signals.