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Sram patents

      

This page is updated frequently with new Sram-related patent applications.




 Structure and  sram finfet device patent thumbnailStructure and sram finfet device
The present disclosure provides an embodiment of a fin-like field-effect transistor (finfet) device. The device includes a first fin structure disposed over an n-type finfet (nfet) region of a substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


 Boosted read write word line patent thumbnailBoosted read write word line
One or more techniques or systems for boosting a read word line (rwl) or a write word line (wwl) of a two port synchronous random access memory (sram) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a rwl, a wwl, or a read write word line (rwwl).
Taiwan Semiconductor Manufacturing Company Limited


 Dual write wordline memory cell patent thumbnailDual write wordline memory cell
A static random-access memory (sram) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline.
Industry-academic Cooperation Foundation, Yonsei University


 Low power sense amplifier for static random access memory patent thumbnailLow power sense amplifier for static random access memory
A low power sense amplifier for an sram is described. A first pass gate transistor is driven by bit line true and a second pass gate transistor is driven by bit line complement.
International Business Machines Corporation


 Memory chip and layout design for manufacturing same patent thumbnailMemory chip and layout design for manufacturing same
A static random access memory (sram) chip including a plurality of sram cells and a plurality of cell current tracking cells. Each of the sram cells include a source voltage reference conductor, a first ground reference conductor, two cross-coupled inverters, and two pass-gate devices.
Taiwan Semiconductor Manufacturing Company, Ltd.


 Static random access memory and  controlling the same patent thumbnailStatic random access memory and controlling the same
A static random access memory (sram) including at least a memory cell array, a first data line connected to the memory cell array, and a read assist unit connected to the first data line. The read assist unit is configured to suppress a voltage level of the first data line during a read operation of the memory cell array..
Taiwan Semiconductor Manufacturing Company, Ltd.


 Semiconductor integrated circuit device patent thumbnailSemiconductor integrated circuit device
The invention provides a semiconductor integrated circuit device provided with an sram that satisfies the requirements for both the snm and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines..
Renesas Electronics Corporation


 Sram with two-level voltage regulator patent thumbnailSram with two-level voltage regulator
A programmable logic device (pld) is provided with a two-level voltage regulator for powering sram cells within the device. In one example, a pld includes a plurality of static random access memory (sram) cells configured to store a configuration for the programmable logic device.
Lattice Semiconductor Corporation


 Sram cells patent thumbnailSram cells
There is provided a memory unit that comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to a first local bit line and a second local bit line by respective first and second access transistors, and each memory cell being associated with a word line configured to control the first and second access transistors of the memory cell. The first and second local bit lines of each memory cell group being operatively connected to respective first and second column bit lines by respective first and second group access switches, the first group access switch being configured to be controlled by the second column bit line, and the second group access switch being configured to be controlled by the first column bit line..
Surecore Limited


 Static random access memory and  using the same patent thumbnailStatic random access memory and using the same
A static random access memory (sram) including a bit cell, wherein the bit cell includes at least two p-type pass gates. The sram further includes a bit line connected to the bit cell, and a bit line bar connected to the bit cell.
Taiwan Semiconductor Manufacturing Company, Ltd.


Memory chip and layout design for manufacturing same

An embedded synchronous random access memory (sram) chip, includes a first single-port (sp) sram macro and a second sp macro. The first macro includes a first periphery circuit, and a plurality of first sram cells.
Taiwan Semiconductor Manufacturing Company, Ltd.

Method and bit-line sensing gates on an sram cell

A circuit for providing additional current in a memory cell without a higher supply voltage is provided. Embodiments include a circuit having a six transistor static random access memory (sram) cell including a first inverter and second cross-coupled to a second inverter; a first transistor having a first source coupled to a first bit-line, a first drain coupled to the first inverter, and a first gate coupled to a word-line; a second transistor having a second source coupled to the second inverter, a second drain coupled to a second bit-line, and a second gate coupled to the word-line; and a plurality of bit-line sensing transistors coupled to the first transistor and to the second transistor..
Globalfoundries Inc.

Sidecar sram for high granularity in floor plan aspect ratio

A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory.
Advanced Micro Devices, Inc.

Method and fabricating a memory device with a dielectric etch stop layer

The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as dram or sram, various layers are deposited to form structures, such as pmos gates, nmos gates, memory cells, p+ active areas, and n+ active areas.
Micron Technology, Inc.

Methods and designing and constructing dual write memory circuits with voltage assist

Static random access memory (sram) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6t) sram bit cell is proposed.
Cisco Technology, Inc.

Systems and methods involving multi-bank, dual-pipe memory circuitry

Multi-bank, dual-pipe sram systems, methods, processes of operating such srams, and/or methods of fabricating multi-bank, dual-pipe sram are disclosed. For example, one illustrative multi-bank, dual-pipe sram may comprise features for capturing read and write addresses, splitting and/or combining them via one or more splitting/combining processes, and/or bussing them to the sram memory banks, where they may be read and written to a particular bank.
Gsi Technology, Inc.

Systems and methods involving multi-bank memory circuitry

Multi-bank sram devices, systems, methods of operating multi-bank srams, and/or methods of fabricating multi-bank sram systems are disclosed. For example, illustrative multi-bank srams and methods may include or involve features for capturing read and write addresses at a particular frequency, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each sram bank, where they may be split and/or combined via one or more splitting/combining processes to read and write to a particular bank.
Gsi Technology, Inc.

High-density latch arrays

A system and device are provided for implementing memory arrays using high-density latch cells. The device includes an array of cells arranged into columns and rows.
Nvidia Corporation

Array power supply-based screening of static random access memory cells for bias temperature instability

A method of screening complementary metal-oxide-semiconductor cmos integrated circuits, such as integrated circuits including cmos static random access memory (sram) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of sram cells formed of cross-coupled cmos inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both).
Texas Instruments Incorporated

Static random access memory and controlling the same

A static random access memory (sram) that includes a memory cell comprising at least two p-type pass gates. The sram also includes a first data line connected to the memory cell, a second data line connected to the memory cell and a voltage control unit connected to the first data line, wherein the voltage control unit is configured to control the memory cell..
Taiwan Semiconductor Manufacturing Company, Ltd.

Apparatus and preventing error in physically unclonable function

An apparatus and method that prevent a bit error in a static random access memory (sram)-based physically unclonable function (puf). The method for preventing an error in a puf includes selecting any value, from a physically unclonable function based on a volatile memory device, as an input value, and checking a response corresponding to the selected input value, classifying cells having a plurality of bits corresponding to the response depending on frequency of error occurrence, calculating a number of white cells, in which an error does not occur, from classified results, and determining whether the number of white cells is greater than a preset threshold number of white cells, and selecting an input value of the physically unclonable function based on results of determination..
Electronics And Telecommunications Research Institute

Structure and effective device width adjustment in finfet devices using gate workfunction shift

Embodiments of the present invention provide methods and structures by which the inherent discretization of effective width can be relaxed through introduction of a fractional effective device width, thereby allowing greater flexibility for design applications, such as sram design optimization. A portion of some fins are clad with a capping layer or workfunction material to change the threshold voltage (vt) for a part of the fin, rendering that part of the fin electrically inactive, which changes the effective device width (weff).
International Business Machines Corporation

Non-volatile sram with multiple storage states

Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. In some examples, the multi-storage state non-volatile random access memory device has two or more memory cells.
Empire Technology Development Llc

Array power supply-based screening of static random access memory cells for bias temperature instability

A method of screening complementary metal-oxide-semiconductor cmos integrated circuits, such as integrated circuits including cmos static random access memory (sram) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of sram cells formed of cross-coupled cmos inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both).
Texas Instruments Incorporated

Dual-port sram connection structure

The present disclosure provides a static random access memory (sram) cell. The sram cell includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least two pull-down devices; at least four pass gate devices configured with the two cross-coupled inverters; at least two ports coupled with the at least four pass-gate devices for reading and writing; a first contact feature contacting first two pull-down devices (pd-11 and pd-12) of the first inverter; and a second contact feature contacting second two pull-down devices (pd-21 and pd-22) of the second inerter..
Taiwan Semiconductor Manufacturing Company, Ltd.

Array power supply-based screening of static random access memory cells for bias temperature instability

A method of screening complementary metal-oxide-semiconductor cmos integrated circuits, such as integrated circuits including cmos static random access memory (sram) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of sram cells formed of cross-coupled cmos inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both).
Texas Instruments Incorporated

High density static random access memory array having advanced metal patterning

Methods and apparatus directed toward a high density static random access memory (sram) array having advanced metal patterning are provided. In an example, provided is a method for fabricating an sram.
Qualcomm Incorporated

Semiconductor device

A semiconductor device, which can improve reading and writing stability of a static random access memory (sram) is provided. The semiconductor device includes a substrate having a first region and a second region defined therein, a first fin type active pattern formed on the substrate, extending in a first direction and including a first part and a second part, in the first region, the second part being disposed in the first direction at both sides of the first part, a second fin type active pattern formed on the substrate, extending in a second direction and having a third part and a fourth part, in the second region, the fourth part being disposed in the second direction at both sides of the third part and recessed relative to the third part, a first gate electrode extending in a third direction different from the first direction and formed on the first part, a second gate electrode extending in a fourth direction different from the second direction and formed on the third part, a first source/drain formed in the second part and doped with a first type impurity, and a second source/drain including a first epitaxial layer doped with the first type impurity and formed on the fourth part..
Samsung Electronics Co., Ltd.

Configurable delay circuit and clock buffering

An sram clock circuit and an sram. In one embodiment, the sram clock circuit includes: (1) a plurality of transistor stacks optionally serially electrically couplable to form a configurable delay path through which a clock signal is buffered, and (2) a delay path select circuit respectively electrically coupled between pairs of the plurality of transistor stacks and operable to selectively electrically couple the plurality of transistor stacks to a base delay path, thereby activating the configurable delay path based on a desired delay..
Nvidia Corporation

Finfets suitable for use in a high density sram cell

Single gate and dual gate finfet devices suitable for use in an sram memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that sti is unnecessary. Pairs of finfets can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates.
Stmicroelectronics, Inc.

High density sram array design with skipped, inter-layer conductive contacts

A static random access memory (sram) cell includes a first conductive layer including a wordline landing pad extending into a neighboring memory cell in an adjacent row of a memory array. The wordline landing pad in the first conductive layer is electrically isolated from all gate contacts of the neighboring memory cell.
Qualcomm Incorporated

Assist circuits for sram testing

Assist circuits for sram memory tests allow voltage scaling in low-power srams. Word line level reduction (wlr) and negative bit line (nbl) boost assist techniques improve read stability and write margin of sram core-cells, respectively, when the memory operates at a lowered supply voltage.

8t based sram cell and related method

Various embodiments include memory devices and related methods. An embodiment includes circuitry including: a first inverter having a first inverter storage node, the first inverter cross-coupled to a second inverter having a second inverter storage node, wherein each of the first inverter and the second inverter has a reverse bit line controlled feedback transistor coupled between an pull-down transistor and a pull-up transistor, and wherein each pull-down transistor is further coupled to a ground; a first signal line coupled with the reverse bit line controlled feedback transistor of the second inverter; a second signal line coupled with the reverse bit line controlled feedback transistor of the first inverter; a first access transistor coupled with the first inverter storage node, the first signal line, and a third signal line; and a second access transistor coupled with the second inverter storage node, the second signal line, and the third signal line..
International Business Machines Corporation

Memory array test logic

A test circuit for a static random access memory (sram) array includes a plurality of stages coupled in a ring. Each stage includes a plurality of bit cells to store information, a bit line and a complementary bit line coupled to the plurality of bit cells, and a plurality of word lines coupled to the plurality of bit cells.
Advanced Micro Devices Inc.

Structure and sram finfet device

The present disclosure provides an embodiment of a fin-like field-effect transistor (finfet) device. The device includes a substrate having an n-type finfet (nfet) region and a p-type finfet (pfet) region.
Taiwan Semiconductor Manufacturing Company, Ltd.

Connection structure for vertical gate all around (vgaa) devices on semiconductor on insulator (soi) substrate

A vertical gate all around (vgaa) nanowire device circuit routing structure is disclosed. The circuit routing structure comprises a plurality of vgaa nanowire devices including a nmos and a pmos device.
Taiwan Semiconductor Manufacturing Company Limited

Word line decoders for dual rail static random access memories

Word line decoders for dual rail sram devices are disclosed for high performance sub-micron sram designs. One embodiment is an sram device that includes a memory cell array and a word line traversing the memory cell array for selecting memory cells of the memory cell array.
Lsi Corporation

Sram cell and cell layout method

Embodiments of the present disclosure include an array of sram cells, an sram cell, and methods of forming the same. An embodiment is an array of static random access memory (sram) cells including a plurality of overlapping rectangular regions.
Stmicroelectronics International N.v.

Semiconductor device, electronic component, and electronic device

A semiconductor device having a novel structure. A multiport sram and a data memory portion including an os transistor are stacked.

Low-power sram cells

The present invention provides a memory unit (4) comprising: a storage element (6) comprising a pair of back to back inverters (12a, 12b and 14a, 14b) having respective first and second storage access nodes (24, 26); first and second voltage lines (vss, vdd 16a, 6b) across which said pair of back to back inverters (12a, 12b and 14a, 14b) are connected; a first access transistor (18a), connected to said first storage node (24); a second access transistor (18b), connected to said second storage node (26); a write word line (22) connected to a gate (18g1) on said first access transistor (18a) and a gate (18g2) on said second access transistor (18b); a first bit line (28) operably connected for controlling 10 said node (24); a second bit line (30) operably connected for controlling said node (26); in which there is provided a data dependent conductive path (46) between the first and second bit lines (28, 30).. .

Static random access memory devices

The present application relates to an improved static random access memory (sram) device having a plurality of storage cells and a separate read/write circuit. Each of the plurality of storage cells is connected to a read/write data node of the read/write circuit by a dedicated connection, and an access switch which permits read/write access to the storage cell.

Data-aware sram ming same

Exemplary embodiments for sram cells, new control units for sram systems, and embodiments of sram systems are described herein. An sram cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal.
Taiwan Semiconductor Manufacturing Company, Ltd.

Finfet drive strength modification

One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a sram cell formed from finfet transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved sram cell performance..

Integrated circuit and forming the integrated circuit with improved logic transistor performance and sram transistor yield

In an integrated circuit that includes an nmos logic transistor, an nmos sram transistor, and a resistor, the gate of the sram transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps.. .
Texas Instruments Incorporated

Semiconductor device, electronic component, and electronic device

Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an sram and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region.
Semiconductor Energy Laboratory Co., Ltd.

Performance and power improvement on dma writes to level two combined cache/sram that is cached in level one data cache and line is valid and dirty

This invention optimizes dma writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data.
Texas Instruments Incorporated

Design-for-test apparatuses and techniques

Embodiments of design-for-test (dft) apparatuses and related techniques are disclosed herein. In some embodiments, a dft apparatus may include a static random access memory (sram) cell, read/write/decoder (r/w/decoder) circuitry to provide a nominal word line (wl) voltage and a nominal bit line (bl) voltage for application to the sram cell during accesses.

Negative bitline boost scheme for sram write-assist

A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element.
Taiwan Semiconductor Manufacturing Co., Ltd.

Methods and circuits for generating physically unclonable function

Various embodiments include solutions for generating a physically unclonable function. In some cases, a method includes an electronic circuit including: a static random access memory (sram) device having at least one memory cell with at least one transistor device therein, sram bias temperature instability aging circuitry coupled with the sram device and configured to apply aging conditions to the at least one memory cell to degrade the at least one transistor device within the at least one memory cell, and at least one computing device coupled with the sram device and configured to: skew a storage cell value in the at least one transistor device, measure a skewed value of the storage cell after the skewing, and create a physically unclonable function from the skewed value of the storage cell..
International Business Machines Corporation

Semiconductor device

To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an lcd driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an lcd driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but srams (internal circuits) are arranged..
Renesas Electronics Corporation

Bit line write assist for static random access memory architectures

sram devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an sram device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells.
Lsi Corporation

Compact system with memory and pmu integration

One or more integrated circuits including at least one integrated circuit that is fabricated in a dram fabrication process. Capacitors in the dram-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip pmus.
Apple Inc.

Semiconductor storage device

A semiconductor storage device includes an sram memory cell composed of a drive transistor, a transfer transistor and a load transistor, an i/o circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the i/o circuit between a resume standby mode and a normal operation mode, wherein the i/o circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.. .
Renesas Electronics Corporation

Boost system for dual-port sram

A boost system for dual-port sram includes a comparator and a boost circuit. The comparator is configured to compare a first row address of a first port and a second row address of a second port, and output a first enable signal.
Taiwan Semiconductor Manufacturing Company Ltd.

Methods and sram cell structure

An sram cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second cvdd node, a first and a second cvss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second cvdd nodes, the first and second cvss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon.
Taiwan Semiconductor Manufacturing Company, Ltd.

Structure and finfet sram

Provided is an embedded finfet sram structure and methods of making the same. The embedded finfet sram structure includes an array of sram cells.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device

A well voltage supply cell includes third gate electrode group (including a third gate electrode corresponding to a first gate electrode) located symmetrically to first gate electrode group (including the first gate electrode constituting an access transistor) of a first sram cell, fourth gate electrode group (including a fourth gate electrode corresponding to a second gate electrode) located symmetrically to second gate electrode group (including the second gate electrode constituting an access transistor) of a second sram cell. A p-type impurity diffusion region located on a p well between the third gate electrode and the fourth gate electrode located opposite to each other, a first n-type impurity diffusion region located on the side of the third gate electrode closer to the first sram cell, and a second n-type impurity diffusion region located on the side of the fourth gate electrode closer to the second sram cell..
Renesas Electronics Corporation

Write assist scheme for low power sram

A write-assist memory includes a memory supply voltage and a column of sram cells that is controlled by a pair of bit lines, during a write operation. Additionally, the write-assist memory includes a write-assist unit that is coupled to the memory supply voltage and the column of sram cells and has a separable conductive line located between the pair of bit lines that provides a collapsible sram supply voltage to the column of sram cells based on a capacitive coupling of a control signal in the pair of bit lines, during the write operation.
Nvidia Corporation

Semicondutor integrated circuit device and system

A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural sram modules.
Renesas Electronics Corporation

Soi sram having well regions with opposite conductivity

Below an active region in which a driver transistor including a sram is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor.

Sram cell connection structure

A static random access memory (sram) cell includes a first pull-up transistor and a second pull-up transistor, and a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor. A conductive feature includes a first leg having a first longitudinal direction, wherein the first leg interconnects a drain of the first pull-up transistor and a drain of the first pull-down transistor.
Taiwan Semiconductor Manufacturing Company, Ltd.

1t sram/dram

One-transistor volatile memory devices and manufacturing methods thereof are provided. The device includes a substrate having top and bottom surfaces and an isolation well disposed below the top substrate surface.
Globalfoundries Singapore Pte. Ltd.

1t sram/dram

One-transistor (1t) volatile memory devices and manufacturing methods thereof are provided. The device includes a substrate having top and bottom surfaces and an isolation buffer layer disposed below the top substrate surface.
Globalfoundries Singapore Pte. Ltd.

Method for cache sram data retention in switched off power supply mode generating extremely small power dissipation

If the power of sram is completely switched off including substrate and wells or more precisely if power supply rails are put on ground potential, leakage is non existing but the data is lost. It is however possible that data is retained in power off mode under optical illumination of substrate where parasitic photodiodes connected to charge nodes are operating in photovoltaic mode.

Testing signal development on a bit line in an sram

An embodiment of the invention discloses a method for testing a memory cell in an sram. The number of dummy memory cells on a single dummy word line used to drive the dummy bit lines is selected.
Texas Instruments Incorporated

Integrated read/write tracking in sram

Systems and methods presented herein provide for integrated read/write tracking in an sram device. In one embodiment, an sram device includes a clock, a memory cell array, a column of dummy bit cells operable to mirror bit line loading of the memory cell array, and a row of dummy bit cells operable to mirror word line loading of the memory cell array.
Lsi Corporation

Cell layout for sram finfet transistors

An sram array and method of making is disclosed. Each sram cell comprises two pull-up (pu), two pass-gate (pg), and two pull-down (pd) finfets.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device

A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an sram memory cell. In the sram memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor.
Renesas Electronics Corporation

Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail sram memories

In one embodiment, a self-timed, dual-rail sram includes a self-timing circuit having a logic gate that is powered by voltage vdd and configured to receive a fire-sense-amplifier timing signal and to produce a vdd-domain sense-amplifier-enable signal soelv. The self-timing circuit includes an inverting level-shifter having complementary n-type and p-type transistors connected in series between voltage vdda and ground.
Lsi Corporation

Hybrid approach to write assist for memory array

A hybrid write-assist memory system includes an array voltage supply and a static random access memory (sram) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the sram cell and provides a voltage reduction of the separable cell supply voltage during a write operation.
Nvidia Corporation

Negative bit line write assist for memory array

A negative bit line write assist system includes an array voltage supply and a static random access memory (sram) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the sram cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation.
Nvidia Corporation



Sram topics:
  • Random Access
  • Static Random Access Memory
  • Memory Cell
  • Semiconductor
  • Memory Cells
  • Transistors
  • Semiconductor Memory
  • Memory Device
  • Integrated Circuit
  • Robustness
  • Field Effect Transistor
  • Clamping Circuit
  • Internal Node
  • Implantation
  • Data Storage


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