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 Sram memory cell and sram memory patent thumbnailSram memory cell and sram memory
Various embodiments provide semiconductor structures and their fabrication methods. An sram memory cell can include at least one semiconductor structure, and an sram memory can include at least one sram memory cell.
Semiconductor Manufacturing International Corp.


 Improved sram storage unit based on dice structure patent thumbnailImproved sram storage unit based on dice structure
The present invention provides an improved sram memory cell based on a dice structure, which comprises following structures: four inverter structures formed through arranging pmos transistors and nmos transistors in series, wherein the part between the drains of a pmos transistor and an nmos transistor serves as a storage node; each storage node controls the gate voltage of an nmos transistor of the other inverter structure and of a pmos transistor of another inverter structure; a transmission structure consisting of four nmos transistors, whose source, gate and drain are respectively connected with a bit line/bit bar line, a word line and a storage node. The use of an improved sram memory cell based on a dice structure not only avoids such defects as small static noise margin and being prone to transmission error facing the traditional cell structures consisting of 6 transistors, but also resolves the problem that the current sram storage cells based on a dice structure can easily be affected by the electrical level of storage nodes.
Institute Of Microelectronics, Chinese Academy Of Sciences


 Semiconductor memory device patent thumbnailSemiconductor memory device
According to one embodiment, a semiconductor memory device includes: a memory cell array including an sram cell; and a first voltage generator including first and second circuits. The first and second circuits include a diode-connected first transistor and a diode-connected second transistor, respectively.
Kabushiki Kaisha Toshiba


 Semiconductor memory device patent thumbnailSemiconductor memory device
According to one embodiment, a semiconductor memory device includes an sram. The sram comprises a memory cell including a first inverter, a second inverter, a first transfer transistor, and a second transfer transistor and a peripheral circuit configured to supply various voltages to a word line, a first bit line, and a second bit line.
Kabushiki Kaisha Toshiba


 Display control device patent thumbnailDisplay control device
The display controller (1) includes: a dram (31); a sram (32) which consumes electric power less than the dram (31); an update judging section (61); a secondary compression section (70); and a decompression section (40). In a case where the update judging section (61) has judged that image data is not updated, (i) the secondary compression section (70) compresses image data and then stores compressed image data in the sram (32), (ii) the dram (31) stops a memory retaining operation, and (iii) the decompression section (40) decompresses the compressed image data and then supplies decompressed data to an lcd (3)..
Sharp Kabushiki Kaisha


 Semiconductor device, test program, and test method patent thumbnailSemiconductor device, test program, and test method
An sram including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (vdd) potential and drive the other bit line at an intermediate potential (vss+several tens mv to one handled and several tens mv) a little higher than a low level (vss) potential for normal writing when writing data into the memory cell.. .

 Static random access memory cell having improved write margin for use in ultra-low power application patent thumbnailStatic random access memory cell having improved write margin for use in ultra-low power application
A static random access memory (sram) cell is provided with improved write margin. The sram cell includes: a pair of inverters cross coupled to each other and forming two storage nodes; read access switches electrically coupled between a read bit line and the two storage nodes; write access switches electrically coupled between write bit lines and two storage nodes; and supply switches electrically coupled between a supply voltage and the pair of inverters and operable, in response to a signal on at least one of the write bit lines, to selectively connect the supply voltage to at least one of the inverters in the pair of inverters.
The Regents Of The University Of Michigan


 Static random-access memory (sram) sensor patent thumbnailStatic random-access memory (sram) sensor
An apparatus includes a static random-access memory and circuitry configured to initiate a corrective action associated with the static random-access memory. The corrective action may be initiated based on a number of static random-access memory cells that have a particular state responsive to a power-up of the static random-access memory..
Qualcomm Incorporated


 Methods and  sram cell structure patent thumbnailMethods and sram cell structure
An sram cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second cvdd node, a first and a second cvss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second cvdd nodes, the first and second cvss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon.
Taiwan Semiconductor Manufacturing Company, Ltd.


 Tunable negative bitline write assist and boost attenuation circuit patent thumbnailTunable negative bitline write assist and boost attenuation circuit
An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (sram) arrays. The apparatus includes a memory array comprising a plurality of sram cells.
International Business Machines Corporation


Sram module and writing control method thereof


A sram module and a writing control method of the sram module are disclosed. The writing control method of the sram module is applied to a sram module that includes a plurality of memory cells and a bit line.
M31 Technology Corporation


Integrated circuit devices and methods


An integrated circuit can include multiple sram cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the sram cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple sram cells.. .
Mie Fujitsu Semiconductor Limited


Flash memory device for storing sensitive information and other data


A flash memory process and device for encrypting and storing data in a non-volatile flash memory associated with a host system. The device includes a flash memory, an encryption engine, a key store, a sram to interface with the host system, and associated control circuitry.
Bae Systems Information And Electric Systems Integration Inc.


Adjustment signal level in semiconductor device and semiconductor device


Characteristics of each transistor in a semiconductor device including a transistor of a memory cell are measured by an asv monitoring circuit, a power supply voltage supplied to the semiconductor device is determined based on the measured characteristics of the transistor, a data read-out speed of the memory cell under the determined power supply voltage supplied is measured while changing a signal level of a word line by an sram word line monitoring circuit, the signal level of the word line is determined by comparing the measured data read-out speed of the memory cell and a specification range of the memory cell, and the signal level of the word line is appropriately set at the power supply voltage applied by the asv.. .
Socionext Inc.


Multiple-port sram device


A multiple-port memory cell includes first conductive lines in a first metal layer, second conductive lines in a second metal layer, third conductive lines a third metal layer, and fourth conductive lines in a fourth metal layer. The first conductive lines include a write bit line electrically coupled with a write bit line node; a first read bit line electrically coupled with a first read bit line node; and a second read bit line electrically coupled with a second read bit line node.
Taiwan Semiconductor Manufacturing Company Ltd.


Semiconductor device, electronic component, and electronic device


To provide a semiconductor device having a novel structure. To provide a semiconductor device excellent in reducing power consumption.
Semiconductor Energy Laboratory Co., Ltd.


Dual-port sram timing control circuit


A dual-port sram timing control circuit, with three nmos transistors connected in series respectively between ground and nodes of the two bit lines to which the cell structure corresponds. The gates of the nmos transistors are connected to a corresponding wordline, a pulse signal and a timing control signal, respectively.
Shanghai Huahong Grace Semiconductor Manufacturing Corporation


Tunable negative bitline write assist and boost attenuation circuit


An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (sram) arrays. The apparatus includes a memory array comprising a plurality of sram cells.
International Business Machines Corporation


Semiconductor device and manufacturing method thereof


When vc inspection for a teg is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an sram is formed on an soi substrate in a chip region.
Renesas Electronics Corporation


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Dual-port sram devices and methods of manufacturing the same


A dual-port sram device includes a substrate having a field region and first to fourth active fins extending in a first direction, and a unit cell having first to eighth gate structures. The first and second gate structures are on the first, second and fourth active fins, and extend in a second direction crossing the first direction.

Power gate for latch-up prevention


In an embodiment of the invention, power is provided to an sram array without causing latch-up by charging the positive voltage node in the sram array and the nwell regions in the sram at approximately the same rate.. .

Systems and methods involving multi-bank, dual- or multi-pipe srams


Systems and methods are disclosed for increasing the performance of static random access memory (sram). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank srams, such as quad-b2 srams.

Non-volatile static random access memory (nvsram)


A nonvolatile memory device includes a shared port block, a plurality of decoded address signals, a read signal, and a read word line. The shared port block includes a shared port communicatively coupled to a block, the block comprising a plurality of memory cells, wherein the shared port is operable to sense a voltage level at each of the plurality of memory cells.

Low-drive current finfet structure for improving circuit density of ratioed logic in sram devices


A method of fabricating an sram semiconductor device includes forming first and second finfets on an upper surface of a bulk substrate. The first finfet includes a first source/drain region containing first dopants, and the second finfet includes a second source/drain region containing second dopants.

Semiconductor integrated circuit device


In an image information chip or the like, a multi-port sram is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port.

Low-drive current finfet structure for improving circuit density of ratioed logic in sram devices


A method of fabricating an sram semiconductor device includes forming first and second finfets on an upper surface of a bulk substrate. The first finfet includes a first source/drain region containing first dopants, and the second finfet includes a second source/drain region containing second dopants.

Volatile/non-volatile sram device


A method of operation of a static random access memory (sram) storage element includes programming a value to the sram storage element prior to a power-down event. The method further includes, in response to a power-on event at the sram storage element after the power-down event, increasing a supply voltage of the sram storage element and sensing a state of the sram storage element to determine the value programmed to the sram storage element prior to the power-down event.

Semiconductor integrated circuit device and wearable device


A semiconductor device includes a cpu, a system controller which designates an operation speed of the cpu, p-type sotb transistors, and n-type sotb transistors. The semiconductor device is provided with an sram which is connected to the cpu, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the p-type sotb transistors and the n-type sotb transistors.

Low power dma snoop and skip


Methods for preprocessing pixel data using a direct memory access (dma) engine during a data transfer of the pixel data from a first memory (e.g., a dram) to a second memory (e.g., an sram) are described. The pixel data may derive from a color camera or a depth camera in which individual pixel values are not a multiple of eight bits.

Pseudo sram using resistive elements for non-volatile storage


A memory device includes a first select transistor having a first current electrode coupled to a first bit line, a control electrode and a second current electrode. A second select transistor has a first current electrode coupled to a second bit line, a control electrode and a second current electrode.
Freescale Semiconductor, Inc.


Non-volatile sram with multiple storage states


Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. In some examples, the multi-storage state non-volatile random access memory device has two or more memory cells.
Empire Technology Development Llc


Semiconductor integrated circuit device and system


A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural sram modules.
Renesas Electronics Corporation


Lighting device having phosphor wheel and excitation radiation source


Various embodiments may relate to a lighting device, including an excitation radiation source and a two-sided luminescent-material wheel. At least one luminescent material is provided on each of the two sides of the two-sided luminescent-material wheel, thus both on the front side and on the opposite back side.
Osram Gmbh


Radiation-emitting apparatus


A radiation emitting apparatus including a substrate, at least one layer sequence arranged on the substrate and producing electromagnetic radiation in a wavelength range, having at least one first electrode surface, at least one second electrode surface, and at least one functional layer between the first electrode surface and the second electrode surface, wherein the functional layer produces electromagnetic radiation in the wavelength range in a switched-on operating state, and a scatter layer having a first region and a second region, wherein radiation produced by the functional layer is directly incident on the scatter layer only in the first region of the scatter layer, and the scatter layer at least partially scatters radiation incident upon the first region of the scatter layer so that said radiation enters the second region of the scatter layer.. .
Osram Oled Gmbh


Optoelectronic semiconductor chip, semiconductor component and producing optoelectronic semiconductor chips


An optoelectronic semiconductor chip includes a carrier, a semiconductor body having an active region that generates and/or receives radiation, and an insulation layer wherein the semiconductor body is fastened on the carrier with a connecting layer; the carrier extends in a vertical direction between a first main surface facing toward the semiconductor body, and a second main surface facing away from the semiconductor body, and a lateral surface connects the first main surface and the second main surface to one another; a first region of the lateral surface of the carrier has an indentation; a second region of the lateral surface runs in the vertical direction between the indentation and the second main surface; the insulation layer at least partially covers each of the semiconductor body and the first region; and the second region is free of the insulation layer.. .
Osram Opto Semiconductors Gmbh


Method of producing an optoelectronic component


A method of producing an optoelectronic component includes providing an optoelectronic semiconductor chip having a mask layer arranged on an upper side of the optoelectronic semiconductor chip; providing a carrier having walls arranged on a surface of the carrier, the walls laterally limiting a receiving region; arranging an optoelectronic semiconductor chip in the receiving region, wherein a bottom side of the optoelectronic semiconductor chip faces the surface of the carrier; filling a region of the receiving region surrounding the optoelectronic semiconductor chip with an optically reflective material up to a height that lies between the upper side of the optoelectronic semiconductor chip and an upper side of the mask layer; removing the mask layer to create a free space in the optically reflective material; and introducing a wavelength-converting material into the free space.. .
Osram Opto Semiconductors Gmbh


Embedded sram and methods of forming the same


A chip includes a semiconductor substrate, and a first n-type metal oxide semiconductor field effect transistor (nmosfet) at a surface of the semiconductor substrate. The first nmosfet includes a gate stack over the semiconductor substrate, a source/drain region adjacent to the gate stack, and a dislocation plane having a portion in the source/drain region.
Taiwan Semiconductor Manufacturing Company, Ltd.


Static random access memory (sram) bit cells with wordline landing pads split across boundary edges of the sram bit cells


Static random access memory (sram) bit cells with wordline landing pads split across boundary edges of the sram bit cells are disclosed. In one aspect, an sram bit cell is disclosed employing write wordline in second metal layer, first read wordline in third metal layer, and second read wordline in fourth metal layer.
Qualcomm Incorporated


Static random access memory (sram) bit cells with wordlines on separate metal layers for increased performance, and related methods


Static random access memory (sram) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an sram bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer.
Qualcomm Incorporated


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Semiconductor device


A nonvolatile memory is provided. A semiconductor device (a nonvolatile memory) has a circuit configuration similar to that of a general sram.
Semiconductor Energy Laboratory Co., Ltd.


Merged source/drain and gate contacts in sram bitcell


A method of forming a semiconductor device with uniform regular shaped gate contacts and the resulting device are disclosed. Embodiments include forming first and second gate electrodes adjacent one another on a substrate; forming at least one trench silicide (ts) on the substrate between the first and second gate electrodes; forming a gate contact on the first gate electrode, the gate contact having a regular shape; forming a source/drain contact on a trench silicide between the first and second gate electrodes, wherein an upper portion of the source/drain contact overlaps an upper portion of the gate contact..
Globalfoundries Inc.


Circuits and methods for performance optimization of sram memory


In aspects of the present application, circuitry for storing data is provided including a static random access memory (sram) circuit operable to store data in an array of sram cell circuits arranged in rows and columns, each sram cell coupled to a pair of complementary bit lines disposed along the columns of sram cells circuits, and one or more precharge circuits in the sram memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the sram circuit is operable to cause coupling transistors within the sram circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the sram circuit, indicating a bitline precharge is to be performed..
Texas Instruments Incorporated


Light module for a projection or illumination arrangement


A light module includes an excitation radiation source designed to emit an excitation radiation having a polarization, at least one first phosphor, an output, at which an output signal is providable, at least one first polarization beam splitter, a first polarization modulator arranged serially between the radiation source and the first splitter. The first modulator is designed to modify the polarization of the radiation source depending on a control signal.
Osram Gmbh


Retrofit-style lamp and fixture, each including a one-dimensional linear batwing lens


A retrofit-style lamp is disclosed. The retrofit-style lamp includes a plurality of light sources, and a one-dimensional linear batwing lens.
Osram Sylvania Inc.


Sram cell with dynamic split ground and split wordline


An sram cell with dynamic split ground (gnd) and split wordline (wl) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline.
International Business Machines Corporation


Novel finfet 6t sram cell structure


A static memory circuit includes a pull-up transistor, a pull-down transistor, a pass-gate transistor associated with the pull-up and pull-down transistors, and first and second word lines electrically insulated from each other. The pass-gate transistor includes a number of fins and a gate electrode having a number of first and second gates, each one of the gates is disposed on one of the fins, the first gates are connected to the first word line, and the second gates are connected to the second word line.
Semiconductor Manufacturing International (shanghai) Corporation


Cross-coupled thyristor sram semiconductor structures and methods of fabrication


A memory cell based upon thyristors for an sram integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


Method of using a static random access memory


A method of using a static random access memory (sram) includes pre-discharging a data line to a reference voltage, activating a bit cell connected to the data line, wherein the bit cell comprises a p-type pass gate, and exchanging bit information between the data line and the activated bit cell.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


Scalable floating body memory cell for memory compilers and using floating body memories with memory compilers


A floating body sram cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body sram cell by a memory compiler for use in array design is provided..
Zeno Semiconductor, Inc.


Static random access memory free from write disturb and testing method thereof


A static random access memory (sram) includes a memory cell array, a row decoder, a plurality of word-line drivers and an arbiter. The memory cell array includes a plurality of memory cell rows, wherein the memory cell rows are enabled by a plurality of word-lines, respectively.
Mediatek Inc.


Hybrid wildcard match table


Embodiments of the present invention are directed to a wildcard matching solution that uses a combination of static random access memories (srams) and ternary content addressable memories (tcams) in a hybrid solution. In particular, the wildcard matching solution uses a plurality of sram pools for lookup and a spillover tcam pool for unresolved hash conflicts..
Cavium, Inc.


Hybrid wildcard match table


Embodiments of the present invention are directed to a wildcard matching solution that uses a combination of static random access memories (srams) and ternary content addressable memories (tcams) in a hybrid solution. In particular, the wildcard matching solution uses a plurality of sram pools for lookup and a spillover tcam pool for unresolved hash conflicts..
Xpliant, Inc


Fin field-effect transistor static random access memory devices with p-channel metal-oxide-semiconductor pass gate transistors


A complementary metal oxide semiconductor (cmos) static random access memory (sram) cell. A cmos sram cell in accordance with an aspect of the present disclosure includes a bit line and a word line.
Qualcomm Incorporated


Sram cells with vertical gate-all-round mosfets


A static random access memory (sram) cell includes a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate as a second source/drain region.
Taiwan Semiconductor Manufacturing Co., Ltd.


Systems and methods involving control-i/o buffer enable circuits and/or features of saving power in standby mode


Systems and methods are disclosed involving control i/o buffer enable circuitry and/or features of saving power in standby mode. In illustrative implementations, aspects of the present innovations may be directed to providing low standby power consumption, such as providing low standby power consumption in high-speed synchronous sram and rldram devices..
Gsi Technology, Inc.


Method of reducing gate leakage in a mos device by implanting gate leakage reducing species into the edge of the gate


In a mos device, gate leakage is reduced by implanting gate oxide leakage reduction species such as nitrogen into the gate oxide along the edges of the gate to reduce gate leakage and hence reduce data retention fails in sram devices and allow low vdd sram operation without increasing gate oxide thickness. By implanting nitrogen along the edges of the gate it simultaneously replaces lost gate oxide nitrogen to further reduce gate leakage..
Texas Instruments Incorporated


Method of controlling auxiliary branches for sram cell


A method includes: during a read operation of a first storage node and a second storage node formed by cross-coupled inverters, based on data stored in the first storage node and the second storage node, causing a first auxiliary branch or a second auxiliary branch to assist a corresponding one of the cross-coupled inverters in holding data; and during a write operation of the first storage node and the second storage node, based on data to be written to the first storage node and the second storage node, causing the first auxiliary branch or the second auxiliary branch to assist a corresponding one of the cross-coupled inverters in flipping data.. .
Taiwan Semiconductor Manufacturing Company Ltd.


Semiconductor device


In a semiconductor device having an sram memory cell, its reliability is improved. In the semiconductor device having the sram memory cell, electrically-independent four semiconductor regions functioning as hack gates are provided below two load transistors and two driver transistors, so that threshold voltages for the load transistors and driver transistors are controlled.
Renesas Electronics Corporation


Structure and finfet sram


Provided is an embedded finfet sram structure and methods of making the same. The embedded finfet sram structure includes an array of sram cells.
Taiwan Semiconductor Manufacturing Company, Ltd.


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10t non-volatile static random-access memory


A memory including an array of nvsram cells and method of operating the same are provided. Each nvsram cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including exactly one non-volatile memory (nvm) element, a first transistor coupled to the nvm element through which data true is coupled to the volatile charge storage circuit, a second transistor coupled to the nvm element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the nvm element is coupled to a positive voltage supply line (vcct).

6t sram cell


A 6t sram cell includes a write inverter which includes a write pull-up transistor and a write pull-down transistor, a read inverter which includes a read pull-up transistor and a read pull-down transistor, a write access transistor, and a read access transistor. To-be-written data is written into the 6t sram cell via the write access transistor in a one-sided write operation, and to-be-read data is read via the read access transistor in a one-sided read operation.

Static random access memory and controlling the same


A static random access memory (sram) including at least a first memory cell array, a second memory cell array, a first data line connected to the first memory cell array and the second memory cell array, a primary driver circuit connected to the first data line and a supplementary driver circuit connected to the first data line, wherein the supplementary driver circuit is configured to pull a voltage level of the first data line to a first voltage level during a write operation of the sram.. .

Static random access memory and method thereof


A static random access memory (sram) includes a voltage generator coupled to receive a positive power supply voltage, and to controllably generate a first power supply voltage, which is with a reduced level and is higher than a retention voltage during a specific period. A first inverter and a second inverter each is connected between the first power supply voltage and a second power supply voltage.

Efficient memory architecture for low density parity check decoding


A low density parity check (ldpc) decoder integrated on a single semiconductor substrate may comprise one or more arrays of first-type memory cells and one or more arrays of second-type memory cells. The ldpc decoder may be configured to store intrinsic messages in the array of first-type cells and to store extrinsic messages in the array of second-type cells.
Maxlinear, Inc.


Two-transistor sram semiconductor structure and methods of fabrication


A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


Cross-coupled thyristor sram semiconductor structures and methods of fabrication


A memory cell based upon thyristors for an sram integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


Six-transistor sram semiconductor structures and methods of fabrication


A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


Write assist sram circuits and methods of operation


A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


Six-transistor sram circuits and methods of operation


A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


Cross-coupled thyristor sram circuits and methods of operation


A memory cell based upon thyristors for an sram integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


Seven-transistor static random-access memory bitcell with reduced read disturbance


Systems and methods relate to a seven transistor static random-access memory (7t sram) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor.
Qualcomm Incorporated


Selective current boosting in a static random-access memory


Systems and methods include a static random-access memory (sram) bit cell circuit having an access transistor configured to pass a read current to a storage node, the access transistor including an access transistor back gate. The access transistor back gate is biased to enable selective current boosting of the read current during a read operation..
Qualcomm Incorporated


Multi-port memory circuits


A multi-port hybrid full-swing/low-swing memory circuit in a static random access memory (sram) device comprises a first wordline driver that comprises a read wordline driver, a second wordline driver that comprises either a read wordline driver or a read/write wordline driver, a memory cell coupled to the first and second wordline drivers, a sense amplifier coupled to the memory cell, and a latch coupled to the memory cell. The memory circuit is capable of achieving high-speed low-swing or low-speed full-swing operations while avoiding the need for a large circuit area on an integrated circuit..
Qualcomm Incorporated


Two-transistor sram circuit and methods of fabrication


A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


Overvoltage protection for a fine grained negative wordline scheme


A fine grained negative wordline scheme for sram memories is disclosed. The scheme includes a circuit having a static random access memory (sram) cell including at least a wordline coupled to a plurality of nfets of a transistor array.
International Business Machines Corporation


Overvoltage protection for a fine grained negative wordline scheme


A fine grained negative wordline scheme for sram memories is disclosed. The scheme includes a circuit having a static random access memory (sram) cell including at least a wordline coupled to a plurality of nfets of a transistor array.
International Business Machines Corporation


Overvoltage protection for a fine grained negative wordline scheme


A fine grained negative wordline scheme for sram memories is disclosed. The scheme includes a circuit having a static random access memory (sram) cell including at least a wordline coupled to a plurality of nfets of a transistor array.
International Business Machines Corporation


Sram array comprising multiple cell cores


An sram array having multiple cell cores to store and retrieve data. A cell core includes a plurality of sram cells, and at least two corresponding cell cores build a cell core row.
International Business Machines Corporation


Overvoltage protection for a fine grained negative wordline scheme


A fine grained negative wordline scheme for sram memories is disclosed. The scheme includes a circuit having a static random access memory (sram) cell including at least a wordline coupled to a plurality of nfets of a transistor array.
International Business Machines Corporation


Semiconductor device having memory cell with electrostatic capacitance circuit


A capacitance coupled to a memory node and a word line of an sram cell provides an electrostatic capacitance between the memory node and the word line. The capacitance has a first electrostatic capacitance when the word line is in a nonselective state (usually a low level) and the memory node retains a high level; the capacitance has a second electrostatic capacitance which is smaller than the first electrostatic capacitance when the word line is in the nonselective state (usually the low level) and the memory node retains the low level..
Renesas Electronics Corporation


Structure and sram finfet device


The present disclosure provides an embodiment of a fin-like field-effect transistor (finfet) device. The device includes a first fin structure disposed over an n-type finfet (nfet) region of a substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


Efficient coding for memory redundancy


A system may be provided that provides redundancy for a plurality of embedded memories such as srams. The system may include one or more decoders, each capable of decoding a selection address to identify a defective one of the embedded memories..
Qualcomm Incorporated


Method and providing multi-page read and write using sram and nonvolatile memory devices


A memory device includes a static random-access memory (“sram”) circuit and a first nonvolatile memory (“nvm”) string, a second nvm string, a first and a second drain select gates (“dsgs”). The sram circuit is able to temporarily store information in response to bit line (“bl”) information which is coupled to at the input terminal of the sram circuit.
Neo Semiconductor, Inc.


Design-for-test apparatuses and techniques


Embodiments of design-for-test (dft) apparatuses and related techniques are disclosed herein. In some embodiments, a dft apparatus may include an sram cell, read/write (r/w) circuitry to provide a nominal word line (wl) voltage and a nominal bl voltage for application to the sram cell during accesses.
Intel Ip Corporation


Dual-port static random access memory (sram)


In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters.
Intel Corporation


Memory device with memory cells sram (static random access memories) and controlling the polarization of boxes of transistors of the memory cells


A memory device includes a matrix of several columns of sram memory cells each including transistors forming a memory point, a read port and a write port, and such that the transistors of the read port and/or the p-type transistors include a second well with a conductivity type opposite that of a first well of the other transistors. The memory device also includes a polarization unit for the second wells, able to select and apply polarization potentials on the second wells, including a memory circuit of the polarization states of the second wells for each column or group of columns and a selection circuit applying a polarization potential on the second wells according to one of the values received as input, as a function of the stored polarization state associated with the column or group of columns..
Commissariat A L'energie Atomique Et Aux Energies Alternatives


Sram cells with vertical gate-all-round mosfets


A static random access memory (sram) cell includes a first boundary and a second boundary opposite to, and parallel to, the first boundary, a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate over the channel as a second source/drain region.
Taiwan Semiconductor Manufacturing Company, Ltd.


Initiating operation of a timing device using a read only memory (rom) or a one time programmable non volatile memory (otp nvm)


The present invention provides a method and a programmable timing device that includes a timing device circuit for generating at least one timing signal, a static random access memory (sram) coupled to the timing device circuit, a read only memory (rom) having a first timing device configuration stored therein, a one time programmable non volatile memory (otp nvm) for storing a second timing device configuration and selection logic. The selection logic includes an output coupled to the sram, a first input coupled to the rom and a second input coupled to the otp nvm.
Integrated Device Technology, Inc.


Semiconductor device


A static random access memory (sram) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.. .
Unisantis Electronics Singapore Pte. Ltd.


Semiconductor storage device


A semiconductor storage device includes an sram memory cell composed of a drive transistor, a transfer transistor and a load transistor, an i/o circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the i/o circuit between a resume standby mode and a normal operation mode, wherein the i/o circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.. .
Renesas Electronics Corporation


Static random access memory with reduced write power


A static random access memory (sram) features reduced write cycle power consumption. The sram includes an array of static storage cells and a write controller.
Texas Instruments Incorporated


Method and circuits for low latency initialization of static random access memory


A method and various circuit embodiments for low latency initialization of an sram are disclosed. In one embodiment, an ic includes an sram coupled to at least one functional circuit block.
Apple Inc.


Semiconductor device


A logic circuit in a system lsi is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an sram circuit of the system lsi controls a substrate bias to reduce leakage current..
Renesas Electronics Corporation


Physical unclonable function using augmented memory for challenge-response hashing


A technique is presented for performing a physical unclonable function (puf) using an array of sram cells. The technique can be viewed as an attempt to read multiple cells in a column at the same time, creating contention that is resolved according to process variation.
The Regents Of The University Of Michigan


Low power sram


A static random access memory (sram) that includes an array of storage cells arranged as rows and columns and a read controller to manage reading from the storage cells. The array of storage cells includes word lines that correspond to the rows and bit lines that correspond to the columns.
Texas Instruments Incorporated


Low voltage sram


In some embodiments, an sram includes an array of storage cells arranged as rows and columns, each storage cell of the array of storage cells includes a first type of transistor and a second type of transistor. The sram also includes a memory controller configured to detect a temperature of the sram and apply a body bias to the first type of transistor in each of the storage cells and refrain from an application of a body bias to the second type of transistor in each of the storage cells..
Texas Instruments Incorporated


Silicon germanium read port for a static random access memory register file


A static random access memory (sram) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (pmos) transistor having a silicon germanium (sige) channel.
Qualcomm Incorporated


Three-port bit cell having increased width


An apparatus includes a first read port, a second read port, a write port, and at least one storage latch. A width of a bit cell that includes the first read port, the second read port, and the write port is greater than twice a contacted poly pitch (cpp) associated with the bit cell.
Qualcomm Incorporated




Sram topics:
  • Random Access
  • Static Random Access Memory
  • Memory Cell
  • Semiconductor
  • Memory Cells
  • Transistors
  • Semiconductor Memory
  • Memory Device
  • Integrated Circuit
  • Robustness
  • Field Effect Transistor
  • Clamping Circuit
  • Internal Node
  • Implantation
  • Data Storage


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