|| List of recent Sram-related patents
|Method for reading out multiple sram blocks with different column sizing in stitched cmos image sensor|
A controlling console for moving elements such as trusses and winches. A console body has a display screen, and a processor which is programmed to produce an output screen on the display screen which accepts controls for controlling at least one movable device.
|In-place resynthesis and remapping techniques for soft error mitigation in fpga|
In-place resynthesis for static memory (sram) based field programmable gate arrays (fpgas) toward reducing sensitivity to single event upsets (seus). Resynthesis and remapping are described which have a low overheard and improve fpga designs without the need of rerouting luts of the fpga.
|Threshold voltage measurement device|
A threshold voltage measurement device is disclosed. The device is coupled to a 6t sram.
To provide a semiconductor device with high reliability in operation, in which data in a volatile memory can be saved to a non-volatile memory. For example, the semiconductor device includes an sram provided with first and second data storage portions and a non-volatile memory provided with third and fourth data storage portions.
|Semiconductor device and driving method of semiconductor device|
To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an sram provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions.
|Static random access memory (sram) cell and method for forming same|
An embodiment is a method for forming a static random access memory (sram) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell connection and a second linear intra-cell connection.
|Butted contact shape to improve sram leakage current|
The present disclosure relates to an sram memory cell. The sram memory cell has a semiconductor substrate with an active area and a gate region positioned above the active area.
|Low-voltage fast-write nvsram cell|
This invention discloses several embodiments of a low-voltage fast-write nvsram cells, made of either of a 2-poly floating-gate type flash cell or a 1-poly charge-trapping sonos or monos flash cell with improvement by adding a bridge circuit. This bridge circuit is preferably inserted between each lv 6t sram cell and each hv flash cell that comprises one paired complementary flash strings.
|Reducing power in sram using supply voltage control|
An embodiment of the invention provides a method for decreasing power in a static random access memory (sram). A first voltage is applied between latch sourcing and latch sinking supply lines for columns of memory cells that are column addressed during a read cycle.
|Structure for finfets|
An sram array is formed by a plurality of finfets formed by fin lines. Each fin line is formed in a substrate, wherein a bottom portion of the fin line is enclosed by an isolation region and an upper portion of the fin line protrudes above a top surface of the isolation region.
|Semiconductor memory device and fabrication process thereof|
A sram includes a first cmos inverter of first and second mos transistors connected in series, a second cmos inverter of third and fourth mos transistors connected in series and forming a flip-flop circuit together with the first cmos inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third mos transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element.. .
|Implementing supply and source write assist for sram arrays|
A method and circuit for implementing write assist for static random access memory (sram) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a write driver including a common bit line supply node, and a common bit line source node.
|Low noise memory array|
A method of operating a memory circuit compatible with dynamic random access memories (dram) and static random access memories (sram) is disclosed. The method includes selecting a word line (708) connected to a row of memory cells in response to a plurality of row address signals and selecting a plurality of columns (706,710) of memory cells in response to a plurality of column address signals.
|Low noise memory array|
A circuit compatible with dynamic random access memories (dram) and static random access memories (sram) is disclosed. The circuit includes a substrate having a first conductivity type.
|Semiconductor integrated circuit device|
The invention provides a semiconductor integrated circuit device provided with an sram that satisfies the requirements for both the snm and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines..
|Global bit select circuit with write around capability|
A global to local bit line interface circuit for domino static random access memory (sram) devices includes a pair of complementary global write bit lines in selective communication with an array of sram cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected sram cell with write data presented on a pair of complementary write data input lines; a pair of complementary global read bit lines in selective communication with the array of sram cells through corresponding local read bit lines, the complementary global read bit lines configured to read data stored in a selected sram cell and present the read data on a pair of complementary read data output lines; and write-around logic configured to directly couple the write data presented on the complementary global write bit lines to read data output circuitry associated with the complementary global read bit lines.. .
|Apparatus for sram cells|
A memory cell comprises a first word line in a first interconnect layer, a first vss line, a first bit line, a power source line, a second bit line and a second vss line formed a second interconnect layer, a second word line in a third interconnect layer. The memory cell further comprises a word line strap structure formed between the power source line and the second bit line, wherein the word line strap structure couples the first word line and the second word line..
|Eight transistor soft error robust storage cell|
A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes.
|Pre-colored methodology of multiple patterning|
Some embodiments relate to a method of pre-coloring word lines and control lines within an sram integrated chip design to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The method is performed by generating a graphical ic layout file having an sram circuit with a plurality of word lines and y-control lines.
|Method for improving write margins of sram cells|
The present invention provides a method for improving the write margins of the sram cells. The method comprises: before etching a polysilicon layer to form the polysilicon gates, performing a pre-implantation process to the polysilicon layer; wherein the polysilicon layer defines sram nmosfets regions and sram pmosfets regions; wherein the pre-implantation process comprises pre-implanting the fifth-group elements to the sram nmosfets regions and the nmosfets regions except to the sram nmosfets regions in the polysilicon layer, and pre-implanting the third-group elements to the pmosfets regions excluding the sram pmosfets regions in the polysilicon layer; wherein the process of pre-implanting the third-group elements comprises forming a pre-implantation photo mask capable of covering the sram pmosfets regions and using the pre-implantation photo mask to pre-implanting the third-group elements..
|Low extension dose implants in sram fabrication|
A static random access memory fabrication method includes forming a gate stack on a substrate, forming isolating spacers adjacent the gate stack, the isolating spacers and gate stack having a gate length, forming a source and drain region adjacent the gate stack, which generates an effective gate length, wherein the source and drain regions are formed from a low extension dose implant that varies a difference between the gate length and the effective gate length.. .
|Dual-port sram with bit line clamping|
In one embodiment, a memory includes a plurality of bit lines and a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation. The write driver is coupled to an internal node.
|Methods and apparatus for sram cell structure|
An sram cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second cvdd node, a first and a second cvss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second cvdd nodes, the first and second cvss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon.
|Single cycle data copy for two-port sram|
A static random access memory (sram) includes a column of sram memory cells. The sram may include a circuit to copy a value stored in any sram memory cell in a column of sram memory cells to any sram memory cell in the column of sram memory cells in a single cycle of the sram..
|Low extension dose implants in sram fabrication|
A static random access memory fabrication array includes at least one p-type field effect transistor, including a gate stack and isolating spacers forming a gate having a gate length lgate and an effective gate length, leff and a source and drain region adjacent the gate stack, wherein the source and drain regions are formed from a low extension dose implant that decreases a difference between lgate and leff.. .
|Stable sram cell|
Sram cells and sram cell arrays are described. In one embodiment, an sram cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value.
|System and method for implementing a low-cost cpu cache using a single sram|
One embodiment of the present invention relates to a cpu cache system that stores tag information and cached data in the same sram. The system includes an sram memory device, a lookup buffer, and a cache controller.
|Methods and apparatus for designing and constructing multi-port memory circuits with voltage assist|
To handle multiple concurrent memory requests, a dual-port six transistor (6t) sram bit cell is proposed. The dual-port 6t sram cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently.
Memory cells are described with cross-coupled inverters including unidirectional gate conductors. Gate conductors for access transistors may also be aligned with a long axis of the inverter gate conductor.
|Implementing rc and coupling delay correction for sram|
A method and circuit for implementing delay correction in static random access memory (sram), and a design structure on which the subject circuit resides are provided. The sram circuit includes a precharge enable signal coupled between precharge near and precharge far signals and wordline near and wordline far signals of the sram.
|Structure and method for a sram circuit|
The present disclosure provides an integrated circuit formed in a semiconductor substrate. The integrated circuit includes a first static random access memory (sram) cell having a first cell size; and a second sram cell having a second cell size greater than the first cell size.
|Semiconductor memory device|
In a static random access memory (sram) device having a hierarchical bit line architecture, a local sense amplifier (sa) circuit includes p-channel transistors which precharge local bit lines connected to memory cells, p-channel transistors each having a gate connected to a corresponding one of the local bit lines and a drain connected to a corresponding one of global bit lines, and n-channel transistors each having a gate connected to a corresponding one of the global bit lines and a drain connected to a corresponding one of the local bit lines. As a result, restore operation to a non-selected memory cell during write operation can be achieved without the need of a fine timing control, the speed of read operation by a feedback function can be increased, and the area can be reduced..
|8t sram cell with one word line|
An integrated circuit with sram cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and one passgate transistor may be variously configured to a separate read data line and write data line, or a combined data line, in different embodiments.
An sgt-based static memory cell which is a six-transistor sram cell includes an sgt driver transistor including a first gate electrode surrounding a first gate insulating film and composed of at least a metal; an sgt selection transistor including a second gate electrode surrounding a second gate insulating film and composed of at least a metal; an sgt load transistor including a third gate electrode surrounding a third gate insulating film and composed of at least a metal; and a gate wire connected to the second gate electrode. An island-shaped semiconductor layer of the driver transistor has a peripheral length that is less than twice that of an island-shaped semiconductor layer of the selection transistor.
|Vdiff max limiter in srams for improved yield and power|
An integrated circuit structure comprises a static random access memory (sram) structure and a logic circuit. A power supply is operatively connected to the sram structure, and provides a first voltage to the sram structure.
|Sram based on 6 transistor structure including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor|
The present invention provides a 6t sram including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor. The first inverter zs a first pull-up transistor and a first pull-down transistor.
|Oscillator based on a 6t sram for measuring the bias temperature instability|
The present invention provides an oscillator which is based on a 6t sram for measuring the bias temperature instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter.
|High performance two-port sram architecture using 8t high performance single-port bit cell|
An 8t memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state.
|Image processing apparatus having storage unit that stores setting values, and control method and storage medium therefor|
An image processing apparatus having improved user-friendliness in setting the setting values that represent contents of operation to be performed by the image processing apparatus. In a case that a login user has changed at least one setting value during the login, a cpu of the image processing apparatus causes a sram to store a setting value before change corresponding to the changed setting value.