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Multiport memory with matching address control

Date/App# patent app List of recent Sram-related patents
07/17/14
20140201593
 Efficient memory architecture for low density parity check decoding patent thumbnailnew patent Efficient memory architecture for low density parity check decoding
A low density parity check (ldpc) decoder integrated on a single semiconductor substrate may comprise one or more arrays of first-type memory cells and one or more arrays of second-type memory cells. The ldpc decoder may be configured to store intrinsic messages in the array of first-type cells and to store extrinsic messages in the array of second-type cells.
07/17/14
20140198590
 Multiport memory with matching address control patent thumbnailnew patent Multiport memory with matching address control
In a multiple port sram, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A second bit cell is coupled to the first and second word lines and a third and fourth bit line pair.
07/17/14
20140198562
 Ten-transistor dual-port sram with shared bit-line architecture patent thumbnailnew patent Ten-transistor dual-port sram with shared bit-line architecture
A 10-transistor dual-port sram with shared bit-line architecture includes a first memory cell and a second memory cell. The first memory cell has a first storage unit, a first switch set, and a second switch set.
07/17/14
20140198561
 Multiport memory with matching address and data line control patent thumbnailnew patent Multiport memory with matching address and data line control
In a multiple port sram, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic.
07/10/14
20140191338
 Semiconductor device and method for manufacturing same patent thumbnailSemiconductor device and method for manufacturing same
In a region just below an access gate electrode in an sram memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region.
07/10/14
20140191330
 Finfet and method of fabrication patent thumbnailFinfet and method of fabrication
An improved finfet and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon.
07/03/14
20140185369
 Sense amplifier scheme for low voltage sram and register files patent thumbnailSense amplifier scheme for low voltage sram and register files
In at least one embodiment, a sense amplifier circuit includes a bit line, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the bit line and includes an nmos transistor coupled between a power node and the bit line.
07/03/14
20140185367
 Sram bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter patent thumbnailSram bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter
Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch.
07/03/14
20140185366
 Pre-charge tracking of global read lines in high speed sram patent thumbnailPre-charge tracking of global read lines in high speed sram
In embodiments of the invention, a memory circuit includes a static random access memory (sram), rows of m sense amplifiers, a global read precharge tracking control circuit controlling a precharge of global read lines, a sense amplifier output tracking circuit generating a reset sense amplifier signal for the sense amplifier control circuits, and a read delay circuit generating a trigger signal for the global read precharge tracking control circuit and the sense amplifier output tracking circuit and performing a fixed delay tracking of a read operation in a read cycle. A dummy global read line is coupled to the global read precharge tracking control circuit and returns from a half way to the top of the sram forming a tracking dummy global read line that determines a completion of the precharge of the global read lines before the sense amplifiers start discharging the global read lines in the read cycle..
07/03/14
20140185365
 Dual-port sram connection structure patent thumbnailDual-port sram connection structure
The present disclosure provides a static random access memory (sram) cell. The sram cell includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least two pull-down devices; at least four pass gate devices configured with the two cross-coupled inverters; at least two ports coupled with the at least four pass-gate devices for reading and writing; a first contact feature contacting first two pull-down devices (pd-11 and pd-12) of the first inverter; and a second contact feature contacting second two pull-down devices (pd-21 and pd-22) of the second inerter..
07/03/14
20140185364
Methods and apparatus for designing and constructing multi-port memory circuits
Static random access memory (sram) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6t) sram memory cell is proposed.
06/26/14
20140177349
Shared integrated sleep mode regulator for sram memory
Embodiments are described for a method for regulating sleep mode of a plurality of sub-banks in an sram array by isolating all of the sub-banks from a regulator upon access to at least one sub-bank that causes the accessed sub-bank to go to an operating voltage, and isolating the accessed sub-bank from non accessed sub-banks, while maintaining a sleep voltage on a load memory array and each of the sub-banks through the regulator; comparing a voltage on the non accessed sub-banks to a voltage output of the regulator; and providing a sleep voltage level to all of the sub-banks through the regulator when the voltage on the non accessed sub-banks is less than the sleep voltage.. .
06/26/14
20140177323
Bit-flipping in memories
Data stored in sram cells are periodically flipped e.g., before long idle periods. Operating the memories in both a ‘flipped’ mode and a ‘non-flipped’ mode helps cause the bias temperature instability (bti) degradation to be symmetric, thereby not degrading the static noise margin (snm) degradation of the cells.
06/19/14
20140169077
Operation aware auto-feedback sram
A static random-access memory is described. The sram includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation.
06/19/14
20140169076
Power management sram write bit line drive circuit
A static random access memory (sram) having two or more sram memory cells connected with a write bit line (wbl) and a write bit line complement (wblc) is disclosed. The sram may include a write driver logic coupled to the wbl and the wblc.
06/12/14
20140164856
Pbist engine with reduced sram testing bus width
A programmable built in self test (pbist) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pbist module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pbist..
06/12/14
20140160871
System and method for performing sram write assist
A method and a system are provided for performing write assist. Write assist circuitry is initialized and voltage collapse is initiated to reduce a column supply voltage provided to a storage cell.
06/05/14
20140154845
Complementary soi lateral bipolar for sram in a cmos platform
An example embodiment is a memory array. The memory array includes a soi substrate and lateral bipolar junction transistors (bjts) fabricated on the soi substrate.
06/05/14
20140153349
Simultaneous two/dual port access on 6t sram
A method includes generating a first and a second internal clock signal from a clock signal, wherein a first internal clock signal edge of the first internal clock signal and a second internal clock signal edge of the second internal clock signal are generated from a same edge of the clock signal. A first one of the first and the second internal clock edges is used to trigger a first operation on a six-transistor (6t) static random access memory (sram) cell of a sram array.
06/05/14
20140153328
Complementary soi lateral bipolar for sram in a cmos platform
An example embodiment is a memory array. The memory array includes a soi substrate and lateral bipolar junction transistors (bjts) fabricated on the soi substrate.
06/05/14
20140153323
Methods for operating sram cells
A circuit includes a static random access memory (sram) array. An sram cell is in the sram array and includes a p-well region, a first and a second n-well region on opposite sides of the p-well region, and a first and a second pass-gate finfet.
06/05/14
20140153322
Sram cell comprising finfets
A static random access memory (sram) cell includes a first long boundary and a second long boundary parallel to a first direction, and a first short boundary and a second short boundary parallel to a second direction perpendicular to the first direction. The first and the second long boundaries are longer than, and form a rectangle with, the first and the second short boundaries.
06/05/14
20140153321
Methods and apparatus for finfet sram arrays in integrated circuits
Methods and apparatus for providing single finfet and multiple finfet sram arrays on a single integrated circuit are provided. A first single port sram array of a plurality of first bit cells is described, each first bit cell having a y pitch y1 and an x pitch x1, the ratio of x1 to y1 being greater than or equal to 2, each bit cell further having single fin finfet transistors to form a 6t sram cell and a first voltage control circuit; and a second single port sram array of a plurality of second bit cells, each second bit cell having a y pitch y2 and an x pitch x2, the ratio of x2 to y2 being greater than or equal to 3, each of the plurality of second bit cells comprising a 6t sram cell wherein the ratio of x2 to x1 is greater than about 1.1..
06/05/14
20140151812
Contact plugs in sram cells and the method of forming the same
A method includes forming a dielectric layer over a portion of an sram cell. The sram cell includes a first pull-up transistor and a second pull-up transistor, a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor, and a first pass-gate transistor and a second pass-gate transistor connected to drains of the first pull-up transistor and the first pull-down transistor and drains of the second pull-up transistor and the second pull-down transistor, respectively.
06/05/14
20140151811
Sram cell comprising finfets
A static random access memory (sram) cell includes a first pull-up fin field-effect transistor (finfet) and a second pull-up finfet, and a first pull-down finfet and a second pull-down finfet forming cross-latched inverters with the first pull-up finfet and the second pull-up finfet. A first pass-gate finfet is connected to drains of the first pull-up finfet and the first pull-down finfet.
05/29/14
20140146631
Vccmin for a dual port synchronous random access memory (dpsram) cell utilized as a single port synchronous random access memory (spsram) cell
One or more techniques for improving vccmin for a dual port synchronous random access memory (dpsram) cell utilized as a single port synchronous random access memory (spsram) cell are provided herein. In some embodiments, a second word line signal is sent to a second word line of the dpsram cell.
05/29/14
20140146628
Technique for improving static random-access memory sense amplifier voltage differential
A static random-access memory (sram) module includes a column select (rsel) driver coupled to an input/output (i/o) circuit by an rsel line. The i/o circuit is configured to read bit line signals from a bit cell within the sram module.
05/29/14
20140146034
Display device
A display device is driven through no wire cable such as an fpc, and a display image is continuously held for a certain period of time by storing an image signal received from a wireless communication device so that the display image can be held even when the display device is out of communication range with the wireless communication device. A display device includes at least a pixel circuit having an sram (static random access memory) circuit, a circuit which controls the pixel circuit, an antenna circuit, a circuit which generates a demodulation signal, a circuit which rectifies a wireless signal, a circuit which generates first voltage, a charge circuit which stores second voltage, a charge control circuit, a voltage supply control circuit, and a circuit which controls the charge control circuit and the voltage supply control circuit..
05/22/14
20140143486
Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
The msmc (multicore shared memory controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or dma, and the emif (external memory interface) in a multicore soc. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters.
05/22/14
20140143485
Technique for optimizing static random-access memory passive power consumption
A static read-only memory (sram) includes one or more bit cell rows that each includes a collection of bit cells. Each bit cell row is coupled to two or more different wordlines, where each wordline associated with a given bit cell row provides memory access to a different subset of bit cells within that bit cell row..
05/22/14
20140140147
Static random access memory circuit with step regulator
Implementations of the present disclosure involve a circuit and/or method for providing a static random access memory (sram) component of a very large scale integration (vlsi) design, such as a microprocessor design. In particular, the present disclosure provides for an sram circuit that includes a step voltage regulator coupled to the sram circuit and designed to maintain a fixed-value voltage drop across the regulator rather than a fixed voltage across the load of the sram circuit.
05/22/14
20140138797
Dense finfet sram
A method for fabricating the device includes patterning a first structure and a second structure on a semiconductor device. A first angled ion implantation is applied to the second structure such that the first structure is protected and a second angled ion implantation is applied to the first structure such that the second structure is protected, wherein exposed portions of the first and second structures have an altered rate of oxidation.
05/22/14
20140138773
Dense finfet sram
A method for fabricating the device includes patterning a first structure and a second structure on a semiconductor device. A first angled ion implantation is applied to the second structure such that the first structure is protected and a second angled ion implantation is applied to the first structure such that the second structure is protected, wherein exposed portions of the first and second structures have an altered rate of oxidation.
05/15/14
20140136909
Testing of srams
Systems, methods, and other embodiments associated with at-speed testing of static random access memory (sram) are described. In one embodiment, a method includes loading, into a multi-stage pipeline of memory devices, a control pattern for testing a static random access memory (sram).
05/15/14
20140136778
System, method, and computer program product for implementing a storage array
A system, method, and computer program product are provided for implementing a storage array. In use, a storage array is implemented utilizing static random-access memory (sram).
05/15/14
20140133217
Concurrent use of sram cells with both nmos and pmos pass gates in a memory system
A memory system includes first memory cells and second memory cells. Each of the first memory cells includes first and second pass gates including nmos transistors.
05/15/14
20140132837
Wireless video/audio data transmission system having i-frame only gop structure
A wireless video/audio transmission system includes a transmitter configured to wirelessly transmit video/audio data streams the transmitter has an encoder module for generating the data streams including video data, audio data, and timing information. The video data includes only i-frames.
05/15/14
20140131813
Cell layout for sram finfet transistors
An sram array and method of making is disclosed. Each sram cell comprises two pull-up (pu), two pass-gate (pg), and two pull-down (pd) finfets.
05/15/14
20140131810
Semiconductor memory device
In a static memory cell constituted using four mos transistors, the mos transistors are sgts formed on a soi substrate in which the drains, gates, and sources are arranged in the vertical direction. The gates of access transistors are shared, as a word line, among a plurality of cells adjacent to one another in the horizontal direction.
05/08/14
20140126277
Sram with buffered-read bit cells and its testing
An sram with buffered-read bit cells is disclosed (figs. 1-6).
05/08/14
20140126276
Power management sram global bit line precharge circuit
A domino static random access memory (sram) having one or more sram memory cells connected with a local bit line is disclosed. The sram may include a precharge device connected between a voltage supply and the local bit line, and global bit line (gbl) discharge logic connected between a local bit line and a gbl.
05/08/14
20140126273
Power management sram global bit line precharge circuit
A domino static random access memory (sram) having one or more sram memory cells connected with a local bit line is disclosed. The sram may include a precharge device connected between a voltage supply and the local bit line, and global bit line (gbl) discharge logic connected between a local bit line and a gbl.
05/01/14
20140119120
Nvsram cells with voltage flash charger
The present invention discloses two preferred embodiments of a 12 t nvsram cell with a flash-based charger and a pseudo 10 t nvsram cell with one shared flash-based charger. The flash-based charger can be made of a 2-poly floating-gate type or a 1-poly charge-trapping sonos/monos flash type, regardless of pmos type or nmos type.
05/01/14
20140119119
Pseudo-8t nvsram cell with a charge-follower
The present invention discloses a 10t nvsram cell with a 6t sram cell with 4t flash cell with one dedicated flash-based charger. In addition, a pseudo-8t nvsram cell with a shared flash-based charger between two adjacent 8t nvsram cells at top and bottom in cell layout is also disclosed to further reduce cell size by 20%.
05/01/14
20140119118
8t nvsram cell and cell operations
One or more embodiments of 8t nvsram cell are provided for improving nvsram memory architecture with reduced cell size as opposed to the prior art of 12t nvsram cell. This novel 8t nvsram cell uses one step write operation under either a fn-channel write scheme to increase a paired flash transistor vt values in positive direction with a desired Δvt12≧1v or a fn-edge write scheme to decrease the vt values in negative direction with a similar desired Δvt12≧1v to write the Δvt12 into the paired flash transistors within 1-10 ms without requiring a pre-erase step.
05/01/14
20140119104
Data-aware sram systems and methods forming same
Exemplary embodiments for sram cells, new control units for sram systems, and embodiments of sram systems are described herein. An sram cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal.
05/01/14
20140119103
Sram cells suitable for fin field-effect transistor (finfet) process
A static random access memory (sram) cell includes first and second n-channel transistors, first and second p-channel transistors, first and second enable transistors, and first and second pass gates. The first n-channel transistor, the first p-channel transistor, and the first enable transistor are connected in series between first and second reference potentials.
05/01/14
20140119102
Dummy read to prevent crowbar current during read-write collisions in memory arrays with crosscoupled keepers
Systems and methods for detecting and suppressing crowbar currents in memory arrays. A dummy read is implemented to prevent crowbar currents in the case of simultaneous read-write collisions in a static random access memory (sram) array having cross-coupled bitline keepers.
05/01/14
20140119100
Sram with improved write operation
A memory including an array of memory cells, word lines, and voltage supply lines. Each voltage supply line of the plurality of voltage supply lines is coupled to a first voltage supply terminal of a subset of memory cells of subsets of memory cells of the array.
05/01/14
20140117507
Double trench well formation in sram cells
A method is provided for forming sram cells with low energy implants. Embodiments include forming deep trenches in a silicon substrate; forming a deep n-well or deep p-well around a bottom of each deep trench; filling the deep trenches with oxide; forming a first or second shallow trench between each pair of adjacent deep trenches; forming a first p-well or first n-well, respectively, above each deep n-well or p-well; forming a second n-well at a bottom of each first shallow trench; forming a p+ region above each second n-well on each side of each first shallow trench; filling the first shallow trenches with oxide; forming a second p-well at a bottom of each second shallow trench; filling the second shallow trenches with oxide; forming a p+ region above each second n-well on each side of each first shallow trench; and forming an n+ region above each second p-well..
04/24/14
20140115279
Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and edc
This invention is an integrated memory controller/interconnect that provides very high bandwidth access to both on-chip memory and externally connected off-chip memory. This invention includes an arbitration for all memory endpoints including priority, fairness, and starvation bounds; virtualization; and error detection and correction hardware to protect the on-chip sram banks including automated scrubbing..
04/24/14
20140112081
Data-dependent pullup transistor supply and body bias voltage application for a static random access memory (sram) cell
A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor.
04/24/14
20140112072
10t nvsram cell and cell operations
A 10t nvsram cell is provided with a bottom hv nmos select transistor in each 3t fstring removed from traditional 12t nvsram cell. A recall operation by reading a stored Δvt state of flash transistors into each sram cell uses a charge-sensing scheme rather than the current-sensing scheme, with all other key operations unchanged.
04/24/14
20140112064
Sram global precharge, discharge, and sense
An sram includes a global bit line, an sram cell, precharge logic, discharge logic, and sense logic. The sram cell stores a first logical value or a second logic value and is coupled to the global bit line.
04/24/14
20140112060
Sram global precharge, discharge, and sense
An sram includes a global bit line, an sram cell, precharge logic, discharge logic, and sense logic. The sram cell stores a first logical value or a second logic value and is coupled to the global bit line.
04/17/14
20140104960
Methods and apparatus for designing and constructing high-speed memory circuits
Static random access memory (sram) circuits are used in most digital integrated circuits to store digital data bits. Sram memory circuits are generally read by decoding an address, reading from an addressed memory cell using a set of bit lines, outputting data from the read memory cell, and precharging the bit lines for a subsequent memory cycle.
04/17/14
20140104946
On-chip hv and lv capacitors acting as the second back-up supplies for nvsram auto-store operation
Two on-chip capacitors including one hv capacitor vppcap and one lv vcc capacitor vcccap are built over a nvsram memory chip as a back-up second power supplies for each nvsram cell, regardless of 1-poly, 2-poly, pmos or nmos flash cell structures therein. The on-chip hv and lv capacitors are preferably made from one or more mim or mip layers for achieving required capacitance.
04/17/14
20140103960
Programmable logic device
To obtain a pld that achieves high-speed configuration capable of dynamic configuration, consumes less power, and has a short startup time and a pld that has a smaller number of transistors or a smaller circuit area than a pld using an sram as a configuration memory, a plurality of logic elements arranged in an array and a switch for selecting electrical connection between the logic elements are provided. The switch includes a first transistor including a multilayer film including an oxide layer and an oxide semiconductor layer, a node that becomes floating when the first transistor is turned off, and a second transistor in which electrical continuity between a source and a drain is determined based on configuration data held at the node..
04/17/14
20140103445
Semiconductor sram structures and fabrication methods
Various embodiments provide semiconductor structures and their fabrication methods. An sram memory cell can include at least one semiconductor structure, and an sram memory can include at least one sram memory cell.
04/10/14
20140099758
Sram devices utilizing strained-channel transistors and methods of manufacture
A novel sram memory cell structure and method of making the same are provided. The sram memory cell structure comprises strained pmos transistors formed in a semiconductor substrate.
04/10/14
20140098596
8-transistor dual-ported static random access memory
An 8-transistor sram (static random access memory) storage cell provides differential read bit lines that are precharged to a low voltage level for read operations. The 8-transistor storage cell provides separate ports for read and write operations, including differential read bit lines.
04/03/14
20140092696
Power management domino sram bit line discharge circuit
A domino static random access memory (sram) having one or more sram memory cells connected with a local bit line is disclosed. The sram may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line.
04/03/14
20140092675
Two-port sram write tracking scheme
A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit further includes a second transistor configured to pre-charge a read bit line connected to the at least two memory cells.
04/03/14
20140092674
Circuits and methods of a self-timed high speed sram
Circuits and methods for precisely self-timed sram memory are disclosed to track the wordline and/or bitline/bitline bar (bl/blb) propagation delays. At least one reference cell can be placed near the far end of a driver to drive a selected wordline or a reference wordline.
04/03/14
20140092673
Memory cell
This invention relates generally to a memory cell. The embodiments of the present invention provide a sram cell and a sram cell array comprising such sram cell.
04/03/14
20140092672
Power management domino sram bit line discharge circuit
A domino static random access memory (sram) having one or more sram memory cells connected with a local bit line is disclosed. The sram may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line.
04/03/14
20140091396
Pass gate, semiconductor memory, and semiconductor device
According to one embodiment, a pass gate provided between a data holding unit of an sram cell and a bit line, includes a first tunnel transistor and a first diode connected in series between the data holding unit and the bit line, and a second tunnel transistor and a second diode connected in series between the data holding unit and the bit line and connected in parallel to the first tunnel transistor and the first diode. Gate electrodes of the first tunnel transistor and the second tunnel transistor are connected to a word line.
03/27/14
20140085978
Method and architecture for improving defect detectability, coupling area, and flexibility of nvsram cells and arrays
Several preferred embodiments of 1s1f 16t nvsram, 1s1f 20t nvsram, 1s2f 22t nvsram, 1s2f 14t nvsram cells are proposed, regardless of 1-poly, 2-poly, pmos or nos flash cell structures. Two separate sourcelines for the paired flash strings are also proposed for easy adding ability for the nvsram circuit to detect the marginally erased vt0 and marginally programmed vt1 of the paired flash cell.
03/20/14
20140078819
Static random access memory cell with single-sided buffer and asymmetric construction
Balanced electrical performance in a static random access memory (sram) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors.
03/20/14
20140078817
Integrated circuits with sram cells having additional read stacks and methods for their fabrication
Integrated circuits that include sram cells having additional read stacks and methods for their fabrication are provided. In accordance with one embodiment a method for fabricating such an integrated circuit includes forming a plurality of sram cells in and on a semiconductor substrate, each of the plurality of sram cells including a read pull down transistor and a read pass gate transistor.
03/20/14
20140078806
Channel hot carrier tolerant tracking circuit for signal development on a memory sram
An embodiment of the invention discloses an electronic device for reducing degradation in nmos circuits in a tracking circuit. A first multiplexer selects, based on n bits from a row address in a memory array, which tracking circuit from a group of 2n tracking circuits will be used to provide a signal develop time for a memory cell in the memory array using a dummy word line signal.


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Sram topics: Random Access, Static Random Access Memory, Memory Cell, Semiconductor, Memory Cells, Transistors, Semiconductor Memory, Memory Device, Integrated Circuit, Robustness, Field Effect Transistor, Clamping Circuit, Internal Node, Implantation, Data Storage

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