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Sram patents



      
           
This page is updated frequently with new Sram-related patent applications. Subscribe to the Sram RSS feed to automatically get the update: related Sram RSS feeds. RSS updates for this page: Sram RSS RSS


Global bitline write assist for sram architectures

Lsi

Global bitline write assist for sram architectures

Interleaved write assist for hierarchical bitline sram architectures

Lsi

Interleaved write assist for hierarchical bitline sram architectures

Interleaved write assist for hierarchical bitline sram architectures

Structure and method for sram cell circuit

Date/App# patent app List of recent Sram-related patents
05/21/15
20150138897
 Stack position determination in memory devices configured for stacked arrangements patent thumbnailStack position determination in memory devices configured for stacked arrangements
Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
Iii Holdings 2, Llc
05/21/15
20150138876
 Global bitline write assist for sram architectures patent thumbnailGlobal bitline write assist for sram architectures
An sram device includes a segmented memory cell array with a plurality of memory cells. Each segment of memory cells includes a bitline coupled to the memory cells in the segment.
Lsi Corporation
05/21/15
20150138863
 Interleaved write assist for hierarchical bitline sram architectures patent thumbnailInterleaved write assist for hierarchical bitline sram architectures
An sram device includes a plurality of memory cells and a first metallization layer comprising a first pair of bitlines operable to couple to a first segment of the memory cells. The device also includes a second metallization layer comprising a second pair of bitlines operable to couple to a second segment of the memory cells and a write assist line interleaved with the first and second metallization layers to provide a substantially constant coupling capacitance with each of the first and second pairs of bitlines..
Lsi Corporation
05/14/15
20150132903
 Structure and  sram cell circuit patent thumbnailStructure and sram cell circuit
The present disclosure provides a static random access memory (sram) cell. The sram cell includes a first and a second pull-up devices; a first and a second pull-down devices configured with the first and second pull-up devices to form two cross-coupled inverters for data storage; and a first and second pass-gate devices configured with the two cross-coupled inverters to form a port for data access, wherein the first and second pull-down devices each includes a first channel doping feature of a first doping concentration, and the first and second pass-gate devices each includes a second channel doping feature of a second doping concentration greater than the first doping concentration..
05/14/15
20150131368
 Implementing sense amplifier for sensing local write driver with bootstrap write assist for sram arrays patent thumbnailImplementing sense amplifier for sensing local write driver with bootstrap write assist for sram arrays
A method and circuit for implementing sense amplifiers for sensing local write driver with bootstrap write assist for static random access memory (sram) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a sense amplifier used in both read and write operations with a write assist boost circuitry.
05/14/15
20150131366
 Voltage controller patent thumbnailVoltage controller
A voltage controller is provided that is connected to a voltage inducing circuit which is connected to a static random-access memory (sram) cell. The voltage controller comprises a voltage clamping circuit and a pull up circuit.
05/14/15
20150131365
 Spsram wrapper patent thumbnailSpsram wrapper
Among other things, one or more techniques or systems for facilitating access operations to a single port memory device are provided. Multiple access operations to a single port memory device, such as a 6 transistor bitcell array of an spsram, are performed during a single clock period of a system clock.
05/14/15
20150131364
 Negative bitline boost scheme for sram write-assist patent thumbnailNegative bitline boost scheme for sram write-assist
A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element.
05/07/15
20150127900
 Ternary content addressable memory utilizing common masks and hash lookups patent thumbnailTernary content addressable memory utilizing common masks and hash lookups
A ternary content-addressable memory (tcam) that is implemented based on other types of memory (e.g., sram) in conjunction with processing, including hashing functions. Such a h-tcam may be used, for example, in implementation of routing equipment.
Cisco Technology, Inc.
04/30/15
20150117093
 Method for driving semiconductor device patent thumbnailMethod for driving semiconductor device
A semiconductor device includes sram that stores data in an inverter loop including a cmos inverter, transistors electrically connected to an input terminal or an output terminal of the cmos inverter, and capacitors electrically connected to the corresponding transistors. The semiconductor device is configured to hold potentials corresponding to data at nodes between the transistors and the corresponding capacitors in a period during which supply of power to the cmos inverter stops.
Semiconductor Energy Laboratory Co., Ltd.
04/30/15
20150117092

Multi-channel physical interfaces and methods for static random access memory devices


An integrated circuit (ic) device can include a static random access memory (sram) section comprising a plurality of memory banks; and an interface comprising physical connections for more than eight memory channels, the connections for each memory channel including an address section including connections for sram control inputs and a complete address to access the memory banks, and a data section including data inputs and outputs (data ios) to transfer data for one memory bank.. .
Cypress Semiconductor Corporation
04/23/15
20150113492

Sram layouts


Roughly described, the cell layout in an sram array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area.
Synopsys, Inc.
04/23/15
20150109870

Arithmetic processing unit and driving method thereof


An arithmetic processing unit including an sram with low power consumption and performing backup and recovery operation with no burden on circuits. One embodiment is a memory device including a plurality of memory cells.
Semiconductor Energy Laboratory Co., Ltd.
04/23/15
20150109852

Data-controlled auxiliary branches for sram cell


A circuit includes a first inverter, a second inverter, a first auxiliary branch and a second auxiliary branch. The first and second inverters are cross-coupled to form a first storage node and a second storage node.
Taiwan Semiconductor Manufacturing Company, Ltd.
04/23/15
20150109845

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements


Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, rerams, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
Iii Holdings 2., Llc
04/16/15
20150103585

High stability static random access memory cell


A static random access memory (sram) cell is a latch circuit formed with two inverters each formed with a pmos transistor and an nmos transistor. The latch circuit is coupled to a capacitor through a switch.
United Microelectronics Corp.
04/16/15
20150102423

Method for finfet sram ratio tuning


A semiconductor device and method of forming the same include a substrate having a plurality of memory cells formed thereon. A memory cell includes pass-gate transistors, pull-up transistors, and pull-down transistors.
Semiconductor Manufacturing International (shanghai) Corporation
04/16/15
20150102421

Semiconductor device


A semiconductor device having an sram which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions..
Renesas Electronics Corporation
04/16/15
20150102417

Double trench well formation in sram cells


A method is provided for forming sram cells with low energy implants. Embodiments include forming deep trenches in a silicon substrate; forming a deep n-well or deep p-well around a bottom of each deep trench; filling the deep trenches with oxide; forming a first or second shallow trench between each pair of adjacent deep trenches; forming a first p-well or first n-well, respectively, above each deep n-well or p-well; forming a second n-well at a bottom of each first shallow trench; forming a p+ region above each second n-well on each side of each first shallow trench; filling the first shallow trenches with oxide; forming a second p-well at a bottom of each second shallow trench; filling the second shallow trenches with oxide; forming a p+ region above each second n-well on each side of each first shallow trench; and forming an n+ region above each second p-well..
Globalfoundries Inc.
04/09/15
20150098268

Semiconductor memory


The disclosed invention provides an sram capable of stably generating a puf-id without having to be powered on/off under control. The sram including a plurality of write ports is provided with a plurality of word lines, each transferring write data from each of the write ports to one memory cell.
Renesas Electronics Corporation
04/02/15
20150092477

Adaptive data-retention-voltage regulating system for sram


An adaptive data-retention-voltage regulating system for static random-access memory (srams) is revealed. The system includes a power supply unit, a data-retention-voltage (drv) monitor cell for monitoring static noise margin (snm) of sram, a data loss detector for generating a data loss signal, and a dynamic regulating controller that receives the data loss signal for generating a refresh signal and a switch signal.
National Cheng Kung University
04/02/15
20150092476

Dual port sram with dummy read recovery


An integrated includes a dual port memory cell such as a sram cell. A first port dummy read recovery block couples the first port complementary bit line to a high voltage supply node during a write logic low operation to the data node through the second port bit line, and couples the first port bit line to a high voltage supply node during a write logic low operation to the complementary data node through the second port complementary bit line.
Taiwan Semiconductor Manufacturing Co., Ltd.
04/02/15
20150091928

Image processing device and method thereof


An image processing device that converts original image data to target image data is provided. The image processing device includes: a static random access memory (sram); an image scaling circuit that generates scaled image data according to the original image data and stores the scaled image data to the sram; and a video encoding circuit that accesses the scaled image data from the sram and encodes the accessed scaled image data to generate the target image data.
Mstar Semiconductor, Inc.
04/02/15
20150091097

Hardmask for a halo/extension implant of a static random access memory (sram) layout


Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (sram) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (pd) transistor over a substrate; forming a pass-gate (pg) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the pd transistor and a second section adjacent the pg transistor, wherein a distance between the first section and the pd transistor is shorter than a distance between the second section and the pg transistor.
Globalfoundries Inc.
03/26/15
20150085566

Input trigger independent low leakage memory circuit


Wordline-driver biasing and column-based source-biasing circuitry facilitate reduced current leakage, for example, in soc device sram circuits in a manner that is independent of the read/write/standby operating mode, and without an external trigger. Wordline-driver-biasing circuitry turns off (i.e., decouples from system power) wordline-drivers that are connected to unselected wordlines during read/write operations using one of a decoder-enable signal, which is generated in response to row address values, or based on the activation of a self-timing internal clock, which is generated by the memory circuit when it is activated (i.e., switched from standby to read/write mode).
Synopsys, Inc.
03/19/15
20150078068

Integrated circuits with sram cells having additional read stacks


Integrated circuits that include sram cells having additional read stacks are provided. In accordance with one embodiment an integrated circuit includes a memory storage array of memory cells.
Globalfoundries Inc.
03/19/15
20150078067

Method of measuring threshold voltage of mos transistor in sram array


Methods of measuring threshold voltages of mos transistors in a sram array are provided. The sram array includes array-arranged cells having a first pass nmos transistor, a second pass nmos transistor, a first pull-down nmos transistor, a second pull-down nmos transistor, a first pull-up pmos transistor, and a second pull-up transistor.
Semiconductor Manufacturing International (beijing) Corporation
03/12/15
20150074344

Adaptive memory system for enhancing the performance of an external computing device


An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., static random access memory or sram), a second memory type (e.g., dynamic random access memory or dram), a third memory type (e.g., flash), an internal bus system, and an external bus interface.
Mobile Semiconductor Corporation
03/12/15
20150070977

Semiconductor device


A well voltage supply cell includes third gate electrode group (including a third gate electrode corresponding to a first gate electrode) located symmetrically to first gate electrode group (including the first gate electrode constituting an access transistor) of a first sram cell, fourth gate electrode group (including a fourth gate electrode corresponding to a second gate electrode) located symmetrically to second gate electrode group (including the second gate electrode constituting an access transistor) of a second sram cell. A p-type impurity diffusion region located on a p well between the third gate electrode and the fourth gate electrode located opposite to each other, a first n-type impurity diffusion region located on the side of the third gate electrode closer to the first sram cell, and a second n-type impurity diffusion region located on the side of the fourth gate electrode closer to the second sram cell..
Renesas Electronics Corporation
03/12/15
20150070976

Semiconductor device


There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an sram memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation.
Renesas Electronics Corporation
03/05/15
20150064853

Integrated circuit including dram and sram/logic


An integrated circuit comprising an n+ type layer, a buffer layer arranged on the n+ type layer; a p type region formed on with the buffer layer; an insulator layer overlying the n+ type layer, a silicon layer overlying the insulator layer, an embedded ram fet formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the n+ type layer, the n+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the n+ type layer, a first logic ram fet formed in the silicon layer above the p type region, the p type region functional as a p-type back gate of the first logic ram fet, and a second contact through the silicon layer and the insulating layer and electrically connecting to the p type region.. .
International Business Machines Corporation
03/05/15
20150063010

Negative bias thermal instability stress testing for static random access memory (sram)


In one embodiment, one portion of an sram array is stressed by first writing a “1” in every bit of the array, followed by an evaluation of the relevant parameters of the array using a ring oscillator driven by a mirrored bit-line current, the ring oscillator not in line of the bit-line of the sram. The other portion of the array is then stressed after writing a “0” in every bit of the array.
Synopsys, Inc.
03/05/15
20150063009

Dynamic static random access memory (sram) array characterization


A sensor circuit is used to provide bit-cell read strength distribution of an sram array. A current-mirror circuit mirroring the bit-line current of an sram array is used to power the sensor circuit.
Synopsys, Inc.
03/05/15
20150063007

Static random access memory device including dual power line and bit line precharge method thereof


A static random access memory (sram) device is provided. A memory cell is supplied with a first driving voltage.
02/26/15
20150058928

Applying circuit delay-based physically unclonable functions (pufs) for masking operation of memory-based pufs to resist invasive and clone attacks


One feature pertains to generating a unique identifier for an electronic device by combining static random access memory (sram) pufs and circuit delay based pufs (e.g., ring oscillator (ro) pufs, arbiter pufs, etc.). The circuit delay based pufs may be used to conceal either a challenge to, and/or response from, the sram pufs, thereby inhibiting an attacker from being able to clone a memory device's response..
Qualcomm Incorporated
02/26/15
20150056792

Finfet and fabrication


An improved finfet and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon.
Intemational Business Machines Corporation
02/26/15
20150055667

Laser component and producing it


A laser component includes a housing in which a first carrier block is arranged. A first laser chip having an emission direction is arranged on a longitudinal side of the first carrier block.
Osram Gmbh
02/26/15
20150055402

Novel 3d structure for advanced sram design to avoid half-selected issue


Disclosed is a novel static random access memory (sram) device. The sram device comprises a plurality of memory array layers vertically disposed one above another, a layer decoder circuit disposed on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs wherein each complementary bit line pair extends vertically to couple a memory cell in each memory array layer.
Taiwan Semiconductor Manufacturing Company Limited
02/26/15
20150055338

Led lighting device with mint-colored and amber-colored light-emitting diodes


Various embodiments may relate to an led lighting device, including at least one mint-colored light-emitting diode, at least one amber-colored light-emitting diode and at least one yellow light-emitting diode and/or blue light-emitting diode.. .
Osram Gmbh
02/26/15
20150055319

Wavelength conversion structure for a light source


A wavelength conversion structure for a light source including a solid-state light-emitting device. The wavelength conversion structure includes one or more apertures formed therein.
Osram Sylvania Inc.
02/26/15
20150053951

Organic light-emitting device and producing an organic light-emitting device


The invention relates to an organic light-emitting part having a functional layer stack (10), which functional layer stack has a substrate (1), a first electrode (2) above the substrate, an organic functional layer stack (4) above the first electrode, having an organic light-emitting layer (5), and a second electrode (3) above the organic functional layer stack, wherein a layer (1, 2, 3) of the functional layer stack (10) forms a carrier layer (6) for a diffusion layer (7), wherein the diffusion layer (7) has at least one first and one second organic component (71, 72) having indices of refraction that differ from each other, wherein the first organic component (71) is hydrophobic and the second organic component (72) is hydrophilic, wherein the glass transition temperature of a mixture of the first organic component (71) and the second organic component (72); lies above the room temperature and wherein the first organic component (71) and the second organic component (72) are partially segregated in the diffusion layer (7) and the diffusion layer (7) has a mesoscopic boundary layer (75) between the first and second organic components (71, 72) or the diffusion layer (7) is present as a mesophase (78) having the first and second organic component (71, 72). The invention further relates to a method for producing an organic light-emitting part..
Osram Opto Semiconductors Gmbh
02/26/15
20150053919

Optoelectronic semiconductor chip and producing an optoelectronic semiconductor chip


An optoelectronic semiconductor chip having a semiconductor layer sequence includes at least one active layer that generates primary radiation; a plurality of conversion layers that at least partially absorb the primary radiation and convert the primary radiation into secondary radiation of a longer wavelength than the primary radiation; and a roughened portion that extends at least into one of the conversion layers, wherein the roughened portion has a random structure, the semiconductor layer sequence is arranged on a carrier, a top side of the semiconductor layer sequence facing away from the carrier is formed by the roughened portion, the at least one active layer is located between the carrier and the conversion layers, and the roughened portion includes a plurality of recesses free of a semiconductor material.. .
Osram Opto Semiconductors Gmbh
02/19/15
20150049541

Semiconductor memory device


When threshold voltages of constituent transistors are reduced in order to operate an sram circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the sram circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of mos transistors in sram memory cells mc by controlling a potential of a source line ssl of the driver mos transistors in the memory cells..
Renesas Electronics Corporation
02/12/15
20150046692

System on chip for reducing wake-up time, operating same, and computer system including same


A system on chip (soc) includes an internal read-only memory (rom) configured to store a first boot loader; a first internal static random access memory (sram) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal sram configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (dram) controller configured to load an operating system (os) from the booting device into a dram according to control of the second boot loader.. .
02/05/15
20150036418

Circuits for voltage or current biasing static random access memory (sram) bitcells during sram reset operations, and related systems and methods


Circuits for voltage or current biasing static random access memory (sram) bitcells during sram reset operations are disclosed. Related systems and methods are also disclosed.
Qualcomm Incorporated
02/05/15
20150036417

Sram read buffer with reduced sensing delay and improved sensing margin


A device includes a static random access memory (sram) cell and a read buffer coupled to an output of the sram cell. The read buffer includes an inverter and a switch.
Industry-academic Cooperation Foundation, Yonsei University
01/29/15
20150029785

Methods for operating a finfet sram array


A method of operating an sram array may include: providing a plurality of bit cells, each of the plurality of bit cells comprising a cross coupled inverter pair; a first pass gate; and a second pass gate. A word line voltage may be applied to the first pass gate and the second pass gate, while a first cell positive voltage supply cvdd may be applied to terminals of the cross coupled inverter pair.
Taiwan Semiconductor Manufacturing Company, Ltd.
01/29/15
20150029784

Semiconductor integrated circuit device


There is provided a semiconductor integrated circuit device that can generate a unique id with the suppression of overhead. When a unique id is generated, the potential of a word line of a memory cell in an sram is raised above the power supply voltage of the sram, and then lowered below the power supply voltage of the sram.
Renesas Electronics Corporation
01/29/15
20150029783

Method of detecting transistors mismatch in a sram cell


The present invention provides a method of detecting the transistor mismatch in a sram cell. The sram cell comprises two pass-gate transistors and a bi-stable circuit including two pull up transistors and two pull down transistors.
Shanghai Huali Microelectronics Corporation
01/22/15
20150023091

Semiconductor device having timing control for read-write memory access operations


A semiconductor device avoids the disturb problem and the collision between write and read operations in a dp-sram cell or a 2p-sram cell. The semiconductor device 1 includes a write word line wla and a read word line wlb each coupled to memory cells 3.
Renesas Electronics Corporation
01/22/15
20150021706

Integrated circuit and forming the integrated circuit with improved logic transistor performance and sram transistor yield


In an integrated circuit that includes an nmos logic transistor, an nmos sram transistor, and a resistor, the gate of the sram transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps.. .
Texas Instruments Incorporated
01/15/15
20150016188

Method for managing the operation of a memory device having a sram memory plane and a non volatile memory plane, and corresponding memory device


A method can be used for managing the operation of a memory cell that includes an sram elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the sram elementary memory cell and the non-volatile elementary memory cell.
Stmicroelectronics (rousset) Sas
01/15/15
20150016182

Sram memory card and voltage monitoring circuit


An sram memory card includes a monitoring unit that monitors, via a contact, a power supply voltage generated by a battery, set an on value in an alarm signal when electric potential at the contact is lower than a threshold and set an off value in the alarm signal when the electric potential at the contact is equal to or higher than the threshold, and output the alarm signal to an apparatus via an interface unit; a detecting unit that detects an on/off state of the power supply of the apparatus via the interface unit; and a discharge circuit that discharges, according to the on/off state of the power supply of the apparatus detected by the detecting unit, charges accumulated in a first electrode of a capacitive element.. .
Mitsubishi Electric Corporation
01/15/15
20150015274

Direct memory based ring oscillator (dmro) for on-chip evaluation of sram cell delay and stability


A novel and useful direct memory based ring oscillator (dmro) circuit and related method for on-chip evaluation of sram delay and stability. The dmro circuit uses an un-modified sram cell in each delay stage of the oscillator.
International Business Machines Corporation
01/08/15
20150012690

Multi-leveled cache management in a hybrid storage system


A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, sdram, and sram. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory.
01/08/15
20150009741

Valid command detection based on stack position identifiers in memory devices configured for stacked arrangements


Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, rerams, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
Iii Holdings 2, Llc
01/08/15
20150009740

Latency adjustment based on stack position identifier in memory devices configured for stacked arrangements


Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, rerams, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
01/08/15
20150009739

Memory devices with serially connected signals for stacked arrangements


Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
Iii Holdings 2, Llc
01/08/15
20150009738

Pad selection in memory devices configured for stacked arrangements


Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
Iii Holdings 2, Llc
01/08/15
20150009737

Self-refresh adjustment in memory devices configured for stacked arrangements


Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
Iii Holdings 2, Llc
01/08/15
20150008971

Noise current compensation circuit


Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals a and b, and two control terminals con and conf.
Southeast University
01/08/15
20150008533

Multi-port sram manufacturing


Some embodiments relate to an integrated circuit including fin field effect transistors (finfets) thereon. The integrated circuit includes first and second active fin regions having a first conductivity type and spaced apart from one another.
Taiwan Semiconductor Manufacturing Co., Ltd.
01/08/15
20150008522

Semiconductor device


Improvements are achieved in the characteristics of a semiconductor device including sram memory cells. Under an active region in which an access transistor forming an sram is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region.
Renesas Electronics Corporation
01/01/15
20150003148

Methods and designing and constructing dual write memory circuits with voltage assist


Static random access memory (sram) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6t) sram bit cell is proposed.
Memoir Systems, Inc.
01/01/15
20150003147

Sram restore tracking circuit and method


Novel and useful sram restore tracking circuit adapted to improve the tracking of sram cell behavior for different pvt corners. The sram array access path is mainly influenced by two stages: (1) the wordline (wl) delay and (2) the sram cell delay.
International Business Machines Corporation


Popular terms: [SEARCH]

Sram topics: Random Access, Static Random Access Memory, Memory Cell, Semiconductor, Memory Cells, Transistors, Semiconductor Memory, Memory Device, Integrated Circuit, Robustness, Field Effect Transistor, Clamping Circuit, Internal Node, Implantation, Data Storage

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