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Sram patents


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new patent Techniques for forming a compacted array of functional cells
Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (ngl) processes, such as electron-beam direct write (ebdw) and extreme ultraviolet lithography (euvl), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (fpga) structures configured with logic cells, static random-access memory (sram) structures configured with bit cells, or other memory or logic devices having cell-based structures.
Intel Corporation

new patent Sram timing-based physically unclonable function
Methods and apparatus for creating a physically unclonable function for sram are disclosed. An example method includes after applying a voltage to a memory array: determining a first duration between the applying of the voltage and a first output of a first bit cell, the first output corresponding to a first value stored in the first bit cell, and determining a second duration between the applying of the voltage and a second output of a second bit cell, the second output corresponding to a second value stored in the second bit cell.
Texas Instruments Incorporated

Tunable negative bitline write assist and boost attenuation circuit
An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (sram) arrays. The apparatus includes a memory array comprising a plurality of sram cells.
International Business Machines Corporation

Boost control to improve sram write operation
Approaches for providing write-assist boost for a static random access memory (sram) array are provided. A circuit includes a write driver of a static random access memory (sram) array.
International Business Machines Corporation

Two-port sram connection structure
A static random access memory (sram) device is provided in accordance with some embodiments. The sram device comprises a plurality of two-port sram arrays, which comprise a plurality of two-port sram cells.
Taiwan Semiconductor Manufacturing Co., Ltd.

Static random access memory
The invention concerns a static random access memory (sram) comprising: a plurality of memory cells each having a pair of cross-coupled inverters (102, 104), a first of the inverters (102) being supplied by first and second power supply rails (vdd, vss) and a second of the inverters (104) being supplied by third and fourth supply rails (114, 116), an input of the second inverter (102) being coupled to a first bit line (bl, wbl) via a first transistor (118); and a power supply circuit (120) adapted to apply a first voltage difference (vdd) across the first and second power supply rails (vdd, vss) and a second voltage difference (vdh, vsl) across the third and fourth power supply rails (114, 116), the second voltage difference being greater than the first voltage difference.. .
Commissariat à L'energie Atomique Et Aux Energies Alternatives

High-speed pseudo-dual-port memory with separate precharge controls
A pseudo-dual-port (pdp) memory such as a pdp sram is provided that independently controls the bit line precharging and the sense amplifier precharging to increase memory operating speed while eliminating or reducing the discharge of crowbar current.. .
Qualcomm Incorporated

Non-volatile static ram and operation thereof
A memory device and array which includes a static random access memory (sram) circuit coupled to a non-volatile circuit, such as a ferroelectric-ram (f-ram) circuit, in which the f-ram circuit stores a bit of data from the sram circuit during power-out periods, the f-ram circuit is further coupled to bit-line(s) to output the bit of data stored in the f-ram circuit when operation power is restored.. .
Cypress Semiconductor Corporation

Circuit to improve sram stability
Approaches for stability of cells in a static random access memory (sram) array are provided. A circuit includes a precharging circuit configured to precharge bitlines of a static random access memory (sram) array to a first voltage potential for a non-read operation and to a second voltage potential for a read operation.
International Business Machines Corporation

Semiconductor device having capability of generating chip identification information
A semiconductor device having a capability of generating chip identification information includes: an sram macro having a plurality of memory cells arranged in rows and columns: a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.. .
Renesas Electronics Corporation

Multiple-port sram device

A multiple-port memory cell includes first conductive lines in a first metal layer, second conductive lines in a second metal layer, third conductive lines a third metal layer, and fourth conductive lines in a fourth metal layer. The first conductive lines include a write bit line electrically coupled with a write bit line node; a first read bit line electrically coupled with a first read bit line node; and a second read bit line electrically coupled with a second read bit line node.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor integrated circuit device

There is provided a semiconductor integrated circuit device that can generate a unique id with the suppression of overhead. When a unique id is generated, the potential of a word line of a memory cell in an sram is raised above the power supply voltage of the sram, and then lowered below the power supply voltage of the sram.
Renesas Electronics Corporation

Low-power row-oriented memory write assist circuit

Aspects of the present disclosure generally relate to static random access memory (sram), and more specifically, to a low-power, row-oriented memory write assist circuit. The sram may generally comprise an array of bit cells arranged in rows and columns, wherein each bit cell in a row is selected for writing via a corresponding wordline for that row and wherein each bit cell in a column is coupled to a corresponding pair of bitlines for supplying complementary data values, and at least one row-oriented write assist circuit configured to temporarily reduce, to a desired voltage level, a voltage on an internal voltage line used to supply power to the bit cells of a row selected for writing..
Cisco Technology, Inc.

Aging sensor for a static random access memory (sram)

A static random access memory (sram) includes a first bitcell and a second bitcell. The first bitcell includes an aging transistor and the second bitcell includes a non-aging transistor.
Qualcomm Incorporated

Dual-port static random-access memory cell

The present disclosure provides a static random access memory (sram) cell comprising first, second, and third fins defined in various well regions. The fins are spaced from each other along a first direction and extend lengthwise generally along a second direction perpendicular to the first direction.
Taiwan Semiconductor Manufacturing Company, Ltd.

Optoelectronic component and producing an optoelectronic component

The invention relates to an optoelectronic component (100) comprising an organic light emitting diode (1) designed for emitting radiation and/or heat, a substrate (2), on which the organic light emitting diode is arranged, wherein the substrate (2) comprises a first substrate material (21) and at least one substrate cavity (22) which is filled with a second substrate material (23) different than the first substrate material (21), wherein the second substrate material (23) is designed to dissipate the heat emitted by the organic light emitting diode (1).. .
Osram Oled Gmbh

Light-emitting device and producing a light-emitting device

A light-emitting device includes a substrate having a substrate upper side, a layer sequence arranged on the substrate upper side and having at least one active, light-emitting, organic layer, wherein the layer sequence includes a plurality of emission regions that emit light, current-conducting rails which are a part of the layer sequence, wherein, in a plan view of the substrate upper side, the emissionr egions of the layer sequence are arranged next to the current-conducting rails, an encapsulation glass, wherein the layer sequence is arranged between the substrate and the encapsulation glass, and spacers formed as elevations on an encapsulation glass underside and facing towards the layer sequence of the encapsulation glass, wherein, in a plan view of the substrate upper side, the spacers at least partly overlap with the current-conducting rails, and the spacers prevent direct contact between the encapsulation glass and the layer sequence in the emission regions.. .
Osram Oled Gmbh

Optoelectronic semiconductor chip, optoelectronic semiconductor component, and a producing an optoelectronic semiconductor component

An optoelectronic semiconductor chip includes a semiconductor body that emits primary light, and a luminescence conversion element that emits secondary light by wavelength conversion of at least part of the primary light, wherein the luminescence conversion element has a first lamina fixed to a first partial region of an outer surface of the semiconductor body, the outer surface emitting primary light, and leaving free a second partial region of the outer surface, the luminescence conversion element has a second lamina fixed to a surface of the first lamina facing away from the semiconductor body and spaced apart from the semiconductor body, the first lamina is at least partly transmissive to the primary radiation, a section of the second lamina covers at least the second partial region, and at least the section of the second lamina is absorbent and/or reflective and/or scattering for the primary radiation.. .
Osram Opto Semiconductors Gmbh

Systems and methods for sram with backup non-volatile memory that includes mtj resistive elements

A memory device has an sram that stores a logic state. A first mtj has two terminals.
Freescale Semiconductor, Inc.

Device comprising a plurality of fdsoi static random-access memory bitcells and operation thereof

A device including a plurality of static random-access memory (sram) bitcells arranged in rows and columns, wherein the sram bitcells comprise fully depleted silicon-on-insulator field effect transistors (fdsoi-fets). The fdsoi-fets comprise p-channel-pull-up-transistors, wherein each p-channel-pull-up-transistor comprises a back gate.
Globalfoundries Inc.

Complementary bipolar sram

A complementary lateral bipolar sram device and method of operating. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state.
International Business Machines Corporation

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, rerams, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
Iii Holdings 2, Llc

System on chip for reducing wake-up time, operating same, and computer system including same

A system on chip (soc) includes an internal read-only memory (rom) configured to store a first boot loader; a first internal static random access memory (sram) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal sram configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (dram) controller configured to load an operating system (os) from the booting device into a dram according to control of the second boot loader.. .
Samsung Electronics Co., Ltd.

Light-emitting apparatus

In various embodiments, a light-emitting apparatus is provided. The light-emitting apparatus includes at least one semiconductor light source configured to emit at least one primary light beam, a deflection device configured to deflect the at least one primary light beam onto respectively associated different positions on a phosphor body, at least one light detector configured to detect light that was emitted by the phosphor body, and an evaluation device.
Osram Gmbh

Semiconductor devices and methods of manufacture thereof

A method of forming an sram cell includes forming a first vertical pull-down transistor, a second vertical pull-down transistor, a first vertical pass-gate transistor, and a second vertical pass-gate transistor over a semiconductor substrate. The method includes forming a first conductive trace over a top surface of the first vertical pull-down transistor and the first vertical pass-gate transistor, forming a second conductive trace over a top surface of the second vertical pull-down transistor and the second vertical pass-gate transistor, and forming a first vertical pull-up transistor over a first portion of the first conductive trace.
Taiwan Semiconductor Manufacturing Company, Ltd.

Power savings via selection of sram power source

A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the sram cell when the system voltage is higher than the memory supply voltage with some margin.
Nvidia Corportion

Compact self-aligned implantation transistor edge resistor for sram seu mitigation

This disclosure is directed to techniques for fabricating cmos devices for sram cells with resistors formed along transistor well sidewall edges by self-aligned, angled implantation, which may enable more compact sram architecture with seu mitigation, such as for space-based or other radiation-hardened applications. An example method includes implanting a dopant into a doped semiconductor well covered by a barrier, wherein the doped semiconductor well is disposed on a buried insulator and wherein the dopant is of opposite doping type to the doped semiconductor well, thereby fortning a resistor on an edge of the doped semiconductor well, wherein the resistor has the opposite doping type.
Honeywell International Inc.

Methods of reading six-transistor sram cells

A six-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with methods of operation. Methods of increasing the operational speed in reading the contents of a selected memory cell in an array of such memory cells while lowering power consumption, and of avoiding an indeterminate memory cell state when a memory cell is “awakened” from standby are described..
Kilopass Technology, Inc.

Semiconductor device

There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an sram memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation.
Renesas Electronics Corporation

Sram multi-cell operations

A multi-memory cell operator includes a non-destructive memory array, an activation unit and a multiple column decoder. The non-destructive memory array has first and second bit lines per column.
Gsi Technology Inc.

Semiconductor integrated circuit device

Prior known static random access memory (sram) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a p-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the p-type well region in which an inverter making up an sram cell is formed is subdivided into two portions, which are disposed on the opposite sides of an n-type well region nw1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines.
Renesas Electronics Corporation

Memory bit cell for reduced layout area

An approach for providing sram bit cells with miniaturized bit cells, without local interconnection layers, with improved lithographic printability, and enabling methodology are disclosed. Embodiments include providing first color structures, in a m1 layer, including a first word line, a first bit line, a second bit line, a first ground line, a second ground line, a second latch line or a combination thereof, wherein the first color structures include side edges longer than tip edges; providing second color structures, in the m1 layer, including a second word line, a first power line, a second power line, a first latch line or a combination thereof, wherein the second color structures include side edges longer than tip edges; and forming a bit cell including the first color structures and the second color structures, wherein adjacent tip edges include a first color structure tip edge and a second color structure tip edge..
Globalfoundries Inc.

Static random access memory

A static random access memory (sram) is disclosed. The sram includes a plurality of sram cells on a substrate, in which each of the sram cells comprises: a gate structure on the substrate; a first interlayer dielectric (ild) layer around the gate structure; a first contact plug in the first ild layer; a second ild layer on the first ild layer; and a second contact plug in the second ild layer and electrically connected to the first contact plug..
United Microelectronics Corp.

Offset detection

There is provided a method of detecting offset in a sense amplifier of an sram memory unit. The method comprises using a sense amplifier of the sram memory unit to implement a read of a first data value stored in a memory cell of the sram memory unit, and measuring a first time for the sense amplifier to read the first data value.
Surecore Limited

Error correction in solid state drives (ssd)

A paging scheme for a solid state drive (ssd) error correction mechanism that exchanges portions of a parity component, such as a page, between sram and less expensive dram, which stores the remainder of a context of pages. A parity operation applies an xor function to corresponding memory positions in the pages of the context.

Readout circuitry for image sensor

Readout circuitry to readout an array of image sensor pixels includes readout units that include a plurality of analog-to-digital converters (“adcs”), a plurality of blocks of static random-access memory (“sram”), and a plurality of blocks of dynamic random-access memory (“dram”). The plurality adcs is coupled to readout analog image signals two-dimensional blocks of the array of image sensor pixels.
Omnivision Technologies, Inc.

Semiconductor device

To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an lcd driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an lcd driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but srams (internal circuits) are arranged..
Renesas Electronics Corporation

Circuits and methods for performance optimization of sram memory

In described examples, a memory controller circuit controls accesses to an sram circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the sram circuit indicating that a series of sram cells along a selected row of sram cells will be accessed; a precharge first mode signal to the sram circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the sram circuit indicating that a last access along the selected row will occur.
Texas Instruments Incorporated

Hybrid finfet/nanowire sram cell using selective germanium condensation

A semiconductor device including a pfet and an nfet where: (i) the gate and conductor channel of the pfet are electrically insulated from a buried oxide layer; and (ii) the conductor channel of the nfet is in the form of a fin extending upwards from, and in electrical contact with, the buried oxide layer. Also, a method of making the pfet by adding a fin structure extending from the top surface of the buried oxide layer, then condensing germanium locally into the lattice structure of the lower portion of the fin structure, and then etching away the lower portion of the fin structure so that it becomes a carrier channel suspended above, and electrically insulated from the buried oxide layer..
International Business Machines Corporation

Implementation of a one time programmable memory using a mram stack design

An integrated circuit includes a magnetic otp memory array formed of multiple magnetic otp memory cells having an mtj stack with a fixed magnetic layer, a tunnel barrier insulating layer, a free magnetic layer, and a second electrode. When a voltage is applied across the magnetic otp memory cell, the resistance of the mtj stack and the gating transistor form a voltage divider to apply a large voltage across the mtj stack to breakdown the tunnel barrier to short the fixed layer to the free layer.
Headway Technologies, Inc.

Semiconductor storage device

A semiconductor storage device includes an sram memory cell composed of a drive transistor, a transfer transistor and a load transistor, an i/o circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the i/o circuit between a resume standby mode and a normal operation mode, wherein the i/o circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.. .
Renesas Electronics Corporation

Static random access memory and operating the same

A static random access memory (sram) including at least a memory cell array, a first data line, a second data line, a third data line and a driver circuit. The first data line is electrically coupled with the memory cell array.
Taiwan Semiconductor Manufacturing Company, Ltd.

Dual-port sram cell structure with vertical devices

Dual-port sram cells are described. In an embodiment, a cell includes first and second pull-down, first and second pull-up, and first through fourth pass-gate transistors.
Taiwan Semiconductor Manufacturing Company, Ltd.

Method to identify extrinsic sram bits for failure analysis based on fail count voltage response

A method and an apparatus for identifying non-intrinsic defect bits from a population of failing bits for failure analysis to characterize the extrinsic failure mechanisms is provided. Embodiments include performing a failure mode test on a bank of a memory array at different low vdd; determining optimal bank size to observe plateaus of fail counts; determining fail counts of the bank at each different low vdd; determining a plateau of the fail counts; determining whether the plateau represents extrinsic bits of the bank; and submitting the extrinsic bits for root cause analysis..
Globalfoundries Inc.

Semiconductor device and driving semiconductor device

To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an sram provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions.
Semiconductor Energy Laboratory Co., Ltd.

Self-storing and self-restoring non-volatile static random access memory

An apparatus is provided which comprises: a static random access memory (sram) cell with at least two non-volatile (nv) resistive memory elements integrated within the sram cell; and first logic to self-store data stored in the sram cell to the at least two nv resistive memory elements. A method is provided which comprises performing a self-storing operation, when a voltage applied to a sram cell decreases to a threshold voltage, to store voltage states of the sram cell to at least two nv resistive memory elements, wherein the at least two nv resistive memory elements are integrated with the sram cell; and performing self-restoring operation, when the voltage applied to the sram cell increases to the threshold voltage, by copying data from the at least two nv resistive memory elements to storage nodes of the sram cell..
Intel Corporation

Semiconductor device including memory cell array and power supply region

A semiconductor device having an sram which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions..
Renesas Electronics Corporation

Semiconductor device and manufacturing same

An object of the invention is to provide a semiconductor device having less cracking or peeling and a method of manufacturing the same. A fuse portion of a semiconductor device has bit lines electrically coupled to a sram memory cell.
Renesas Electronics Corporation

Programmable logic device with on-chip user non-volatile memory

The present invention discloses a programmable logic device with on-chip user non-volatile memory, comprising: a programmable logic array, which is a user programmable logic array and comprises a sram array and a logic block array with an interface; the sram array is used to store configuration data to control the logic block array in real time, therefore, the logic block can be formed to perform the function a user desires; a non-volatile memory block, comprising one or more segments storing configuration data and one or more segments storing user data which is used during fpga's normal operation after configuration; the non-volatile memory block has only one interface, and the non-volatile memory block connects to a programming controller through the interface; a programming controller, which can randomly access the non-volatile memory through a data bus, an address bus, and corresponding control signals.. .
Gowin Semiconductor Corporation, Ltd.

Sram memory cell and sram memory

Various embodiments provide semiconductor structures and their fabrication methods. An sram memory cell can include at least one semiconductor structure, and an sram memory can include at least one sram memory cell.
Semiconductor Manufacturing International Corp.

Improved sram storage unit based on dice structure

The present invention provides an improved sram memory cell based on a dice structure, which comprises following structures: four inverter structures formed through arranging pmos transistors and nmos transistors in series, wherein the part between the drains of a pmos transistor and an nmos transistor serves as a storage node; each storage node controls the gate voltage of an nmos transistor of the other inverter structure and of a pmos transistor of another inverter structure; a transmission structure consisting of four nmos transistors, whose source, gate and drain are respectively connected with a bit line/bit bar line, a word line and a storage node. The use of an improved sram memory cell based on a dice structure not only avoids such defects as small static noise margin and being prone to transmission error facing the traditional cell structures consisting of 6 transistors, but also resolves the problem that the current sram storage cells based on a dice structure can easily be affected by the electrical level of storage nodes.
Institute Of Microelectronics, Chinese Academy Of Sciences

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes: a memory cell array including an sram cell; and a first voltage generator including first and second circuits. The first and second circuits include a diode-connected first transistor and a diode-connected second transistor, respectively.
Kabushiki Kaisha Toshiba

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes an sram. The sram comprises a memory cell including a first inverter, a second inverter, a first transfer transistor, and a second transfer transistor and a peripheral circuit configured to supply various voltages to a word line, a first bit line, and a second bit line.
Kabushiki Kaisha Toshiba

Display control device

The display controller (1) includes: a dram (31); a sram (32) which consumes electric power less than the dram (31); an update judging section (61); a secondary compression section (70); and a decompression section (40). In a case where the update judging section (61) has judged that image data is not updated, (i) the secondary compression section (70) compresses image data and then stores compressed image data in the sram (32), (ii) the dram (31) stops a memory retaining operation, and (iii) the decompression section (40) decompresses the compressed image data and then supplies decompressed data to an lcd (3)..
Sharp Kabushiki Kaisha

Sram topics:
  • Random Access
  • Static Random Access Memory
  • Memory Cell
  • Semiconductor
  • Memory Cells
  • Transistors
  • Semiconductor Memory
  • Memory Device
  • Integrated Circuit
  • Robustness
  • Field Effect Transistor
  • Clamping Circuit
  • Internal Node
  • Implantation
  • Data Storage

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    This listing is a sample listing of patent applications related to Sram for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Sram with additional patents listed. Browse our RSS directory or Search for other possible listings.


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