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Sram patents



      
           
This page is updated frequently with new Sram-related patent applications. Subscribe to the Sram RSS feed to automatically get the update: related Sram RSS feeds. RSS updates for this page: Sram RSS RSS


Semiconductor device

Renesas Electronics

Semiconductor device

Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail sram memories

Lsi

Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail sram memories

Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail sram memories

Nvidia

Hybrid approach to write assist for memory array


Date/App# patent app List of recent Sram-related patents
07/23/15
20150206890 
 Cell layout for sram finfet transistors patent thumbnailCell layout for sram finfet transistors
An sram array and method of making is disclosed. Each sram cell comprises two pull-up (pu), two pass-gate (pg), and two pull-down (pd) finfets.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206889 
 Semiconductor device patent thumbnailSemiconductor device
A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an sram memory cell. In the sram memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor.
Renesas Electronics Corporation


07/23/15
20150206578 
 Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail sram memories patent thumbnailArea-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail sram memories
In one embodiment, a self-timed, dual-rail sram includes a self-timing circuit having a logic gate that is powered by voltage vdd and configured to receive a fire-sense-amplifier timing signal and to produce a vdd-domain sense-amplifier-enable signal soelv. The self-timing circuit includes an inverting level-shifter having complementary n-type and p-type transistors connected in series between voltage vdda and ground.
Lsi Corporation


07/23/15
20150206577 
 Hybrid approach to write assist for memory array patent thumbnailHybrid approach to write assist for memory array
A hybrid write-assist memory system includes an array voltage supply and a static random access memory (sram) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the sram cell and provides a voltage reduction of the separable cell supply voltage during a write operation.
Nvidia Corporation


07/23/15
20150206576 
 Negative bit line write assist for memory array patent thumbnailNegative bit line write assist for memory array
A negative bit line write assist system includes an array voltage supply and a static random access memory (sram) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the sram cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation.
Nvidia Corporation


07/16/15
20150200194 
 Method of manufacturing a semiconductor device patent thumbnailMethod of manufacturing a semiconductor device
A method of manufacturing a semiconductor device is provided. The method includes forming a fin structure on a semiconductor substrate and forming a well region in the semiconductor substrate by ion implantation so as to form transistors.
Semiconductor Manufacturing International (shanghai) Corporation


07/16/15
20150200107 
 Dense finfet sram patent thumbnailDense finfet sram
A method for fabricating the device includes patterning a first structure and a second structure on a semiconductor device. A first angled ion implantation is applied to the second structure such that the first structure is protected and a second angled ion implantation is applied to the first structure such that the second structure is protected, wherein exposed portions of the first and second structures have an altered rate of oxidation.
International Business Machines Corporation


07/16/15
20150200006 
 Sram write driver with improved drive strength patent thumbnailSram write driver with improved drive strength
A subsystem configured to write data to a static random access memory cell employs a single n-channel mos device connected to ground in each leg of the bi-stable memory cell to overdrive the stored data. The subsystem implements the dual control required to effect matrix operation of the sram cell in the gate circuit of the single n-channel mos device in the drive path.
Nvidia Corporation


07/16/15
20150199223 
 Approach to predictive verification of write integrity in a memory driver patent thumbnailApproach to predictive verification of write integrity in a memory driver
A subsystem is configured to apply an offset voltage to a test, or canary, sram write driver circuit to create a condition that induces failure of the write operation. The offset voltage is incrementally increased until failure of the test write operation occurs in the canary sram circuit.
Nvidia Corporation


07/09/15
20150194432 
 Butted contact shape to improve sram leakage current patent thumbnailButted contact shape to improve sram leakage current
The present disclosure relates to an sram memory cell. The sram memory cell has a semiconductor substrate with an active area and a gate region positioned above the active area.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/09/15
20150194431 

Static random access memory cell and forming method thereof


A sram cell and a forming method thereof are provided. The sram cell includes: a pull-up transistor, a pull-down transistor, a pass gate transistor, a tensile stress film which covers the pull-up transistor and the pull-down transistor, and an interlayer dielectric isolating layer which covers the tensile stress film and the pass gate transistor.
Shanghai Huahong Grace Semiconductor Manufacturing Corporation


07/09/15
20150194208 

Sram wordline driver supply block with multiple modes


A wordline driver supply block supporting multiple operation modes of a memory of a microprocessor in a device for reducing power consumption thereof.. .

07/09/15
20150194205 

Dual-port sram systems


Schematic circuit designs for a dual-port sram cell are disclosed, together with various layout schemes for the dual-port sram cell. The dual-port sram cell comprises: a data latch storage unit comprising a first terminal and a second terminal; a first dummy circuit coupled to the first terminal of the data latch storage unit, the first dummy circuit comprising a first partial dummy transistor and a second partial dummy transistor, wherein the first partial dummy transistor is formed in a first active area of a substrate and the second partial dummy transistor is formed in a second active area of the substrate; and a first gate electrode extending over an edge of the first active area and over an edge of the second active area, wherein the edges of the first active area and the second active area are disposed within a width of the first gate electrode..
Taiwan Semiconductor Manufacturing Company, Ltd.


07/02/15
20150187985 

Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip


In at least one embodiment, the method is designed to produce an optoelectronic semiconductor chip. The method includes at least the following steps in the stated sequence: a) providing a growth substrate with a growth side, b) depositing at least one nucleation layer based on alxga1-xoyn1-y on the growth side, c) depositing and structuring a masking layer, d) optionally growing a gan-based seed layer in regions on the nucleation layer not covered by the masking layer, e) partially removing the nucleation layer and/or the seed layer in regions not covered by the masking layer or applying a second masking layer on the nucleation layer or on the seed layer in the regions not covered by the masking layer, and f) growing an alingan-based semiconductor layer sequence with at least one active layer..
Osram Opto Semiconductors Gmbh


07/02/15
20150187685 

Leadframe assembly, housing assembly, module assembly and determining at least one value of a measurement variable of an electronic module


A leadframe assembly is formed from an electrically conductive material. The leadframe assembly includes a first longitudinal element, at least one second longitudinal element, a plurality of first leadframe sections and a plurality of second leadframe sections..
Osram Opto Semiconductors Gmbh


07/02/15
20150184838 

Led retrofit lamp and process for manufacturing the same


Various embodiments may relate to an led retrofit lamp, including a lamp tube, an led light engine disposed in the lamp tube, and end caps arranged at two open ends of the lamp tube, the led light engine including a circuit board and at least one light source disposed on the circuit board. The led retrofit lamp further includes one pair of retaining structures fixed at two opposite ends of the circuit board, respectively, and at least one pair of elastic tension structures connected to the retaining structures.
Osram Gmbh


06/25/15
20150179673 

Semiconductor device and manufacturing method thereof


When vc inspection for a teg is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an sram is formed on an soi substrate in a chip region.
Renesas Electronics Corporation


06/25/15
20150179655 

Static random access memory (sram) cells including vertical channel transistors and methods of forming the same


A static random access memory (sram) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor sram cell, wherein each of the transistors is configured as a vertical channel transistor.. .
Samsung Electronics Co., Ltd.


06/25/15
20150179653 

Method and improving read margin for an sram bit-cell


Described is a 6t sram cell which comprises: a first n-type transistor with a gate terminal coupled to word-line, source/drain terminal coupled to a first bit-line and drain/source terminal coupled to a first node; and a second n-type transistor with a source terminal coupled to a first supply node, a drain terminal coupled to the first node, and a gate terminal for coupling to multiple terminals, wherein the gate terminal includes a capacitor to increase coupling capacitance of the second n-type transistor. Described is a method which comprises: forming a metal gate in a first direction; forming a first spacer in the first direction on one side of the metal gate, the first spacer having a first dimension; and forming a second spacer in the first direction on another side of the metal gate, the second spacer having a second dimension which is substantially different from the first dimension..

06/25/15
20150179232 

System and performing sram access assists using vss boost


A method and a system are provided for performing memory access assist using voltage boost. A memory access request is received at a storage cell array that comprises two or more subarrays, each subarray including at least one row of storage cells.
Nvidia Corporation


06/25/15
20150177992 

Electronic device


An sram writing section sets an updating request flag in a non-delay updating request flag region corresponding to a non-delay region where the restoration data is written. When the updating request flag is set in the non-delay updating request flag region, an eeprom writing section writes the restoration data stored in the non-delay region corresponding to the non-delay updating request flag region into an eeprom..

06/18/15
20150172706 

Image processor


The codec processor includes an sram that holds a reference image read from an image storage, and a motion search unit that performs motion search on the basis of a reference image held in the sram to generate a prediction block for a target block in an input image. The sram holds a reference image having a horizontally equivalent number of pixels to a horizontal number of pixels of the input image and a number of pixels vertically larger than or equal to a vertical motion search range..
Megachips Corporation


06/18/15
20150171378 

Method for producing an optoelectronic component and patterning an organic, optoelectronic component


Various embodiments may relate to a method for producing an organic optoelectronic component, including forming a first layer on or over a substrate, the substrate including at least one contact pad of the organic optoelectronic component, at least one electrode of the organic optoelectronic component being electrically connected to the at least one contact pad, forming a second layer on or over the first layer, and removing at least the second layer in at least one region of the substrate with the first layer and the contact pad. The adhesion of the substance or of the substance mixture of the first layer on the interface with the substrate is less than the adhesion of the substance or of the substance mixture of the second layer on the interface with the substrate..
Osram Oled Gmbh


06/18/15
20150171375 

Optoelectronic component


An optoelectronic component may include an electrically active region and a light-refracting structure which includes at least one graphene layer, in which at least one lens-like structure is formed. The electrically active region may include a first electrode, a second electrode, and an organic functional layer structure between the first electrode and the second electrode..
Osram Opto Semiconductors Gmbh


06/18/15
20150171093 

Structure and a sram circuit


The present disclosure provides an integrated circuit formed in a semiconductor substrate. The integrated circuit includes a first static random access memory (sram) cell having a first cell size; and a second sram cell having a second cell size greater than the first cell size.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/18/15
20150170736 

Process tolerant current leakage reduction in static random access memory (sram)


A memory device biasing circuit is disclosed, the circuit having a pair of semiconductor devices coupled to receive a supply voltage having a supply voltage level suitable for operating a memory device in an active mode and operable for providing an adjustable biased voltage to the memory device that is greater than a minimal voltage level for operating the memory device in a data retention mode. The pair of semiconductor devices includes a first semiconductor device; and, a second semiconductor device that includes an opposite type of semiconductor device than the first semiconductor device such that the pair of semiconductor devices includes each of an n-type semiconductor device and a p-type semiconductor device.
Qualcomm Incorporated


06/18/15
20150170735 

Dual port sram bitcell structures with improved transistor arrangement


Dual port static random access memory (sram) bitcell structures with improve symmetry in access transistors physical placement are provided. The bitcell structures may include, for example, two pairs of parallel pull-down transistors.
Globalfoundries Inc.


06/18/15
20150170734 

Multi-port sram with shared write bit-line architecture and selective read path for low power operation


A multi-port sram with shared write bit-line architecture and selective read path for low power operation includes a first memory cell, a second memory cell, and a common switch set. The second memory cell makes use of the common switch set to share the a-port write bit-line and the b-port write bit-line with the first memory cell so as to reduce half write bit-line number and reduce the write current consumption caused by pre-charging the bit-line to vdd.
National Chiao Tung University


06/18/15
20150167938 

Method for producing an illuminant


A method for producing an illuminant is specified, in which a positioning device (3) holds an optoelectronic semiconductor component (1) inside a tolerance range (4) on the upper side of a connection carrier (2) during the mechanical fixation and electrical connecting of the optoelectronic semiconductor component (1) to the connection carrier (2).. .
Osram Opto Semiconductors Gmbh


06/18/15
20150167925 

Lens, omnidirectional illumination device and retrofit lamp including the lens


Various embodiments relate to a lens for omnidirectional illumination which is rotationally symmetrical and includes a light incident surface, a first light refractive surface, a first light reflective surface, and a second light refractive surface designed to be rotationally symmetrical, respectively. The second light refractive surface is defined by a bezier curve in a cross section, a first portion of light through the light incident surface is refracted by the first light refractive surface, a second portion of the light through the light incident surface is reflected by the first light reflective surface to the second light refractive surface, and then is refracted by the second light refractive surface, a third portion of the light through the light incident surface is refracted by the second light refractive surface, to produce first, second and third emergent lights, respectively.
Osram Gmbh


06/18/15
20150167907 

Illumination device comprising a phosphor arrangement and a laser


A lighting device comprising a phosphor arrangement (2) having a phosphor region; (31-33), a first laser (5) for irradiating a part of the phosphor region (31-33) with a first laser radiation; wherein the phosphor region (31-33) comprises at least one phosphor which can be irradiated by the first laser radiation and re-emits said first laser radiation at least partly in a manner wavelength-converted into colored light having a first light color; a second laser (6) configured for emitting a second laser radiation having a second light color, wherein the second light color of the second laser radiation is identical in color to the first light color of the wavelength-converted colored light; and wherein the lighting device is configured to simultaneously emit the second laser radiation and the wavelength-converted colored light of identical color emitted by the phosphor.. .
Osram Gmbh


06/18/15
20150167905 

Lighting device


A lighting device may include a plurality of laser light sources, and an optical apparatus for concentrating the light emitted by the laser light sources. The optical apparatus has at least one ring-shaped reflector having a parabolic light reflection surface and at least one light conversion element for light wavelength conversion, which is arranged at the focus of the at least one ring-shaped reflector..
Osram Gmbh


06/11/15
20150162075 

List sort static random access memory


A list sort static random access memory (lssram) unit cell includes a static random access memory (sram) cell having a pair of cross-coupled elements to store data and a dynamic/static (d/s) mode selector to selectably switch the lssram unit cell between a dynamic storage mode and a static storage mode. The lssram unit cell further includes a swap selector to swap the stored data with data stored in an adjacent memory cell during the dynamic storage mode when the swap selector is activated, and a data comparator to compare the stored data in the sram cell with the data stored in the adjacent memory cell and to activate the swap selector according to a result of the comparison..

06/11/15
20150162052 

Three-dimensional static random access memory device structures


Systems and methods are provided for fabricating a static random access memory (sram) cell in a multi-layer semiconductor device structure. An example sram device includes a first array of sram cells, a second array of sram cells, a processing component, and one or more inter-layer connection structures.
Taiwan Semiconductor Manufacturing Company Limited


06/04/15
20150156517 

Image encoding system and method thereof


An image encoding system is disclosed. The image encoding system comprises a wavelet transform unit and a processing circuit.
Aspeed Technology Inc.


06/04/15
20150155286 

Structure and statice random access memory device of vertical tunneling field effect transistor


Forming an sram cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters, the pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (tfet) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


06/04/15
20150155056 

Circuit and controlling internal test mode entry of an asram chip


The present application provides a circuit and method for controlling internal test mode entry of an asram chip. The circuit comprises an address code comparator for detecting whether address codes on an address bus of the asram chip match a predefined validation code; a test mode detector for determining whether to let the asram chip enter into an internal test mode; a test mode clock generator for generating a clock signal for the test mode decoder; and a test mode decoder for generating a test control signal.
Integrated Silicon Solution (shanghai), Inc.


06/04/15
20150155021 

Area-efficient process-and-temperature-adaptive self-time scheme for performance and power improvement


In certain embodiments, a method and apparatus for adjusting the timing of a sense-amplifier read operation in an sram integrated memory circuit to overcome process-and-temperature variations are disclosed. A charge-injection pull-up transistor is provided to adjust the rate at which a signal line (e.g., a tracking bit line (tbl) and/or a clock signal (e.g., gclkb)) transitions from one voltage level to another voltage level.
Lsi Corporation


06/04/15
20150154066 

Error correction in solid state drives (ssd)


A paging scheme for a solid state drive (ssd) error correction mechanism that exchanges portions of a parity component, such as a page, between sram and less expensive dram, which stores the remainder of a context of pages. A parity operation applies an xor function to corresponding memory positions in the pages of the context.

05/28/15
20150147857 

Memory cell


Memory cells are described with cross-coupled inverters including unidirectional gate conductors. Gate conductors for access transistors may also be aligned with a long axis of the inverter gate conductor.
University Of Virginia Patent Foundation


05/28/15
20150146480 

Novel 3d structure for advanced sram design to avoid half-selected issue


Systems are provided for a three dimension static random access memory (sram) structure. The sram structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/28/15
20150146479 

Sram write-assisted operation with vdd-to-vcs level shifting


An electronic circuit and a method for driving data writes to an sram bit cell in an electronic circuit. The electronic circuit translates a first write signal in a lower voltage domain to a second write signal in a higher voltage domain.
International Business Machines Corporation


05/28/15
20150146478 

Sram bit-line and write assist lowering dynamic power and peak current, and a dual input level-shifter


Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch.

05/28/15
20150146476 

Passive sram write assist


Passive write assist passively improves sram performance (e.g., write margin speed) while reducing manufacturing costs (e.g., die area, packaging) and operating costs (e.g., power consumption, cooling) associated with active write assist schemes. Passive write assist may be implemented in peripheral circuitry or embedded in an sram array or even in each array cell or bitcell.
Broadcom Corporation


05/21/15
20150138897 

Stack position determination in memory devices configured for stacked arrangements


Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
Iii Holdings 2, Llc


05/21/15
20150138876 

Global bitline write assist for sram architectures


An sram device includes a segmented memory cell array with a plurality of memory cells. Each segment of memory cells includes a bitline coupled to the memory cells in the segment.
Lsi Corporation


05/21/15
20150138863 

Interleaved write assist for hierarchical bitline sram architectures


An sram device includes a plurality of memory cells and a first metallization layer comprising a first pair of bitlines operable to couple to a first segment of the memory cells. The device also includes a second metallization layer comprising a second pair of bitlines operable to couple to a second segment of the memory cells and a write assist line interleaved with the first and second metallization layers to provide a substantially constant coupling capacitance with each of the first and second pairs of bitlines..
Lsi Corporation


05/14/15
20150132903 

Structure and sram cell circuit


The present disclosure provides a static random access memory (sram) cell. The sram cell includes a first and a second pull-up devices; a first and a second pull-down devices configured with the first and second pull-up devices to form two cross-coupled inverters for data storage; and a first and second pass-gate devices configured with the two cross-coupled inverters to form a port for data access, wherein the first and second pull-down devices each includes a first channel doping feature of a first doping concentration, and the first and second pass-gate devices each includes a second channel doping feature of a second doping concentration greater than the first doping concentration..

05/14/15
20150131368 

Implementing sense amplifier for sensing local write driver with bootstrap write assist for sram arrays


A method and circuit for implementing sense amplifiers for sensing local write driver with bootstrap write assist for static random access memory (sram) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a sense amplifier used in both read and write operations with a write assist boost circuitry.

05/14/15
20150131366 

Voltage controller


A voltage controller is provided that is connected to a voltage inducing circuit which is connected to a static random-access memory (sram) cell. The voltage controller comprises a voltage clamping circuit and a pull up circuit.

05/14/15
20150131365 

Spsram wrapper


Among other things, one or more techniques or systems for facilitating access operations to a single port memory device are provided. Multiple access operations to a single port memory device, such as a 6 transistor bitcell array of an spsram, are performed during a single clock period of a system clock.

05/14/15
20150131364 

Negative bitline boost scheme for sram write-assist


A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element.

05/07/15
20150127900 

Ternary content addressable memory utilizing common masks and hash lookups


A ternary content-addressable memory (tcam) that is implemented based on other types of memory (e.g., sram) in conjunction with processing, including hashing functions. Such a h-tcam may be used, for example, in implementation of routing equipment.
Cisco Technology, Inc.


04/30/15
20150117093 

Method for driving semiconductor device


A semiconductor device includes sram that stores data in an inverter loop including a cmos inverter, transistors electrically connected to an input terminal or an output terminal of the cmos inverter, and capacitors electrically connected to the corresponding transistors. The semiconductor device is configured to hold potentials corresponding to data at nodes between the transistors and the corresponding capacitors in a period during which supply of power to the cmos inverter stops.
Semiconductor Energy Laboratory Co., Ltd.


04/30/15
20150117092 

Multi-channel physical interfaces and methods for static random access memory devices


An integrated circuit (ic) device can include a static random access memory (sram) section comprising a plurality of memory banks; and an interface comprising physical connections for more than eight memory channels, the connections for each memory channel including an address section including connections for sram control inputs and a complete address to access the memory banks, and a data section including data inputs and outputs (data ios) to transfer data for one memory bank.. .
Cypress Semiconductor Corporation


04/23/15
20150113492 

Sram layouts


Roughly described, the cell layout in an sram array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area.
Synopsys, Inc.


04/23/15
20150109870 

Arithmetic processing unit and driving method thereof


An arithmetic processing unit including an sram with low power consumption and performing backup and recovery operation with no burden on circuits. One embodiment is a memory device including a plurality of memory cells.
Semiconductor Energy Laboratory Co., Ltd.


04/23/15
20150109852 

Data-controlled auxiliary branches for sram cell


A circuit includes a first inverter, a second inverter, a first auxiliary branch and a second auxiliary branch. The first and second inverters are cross-coupled to form a first storage node and a second storage node.
Taiwan Semiconductor Manufacturing Company, Ltd.


04/23/15
20150109845 

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements


Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, rerams, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
Iii Holdings 2., Llc


04/16/15
20150103585 

High stability static random access memory cell


A static random access memory (sram) cell is a latch circuit formed with two inverters each formed with a pmos transistor and an nmos transistor. The latch circuit is coupled to a capacitor through a switch.
United Microelectronics Corp.


04/16/15
20150102423 

Method for finfet sram ratio tuning


A semiconductor device and method of forming the same include a substrate having a plurality of memory cells formed thereon. A memory cell includes pass-gate transistors, pull-up transistors, and pull-down transistors.
Semiconductor Manufacturing International (shanghai) Corporation


04/16/15
20150102421 

Semiconductor device


A semiconductor device having an sram which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions..
Renesas Electronics Corporation


04/16/15
20150102417 

Double trench well formation in sram cells


A method is provided for forming sram cells with low energy implants. Embodiments include forming deep trenches in a silicon substrate; forming a deep n-well or deep p-well around a bottom of each deep trench; filling the deep trenches with oxide; forming a first or second shallow trench between each pair of adjacent deep trenches; forming a first p-well or first n-well, respectively, above each deep n-well or p-well; forming a second n-well at a bottom of each first shallow trench; forming a p+ region above each second n-well on each side of each first shallow trench; filling the first shallow trenches with oxide; forming a second p-well at a bottom of each second shallow trench; filling the second shallow trenches with oxide; forming a p+ region above each second n-well on each side of each first shallow trench; and forming an n+ region above each second p-well..
Globalfoundries Inc.


04/09/15
20150098268 

Semiconductor memory


The disclosed invention provides an sram capable of stably generating a puf-id without having to be powered on/off under control. The sram including a plurality of write ports is provided with a plurality of word lines, each transferring write data from each of the write ports to one memory cell.
Renesas Electronics Corporation


04/02/15
20150092477 

Adaptive data-retention-voltage regulating system for sram


An adaptive data-retention-voltage regulating system for static random-access memory (srams) is revealed. The system includes a power supply unit, a data-retention-voltage (drv) monitor cell for monitoring static noise margin (snm) of sram, a data loss detector for generating a data loss signal, and a dynamic regulating controller that receives the data loss signal for generating a refresh signal and a switch signal.
National Cheng Kung University


04/02/15
20150092476 

Dual port sram with dummy read recovery


An integrated includes a dual port memory cell such as a sram cell. A first port dummy read recovery block couples the first port complementary bit line to a high voltage supply node during a write logic low operation to the data node through the second port bit line, and couples the first port bit line to a high voltage supply node during a write logic low operation to the complementary data node through the second port complementary bit line.
Taiwan Semiconductor Manufacturing Co., Ltd.


04/02/15
20150091928 

Image processing device and method thereof


An image processing device that converts original image data to target image data is provided. The image processing device includes: a static random access memory (sram); an image scaling circuit that generates scaled image data according to the original image data and stores the scaled image data to the sram; and a video encoding circuit that accesses the scaled image data from the sram and encodes the accessed scaled image data to generate the target image data.
Mstar Semiconductor, Inc.


04/02/15
20150091097 

Hardmask for a halo/extension implant of a static random access memory (sram) layout


Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (sram) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (pd) transistor over a substrate; forming a pass-gate (pg) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the pd transistor and a second section adjacent the pg transistor, wherein a distance between the first section and the pd transistor is shorter than a distance between the second section and the pg transistor.
Globalfoundries Inc.


03/26/15
20150085566 

Input trigger independent low leakage memory circuit


Wordline-driver biasing and column-based source-biasing circuitry facilitate reduced current leakage, for example, in soc device sram circuits in a manner that is independent of the read/write/standby operating mode, and without an external trigger. Wordline-driver-biasing circuitry turns off (i.e., decouples from system power) wordline-drivers that are connected to unselected wordlines during read/write operations using one of a decoder-enable signal, which is generated in response to row address values, or based on the activation of a self-timing internal clock, which is generated by the memory circuit when it is activated (i.e., switched from standby to read/write mode).
Synopsys, Inc.


03/19/15
20150078068 

Integrated circuits with sram cells having additional read stacks


Integrated circuits that include sram cells having additional read stacks are provided. In accordance with one embodiment an integrated circuit includes a memory storage array of memory cells.
Globalfoundries Inc.


03/19/15
20150078067 

Method of measuring threshold voltage of mos transistor in sram array


Methods of measuring threshold voltages of mos transistors in a sram array are provided. The sram array includes array-arranged cells having a first pass nmos transistor, a second pass nmos transistor, a first pull-down nmos transistor, a second pull-down nmos transistor, a first pull-up pmos transistor, and a second pull-up transistor.
Semiconductor Manufacturing International (beijing) Corporation


03/12/15
20150074344 

Adaptive memory system for enhancing the performance of an external computing device


An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., static random access memory or sram), a second memory type (e.g., dynamic random access memory or dram), a third memory type (e.g., flash), an internal bus system, and an external bus interface.
Mobile Semiconductor Corporation


03/12/15
20150070977 

Semiconductor device


A well voltage supply cell includes third gate electrode group (including a third gate electrode corresponding to a first gate electrode) located symmetrically to first gate electrode group (including the first gate electrode constituting an access transistor) of a first sram cell, fourth gate electrode group (including a fourth gate electrode corresponding to a second gate electrode) located symmetrically to second gate electrode group (including the second gate electrode constituting an access transistor) of a second sram cell. A p-type impurity diffusion region located on a p well between the third gate electrode and the fourth gate electrode located opposite to each other, a first n-type impurity diffusion region located on the side of the third gate electrode closer to the first sram cell, and a second n-type impurity diffusion region located on the side of the fourth gate electrode closer to the second sram cell..
Renesas Electronics Corporation


03/12/15
20150070976 

Semiconductor device


There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an sram memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation.
Renesas Electronics Corporation


03/05/15
20150064853 

Integrated circuit including dram and sram/logic


An integrated circuit comprising an n+ type layer, a buffer layer arranged on the n+ type layer; a p type region formed on with the buffer layer; an insulator layer overlying the n+ type layer, a silicon layer overlying the insulator layer, an embedded ram fet formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the n+ type layer, the n+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the n+ type layer, a first logic ram fet formed in the silicon layer above the p type region, the p type region functional as a p-type back gate of the first logic ram fet, and a second contact through the silicon layer and the insulating layer and electrically connecting to the p type region.. .
International Business Machines Corporation


03/05/15
20150063010 

Negative bias thermal instability stress testing for static random access memory (sram)


In one embodiment, one portion of an sram array is stressed by first writing a “1” in every bit of the array, followed by an evaluation of the relevant parameters of the array using a ring oscillator driven by a mirrored bit-line current, the ring oscillator not in line of the bit-line of the sram. The other portion of the array is then stressed after writing a “0” in every bit of the array.
Synopsys, Inc.


03/05/15
20150063009 

Dynamic static random access memory (sram) array characterization


A sensor circuit is used to provide bit-cell read strength distribution of an sram array. A current-mirror circuit mirroring the bit-line current of an sram array is used to power the sensor circuit.
Synopsys, Inc.


03/05/15
20150063007 

Static random access memory device including dual power line and bit line precharge method thereof


A static random access memory (sram) device is provided. A memory cell is supplied with a first driving voltage.

02/26/15
20150058928 

Applying circuit delay-based physically unclonable functions (pufs) for masking operation of memory-based pufs to resist invasive and clone attacks


One feature pertains to generating a unique identifier for an electronic device by combining static random access memory (sram) pufs and circuit delay based pufs (e.g., ring oscillator (ro) pufs, arbiter pufs, etc.). The circuit delay based pufs may be used to conceal either a challenge to, and/or response from, the sram pufs, thereby inhibiting an attacker from being able to clone a memory device's response..
Qualcomm Incorporated


02/26/15
20150056792 

Finfet and fabrication


An improved finfet and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon.
Intemational Business Machines Corporation


02/26/15
20150055667 

Laser component and producing it


A laser component includes a housing in which a first carrier block is arranged. A first laser chip having an emission direction is arranged on a longitudinal side of the first carrier block.
Osram Gmbh


02/26/15
20150055402 

Novel 3d structure for advanced sram design to avoid half-selected issue


Disclosed is a novel static random access memory (sram) device. The sram device comprises a plurality of memory array layers vertically disposed one above another, a layer decoder circuit disposed on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs wherein each complementary bit line pair extends vertically to couple a memory cell in each memory array layer.
Taiwan Semiconductor Manufacturing Company Limited


02/26/15
20150055338 

Led lighting device with mint-colored and amber-colored light-emitting diodes


Various embodiments may relate to an led lighting device, including at least one mint-colored light-emitting diode, at least one amber-colored light-emitting diode and at least one yellow light-emitting diode and/or blue light-emitting diode.. .
Osram Gmbh


02/26/15
20150055319 

Wavelength conversion structure for a light source


A wavelength conversion structure for a light source including a solid-state light-emitting device. The wavelength conversion structure includes one or more apertures formed therein.
Osram Sylvania Inc.


02/26/15
20150053951 

Organic light-emitting device and producing an organic light-emitting device


The invention relates to an organic light-emitting part having a functional layer stack (10), which functional layer stack has a substrate (1), a first electrode (2) above the substrate, an organic functional layer stack (4) above the first electrode, having an organic light-emitting layer (5), and a second electrode (3) above the organic functional layer stack, wherein a layer (1, 2, 3) of the functional layer stack (10) forms a carrier layer (6) for a diffusion layer (7), wherein the diffusion layer (7) has at least one first and one second organic component (71, 72) having indices of refraction that differ from each other, wherein the first organic component (71) is hydrophobic and the second organic component (72) is hydrophilic, wherein the glass transition temperature of a mixture of the first organic component (71) and the second organic component (72); lies above the room temperature and wherein the first organic component (71) and the second organic component (72) are partially segregated in the diffusion layer (7) and the diffusion layer (7) has a mesoscopic boundary layer (75) between the first and second organic components (71, 72) or the diffusion layer (7) is present as a mesophase (78) having the first and second organic component (71, 72). The invention further relates to a method for producing an organic light-emitting part..
Osram Opto Semiconductors Gmbh


02/26/15
20150053919 

Optoelectronic semiconductor chip and producing an optoelectronic semiconductor chip


An optoelectronic semiconductor chip having a semiconductor layer sequence includes at least one active layer that generates primary radiation; a plurality of conversion layers that at least partially absorb the primary radiation and convert the primary radiation into secondary radiation of a longer wavelength than the primary radiation; and a roughened portion that extends at least into one of the conversion layers, wherein the roughened portion has a random structure, the semiconductor layer sequence is arranged on a carrier, a top side of the semiconductor layer sequence facing away from the carrier is formed by the roughened portion, the at least one active layer is located between the carrier and the conversion layers, and the roughened portion includes a plurality of recesses free of a semiconductor material.. .
Osram Opto Semiconductors Gmbh


02/19/15
20150049541 

Semiconductor memory device


When threshold voltages of constituent transistors are reduced in order to operate an sram circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the sram circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of mos transistors in sram memory cells mc by controlling a potential of a source line ssl of the driver mos transistors in the memory cells..
Renesas Electronics Corporation


02/12/15
20150046692 

System on chip for reducing wake-up time, operating same, and computer system including same


A system on chip (soc) includes an internal read-only memory (rom) configured to store a first boot loader; a first internal static random access memory (sram) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal sram configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (dram) controller configured to load an operating system (os) from the booting device into a dram according to control of the second boot loader.. .

02/05/15
20150036418 

Circuits for voltage or current biasing static random access memory (sram) bitcells during sram reset operations, and related systems and methods


Circuits for voltage or current biasing static random access memory (sram) bitcells during sram reset operations are disclosed. Related systems and methods are also disclosed.
Qualcomm Incorporated


02/05/15
20150036417 

Sram read buffer with reduced sensing delay and improved sensing margin


A device includes a static random access memory (sram) cell and a read buffer coupled to an output of the sram cell. The read buffer includes an inverter and a switch.
Industry-academic Cooperation Foundation, Yonsei University


01/29/15
20150029785 

Methods for operating a finfet sram array


A method of operating an sram array may include: providing a plurality of bit cells, each of the plurality of bit cells comprising a cross coupled inverter pair; a first pass gate; and a second pass gate. A word line voltage may be applied to the first pass gate and the second pass gate, while a first cell positive voltage supply cvdd may be applied to terminals of the cross coupled inverter pair.
Taiwan Semiconductor Manufacturing Company, Ltd.


01/29/15
20150029784 

Semiconductor integrated circuit device


There is provided a semiconductor integrated circuit device that can generate a unique id with the suppression of overhead. When a unique id is generated, the potential of a word line of a memory cell in an sram is raised above the power supply voltage of the sram, and then lowered below the power supply voltage of the sram.
Renesas Electronics Corporation


01/29/15
20150029783 

Method of detecting transistors mismatch in a sram cell


The present invention provides a method of detecting the transistor mismatch in a sram cell. The sram cell comprises two pass-gate transistors and a bi-stable circuit including two pull up transistors and two pull down transistors.
Shanghai Huali Microelectronics Corporation




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Sram topics: Random Access, Static Random Access Memory, Memory Cell, Semiconductor, Memory Cells, Transistors, Semiconductor Memory, Memory Device, Integrated Circuit, Robustness, Field Effect Transistor, Clamping Circuit, Internal Node, Implantation, Data Storage

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