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Sram

Sram-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Structure and method for sram finfet device
Taiwan Semiconductor Manufacturing Company, Ltd.
December 31, 2015 - N°20150380410

The present disclosure provides an embodiment of a fin-like field-effect transistor (finfet) device. The device includes a first fin structure disposed over an n-type finfet (nfet) region of a substrate. The first fin structure includes a silicon (si) layer, a silicon germanium oxide (sigeo) layer disposed over the silicon layer and a germanium (ge) feature disposed over the sigeo layer. ...
Boosted read write word line
Taiwan Semiconductor Manufacturing Company Limited
December 31, 2015 - N°20150380082

One or more techniques or systems for boosting a read word line (rwl) or a write word line (wwl) of a two port synchronous random access memory (sram) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a rwl, a wwl, or a read ...
Dual write wordline memory cell
Industry-academic Cooperation Foundation, Yonsei University
December 31, 2015 - N°20150380080

A static random-access memory (sram) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the ...
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Memory chip and layout design for manufacturing same
Taiwan Semiconductor Manufacturing Company, Ltd.
December 31, 2015 - N°20150380078

A static random access memory (sram) chip including a plurality of sram cells and a plurality of cell current tracking cells. Each of the sram cells include a source voltage reference conductor, a first ground reference conductor, two cross-coupled inverters, and two pass-gate devices. Each cell current tracking cell include a first half-cell and a second half-cell. The first half-cell ...
Static random access memory and method of controlling the same
Taiwan Semiconductor Manufacturing Company, Ltd.
December 31, 2015 - N°20150380077

A static random access memory (sram) including at least a memory cell array, a first data line connected to the memory cell array, and a read assist unit connected to the first data line. The read assist unit is configured to suppress a voltage level of the first data line during a read operation of the memory cell array.
Semiconductor integrated circuit device
Renesas Electronics Corporation
December 31, 2015 - N°20150380076

The invention provides a semiconductor integrated circuit device provided with an sram that satisfies the requirements for both the snm and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply ...
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Sram cells
Surecore Limited
December 24, 2015 - N°20150371708

There is provided a memory unit that comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to a first local bit line and a second local bit line by respective first and second access transistors, and each memory cell being associated with a word line configured to ...
Static random access memory and method of using the same
Taiwan Semiconductor Manufacturing Company, Ltd.
December 24, 2015 - N°20150371702

A static random access memory (sram) including a bit cell, wherein the bit cell includes at least two p-type pass gates. The sram further includes a bit line connected to the bit cell, and a bit line bar connected to the bit cell. The sram further includes a pre-discharge circuit connected to the bit line and to the bit line ...
Memory chip and layout design for manufacturing same
Taiwan Semiconductor Manufacturing Company, Ltd.
December 24, 2015 - N°20150371701

An embedded synchronous random access memory (sram) chip, includes a first single-port (sp) sram macro and a second sp macro. The first macro includes a first periphery circuit, and a plurality of first sram cells. The second macro includes a second periphery circuit, and a plurality of second sram cells. Further, each cell of the plurality of first sram cells ...
Method and apparatus for bit-line sensing gates on an sram cell
Globalfoundries Inc.
December 17, 2015 - N°20150364183

A circuit for providing additional current in a memory cell without a higher supply voltage is provided. Embodiments include a circuit having a six transistor static random access memory (sram) cell including a first inverter and second cross-coupled to a second inverter; a first transistor having a first source coupled to a first bit-line, a first drain coupled to the ...
Sidecar sram for high granularity in floor plan aspect ratio
Advanced Micro Devices, Inc.
December 17, 2015 - N°20150364168

A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes m bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (m−a) bits of ...
Method and apparatus for fabricating a memory device with a dielectric etch stop layer
Micron Technology, Inc.
December 10, 2015 - N°20150357233

The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as dram or sram, various layers are deposited to form structures, such as pmos gates, nmos gates, memory cells, p+ active areas, and n+ active areas. These structures ...
Methods and apparatus for designing and constructing dual write memory circuits with voltage assist
Cisco Technology, Inc.
December 10, 2015 - N°20150357030

Static random access memory (sram) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6t) sram bit cell is proposed. The dual-port 6t sram cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of ...
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Systems and methods involving multi-bank memory circuitry
Gsi Technology, Inc.
December 10, 2015 - N°20150357027

Multi-bank sram devices, systems, methods of operating multi-bank srams, and/or methods of fabricating multi-bank sram systems are disclosed. For example, illustrative multi-bank srams and methods may include or involve features for capturing read and write addresses at a particular frequency, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each sram bank, ...
High-density latch arrays
Nvidia Corporation
December 10, 2015 - N°20150357009

A system and device are provided for implementing memory arrays using high-density latch cells. The device includes an array of cells arranged into columns and rows. Each cell comprises a latch cell that includes a transmission gate, a pair of inverters, and an output buffer. Each row of latch cells is connected to at least one common node for addressing ...
Array power supply-based screening of static random access memory cells for bias temperature instability
Texas Instruments Incorporated
December 03, 2015 - N°20150348615

A method of screening complementary metal-oxide-semiconductor cmos integrated circuits, such as integrated circuits including cmos static random access memory (sram) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of sram cells formed of cross-coupled cmos inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power ...
Static random access memory and method of controlling the same
Taiwan Semiconductor Manufacturing Company, Ltd.
December 03, 2015 - N°20150348598

A static random access memory (sram) that includes a memory cell comprising at least two p-type pass gates. The sram also includes a first data line connected to the memory cell, a second data line connected to the memory cell and a voltage control unit connected to the first data line, wherein the voltage control unit is configured to control ...
Apparatus and method for preventing error in physically unclonable function
Electronics And Telecommunications Research Institute
December 03, 2015 - N°20150347216

An apparatus and method that prevent a bit error in a static random access memory (sram)-based physically unclonable function (puf). The method for preventing an error in a puf includes selecting any value, from a physically unclonable function based on a volatile memory device, as an input value, and checking a response corresponding to the selected input value, classifying ...
Structure and method for effective device width adjustment in finfet devices using gate workfunction shift
International Business Machines Corporation
November 26, 2015 - N°20150340294

Embodiments of the present invention provide methods and structures by which the inherent discretization of effective width can be relaxed through introduction of a fractional effective device width, thereby allowing greater flexibility for design applications, such as sram design optimization. A portion of some fins are clad with a capping layer or workfunction material to change the threshold voltage (vt) ...
Non-volatile sram with multiple storage states
Empire Technology Development Llc
November 26, 2015 - N°20150340090

Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. In some examples, the multi-storage state non-volatile random access memory device has two or more memory cells. Each memory cell may include a pair of programmable resistive devices that may be dynamically programmed to configure the memory cell in a particular logic state.
Array power supply-based screening of static random access memory cells for bias temperature instability
Texas Instruments Incorporated
November 26, 2015 - N°20150340084

A method of screening complementary metal-oxide-semiconductor cmos integrated circuits, such as integrated circuits including cmos static random access memory (sram) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of sram cells formed of cross-coupled cmos inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power ...
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