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Sram

Sram-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Semiconductor device
Renesas Electronics Corporation
November 09, 2017 - N°20170323890

A semiconductor device aims to prevent a leak current from flowing between a well and a corner of an active region formed on an upper surface of another well in an sram. In a memory cell of the sram, a load mosfet is formed. An end of an active region extending in y-direction is arranged to gradually go away from ...
Static random-access memory (sram) cell array
Renesas Electronics Corporation
November 02, 2017 - N°20170317091

A static random-access memory (sram) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each pg (pass-gate) finfet shares at least one of the active fins with a pd (pull-down) finfet, and at least one ...
Method of forming static random-access memory (sram) cell array
Renesas Electronics Corporation
November 02, 2017 - N°20170317090

A static random-access memory (sram) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each pg (pass-gate) finfet shares at least one of the active fins with a pd (pull-down) finfet, and at least one ...
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Semiconductor integrated circuit device
Renesas Electronics Corporation
November 02, 2017 - N°20170317065

The present disclosure allows for reducing parasitic capacitance of a bit line, and a drop in access performance in an sram cell including fin-type transistors. The sram cell is defined by transistors each of which has a fin structure and by a local metal interconnection layer. Bit lines are formed on the local metal interconnection layer, and diffusion layer contacts ...
Pillar-shaped semiconductor memory device and method for producing the same
Unisantis Electronics Singapore Pte. Ltd.
October 26, 2017 - N°20170309632

An sram includes three si pillars. In upper parts of the si pillars, a first load p-channel, a first driver n-channel, and a first selection n-channel are formed, and in lower parts of the si pillars, a second load p-channel, a second driver n-channel, and a second selection n-channel are formed. At the same height in the si pillars, a ...
Semiconductor integrated circuit device and system
Renesas Electronics Corporation
October 26, 2017 - N°20170309327

A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural sram modules. The plural sram modules perform power control independently of the logic circuit, and an independent power control is performed among the plural sram modules. Specifically, ...
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Phosphor, method for producing a phosphor and use of a phosphor
Osram Gmbh
October 26, 2017 - N°20170306224

A phosphor and a lighting device are disclosed. In an embodiment a lighting device includes a first phosphor disposed in a beam path of the primary radiation source, wherein the first phosphor has the formula sr(sram1−a)si2al2(n,x)6:d,a,b,e,g,l, wherein element m is selected from ca, ba, mg or combinations ...
Semiconductor integrated circuit device
Osram Gmbh
October 19, 2017 - N°20170301678

In an image information chip or the like, a multi-port sram is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded sram can be reduced, the number of write ...
Semiconductor device
Osram Gmbh
October 19, 2017 - N°20170301664

Based on a basic idea to effectively utilize a space created in a third wiring layer (m3) by a zero-th wiring layer (m0) which can exist by miniaturization of a finfet, an auxiliary line al is arranged in the space created in the third wiring layer, and this auxiliary line al and a word line wl are electrically connected to ...
Temperature compensated read assist circuit for a static random access memory (sram)
Osram Gmbh
October 19, 2017 - N°20170301396

A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit including a p-channel pull-up transistor. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node and an n-channel diode-connected transistor having a source-drain path connected between a ...
Integrated circuit devices and methods
Osram Gmbh
October 19, 2017 - N°20170301395

An integrated circuit can include multiple sram cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the ...
Sram structure with reduced capacitance and resistance
Osram Gmbh
October 19, 2017 - N°20170301394

A structure includes an sram cell includes a first and a second pull-up mos device, and a first and a second pull-down mos device forming cross-latched inverters with the first pull-up mos device and the second pull-up mos device. A first metal layer is over the gate electrodes of the mos devices in the sram cell. The structure further includes ...
Sram cells with vertical gate-all-round mosfets
Osram Gmbh
October 19, 2017 - N°20170301393

A static random access memory (sram) cell includes a first boundary and a second boundary opposite to, and parallel to, the first boundary, a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first ...
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Static random access memory circuits
Taiwan Semiconductor Manufacturing Company, Ltd.
October 12, 2017 - N°20170294224

A static random access memory (sram) includes a bit cell that receives an operating voltage and a reference voltage, and includes a p-type pass gate. A bit information path is connected to the bit cell by the p-type pass gate, and a pre-discharge circuit is connected to the bit information path. The pre-discharge circuit includes an n-type transistor that discharges ...
Write assist circuit for lowering a memeory supply voltage and coupling a memory bit line
Broadcom Corporation
October 12, 2017 - N°20170294223

A circuit and method performs a write assist for a memory cell (e. G., a static random access memory cell (sram)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further ...
Storage bitcell with isolation
Arm Limited
October 12, 2017 - N°20170294222

A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as static random-access memory (sram) circuitry.
Static random access memory (sram) device
Renesas Electronics Corporation
October 05, 2017 - N°20170287918

To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, ...
Semiconductor device and manufacturing method thereof
Renesas Electronics Corporation
October 05, 2017 - N°20170287795

When vc inspection for a teg is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an sram is formed on an soi substrate in a chip region. Also, in a teg ...
Semiconductor device
Renesas Electronics Corporation
October 05, 2017 - N°20170287554

There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an sram memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist ...
Method and system for predicting high-temperature operating life of sram devices
Semiconductor Manufacturing International (beijing) Corporation
October 05, 2017 - N°20170285099

A method for predicting high-temperature operating life of an integrated circuit (ic) includes performing bias temperature instability tests and high-temperature operating life tests on a device of the ic, establishing a relationship between the device bias temperature instability and the ic's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests. ...
Semiconductor storage device
Renesas Electronics Corporation
September 28, 2017 - N°20170278566

A semiconductor storage device includes an sram memory cell composed of a drive transistor, a transfer transistor and a load transistor, an i/o circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the i/o circuit between a resume standby mode and a normal ...
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