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Sram patents



      

This page is updated frequently with new Sram-related patent applications.




Date/App# patent app List of recent Sram-related patents
04/07/16
20160098321 
 Efficient memory architecture for low density parity check decoding patent thumbnailEfficient memory architecture for low density parity check decoding
A low density parity check (ldpc) decoder integrated on a single semiconductor substrate may comprise one or more arrays of first-type memory cells and one or more arrays of second-type memory cells. The ldpc decoder may be configured to store intrinsic messages in the array of first-type cells and to store extrinsic messages in the array of second-type cells.
Maxlinear, Inc.


03/31/16
20160093623 
 Two-transistor sram semiconductor structure and methods of fabrication patent thumbnailTwo-transistor sram semiconductor structure and methods of fabrication
A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


03/31/16
20160093622 
 Cross-coupled thyristor sram semiconductor structures and methods of fabrication patent thumbnailCross-coupled thyristor sram semiconductor structures and methods of fabrication
A memory cell based upon thyristors for an sram integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


03/31/16
20160093607 
 Six-transistor sram semiconductor structures and methods of fabrication patent thumbnailSix-transistor sram semiconductor structures and methods of fabrication
A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


03/31/16
20160093369 
 Write assist sram circuits and methods of operation patent thumbnailWrite assist sram circuits and methods of operation
A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


03/31/16
20160093368 
 Six-transistor sram circuits and methods of operation patent thumbnailSix-transistor sram circuits and methods of operation
A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


03/31/16
20160093367 
 Cross-coupled thyristor sram circuits and methods of operation patent thumbnailCross-coupled thyristor sram circuits and methods of operation
A memory cell based upon thyristors for an sram integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


03/31/16
20160093365 
 Seven-transistor static random-access memory bitcell with reduced read disturbance patent thumbnailSeven-transistor static random-access memory bitcell with reduced read disturbance
Systems and methods relate to a seven transistor static random-access memory (7t sram) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor.
Qualcomm Incorporated


03/31/16
20160093364 
 Selective current boosting in a static random-access memory patent thumbnailSelective current boosting in a static random-access memory
Systems and methods include a static random-access memory (sram) bit cell circuit having an access transistor configured to pass a read current to a storage node, the access transistor including an access transistor back gate. The access transistor back gate is biased to enable selective current boosting of the read current during a read operation..
Qualcomm Incorporated


03/31/16
20160093363 
 Multi-port memory circuits patent thumbnailMulti-port memory circuits
A multi-port hybrid full-swing/low-swing memory circuit in a static random access memory (sram) device comprises a first wordline driver that comprises a read wordline driver, a second wordline driver that comprises either a read wordline driver or a read/write wordline driver, a memory cell coupled to the first and second wordline drivers, a sense amplifier coupled to the memory cell, and a latch coupled to the memory cell. The memory circuit is capable of achieving high-speed low-swing or low-speed full-swing operations while avoiding the need for a large circuit area on an integrated circuit..
Qualcomm Incorporated


03/31/16
20160093362 

Two-transistor sram circuit and methods of fabrication


A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


03/31/16
20160093361 

Overvoltage protection for a fine grained negative wordline scheme


A fine grained negative wordline scheme for sram memories is disclosed. The scheme includes a circuit having a static random access memory (sram) cell including at least a wordline coupled to a plurality of nfets of a transistor array.
International Business Machines Corporation


03/31/16
20160093360 

Overvoltage protection for a fine grained negative wordline scheme


A fine grained negative wordline scheme for sram memories is disclosed. The scheme includes a circuit having a static random access memory (sram) cell including at least a wordline coupled to a plurality of nfets of a transistor array.
International Business Machines Corporation


03/31/16
20160093359 

Overvoltage protection for a fine grained negative wordline scheme


A fine grained negative wordline scheme for sram memories is disclosed. The scheme includes a circuit having a static random access memory (sram) cell including at least a wordline coupled to a plurality of nfets of a transistor array.
International Business Machines Corporation


03/24/16
20160086659 

Sram array comprising multiple cell cores


An sram array having multiple cell cores to store and retrieve data. A cell core includes a plurality of sram cells, and at least two corresponding cell cores build a cell core row.
International Business Machines Corporation


03/24/16
20160086658 

Overvoltage protection for a fine grained negative wordline scheme


A fine grained negative wordline scheme for sram memories is disclosed. The scheme includes a circuit having a static random access memory (sram) cell including at least a wordline coupled to a plurality of nfets of a transistor array.
International Business Machines Corporation


03/24/16
20160086656 

Semiconductor device having memory cell with electrostatic capacitance circuit


A capacitance coupled to a memory node and a word line of an sram cell provides an electrostatic capacitance between the memory node and the word line. The capacitance has a first electrostatic capacitance when the word line is in a nonselective state (usually a low level) and the memory node retains a high level; the capacitance has a second electrostatic capacitance which is smaller than the first electrostatic capacitance when the word line is in the nonselective state (usually the low level) and the memory node retains the low level..
Renesas Electronics Corporation


03/17/16
20160079427 

Structure and sram finfet device


The present disclosure provides an embodiment of a fin-like field-effect transistor (finfet) device. The device includes a first fin structure disposed over an n-type finfet (nfet) region of a substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


03/17/16
20160078969 

Efficient coding for memory redundancy


A system may be provided that provides redundancy for a plurality of embedded memories such as srams. The system may include one or more decoders, each capable of decoding a selection address to identify a defective one of the embedded memories..
Qualcomm Incorporated


03/17/16
20160078938 

Method and providing multi-page read and write using sram and nonvolatile memory devices


A memory device includes a static random-access memory (“sram”) circuit and a first nonvolatile memory (“nvm”) string, a second nvm string, a first and a second drain select gates (“dsgs”). The sram circuit is able to temporarily store information in response to bit line (“bl”) information which is coupled to at the input terminal of the sram circuit.
Neo Semiconductor, Inc.


03/17/16
20160078927 

Design-for-test apparatuses and techniques


Embodiments of design-for-test (dft) apparatuses and related techniques are disclosed herein. In some embodiments, a dft apparatus may include an sram cell, read/write (r/w) circuitry to provide a nominal word line (wl) voltage and a nominal bl voltage for application to the sram cell during accesses.
Intel Ip Corporation


03/17/16
20160078926 

Dual-port static random access memory (sram)


In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters.
Intel Corporation


03/17/16
20160078924 

Memory device with memory cells sram (static random access memories) and controlling the polarization of boxes of transistors of the memory cells


A memory device includes a matrix of several columns of sram memory cells each including transistors forming a memory point, a read port and a write port, and such that the transistors of the read port and/or the p-type transistors include a second well with a conductivity type opposite that of a first well of the other transistors. The memory device also includes a polarization unit for the second wells, able to select and apply polarization potentials on the second wells, including a memory circuit of the polarization states of the second wells for each column or group of columns and a selection circuit applying a polarization potential on the second wells according to one of the values received as input, as a function of the stored polarization state associated with the column or group of columns..
Commissariat A L'energie Atomique Et Aux Energies Alternatives


03/17/16
20160078922 

Sram cells with vertical gate-all-round mosfets


A static random access memory (sram) cell includes a first boundary and a second boundary opposite to, and parallel to, the first boundary, a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate over the channel as a second source/drain region.
Taiwan Semiconductor Manufacturing Company, Ltd.


03/17/16
20160077958 

Initiating operation of a timing device using a read only memory (rom) or a one time programmable non volatile memory (otp nvm)


The present invention provides a method and a programmable timing device that includes a timing device circuit for generating at least one timing signal, a static random access memory (sram) coupled to the timing device circuit, a read only memory (rom) having a first timing device configuration stored therein, a one time programmable non volatile memory (otp nvm) for storing a second timing device configuration and selection logic. The selection logic includes an output coupled to the sram, a first input coupled to the rom and a second input coupled to the otp nvm.
Integrated Device Technology, Inc.


03/10/16
20160071851 

Semiconductor device


A static random access memory (sram) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.. .
Unisantis Electronics Singapore Pte. Ltd.


03/10/16
20160071578 

Semiconductor storage device


A semiconductor storage device includes an sram memory cell composed of a drive transistor, a transfer transistor and a load transistor, an i/o circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the i/o circuit between a resume standby mode and a normal operation mode, wherein the i/o circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.. .
Renesas Electronics Corporation


03/10/16
20160071577 

Static random access memory with reduced write power


A static random access memory (sram) features reduced write cycle power consumption. The sram includes an array of static storage cells and a write controller.
Texas Instruments Incorporated


03/10/16
20160071574 

Method and circuits for low latency initialization of static random access memory


A method and various circuit embodiments for low latency initialization of an sram are disclosed. In one embodiment, an ic includes an sram coupled to at least one functional circuit block.
Apple Inc.


03/10/16
20160071573 

Semiconductor device


A logic circuit in a system lsi is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an sram circuit of the system lsi controls a substrate bias to reduce leakage current..
Renesas Electronics Corporation


03/03/16
20160065379 

Physical unclonable function using augmented memory for challenge-response hashing


A technique is presented for performing a physical unclonable function (puf) using an array of sram cells. The technique can be viewed as an attempt to read multiple cells in a column at the same time, creating contention that is resolved according to process variation.
The Regents Of The University Of Michigan


03/03/16
20160064070 

Low power sram


A static random access memory (sram) that includes an array of storage cells arranged as rows and columns and a read controller to manage reading from the storage cells. The array of storage cells includes word lines that correspond to the rows and bit lines that correspond to the columns.
Texas Instruments Incorporated


03/03/16
20160064069 

Low voltage sram


In some embodiments, an sram includes an array of storage cells arranged as rows and columns, each storage cell of the array of storage cells includes a first type of transistor and a second type of transistor. The sram also includes a memory controller configured to detect a temperature of the sram and apply a body bias to the first type of transistor in each of the storage cells and refrain from an application of a body bias to the second type of transistor in each of the storage cells..
Texas Instruments Incorporated


03/03/16
20160064068 

Silicon germanium read port for a static random access memory register file


A static random access memory (sram) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (pmos) transistor having a silicon germanium (sige) channel.
Qualcomm Incorporated


03/03/16
20160064067 

Three-port bit cell having increased width


An apparatus includes a first read port, a second read port, a write port, and at least one storage latch. A width of a bit cell that includes the first read port, the second read port, and the write port is greater than twice a contacted poly pitch (cpp) associated with the bit cell.
Qualcomm Incorporated


03/03/16
20160062887 

Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems


The msmc (multicore shared memory controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or dma, and the emif (external memory interface)in a multicore soc. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters.
Texas Instruments Incorporated


02/25/16
20160055921 

Direct memory based ring oscillator (dmro) for on-chip evaluation of sram cell delay and stability


A novel and useful direct memory based ring oscillator (dmro) circuit and related method for on-chip evaluation of sram delay and stability. The dmro circuit uses an unmodified sram cell in each delay stage of the oscillator.
International Business Machines Corporation


02/18/16
20160049410 

Sram well-tie with an uninterrupted grated first poly and first contact patterns in a bit cell array


An integrated circuit containing an sram may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in sram cells. Strap rows of the sram containing well ties and/or substrate taps which have sram cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps..
Texas Instruments Incorporated


02/18/16
20160049189 

Method of minimizing the operating voltage of an sram cell


An sram cell is formed of fdsoi-type nmos and pmos transistors. A doped well extends under the nmos and pmos transistors and is separated therefrom by an insulating layer.
Stmicroelectronics International N.v.


02/18/16
20160049188 

Semiconductor integrated circuit device


A p-type well region in which an inverter making up an sram cell is formed is subdivided into two portions, which are disposed on the opposite sides of an n-type well region nw1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows..
Renesas Electronics Corporation


02/11/16
20160043658 

Isolated transformer-less capacitive power supply


An isolated transformer-less capacitive power supply, and methods for using the same to generate power, are disclosed. The power supply includes first and second input terminals to receive an alternating current (ac) voltage.
Osram Sylvania Inc.


02/11/16
20160043530 

Semiconductor laser having improved index guiding


A semiconductor laser includes a main body, a strip having a narrower width provided on the main body, and an active zone that generates light radiation, wherein surfaces of the main body laterally with respect to the strip and side surfaces of the strip are covered with an electrically insulating protective layer, an electrically conductive layer as a contact is provided on a top side of the strip, a cavity is provided between a side surface of the strip and the protective layer at least in a delimited section.. .
Osram Opto Semiconductors Gmbh


02/11/16
20160043339 

Method for producing an electronic component and electronic component


A method for producing an electronic component with at least one first electrode zone (21) and one second electrode zone (23), which are separated from one another by an insulator (9) and each comprise at least one sublayer of a first electrically conductive material. Also disclosed is an electronic component, which may be produced using the disclosed method..
Osram Opto Semiconductors Gmbh


02/11/16
20160043291 

Light-emitting semiconductor component


An optoelectronic component includes a carrier including a mounting surface, at least one light-emitting element arranged on the mounting surface and electrically conductively connected to the carrier, at least one reinforcing body integrated in the optoelectronic component, a housing consisting of a housing encapsulation compound or a housing molding compound, wherein the light emitting component is arranged in an emitter cavity of the housing, and a reinforcing body cavity in which the reinforcing body is arranged fully or partially encapsulated or encased with a reinforcing body encapsulation compound.. .
Osram Opto Semiconductors Gmbh


02/11/16
20160043271 

Method for producing an assembly emitting electromagnetic radiation, and assembly emitting electromagnetic radiation


In various exemplary embodiments, a method is provided for producing an assembly emitting electromagnetic radiation. In this case, a component composite structure is provided which has components emitting electromagnetic radiation, which components are coupled to one another physically in the component composite structure.
Osram Opto Semiconductors Gmbh


02/11/16
20160043092 

Fin field-effect transistor static random access memory devices with p-channel metal-oxide-semiconductor pass gate transistors


A complementary metal oxide semiconductor (cmos) static random access memory (sram) cell. A cmos sram cell in accordance with an aspect of the present disclosure includes a bit line and a word line.
Qualcomm Incorporated


02/11/16
20160043091 

Semiconductor device


A semiconductor device having an sram which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions..
Renesas Electronics Corporation


02/04/16
20160035414 

Sram bit-line and write assist lowering dynamic power and peak current, and a dual input level-shifter


Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch.

02/04/16
20160035413 

Non-volatile static random access memory circuits


A non-volatile static random access memory (nvsram) circuit is provided. The nvsram circuit includes first and second switches and a latch circuit.
Winbond Electronics Corp.


02/04/16
20160035397 

Overvoltage protection for a fine grained negative wordline scheme


A fine grained negative wordline scheme for sram memories is disclosed. The scheme includes a circuit having a static random access memory (sram) cell including at least a wordline coupled to a plurality of nfets of a transistor array.
International Business Machines Corporation


01/28/16
20160027500 

Circuit for mitigating write disturbance of dual-port sram


A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port sram. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line.
Faraday Technology Corporation


01/28/16
20160027499 

Dual-port static random-access memory cell


The present disclosure provides a static random access memory (sram) cell comprising a first inverter including a first pull-up (pu) device, a first pull-down (pd) device, and a second pd device; a second inverter cross-coupled to the first inverter, the second inverter including a second pu device, a third pd device, and a fourth pd device; first and second pass gate (pg) devices coupled to the first inverter to form a first port; and third and fourth pg devices coupled to the second inverter to form a second port. The first and second pg devices, the first pd device of the first inverter, and the third pd device of the second inverter are configured on a first active region.
Taiwan Semiconductor Manufacturing Company, Ltd.


01/21/16
20160020768 

Digital circuits having improved transistors, and methods therefor


Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
Mie Fujitsu Semiconductor Limited


01/21/16
20160020214 

Sram layout for double patterning


An integrated circuit with a sar sram cell with power routed in metal-1. An integrated circuit with a sar sram cell that has power routed in metal-1 and has metal-1 and metal-2 integrated circuit and sar sram cell patterns which are dpt compatible.
Texas Instruments Incorporated


01/21/16
20160019945 

Power gate for latch-up prevention


In an embodiment of the invention, power is provided to an sram array without causing latch-up by charging the positive voltage node in the sram array and the nwell regions in the sram at approximately the same rate.. .
Texas Instruments Incorporated


01/07/16
20160005458 

Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features


A sectioned bit line of an sram memory device, an sram memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line.
Gsi Technology Inc.


12/31/15
20150380410 

Structure and sram finfet device


The present disclosure provides an embodiment of a fin-like field-effect transistor (finfet) device. The device includes a first fin structure disposed over an n-type finfet (nfet) region of a substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/31/15
20150380082 

Boosted read write word line


One or more techniques or systems for boosting a read word line (rwl) or a write word line (wwl) of a two port synchronous random access memory (sram) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a rwl, a wwl, or a read write word line (rwwl).
Taiwan Semiconductor Manufacturing Company Limited


12/31/15
20150380080 

Dual write wordline memory cell


A static random-access memory (sram) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline.
Industry-academic Cooperation Foundation, Yonsei University


12/31/15
20150380079 

Low power sense amplifier for static random access memory


A low power sense amplifier for an sram is described. A first pass gate transistor is driven by bit line true and a second pass gate transistor is driven by bit line complement.
International Business Machines Corporation


12/31/15
20150380078 

Memory chip and layout design for manufacturing same


A static random access memory (sram) chip including a plurality of sram cells and a plurality of cell current tracking cells. Each of the sram cells include a source voltage reference conductor, a first ground reference conductor, two cross-coupled inverters, and two pass-gate devices.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/31/15
20150380077 

Static random access memory and controlling the same


A static random access memory (sram) including at least a memory cell array, a first data line connected to the memory cell array, and a read assist unit connected to the first data line. The read assist unit is configured to suppress a voltage level of the first data line during a read operation of the memory cell array..
Taiwan Semiconductor Manufacturing Company, Ltd.


12/31/15
20150380076 

Semiconductor integrated circuit device


The invention provides a semiconductor integrated circuit device provided with an sram that satisfies the requirements for both the snm and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines..
Renesas Electronics Corporation


12/31/15
20150380064 

Sram with two-level voltage regulator


A programmable logic device (pld) is provided with a two-level voltage regulator for powering sram cells within the device. In one example, a pld includes a plurality of static random access memory (sram) cells configured to store a configuration for the programmable logic device.
Lattice Semiconductor Corporation


12/24/15
20150371708 

Sram cells


There is provided a memory unit that comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to a first local bit line and a second local bit line by respective first and second access transistors, and each memory cell being associated with a word line configured to control the first and second access transistors of the memory cell. The first and second local bit lines of each memory cell group being operatively connected to respective first and second column bit lines by respective first and second group access switches, the first group access switch being configured to be controlled by the second column bit line, and the second group access switch being configured to be controlled by the first column bit line..
Surecore Limited


12/24/15
20150371702 

Static random access memory and using the same


A static random access memory (sram) including a bit cell, wherein the bit cell includes at least two p-type pass gates. The sram further includes a bit line connected to the bit cell, and a bit line bar connected to the bit cell.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/24/15
20150371701 

Memory chip and layout design for manufacturing same


An embedded synchronous random access memory (sram) chip, includes a first single-port (sp) sram macro and a second sp macro. The first macro includes a first periphery circuit, and a plurality of first sram cells.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/17/15
20150364183 

Method and bit-line sensing gates on an sram cell


A circuit for providing additional current in a memory cell without a higher supply voltage is provided. Embodiments include a circuit having a six transistor static random access memory (sram) cell including a first inverter and second cross-coupled to a second inverter; a first transistor having a first source coupled to a first bit-line, a first drain coupled to the first inverter, and a first gate coupled to a word-line; a second transistor having a second source coupled to the second inverter, a second drain coupled to a second bit-line, and a second gate coupled to the word-line; and a plurality of bit-line sensing transistors coupled to the first transistor and to the second transistor..
Globalfoundries Inc.


12/17/15
20150364168 

Sidecar sram for high granularity in floor plan aspect ratio


A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory.
Advanced Micro Devices, Inc.


12/10/15
20150357233 

Method and fabricating a memory device with a dielectric etch stop layer


The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as dram or sram, various layers are deposited to form structures, such as pmos gates, nmos gates, memory cells, p+ active areas, and n+ active areas.
Micron Technology, Inc.


12/10/15
20150357030 

Methods and designing and constructing dual write memory circuits with voltage assist


Static random access memory (sram) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6t) sram bit cell is proposed.
Cisco Technology, Inc.


12/10/15
20150357028 

Systems and methods involving multi-bank, dual-pipe memory circuitry


Multi-bank, dual-pipe sram systems, methods, processes of operating such srams, and/or methods of fabricating multi-bank, dual-pipe sram are disclosed. For example, one illustrative multi-bank, dual-pipe sram may comprise features for capturing read and write addresses, splitting and/or combining them via one or more splitting/combining processes, and/or bussing them to the sram memory banks, where they may be read and written to a particular bank.
Gsi Technology, Inc.


12/10/15
20150357027 

Systems and methods involving multi-bank memory circuitry


Multi-bank sram devices, systems, methods of operating multi-bank srams, and/or methods of fabricating multi-bank sram systems are disclosed. For example, illustrative multi-bank srams and methods may include or involve features for capturing read and write addresses at a particular frequency, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each sram bank, where they may be split and/or combined via one or more splitting/combining processes to read and write to a particular bank.
Gsi Technology, Inc.


12/10/15
20150357009 

High-density latch arrays


A system and device are provided for implementing memory arrays using high-density latch cells. The device includes an array of cells arranged into columns and rows.
Nvidia Corporation


12/03/15
20150348615 

Array power supply-based screening of static random access memory cells for bias temperature instability


A method of screening complementary metal-oxide-semiconductor cmos integrated circuits, such as integrated circuits including cmos static random access memory (sram) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of sram cells formed of cross-coupled cmos inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both).
Texas Instruments Incorporated


12/03/15
20150348598 

Static random access memory and controlling the same


A static random access memory (sram) that includes a memory cell comprising at least two p-type pass gates. The sram also includes a first data line connected to the memory cell, a second data line connected to the memory cell and a voltage control unit connected to the first data line, wherein the voltage control unit is configured to control the memory cell..
Taiwan Semiconductor Manufacturing Company, Ltd.


12/03/15
20150347216 

Apparatus and preventing error in physically unclonable function


An apparatus and method that prevent a bit error in a static random access memory (sram)-based physically unclonable function (puf). The method for preventing an error in a puf includes selecting any value, from a physically unclonable function based on a volatile memory device, as an input value, and checking a response corresponding to the selected input value, classifying cells having a plurality of bits corresponding to the response depending on frequency of error occurrence, calculating a number of white cells, in which an error does not occur, from classified results, and determining whether the number of white cells is greater than a preset threshold number of white cells, and selecting an input value of the physically unclonable function based on results of determination..
Electronics And Telecommunications Research Institute


11/26/15
20150340294 

Structure and effective device width adjustment in finfet devices using gate workfunction shift


Embodiments of the present invention provide methods and structures by which the inherent discretization of effective width can be relaxed through introduction of a fractional effective device width, thereby allowing greater flexibility for design applications, such as sram design optimization. A portion of some fins are clad with a capping layer or workfunction material to change the threshold voltage (vt) for a part of the fin, rendering that part of the fin electrically inactive, which changes the effective device width (weff).
International Business Machines Corporation


11/26/15
20150340090 

Non-volatile sram with multiple storage states


Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. In some examples, the multi-storage state non-volatile random access memory device has two or more memory cells.
Empire Technology Development Llc


11/26/15
20150340084 

Array power supply-based screening of static random access memory cells for bias temperature instability


A method of screening complementary metal-oxide-semiconductor cmos integrated circuits, such as integrated circuits including cmos static random access memory (sram) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of sram cells formed of cross-coupled cmos inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both).
Texas Instruments Incorporated


11/26/15
20150340083 

Dual-port sram connection structure


The present disclosure provides a static random access memory (sram) cell. The sram cell includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least two pull-down devices; at least four pass gate devices configured with the two cross-coupled inverters; at least two ports coupled with the at least four pass-gate devices for reading and writing; a first contact feature contacting first two pull-down devices (pd-11 and pd-12) of the first inverter; and a second contact feature contacting second two pull-down devices (pd-21 and pd-22) of the second inerter..
Taiwan Semiconductor Manufacturing Company, Ltd.


11/26/15
20150340081 

Array power supply-based screening of static random access memory cells for bias temperature instability


A method of screening complementary metal-oxide-semiconductor cmos integrated circuits, such as integrated circuits including cmos static random access memory (sram) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of sram cells formed of cross-coupled cmos inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both).
Texas Instruments Incorporated


11/19/15
20150333131 

High density static random access memory array having advanced metal patterning


Methods and apparatus directed toward a high density static random access memory (sram) array having advanced metal patterning are provided. In an example, provided is a method for fabricating an sram.
Qualcomm Incorporated


11/19/15
20150333075 

Semiconductor device


A semiconductor device, which can improve reading and writing stability of a static random access memory (sram) is provided. The semiconductor device includes a substrate having a first region and a second region defined therein, a first fin type active pattern formed on the substrate, extending in a first direction and including a first part and a second part, in the first region, the second part being disposed in the first direction at both sides of the first part, a second fin type active pattern formed on the substrate, extending in a second direction and having a third part and a fourth part, in the second region, the fourth part being disposed in the second direction at both sides of the third part and recessed relative to the third part, a first gate electrode extending in a third direction different from the first direction and formed on the first part, a second gate electrode extending in a fourth direction different from the second direction and formed on the third part, a first source/drain formed in the second part and doped with a first type impurity, and a second source/drain including a first epitaxial layer doped with the first type impurity and formed on the fourth part..
Samsung Electronics Co., Ltd.


11/19/15
20150332757 

Configurable delay circuit and clock buffering


An sram clock circuit and an sram. In one embodiment, the sram clock circuit includes: (1) a plurality of transistor stacks optionally serially electrically couplable to form a configurable delay path through which a clock signal is buffered, and (2) a delay path select circuit respectively electrically coupled between pairs of the plurality of transistor stacks and operable to selectively electrically couple the plurality of transistor stacks to a base delay path, thereby activating the configurable delay path based on a desired delay..
Nvidia Corporation


11/12/15
20150325597 

Finfets suitable for use in a high density sram cell


Single gate and dual gate finfet devices suitable for use in an sram memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that sti is unnecessary. Pairs of finfets can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates.
Stmicroelectronics, Inc.


11/12/15
20150325514 

High density sram array design with skipped, inter-layer conductive contacts


A static random access memory (sram) cell includes a first conductive layer including a wordline landing pad extending into a neighboring memory cell in an adjacent row of a memory array. The wordline landing pad in the first conductive layer is electrically isolated from all gate contacts of the neighboring memory cell.
Qualcomm Incorporated


11/12/15
20150325313 

Assist circuits for sram testing


Assist circuits for sram memory tests allow voltage scaling in low-power srams. Word line level reduction (wlr) and negative bit line (nbl) boost assist techniques improve read stability and write margin of sram core-cells, respectively, when the memory operates at a lowered supply voltage.

11/12/15
20150325286 

8t based sram cell and related method


Various embodiments include memory devices and related methods. An embodiment includes circuitry including: a first inverter having a first inverter storage node, the first inverter cross-coupled to a second inverter having a second inverter storage node, wherein each of the first inverter and the second inverter has a reverse bit line controlled feedback transistor coupled between an pull-down transistor and a pull-up transistor, and wherein each pull-down transistor is further coupled to a ground; a first signal line coupled with the reverse bit line controlled feedback transistor of the second inverter; a second signal line coupled with the reverse bit line controlled feedback transistor of the first inverter; a first access transistor coupled with the first inverter storage node, the first signal line, and a third signal line; and a second access transistor coupled with the second inverter storage node, the second signal line, and the third signal line..
International Business Machines Corporation


11/05/15
20150318056 

Memory array test logic


A test circuit for a static random access memory (sram) array includes a plurality of stages coupled in a ring. Each stage includes a plurality of bit cells to store information, a bit line and a complementary bit line coupled to the plurality of bit cells, and a plurality of word lines coupled to the plurality of bit cells.
Advanced Micro Devices Inc.


10/29/15
20150311212 

Structure and sram finfet device


The present disclosure provides an embodiment of a fin-like field-effect transistor (finfet) device. The device includes a substrate having an n-type finfet (nfet) region and a p-type finfet (pfet) region.
Taiwan Semiconductor Manufacturing Company, Ltd.


10/22/15
20150303270 

Connection structure for vertical gate all around (vgaa) devices on semiconductor on insulator (soi) substrate


A vertical gate all around (vgaa) nanowire device circuit routing structure is disclosed. The circuit routing structure comprises a plurality of vgaa nanowire devices including a nmos and a pmos device.
Taiwan Semiconductor Manufacturing Company Limited


10/22/15
20150302918 

Word line decoders for dual rail static random access memories


Word line decoders for dual rail sram devices are disclosed for high performance sub-micron sram designs. One embodiment is an sram device that includes a memory cell array and a word line traversing the memory cell array for selecting memory cells of the memory cell array.
Lsi Corporation


10/22/15
20150302917 

Sram cell and cell layout method


Embodiments of the present disclosure include an array of sram cells, an sram cell, and methods of forming the same. An embodiment is an array of static random access memory (sram) cells including a plurality of overlapping rectangular regions.
Stmicroelectronics International N.v.


10/15/15
20150294991 

Semiconductor device, electronic component, and electronic device


A semiconductor device having a novel structure. A multiport sram and a data memory portion including an os transistor are stacked.

10/15/15
20150294714 

Low-power sram cells


The present invention provides a memory unit (4) comprising: a storage element (6) comprising a pair of back to back inverters (12a, 12b and 14a, 14b) having respective first and second storage access nodes (24, 26); first and second voltage lines (vss, vdd 16a, 6b) across which said pair of back to back inverters (12a, 12b and 14a, 14b) are connected; a first access transistor (18a), connected to said first storage node (24); a second access transistor (18b), connected to said second storage node (26); a write word line (22) connected to a gate (18g1) on said first access transistor (18a) and a gate (18g2) on said second access transistor (18b); a first bit line (28) operably connected for controlling 10 said node (24); a second bit line (30) operably connected for controlling said node (26); in which there is provided a data dependent conductive path (46) between the first and second bit lines (28, 30).. .

10/15/15
20150294713 

Static random access memory devices


The present application relates to an improved static random access memory (sram) device having a plurality of storage cells and a separate read/write circuit. Each of the plurality of storage cells is connected to a read/write data node of the read/write circuit by a dedicated connection, and an access switch which permits read/write access to the storage cell.

10/01/15
20150279450 

Data-aware sram ming same


Exemplary embodiments for sram cells, new control units for sram systems, and embodiments of sram systems are described herein. An sram cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal.
Taiwan Semiconductor Manufacturing Company, Ltd.


09/24/15
20150270272 

Finfet drive strength modification


One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a sram cell formed from finfet transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved sram cell performance..

09/24/15
20150270174 

Integrated circuit and forming the integrated circuit with improved logic transistor performance and sram transistor yield


In an integrated circuit that includes an nmos logic transistor, an nmos sram transistor, and a resistor, the gate of the sram transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps.. .
Texas Instruments Incorporated




Sram topics: Random Access, Static Random Access Memory, Memory Cell, Semiconductor, Memory Cells, Transistors, Semiconductor Memory, Memory Device, Integrated Circuit, Robustness, Field Effect Transistor, Clamping Circuit, Internal Node, Implantation, Data Storage

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