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Sram patents



      
           
This page is updated frequently with new Sram-related patent applications. Subscribe to the Sram RSS feed to automatically get the update: related Sram RSS feeds. RSS updates for this page: Sram RSS RSS


Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and sram…

Texas Instruments

Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and sram…

Method for managing the operation of a memory device having a sram memory plane and a non volatile memory plane, and…

Stmicroelectronics (rousset) Sas

Method for managing the operation of a memory device having a sram memory plane and a non volatile memory plane, and…

Method for managing the operation of a memory device having a sram memory plane and a non volatile memory plane, and…

Mitsubishi Electric

Sram memory card and voltage monitoring circuit

Date/App# patent app List of recent Sram-related patents
01/22/15
20150023091
 Semiconductor device having timing control for read-write memory access operations patent thumbnailSemiconductor device having timing control for read-write memory access operations
A semiconductor device avoids the disturb problem and the collision between write and read operations in a dp-sram cell or a 2p-sram cell. The semiconductor device 1 includes a write word line wla and a read word line wlb each coupled to memory cells 3.
Renesas Electronics Corporation
01/22/15
20150021706
 Integrated circuit and  forming the integrated circuit with improved logic transistor performance and sram transistor yield patent thumbnailIntegrated circuit and forming the integrated circuit with improved logic transistor performance and sram transistor yield
In an integrated circuit that includes an nmos logic transistor, an nmos sram transistor, and a resistor, the gate of the sram transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps.. .
Texas Instruments Incorporated
01/15/15
20150016188
 Method for managing the operation of a memory device having a sram memory plane and a non volatile memory plane, and corresponding memory device patent thumbnailMethod for managing the operation of a memory device having a sram memory plane and a non volatile memory plane, and corresponding memory device
A method can be used for managing the operation of a memory cell that includes an sram elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the sram elementary memory cell and the non-volatile elementary memory cell.
Stmicroelectronics (rousset) Sas
01/15/15
20150016182
 Sram memory card and voltage monitoring circuit patent thumbnailSram memory card and voltage monitoring circuit
An sram memory card includes a monitoring unit that monitors, via a contact, a power supply voltage generated by a battery, set an on value in an alarm signal when electric potential at the contact is lower than a threshold and set an off value in the alarm signal when the electric potential at the contact is equal to or higher than the threshold, and output the alarm signal to an apparatus via an interface unit; a detecting unit that detects an on/off state of the power supply of the apparatus via the interface unit; and a discharge circuit that discharges, according to the on/off state of the power supply of the apparatus detected by the detecting unit, charges accumulated in a first electrode of a capacitive element.. .
Mitsubishi Electric Corporation
01/15/15
20150015274
 Direct memory based ring oscillator (dmro) for on-chip evaluation of sram cell delay and stability patent thumbnailDirect memory based ring oscillator (dmro) for on-chip evaluation of sram cell delay and stability
A novel and useful direct memory based ring oscillator (dmro) circuit and related method for on-chip evaluation of sram delay and stability. The dmro circuit uses an un-modified sram cell in each delay stage of the oscillator.
International Business Machines Corporation
01/08/15
20150012690
 Multi-leveled cache management in a hybrid storage system patent thumbnailMulti-leveled cache management in a hybrid storage system
A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, sdram, and sram. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory.
01/08/15
20150009741
 Valid command detection based on stack position identifiers in memory devices configured for stacked arrangements patent thumbnailValid command detection based on stack position identifiers in memory devices configured for stacked arrangements
Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, rerams, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
Iii Holdings 2, Llc
01/08/15
20150009740
 Latency adjustment based on stack position identifier in memory devices configured for stacked arrangements patent thumbnailLatency adjustment based on stack position identifier in memory devices configured for stacked arrangements
Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, rerams, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
01/08/15
20150009739
 Memory devices with serially connected signals for stacked arrangements patent thumbnailMemory devices with serially connected signals for stacked arrangements
Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
Iii Holdings 2, Llc
01/08/15
20150009738
 Pad selection in memory devices configured for stacked arrangements patent thumbnailPad selection in memory devices configured for stacked arrangements
Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
Iii Holdings 2, Llc
01/08/15
20150009737

Self-refresh adjustment in memory devices configured for stacked arrangements


Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
Iii Holdings 2, Llc
01/08/15
20150008971

Noise current compensation circuit


Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals a and b, and two control terminals con and conf.
Southeast University
01/08/15
20150008533

Multi-port sram manufacturing


Some embodiments relate to an integrated circuit including fin field effect transistors (finfets) thereon. The integrated circuit includes first and second active fin regions having a first conductivity type and spaced apart from one another.
Taiwan Semiconductor Manufacturing Co., Ltd.
01/08/15
20150008522

Semiconductor device


Improvements are achieved in the characteristics of a semiconductor device including sram memory cells. Under an active region in which an access transistor forming an sram is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region.
Renesas Electronics Corporation
01/01/15
20150003148

Methods and designing and constructing dual write memory circuits with voltage assist


Static random access memory (sram) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6t) sram bit cell is proposed.
Memoir Systems, Inc.
01/01/15
20150003147

Sram restore tracking circuit and method


Novel and useful sram restore tracking circuit adapted to improve the tracking of sram cell behavior for different pvt corners. The sram array access path is mainly influenced by two stages: (1) the wordline (wl) delay and (2) the sram cell delay.
International Business Machines Corporation
01/01/15
20150001633

Semicondutor integrated circuit device and system


A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural sram modules.
Renesas Electronics Corporation
12/25/14
20140380068

Sram regulating retention scheme with discrete switch control and instant reference voltage generation


A system including control logic, a voltage reference, a sense amplifier, and a voltage supply circuit is presented. The sense amplifier may be configured to detect a current state of the voltage supply circuit output compared to the reference voltage.
Apple Inc.
12/25/14
20140379977

Dynamic/static random access memory (d/sram)


Dynamic/static random access memory (d/sram) cell, block shift static random access memory (bs-sram) and method using the same employ dynamic storage mode and dynamic storage mode switching to shift data. The d/sram cell includes a static random access memory (sram) cell having a pair of cross-coupled elements to store data, and a dynamic/static (d/s) mode selector to selectably switch the d/sram cell between the dynamic storage mode and a static storage mode.
12/25/14
20140376305

Circuit for enhancing robustness of sub-threshold sram memory cell


The present invention discloses a circuit for improving process robustness of sub-threshold sram memory cells, which serves as an auxiliary circuit for a sub-threshold sram memory cell. The output of the circuit is connected to the pmos tube of the sub-threshold sram memory cell and the substrate of a pmos tube in the circuit.
Southeast University
12/25/14
20140374831

Embedded sram and methods of forming the same


A chip includes a semiconductor substrate, and a first n-type metal oxide semiconductor field effect transistor (nmosfet) at a surface of the semiconductor substrate. The first nmosfet includes a gate stack over the semiconductor substrate, a source/drain region adjacent to the gate stack, and a dislocation plane having a portion in the source/drain region.
Taiwan Semiconductor Manufacturing Company, Ltd.
12/18/14
20140370713

Method of forming fine patterns of a semiconductor device


A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region, where the widths of the narrow-width patterns are smaller than the resolution limitations in a photolithography process used to make the semiconductor device. The first and second regions may comprise cell array regions, with memory cells in the first region and peripheral circuits for operating the memory cells in the second region.
Samsung Electronics Co., Ltd.
12/18/14
20140369562

Image processor


An image processor includes an lsram accessible with a higher speed than a frame memory and configured to hold a second image in a predetermined range of a first image, an image production unit configured to read an image in a predetermined range of the second image and produce a third image for rough search based on the read image, an msram accessible with a higher speed than the frame memory and configured to hold the third image, a first search unit configured to read the third image and perform first motion search based on the third image, and a second search unit configured to read a fourth image in a predetermined range of the second image based on a search result by the first search unit and perform second motion search that is more detailed than the first motion search based on the fourth image.. .
Megachips Corporation
12/18/14
20140369120

Memory device including a sram memory plane and a non volatile memory plane, and operating methods


A memory device includes at least one memory cell having a first sram-type elementary memory cell having two inverters coupled to one another crosswise and two groups, each having at least one non-volatile elementary memory cell. The non-volatile elementary memory cells of the two groups are coupled firstly to a supply terminal and secondly to the outputs and to the inputs of the two inverters via a controllable interconnection stage..
Stmicroelectronics (rousset) Sas
12/18/14
20140369119

Compact memory device including a sram memory plane and a non volatile memory plane, and operating methods


A memory device includes a memory cell with an elementary sram-type cell and an elementary module coupled between a supply terminal and the elementary sram-type cell. The elementary module has a single nonvolatile eeprom elementary memory cell that includes a floating gate transistor.
Stmicroelectronics (rousset) Sas
12/11/14
20140365416

Synapse array, pulse shaper circuit and neuromorphic system


A synapse array based on a static random access memory (sram), a pulse shaper circuit, and a neuromorphic system are provided. The synapse array includes a plurality of synapse circuits.
12/11/14
20140362636

Capacitor backup for sram


Embodiments of the disclosure provide a method for backing up data in an sram device, and an sram device that includes a capacitive backup circuit for backing up data in an sram device. The method may include writing data to the sram cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state.
12/11/14
20140362635

Capacitor backup for sram


Embodiments of the disclosure provide a method for backing up data in an sram device, and an sram device that includes a capacitive backup circuit for backing up data in an sram device. The method may include writing data to the sram cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state.
12/04/14
20140359209

Word shift static random access memory (ws-sram)


Word shift static random access memory (ws-sram) cell, word shift static random access memory (ws-sram) and method using the same employ dynamic storage mode switching to shift data. The ws-sram cell includes a static random access memory (sram) cell having a pair of cross-coupled elements to store data, a dynamic/static (d/s) mode selector to selectably switch the ws-sram cell between the dynamic storage mode and a static storage mode, and a column selector to selectably determine whether or not the ws-sram cell accepts shifted data.
12/04/14
20140353764

Layout to minimize fet variation in small dimension photolithography


A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second fet (field effect transistor).
12/04/14
20140353717

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region


An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure.
11/27/14
20140347933

Nor-based bcam/tcam cell and array with nand scalability


This invention discloses a 2t-string nor-based cam logic cell comprising two physical nand cells connected in series with two horizontal wls and one vertical bl and one vertical sl. Additionally, a sector of nor-based cam logic cell array is configured with n vertical cell strings each including m 2t-string nor-based cam logic cells connected in parallel sharing a local vertical sl and one dedicated vertical ml as an operand word vertical page.
11/27/14
20140347916

Eight transistor (8t) write assist static random access memory (sram) cell


Disclosed are devices, systems and/or methods relating to an eight transistor (8t) static random access memory (sram) cell, according to one or more embodiments. In one embodiment, an sram storage cell is disclosed comprising a word line, a write column select line, a cross-coupled data latch, and a first nmos switch device serially coupled to a second nmos switch device.
11/27/14
20140346609

Cmos process to improve sram yield


An integrated circuit containing an sar sram and cmos logic, in which sidewall spacers on the gate extension of the sar sram cell are thinner than sidewall spacers on the logic pmos gates, so that the depth of the drain node sram psd layer is maintained under the stretch contact. A process of forming an integrated circuit containing an sar sram and cmos logic, including selectively etch the sidewall spacers on the on the gate extension of the sar sram cell, so that the depth of the drain node sram psd layer is maintained under the stretch contact.
11/20/14
20140339551

Semiconductor device


A nonvolatile memory is provided. A semiconductor device (a nonvolatile memory) has a circuit configuration similar to that of a general sram.
11/13/14
20140334688

Image processor


An image processor includes an lsram accessible with a higher speed than a frame memory and configured to hold a second image in a predetermined range of a first image, an image production unit configured to read an image in a predetermined range of the second image from the lsram and produce a third image for rough search based on the read image, an msram accessible with a higher speed than the frame memory and configured to hold the third image produced by the image production unit, a search unit configured to read the third image from the msram and perform first motion search based on the third image, and a search unit configured to read a fourth image in a predetermined range of the second image from the lsram based on a search result by the search unit and perform second motion search that is more detailed than the first motion search based on the fourth image.. .
11/13/14
20140334226

Circuit for reverse biasing inverters for reducing the power consumption of an sram memory


Cmos integrated circuits with very low consumption when idle, and notably the sram volatile memories, are provided. The inverters of the circuit are made up of an nmos transistor and a pmos transistor.
11/13/14
20140332967

Bit cell with double patterened metal layer structures


An approach for providing sram bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge..
11/06/14
20140328113

Pre-charging bitlines in a static random access memory (sram) prior to data access for reducing leakage power, and related systems and methods


Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (sram) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a sram data array of the sram.
11/06/14
20140327082

Sram well-tie with an uninterrupted grated first poly and first contact patterns in a bit cell array


An integrated circuit containing an sram may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in sram cells. Strap rows of the sram containing well ties and/or substrate taps which have sram cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps..
10/30/14
20140322870

Sram cell with different crystal orientation than associated logic


An integrated circuit containing logic transistors and an array of sram cells in which the logic transistors are formed in semiconductor material with one crystal orientation and the sram cells are formed in a second semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of sram cells in which the logic transistors are formed in a top semiconductor layer with one crystal orientation and the sram cells are formed in an epitaxial semiconductor layer with another crystal orientation.
10/30/14
20140321462

Scalable and efficient flow-aware packet distribution


Techniques for efficiently distributing data packets in a network device are provided. In one embodiment, the network device can store a plurality of virtual ip addresses and a plurality of real server ip addresses in an sram-based table.
10/30/14
20140320482

Liquid crystal display (lcd) device


A lcd device includes pixels formed of column data lines and row scanning lines. The pixel includes a display element; a first switching unit that performs sampling on each frame data of an input video signal; a first holding unit that configures an sram, and holds sub frame data; a second switching unit that causes the sub frame data held in the first holding unit; and a second holding unit that configures a dram, and applies output data to the pixel electrode, a pixel control unit that performs an operation of repeating writing the sub frame data in the first holding unit, turning on the second switching units, and rewriting memory content of the second holding units; and a timing control unit.
10/30/14
20140320477

Liquid crystal display device


Provided is a liquid crystal display device that includes: pixels, a pixel control unit, and a common voltage generation unit. The pixel includes: a display element; a first switching unit configured to sample each frame data; a first holding unit configured to form an sram, and to hold sub-frame data sampled; a second switching unit configured to output the sub-frame data; and a second holding unit configured to form a dram, and configured of which stored content is rewritten by the sub-frame data.
10/30/14
20140319609

Finfet drive strength modification


One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a sram cell formed from finfet transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved sram cell performance..
10/23/14
20140315363

6t sram architecture for gate-all-around nanowire devices


A memory device includes a first plurality of semiconductor nanowires tethered between landing pads and suspended over a substrate. A first gate electrode surrounds each of the first plurality of semiconductor nanowires, making them gate-all-around, (gaa) semiconductor nanowires.
10/23/14
20140313819

System on chip including dual power rail and voltage supply method thereof


A system on chip includes an sram. The sram includes at least one memory cell and a peripheral circuit accessing the at least memory cell.
10/23/14
20140313817

Sram core cell design with write assist


A static random access memory (sram) cell is disclosed. The sram cell includes a storage unit configured to store a data bit in a storage node.
10/23/14
20140312426

6t sram architecture for gate-all-around nanowire devices


A memory device includes a first plurality of semiconductor nanowires tethered between landing pads and suspended over a substrate. A first gate electrode surrounds each of the first plurality of semiconductor nanowires, making them gate-all-around (gaa) semiconductor nanowires.
10/16/14
20140307739

Systems and methods for accessing a multi-bank sram


A device may include multi-bank sram logic configured to receive an lookup result that includes a first number of addresses, parse each of the first number of addresses from the received lookup result, simultaneously provide at least one of the first number of parsed addresses to each of a first number of srams, simultaneously read data from each of the first number of srams and simultaneously transmit the read data from each of the first number of srams.. .
10/16/14
20140307503

Eight transistor soft error robust storage cell


A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes.
10/16/14
20140307501

Scalable floating body memory cell for memory compilers and using floating body memories with memory compilers


A floating body sram cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body sram cell by a memory compiler for use in array design is provided..
10/09/14
20140304463

Systems and methods involving multi-bank, dual- or multi-pipe srams


Systems and methods are disclosed for increasing the performance of static random access memory (sram). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank srams, such as quad-b2 srams.
10/09/14
20140299941

Sram cell with reduced voltage droop


A mesh circuit for the vss supply voltage of a sram device is disclosed. Embodiments also provide a sram bitcell design comprising a vss mesh disposed in two different metal layers.
10/02/14
20140295630

Sige sram butted contact resistance improvement


The present disclosure relates to a method for fabricating a butted a contact arrangement configured to couple two transistors, wherein an active region of a first transistor is coupled to a gate of a second transistor. The gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active region of the first transistor and an isolation layer formed about the first transistor.
10/02/14
20140293682

Memory bitcell clusters employing localized generation of complementary bitlines to reduce memory area, and related systems and methods


Embodiments disclosed include memory bitcell clusters employing localized generation of complementary bitlines to reduce memory area. The memory bitcell clusters disclosed may be static random access memory (sram) used as central processing unit (cpu) register files.
10/02/14
20140293681

8t sram cell with one word line


An integrated circuit with sram cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and one passgate transistor may be variously configured to a separate read data line and write data line, or a combined data line, in different embodiments.
10/02/14
20140293679

Management of sram initialization


An embodiment of the current disclosure is directed to a static random access memory (sram) device, and a design structure for the sram device. The sram device may include one or more sram cells.
09/18/14
20140281341

Multiple, per sensor configurable fifos in a single static random access memory (sram) structure


A device includes one or more sensors, one or more processors, one or more sensors, and a memory. The memory has a first portion, a second portion, and a third portion.
09/18/14
20140281184

Mixed memory type hybrid cache


A hybrid cache includes a static random access memory (sram) portion and a resistive random access memory portion. Cache lines of the hybrid cache are configured to include both sram macros and resistive random access memory macros.
09/18/14
20140269137

Canary based sram adaptive voltage scaling (avs) architecture and canary cells for the same


A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank..
09/18/14
20140269114

Circuit for memory write data operation


A pulsed dynamic lcv circuit for improving write operations for sram. The pulsed dynamic lcv circuit includes voltage adjustment circuitry having a plurality of selectable reduced supply voltages and timing adjustment circuitry having a plurality of selectable logical state transition timings for adjustably controlling the voltage and timing of a transition from a selected reduced supply voltage back to a nominal supply voltage.
09/18/14
20140269041

Emulation of static random access memory (sram) by magnetic random access memory (mram)


A magnetic memory system includes a magnetic random access memory (mram) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (fifo) interface device coupled to the mram and including a plurality of fifos each of the magnetic memory banks is coupled to a respective one of the plurality of fifos, the fifo being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the mram is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks..
09/18/14
20140269021

Timing logic for memory array


Among other things, techniques and systems are provided for devising a schedule for performing read/write operations on a memory cell. A control signal is provided to timing logic.
09/18/14
20140269019

Dual-port static random access memory (sram)


In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters.
09/18/14
20140269016

Multiport memory with matching address control


A multiport sram has an array of cells, a first port, and a second port. During a period of different row addresses for the ports, the first port uses first word lines and first bit lines.
09/11/14
20140254293

High-speed memory write driver circuit with voltage level shifting features


Various aspects of a fast, energy efficient write driver capable of efficient operation in a dual-voltage domain memory architecture are provided herein. Specifically, various aspects of the write driver described herein combine a high speed driver with voltage level shifting capabilities that may be implemented efficiently in reducing use of silicon area while using lower power.
09/11/14
20140254249

Stable sram cell


Sram cells and sram cell arrays are described. In one embodiment, an sram cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value.
09/11/14
20140254248

Stable sram cell


Sram cells and sram cell arrays are described. In one embodiment, an sram cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value.
09/11/14
20140254246

Dual-port sram systems


Schematic circuit designs for a dual-port sram cell are disclosed, together with various layout schemes for the dual-port sram cell. The dual-port sram cell comprises a storage unit and a plurality of partial dummy transistors connected to the outputs of the storage unit.


Popular terms: [SEARCH]

Sram topics: Random Access, Static Random Access Memory, Memory Cell, Semiconductor, Memory Cells, Transistors, Semiconductor Memory, Memory Device, Integrated Circuit, Robustness, Field Effect Transistor, Clamping Circuit, Internal Node, Implantation, Data Storage

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