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Sram

Sram-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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NEW Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
Stmicroelectronics, Inc.
June 22, 2017 - N°20170179137

An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial ...
NEW Semiconductor integrated circuit device
Renesas Electronics Corporation
June 22, 2017 - N°20170179136

Prior known static random access memory (sram) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a p-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, ...
NEW Static random access memory device with vertical fet devices
Taiwan Semiconductor Manufacturing Co., Ltd.
June 22, 2017 - N°20170179135

An sram includes an sram array comprising a plurality of sram cells arranged in a matrix. Each of the sram cells includes six vertical field effect transistors. The sram array includes a plurality of groups of conductive regions extending in the column direction. Each of the plurality of groups of conductive regions includes a first to a fourth conductive region ...
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NEW Sram design to facilitate single fin cut in double sidewall image transfer process
International Business Machines Corporation
June 22, 2017 - N°20170178963

A double sidewall image transfer process for forming finfet structures having a fin pitch of less than 40 nm generates paired fins with a spacing determined by the width of a sidewall spacer that forms a second mandrel. Here, the fin pairs are created at two different spacings without requiring the minimum space for the standard sidewall structure. An enlarged space ...
NEW Semiconductor integrated circuit device and wearable device
International Business Machines Corporation
June 22, 2017 - N°20170178717

A semiconductor device includes a cpu, a system controller which designates an operation speed of the cpu, p-type sotb transistors, and n-type sotb transistors. The semiconductor device is provided with an sram which is connected to the cpu, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the ...
Semiconductor device
Renesas Electronics Corporation
June 15, 2017 - N°20170170183

A semiconductor device aims to prevent a leak current from flowing between a well and a corner of an active region formed on an upper surface of another well in an sram. In a memory cell of the sram, a load mosfet is formed. An end of an active region extending in y-direction is arranged to gradually go away from ...
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Static random access memory (sram) device for improving electrical characteristics and logic device including the ...
Samsung Electronics Co., Ltd.
June 08, 2017 - N°20170162583

A static random access memory (sram) device includes a circuit element that includes a first inverter having a first load transistor and a first drive transistor and a second inverter having a second load transistor and a second drive transistor. Input and output nodes of the first inverter and the second inverter are cross-connected to each other. A first transfer ...
Method for manufacturing static random access memory device
Taiwan Semiconductor Manufacturing Company, Ltd.
June 08, 2017 - N°20170162580

In a method of manufacturing an sram device, an insulating layer is formed over a substrate. First dummy patterns are formed over the insulating layer. Sidewall spacer layers, as second dummy patterns, are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the second dummy patterns over the insulating layer. After removing the ...
Sram-like ebi structure design and implementation to capture mosfet source-drain leakage eariler
Globalfoundries Inc.
June 01, 2017 - N°20170154687

A sram-like electron beam inspection (ebi) structure and method for determining defects in integrated circuits inline during the production process at a level that enables earlier detection during fabrication. Initial layers, such as active layer, poly gate and contact of an ic are first fabricated, and a conductive mesh with horizontal components is provided above the contact layers connecting contact ...
Sense amplifier in low power and high performance sram
Texas Instruments Incorporated
June 01, 2017 - N°20170154672

A static random access memory (sram) includes an array of storage cells and a first sense amplifier. The array of storage cells is arranged as rows and columns. The rows correspond to word lines and the columns correspond to bit lines. The first sense amplifier includes a first transistor and a second transistor. The first sense amplifier is configured to ...
Sram structure with reduced capacitance and resistance
Taiwan Semiconductor Manufacturing Company, Ltd.
June 01, 2017 - N°20170154671

A structure includes an sram cell includes a first and a second pull-up mos device, and a first and a second pull-down mos device forming cross-latched inverters with the first pull-up mos device and the second pull-up mos device. A first metal layer is over the gate electrodes of the mos devices in the sram cell. The structure further includes ...
Compact system with memory and pmu integration
Apple Inc.
June 01, 2017 - N°20170154664

One or more integrated circuits including at least one integrated circuit that is fabricated in a dram fabrication process. Capacitors in the dram-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip pmus. Embedded dram memories can be used instead of sram memories, with increased density and reduced ...
Hybrid logic and sram contacts
Apple Inc.
May 25, 2017 - N°20170148799

The method includes forming a first opening in a dielectric layer exposing a source drain region of an sram device and forming a second opening in the dielectric layer exposing a source drain region of a logic device, forming a third opening in the dielectric layer exposing a gate of the sram device and forming a fourth opening in the ...
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Six-transistor sram semiconductor structures and methods of fabrication
Apple Inc.
May 25, 2017 - N°20170148782

A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard cmos process technology can be used to manufacture ...
Synchronous random access memory (sram) chip and two port sram array
Apple Inc.
May 25, 2017 - N°20170148509

A static random access memory (sram) chip includes a first and second conductor, a set of sram cells and a set of first and second tracking cells. The first conductor extends in a first direction, is coupled to a first supply voltage, and on a first metal layer. The second conductor extends in a second direction, is coupled to a ...
Sram device capable of working in multiple low voltages without loss of performance
Apple Inc.
May 25, 2017 - N°20170148508

A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The ...
Semiconductor device
Apple Inc.
May 25, 2017 - N°20170148505

Provided are a semiconductor device. The semiconductor device includes an sram cell including a first pull-up transistor, a first pull-down transistor and a first pass transistor formed on a substrate, a first read buffer transistor connected to gate terminals of the first pull-up transistor and the first pull-down transistor, and a second read buffer transistor which shares a drain terminal ...
Queue management method and apparatus
Apple Inc.
May 25, 2017 - N°20170147251

Embodiments of the present invention disclose a queue management method. The method includes writing a pd queue to a dram, where the pd queue includes multiple pds, and the multiple pds correspond one-to-one to multiple packets included in a first packet queue. The method also includes writing at least one pd in the pd queue to an sram, where the ...
Serial device emulator using two memory levels with dynamic and configurable response
Total Phase, Inc.
May 18, 2017 - N°20170139726

A digital logic device is disclosed that includes registers, sram, dram, and a processor configured to store in the registers an initial portion of a first response data to a command, and store in the sram the first response data. The processor is further configured to store in a lookup table the memory location and size of the first response ...
Three-dimensional static random access memory device structures
Taiwan Semiconductor Manufacturing Company Limited
May 11, 2017 - N°20170133387

Systems and methods are provided for fabricating a static random access memory (sram) cell in a multi-layer semiconductor device structure. An example sram device includes a first array of sram cells, a second array of sram cells, a processing component, and one or more inter-layer connection structures. The first array of sram cells are formed in a first device layer ...
Static random access memory device with vertical fet devices
Taiwan Semiconductor Manufacturing Co., Ltd.
May 04, 2017 - N°20170125424

An sram includes an sram array including a plurality of sram cells arranged in a matrix. Each of the sram cells includes six vertical field effect transistors. The sram array includes a plurality of groups of conductive regions extending in the column direction. Each of the plurality of groups of conductive regions includes a first to a fourth conductive region ...
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