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Sram patents

      

This page is updated frequently with new Sram-related patent applications.




 Control circuit of high-definition naked-eye portable stereoscopic video player and stereoscopic video conversion method patent thumbnailControl circuit of high-definition naked-eye portable stereoscopic video player and stereoscopic video conversion method
The present invention relates to a control circuit of a high-definition naked-eye portable stereoscopic video player and a stereoscopic video conversion method which enables the user to watch a stereoscopic video without wearing the stereoscopic glasses, wherein the control circuit includes a power supply. An hd video ch1 and an hd video ch2 are connected to the signal input terminal of a respective hdmi decoder through a respective hdmi plug interface.
Hangzhou 3dworld Technology Co., Ltd.


 Semiconductor integrated circuit device patent thumbnailSemiconductor integrated circuit device
In an image information chip or the like, a multi-port sram is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port.
Renesas Electronics Corporation


 Design structure for reducing pre-charge voltage for static random-access memory arrays patent thumbnailDesign structure for reducing pre-charge voltage for static random-access memory arrays
A memory cell arrangement of sram cell groups may be provided in which in each of the groups multiple sram cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line.
International Business Machines Corporation


 Design structure for reducing pre-charge voltage for static random-access memory arrays patent thumbnailDesign structure for reducing pre-charge voltage for static random-access memory arrays
A memory cell arrangement of sram cell groups may be provided in which in each of the groups multiple sram cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line.
International Business Machines Corporation


 Design structure for reducing pre-charge voltage for static random-access memory arrays patent thumbnailDesign structure for reducing pre-charge voltage for static random-access memory arrays
A memory cell arrangement of sram cell groups may be provided in which in each of the groups multiple sram cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line.
International Business Machines Corporation


 Cpu bist testing of integrated circuits using serial wire debug patent thumbnailCpu bist testing of integrated circuits using serial wire debug
A method of simultaneously built in self-testing (bist) a sub circuit in a plurality of integrated circuit (ic) chips by embedded microprocessor (cpu) and sram memory using 2 to 4 digital pins per ic chip on automatic test equipment (ate) using a serial wire debug testing protocol. A method of simultaneously built in self-testing (bist) an embedded nonvolatile memory in a plurality of integrated circuit (ic) chips by embedded microprocessor (cpu) and sram memory using 2 to 4 digital pins per ic chip on automatic test equipment (ate) using a serial wire debug testing protocol..
Texas Instruments Incorporated


 Integrated circuit device and  applying error correction to sram memory patent thumbnailIntegrated circuit device and applying error correction to sram memory
In accordance with an embodiment of the invention, an integrated circuit (ic) device is disclosed. In the embodiment, the ic device includes an sram module, wrapper logic coupled to the sram module, a context source, and an ecc profile controller coupled to the context source and to the wrapper logic, the ecc profile controller configured to select an ecc profile in response to context information received from the context source for use by the wrapper logic..
Nxp B.v.


 Integrated circuit device and  reducing sram leakage patent thumbnailIntegrated circuit device and reducing sram leakage
An integrated circuit (ic) device including an sram module coupled to wrapper logic is disclosed. The wrapper logic includes an error correction code (ecc) encoder configured to encode input data in accordance with an ecc encoding scheme and output the encoded input data to the sram module, an ecc decoder configured to decode output data received from the sram module, output the decoded output data, and write decoding information back to the sram module, an error controller coupled to the ecc decoder that is configured to control the ecc decoder in accordance with the ecc encoding scheme, and a central controller coupled to the components of the wrapper logic and the sram module in order to control operations between the components of the wrapper logic and the sram module..
Nxp B.v.


 Integrated circuit device and  reading data from an sram memory patent thumbnailIntegrated circuit device and reading data from an sram memory
In accordance with an embodiment of the invention, an ic device is disclosed. In the embodiment, the ic device includes an array of bit cells of static random-access memory (sram), a multi-level digitization module configured to generate a value in a range of values from a bit cell in the array of bit cells, the range of values including more than two discrete values, an output buffer configured to store the generated values, and an error correction code (ecc) decoder configured to output error corrected values based on the stored values..
Nxp B.v.


 Methods and apparatus to create a physically unclonable function patent thumbnailMethods and apparatus to create a physically unclonable function
Methods and apparatus for creating a physically unclonable function for sram are disclosed. An example method includes decreasing a supply voltage of a memory array to a first voltage level, the first voltage level being below a normal operating voltage associated with the memory array, reading a first value of a bit cell after the supply voltage has been at the first voltage level, and determining a function based on the first value of the bit cell and a second value, the second value stored in the bit cell when the memory array is operating at a voltage level above the first voltage level, the function to represent an identification of a circuit including the memory array..
Texas Instruments Incorporated


Sram cell with dynamic split ground and split wordline

An sram cell with dynamic split ground (gnd) and split wordline (wl) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline.
International Business Machines Corporation

Sram cell with dynamic split ground and split wordline

An sram cell with dynamic split ground (gnd) and split wordline (wl) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline.
International Business Machines Corporation

Static random access memory with reduced write power

A static random access memory (sram) features reduced write cycle power consumption. The sram includes an array of static storage cells and a write controller.
Texas Instruments Incorporated

Method, system, and memory with feedthrough and retiming paths to support memory to memory requests

Memory systems, such as sram systems, are described that comprise a series of adjacently placed memory components for providing memory data and memory transaction information from one component to another. Input pins are strategically placed, and muxing and ancillary logic are included within memory components, to allow for the adjacent placement.
Broadcom Corporation

Techniques for forming a compacted array of functional cells

Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (ngl) processes, such as electron-beam direct write (ebdw) and extreme ultraviolet lithography (euvl), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (fpga) structures configured with logic cells, static random-access memory (sram) structures configured with bit cells, or other memory or logic devices having cell-based structures.
Intel Corporation

Sram timing-based physically unclonable function

Methods and apparatus for creating a physically unclonable function for sram are disclosed. An example method includes after applying a voltage to a memory array: determining a first duration between the applying of the voltage and a first output of a first bit cell, the first output corresponding to a first value stored in the first bit cell, and determining a second duration between the applying of the voltage and a second output of a second bit cell, the second output corresponding to a second value stored in the second bit cell.
Texas Instruments Incorporated

Tunable negative bitline write assist and boost attenuation circuit

An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (sram) arrays. The apparatus includes a memory array comprising a plurality of sram cells.
International Business Machines Corporation

Boost control to improve sram write operation

Approaches for providing write-assist boost for a static random access memory (sram) array are provided. A circuit includes a write driver of a static random access memory (sram) array.
International Business Machines Corporation

Two-port sram connection structure

A static random access memory (sram) device is provided in accordance with some embodiments. The sram device comprises a plurality of two-port sram arrays, which comprise a plurality of two-port sram cells.
Taiwan Semiconductor Manufacturing Co., Ltd.

Static random access memory

The invention concerns a static random access memory (sram) comprising: a plurality of memory cells each having a pair of cross-coupled inverters (102, 104), a first of the inverters (102) being supplied by first and second power supply rails (vdd, vss) and a second of the inverters (104) being supplied by third and fourth supply rails (114, 116), an input of the second inverter (102) being coupled to a first bit line (bl, wbl) via a first transistor (118); and a power supply circuit (120) adapted to apply a first voltage difference (vdd) across the first and second power supply rails (vdd, vss) and a second voltage difference (vdh, vsl) across the third and fourth power supply rails (114, 116), the second voltage difference being greater than the first voltage difference.. .
Commissariat à L'energie Atomique Et Aux Energies Alternatives

High-speed pseudo-dual-port memory with separate precharge controls

A pseudo-dual-port (pdp) memory such as a pdp sram is provided that independently controls the bit line precharging and the sense amplifier precharging to increase memory operating speed while eliminating or reducing the discharge of crowbar current.. .
Qualcomm Incorporated

Non-volatile static ram and operation thereof

A memory device and array which includes a static random access memory (sram) circuit coupled to a non-volatile circuit, such as a ferroelectric-ram (f-ram) circuit, in which the f-ram circuit stores a bit of data from the sram circuit during power-out periods, the f-ram circuit is further coupled to bit-line(s) to output the bit of data stored in the f-ram circuit when operation power is restored.. .
Cypress Semiconductor Corporation

Circuit to improve sram stability

Approaches for stability of cells in a static random access memory (sram) array are provided. A circuit includes a precharging circuit configured to precharge bitlines of a static random access memory (sram) array to a first voltage potential for a non-read operation and to a second voltage potential for a read operation.
International Business Machines Corporation

Semiconductor device having capability of generating chip identification information

A semiconductor device having a capability of generating chip identification information includes: an sram macro having a plurality of memory cells arranged in rows and columns: a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.. .
Renesas Electronics Corporation

Multiple-port sram device

A multiple-port memory cell includes first conductive lines in a first metal layer, second conductive lines in a second metal layer, third conductive lines a third metal layer, and fourth conductive lines in a fourth metal layer. The first conductive lines include a write bit line electrically coupled with a write bit line node; a first read bit line electrically coupled with a first read bit line node; and a second read bit line electrically coupled with a second read bit line node.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor integrated circuit device

There is provided a semiconductor integrated circuit device that can generate a unique id with the suppression of overhead. When a unique id is generated, the potential of a word line of a memory cell in an sram is raised above the power supply voltage of the sram, and then lowered below the power supply voltage of the sram.
Renesas Electronics Corporation

Low-power row-oriented memory write assist circuit

Aspects of the present disclosure generally relate to static random access memory (sram), and more specifically, to a low-power, row-oriented memory write assist circuit. The sram may generally comprise an array of bit cells arranged in rows and columns, wherein each bit cell in a row is selected for writing via a corresponding wordline for that row and wherein each bit cell in a column is coupled to a corresponding pair of bitlines for supplying complementary data values, and at least one row-oriented write assist circuit configured to temporarily reduce, to a desired voltage level, a voltage on an internal voltage line used to supply power to the bit cells of a row selected for writing..
Cisco Technology, Inc.

Aging sensor for a static random access memory (sram)

A static random access memory (sram) includes a first bitcell and a second bitcell. The first bitcell includes an aging transistor and the second bitcell includes a non-aging transistor.
Qualcomm Incorporated

Dual-port static random-access memory cell

The present disclosure provides a static random access memory (sram) cell comprising first, second, and third fins defined in various well regions. The fins are spaced from each other along a first direction and extend lengthwise generally along a second direction perpendicular to the first direction.
Taiwan Semiconductor Manufacturing Company, Ltd.

Optoelectronic component and producing an optoelectronic component

The invention relates to an optoelectronic component (100) comprising an organic light emitting diode (1) designed for emitting radiation and/or heat, a substrate (2), on which the organic light emitting diode is arranged, wherein the substrate (2) comprises a first substrate material (21) and at least one substrate cavity (22) which is filled with a second substrate material (23) different than the first substrate material (21), wherein the second substrate material (23) is designed to dissipate the heat emitted by the organic light emitting diode (1).. .
Osram Oled Gmbh

Light-emitting device and producing a light-emitting device

A light-emitting device includes a substrate having a substrate upper side, a layer sequence arranged on the substrate upper side and having at least one active, light-emitting, organic layer, wherein the layer sequence includes a plurality of emission regions that emit light, current-conducting rails which are a part of the layer sequence, wherein, in a plan view of the substrate upper side, the emissionr egions of the layer sequence are arranged next to the current-conducting rails, an encapsulation glass, wherein the layer sequence is arranged between the substrate and the encapsulation glass, and spacers formed as elevations on an encapsulation glass underside and facing towards the layer sequence of the encapsulation glass, wherein, in a plan view of the substrate upper side, the spacers at least partly overlap with the current-conducting rails, and the spacers prevent direct contact between the encapsulation glass and the layer sequence in the emission regions.. .
Osram Oled Gmbh

Optoelectronic semiconductor chip, optoelectronic semiconductor component, and a producing an optoelectronic semiconductor component

An optoelectronic semiconductor chip includes a semiconductor body that emits primary light, and a luminescence conversion element that emits secondary light by wavelength conversion of at least part of the primary light, wherein the luminescence conversion element has a first lamina fixed to a first partial region of an outer surface of the semiconductor body, the outer surface emitting primary light, and leaving free a second partial region of the outer surface, the luminescence conversion element has a second lamina fixed to a surface of the first lamina facing away from the semiconductor body and spaced apart from the semiconductor body, the first lamina is at least partly transmissive to the primary radiation, a section of the second lamina covers at least the second partial region, and at least the section of the second lamina is absorbent and/or reflective and/or scattering for the primary radiation.. .
Osram Opto Semiconductors Gmbh

Systems and methods for sram with backup non-volatile memory that includes mtj resistive elements

A memory device has an sram that stores a logic state. A first mtj has two terminals.
Freescale Semiconductor, Inc.

Device comprising a plurality of fdsoi static random-access memory bitcells and operation thereof

A device including a plurality of static random-access memory (sram) bitcells arranged in rows and columns, wherein the sram bitcells comprise fully depleted silicon-on-insulator field effect transistors (fdsoi-fets). The fdsoi-fets comprise p-channel-pull-up-transistors, wherein each p-channel-pull-up-transistor comprises a back gate.
Globalfoundries Inc.

Complementary bipolar sram

A complementary lateral bipolar sram device and method of operating. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state.
International Business Machines Corporation

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

Disclosed are various embodiments related to stacked memory devices, such as drams, srams, eeproms, rerams, and cams. For example, stack position identifiers (spids) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments.
Iii Holdings 2, Llc

System on chip for reducing wake-up time, operating same, and computer system including same

A system on chip (soc) includes an internal read-only memory (rom) configured to store a first boot loader; a first internal static random access memory (sram) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal sram configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (dram) controller configured to load an operating system (os) from the booting device into a dram according to control of the second boot loader.. .
Samsung Electronics Co., Ltd.

Light-emitting apparatus

In various embodiments, a light-emitting apparatus is provided. The light-emitting apparatus includes at least one semiconductor light source configured to emit at least one primary light beam, a deflection device configured to deflect the at least one primary light beam onto respectively associated different positions on a phosphor body, at least one light detector configured to detect light that was emitted by the phosphor body, and an evaluation device.
Osram Gmbh

Semiconductor devices and methods of manufacture thereof

A method of forming an sram cell includes forming a first vertical pull-down transistor, a second vertical pull-down transistor, a first vertical pass-gate transistor, and a second vertical pass-gate transistor over a semiconductor substrate. The method includes forming a first conductive trace over a top surface of the first vertical pull-down transistor and the first vertical pass-gate transistor, forming a second conductive trace over a top surface of the second vertical pull-down transistor and the second vertical pass-gate transistor, and forming a first vertical pull-up transistor over a first portion of the first conductive trace.
Taiwan Semiconductor Manufacturing Company, Ltd.

Power savings via selection of sram power source

A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the sram cell when the system voltage is higher than the memory supply voltage with some margin.
Nvidia Corportion

Compact self-aligned implantation transistor edge resistor for sram seu mitigation

This disclosure is directed to techniques for fabricating cmos devices for sram cells with resistors formed along transistor well sidewall edges by self-aligned, angled implantation, which may enable more compact sram architecture with seu mitigation, such as for space-based or other radiation-hardened applications. An example method includes implanting a dopant into a doped semiconductor well covered by a barrier, wherein the doped semiconductor well is disposed on a buried insulator and wherein the dopant is of opposite doping type to the doped semiconductor well, thereby fortning a resistor on an edge of the doped semiconductor well, wherein the resistor has the opposite doping type.
Honeywell International Inc.

Methods of reading six-transistor sram cells

A six-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with methods of operation. Methods of increasing the operational speed in reading the contents of a selected memory cell in an array of such memory cells while lowering power consumption, and of avoiding an indeterminate memory cell state when a memory cell is “awakened” from standby are described..
Kilopass Technology, Inc.

Semiconductor device

There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an sram memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation.
Renesas Electronics Corporation

Sram multi-cell operations

A multi-memory cell operator includes a non-destructive memory array, an activation unit and a multiple column decoder. The non-destructive memory array has first and second bit lines per column.
Gsi Technology Inc.

Semiconductor integrated circuit device

Prior known static random access memory (sram) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a p-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the p-type well region in which an inverter making up an sram cell is formed is subdivided into two portions, which are disposed on the opposite sides of an n-type well region nw1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines.
Renesas Electronics Corporation

Memory bit cell for reduced layout area

An approach for providing sram bit cells with miniaturized bit cells, without local interconnection layers, with improved lithographic printability, and enabling methodology are disclosed. Embodiments include providing first color structures, in a m1 layer, including a first word line, a first bit line, a second bit line, a first ground line, a second ground line, a second latch line or a combination thereof, wherein the first color structures include side edges longer than tip edges; providing second color structures, in the m1 layer, including a second word line, a first power line, a second power line, a first latch line or a combination thereof, wherein the second color structures include side edges longer than tip edges; and forming a bit cell including the first color structures and the second color structures, wherein adjacent tip edges include a first color structure tip edge and a second color structure tip edge..
Globalfoundries Inc.

Static random access memory

A static random access memory (sram) is disclosed. The sram includes a plurality of sram cells on a substrate, in which each of the sram cells comprises: a gate structure on the substrate; a first interlayer dielectric (ild) layer around the gate structure; a first contact plug in the first ild layer; a second ild layer on the first ild layer; and a second contact plug in the second ild layer and electrically connected to the first contact plug..
United Microelectronics Corp.

Offset detection

There is provided a method of detecting offset in a sense amplifier of an sram memory unit. The method comprises using a sense amplifier of the sram memory unit to implement a read of a first data value stored in a memory cell of the sram memory unit, and measuring a first time for the sense amplifier to read the first data value.
Surecore Limited

Error correction in solid state drives (ssd)

A paging scheme for a solid state drive (ssd) error correction mechanism that exchanges portions of a parity component, such as a page, between sram and less expensive dram, which stores the remainder of a context of pages. A parity operation applies an xor function to corresponding memory positions in the pages of the context.

Readout circuitry for image sensor

Readout circuitry to readout an array of image sensor pixels includes readout units that include a plurality of analog-to-digital converters (“adcs”), a plurality of blocks of static random-access memory (“sram”), and a plurality of blocks of dynamic random-access memory (“dram”). The plurality adcs is coupled to readout analog image signals two-dimensional blocks of the array of image sensor pixels.
Omnivision Technologies, Inc.



Sram topics:
  • Random Access
  • Static Random Access Memory
  • Memory Cell
  • Semiconductor
  • Memory Cells
  • Transistors
  • Semiconductor Memory
  • Memory Device
  • Integrated Circuit
  • Robustness
  • Field Effect Transistor
  • Clamping Circuit
  • Internal Node
  • Implantation
  • Data Storage


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    This listing is a sample listing of patent applications related to Sram for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Sram with additional patents listed. Browse our RSS directory or Search for other possible listings.


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