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Silicon-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Electric motor
February 15, 2018 - N°20180048195

An electric motor includes a permanent magnet rotor unit and a stator unit. The permanent magnet rotor unit includes a spindle, at least one magnet fixedly disposed beside the spindle, at least one magnetic yoke fixedly disposed at an outer end of the magnet. The stator unit includes a cylindrical extension body. At least one coil is provided on the ...
Germanium-on-silicon laser in cmos technology
Universite Paris Sud
February 15, 2018 - N°20180048123

A germanium waveguide is formed from a p-type silicon substrate that is coated with a heavily-doped n-type germanium layer and a first n-type doped silicon layer. Trenches are etched into the silicon substrate to form a stack of a substrate strip, a germanium strip, and a first silicon strip. This structure is then coated with a silicon nitride layer.
Rechargeable battery with wafer current collector and assembly method
Gridtential Energy, Inc.
February 15, 2018 - N°20180047992

Apparatus and techniques herein related battery plates. For example, a first battery plate can include a conductive silicon wafer. A first mechanical support can be located on a first side of the conductive silicon wafer. A first active material can be adhered to the first mechanical support and the first side of the conductive silicon wafer, the first active material ...
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Negative electrode active material and method for producing the same, negative electrode, and battery
Sony Corporation
February 15, 2018 - N°20180047981

A negative electrode contains a negative electrode active material. A negative electrode active material includes: lithium; a first element consisting of silicon or tin; and a second element consisting of oxygen or fluorine, in which the negative electrode active material contains substantially no compound phase of the first element and the lithium, and contains an amorphous phase containing the first ...
Separation method, light-emitting device, module, and electronic device
Semiconductor Energy Laboratory Co., Ltd.
February 15, 2018 - N°20180047902

A method for manufacturing a flexible semiconductor device is disclosed. The method includes: forming a separation layer of a metal over a substrate; treating the separation layer with plasma under an atmosphere containing nitrogen, oxygen, silicon, and hydrogen; forming a layer over the plasma-treated separation layer, the layer being capable of supplying hydrogen and nitrogen to the separation layer; forming ...
Process for depositing porous organosilicate glass films for use as resistive random access memory
Versum Materials Us, Llc
February 15, 2018 - N°20180047898

A process for forming a resistive random-access memory device, the process comprising the steps of: depositing a first electrode on a substrate; forming a porous resistive memory material layer on the first electrode, wherein the porous resistive memory layer is formed by (i) depositing a gaseous composition comprising a silicon precursor and a porogen precursor and, once deposited, (ii) removing ...
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  • 4172+ full patent PDF documents of Silicon-related inventions.
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Method of manufacturing a semiconductor device
Sii Semiconductor Corporation
February 15, 2018 - N°20180047858

Provided is a method of manufacturing a semiconductor device having a photodiode that has a shallow p-n junction and thus achieves high sensitivity to an ultraviolet ray, in which an oxide containing impurities at high concentration is deposited on the surface of the silicon substrate, and thereafter a diffusion region is formed to have a shallow junction by performing thermal ...
Power semiconductor element and power semiconductor module using same
Hitachi, Ltd.
February 15, 2018 - N°20180047855

In a schottky barrier diode comprising silicon carbide: an active region includes a first semiconductor region of a first conductivity type configuring a first schottky junction having a plurality of linear patterns between a first electrode and the first semiconductor region and a second semiconductor region of a second conductivity type adjacent to the first schottky junction and connected to ...
Semi-floating gate fet
Stmicroelectronics, Inc.
February 15, 2018 - N°20180047849

A semi-floating gate transistor is implemented as a vertical fet built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, ...
Tensile strained high percentage silicon germanium alloy finfets
International Business Machines Corporation
February 15, 2018 - N°20180047847

A thermal mixing process is employed to convert a portion of a silicon germanium alloy fin having a first germanium content and an overlying non-doped epitaxial silicon source material into a silicon germanium alloy source structure having a second germanium content that is less than the first germanium content, to convert another portion of the silicon germanium alloy fin and ...
Structure and method for forming strained finfet by cladding stressors
International Business Machines Corporation
February 15, 2018 - N°20180047845

Various methods and structures for fabricating a strained semiconductor fin of a finfet device. A strained semiconductor fin structure includes a substrate, a semiconductor fin disposed on the substrate, the semiconductor fin having two fin ends, and a stressor material cladding wrapped around a portion of each of the two fin ends forming a strained semiconductor fin that includes at ...
High voltage mosfet devices and methods of making the devices
Monolith Semiconductor Inc.
February 15, 2018 - N°20180047844

A sic mosfet device having low specific on resistance is described. The device has n+, p-well and jfet regions extended in one direction (y-direction) and p+ and source contacts extended in an orthogonal direction (x-direction). The polysilicon gate of the device covers the jfet region and is terminated over the p-well region to minimize electric field at the polysilicon gate ...
Techniques for forming non-planar germanium quantum well devices
Intel Corporation
February 15, 2018 - N°20180047839

Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group iv or iii-v semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e. G. Sige or gaas buffer on ...
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Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts
Globalfoundries Inc.
February 15, 2018 - N°20180047824

An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an ...
Semiconductor device including metal-semiconductor junction
Samsung Electronics Co., Ltd.
February 15, 2018 - N°20180047818

A semiconductor device includes a silicon semiconductor layer including at least one region doped with a first conductive type dopant, a metal material layer electrically connected to the doped region, and a self-assembled monolayer (sam) between the doped region and the metal material layer, the sam forming a molecular dipole on an interface of the silicon semiconductor layer in a ...
Array substrate manufacturing method and array substrate
Wuhan China Star Optoelectronics Technology Co., Ltd.
February 15, 2018 - N°20180047764

The present invention provides an array substrate manufacturing method and an array substrate. The array substrate manufacturing method of the present invention uses an organic photoresist material to form a passivation protection layer (90) for substituting the conventional passivation protection layer that is made of a silicon nitride material and applies one mask to subject the passivation protection layer (90) and a ...
Transistor display panel and manufacturing method thereof
Samsung Display Co., Ltd.
February 15, 2018 - N°20180047762

A method of manufacturing a transistor display panel and a transistor display panel, the method including forming a polycrystalline silicon layer on a substrate; forming an active layer by patterning the polycrystalline silicon layer; forming a first insulating layer covering the substrate and the active layer; exposing the active layer by polishing the first insulating layer using a polishing apparatus; ...
Semiconductor device
Semiconductor Energy Laboratory Co., Ltd.
February 15, 2018 - N°20180047753

A nitride insulating film which prevents diffusion of hydrogen into an oxide semiconductor film in a transistor including an oxide semiconductor is provided. Further, a semiconductor device which has favorable electrical characteristics by using a transistor including a silicon semiconductor and a transistor including an oxide semiconductor is provided. Two nitride insulating films having different functions are provided between the ...
Semiconductor device and method of manufacturing the same
Renesas Electronics Corporation
February 15, 2018 - N°20180047746

Deterioration in reliability is prevented regarding a semiconductor device. The deterioration is caused when an insulating film for formation of a sidewall is embedded between gate electrodes at the time of forming sidewalls having two kinds of different widths on a substrate. A sidewall-shaped silicon oxide film is formed over each sidewall of a gate electrode of a low breakdown ...
Semiconductor device and production method thereof
Seiko Epson Corporation
February 15, 2018 - N°20180047745

A semiconductor device includes: a memory transistor including a first silicon oxide film, a first silicon nitride film, a second silicon oxide film, and a first gate electrode that are disposed in sequence on a substrate; and a mos transistor including a third silicon oxide film and a second gate electrode that are disposed in sequence on the substrate. The ...
3d ctf integration using hybrid charge trap layer of sin and self aligned sige nanodot
Applied Materials, Inc.
February 15, 2018 - N°20180047743

Provided are an improved memory device and a method of manufacturing the same. In one embodiment, the memory device may include a vertical stack of alternating oxide layer and nitride layer, the vertical stack having a channel region formed therethrough, a plurality of nanostructures selectively formed on nitride layer of the vertical stack, and a gate oxide layer disposed on ...
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