|| List of recent Silicon Wafer-related patents
| Method and device for peeling off silicon wafers|
A device for peeling off silicon wafers, including: a supporting member that is configured to support a board-shaped member to which plural silicon wafers are bonded via an adhesive; a heating unit for heating the board-shaped member; a shifting mechanism that is configured to shift, in a horizontal direction, the supporting member relatively with respect to the heating unit; a peeling-off mechanism that is configured to peel off the silicon wafers one by one; and a container for allowing the silicon wafers, the board-shaped member and the supporting member to soak in a liquid.. .
| Low-metal content electroconductive paste composition|
An electroconductive paste for use in solar cell technology comprising a first silver particle that is less than one micron in size and having a surface area of greater than 2.4 m2/g, as well as glass frit and an organic vehicle. Another embodiment of the invention relates to an electroconductive paste for use in solar cell technology further comprising a second silver particle that is greater than one micron in size and having a surface area of less than 2 m2/g.
| Recovery of silicon value from kerf silicon waste|
The present invention is for the recovery of maximum silicon value of kerf silicon waste, produced during the manufacture of silicon wafers by wire saw, diamond saw and chemical mechanical polishing, as high purity metallurgical silicon. This recovery is achieved by a process scheme that effects an initial removal of minor extrinsic metallic impurities but not the major silicon compound impurities, and followed, preferentially, by a direct metallurgical process to form elemental silicon.
|Method for producing silicon wafer|
The present invention provides a method for producing a silicon wafer including a step of, after growing the oxide film on one surface of a raw material silicon wafer by chemical-vapor deposition, performing double-side polishing of the raw material silicon wafer in such a manner that a suede polishing pad or a velour polishing pad with an asker-c rubber hardness of 50° or more but less than 90° is used for the oxide-film surface.. .
|Method for fracturing and forming a pattern using shaped beam charged particle beam lithography|
In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a plurality of circular or nearly-circular shaped beam shots can form a non-circular pattern on a surface. Methods for manufacturing a reticle and for manufacturing a substrate such as a silicon wafer by forming non-circular patterns on a surface using a plurality of circular or nearly-circular shaped beam shots is also disclosed..
|Seebeck solar cell|
A seebeck solar cell device is disclosed, combining both photovoltaic and thermoelectric techniques. The device may be formed using, for example, a conventional photovoltaic cell formed from a doped silicon wafer.
|High quality gan high-voltage hfets on silicon|
Substrates of gan over silicon suitable for forming electronics devices such as heterostructure field effect transistors (hfets), and methods of making the substrates, are disclosed. Voids in a crystalline al2o3 film on a top surface of a silicon wafer are formed.
|Glass composition and its use in conductive silver paste|
A lead-tellurium-lithium-titanium-oxide glass composition is useful as a component of a conductive silver paste. Especially useful are p-containing and v-containing lead-tellurium-lithium-titanium-oxide glass composition.
|Pressure transducer utilizing non-lead containing frit|
A piezoresistive sensor device and a method for making a piezoresistive device are disclosed. The sensor device comprises a silicon wafer having piezoresistive elements and contacts in electrical communication with the elements.
|Method for manufacturing semiconductor wafer|
A method of manufacturing a silicon wafer, an oxygen concentration in a surface layer to be maintained more than a predetermined value while promoting a defect-free layer. Strength of the surface layer can be made higher than that of an ordinary annealed sample as a cop free zone is secured.
|Overlay targets with orthogonal underlayer dummyfill|
The disclosure is directed to designing and using an overlay target with orthogonal underlayer dummyfill. According to various embodiments, an overlay target may include one or more segmented overlay pattern elements forming at least one overlay target structure.
|Solar cell wafer and method of producing the same|
A solar cell wafer having a porous layer on a surface of a semiconductor wafer typified by a silicon wafer, which can further reduce reflection loss of light at the surface. A solar cell wafer 100 of the present invention has a porous layer 11 having a pore diameter of 10 nm or more and 45 nm or less, on at least one surface 10a of a semiconductor wafer 10, and the layer thickness of the porous layer 11 is more than 50 nm and 450 nm or less..
|Method for cleaning silicon wafer and apparatus for cleaning silicon wafer|
A silicon wafer after being cleaned by using a cleaning liquid is rinsed by using carbonic water. According to such a silicon wafer cleaning method, generation of static due to a rinsing treatment is not caused, so that an electrostatic breakdown is not caused, adhesion of dirt to a cleaned silicon wafer surface due to the static is not caused, adhesion of metal impurities can be prevented in the rinsing treatment of the silicon wafer and, while giving consideration to the cost, furthermore, a rinsing treatment using a clean rinsing liquid free from causing any residue can be performed..
|Method for optical proximity correction of a reticle to be manufactured using shaped beam lithography|
In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a series of curvilinear character projection shots are determined for a charged particle beam writer system, such that the set of shots can form a continuous track, possibly of varying width, on a surface. A method for forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed.
|Method of manufacturing laminated wafer by high temperature laminating method|
A method of manufacturing a laminated wafer is provided by forming a silicon film layer on a surface of an insulating substrate comprising the steps in the following order of: applying a surface activation treatment to both a surface of a silicon wafer or a silicon wafer to which an oxide film is layered and a surface of the insulating substrate followed by laminating in an atmosphere of temperature exceeding 50° c. And lower than 300° c., applying a heat treatment to a laminated wafer at a temperature of 200° c.
|Vacuum treatment apparatus and a method for manufacturing|
A vacuum treatment apparatus and method for manufacturing has a plurality of treatment chambers for treating workpieces, in particular silicon wafers, a transfer chamber attached to the treatment chambers communicating via respective openings and having handling zones located adjacent to each of the treatment chambers. A workpiece carrier is arranged within the transfer chamber and configured to transfer the workpieces between the handling zones, and one or more handlers for moving the workpieces between the handling zones and the treatment chambers.
|Strain-enhanced silicon photon-to-electron conversion devices|
Improved silicon solar cells, silicon image sensors and like photosensitive devices are made to include strained silicon at or sufficiently near the junctions or other active regions of the devices to provide increased sensitivity to longer wavelength light. Strained silicon has a lower band gap than conventional silicon.
|Permanently bonded fluid channel nozzle plate fabrication|
Fabricating a printhead includes providing a silicon wafer including first and second surfaces and a nozzle membrane layer on the first surface of the silicon wafer. The silicon wafer is sized to a thickness ranging from 10 to 250 microns.
|Soi wafer, manufacturing method therefor, and mems device|
In order to obtain a soi wafer having an excellent ability of gettering metal impurities, an efficient method of manufacturing a soi wafer, and a highly reliable mems device using such a soi wafer, provided is a soi wafer including: a support wafer (1) and an active layer wafer (6) which are bonded together with an oxide film (3) therebetween, each of the support wafer (1) and the active layer wafer (6) being a silicon wafer; a cavity (1b) formed in a bonding surface of at least one of the silicon wafers; and a gettering material (2) formed on a surface on a side opposite to the bonding surface.. .
|Process of forming a grid electrode on the front-side of a silicon wafer|
Wherein the inorganic content of metal paste b contains less glass frit plus optionally present other inorganic additives than the inorganic content of metal paste a.. .
|Freestanding network of carbon nanofibers|
The present invention relates to a freestanding network of carbon nanofibers. The present invention further relates to a method of fabricating a freestanding network of carbon nanofibers.
|Silicon wafer and fabrication method thereof|
A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first denuded zone being formed with a depth ranging from approximately 20 μm to approximately 80 μm from the top surface, and a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen uniformly distributed within a variation of 10% over the bulk area..
|Tellurium inorganic reaction systems for conductive thick film paste for solar cell contacts|
This disclosure relates to electroconductive paste formulations useful in solar panel technology. In one aspect, the disclosure relates to an inorganic reaction system for use in electroconductive paste compositions, wherein the inorganic reaction system comprises a lead containing matrix composition and a tellurium containing matrix composition.
|Broken wafer recovery system|
An apparatus and method for recovery and cleaning of broken substrates, especially beneficial for fabrication systems using silicon wafer carried on trays. Removal of broken wafers and particles from within the fabrication system is enabled without requiring disassembly of the system and without requiring manual labor.
|Method for making a semi-conducting substrate located on an insulation layer|
A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.. .
|Method for producing trench-like depressions in the surface of a wafer|
In a method of producing trench-like depressions (24) in the surface of a wafer (27), particularly a silicon wafer, by plasma etching, in which the depressions (24) are produced by alternate passivation and etching, each depression (24) in its final geometry is provided with a protective layer (30) of the polytetrafluoroethylene type.. .
|Method of manufacturing semiconductor device|
A reverse blocking igbt is manufactured using a silicon wafer sliced from a single crystal silicon ingot which is manufactured by a floating method using a single crystal silicon ingot manufactured by a czochralski method as a raw material. A separation layer for ensuring a reverse blocking performance of the reverse blocking igbt is formed by diffusing impurities implanted into the silicon wafer using a thermal diffusion process.
|Methods for forming resistive switching memory elements|
Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits.
|Rf esd device level differential voltage measurement|
A method of measuring, recording, and calculating high speed differential voltage measurements across a device-under-test during electrostatic discharge testing of for discrete devices and silicon wafer probing uses high frequency components and a combination of high impedance resistors and attenuators to allow differential voltage measurements of stress signals including ied 61000-4-2, hmm, hbm, and mm with voltages in excess of +/−12000v.. .
|Electrode body, wiring substrate, and semiconductor device|
An electrode body is provided as an electrode body capable of appropriately reducing a load when silicon wafer direct bonding is performed. The electrode body includes a base member that has a predetermined thickness; and an electrode portion that is formed on one surface of the base member in a thickness direction thereof.
|Method for cleaning textured silicon wafers|
Substrates for solar cells are prepared by the reverse of the standard rca clean. The substrates are first cleaned in rca-2 solution and then in rca-1 solution.
|Method of cutting semiconductor substrate|
Multiphoton absorption is generated, so as to form a part which is intended to be cut 9 due to a molten processed region 13 within a silicon wafer 11, and then an adhesive sheet 20 bonded to the silicon wafer 11 is expanded. This cuts the silicon wafer 11 along the part which is intended to be cut 9 with a high precision into semiconductor chips 25.
|Nanoporous silicon and lithium ion battery anodes formed therefrom|
An electrode for a lithium ion battery, the electrode including nanoporous silicon structures, each nanoporous silicon structure defining a multiplicity of pores, a binder, and a conductive substrate. The nanoporous silicon structures are mixed with the binder to form a composition, and the composition is adhered to the conductive substrate to form the electrode.
|Method to prepare silicon particles for use in lithium secondary battery anodes|
The disclosure describes a process to fabricate composite anodes for lithium secondary batteries using silicon particles obtained from the byproducts of silicon manufacturing processes. Silicon particles are obtained from the byproducts of solar cell manufacturing or silicon wafer manufacturing steps such as sawing, polishing and deposition processes.
A silicon wafer is provided in which a dislocation is less likely lo be generated originating from an oxide precipitate in a semiconductor device forming process, and a gettering effect with respect to cu is increased. A silicon wafer 1 is characterized in that a surface layer portion 1a from a surface to a depth of at least 5 μm has an lstd density of less than 1.0/cm2, and that in a bulk portion 1b except the surface layer portion 1a, planar oxide precipitates 2a and polyhedral oxide precipitates 2b having a scattered light intensity of 3000 to 5000 a.u., and a density of 1.0×109 to 6.0×109 (particles/cm3) are each intermingled and grown, and a density ratio of the planar oxide precipitate to polyhedral oxide precipitate is represented by (planar oxide precipitate:polyhedral oxide precipitate=x: (100-x), where x is 10 to 40)..
|New electrical conductor for attaching silicon wafers in photovoltaic modules|
The invention relates to an electrical conductor (2) having a longitudinal axis (a) parallel to the rolling direction of a conductor wire, comprising copper material and an attachment surface (7) configured for attaching to a receiving surface of a silicon wafer (3) to establish an electrical connection. The copper material has a purity of at least 99.5% wherein the grains have a cubic texture comprising a set of cubic axes directed within an up to 20 degree angular range to the longitudinal axis (a), and whereby at least 65% of the grains have said cubic texture.
|Process and apparatus for measuring the crystal fraction of crystalline silicon casted mono wafers|
Provided are methods and apparatus for determining the crystal fraction of a casted-mono silicon wafer. A light source is directed at the wafer and the transmission or reflection is measured by a detector.
|Trench process and structure for backside contact solar cells with polysilicon doped regions|
A solar cell includes polysilicon p-type and n-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the p-type doped region from the n-type doped region.
|Piezoresistive load sensor|
A three-axis load sensor utilizing four piezoresistive devices on a flexible silicon membrane is provided. The load sensor further includes a mesa disposed on the membrane substantially equidistant from the piezoresistive devices.