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Silicon Interposer patents

      

This page is updated frequently with new Silicon Interposer-related patent applications.




 Semiconductor package and mounting structure thereof patent thumbnailnew patent Semiconductor package and mounting structure thereof
A semiconductor package includes an interposer, a semiconductor element installed on a first surface of the interposer, bumps formed on a second surface of the interposer, and a chip component installed on the second surface of the interposer. The interposer is a silicon interposer; the semiconductor element is flip-chip mounted on the first surface of the interposer; the chip component is a thin film passive element formed by carrying out a thin film process on a silicon substrate, and a pad being formed on one surface of the thin film passive element; and the pad of the chip component is connected to a land formed on the second surface of the interposer using a conductive bonding material.
Murata Manufacturing Co., Ltd.


 Electronic package and fabrication method thereof patent thumbnailElectronic package and fabrication method thereof
An electronic package is provided, which includes: a circuit structure having opposite first and second sides; at least an electronic element disposed on the first side of the circuit structure; an encapsulant formed on the first side of the circuit structure for encapsulating the electronic element; a dielectric layer formed on portions of the second side of the circuit structure; and a metal structure formed on the dielectric layer and the circuit structure. The metal structure has a first metal layer bonded to the circuit structure and a second metal layer formed on the first metal layer and the dielectric layer.
Siliconware Precision Industries Co., Ltd.


 Probe card for testing wafer patent thumbnailProbe card for testing wafer
A probe card for circuit-testing comprising a testing pcb, a probe head, and a silicon interposer substrate is provided. The probe head has a plurality of probes provided with a fine pitch arrangement and held inside.
Hermes-epitek Corp.


 Semiconductor package with high routing density patch patent thumbnailSemiconductor package with high routing density patch
Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (slim) patch, comprising a beol portion, and can be tsv-less.
Amkor Technology, Inc.


 Silicon interposer sndwich structure for esd, emi, and emc shielding and protection patent thumbnailSilicon interposer sndwich structure for esd, emi, and emc shielding and protection
A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer.
International Business Machines Corporation


 Interposer with lattice construction and embedded conductive metal structures patent thumbnailInterposer with lattice construction and embedded conductive metal structures
A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material.
International Business Machines Corporation


 Interposer with lattice construction and embedded conductive metal structures patent thumbnailInterposer with lattice construction and embedded conductive metal structures
A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material.
International Business Machines Corporation


 Scalable 2.5d interface architecture patent thumbnailScalable 2.5d interface architecture
Systems and methods for interface block. The interface block includes input/output modules distributed along the interface block and a mid-stack module interspersed within the input/output modules.
Altera Corporation


 Carrier-less silicon interposer patent thumbnailCarrier-less silicon interposer
An interposer has conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component includes a first element having a thermal expansion coefficient less than 10 ppm/° c., and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element.
Invensas Corporation


 Testing interposer method and apparatus patent thumbnailTesting interposer method and apparatus
The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer..
Texas Instruments Incorporated


Semiconductor package and fabrication method thereof and carrier structure

A carrier structure is provided, which includes: a metal oxide plate having opposite first and second surfaces and a plurality of through holes penetrating the first and second surfaces; a plurality of conductive portions formed in the through holes, respectively; and a plurality of conductive pads formed on the first surface of the metal oxide plate, wherein each of the conductive pads is correspondingly positioned on and in contact with a plurality of the conductive portions so as to be electrically connected to the plurality of the conductive portions. By replacing a conventional silicon interposer with the metal oxide plate, the present invention eliminates the need to form through silicon vias as required in the prior art and therefore simplifies the fabrication process..
Siliconware Precision Industries Co., Ltd.

Low latency, high bandwidth memory subsystem incorporating die-stacked dram

A memory subsystem incorporating a die-stacked dram (dsdram) is disclosed. In one embodiment, a system include a processor implemented on a silicon interposer of an integrated circuit (ic) package, a dsdram coupled to the processor, the dsdram implemented on the silicon interposer of the ic package, and a dram implemented separately from the ic package.
Oracle International Corporation

Embedded die flip-chip package assembly

Embodiments of the present disclosure describe integrated circuit (ic) package assemblies and methods of fabricating ic package assemblies. These embodiments include dies embedded in embedding substrates to provide larger pitch interconnects to facilitate coupling to substrates or circuit boards through flip chip techniques.

Testing interposer method and apparatus

The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer..
Texas Instruments Incorporated

Carrier-less silicon interposer using photo patterned polymer as substrate

A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example.
Invensas Corporation

Apparatus for dicing interposer assembly

Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon.
Taiwan Semiconductor Manufacturing Company, Ltd.

Universal encapsulation substrate, encapsulation structure and encapsulation method

A universal packaging substrate, comprising a first substrate (102) and a silicon interposer (103), wherein, a plurality of bumps (106) are formed between the upper surface of the first substrate (102) and the lower surface of the silicon interposer (103) and electrically connect the upper surface of the first substrate (102) and the lower surface of the silicon interposer (103), and a plurality of wire bonding pads are formed on the upper surface of the silicon interposer (103) and are electrically connected to the bumps (106) respectively via silicon through holes (105). Also disclosed are a packaging structure provided with the packaging substrate and an packaging method.

Heterogeneous integration of memory and split-architecture processor

A method for fabricating a semiconductor device provides a first chip having first terminals, a second chip having second terminals, and a third chip having third terminals. A first silicon interposer having first through silicon vias tsvs and a second silicon interposer having second tsvs is provided.
Texas Instruments Incorporated

Semiconductor package and fabricating the same

The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced..
Siliconware Precision Industries Co., Ltd.

Semiconductor package and fabricating the same

The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. The present invention does not require formation of a silicon interposer, therefore the overall cost of the final product is much reduced..
Siliconware Precision Industries Co., Ltd.

Parallel signal via structure

A silicon interposer with redundant thru-silicon vias. The silicon interposer includes a first trace structure on a first side of the interposer and a second trace structure on a second side of the interposer.

Wafer scale packaging platform for transceivers

A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components.

Carrier-less silicon interposer

An interposer can have conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component can include a first element having a thermal expansion coefficient less than 10 ppm/° c., and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element.

Computation memory operations in a logic layer of a stacked memory

Some die-stacked memories will contain a logic layer in addition to one or more layers of dram (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies.

Compound memory operations in a logic layer of a stacked memory

Some die-stacked memories will contain a logic layer in addition to one or more layers of dram (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies.

Integrated circuit device with stitched interposer

Systems, methods, and devices are provided to enable an integrated circuit device of relatively higher capacity. Such an integrated circuit device may include at least two component integrated circuits that communicate with one another.

3d semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor

A standard memory chip (150) is vertically assembled with two processor chips (130, 140) of split architecture by means of a small silicon interposer (120) stacked onto a large silicon interposer (110); both interposers include through-silicon vias (tsvs), while the chips are free of tsvs. The tsvs of small interposer (120) connect to the memory chip (150) and to the bottom interposer (110).

Integration of chips and silicon-based trench capacitors using low parasitic silicon-level connections

Methods and apparatuses are described for integration of integrated circuit die and silicon-based trench capacitors using silicon-level connections to reduce connection lengths, parasitics and necessary capacitance magnitudes and volumes. A trench capacitor can be fabricated on silicon and mounted on or embedded in a chip or one or more sides of a through silicon interposer (tsi) for silicon-level connections to chip circuitry.

Probe card for circuit-testing

A probe card for circuit-testing comprising a testing pcb, a probe head, and a silicon interposer substrate is provided. The probe head has a plurality of probes provided with a fine pitch arrangement and held inside.

Optoelectronic integrated package module and manufacturing the same

According to one embodiment, there is provided an optoelectronic integrated package module including a silicon interposer, an optical semiconductor element formed in the silicon interposer, and a semiconductor integrated circuit chip module including a first semiconductor integrated circuit chip including a logic circuit and mounted on a first principal surface and a second semiconductor integrated circuit chip having a second principal surface side mounted on the silicon interposer. The first and second semiconductor integrated circuit chips are electrically connected to each other via the via interconnections formed inside the second semiconductor integrated circuit chip from the first principal surface.

Optoelectronic integrated package module

According to one embodiment, there is provided an optoelectronic integrated package module including a silicon interposer that has an electrical interconnection and an optical waveguide, and formed on a silicon substrate, an optical semiconductor element formed in the silicon interposer, and electrically connected to the electrical interconnection and optically coupled to the optical waveguide, an electrical circuit element formed in the silicon interposer, and electrically connected to the optical semiconductor element, and a semiconductor integrated circuit chip mounted on the silicon interposer, and electrically connected to the electrical circuit element. The semiconductor integrated circuit chip transmits an electrical signal to the optical semiconductor element via the electrical circuit element or receives an electrical signal from the optical semiconductor element via the electrical circuit element..

Semiconductor device having silicon interposer on which semiconductor chip is mounted

Disclosed herein is a device that includes a silicon interposer having wiring lines on first and second wiring layers. The wiring lines includes first, second and third wiring lines provided on the first wiring layer and a fourth wiring line provided on the second wiring layer.



Silicon Interposer topics:
  • Silicon Interposer
  • Semiconductor
  • Integrated Circuit
  • Circuit Board
  • Semiconductor Substrate
  • Electronic Device


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    This listing is a sample listing of patent applications related to Silicon Interposer for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Silicon Interposer with additional patents listed. Browse our RSS directory or Search for other possible listings.


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