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Silicon Interposer

Silicon Interposer-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Carrier-less silicon interposer using photo patterned polymer as substrate
Invensas Corporation
October 12, 2017 - N°20170294321

A component, e. G., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° c., and a second element at the ...
Testing interposer method and apparatus
Texas Instruments Incorporated
August 24, 2017 - N°20170242069

The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.
Method of fabricating semiconductor package
Texas Instruments Incorporated
May 25, 2017 - N°20170148761

The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor ...
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Interposer with lattice construction and embedded conductive metal structures
International Business Machines Corporation
December 22, 2016 - N°20160372337

A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i. E., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a ...
Semiconductor package and mounting structure thereof
Murata Manufacturing Co., Ltd.
December 01, 2016 - N°20160351504

A semiconductor package includes an interposer, a semiconductor element installed on a first surface of the interposer, bumps formed on a second surface of the interposer, and a chip component installed on the second surface of the interposer. The interposer is a silicon interposer; the semiconductor element is flip-chip mounted on the first surface of the interposer; the chip component ...
Electronic package and fabrication method thereof
Siliconware Precision Industries Co., Ltd.
November 10, 2016 - N°20160329267

An electronic package is provided, which includes: a circuit structure having opposite first and second sides; at least an electronic element disposed on the first side of the circuit structure; an encapsulant formed on the first side of the circuit structure for encapsulating the electronic element; a dielectric layer formed on portions of the second side of the circuit structure; ...
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Silicon Interposer Patent Applications
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Semiconductor package with high routing density patch
Amkor Technology, Inc.
October 20, 2016 - N°20160307870

Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch ...
Silicon interposer sndwich structure for esd, emi, and emc shielding and protection
International Business Machines Corporation
August 11, 2016 - N°20160233190

A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The ...
Interposer with lattice construction and embedded conductive metal structures
International Business Machines Corporation
June 16, 2016 - N°20160172290

A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i. E., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a ...
Interposer with lattice construction and embedded conductive metal structures
International Business Machines Corporation
June 16, 2016 - N°20160172288

A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i. E., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a ...
Scalable 2.5d interface architecture
Altera Corporation
April 07, 2016 - N°20160098061

Systems and methods for interface block. The interface block includes input/output modules distributed along the interface block and a mid-stack module interspersed within the input/output modules. The input/output modules include at least one data module and at least one command module. At least one of the input/output modules is shared by an adjacent pair of channels. ...
Carrier-less silicon interposer
Invensas Corporation
March 17, 2016 - N°20160079090

An interposer has conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component includes a first element having a thermal expansion coefficient less than 10 ppm/° c., and an insulating second element, with a plurality of openings extending from the second side through ...
Testing interposer method and apparatus
Texas Instruments Incorporated
December 10, 2015 - N°20150355232

The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.
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Silicon Interposer Patent Applications
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  • + full patent PDF documents of Silicon Interposer-related inventions.
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Low latency, high bandwidth memory subsystem incorporating die-stacked dram
Oracle International Corporation
October 01, 2015 - N°20150279436

A memory subsystem incorporating a die-stacked dram (dsdram) is disclosed. In one embodiment, a system include a processor implemented on a silicon interposer of an integrated circuit (ic) package, a dsdram coupled to the processor, the dsdram implemented on the silicon interposer of the ic package, and a dram implemented separately from the ic package. The dsdram and the dram ...
Embedded die flip-chip package assembly
Oracle International Corporation
September 10, 2015 - N°20150255412

Embodiments of the present disclosure describe integrated circuit (ic) package assemblies and methods of fabricating ic package assemblies. These embodiments include dies embedded in embedding substrates to provide larger pitch interconnects to facilitate coupling to substrates or circuit boards through flip chip techniques. The embedding substrates may contain conductive pathways for coupling die contacts to larger pitch contacts located on ...
Testing interposer method and apparatus
Texas Instruments Incorporated
June 18, 2015 - N°20150168493

The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.
Carrier-less silicon interposer using photo patterned polymer as substrate
Invensas Corporation
June 04, 2015 - N°20150155230

A component, e. G., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° c., and a second element at the ...
Apparatus for dicing interposer assembly
Taiwan Semiconductor Manufacturing Company, Ltd.
May 28, 2015 - N°20150145133

Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a silicon interposer, a fixture mounted to the wafer carrier and comprising a layer of material to ...
Universal encapsulation substrate, encapsulation structure and encapsulation method
Taiwan Semiconductor Manufacturing Company, Ltd.
April 30, 2015 - N°20150115437

A universal packaging substrate, comprising a first substrate (102) and a silicon interposer (103), wherein, a plurality of bumps (106) are formed between the upper surface of the first substrate (102) and the lower surface of the silicon interposer (103) and electrically connect the upper surface of the first substrate (102) and the lower surface of the silicon interposer (103), and a plurality of wire bonding pads ...
Heterogeneous integration of memory and split-architecture processor
Texas Instruments Incorporated
April 23, 2015 - N°20150111318

A method for fabricating a semiconductor device provides a first chip having first terminals, a second chip having second terminals, and a third chip having third terminals. A first silicon interposer having first through silicon vias tsvs and a second silicon interposer having second tsvs is provided. The first tsvs are arrayed in a first, a second, and a third ...
Semiconductor package and method of fabricating the same
Siliconware Precision Industries Co., Ltd.
February 05, 2015 - N°20150035164

The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor ...
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