This page is updated frequently with new Shared Memory-related patent applications.
|Platform and software framework for data intensive applications in the cloud|
A system deploys visualization tools, business analytics software, and big data software in a multi-instance mode on a large, coherent shared memory many-core computing system. The single machine solution provides or high performance and scalability and may be implemented remotely as a large capacity server (i.e., in the cloud) or locally to a user.
Silicon Graphics International Corp.
|I/o bus shared memory system|
A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device.
Macronix International Co., Ltd.
|Work stealing in heterogeneous computing systems|
A work stealer apparatus includes a determination module. The determination module is to determine to steal work from a first hardware computation unit of a first type for a second hardware computation unit of a second type that is different than the first type.
|Authentication apparatus based on public key cryptosystem, mobile device having the same and authentication method|
An authentication apparatus, included in a device supporting a network communication, includes a certificate handler that receives a certificate of an opponent and parses or verifies the certificate of the opponent. Cryptographic primitives receive an authentication request of the opponent, generate a random number in response to the authentication request, generate a challenge corresponding to the random number, and verify a response of the opponent corresponding to the challenge.
Samsung Electronics Co., Ltd.
|Distributed graph database|
A distributed graph database that enables scaling and efficient processing is described. The distributed graph database can, for example, scale up to petabytes of data to enable transactional processing of graph data with low latency and low processing overhead.
Microsoft Technology Licensing, Llc
|Virtual node deployments of cluster-based applications|
Examples relate to deploying distributed applications using virtual nodes. In some examples, virtual nodes are created and are each assigned a core subset of a number of processing cores, an internet protocol (ip) address, and an in-memory file system configured to provide access to a portion of physically shared memory.
Hewlett Packard Enterprise Development Lp
|On-chip atomic transaction engine|
A hardware-assisted distributed memory system may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory regions may be made through a network of on-chip atomic transaction engine (ate) instances, one per core, over a private interconnect matrix that connects them together.
Oracle International Corporation
|Distributed lock-free rdma-based memory allocation and de-allocation|
An “rdma-based memory allocator” applies remote direct memory access (rdma) messaging to provide fast lock-free memory allocations and de-allocations for shared memory distributed across multiple servers in an rdma-based network. Alternately, in various implementations, the rdma-based memory allocator combines rdma messaging and remote procedure call (rpc) requests to provide fast lock-free memory allocations and de-allocations for shared memory distributed across multiple servers in an rdma-based network.
Microsoft Technology Licensing, Llc
A control apparatus, in a storage system, accesses a specific storage area in a shared memory by designating a fixed virtual address, even when a capacity of the shared memory in the storage system changes. A space of a physical address indicating a storage area in a plurality of memories in a self-control-subsystem of two control-subsystems and a space of a physical address indicating a storage area in the plurality of memories in the other-control-subsystem are associated with a space of a virtual address used by each of a processor and an input/output device in the self-control-subsystem.
|Qualified video delivery|
A video server is configured to provide streaming video to players of computer games over a computing network. The video server can provided video of different games to different players simultaneously.
Sony Interactive Entertainment America Llc
Using external memory for wireless wide area networks and wireless local area networks for power savings
Certain aspects of the present disclosure generally relate to wireless communications and, more particularly, to using an external memory for both a wireless wide area network (wwan) and a wireless local area network (wlan) for wlan power savings. An exemplary method includes obtaining messages (e.g., paging messages) via a receiver; reading, during a first wakeup period in which the apparatus is to monitor for messages in a first wireless local area network (wlan) while the receiver is powered on, state information for the first wlan from a shared memory also used to store state information for a wireless wide area network (wwan), and using the state information to configure the apparatus for communicating in the first wlan..
Parallel fieldbus network-based motor control system
According to an aspect of the present invention, there is provided a parallel fieldbus network-based motor control system including: one or more slave modules that control one or more motors and correspond to each of the one or more motors; and a master module that generates command data for controlling each of the one or more motors and transmits the generated command data to each of the one or more slave modules, wherein each of the one or more slave modules includes a basic processor and an auxiliary processor, the auxiliary processor acquires the command data from the master module via a basic network, and supports the acquired command data to be stored in a shared memory and transmitted to the basic processor or transmits the acquired command data to the basic processor via a local network, the basic processor controls the motor corresponding to the corresponding slave module in accordance with the command data acquired from the master module via the basic network, read from the shared memory, or transmitted via the local network or supports to control the motor, and supports result data executed in accordance with the command data to be stored in the shared memory and transmitted to the auxiliary processor or transmits the result data to the auxiliary processor via the local network, and when abnormality occurs in the basic network, the maser module provides the command data to the basic processor or the auxiliary processor via an auxiliary network or a wireless network, and the auxiliary processor provides the result data to the master module via the auxiliary network or the wireless network, or acquires command data for continuing to control the motor corresponding to the corresponding slave mode from the master module and supports the acquired command data to be stored in the shared memory and transmitted to the basic processor or transmits the acquired command data to the basic processor via the local network.. .
Center Of Human-centered Interaction For Coexistence
System and a dynamic shared memory hash table with notifications
A method and apparatus of a device that grows and/or shrinks a table that is shared between a writer and a plurality of readers is described. In an exemplary embodiment, a device receives an entry to be added to the shared table.
Arista Networks, Inc.
Compiler optimization to reduce the control flow divergence
In one embodiment a graphics processing system comprises a graphics processor having execution logic and shared memory and a shader compiler unit to compile a shader program for execution by the execution logic of the graphic processor, wherein the shader is to optimize the shader program during the compile, wherein to optimize the shader program includes to convert a divergent block of parallel instructions into a divergent block and a non-divergent block of instructions.. .
Assisted coherent shared memory
An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes.
Computing system management using shared memory
A system management command is stored in a management partition of a global memory by a first node of a multi-node computing system. The global memory is shared by each node of the multi-node computing system.
Hewlett Packard Enterprise Development Lp
Methods and apparatus to monitor media presentations
Methods, apparatus, systems and articles of manufacture to monitor media presentations are disclosed. An example method includes providing a software development kit (sdk) to an application developer.
The Nielsen Company (us), Llc
System and a shared memory hash table with notifications and reduced memory utilization
A method and apparatus of a device that includes a shared memory hash table that notifies one or more readers of changes to the shared memory hash table is described. In an exemplary embodiment, a device receives a key that corresponds to the value, where the key used to retrieve the value form the shared memory hash table and the shared memory hash table is written to by a writer and read from by a plurality of readers.
Arista Networks, Inc.
Enhanced advanced driver assistance system (adas) system on chip
A system on chip (soc) having an integrated circuit (ic) integrating into a single chip advance driver assistance systems (adas) processing unit(s), application processing unit(s), at least one memory storing adas code comprising adas computer instructions adapted to be executed on the adas processing unit(s) for processing vehicle sensor data and vm code for executing vm(s) on the application processing unit(s) and a hypervisor which manages an execution of at least one operation system of the vm(s) and an access to a processor shared memory of the adas processing unit(s) for acquiring an outcome of executing the adas computer instructions for the completion of an adas enhancing function by the execution of the vm(s) on the application processing unit(s).. .
Ionroad Technologies Ltd.
Wand: concurrent boxing system for all pointers with or without garbage collection
Boxed pointers are disclosed, for all pointers, for safe and sequential or parallel use. Since a pointer box can be arbitrarily large, it supports any fat pointer encoding possible.
Data collection system and method
This system is a data collection system collecting a robot operation-related data/signal from a robot controller. The data collection system includes a data collection condition setting unit setting a collection condition of the robot operation-related data/signal from the robot controller and a data storage unit storing the robot operation-related data/signal collected from the robot controller.
Kawasaki Jukogyo Kabushiki Kaisha
Cpu/gpu synchronization mechanism
A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory..
Read/write split database query routing
Systems and methods for improving database system performance are described. In one embodiment, a database system includes a database application cluster including at least one read-write node and a plurality of read nodes, a shared memory, and a multiplexer coupled to the database application cluster and shared memory.
Query result caching for database environments
Systems and methods for improving database system performance are described. In one embodiment, a database system includes a master database, a cache system, a shared memory, and a multiplexer coupled to the master database, cache system, and shared memory.
Replica database query routing for database environments
Systems and methods for improving database system performance are described. In one embodiment, a database system includes a master database, a replica database, a shared memory, and a multiplexer coupled to the master database, replica database, and shared memory.
Distributing computing system implementing a non-speculative hardware transactional memory and a using same for distributed computing
A distributed computation system comprising computation units and memory shared between computation units, comprises a hardware module for detecting conflicts of access of computation units to shared memory; each hardware module for detecting conflicts configured to: store a probabilistic data structure, indicative of the addresses of shared memory involved in the current transactions; receive at least one message indicative of request for access, by one computation unit to an address of shared memory; determine, from a probabilistic data structure, whether the address is already involved in a current transaction, and transmit a message indicating presence or absence of access conflicts; receive a message indicative or confirmative of reservation or releasing of an address of shared memory, and update the probabilistic data structure for the reserved addresses and the released addresses to be considered, as being/not being involved in a current transaction. A method for using the system is provided..
Commissariat A L'energie Atomique Et Aux Energies Alternatives
Shared memory controller and using same
A controller for a shared memory is disclosed. The controller comprises a transaction scanner configured to scan-in a plurality of transactions to access the shared memory and to divide the transactions into beat-level memory access commands.
Futurewei Technologies, Inc.
Low density parity check decoding method performing on general graphic processing unit and decoding appratus
A low density parity check (ldpc) decoding method and a decoding apparatus are provided. The method includes following steps.
Winbond Electronics Corp.
Communication system and communication method
A communication system includes a plurality of communication devices that transmits shared data in turn through wireless communication. Each of the communication devices includes a shared memory, a transmission processor, a reception processor, and a data comparator.
Kabushiki Kaisha Toshiba
Lock-free dual queue with condition synchronization and time-outs
Systems and methods for operating software data structures are provided. In one embodiment, lock-free dual queues with conditional synchronization and time-outs are described.
Level 3 Communications, Llc
Shared memory architecture autoupdater
A method of updating a bootloader includes a slave controller that includes a central processing unit in communication with non-volatile memory having a shared memory architecture. The shared memory architecture including a non-volatile application memory block having application code and a non-volatile launcher memory block having bootloader code for initiating the slave controller.
Remote direct memory access (rdma) high performance producer-consumer message processing
A method, system and computer program product for remote direct memory access (rdma) optimized producer-consumer message processing in a messaging hub is provided. The method includes initializing a shared memory region in memory of a host server hosting operation of a messaging hub.
International Business Machines Corporation
Sharing memory and i/o services between nodes
A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource.
Packet copy management for service chain processing within virtual processing systems
Systems and methods are disclosed to provide packet copy management for service chain processing within virtual processing systems. A packet manager virtual machine (vm) controls access to shared memory that stores packet data for packets being processed by service chain vms operating within a virtual processing environment.
Systems and methods for secure multi-tenant data storage
Systems and methods are provided for transmitting data for secure storage. For each of two or more data sets, a plurality of shares are generated containing a distribution of data from an encrypted version of the data set.
Security First Corp.
Hybrid heterogeneous host system, resource configuration method and task scheduling method
A hybrid heterogeneous host system, a resource configuration method and a task scheduling method are disclosed. The system includes: a basic unit, including: computing resource nodes, storage resource nodes and input/output i/o resource nodes; wherein multiple basic units are connected via a high-speed internetwork; and a software definition unit, configured to: when system resources are increased or reduced, extend the address space of an increased hardware resource to a current address space, or delete an address space of a reduced hardware resource from the current address space, and update a system resource view.
Inspur (beijing) Electronic Information Indusrty Co., Ltd.
Remote-direct-memory-access-based virtual machine live migration
The current document is directed to methods and systems for moving executing virtual machines between host systems in a virtual data center. In described implementations, remote-direct memory access is used for transferring memory contents and, in certain implementations, additional data between the host systems to facilitate live migration of virtual machines.
Rack scale architecture (rsa) and shared memory controller (smc) techniques of fast zeroing
Methods and apparatus related to rack scale architecture (rsa) and/or shared memory controller (smc) techniques of fast zeroing are described. In one embodiment, a storage device stores meta data corresponding to a portion of a non-volatile memory.
Adaptive private network asynchronous distributed shared memory services
A highly predicable quality shared distributed memory process is achieved using less than predicable public and private internet protocol networks as the means for communications within the processing interconnect. An adaptive private network (apn) service provides the ability for the distributed memory process to communicate data via an apn conduit service, to use high throughput paths by bandwidth allocation to higher quality paths avoiding lower quality paths, to deliver reliability via fast retransmissions on single packet loss detection, to deliver reliability and timely communication through redundancy transmissions via duplicate transmissions on high a best path and on a most independent path from the best path, to lower latency via high resolution clock synchronized path monitoring and high latency path avoidance, to monitor packet loss and provide loss prone path avoidance, and to avoid congestion by use of high resolution clock synchronized enabled congestion monitoring and avoidance..
Talari Networks Incorporated
System and removing data from processor caches in a distributed multi-processor computer system
A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor interface (24) receives the flush request and performs a snoop operation to determine whether the data is maintained in a one of the local processors (601) and whether the data has been modified.
Silicon Graphics International Corp.
Parallel caching architecture and methods for block-based data processing
A multi-processor computer system with shared memory resources includes a first plurality of sensors configured to acquire inertial and positional data related to a mobile platform. The system further includes a first plurality of co-processors having a hardware logic configured to control the acquisition of the inertial and positional data and configured to analyze the acquired data.
Methods and signal flow graph pipelining in an array processing unit that reduces storage of temporary variables
A system for pipelining signal flow graphs by a plurality of shared memory processors organized in a 3d physical arrangement with the memory overlaid on the processor nodes that reduces storage of temporary variables. A group function formed by two or more instructions to specify two or more parts of the group function.
Idle mode operations in multi-subscriber identity module (sim) mobile communication devices
Various embodiments include methods implemented on a mobile communication device for sharing network information among subscriptions when both a first subscription and a second subscription are in an idle mode. The methods may include determining whether the first subscription and the second subscription share a network operator and are camped on a same base station.
Apparatuses and methods for providing data consistency messaging for shared memory systems
Apparatuses and methods for providing data consistency messaging for shared memory systems are disclosed herein. An example apparatus may include a producer processor unit configured to provide a memory access packet and a first notification packet.
Magnum Semiconductor, Inc.
Exit-less host memory locking in a virtualized environment
Embodiments of the present disclosure enable exit-less host memory locking in a virtualized environment. An example method comprises protecting, by a processing device of a host computer system, a memory page from being accessed by a guest operating system of a virtual machine running on the host computer system.
Red Hat Israel, Ltd.
Method for dynamically storing a flash translation layer of a solid state disk module
A shared memory is initially set in the solid state module. A command for accessing information is received.
Quanta Storage Inc.
Cache coherence in multi-compute-engine systems
Methods and systems for providing cache coherence in multi-compute-engine systems are described herein. In on example, concise cache coherency directory (cdir) for providing cache coherence in the multi-compute-engine systems is described.
Hewlett Packard Enterprise Development Lp
Dynamic protection of shared memory used by output queues in a network device
A network switch includes a buffer to store network packets linked to queues to feed the packets to output ports of the switch associated with the queues. The buffer is shared dynamically among multiple traffic pools.
Cisco Technology, Inc.
Dynamic protection of shared memory and packet descriptors used by output queues in a network device
A network switch includes a buffer to store network packets and packet descriptors (pds) used to link the packets into queues for output ports. The buffer and pds are shared among the multiple traffic pools.
Cisco Technology, Inc.
Method and system for maintaining release consistency in shared memory programming
A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in response to a page fault, initiating a transfer, from one processing unit to another, of data associated with more than one but less than all of the pages of shared memory.. .
Computing architecture with peripherals
A shared memory computing architecture (300) has m interconnect masters (350, 351, 352, 353, 354), one interconnect target (370), and a timeslot based interconnect (319). The interconnect (319) has a unidirectional timeslot based interconnect (320) to transport memory transfer requests with t timeslots and a unidirectional timeslot based interconnect (340) to transport memory transfer responses with r timeslots.
Synaptic Laboratories Limited