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This page is updated frequently with new Shared Memory-related patent applications. Subscribe to the Shared Memory RSS feed to automatically get the update: related Shared RSS feeds. RSS updates for this page: Shared Memory RSS RSS


Mixed shared/non-shared memory transport for virtual machines

Rfid frequency translator

Computer system having voice-control function and voice-control method

Date/App# patent app List of recent Shared Memory-related patents
08/21/14
20140237186
 Filtering snoop traffic in a multiprocessor computing system patent thumbnailFiltering snoop traffic in a multiprocessor computing system
Filtering snoop traffic in a multiprocessor computing system, each processor in the multiprocessor computing system coupled to a high level cache and a low level cache, the including: receiving a snoop message that identifies an address in shared memory targeted by a write operation; identifying a set in the high level cache that maps to the address in shared memory; determining whether the high level cache includes an entry associated with the address in shared memory; responsive to determining that the high level cache does not include an entry corresponding to the address in shared memory: determining whether the set in the high level cache has been bypassed by an entry in the low level cache; and responsive to determining that the set in the high level cache has not been bypassed by an entry in the low level cache, discarding the snoop message.. .
08/14/14
20140229686
 Mixed shared/non-shared memory transport for virtual machines patent thumbnailMixed shared/non-shared memory transport for virtual machines
Methods, systems and computer program products are provided for mixed shared/non-shared memory transport in virtual machines. A computer-implemented method may include providing a shared memory area writeable by a first virtual processor and a second virtual processor that are runnable on a host cpu, retrieving the information stored in the shared memory area by the first virtual processor when the first virtual processor stops running on the host cpu and before the second virtual processor runs on the host cpu, and storing the retrieved information from the shared memory area in a non-shared memory..
08/14/14
20140229246
 Rfid frequency translator patent thumbnailRfid frequency translator
An rfid-based system and method is disclosed which translates discrepant frequencies and protocols, for seamless communication across disparate devices. Any legal frequency is accepted, information transmitted in that frequency is translated then saved in allocated memory accessible to the other side, which receives and processes the information with an appropriate reader-equipped device such as cellphone, handheld device, or computer.
08/07/14
20140223157
 Computer system having voice-control function and voice-control method patent thumbnailComputer system having voice-control function and voice-control method
The invention discloses a computer system having voice-control function. The computer system includes a voice-recognition module, a shared memory, a microcontroller, a power-management module and a central processing unit.
07/24/14
20140207900
 Conversion tracking for installation of applications on mobile devices patent thumbnailConversion tracking for installation of applications on mobile devices
An application executing on a mobile device, such as an application associated with a social networking system provides a link to install a third-party application. The link may be presented in an advertisement, and the link is used to retrieve data comprising a client application for execution by the mobile device.
07/17/14
20140201471
 Arbitrating memory accesses via a shared memory fabric patent thumbnailArbitrating memory accesses via a shared memory fabric
In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values.
07/17/14
20140201451
 Method, apparatus and computer programs providing cluster-wide page management patent thumbnailMethod, apparatus and computer programs providing cluster-wide page management
A data processing system includes a plurality of virtual machines each having associated memory pages; a shared memory page cache that is accessible by each of the plurality of virtual machines; and a global hash map that is accessible by each of the plurality of virtual machines. The data processing system is configured such that, for a particular memory page stored in the shared memory page cache that is associated with two or more of the plurality of virtual machines, there is a single key stored in the global hash map that identifies at least a storage location in the shared memory page cache of the particular memory page.
07/17/14
20140201302
 Method, apparatus and computer programs providing cluster-wide page management patent thumbnailMethod, apparatus and computer programs providing cluster-wide page management
An exemplary method in accordance with embodiments of this invention includes, at a virtual machine that forms a part of a cluster of virtual machines, computing a key for an instance of a memory page that is to be swapped out to a shared memory cache that is accessible by all virtual machines of the cluster of virtual machines; determining if the computed key is already present in a global hash map that is accessible by all virtual machines of the cluster of virtual machines; and only if it is determined that the computed key is not already present in the global hash map, storing the computed key in the global hash map and the instance of the memory page in the shared memory cache.. .
07/17/14
20140198110
 Reducing the number of sequential operations in an application to be performed on a shared memory cell patent thumbnailReducing the number of sequential operations in an application to be performed on a shared memory cell
Methods and apparatuses to reduce the number of sequential operations such as atomic operations in an application to be performed on a shared memory cell may be provided. A translation unit can detect in the application multiple atomic operations to be performed on the same memory and replaces the multiple atomic operations with an equivalent single atomic operation.
07/10/14
20140196004
 Software interface for a hardware device patent thumbnailSoftware interface for a hardware device
Automatically generating code used with device drivers for interfacing with hardware. The method includes receiving a machine readable description of a hardware device, including at least one of hardware registers or shared memory structures of the hardware device.
07/10/14
20140195766
Shared and managed memory unified access
A managed memory in which multiple computing entities each have a corresponding entity-specific portion that is subject to garbage collection. An immutable buffer is located outside of managed memory.
07/10/14
20140195741
Type casting in a managed code system
Type casting in a managed code system is described. The managed code system includes managed memory as well as shared memory located outside of the managed memory.
07/03/14
20140189260
Approach for context switching of lock-bit protected memory
A streaming multiprocessor in a parallel processing subsystem processes atomic operations for multiple threads in a multi-threaded architecture. The streaming multiprocessor receives a request from a thread in a thread group to acquire access to a memory location in a lock-protected shared memory, and determines whether a address lock in a plurality of address locks is asserted, where the address lock is associated the memory location.
07/03/14
20140189256
Processor with memory race recorder to record thread interleavings in multi-threaded software
A processor includes a first core to execute a first software thread, a second core to execute a second software thread, and shared memory access monitoring and recording logic. The logic includes memory access monitor logic to monitor accesses to memory by the first thread, record memory addresses of the monitored accesses, and detect data races involving the recorded memory addresses with other threads.
07/03/14
20140189039
System, method and computer readable medium for offloaded computation of distributed application protocols within a cluster of data processing nodes
A data processing node includes a management environment, an application environment, and a shared memory segment (sms). The management environment includes at least one management services daemon (msd) running on one or more dedicated management processors thereof.
07/03/14
20140185368
Method and apparatus for storing data
A memory system (1) comprising a control logic (2) adapted to receive a number n of write requests (wrs) from input ports and to receive a read request (rr) from an output port within a clock cycle of a clock signal (clk) applied to said memory system (1), wherein n is a natural number; and n+1 memory banks (4) of a shared memory (3) adapted to store data, wherein the control logic (2) is adapted to control a memory bank occupancy level mbol of each memory bank (4) such that the differences between memory bank occupancy levels mbols of the memory banks (4) are minimized. .
06/26/14
20140181422
Protocol engine for processing data in a wireless transmit/receive unit
A protocol engine (pe) for processing data within a protocol stack in a wireless transmit/receive unit (wtru) is disclosed. The protocol stack executes decision and control operations.
06/26/14
20140180662
Radio frequency communication simulation
A computer software tool comprises a simulated radio frequency transmitter device (6), a simulated radio frequency receiver device (6′) and a shared memory resource (10). The shared memory resource (10) is arranged to receive messages from the simulated transmitter (8) and to pass said messages to the simulated receiver (8′) wherein said messages are in a format understandable by software running on both the simulated radio frequency transmitter device (6) and the simulated radio frequency receiver device (6′)..
06/26/14
20140177470
Memory sharing in a network device
A network device includes processor devices configured to perform packet processing functions, and a shared memory system including multiple memory blocks. A memory connectivity network couples the processor devices to the shared memory system.
06/26/14
20140176587
Electronic system and method for selectively allowing access to a shared memory
An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder.
06/19/14
20140169472
Motion estimation engine for video encoding
The motion estimation engine has a multi-threaded structure and comprises a preprocessor for rough motion estimation of motion vectors and in-loop motion estimator for creating a coding tree unit, as well as a shared memory for interaction of the pre-processor with the in-loop motion estimator. The coding tree unit is formed by merging neighboring partitions of coding units using a list of best mv candidates..
06/12/14
20140164857
Testing disk drives shared by multiple processors in a supercomputer complex
According to one embodiment of the present disclosure, an approach is provided in which an interface node selects a logical block address that corresponds to a contiguous memory location located on a storage device that is accessible by multiple interface nodes. The interface node retrieves a logical block address status indicator from a shared memory area and determines, based upon the logical block status indicator, whether the logical block address is utilized by a different interface node.
06/12/14
20140164718
Methods and apparatus for sharing memory between multiple processes of a virtual machine
Methods and apparatus for sharing memory between multiple processes of a virtual machine are disclosed. A hypervisor associates a plurality of guest user memory regions with a first domain and assigns each associated user process an address space identifier to protect the different user memory regions from the different user processes.
06/12/14
20140164207
Electronic trading platform and method thereof
An electronic trading platform performs trading of one or more types of financial instruments and includes at least one cloud providing at least one independent trading environment executed by a server. The at least one cloud includes a plurality of instances of an express interface application executed by the server and configured to receive interests in the financial instruments.
06/05/14
20140156938
Cache region concept
A method to store objects in a memory cache is disclosed. A request is received from an application to store an object in a memory cache associated with the application.
06/05/14
20140153826
System for histogram computation
A system and method includes reception of a first image data value of a digital image, determination of a first index based on the first image data value, determination of a value stored in a first array of a first shared memory at the first index, and determination of whether the value stored in the first array of the first shared memory at the first index is equal to the first image data value. If the value stored in the first array of the first shared memory at the first index is equal to the first image data value, 1 is added to a count value stored in a second array of the first shared memory at the first index.
05/29/14
20140149981
Sharing memory between virtual appliances
A computing device executing a virtual machine and a hypervisor that manages the virtual machine receives a data packet that is addressed to the virtual machine. The computing device writes the data packet to a buffer in a shared memory.
05/29/14
20140149718
Instruction and logic to provide pushing buffer copy and store functionality
Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core.
05/29/14
20140149703
Contention blocking buffer
In response to a processor receiving data associated with a shared memory location, a contention blocking buffer stores a memory address of the shared memory location. In response to a probe seeking to take ownership of the shared memory location, the contention blocking buffer determines if the memory address indicated by the probe is stored at the contention blocking buffer.
05/29/14
20140149690
Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect
This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port.
05/29/14
20140149223
Targeted advertisements in mobile applications
A social networking system enables targeted advertising to its users on mobile devices, either directly in third-party applications or via an ad exchange. An application on the mobile device associated with the social networking system stores user identifying information in a shared memory location on the user's mobile device.
05/22/14
20140143486
Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
The msmc (multicore shared memory controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or dma, and the emif (external memory interface) in a multicore soc. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters.
05/22/14
20140143372
System and method of constructing a memory-based interconnect between multiple partitions
The shared memory interconnect system provides an improved method for efficiently and dynamically sharing resources between two or more guest partitions. The system also provides a method to amend the parameters of the shared resources without resetting all guest partitions.
05/22/14
20140143368
Distributed symmetric multiprocessing computing architecture
Example embodiments of the present invention includes systems and methods for implementing a scalable symmetric multiprocessing (shared memory) computer architecture using a network of homogeneous multi-core servers. The level of processor and memory performance achieved is suitable for running applications that currently require cache coherent shared memory mainframes and supercomputers.
05/15/14
20140132611
System and method for data transmission
The present invention discloses a system and a method for data transmission. The system includes: a plurality of graphics processing units; a global shared memory for storing data transmitted among the plurality of graphics processing units; an arbitration circuit module, which is coupled to each of the plurality of graphics processing units and the global shared memory and configured to arbitrate an access request to the global shared memory from respective graphics processing units to avoid an access conflict among the plurality of graphics processing units.
05/08/14
20140130021
System and method for translating program functions for correct handling of local-scope variables and computing system incorporating the same
A system and method of translating functions of a program. In one embodiment, the system includes: (1) a local-scope variable identifier operable to identify local-scope variables employed in the at least some of the functions as being either thread-shared local-scope variables or thread-private local-scope variables and (2) a function translator associated with the local-scope variable identifier and operable to translate the at least some of the functions to cause thread-shared memory to be employed to store the thread-shared local-scope variables and thread-private memory to be employed to store the thread-private local-scope variables..
05/08/14
20140129783
System and method for allocating memory of differing properties to shared data objects
A system and method for allocating shared memory of differing properties to shared data objects and a hybrid stack data structure. In one embodiment, the system includes: (1) a hybrid stack creator configured to create, in the shared memory, a hybrid stack data structure having a lower portion having a more favorable property and a higher portion having a less favorable property and (2) a data object allocator associated with the hybrid stack creator and configured to allocate storage for shared data object in the lower portion if the lower portion has a sufficient remaining capacity to contain the shared data object and alternatively allocate storage for the shared data object in the higher portion if the lower portion has an insufficient remaining capacity to contain the shared data object..
05/01/14
20140122934
Data synchronization method and apparatus
Embodiments of the present invention provide a data synchronization method and apparatus. The method includes: scanning a code to capture a synchronization instruction; replacing the captured synchronization instruction with a trap instruction; and when the code runs to the trap instruction, trapping a code execution right into a distributed shared memory (dsm) unit, where the dsm unit implements a concurrent multi-write protocol, but implements a single-write protocol when executing the synchronization instruction, thereby supporting the concurrent multi-write protocol and solving the synchronization problem caused by the concurrent multi-write protocol..
05/01/14
20140118541
Transcoding mixing and distribution system and method for a video security system
A system and method for transcoding and mixing of video data in a security video distribution system for a video security system in response to selection of video data. User devices such as mobile user devices can select displayed video data streams sent from the video security system and create new views of the selected video data streams without the prior steps of configuring and pushing new views from a server within the system.
04/24/14
20140115276
Intraprocedural privatization for shared array references within partitioned global address space (pgas) languages
Partitioned global address space (pgas) programming language source code is retrieved by an executed pgas compiler. At least one shared memory array access indexed by an affine expression that includes a distinct thread identifier that is constant and different for each of a group of program execution threads targeted to execute the pgas source code is identified within the pgas source code.
04/24/14
20140115273
Distributed data return buffer for coherence system with speculative address support
The msmc (multicore shared memory controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or dma, and the emif (external memory interface)in a multicore soc. Each processor has an associated return buffer allowing out of order responses of memory read data and cache snoop responses to ensure maximum bandwidth at the endpoints, and all endpoints receive status messages to simplify the return queue..
04/24/14
20140115271
Coherence controller slot architecture allowing zero latency write commit
This invention speeds operation for coherence writes to shared memory. This invention immediately commits to the memory endpoint coherence write data.
04/24/14
20140115267
Hazard detection and elimination for coherent endpoint allowing out-of-order execution
A coherence maintenance address queue tracks each memory access from receipt until the memory reports the access complete. The address of each new access is compared against the address of all entries in the queue.
04/24/14
20140115265
Optimum cache access scheme for multi endpoint atomic access in a multicore system
The msmc (multicore shared memory controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or dma, and the emif (external memory interface) in a multicore soc. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters.
04/17/14
20140108867
Dynamic taint analysis of multi-threaded programs
Disclosed is a dynamic taint analysis framework for multithreaded programs (dtam) that identifies a subset of program inputs and shared memory accesses that are relevant for issues related to concurrency. Computer implemented methods according to the framework generally involve the computer implemented steps of: applying independently a dynamic taint analysis to each of the multiple threads comprising a multi-threaded computer program; aggregating each independent result from the analysis for each of the multiple threads by consolidating effect of taint analysis in one or more possible re-orderings of observed shared memory accesses among threads; and outputting an indicia of the aggregated result as a set of relevant program inputs or a set of relevant shared memory accesses..
04/17/14
20140108758
Data processing method and data processing system
A data processing method that is executed by a first data processing apparatus included among plural data processing apparatuses, includes producing a copy of data, and restoration information that includes a first address of memory to which the copy of the data is stored; transmitting any one among the data and the copy of the data to a second data processing apparatus that is included among the data processing apparatuses; and storing the restoration information to shared memory that is memory of at least one data processing apparatus among the data processing apparatuses, and shared among the data processing apparatuses.. .
04/17/14
20140108736
System and method for removing data from processor caches in a distributed multi-processor computer system
A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor interface (24) receives the flush request and performs a snoop operation to determine whether the data is maintained in a one of the local processors (601) and whether the data has been modified.
04/17/14
20140108516
Client and a server and methods thereof for data management relating to shared data storage
A distributed shared data storage such as the distributed shared memory exemplified with the dsm master can seamlessly migrate (i.e. Move) in the runtime between different nodes without affecting the user perceived performance according to embodiments of the present invention.
04/10/14
20140101278
Speculative prefetching of remote data
A profiler may identify potentially-independent remote data accesses in a program. A remote data access is independent if value returned from said remote data access is not computed from another value returned from another remote data access appearing logically earlier in the program.
04/10/14
20140098291
Display device, display system, mobile information terminal, and display device control method
A display device includes: a second shared memory which is used for sharing data with a smartphone, and into which an identification information item of a process corresponding to a hardware key included in the smartphone is written from the smartphone; a second identification information receiving unit which receives the identification information item from the smartphone by reading the identification information item from the second shared memory; and a second identification information transmitting unit which transmits information indicating selection of the identification information item to the smartphone, by writing the information in the second shared memory.. .
04/03/14
20140096230
Method and system for sharing vpn connections between applications
A method for sharing a virtual private network (vpn) connection among applications is described herein. In an environment in which multiple applications exchange data through the use of the virtual file system, a vpn for a first application can be established, and it can be determined that the first application is deactivated.
04/03/14
20140095810
Memory sharing across distributed nodes
A method and apparatus are disclosed for enabling nodes in a distributed system to share one or more memory portions. A home node makes a portion of its main memory available for sharing, and one or more sharer nodes mirrors that shared portion of the home node's main memory in its own main memory.
04/03/14
20140092974
System and method for motion estimation for large-size block
A method and apparatus are disclosed for providing motion estimation (me) for large-size blocks of image data during image processing using small-size block processing logic. An embodiment method includes obtaining a large-size block for me processing and dividing the large-size block into a plurality of small-size blocks.
04/03/14
20140092743
Method and apparatus for reducing pool starvation in a shared memory switch
A switch includes a reserved pool of buffers in a shared memory. The reserved pool of buffers is reserved for exclusive use by an egress port.
03/27/14
20140089596
Read-copy update implementation for non-cache-coherent systems
A technique for implementing read-copy update in a shared-memory computing system having two or more processors operatively coupled to a shared memory and to associated incoherent caches that cache copies of data stored in the memory. According to example embodiments disclosed herein, cacheline information for data that has been rendered obsolete due to a data update being performed by one of the processors is recorded.
03/27/14
20140086262
Scalable egress partitioned shared memory architecture
Disclosed are various embodiments that provide an architecture of memory buffers for a network component configured to process packets. A network component may receive a packet, the packet being associated with a control structure and packet data, an input port set and an output port set.
03/27/14
20140085320
Efficient processing of access requests for a shared resource
A system and method for efficiently processing access requests for a shared resource. A computing system includes a shared memory accessed by multiple requestors.
03/20/14
20140082291
Speculative permission acquisition for shared memory
In a processor, a method for speculative permission acquisition for access to a shared memory. The method includes receiving a store from a processor core to modify a shared cache line, and in response to receiving the store, marking the cache line as speculative.
03/20/14
20140082241
Method and an apparatus for coherency control
The subject matter discloses a method for data coherency; the method comprising receiving an interrupt request for interrupting a cpu; wherein the interrupt request is from one of a plurality of modules; wherein the interrupt request notifying a writing instruction of a first data by the one of the plurality of modules to a shared memory; and wherein the shared memory is accessible to the plurality of modules through a shared bus; suspending the interrupt request; validating a completion of an execution of the writing instruction; wherein the validating is performed after the suspending; and resuming the interrupt request after the completion of the execution of the writing is validated, whereby to notify a to the cpu about the completion of the execution of the writing instruction.. .
03/13/14
20140075129
Systems and methods exchanging data between processors through concurrent shared memory
A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors..
03/13/14
20140075092
Simulating eeprom in virtual distributed switches
A virtual eeprom driver is simulated for a virtual switch. A write function may be written to a shared memory device and designated as a virtual eeprom driver.
03/13/14
20140075063
Smart device with no ap
A smart device with no ap includes: a central processing module for running an operation system and applications; a peripheral control module for connecting peripherals; and a message mechanism connected with the central processing module and the peripheral control module for transmitting messages therebetween. According to a preferred embodiment of the present invention, data transfer is provided by a shared memory of the two modules, and the messages simulate data exchanges in a usb transfer layer for connecting the peripherals to the central processing module as a usb compound device.
03/13/14
20140071140
Display pipe request aggregation
A system and method for efficiently scheduling memory access requests. A semiconductor chip includes a memory controller for controlling accesses to a shared memory and a display controller for processing frame data.
03/06/14
20140068201
Transactional memory proxy
Processors in a compute node offload transactional memory accesses addressing shared memory to a transactional memory agent. The transactional memory agent typically resides near the processors in a particular compute node.
02/27/14
20140059286
Memory access device for memory sharing among plurality of processors, and access method for same
Provided is a memory access device for a shared memory mechanism of main memory for a plurality of cpus. The present invention includes a plurality of cpus using memory as main memory, another function block using memory as a buffer, a cpu interface which controls access transfer from the plurality of cpus to memory, and a dram controller for performing arbitration of the access transfer to the memory.
02/20/14
20140053165
Configuration technique for an electronic control unit with intercommunicating applications
A technique is specified for configuring an electronic control unit having intercommunicating applications which have been arranged in various partitions and to which differing safety integrity levels have been assigned. According to one method aspect, the communications behaviour of the applications assigned to the differing partitions amongst themselves is analysed, in order to identify data-writing and data-reading applications that are not located in the same partition.
02/20/14
20140053163
Thread processing method and thread processing system
A thread processing method that is executed by a multi-core processor, includes supplying a command to execute a first thread to a first processor; judging a dependence relationship between the first thread and a second thread to be executed by a second processor; comparing a first threshold and a frequency of access of any one among shared memory and shared cache memory by the first thread; and changing a phase of a first operation clock of the first processor when the access frequency is greater than the first threshold and upon judging that no dependence relationship exists.. .
02/20/14
20140053162
Thread processing method and thread processing system
A thread processing method is executed by a specific apparatus included among a plurality of apparatuses, and includes assigning one thread among a plurality of threads to the apparatuses, respectively; acquiring first time information that indicates a time at which the specific apparatus receives an execution result of a corresponding thread from each of the apparatuses; and setting a priority level of an access right to access shared memory that is shared by the apparatuses and the specific apparatus, the setting being based on the first time information and second time information that indicates a time at which reception of execution results of the threads from the apparatuses ends.. .
02/20/14
20140052933
Write transaction management within a memory interconnect
A memory interconnect between transaction masters and a shared memory. A first snoop request is sent to other transaction masters to trigger them to invalidate any local copy of that data they may hold and for them to return any cached line of data corresponding to the write line of data that is dirty.
02/20/14
20140052930
Efficient trace capture buffer management
A system and method for efficiently storing traces of multiple components in an embedded system. A system-on-a-chip (soc) includes a trace unit for collecting and storing trace history, bus event statistics, or both.
02/20/14
20140052929
Programmable resources to track multiple buses
A system and method for efficiently monitoring traces of multiple components in an embedded system. A system-on-a-chip (soc) includes a trace unit for collecting and storing trace history, bus event statistics, or both.


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Shared Memory topics: Shared Memory, Electronic Device, Communications, Storage Device, Mobile Phone, Dictionary, Led Device, Radio Frequency Identification, Application Server, Data Structure, Data Formats, Cache Coherency, Permissions, Concurrent, Arrhythmia

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