|| List of recent Shader-related patents
|Dynamic load balancing apparatus and method for graphic processing unit (gpu)|
The gpu including at least one shader processor may assign a vertex shader task and a pixel shader task to the at least one shader processor.. .
|Compressing graphics data rendered on a primary computer for transmission to a remote computer|
One embodiment of the present invention sets forth a method for compressing via a pixel shader color information associated with a line of pixels. An intermediary representation of an uncompressed stream of color information is first generated that indicates, for each pixel, whether a previous adjacent pixel shares color information with the pixel.
|Patched shading in graphics processing|
Aspects of this disclosure relate to a process for rendering graphics that includes designating a hardware shading unit of a graphics processing unit (gpu) to perform first shading operations associated with a first shader stage of a rendering pipeline. The process also includes switching operational modes of the hardware shading unit upon completion of the first shading operations.
|Post tesellation edge cache|
In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed..
|Methods and apparatus for interactive debugging on a non-pre-emptible graphics processing unit|
Systems and methods are disclosed for performing interactive debugging of shader programs using a non-preemptible graphics processing unit (gpu). An iterative process is employed to repeatedly re-launch a workload for processing by the shader program on the gpu.
|Area-based dependency chain analysis of shaders and command stream|
A method and device are provided for performing tile based rendering. The method and device analyze past and current commands to determine when tiles are renderable independently of other tiles.
|Execution of graphics and non-graphics applications on a graphics processing unit|
The techniques described in this disclosure are directed to efficient parallel execution of graphics and non-graphics application on a graphics processing unit (gpu). The gpu may include a plurality of shader cores within a shader processor.
|Vectorization of shaders|
Intermediate representation (ir) code is received as compiled from a shader in the form of shader language source code. The input ir code is first analyzed during an analysis pass, during which operations, scopes, parts of scopes, and if-statement scopes are annotated for predication, mask usage, and branch protection and predication.
|Scalar optimizations for shaders|
Described herein are optimizations of thread loop intermediate representation (ir) code. One embodiment involves an algorithm that, based on data-flow analysis, computes sets of temporary variables that are loaded at the beginning of a thread loop and stored upon exit from a thread loop.
|Rasterization of compute shaders|
Described are compiler algorithms that partition a compute shader program into maximal-size regions, called thread-loops. The algorithms may remove original barrier-based synchronization yet the thus-transformed shader program remains semantically equivalent to the original shader program (i.e., the transformed shader program is correct).
|Systems and methods for graph rendering|
An exemplary method comprises receiving graph data, generating an edge draw command to draw a first and a second edge as a display object, buffering first and second node positions for first and second sprites, respectively, identifying shader information associated with application of shading of the first sprite and the second sprite, the shader information indicating a change of shade based on distance from a first position and a change of shade based on distance from a second position associated with the second sprite, generating a node draw command to draw at least the first and second sprites, generating a graph shading command to apply shading to at least a portion of the first sprite based and to apply shading to at least a portion of the second sprite based, and providing the edge draw command, node draw command, and graph shading command to a graph execution module.. .
|Accelerated texture lookups using texture coordinate derivatives|
Methods, systems, and devices are disclosed for preparing to prefetch memory in 3d graphical shader programs. Based on the memory addresses of texels from a texture map that were previously read, a memory address of a to-be-read texel is estimated by using a first-order derivative of the memory address with respect to pixel distance.
|Para-virtualized domain, hull, and geometry shaders|
The present invention extends to methods, systems, and computer program products for providing domain, hull, and geometry shaders in a para-virtualized environment. As such, a guest application executing in a child partition is enabled use a programmable gpu pipeline of a physical gpu.
|Para-virtualized high-performance computing and gdi acceleration|
The present invention extends to methods, systems, and computer program products for para-virtualized gpgpu computation and gdi acceleration. Some embodiments provide a compute shader to a guest application within a para-virtualized environment.
|Application-transparent resolution control by way of command stream interception|
A method for controlling image resolution in graphics systems at runtime is provided. In use, the stream of commands and shaders of the running application is intercepted and analyzed at run time.
|Packing multiple shader programs onto a graphics processor|
This disclosure describes techniques for packing multiple shader programs of a common shader program type onto a graphics processing unit (gpu). The techniques may include, for example, causing a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time.
|Accelerated compute tessellation by compact topological data structure|
A system, method, and computer program product are provided for tessellation using shaders. New graphics pipeline stages implemented by shaders are introduced, including an inner ring shader, an outer edge shader, and topologic shader, which work together with a domain shader and geometry shader to provide tessellated points and primitives.
|Off chip memory for distributed tessellation|
Embodiments include an apparatus, a computer readable medium and a method for distributing tessellations within an accelerated processing device (apd) including at least two compute units. Embodiments include processing a plurality of patches in a first compute unit using a hull shader to generate hull shader output data.
|Graphics processing unit with command processor|
Aspects of the disclosure relate to a method of controlling a graphics processing unit. In an example, the method includes receiving one or more tasks from a host processor, and scheduling, independently from the host processor, the one or more tasks to be selectively executed by a shader processor and one or more fixed function hardware units, wherein the shader processor is configured to execute a plurality of instructions in parallel, and the one or more fixed function hardware units are configured to render graphics data..
|Saving and restoring shader context state|
Provided is a method for processing a command in a computing system including an accelerated processing device (apd) having a command processor. The method includes executing an interrupt routine to save one or more contexts related to a first set of instructions on a shader core in response to an instruction to preempt processing of the first set of instructions..
|Policies for shader resource allocation in a shader core|
A method of determining priority within an accelerated processing device is provided. The accelerated processing device includes compute pipeline queues that are processed in accordance with predetermined criteria.
|System and method for creating motion blur|
An embedded, programmable motion blur system and method is described. Embodiments include receiving a plurality of vertices in a graphics processing unit (gpu), displacing at least one vertex, receiving a primitive defined by at least one of the displaced vertices, and generating a plurality of primitive samples from the primitive.
|Handling virtual-to-physical address translation failures|
A method tolerates virtual to physical address translation failures. A translation request is sent from a graphics processing device to a translation mechanism.
|Circular scratch shader|
A computer-implemented method for generating a circular scratch highlight. The method includes generating a plurality of texture planes, where each texture plane includes a plurality of copies of a scratch texture oriented in the same direction; generating a combined texture by combining the plurality of texture planes at different angles; applying the combined texture to a surface of an object; calculating a specular gradient vector based on a light vector and a reflectance vector, wherein the specular gradient vector points in a gradient direction of a specular highlight; and generating the circular scratch highlight by assigning, for each of a plurality of points on the surface of the object, a separate weight value corresponding to each texture plane in the combined texture based on how closely an orientation of the texture plane at the point corresponds to a scratch vector that is perpendicular to the specular gradient vector..
|Methods of and apparatus for processing computer graphics|
When carrying out a second, higher level of anti-aliasing such as 8× msaa, in a graphics processing pipeline 1 configured to “natively” support a first level of anti-aliasing, such as 4× msaa, the rasterisation stage 3, early z (depth) and stencil test stage 4, late z (depth) and stencil test stage 7, blending stage 9, and downsampling and writeback (multisample resolve) stage 11 of the graphics processing pipeline 1 process each graphics fragment or pixel that they receive for processing in plural processing passes, each such processing pass processing a sub-set of the sampling points that the fragment represents, but the fragment shader 6 is configured to process each graphics fragment in a processing pass that processes all the sampling points that the fragment represents in parallel, so as to ensure compliance with the desired higher level of multisampled anti-aliasing.. .
|Saving and restoring non-shader state using a command processor|
Provided is a system including a command processor configured for interrupting processing of a first set of instructions executing within a shader core.. .
|Interception of graphics api calls for optimization of rendering|
A method, system, and computer-readable storage medium are disclosed for graphics application programming interface (api) interception. In one embodiment, one or more function calls to a graphics api may be received.
|Profiling ray tracing renderers|
A profiler for a ray tracing renderer interfaces with the renderer to collect rendering information, such as ray definition information, a pixel origin, objects hit, shader invocation, and related rays. In an interface, an artist views a simplified 3-d scene model and a rendered 2-d image.
|Image processing device|
The present invention intends to provide an image processing apparatus that can process geometrical primitives rapidly and with restrained memory consumption. A sequence of vertex data of a primitive sequence is stored in an index buffer, and size data of the primitive is stored in the head of the sequence.
|Filtering method and apparatus for anti-aliasing|
A filtering method and apparatus for anti-aliasing takes advantage of improved existing hardware by using as input the data stored in the multisampling anti-aliasing (msaa) buffers after rendering. The standard hardware box-filter is then replaced with a more intelligent resolve implemented using shader programs.
|Leveraging graphics processors to optimize rendering 2-d objects|
Methods and computer-readable media for displaying two-dimensional objects on a display device are disclosed. Rendering requests are received from an application to render two-dimensionally modeled graphics to a display device.
|Sun shader apparatus|
A sun shading apparatus includes a supporting frame, a shading frame and a shading fabric. The supporting frame includes a first and a second leg frame, and a supporting bar extended between the first and the second leg frames, while the second leg frame has a third and a fourth mounting slot.
|Customized image filters|
An interactive development environment enables a user to create a customized image filter through a user interface that provides the developer with a capability to create a directed acyclic graph representing the mathematical operations and values that generate a customized visual effect. During development of the customized image filter, a visual shader designer engine may execute the operations and values associated with each node in a prescribed order and display the rendered outcome in the render view area of each node.
|Systems and methods for rendering 2d grid data|
Systems and methods for rendering 2d grids using texture mapping and fragment shaders.. .
|Visual shader designer|
An integrated development environment includes a visual shader designer engine that enables a user to create a pixel shader embodied as a directed acyclic graph. The directed acyclic graph contains nodes, where each node is associated with an operation that is used to generate a color characteristic of a final rendered model.
|Graphics processing method and apparatus using post fragment shader|
Provided is a graphics processing method and apparatus using a post fragment shader. A rendering pipeline of the graphics processing apparatus may include a fragment shader that operates before a raster operator, and a post fragment shader that operates after the raster operator.
|Material trouble shooter|
A materials trouble shooter is provided for use with 3d models in computer graphics. An error texture is displayed that is distinguishable from textures without errors.
|Electronic sun shader for perimeter boards|
Send the adjusted content to said display controller.. .
|Time slice processing of tessellation and geometry shaders|
One embodiment of the present invention sets forth a technique for redistributing geometric primitives generated by tessellation and geometry shaders for processing by multiple graphics pipelines. Geometric primitives that are generated in a first processing cycle are collected and redistributed more evenly and in smaller tasks to the multiple graphics pipelines for vertex processing in a second processing cycle.
|Camera projection meshes|
A 3d rendering method is proposed to increase the performance when projecting and compositing multiple images or video sequences from real-world cameras on top of a precise 3d model of the real world. Unlike previous methods that relied on shadow-mapping and that were limited in performance due to the need to re-render the complex scene multiple times per frame, the proposed method uses, for each camera, one camera projection mesh (“cpm”) of fixed and limited complexity per camera.
|Synchronization of shader operation|
The example techniques described in this disclosure may be directed to synchronization between producer shaders and consumer shaders. For example, a graphics processing unit (gpu) may execute a producer shader to produce graphics data.
|Area-based rasterization techniques for a graphics processing system|
This disclosure describes area-based rasterization techniques that can improve the performance of a graphics processor. The techniques may include selecting a rasterization mode for a graphics primitive from a set of at least two candidate rasterization modes based on a metric indicative of an area of the graphics primitive.