This page is updated frequently with new Semiconductors-related patent applications.
|Simple approach for preparing post-treatment-free solution processed non-stoichiometric niox nanoparticles as conductive hole transport materials|
High-quality non-stoichiometric niox nanoparticles are synthesized by a facile chemical precipitation method. The niox film can function as an effective p-type semiconductor or hole transport layer (htl) without any post-treatments, while offering wide temperature applicability from room-temperature to 150° c.
The University Of Hong Kong
|Wind direction meter, wind direction/flow meter, and movement direction meter|
A wind direction meter has the following plurality of sensors and a control unit. Each sensor has a first surface and has first and second interlayer connection members made of different metals or semiconductors.
|Photosensitive resin composition, resist laminate, cured product of photosensitive resin composition, and cured product of resist laminate (11)|
The purpose of the present invention is to provide: a resin composition, a cured product of which has extremely low residual stress and exhibits excellent adhesion to a metal substrate such as a pt, lt or ta substrate after a wet heat test in the fields of semiconductors and mems/micromachine applications; a laminate of this resin composition; and a cured product of this resin composition or the laminate. The present invention is a photosensitive resin composition which contains an epoxy resin (a), a compound having a phenolic hydroxyl group (b) and a cationic photopolymerization initiator (c), and wherein: the epoxy resin (a) has a weighted average epoxy equivalent weight of 300 g/eq.
Nippon Kayaku Kabushiki Kaisha
|Two-dimensional heterojunction interlayer tunneling field effect transistors|
A two-dimensional (2d) heterojunction interlayer tunneling field effect transistor (thin-tfet) allows for particle tunneling in a vertical stack comprising monolayers of two-dimensional semiconductors separated by an interlayer. In some examples, the two 2d materials may be misaligned so as to influence the magnitude of the tunneling current, but have a modest impact on gate voltage dependence.
University Of Notre Dame Du Lac
|Polymeric semiconductors and related devices|
The present teachings relate to new semiconducting polymers including an optionally substituted naphtho[1,2-d:5,6-d]bis[1,2,3]thiadiazole moiety, an optionally substituted naphtho[2,1-d:6,5-d]bis[1,2,3]thiadiazole moiety, or a chalcogen analog thereof. The present polymers can be used to prepare thin film semiconductor components which can be incorporated into various electronic, optical, and optoelectronic devices..
|Circuit for balancing capacitor voltages at capacitors in a dc circuit|
A circuit for balancing capacitor voltages at capacitors in a dc circuit includes a first circuit path having first and second capacitors connected in series between first and second potentials of a dc voltage of the dc circuit, with a first center tap arranged between the first and second capacitors. A second circuit path includes first and second switchable semiconductors and first and second balancing elements which are connected in series between the first and second potentials.
The invention relates to fullerene derivatives of formula i, to mixtures and formulations containing them, to the use of the fullerene derivatives, mixtures and formulations as organic semiconductors in, or for the preparation of electronic devices, especially organic photovoltaic (opv) devices and organic photodetectors (opd), and to electronic devices comprising, or being prepared from, these fullerene derivatives, mixtures or formulations.. .
|Iii-nitride semiconductors with recess regions and methods of manufacture|
A multi-layer semiconductor structure is disclosed for use in iii-nitride semiconductor devices, including a channel layer comprising a first iii-nitride material, a barrier layer comprising a second iii-nitride material, a pair of ohmic electrodes disposed in ohmic recesses etched into the barrier layer, a gate electrode disposed in a gate recess etched into the barrier layer, and a filler element. The gate electrode is stepped to form a bottom stem and at least one bottom step within the gate recess.
Cambridge Electronics, Inc.
|Temperature compensation of fabricated semiconductors|
Semiconductor devices and methods are described wherein temperature dependence of leakage current in at least one pathway of a device is compensated by a resistor in the device. Control of temperature dependent leakage current is particularly useful for silicon nitride devices and for circuits such as cascode circuits.
Sanken Electric Co., Ltd.
|Fused bis-aryl fullerene derivatives|
The invention relates to novel fullerene derivatives, to methods for their preparation and educts or intermediates used therein, to mixtures and formulations containing them, to the use of the fullerene derivatives, mixtures and formulations as organic semiconductors in, or for the preparation of organic electronic (oe) devices, especially organic photovoltaic (opv) devices and organic photodetectors (opd), and to oe, opv and opd devices comprising, or being prepared from, these fullerene derivatives, mixtures or formulations.. .
Organic semiconducting compounds
The invention relates to novel organic semiconducting compounds, which are small molecules or conjugated polymers, containing one or more isoindigo or thienoisoindigo based polycyclic units, to methods for their preparation and educts or intermediates used therein, to compositions, polymer blends and formulations containing them, to the use of the compounds, compositions and polymer blends as organic semiconductors in, or for the preparation of, organic electronic (oe) devices, especially organic photovoltaic (opv) devices, organic photodetectors (opd), perovskite based solar cells, organic field effect transistors (ofet) and organic light emitting diodes (oled), and to oe, opv, opd, ofet and oled devices comprising these compounds, compositions or polymer blends.. .
Merck Patent Gmbh
P-n bimodal transistors
Resurf-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (ldmos). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain.
Texas Instruments Incorporated
Method to approximate chemical potential in a ternary or quaternary semiconductor
Roughly described, a method is provided to approximate chemical potentials of elements in ternary and quaternary compound semiconductors, for example iii-v semiconductors. In embodiments of the present invention, three, four, or more relationships are solved together to find approximated chemical potentials for each group iii element and each group v element.
Cdzno/si tandem cell for photoelectrochemical water dissociation
Here we present an apparatus comprising a photoelectrochemical cell connected a photovoltaic device, comprised of a layer with a thick n-type absorber and a layer comprising a thin p-type hole emitter. The photoelectrochemical cell has binary, metal-oxide semiconductors with wide bandgaps comprising high electron affinities relative to other semiconductor materials allowing for n-type doping..
Apparatus and detecting faults in multilayer semiconductors
An apparatus according to embodiments detects locations of faults in a multilayer semiconductor (mls). The apparatus comprises a laser source that outputs a laser beam, an optical system that directs the laser beam selectively onto a target region in the mls to generate an irradiated zone in the mls, a stage and a scanner that control a relative position between the irradiated zone and the mls so that the irradiated zone moves along the target region, a controller system that measures electrical signals or electrical signal changes induced by a temperature increase in the mls, and identifies a location of the target region and locations of faults in the mls based on the measured electrical signal or the measured electrical signal changes.
Kabushiki Kaisha Toshiba
Controlled growth of nanoscale wires
The present invention generally relates to nanoscale wires, and to methods of producing nanoscale wires. In some aspects, the nanoscale wires are nanowires comprising a core which is continuous and a shell which may be continuous or discontinuous, and/or may have regions having different cross-sectional areas.
President And Fellows Of Harvard College
High efficiency inverter for distributed generation
Systems, methods, and devices relating to a dc/ac inverter. The inverter has a full bridge converter and an output filter with an integrated magnetic subcircuit.
Slab laser and amplifier and use
A slab laser and its method of use for high power applications including the manufacture of semiconductors and deposition of diamond and/or diamond-like-carbon layers, among other materials. A lamp driven slab design with a face-to-face beam propagation scheme and an end reflection that redirects the amplified radiation back out the same input surface is utilized.
Four-junction solar cell and fabrication method
A method of fabricating a four-junction solar cell includes: forming a first epitaxial structure comprising first and second subcells and a cover layer over a first substrate through a forward epitaxial growth, and forming a second epitaxial structure comprising third and fourth subcells over the second substrate; forming a groove and a metal bonding layer; forming a groove on the cover layer surface of the first epitaxial structure and the substrate back surface of the second epitaxial structure, and depositing a metal bonding layer in the groove; and bonding the first epitaxial structure and the second epitaxial structure; bonding the cover layer surface of the first epitaxial structure and the substrate back surface of the second epitaxial structure, ensuring that the metal bonding layers are aligned to each other to realize dual bonding between the metal bonding layers and between the semiconductors through high temperature and high pressure treatment.. .
Xiamen Sanan Optoelectronics Technology Co., Ltd.
Guided-wave photodetector apparatus employing mid-bandgap states of semiconductor materials, and fabrication methods for same
Guided-wave photodetectors based on absorption of infrared photons by mid-bandgap states in non-crystal semiconductors. In one example, a resonant guided-wave photodetector is fabricated based on a polysilicon layer used for the transistor gate in a soi cmos process without any change to the foundry process flow (‘zero-change’ cmos).
Method of forming a junction field effect transistor
The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (jfet). In one aspect, a method of fabricating a jfet includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type.
Method for mounting semiconductors provided with bumps on substrate locations of a substrate
The invention relates to a method for mounting semiconductor chips provided with bumps as flip chips on substrate locations of a substrate. The method comprises the placing of a flip chip in a cavity arranged in a stationary manner where the bumps are wetted with a fluxing agent and the position of the flip chip is determined by means of a camera.
Besi Switzerland Ag
Assembly structure of high-power semiconductors and heat sink
An assembly structure of high-power semiconductors and heat sink includes a high-power semiconductor module and a heat sink. The high-power semiconductor module includes a printed circuit board, and high-power semiconductor components provided on the surfaces of the printed circuit board.
Method for producing differently doped semiconductors
The present invention relates to a liquid-phase method for doping a semiconductor substrate, characterized in that a first composition containing at least one first dopant is applied to one or more regions of the surface of the semiconductor substrate, in order to create one or more region(s) of the surface of the semiconductor substrate coated with the first composition; a second composition containing at least one second dopant is applied to one or more regions of the surface of the semiconductor substrate, in order to create one or more region(s) of the surface of the semiconductor substrate coated with the second composition, where the one or more region(s) coated with the first composition and the one or more region(s) coated with the second composition are different and do not overlap significantly and where the first dopant is an n-type dopant and the second dopant is a p-type dopant or vice versa; the regions of the surface of the semiconductor substrate coated with the first composition and with the second composition are each fully or partly activated; optionally, the unactivated regions of the surface of the semiconductor substrate coated with the first composition and with the second composition are each oxidized; and the semiconductor substrate is heated to a temperature at which the dopants diffuse out of the coating into the semiconductor substrate. The invention further relates to the semiconductor obtainable by the method and to the use thereof, especially in the production of solar cells..
Evonik Degussa Gmbh
Semiconductor modification process and structures
There is herein described a process for providing improved device performance and fabrication techniques for semiconductors. More particularly, the present invention relates to a process for forming features, such as pixels, on gan semiconductors using a p-gan modification and annealing process.
Epitaxial growth of gallium arsenide on silicon using a graphene buffer layer
Epitaxial growth of gallium arsenide (gaas) on a semiconductor material (e.g., si) using quasi-van der waals epitaxy (qvdwe). Prior to gaas growth a buffer layer (e.g., graphene) is deposited which relieves lattice mismatch/thermal expansion.
King Abdulaziz City For Science And Technology
Semiconductor layered structure and photodiode
A semiconductor layered structure according to the present invention includes a substrate formed of a iii-v compound semiconductor; and semiconductor layers disposed on the substrate and formed of iii-v compound semiconductors. The substrate has a majority-carrier-generating impurity concentration of 1×1017 cm−3 or more and 2×1020 cm−3 or less, and the impurity has an activation ratio of 30% or more..
Sumitomo Electric Industries, Ltd.
Lead selenide capped with a benzoate ligand
Semiconductor materials offer several potential benefits as active elements in the development of harvesting-energy conversion technologies. In particular, lead selenide (pbse) semiconductors have been used and proposed to design solar energy harvesting devices, ir sensors, fet devices, amongst others.
Ana G. Méndez University System
Semiconductor device and semiconductor device package using the same
A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of iii-v group semiconductors.
Delta Electronics, Inc.
Tooling for a package enclosing electronics and methods of use thereof
The disclosure relates to a precise cut, reusable tooling assembly used to precisely hold and align a package base during manufacture into an electronic package that protects electronic circuits, microelectronic circuits and semiconductors. The assembly comprises a carrier plate and a template, and an optional interface bloc, all of which secure a lower or intermediate section of the outer periphery of the package base to prevent movement of the package base during manufacturing processes.
Microcircuit Laboratories Llc
Cupric oxide semiconductors
A method of preparing a cupric oxide semiconductor. The method includes providing a substrate having a first surface, forming a cuprous oxide layer on the first surface, converting the cuprous oxide layer into a cupric oxide layer via an oxidation reaction, and depositing additional cupric oxide on the cupric oxide layer, which serves as a seed layer, to yield a cupric oxide film, thereby obtaining a cupric oxide semiconductor.
Two-dimensional heterostructure materials
Methods, articles of manufacture and systems for creating new nanoscale two dimensional materials comprising designed arrays of lateral or vertical heterojunctions may be fabricated by first lithographically masking a 2d material. Exposed, or unmasked, regions of the 2d material may be converted to a different composition of matter to form lateral or vertical heterojunctions according to the patterned mask.
Fabrication of an optoelectronic semiconductor device and integrated circuit structure
There is provided a method for fabricating an optoelectronic semiconductor device (2,27) including a layer stack (1,26) that comprises a metallization structure (7,7′) including a contact region (8,11) for electrically contacting the semiconductor device (2,27). Moreover, a dielectric layer (12) and a semiconductor layer (3) are provided.
X-fab Semiconductor Foundries Ag
Display apparatus and manufacturing method thereof
A display apparatus and a method of manufacturing the same are disclosed. The display apparatus includes: a first substrate including a light emitting diode part including a plurality of light emitting diodes regularly arranged on the first substrate; and a second substrate including a tft panel unit including a plurality of tfts driving the light emitting diodes.
Seoul Semiconductor Co., Ltd.
Insulating busbar and manufacturing method
To realize an insulating busbar that has both low inductance and high withstand voltage, provided is an insulating busbar that connects to a module on which is mounted a semiconductor chip, including a plurality of circuit conductors; a plurality of connection terminals that respectively electrically connect the circuit conductors to the module; and an insulating resin portion that is formed integrally between each of the circuit conductors and at least a portion of a region around each connection terminal and does not have any gaps between the circuit semiconductors.. .
Fuji Electric Co., Ltd.
New cyclazines and their use as semiconductors
Wherein, if present, x3, x4 are o or c(cn)2 and m, r4a, r4b, r5a, r5b, r6a, r6b, r6c, r6d, r7a, r7a, r8a, r8b, r9, r10a, r10b, rm1, rm2, rm3 and rm4 are as defined in the claims and description. The present invention also relates to a method for their preparation and their use as semiconductors, in particular as semiconductors in organic electronics and organic photovoltaics..
Formation of homojunction in kesterite-based semiconductors
Kesterite-based homojunction photovoltaic devices are provided. The photovoltaic devices include a p-type semiconductor layer including a copper-zinc-tin containing chalcogenide compound and an n-type semiconductor layer including a silver-zinc-tin containing chalcogenide compound having a crystalline structure the same as a crystalline structure the copper-zinc-tin containing chalcogenide compound..
International Business Machines Corporation
Grid polarizer and photo-alignment device
A stripe-shaped grid provided on a transparent substrate is made from dielectrics or semiconductors. For each linear segment of the grid, a gap (t) on one side of the linear segment, and an opposite gap (t) on an opposite side of the linear segment materially satisfy the relation t<t in a periodic fashion.
Ushio Denki Kabushiki Kaisha
Sputtering target, manufacturing sputtering target, and forming thin film
There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured.
Semiconductor Energy Laboratory Co., Ltd.
Method for synthesis of two-dimensional dichalcogenide semiconductors
The present disclosure relates to methods of making a transition metal dichalcogenide. The methods can include a step of depositing a transition metal onto a substrate to form an epitaxial transition metal layer.
Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements
Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements.
Unity Semiconductor Corporation
Stabilized quantum dot structure and making a stabilized quantum dot structure
A stabilized quantum dot structure for use in a light emitting diode (led) comprises, according to one embodiment, a luminescent particle comprising one or more semiconductors, a buffer layer overlying the luminescent particle, where the buffer layer comprises an amorphous material, and a barrier layer overlying the buffer layer, where the barrier layer comprises oxygen, nitrogen and/or carbon. According to another embodiment, the stabilized quantum dot structure includes a luminescent particle comprising one or more semiconductors, and a treated buffer layer comprising amorphous silica overlying the luminescent particle, where the stabilized quantum dot structure exhibits a quantum yield of at least about 0.7 when exposed to a blue light flux of about 30 w/cm2 at a temperature of 80-85° c.
Reducing autodoping of iii-v semiconductors by atomic layer epitaxy (ale)
In one aspect, a method for forming a doped iii-v semiconductor material on a substrate includes the steps of: (a) forming a first monolayer on the substrate, wherein the first monolayer comprises at least one group iii or at least one group v element; and (b) forming a doped second monolayer on a side of the first monolayer opposite the substrate, wherein the second monolayer comprises either i) at least one group v element if the first monolayer comprises at least one group iii element, or ii) at least one group iii element if the first monolayer comprises at least one group v element, wherein a dopant is selectively introduced only during formation of the second monolayer, and wherein steps (a) and (b) are performed using atomic layer epitaxy. Doped iii-v semiconductor materials are also provided..
International Business Machines Corporation
Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics
In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes.
The Board Of Trustees Of The University Of Illinois
Controlling the emission wavelength in group iii-v semiconductor laser diodes
Methods are provided for modifying the emission wavelength of a semiconductor quantum well laser diode, e.g. By blue shifting the emission wavelength.
King Abdullah University Of Science And Technology
Integrated multi-color light emitting device made with hybrid crystal structure
An integrated hybrid crystal light emitting diode (“led”) display device that may emit red, green, and blue colors on a single wafer. The various embodiments may provide double-sided hetero crystal growth with hexagonal wurtzite iii-nitride compound semiconductor on one side of (0001) c-plane sapphire media and cubic zinc-blended iii-v or ii-vi compound semiconductor on the opposite side of c-plane sapphire media.
U.s.a. As Represented By The Administrator Of The National Aeronautics And Space Administration
Write enhancement for one time programmable (otp) semiconductors
A method of programming one-time programmable (otp) memory cells in an array is described. Each memory cell has a mosfet programming element and a mosfet pass transistor, the mosfet pass transistor having a gate electrode over a channel region between two source/drain regions, and the mosfet programming element having a gate electrode over a channel region contiguous to a source/drain region either part of, or connected to, one of the two source/drains associated with the mosfet pass transistor.
Kilopass Technology, Inc.
Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory
Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology.
Unity Semiconductor Corporation
Temperature estimation in power semiconductor device in electric drvie system
Estimating junction temperature in a power semiconductor includes monitoring electrical current direction so as to determine which of a first and a second power semiconductor is in an on-state, and sensing a voltage drop across the one of the power semiconductors. Voltage drop may be correlated with temperature according to a gain dependent upon a level of the electrical current..
Multiple input three-phase inverter with independent mppt and high efficiency
Systems, methods, and devices relating to power converters. A power conditioning system uses multiple dc/dc power converter blocks.
High-purity 1-fluorobutane and plasma etching method
The present invention provides: 1-fluorobutane having a purity of 99.9% by volume or more and a total butene content of 1,000 ppm by volume or less; use of the 1-fluorobutane as a dry etching gas; and a plasma etching method using the 1-fluorobutane as an etching gas. According to the present invention, high-purity 1-fluorobutane which is suitable as a plasma reaction gas for semiconductors, the use of the high-purity 1-fluorobutane as a dry etching gas, and a plasma etching method using the high-purity 1-fluorobutane as an etching gas are provided..