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Semiconductor patents

      

This page is updated frequently with new Semiconductor-related patent applications.

new patent Robust semiconductor power devices with design to protect transistor cells with slower switching speed
this invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device.
Walters Gardens, Inc.


new patent Renesas Electronics Corporation
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new patent Lintec Corporation
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new patent Semiconductor device
one semiconductor device includes a wiring substrate, a semiconductor chip, and a sealing body. The wiring substrate includes an insulating base material, a first conductive pattern formed on one surface of the insulating base material, and a second conductive pattern formed on one surface of the insulating base material, connected to the first conductive pattern and having an end face exposed to the side.
Longitude Semiconductor S.a.r.l.


new patent Magnetic core inductor integrated with multilevel wiring network
an inductor is integrated into a multilevel wiring network of a semiconductor integrated circuit. The inductor includes a planar magnetic core and a conductive winding.
Ferric Inc.


new patent Image processing device and semiconductor device
in an image processing device, a motion image decoding processing unit extracts a feature amount of a target image to be decoded from an input stream, and changes a read size of a cache fill from an external memory to a cache memory, based on the feature amount. The feature amount represents an intra macro block ratio in, for example, one picture (frames or fields), or a motion vector variation.
Renesas Electronics Corporation


new patent Method of coupling optical signal optically with optical waveguide through two lens system
an optical coupling system to couple a collimated beam with a waveguide made of semiconductor materials is disclosed. The waveguide is implemented in an optical modulator and/or an optical hybrid, and has a core with a restricted cross section because of the enhanced refractive index of the semiconductor materials.
Sumitomo Electric Industries, Ltd.


new patent Tristate and cross current free output buffer
a tristate output buffer includes a first branch with a first buffer, and a second branch with a second buffer. The first buffer includes a supply port, a ground port, an output port, two switchable semiconductor elements of a first type, and two switchable semiconductor elements of a second type.
Tesat-spacecom Gmbh & Co. Kg


new patent Memory controller
according to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding.
Toshiba Memory Corporation


new patent Data communication system and semiconductor device
a data communication system has a first data communication circuit for outputting a clock signal to a clock signal line, receiving data input from a data signal line, and outputting data as open drain output to the data signal line, a second data communication circuit for receiving input of a clock signal from the clock signal line, receiving input of data from the data signal line, and outputting data as open drain output to the data signal line, a first pull-up resistor connected between the data signal line and the wiring of a power supply potential, a second pull-up resistor for selectively pulling up the data signal line, and a pull-up control circuit that is connected to the second pull-up resistor, and strengthens pull-up of the data signal line at least in response to a clock signal.. .
Seiko Epson Corporation


new patent

Method for determining a multiphase motor current and electric motor drive

a method for determining a motor current of an electric motor drive with a power source and with an electric motor and with a power converter connected therebetween, wherein an input current of the power source is converted by a pulse width modulated control of a number of semiconductor switches of the power converter into the motor current, wherein an intermediate circuit current of an intermediate circuit of the power source is influenced during the pulse width modulated control of the semiconductor switches, wherein an inductive voltage change is detected at a measuring point of the intermediate circuit due to the influence on the intermediate circuit current, and wherein a value for the generated motor current is determined based on the pulse width modulated control of the semiconductor switches and the inductive voltage change detected at the measuring point.. .
Brose Fahrzeugteile Gmbh & Co. Kommanditgesellschaft, Wuerzburg

new patent

Semiconductor module

reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of igbt chips are electrically connected via a high-side relay board.
Renesas Electronics Corporation

new patent

Electric power conversion device and electric power system

an electric power conversion device includes a first arm and a second arm each including converter cells. The converter cell of the first arm is a first converter cell having a full-bridge configuration including an energy storing element and semiconductor switching elements.
Mitsubishi Electric Corporation

new patent

Switching device

a switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an sic semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the sic semiconductor layer, and a second electrode arranged to be in contact with the sic semiconductor layer for conducting with the first electrode due to the formation of the current path, while the first electrode has a variable resistance portion made of a material whose resistance value increases under a prescribed high-temperature condition for limiting current density of overcurrent to not more than a prescribed value when the overcurrent flows to the current path.. .
Rohm Co., Ltd.

new patent

Semiconductor device and system

a semiconductor device includes an inductor selectively connected to a power supply voltage and configured to store and release energy; a first transistor connected between the power supply voltage and the inductor and configured to provide the power supply voltage to the inductor; a second transistor connected to the first transistor in series, connected between the inductor and a ground voltage, and configured to provide the ground voltage to the inductor; a modulator configured to provide a modulation signal to a control circuit configured to control the first and second transistors by performing pulse width modulation (pwm); a current sensor configured to sense an amount of current passing through the first transistor and generate a first output signal based on the sensed amount of current; and a first overcurrent protection output generator configured to generate a second output signal based on the first output signal and a first reference signal.. .
Samsung Electronics Co., Ltd.

new patent

Semiconductor device and semiconductor device mounting method

a semiconductor device includes a device main body that is semi-annular, the device main body having an inner circumferential surface formed arcuate in plan view and an outer circumferential surface formed arcuate in plan view. Cutout portions are formed on a first end surface, on one end side, in a circumferential direction, of the device main body and a second end surface, on an other end side, in the circumferential direction, of the device main body.
Shindengen Electric Manufacturing Co., Ltd.

new patent

Arc-free dc circuit breaker

the present disclosure provides an arc-free dc circuit breaker that combines magnetic induction transfer and resistive current limiting. The circuit breaker comprises a main current circuit and a transfer current circuit.
Xi'an Jiaotong University

new patent

Semiconductor device for controlling power source

a semiconductor device for power supply control includes an over-current detection circuit which detects an over-current state on a secondary side of a transformer by comparing a voltage in proportion to current flowing in a primary-side winding wire with an over-current detection voltage; a control signal generation circuit which generates a control signal to turn off a switching element when the over-current detection circuit has detected the over-current state; and an over-current detection level generation circuit which generates the over-current detection voltage in accordance with an on-duty of a driving pulse of the switching element. The over-current detection level generation circuit is configured to generate the over-current detection voltage in accordance with: vocp=vint+a·on duty, where vocp represents the over-current detection voltage, on duty represents the on-duty, vint represents the over-current detection voltage to be a reference, and “a” represents a correction coefficient..
Mitsumi Electric Co., Ltd.

new patent

Hybrid circuit breaker having a bridge induction transfer structure

the present disclosure provides a hybrid circuit breaker having a bridge induction transfer structure, characterized in that the circuit breaker comprises a main current circuit, an over-voltage limiting circuit, and a transfer current circuit; and the main current circuit, the over-voltage limiting circuit, and the transfer current circuit are connected in parallel. The induction transfer circuit in the transfer current circuit comprises an induction transfer inductor, an induction transfer capacitor, and an induction transfer branch power semiconductor device which are connected in series; the transfer current circuit further comprises a bridge circuit comprised of a main loop capacitor; the main loop inductor and the induction transfer inductor are coupled to form a transformer.
Xi'an Jiaotong University

new patent

Semiconductor laser device

a semiconductor laser device includes a semiconductor epitaxial structure, an electrode pad layer, and a transparent conductive layer. The semiconductor epitaxial structure includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer.
Playnitride Inc.

new patent

Semiconductor optical device

a semiconductor optical device includes a laminated structure constituted of a first compound semiconductor layer of an n type, an active layer, and a second compound semiconductor layer of a p type, the active layer including at least 3 barrier layers and well layers interposed among the barrier layers, and the semiconductor optical device satisfying egp-br>egn-br>egwell when a bandgap energy of the barrier layer adjacent to the second compound semiconductor layer is represented by egp-br, a bandgap energy of the barrier layer between the well layers is represented by egwell, and a bandgap energy of the barrier layer adjacent to the first compound semiconductor layer is represented by egn-br.. .
Sony Corporation

new patent

Optical amplifier including multi-section gain waveguide

described herein are methods, systems, and apparatuses to utilize a semiconductor optical amplifier (soa) comprising a silicon layer including a silicon waveguide, a non-silicon layer disposed on the silicon layer and including a non-silicon waveguide, first and second mode transition region comprising tapers in the silicon waveguide and/or the non-silicon waveguide for exchanging light between the waveguide, and a plurality of regions disposed between the first and second mode transition regions comprising different cross-sectional areas of the silicon waveguide and the non-silicon waveguide such that confinement factors for the non-silicon waveguide in each of the plurality of regions differ.. .
Juniper Networks, Inc.

new patent

Semiconductor laser module

a semiconductor laser module includes a semiconductor laser that outputs laser light; an optical fiber that guides the laser light; a lens that couples the laser light, which is output from the semiconductor laser, with the optical fiber; a base that is substantially tabular in shape and that has the semiconductor laser, the optical fiber, and the lens fixed thereon either directly or indirectly; and a housing which houses the base and fixes the base either directly or indirectly. Among faces of the base, a face on a side that is fixed either directly or indirectly to the housing includes a junction plane that is joined to the housing either directly or indirectly, and a detachment plane that is detached to remain unfixed from the housing..
Furukawa Electric Co., Ltd.

new patent

Wafer scale monolithic integration of lasers, modulators, and other optical components using ald optical coatings

after forming a monolithically integrated device including a laser and a modulator on a semiconductor substrate, an anti-reflection coating layer is formed over the monolithically integrated device and the semiconductor substrate by an atomic layer deposition (ald) process. The anti-reflection coating layer is lithographically patterned so that an anti-reflection coating is only present on exposed surfaces of the modulator.
International Business Machines Corporation

new patent

Light-emitting diode device

a led device includes a substrate; a plurality of led units on the substrate, wherein each led unit includes: a first semiconductor layer; a second semiconductor layer; a first sidewall; a second sidewall opposite to the first sidewall; and a third sidewall connecting the first and second sidewalls; a first group of conductive connecting structure including n (n is an integer, and n>1) first conductive connecting structures formed on the first sidewall of one of the led units and electrically connecting the led units; and a second group of conductive connecting structure including m (m is an integer, m≥1, and n≠m) second conductive connecting structures formed on the second sidewall of the same one of the led unit and electrically connecting the led units; wherein each of the first and the second conductive connecting structures includes a middle part, a first and a second extending parts; wherein the first and the second extending parts have different length.. .
Epistar Corporation

new patent

Light emitting device

a light-emitting device, comprising: a substrate; a semiconductor stacking layer comprising a first type semiconductor layer on the substrate, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer; and an electrode structure on the second semiconductor layer, wherein the electrode structure comprises a bonding layer, a conductive layer, and a first barrier layer between the bonding layer and the conductive layer; wherein the conductive layer has higher standard oxidation potential than that of the bonding layer.. .
Epistar Corporation

new patent

Method of producing a connection support, connection support and optoelectronic semiconductor component comprising a connection support

a method of producing at least one connection carrier includes: a) providing a carrier plate with a planar top face; b) applying at least one electrically insulating insulation strip to the top face and cohesively connecting the carrier plate and the insulation strip; and c) applying at least one electrically conductive conductor strip to an adhesive surface of the insulation strip and cohesively connecting the insulation strip and the conductor strip, wherein the conductor strip and the carrier plate are electrically insulated from one another by the insulation strip.. .
Heraeus Deutschland Gmbh & Co. Kg

new patent

Light-emitting device package

a light-emitting device (led) package including a package body including a mounting region at an upper portion thereof; a lead frame below the package body; a semiconductor light-emitting device in the mounting region and electrically connected to the lead frame; a top layer attached to a top surface of the semiconductor light-emitting device, the top layer including a red phosphor; and a molding layer in the mounting region, the molding layer covering the top layer and including a short-wavelength phosphor having a peak emission wavelength that is shorter than a peak emission wavelength of the red phosphor, wherein the top layer exposes a side surface of the semiconductor light-emitting device, and the molding layer is in contact with the side surface of the semiconductor light-emitting device.. .
Samsung Electronics Co., Ltd.

new patent

Semiconductor light-emitting device including a reflector layer having a multi-layered structure

a semiconductor light-emitting device includes a light-emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer which are sequentially stacked, a first insulating layer on the second semiconductor layer with a plurality of first openings having first widths and a plurality of second openings having second widths different from the first widths, a first electrode electrically connected to the first semiconductor layer through the first openings, a first sub-electrode layer between the second semiconductor layer and the first insulating layer, the first sub-electrode layer being exposed through the second openings, and a second sub-electrode layer on the first insulating layer, the second sub-electrode layer being connected to the first sub-electrode layer through the second openings, wherein a first distance between the first openings closest to each other is different from a second distance between the second openings closest to each other.. .
Samsung Electronics Co., Ltd.

new patent

Invisible-light light emitting diode and fabrication method thereof

an invisible-light light-emitting diode includes an n-type ohmic contact semiconductor layer, an n-type current spreading layer, an n—gaas visible-light absorption layer, an n-type cladding layer, a light-emitting layer, a p-type cladding layer and a p-type ohmic contact semiconductor layer. In the invisible-light light-emitting diode, the absorption layer is gaas, which can effectively remove all visible light when current density is >1 a/mm2, and essentially all visible light when current density is below 3 a/mm2.
Xiamen San'an Optoelectronics Co., Ltd.

new patent

Light emitting element including zno transparent electrode

an exemplary light emitting diode is provided to comprise: a first semiconductor layer; a mesa disposed on the first semiconductor layer and including an active layer and a second semiconductor layer disposed on the active layer; a zno transparent electrode disposed on the mesa; a first electrode disposed on the first semiconductor layer; and a second electrode disposed on the zno transparent electrode, and including a second electrode pad and at least one second electrode extending portion extending from the second electrode pad. The second electrode extending portion contacts the zno transparent electrode.
Seoul Viosys Co., Ltd.

new patent

Light emitting diode structure

a light emitting diode structure including a substrate, a semiconductor epitaxial structure, a first insulating layer, a first reflective layer, a second reflective layer, a second insulating layer and at least one electrode. The substrate has a tilt surface.
Genesis Photonics Inc.

new patent

Light emitting diode having side reflection layer

a light emitting diode including a side reflection layer. The light emitting diode includes: a semiconductor stack and a light exit surface having a roughened surface through which light generated from an active layer is emitted; side surfaces defining the light exit surface; and a side reflection layer covering at least part of the side surfaces.
Seoul Viosys Co., Ltd.

new patent

Light-emitting element

an embodiment relates to a light-emitting element capable of reducing the driving voltage and improving the optical output, comprising: a support substrate; a light-emitting structure which is arranged on the support substrate, and which comprises a first semiconductor layer, an active layer, and a second semiconductor layer; a plurality of connection grooves comprising bottom surfaces, which expose the second semiconductor layer through removal of the light-emitting structure, and side surfaces, which expose the first semiconductor layer, the active layer, and the second semiconductor layer; a first electrode arranged on the light-emitting structure so as to contact the first semiconductor layer, the first electrode comprising a first electrode pattern, which has ends extending to the peripheries of the connection grooves, and a second electrode pattern, which is arranged on the first electrode pattern; a contact electrode extending to the upper surface of the first semiconductor layer so as to surround the bottom and side surfaces of the connection grooves; a second electrode comprising a bonding electrode connected to a plurality of the contact electrodes; and an insulating pattern arranged between the first electrode and the second electrode.. .
Lg Innotek Co., Ltd.

new patent

P-type contact to semiconductor heterostructure

a contact to a semiconductor heterostructure is described. In one embodiment, there is an n-type semiconductor contact layer.
Sensor Electronic Technology, Inc.

new patent

Ultraviolet light emitting device

a light emitting device, according to one embodiment, may comprise: a substrate; a first conductive semiconductor layer disposed on the substrate; an active layer disposed on the first conductive semiconductor layer and generating an ultraviolet light; a second conductive semiconductor layer disposed on the active layer; and a hole injection layer disposed between the active layer and the second conductive semiconductor layer and comprising a first layer comprising alxga1-xn (0<x≤1) and a second layer comprising gan. The embodiment has the hole injection layer to be multi-layered, thereby having the effect of effectively preventing the absorption of ultraviolet light..
Lg Innotek Co., Ltd.

new patent

Light-emitting device and manufacturing method therefor

disclosed in one embodiment is a light-emitting device comprising: a first semiconductor layer; an active layer arranged on the first semiconductor layer and including a plurality of first uneven portions; an electron blocking layer including a plurality of second uneven portions arranged on the plurality of first uneven portions; and a second semiconductor layer formed on the electron blocking layer, wherein the electron blocking layer has at least two doping concentration peak sections of a p-type dopant in the thickness direction.. .
Lg Innotek Co., Ltd.

new patent

Light-emitting devices and displays with improved performance

light-emitting devices and displays with improved performance are disclosed. A light-emitting device includes a first electrode including an anode opposite a second electrode including a cathode, a hole injection layer adjacent the first electrode, a hole transporting layer disposed on the hole injection layer, and an emissive layer of inorganic semiconductor nanocrystals disposed between the hole transporting layer and the second electrode.
Samsung Electronics Co., Ltd.

new patent

Light emitting diode and fabrication method thereof

a light-emitting diode includes from bottom to up: a substrate, a first-conductive type semiconductor layer, a super lattice, a multi-quantum well layer and a second-conductive type semiconductor layer. At least one layer of granular medium layer is inserted in the super lattice.
Xiamen Sanan Optoelectronics Technology Co., Ltd.

new patent

Light emitting diode

a light emitting diode and a method for fabricating the same are provided. The light emitting diode includes: a transparent substrate; a semiconductor material layer formed on the top surface of a substrate with an active layer generating light; and a fluorescent layer formed on the back surface of the substrate with controlled varied thicknesses.
Samsung Electronics Co., Ltd.

new patent

Semiconductor wafers and semiconductor devices with barrier layer and methods of manufacturing

a semiconductor ingot is sliced to obtain a semiconductor slice with a front side surface and a rear side surface parallel to the front side surface. A passivation layer is formed directly on at least one of the front side surface and the rear side surface.
Infineon Technologies Ag

new patent

Light-receiving element and optical integrated circuit

a light-receiving element (10) according to the present invention includes a semiconductor layer (100) including a p-type semiconductor region (101), an n-type semiconductor region (102), and a multiplication region(103), and a p-type light absorption layer (104) formed on the multiplication region. The p-type semiconductor region and the n-type semiconductor region are formed to sandwich the multiplication region in a planar direction of the semiconductor layer.
Nippon Telegraph And Telephone Corporation

new patent

A material structure for a solar cell, a solar cell and a manufacturing a material structure

the present invention relates to a material structure for a solar cell and a method for manufacturing the material structure. A solar cell comprising the material structure is also disclosed.
Inl - International Iberian Nanotechnology Laboratory

new patent

Solar cell

provided is a solar cell including: a semiconductor substrate; a conductive area disposed on one surface of the semiconductor substrate; a first electrode line disposed on the conductive area and extending in a first direction; and a second electrode line disposed on the conductive area and extending in a second direction different from the first direction, wherein the first electrode line includes first particles having a spherical shape and a first average diameter, and the second electrode line includes the first particles and second particles, the second particles having a non-spherical shape and a second average diameter.. .
Lg Electronics Inc.

new patent

Solar cell panel

disclosed is a solar cell panel including a plurality of solar cells including a first solar cell and a second solar cell. Each of the first and second solar cells includes a semiconductor substrate, a first conductive area disposed on a first surface of the semiconductor substrate, a second conductive area disposed on a second surface of the semiconductor substrate which is opposite the first surface of the semiconductor substrate, a first transparent electrode layer disposed on the first conductive area, a second transparent electrode layer disposed on the second conductive area, and a plurality of interconnectors spaced apart from one another at a constant pitch on the first transparent electrode layer so as to extend in a given direction.
Lg Electronics Inc.

new patent

Efficiency enhancement of solar cells using light management

a photovoltaic cell includes a junction, formed from an n-type semiconductor material and a p-type semiconductor material, a trench, opening toward the light-incident side of the junction, for trapping reflected light, and two photon conversion layers. A first photon conversion layer, arranged at the light-incident side of the junction, converts photons from a higher energy to a lower energy suitable for absorption by the semiconductor material, and a second photon conversion layer, arranged at the opposite side of the junction, converts photons from a lower energy to a higher energy suitable for absorption by the semiconductor material..
The University Of North Carolina At Charlotte

new patent

Solar cell and manufacturing the same

disclosed is a method for manufacturing a solar cell. The method includes: forming a first tunneling layer on one surface of a semiconductor substrate; forming a first conductive region on the first tunneling layer so that the first conductive region includes a metal oxide layer having an amorphous structure; and forming a first electrode electrically connected to the first conductive region..
Lg Electronics Inc.

new patent

Method of forming an electrode structure and manufacturing a photovoltaic cell using the same

in a method of forming an electrode structure for a photovoltaic cell, a transparent conductive layer is formed on a semiconductor layer of amorphous silicon material doped with dopants of a first conductive type. Then, a first metal pattern is formed on the transparent conductive layer by performing an ink jet process using metal nano ink.
Korea University Research And Business Foundation

new patent

Semi-polar led epitaxial structure and fabrication method

a semi-polar led epitaxial structure includes, from bottom to up: a sapphire substrate; a semiconductor bottom layer structure; and a semiconductor functional layer; wherein: a surface of the semiconductor bottom structure has v pits; and a side of the v pits is a semi-polar surface, corresponding to (1-101) family of crystal planes. A fabrication method includes: providing a sapphire substrate; growing a semiconductor bottom structure over the sapphire substrate to form v pits on a surface, wherein a side of the v pits is a semi-polar surface, corresponding to (1-101) family of crystal planes; and growing a semiconductor functional layer over the semi-polar surface of the semiconductor bottom structure..
Xiamen Sanan Optoelectronics Technology Co., Ltd.

new patent

Solar cell and manufacturing the same

disclosed is a solar cell including: a semiconductor substrate; a tunneling layer on a surface of the semiconductor substrate; an intermediate layer on the tunneling layer, wherein the intermediate layer including a hydroxyl group (an oh group); a first conductive region on the intermediate layer, wherein the first conductive region comprising a metal oxide layer for extracting a first carrier; and a first electrode electrically connected to the first conductive region.. .
Lg Electronics Inc.

new patent

Semiconductor device

germanium (ge) contamination to a semiconductor manufacturing apparatus is suppressed. Germanium is a dissimilar material in a silicon semiconductor process.
Renesas Electronics Corporation

new patent

Solar cell and solar cell panel including the same

a solar cell is disclosed. The solar cell includes a semiconductor substrate having a chamfer formed at an edge thereof and an electrode electrically connected to the semiconductor substrate through a conductivity type region.
Lg Electronics Inc.

new patent

Photovoltaic device

a photovoltaic device (1) includes: an i-type amorphous semiconductor layer (102i) formed in contact with one of the surfaces of a semiconductor substrate (101); p-type amorphous semiconductor strips (102p) spaced apart from each other and provided on the i-type amorphous semiconductor layer (102i); and n-type amorphous semiconductor strips (102n) spaced apart from each other and provided on the i amorphous semiconductor layer (102i), each n-type amorphous semiconductor strip (102n) being adjacent to at least one of the p-type amorphous semiconductor strips (102p) as traced along an in-plane direction of the semiconductor substrate (101). The photovoltaic device (1) further includes electrodes (103) as a protection layer formed in contact with the i-type amorphous semiconductor layer (102) between adjacent p-type amorphous semiconductor strips (102) and between adjacent n-type amorphous semiconductor strips (102n)..
Sharp Kabushiki Kaisha

new patent

Stacked schottky diode

a stacked schottky-diode having a stack with a top side and a bottom side. The stack has at least three semiconductor layers, and a first connection contact layer materially connected to the bottom side of the stack.
3-5 Power Electronics Gmbh

new patent

Iii-v semiconductor diode

a stacked iii-v semiconductor diode having an n+ substrate with a dopant concentration of at least 1019 cm−3 and a layer thickness of 50-400 μm, an n− layer with a dopant concentration of 1012-1016 cm−3 and a layer thickness of 10-300 μm, a p+ layer with a dopant concentration of 5·1018-5·1020 cm−3, including a gaas compound and with a layer thickness greater than 2 μm, wherein the n+ substrate and the n− layer are integrally joined to one another. A doped intermediate layer with a layer thickness of 1-50 μm and a dopant concentration of 1012-1017 cm−3 is arranged between the n− layer and the p+ layer, and the intermediate layer is integrally joined to the n− layer and to the p+ layer..
3-5 Power Electronics Gmbh

new patent

Monolithic series switching semiconductor device having low-resistance substrate contact structure and method

a semiconductor device structure includes a region of semiconductor material with a first major surface and an opposing second major surface. A contact structure is disposed in a first portion of the region of semiconductor material and includes a tub structure extending from adjacent a first portion of the first major surface.
Semiconductor Components Industries, Llc

new patent

Semiconductor device and manufacturing same

a semiconductor device includes a semiconductor substrate including a main surface, an element separation film formed over the main surface, and a fin protruding from the element separation film and extending in the first direction in plan view. The semiconductor device further includes a control gate electrode extending in the second direction that is orthogonal to the first direction along the surface of the fin through a gate insulating film and overlaps with a first main surface of the element separation film, and a memory gate electrode extending in the second direction along the surface of the fin through an insulating film and overlaps with a second main surface of the element separation film, in which the second main surface is lower than the first main surface relative to the main surface..
Renesas Electronics Corporation

new patent

Memory device and fabricating thereof

a memory device includes a semiconductor substrate and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Semiconductor device

a semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.. .
United Microelectronics Corp.

new patent

Ternary barristor with schottky junction graphene semiconductor

disclosed is a graphene-based ternary barristor using a schottky junction graphene semiconductor. A graphene channel layer is doped with n-type and n-type dopants to have two different fermi levels and form a pn junction.
Gwangju Institute Of Science And Technology

new patent

Power mosfets manufacturing method

present application provides a method of manufacturing a semiconductor structure, including forming a well, forming a gate electrode over the well, implanting a lightly doped region in a first side of the well, implanting a first drain in the lightly doped region by a first depth, implanting a second drain in the lightly doped region by a second depth, implanting a source in a second side of the well, the second side being opposite to the first side. The second depth is greater than the first depth.
Taiwan Semiconductor Manufacturing Company Ltd.

new patent

Semiconductor device

a semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein.
Rohm Co., Ltd.

new patent

Semiconductor device and manufacturing the same

the semiconductor device according to an aspect of the present invention includes a semiconductor substrate, a drain region, a drift region, a base region, a source region, a gate electrode, an interlayer insulating film, a conductive layer electrically coupled to the drain region, a wiring line, and a contact plug electrically coupled to the source region and the wiring line. The interlayer insulating film has an intermediate interlayer insulating film.

new patent

Semiconductor device with a gate insulating film formed on an inner wall of a trench, and manufacturing the same

a semiconductor device includes a semiconductor substrate, which includes: a drift region that has a first conductivity type; a body region that has a second conductivity type and is formed on the drift region; and an impurity region that has the first conductivity type and is formed inward from a surface of the body region. The semiconductor device further includes a trench, which is formed on a front surface of the semiconductor substrate and reaches the drift region; a control electrode, which is formed in the trench; an oxide film, which is formed between an inner wall of the trench and the control electrode; an electrode, which is connected to the impurity region; and a transistor, which includes a nitride film formed on the front surface of the semiconductor substrate excluding an upper side of the control electrode and a formation position of the electrode, in the semiconductor substrate..
Sanken Electric Co., Ltd.

new patent

Semiconductor device and manufacturing semiconductor device

a semiconductor device includes an active region provided in an n+-type silicon carbide substrate and through which main current flows, a termination region that surrounds a periphery of the active region, and a p-type silicon carbide layer provided on a front surface of the n+-type silicon carbide substrate and extending into the termination region. A region of the p-type silicon carbide layer extending into the termination region includes one or more step portions that progressively reduce a thickness of the p-type silicon carbide layer as the p-type silicon carbide layer becomes farther outward from the active region..
Fuji Electric Co., Ltd.

new patent

High-electron-mobility transistor (hemt) semiconductor devices with reduced dynamic resistance

high-electron-mobility transistor (hemt) devices are described in this patent application. In some implementations, the hemt devices can include a back barrier hole injection structure.
Semiconductor Components Industries, Llc

new patent

Semiconductor device and manufacturing the same

a semiconductor device comprises: a substrate; a semiconductor layer on the substrate; and a gallium nitride cap layer on the semiconductor layer. The gallium nitride cap layer has a thickness of 3 nm to 5.8 nm..
Gpower Semiconductor, Inc.

new patent

High electron mobility transistor with graded back-barrier region

a semiconductor device includes a type iii-v semiconductor body having a main surface and a rear surface opposite the main surface. A barrier region is disposed beneath the main surface.
Infineon Technologies Austria Ag

new patent

Compound semiconductor device

a compound semiconductor device includes a first transistor formed on a gan epitaxial layer. The first transistor includes a gate electrode, a source electrode, a drain electrode, and a protective film covering them.
Advantest Corporation

new patent

Power semiconductor transistor having fully depleted channel region

a power semiconductor transistor includes a trench extending into a semiconductor body along a vertical direction and having first and second trench sidewalls and a trench bottom, an electrode in the trench electrically insulated from the semiconductor body, drift and source regions of a first conductivity type, a semiconductor channel region of a second conductivity type laterally adjacent the first trench sidewall and separating the source and drift regions, and a guidance zone. The guidance zone includes a bar section of the second conductivity type extending along the second trench sidewall or along a sidewall of another trench in the vertical direction to a depth in the semiconductor body deeper than the trench bottom, and a plateau section of the second conductivity type adjoining the bar section and extending under the trench bottom towards the semiconductor channel region.
Infineon Technologies Ag

new patent

Semiconductor device and manufacturing the same

a semiconductor device includes: a semiconductor substrate including: a drift region that has a first conductivity type; a body region that has a second conductivity type and is formed on the drift region; and an impurity region that has the first conductivity type and is formed in a surface of the body region; a trench, which reaches the drift region; an electric-field relaxation layer, which is formed on at least a portion of a bottom surface out of inner walls of the trench and is electrically connected to the impurity region; a control electrode, which is formed in the trench; an insulating film, which is formed between the control electrode and both the inner walls of the trench and the electric-field relaxation layer; and an electrode, which is connected to the impurity region.. .
Sanken Electric Co., Ltd.

new patent

Semiconductor device

a semiconductor device includes: a semiconductor substrate having a first conductivity-type drift region; a transistor portion; and a diode portion, wherein the transistor portion and the diode portion each have: a second conductivity-type base region; a plurality of trench portions penetrating the base region and having conductive portions provided therein; and a mesa portion sandwiched by trench portions, the transistor portion has one or more first conductivity-type accumulation regions that have doping concentrations higher than that of the drift region, the diode portion has one or more first conductivity-type high concentration regions that have doping concentrations higher than that of the drift region, and an integrated concentration of the doping concentrations of the accumulation regions is higher than an integrated concentration of the doping concentrations of the one or more high concentration regions of the mesa portion of the diode portion.. .
Fuji Electric Co., Ltd.

new patent

High resistivity silicon-on-insulator wafer manufacturing reducing substrate loss

a multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor nitride layer in contact with the semiconductor handle substrate, the semiconductor nitride layer selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof; a dielectric layer in contact with the semiconductor nitride layer; and a semiconductor device layer in contact with the dielectric layer..
Sunedison Semiconductor Limited (uen201334164h)

new patent

Cylindrical germanium nanowire device

a semiconductor device includes a substrate, a cavity in the substrate, and a germanium (ge) nanowire suspending in the cavity.. .
Semiconductor Manufacturing International (shanghai) Corporation

new patent

Forming a fin using double trench epitaxy

the present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy. The fin may be composed of a iii-v semiconductor material and may be grown on a silicon, silicon germanium, or germanium substrate.
International Business Machines Corporation

new patent

Method for producing semiconductor device and semiconductor device

a method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.. .
Unisantis Electronics Singapore Pte. Ltd.

new patent

Trench transistors and methods with low-voltage-drop shunt to body diode

methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage.
Maxpower Semiconductor Inc.

new patent

Method of forming gate spacer for nanowire fet device

a method of forming a gate-all-around semiconductor device, includes providing a substrate having a layered fin structure thereon. The layered fin structure includes a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material.
Tokyo Electron Limited

new patent

Semiconductor device including sense insulated-gate bipolar transistor

a semiconductor device of the present invention includes a semiconductor layer including a main igbt cell and a sense igbt cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense igbt cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main igbt cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense igbt cell.. .
Rohm Co., Ltd.

new patent

Ge nano wire transistor with gaas as the sacrificial layer

an apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode..
Intel Corporation

new patent

Silicon carbide semiconductor element and manufacturing silicon carbide semiconductor

a silicon carbide semiconductor element includes n-type silicon carbide epitaxial layers formed on an n+-type silicon carbide semiconductor substrate, plural p base layers selectively formed in surfaces of the silicon carbide epitaxial layers, a p-type silicon carbide epitaxial layer formed in the silicon carbide epitaxial layer, and a trench penetrating at least the silicon carbide epitaxial layer. The silicon carbide semiconductor element also includes, in a portion of the silicon carbide epitaxial layer, a mesa portion exposing the p base layer.
Fuji Electric Co., Ltd.

new patent

Method of manufacturing silicon carbide semiconductor device

in a method of manufacturing a silicon carbide semiconductor device, an n-type drift layer and a p-type epitaxial base layer are sequentially deposited onto an n-type silicon carbide substrate. Next, n-type source regions and a p-type base contact region are formed in the surface layer of the p-type epitaxial base layer.
Fuji Electric Co., Ltd.

new patent

Sloped finfet with methods of forming same

embodiments of the present disclosure provide an integrated circuit (ic) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.. .
International Business Machines Corporation

new patent

Methods of forming integrated circuit structure with silicide reigon

embodiments of the present disclosure relate to methods of forming an integrated circuit (ic) structure with a silicide region. Methods according to the present disclosure can include providing a structure including: a semiconductor region positioned on an electrostatic chuck, and a precursor metal positioned on and in contact with the semiconductor region; heating the semiconductor region of the structure to an annealing temperature by increasing a temperature of the electrostatic chuck; irradiating the structure with a radiant heat source, such that at least some of the precursor metal migrates into a portion of the semiconductor region to form a silicide region during the irradiating; and removing a remainder of the precursor metal from the structure to expose the silicide region, after the irradiating..
Globalfoundries Inc.

new patent

Integrated epitaxial metal electrodes

systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer..
Iqe, Plc

new patent

Semiconductor device

it is an object to provide a semiconductor device with low wiring resistance, high transmittance, or a high aperture ratio. A gate electrode, a semiconductor layer, and a source electrode and a drain electrode are formed using a material having a light-transmitting property and a wiring such as a gate wiring or a source wiring is formed using a material whose resistivity is lower than that of the material having a light-transmitting property.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor device and forming method thereof

a semiconductor device includes a semiconductor substrate, at least one gate stack, a gate spacer and a dielectric cap. The gate stack is located on the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Transistor-based semiconductor device with air-gap spacers and gate contact over active area

a semiconductor structure includes a semiconductor substrate, a semiconductor fin on the semiconductor substrate, a transistor integrated with the semiconductor fin at a top portion thereof, the transistor including an active region including a source, a drain and a channel region therebetween. The semiconductor structure further includes a gate structure over the channel region, the gate structure including a gate electrode, an air-gap spacer pair on opposite sidewalls of the gate electrode, and a gate contact for the gate electrode.
Globalfoundries Inc.

new patent

Semiconductor device

a semiconductor device includes a semiconductor body having a main surface and an active region surrounded by a non-active region. A trench extends from the main surface into the semiconductor body.
Infineon Technologies Austria Ag

new patent

Semiconductor device having a multi-terminal transistor layout

a semiconductor device includes a gate region, a source/drain region and an insulating layer between the gate region and the source/drain region. The source/drain region includes a first leg extending in a first direction, a second leg extending in parallel with the first leg, and a third leg connected between the first leg and the second leg..
Int Tech Co., Ltd.

new patent

Silicon carbide semiconductor device and manufacturing the same

a silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The gate insulating film is provided as being in contact with the first main surface of the silicon carbide substrate.
Renesas Electronics Corporation

new patent

Silicon carbide semiconductor device and manufacturing silicon carbide semiconductor device

a silicon carbide semiconductor device includes plural p-type silicon carbide epitaxial layers provided on an n+-type silicon carbide substrate. In some of the p-type silicon carbide epitaxial layers, an n+ source region is provided in at least a region of an upper portion.
Fuji Electric Co., Ltd.

new patent

Silicon carbide semiconductor device and manufacturing silicon carbide semiconductor device

a silicon carbide semiconductor device includes an n-type drift layer and a p-type epitaxial base layer deposited on an n-type silicon carbide substrate, as well as first trenches and second trenches. N-type source regions are formed in the surface layer of the p-type epitaxial base layer, in the sidewalls of the first trenches, and in the bottoms of the first trenches.
Fuji Electric Co., Ltd.

new patent

Semiconductor device

supposing x is defined as a position of an end of a depletion layer extending when a rated voltage v [v] is applied to a rear surface electrode, w1 is defined as a distance between the position x and an outer peripheral edge of a surface electrode in an outer peripheral direction, w2 is defined as a distance between the position x and an outer peripheral edge of a field insulating film in the outer peripheral direction, t [μm] is defined as a film thickness t [μm] of the field insulating film, a layout of a terminal part is defined so that an electrical field in the field insulating film at the position x expressed as w2v/t(w1+w2) is 3 mv/cm or smaller.. .
Mitsubishi Electric Corporation

new patent

Semiconductor device and manufacturing of semiconductor device

in forming an n+-type source region in a surface region of a p-type base layer by ion implantation, ion implantation of arsenic and ion implantation of nitrogen are sequentially performed. The ion implantation of nitrogen is performed by acceleration energy higher than that of the ion implantation of arsenic.
Fuji Electric Co., Ltd.

new patent

Nanowire semiconductor device structure and manufacturing

a nanowire comprises a source region, a drain region and a channel region. The source region is modified to reduce the lifetime of minority carriers within the source region.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Semiconductor device and fabricating the same

there is provided a semiconductor device capable of enhancing short channel effect by forming a carbon-containing semiconductor pattern in a source/drain region. The semiconductor device includes a first gate electrode and a second gate electrode spaced apart from each other on a fin-type pattern, a recess formed in the fin-type pattern between the first gate electrode and the second gate electrode, and a semiconductor pattern including a lower semiconductor film formed along a profile of the recess and an upper semiconductor film on the lower semiconductor film, wherein the lower semiconductor film includes a lower epitaxial layer and an upper epitaxial layer sequentially formed on the fin-type pattern, and a carbon concentration of the upper epitaxial layer is greater than a carbon concentration of the lower epitaxial layer..
Samsung Electronics Co., Ltd.

new patent

Method of preventing bulk silicon charge transfer for nanowire and nanoslab processing

a method of fabricating a semiconductor device includes providing a substrate having a layered fin structure thereon. The layered fin structure includes base fin portion, a sacrificial portion provided on the base fin portion and a channel portion provided on the sacrificial portion.
Tokyo Electron Limited

new patent

Semiconductor film, solar cell, light-emitting diode, thin film transistor, and electronic device

a semiconductor film includes a cluster of semiconductor quantum dots each having a metal atom and ligands coordinating to respective semiconductor quantum dots, and the semiconductor quantum dots have an average shortest inter-dot distance of less than 0.45 nm. A solar cell, a light-emitting diode, a thin film transistor, and an electronic device include the semiconductor film..
Fujifilm Corporation

new patent

Sic-based superjunction semiconductor device

a method of producing a semiconductor device includes providing a semiconductor body including a semiconductor body material having a dopant diffusion coefficient that is smaller than the corresponding dopant diffusion coefficient of silicon. At least one first semiconductor region doped with dopants of a first conductivity type is produced in the semiconductor body, including by applying a first implantation of first implantation ions.
Infineon Technologies Ag

new patent

Power semiconductor device and method therefor

an rc-igbt according to the invention includes a high electric field cell formed in a region surrounded by an igbt cell or in a region surrounded by a diode cell, and an n+ diffusion layer formed at a position opposed to the high electric field cell, the position being on a second main surface of an n− type drift layer. The high electric field cell has a higher maximum electric field intensity generated when a voltage is applied between main terminals than maximum electric field intensities of the igbt cell, the diode cell, and a withstand voltage holding structure.
Mitsubishi Electric Corporation

new patent

Semiconductor device and manufacturing semiconductor device

a semiconductor device includes a wide-bandgap semiconductor substrate of a first conductivity type, a wide-bandgap semiconductor layer of the first conductivity type provided on a front surface of the wide-bandgap semiconductor substrate of the first conductivity type, a base region of a second conductivity type selectively provided in a surface layer of the wide-bandgap semiconductor layer of the first conductivity type, and a trench having a striped planar pattern. The base regions are cyclically provided in a direction parallel to the trench.
Fuji Electric Co., Ltd.

new patent

Semiconductor structure and forming the same

a semiconductor structure includes a capacitor. The capacitor includes a bottom electrode, a first high-k dielectric layer, a second high-k dielectric layer and a top electrode.
United Microelectronics Corp.

new patent

Semiconductor device packages

a semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface.
Advanced Semiconductor Engineering, Inc.

new patent

Light emitting element display device

a display device includes two or more transistors in one pixel, and the two or more transistors include a first transistor of which a channel semiconductor layer is polycrystalline silicon, and a second transistor of which a channel semiconductor layer is an oxide semiconductor.. .
Japan Display Inc.

new patent

Organic light emitting display having a first insulating layer and a gate metal layer constitute a first capacitor

organic light-emitting display is disclosed. The organic light-emitting display includes a first substrate, a semiconductor layer positioned on the first substrate, a first insulating layer positioned on the semiconductor layer, a gate metal layer positioned on the first insulating layer, a second insulating layer with a contact hole exposing part of the gate metal layer, a source-drain metal layer positioned on the second insulating layer and electrically connected to the gate metal layer via the contact hole, a third insulating layer positioned on the source-drain metal layer, a fourth insulating layer positioned on the third insulating layer, and a pixel electrode positioned on the fourth insulating layer, wherein the fourth insulating layer fully covers the contact hole, and a stepped portion of the pixel electrode caused by the fourth insulating layer is spaced apart from the contact hole..
Lg Display Co., Ltd.

new patent

Display device using semiconductor light-emitting diodes, and manufacturing method therefor

the present invention relates to a display device and, particularly, to a display device using semiconductor light-emitting diodes. In the display device according to the present invention, at least one of the semiconductor light-emitting diodes comprises: a first conductive electrode and a second conductive electrode; a first conductive semiconductor layer having the first conductive electrode arranged thereon; a second conductive semiconductor layer overlapping with the first conductive semiconductor layer in a vertical direction, and having the second conductive electrode arranged thereon; and an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer, wherein a connecting unit electrically connected to the first conductive electrode is formed on one surface of the first conductive semiconductor layer, and the connecting unit is arranged so as to lean to one side on the basis of the second conductive electrode along the horizontal direction..
Lg Electronics Inc.

new patent

Semiconductor device having soi substrate

there is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the n-type semiconductor layer formed from a high resistance n-type substrate, the p-type well diffusion layer and p-type extraction layer are formed and are fixed to ground potential.
Inter-university Research Institute Corporation High Energy Accelerator Research Organization

new patent

Photoelectric conversion device, image pickup system and manufacturing photoelectric conversion device

a photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate.
Canon Kabushiki Kaisha

new patent

Semiconductor device, manufacturing method, solid state image sensor, and electronic equipment

the present disclosure relates to a semiconductor device, a manufacturing method, a solid state image sensor, and electronic equipment that can achieve further improvement in reliability. Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate.
Sony Corporation

new patent

Semiconductor device and imaging device

to improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads.
Sony Corporation

new patent

Infrared image sensor component and manufacturing method thereof

an infrared image sensor component includes a semiconductor substrate, an active pixel region disposed on the semiconductor substrate for receiving an infrared ray, and a transistor coupled to the active pixel region. The transistor includes a gate and a source/drain stressor disposed adjacent to the gate.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Solid-state imaging device and electronic apparatus

a solid-state imaging device includes a semiconductor layer on which a plurality of pixels are arranged along a light-receiving surface being a main surface of the semiconductor layer, photoelectric conversion units provided for the respective pixels in the semiconductor layer, and a trench element isolation area formed by providing an insulating layer in a trench pattern formed on a light-receiving surface side of the semiconductor layer, the trench element isolation area being provided at a position displaced from a pixel boundary between the pixels.. .
Sony Corporation

new patent

Display device and driving the same

a semiconductor device having a configuration hardly generating variations in the current value due to a deteriorated el element is to be provided. A capacitance element is disposed between the gate and the source of a driving tft, video signals are inputted to the gate electrode, and then it is in the floating state.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor device and manufacturing the semiconductor device

first to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor..
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor device and manufacturing the same

a semiconductor device having favorable electric characteristics is provided. The semiconductor device includes a first transistor and second transistor.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Method for manufacturing oxide semiconductor device

an object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor substrate with metallic doped buried oxide

an soi substrate includes a metallic doped isolation (i.e., buried oxide) layer. Doping of the isolation layer increases its thermal conductivity, which improves heat conduction and decreases the susceptibility of devices formed on the substrate to temperature-induced deterioration and/or failure over time.
Globalfoundries Inc.

new patent

Transistor, semiconductor device, and electronic device

to provide a semiconductor device capable of retaining data for a long time. The semiconductor device includes a first transistor, an insulator covering the first transistor, and a second transistor over the insulator.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Thin film transistor, thin film transistor substrate, liquid crystal display device, and manufacturing thin film transistor

it is an object to provide a technique capable of suppressing a damage on a semiconductor channel layer due to a process of forming a source electrode and a drain electrode and also suppressing a short channel effect. A thin film transistor includes a gate electrode, a first insulating film, a source electrode, a drain electrode, a second insulating film, and a semiconductor channel layer that includes an oxide semiconductor.
Mitsubishi Electric Corporation

new patent

Semiconductor device

reliability of a semiconductor device is improved. A p-type misfet of a thin film soi type is formed in an soi substrate including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor layer on the insulating layer, and n+-type semiconductor regions which are source and drain region of the p-type misfet are formed in the semiconductor layer and an epitaxial layer on the semiconductor layer.
Renesas Electronics Corporation

new patent

Self-aligned back-plane and well contacts for fully depleted silicon on insulator device

the present disclosure generally relates to semiconductor structures and, more particularly, to self-aligned back-plane and well contacts for a fully depleted silicon on insulator device and methods of manufacture. The structure includes a back-plane, a p-well and an n-well formed within a bulk substrate; a contact extending from each of the back-plane, the p-well and the n-well; a gate structure formed above the back-plane, the p-well and the n-well; and an insulating spacer isolating the contact of the back-plane from the gate structure..
Globalfoundries Inc.

new patent

Semiconductor structures and fabricating the same

a semiconductor structure is provided, which includes a first substrate, an oxide layer formed on the first substrate, a second substrate formed on the oxide layer, a plurality of semiconductor devices formed in the second substrate, a plurality of first trenches, a contact window, and a third trench. The first trenches are formed in the second substrate and filled with dielectric material and conductive material.
Vanguard International Semiconductor Corporation

new patent

Logic semiconductor device

a semiconductor device includes stacked transistors. Each of the transistors includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region.
Korea University Research And Business Foundation

new patent

Semiconductor device

a semiconductor device includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region.
Korea University Research And Business Foundation

new patent

Semiconductor device having a memory cell array provided inside a stacked body

according to one embodiment, a semiconductor device includes a stacked body, a memory cell array, and a columnar portion. The stacked body is provided on a major surface of a substrate.
Toshiba Memory Corporation

new patent

Semiconductor device and manufacturing the same

provided here may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a first source seed layer, a second source seed layer disposed over the first source seed layer at a position spaced apart from the first source seed layer with a source area interposed between the first source seed layer and the second source seed layer, cell plugs configured to penetrate through the second source seed layer and extend into the source area, the cell plugs being disposed at positions spaced apart from the first source seed layer.
Sk Hynix Inc.

new patent

Three-dimensional memory device having select gate electrode that is thicker than word lines and making thereof

a three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines..
Sandisk Technologies Llc

new patent

Three-dimensional memory device having a multilevel drain select gate electrode and making thereof

a three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each memory stack structure includes a memory film and a vertical semiconductor channel.
Sandisk Technologies Llc

new patent

Semiconductor device

a semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.. .
Samsung Electronics Co., Ltd.

new patent

Semiconductor integrated circuit device relating to resistance characteristics

a semiconductor integrated circuit device may include a structure, a first capping layer, a channel layer and a second capping layer. The structure may have an opening formed in the structure.
Sk Hynix Inc.

new patent

Semiconductor memory device

a semiconductor memory device includes a plurality of electrode layers stacked in a first direction; a semiconductor layer of a columnar shape extending through the electrode layers in the first direction; and a plurality of floating gates provided between the electrode layers and the semiconductor layer respectively. The floating gates surround the semiconductor layer.
Toshiba Memory Corporation

new patent

Semiconductor device and manufacturing the same

a method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation.
Samsung Electronics Co., Ltd.

new patent

Methods of forming semiconductor devices using semi-bidirectional patterning

devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first, a second, and a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a third set of lines in a direction perpendicular to the first and second set of lines; etching to define the third set of lines, leaving an opl; depositing a spacer over the opl; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks..
Globalfoundries Inc.

new patent

Semiconductor device and manufacturing method thereof

a semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Memory cell

a microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region.
Stmicroelectronics Sa

new patent

Semiconductor device and fabricating the same

a semiconductor device includes a semiconductor substrate having a first region and a second region, a plurality of first semiconductor fins in the first region, a plurality of second semiconductor fins in the second region, a first solid-state dopant source layer within the first region on the semiconductor substrate, a first insulating buffer layer on the first solid-state dopant source layer, a second solid-state dopant source layer within the second region on the semiconductor substrate, a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer, a first fin bump in the first region, and a second fin bump in the second region. The first fin bump includes a first sidewall spacer and the second fin bump comprises a second sidewall spacer.
United Microelectronics Corp.

new patent

Semiconductor device and manufacturing the same

a semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.. .
Sony Corporation

new patent

Semiconductor device including barrier layer and manufacturing method thereof

a manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate.
United Microelectronics Corp.

new patent

Formation of band-edge contacts

formation of band-edge contacts include, for example, providing an intermediate semiconductor structure comprising a substrate and a gate thereon and source/drain regions adjacent the gate, depositing a non-epitaxial layer on the source/drain regions, deposing a metal layer on the non-epitaxial layer, and forming metal alloy contacts from the deposited non-epitaxial layer and metal layer on the source/drain regions by annealing the deposited non-epitaxial layer and metal layer.. .
Globalfoundries Inc.

new patent

Semiconductor device and a fabricating the same

in a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Forming gates with varying length using sidewall image transfer

methods of forming semiconductor devices include forming structures having an inner vertical layer and spacers on sidewalls of the inner vertical layer on a first region and a second region of a gate layer. The inner vertical layer is etched in only the first region to expose inner sidewalls of the spacers in the first region.
International Business Machines Corporation

new patent

Semiconductor device and fabricating the same

a semiconductor device includes a substrate including first to third regions, wherein the third region is positioned in a first direction between the first and second regions, a fin protruding on the substrate and extending in the first direction, first and second gate structures respectively formed on the fin in the first and second regions, first and second spacers formed with spacing apart from each other on the fin in the third region. The first and second spacers are sloped in a direction away from each other, and the first and second spacers and an upper surface of the fin define a plurality of acute angles, the first and second spacers defining a recess, the fin and the first and second spacers defining sidewalls of the recess, and a device isolating film substantially filling the recess..
Samsung Electronics Co., Ltd.

new patent

Semiconductor device and manufacture

in accordance with some embodiments, conductive material is removed from over a first plurality of fins and second plurality of fins, wherein the first plurality of fins is located within a small gate length region and the second plurality of fins is located in a large gate length region. The removal is performed by initially performed a dry etch with a low pressure and a high flow rate of at least one etchant, which causes the conductive material to have a larger thickness over the second plurality of fins than over the first plurality of fins.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Semiconductor component and fabricating method thereof

a semiconductor component includes a substrate having a dense zone and a less-dense zone, at least one first finfet device disposed on the dense zone, and at least one second finfet device disposed on the less-dense zone, in which a width of a first source/drain region of the first finfet device is smaller than a width of a second source/drain region of the second finfet device.. .
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Semiconductor structures and methods of forming the same

semiconductor structures and methods for forming a semiconductor structure are provided. A first active semiconductor region is disposed in a first vertical level of the semiconductor structure.
Taiwan Semiconductor Manufacturing Company Limited

new patent

Method of manufacturing semiconductor device

a method of manufacturing a semiconductor device includes: implanting charged particles into a first range and a second range in a semiconductor substrate from at least one of a first surface of the semiconductor substrate and a second surface of the semiconductor substrate located on an opposite side of the first surface so as to increase crystal defect densities in the first range and the second range; implanting n-type impurities into the first range from the first surface so as to make a region amorphous, the region being in the first range and disposed at the first surface; irradiating the first surface with first laser after the implantation of the charged particles and the implantation of the n-type impurities so as to heat the first range and the second range; and crystallizing the region which has been made amorphous in or after the irradiation of the first laser.. .
Toyota Jidosha Kabushiki Kaisha

new patent

Semiconductor devices and methods for operating semiconductor devices

a semiconductor device includes a plurality of forward conducting insulated-gate bipolar transistor cells configured to conduct a current in a forward operating mode of the semiconductor device and to block a current in a reverse operating mode of the semiconductor device. The semiconductor device also includes a plurality of reverse conducting insulated-gate bipolar transistor cells configured to conduct a current both in the forward operating mode and in the reverse operating mode.
Infineon Technologies Ag

new patent

Semiconductor field effect transistors and manufacturing method thereof

a semiconductor device includes a substrate, source/drain contacts, gate structures, conductive elements, and a first stop layer. The substrate has source/drain regions formed therein.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Semiconductor device for electrostatic discharge protection

a semiconductor device for esd protection, includes a drain region, a first doped region, a second doped region and a source region. The drain region is disposed in a substrate at a first side of a gate and the drain region has a first conductivity type.
United Microelectronics Corp.

new patent

Semiconductor device for preventing field inversion

a semiconductor device includes a semiconductor layer having an element formation region in which a semiconductor element is formed. An element isolation well is formed in a surface portion of the semiconductor layer to isolate the element formation region.
Rohm Co., Ltd.

new patent

Display apparatus and manufacturing method thereof

a display apparatus and a micro-light emitting diode are disclosed. The display apparatus includes: a first substrate including a light emitting diode part including a plurality of light emitting diodes regularly arranged on the first substrate.
Seoul Semiconductor Co., Ltd.

new patent

Semiconductor package and manufacturing method thereof

a semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.
Amkor Technology, Inc.

new patent

Semiconductor module

a semiconductor module includes a substrate, a first package mounted on the substrate, second packages mounted on the substrate, a label layer provided on the substrate, and a heat transfer structure interposed between the substrate and the label layer and overlapping at least two of the second packages in a plan view of the module.. .
Samsung Electronics Co., Ltd.

new patent

Vertically stacked multichip modules

in a general aspect, a circuit assembly apparatus can include first and second semiconductor die, and a substrate. The substrate can include an insulating layer; a first metal layer disposed on a first side of the insulating layer, a first side of the first semiconductor die disposed on and electrically coupled with the first metal layer; a second metal layer disposed on a second side of the insulating layer, the second side of the insulating layer being opposite the first side of the insulating layer, a first side of the second semiconductor die being disposed on and electrically coupled with the second metal layer; and a conductive via disposed through the insulating layer, the conductive via electrically coupling the first metal layer with the second metal layer, the first metal layer, the conductive via and the second metal layer electrically coupling the first semiconductor die with the second semiconductor die..
Fairchild Korea Semiconductor Ltd.

new patent

Semiconductor package having a redistribution line structure

a semiconductor package may include a first semiconductor chip having first bonding pads on a first active surface. The semiconductor package may include a second semiconductor chip having second bonding pads which are arranged on a second active surface.
Sk Hynix Inc.

new patent

Compartment shielding for warpage improvement

a semiconductor device package comprises a substrate, a first component, a second component, a package body and a conductive material. The substrate has a surface.
Advanced Semiconductor Engineering, Inc.

new patent

Packaged semiconductor devices and methods of packaging semiconductor devices

packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a mask coating over a carrier, coupling an integrated circuit die over the mask coating, and disposing a molding compound around the integrated circuit die.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Semiconductor package and manufacturing method thereof

a semiconductor package includes a package substrate, a first semiconductor chip, a second semiconductor chip, and a top interposer. The first semiconductor chip and the second semiconductor chip are disposed on the package substrate.
Nanya Technology Corporation

new patent

Semiconductor packages and related methods

methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed.
Semiconductor Components Industries, Llc

new patent

Film for semiconductor device and fabrication method thereof

a film for semiconductor device includes a base material and an adhesive layer formed over the base material. The film is divided into an adhesive area and an expansion area.
Xiamen San'an Optoelectronics Co., Ltd.

new patent

Protective film for semiconductors, semiconductor device, and composite sheet

[solving means]a semiconductor protective film 10 according to an embodiment of the present invention includes a protective layer 11 formed of a non-conductive inorganic material and an adhesive layer 12 provided on one surface of the protective layer 11. The protective layer 11 includes at least a vitreous material and is typically formed of plate glass.

new patent

Semiconductor structure and manufacturing method thereof

a semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess recessed from the first surface towards the second surface; a conductive layer disposed over the first surface and within the recess; and a passivation disposed over the first surface and partially covering the conductive layer, wherein the conductive layer disposed within the recess is exposed from the passivation.. .
Nanya Technology Corporation

new patent

Semiconductor device and manufacturing thereof

a semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby..
Amkor Technology, Inc.

new patent

Semiconductor chip

a semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region.
Samsung Electronics Co., Ltd.

new patent

Semiconductor device and manufacturing the same

an insulating film is formed such that the insulating film covers a source electrode and a gate electrode, and an opening portion exposing a portion of the source electrode and an opening portion exposing a portion of the gate electrode are formed in the insulating film. A plated layer is formed over the source electrode exposed in the opening portion, and a plated layer is formed over the gate electrode exposed in the opening portion.
Renesas Electronics Corporation

new patent

Semiconductor element and production method thereof

in a semiconductor element of the present invention, an electroless nickel-phosphorus plating layer and an electroless gold plating layer are formed on both a front-side electrode and a back-side electrode of a front-back conduction-type substrate. The front-side electrode and the back-side electrode are formed of aluminum or an aluminum alloy.
Mitsubishi Electric Corporation

new patent

Semiconductor device

a semiconductor device includes a lead frame, a transistor, and an encapsulation resin. The lead frame includes a drain frame, a source frame, and a gate frame.
Rohm Co., Ltd.

new patent

Semiconductor device

airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device 1 includes a device substrate 2, a semiconductor circuit 3, a sealing frame 7, a cap substrate 8, via portions 10, electrodes 11, 12 and 13, and a bump portion 14 or the like.
Mitsubishi Electric Corporation

new patent

Multi-height semiconductor structures

among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ild) layer, is formed over a substrate.
Taiwan Semiconductor Manufacturing Company Limited

new patent

Package structure and forming thereof

a package structure includes a first redistribution layer, a molding material, a semiconductor device and an inductor. The molding material is located on the first redistribution layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Interconnect structure and forming the same

aspects of the present disclosure include a semiconductor device which includes a dielectric layer deposited over a conductive region and an interconnect electrically connecting the conductive region with a top surface of the dielectric layer. The interconnect includes a barrier layer extending from an interior of the dielectric layer to the conductive region and covering the conductive region.
Globalfoundries Inc.

new patent

Semiconductor device and manufacturing the same

as means for preventing a leakage of a fuse element cut by laser trimming due to a conductive residue or the like, an insulating film which has a high thermal conductivity and a relatively low adhesion is formed between an element isolation region and the fuse element in the case of forming the fuse element on the element isolation region in a groove on a main surface of an epitaxial substrate. When the fuse element is cut by performing the laser trimming, both of a part of the fuse element and the insulating film below the part of the fuse element are removed..
Renesas Electronics Corporation

new patent

Semiconductor device and a increasing a resistance value of an electric fuse

a semiconductor device is provided which includes an interlayer dielectric formed on a semiconductor substrate, a first insulating layer, having a trench, formed on the interlayer dielectric, a barrier film formed on side and bottom surfaces of the first trench, an electric fuse formed on the barrier film, a second insulating layer formed to directly contact the electric fuse, and a third insulating layer formed on the second insulating layer. A linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and a melting point of the barrier film is greater than a melting point of the electric fuse..
Renesas Electronics Corporation

new patent

Semiconductor device with metallization structure on opposite sides of a semiconductor portion

a semiconductor device includes a semiconductor layer with a thickness of at most 50 μm. A first metallization structure is disposed on a first surface of the semiconductor layer.
Infineon Technologies Ag

new patent

Dielectric thermal conductor for passivating efuse and metal resistor

a semiconductor device includes a first dielectric layer formed on a second dielectric layer and planar contacts formed in the second dielectric layer. The planar contacts are spaced apart to form a gap therebetween.
International Business Machines Corporation

new patent

Semiconductor device with redistribution layers on partial encapsulation and non-photosensitive passivation layers

a semiconductor device with a redistribution structure on partial encapsulation is disclosed and may include an electronic device having a top surface, a bottom surface, and side surfaces between the top and bottom surfaces of the electronic device. An encapsulant may encapsulate the side surfaces of the electronic device, a contact pad may be on the top surface of the electronic device, and a redistribution structure may be coupled to the contact pad.
Amkor Technology, Inc.

new patent

Semiconductor device and method

a semiconductor device includes a substrate, a first redistribution layer (rdl) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first rdl, and an encapsulant over the first rdl and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first rdl.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Semiconductor package structure and manufacturing the same

a semiconductor package structure includes a dielectric structure defining a plurality of through holes, wherein each of the through holes includes a first portion defined by a first sidewall portion and a second portion defined by a second sidewall portion substantially coplanar with the first sidewall portion. The semiconductor package structure further includes a redistribution layer structure disposed on a first surface of the dielectric structure, including a plurality of conductive pads and a plurality of first conductive traces, wherein each of the conductive pads is disposed in a respective through hole, and a sidewall of the conductive pad contacts the first sidewall portion of the through hole, a semiconductor die electrically connected to the redistribution layer structure, and a plurality of conductive structures each disposed on a respective one of the conductive pads and disposed in the second portion of the through hole, wherein a sidewall of the conductive structure and the second sidewall portion of the through hole define a gap..
Advanced Semiconductor Engineering, Inc.

new patent

Substrate, semiconductor package structure and manufacturing process

a substrate includes a first conductive structure, a second conductive structure attached to the first conductive structure and a third conductive structure attached to the second conductive structure. The first conductive structure includes a first dielectric layer and a first circuit layer embedded in the first dielectric layer.
Advanced Semiconductor Engineering, Inc.

new patent

Semiconductor system and device package including interconnect structure

a semiconductor device package includes a semiconductor chip, a glass substrate having a first surface facing the semiconductor chip and a second surface opposite to the first surface, the glass substrate defining a hole that traverses the glass substrate from the first surface to the second surface, an interconnect structure disposed in the hole, and a conductive bump disposed adjacent to the interconnect structure and protruded from the second surface, wherein the conductive bump and the interconnect structure include a same material.. .
Advanced Semiconductor Engineering, Inc.

new patent

Semiconductor devices and methods of making the same

in one embodiment, methods for making semiconductor devices are disclosed.. .
Semiconductor Components Industries, Llc

new patent

Semiconductor device

a semiconductor part includes a resin package and an exposed portion exposed from a bottom surface of the resin package. The exposed portion has a first diagonal line perpendicular to both first and third sides of the package as viewed from the bottom surface.
Rohm Co., Ltd.

new patent

Thermal dissipation device and semiconductor package device including the same

a thermal dissipation device includes a main body and a support member. The main body has an upper surface, a lower surface opposite to the upper surface, and a lateral surface.
Advanced Semiconductor Engineering, Inc.

new patent

Thermal via arrangement for multi-channel semiconductor device

the invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel.
Mediatek Inc.

new patent

Semiconductor device package structure

a semiconductor device package comprises a carrier having a through hole. A lid is over the carrier and comprises a first side wall, a second side wall, and a connection wall.
Advanced Semiconductor Engineering, Inc.

new patent

Contact-via chain as corrosion detector

a detector for determining a faulty semiconductor component including a semiconductor component, a contact-via chain, which is situated laterally at a distance from the semiconductor component and which surrounds the semiconductor component in regions, a guard ring, which is situated laterally at a distance from the semiconductor component, and an evaluation unit, which is situated on the semiconductor component, wherein the evaluation unit is designed to apply an electrical voltage to the contact-via chain, in particular a permanent electrical voltage, to detect a resistance value of the contact-via chain and to produce an output signal when the resistance value of the contact-via chain exceeds a threshold value.. .
Robert Bosch Gmbh

new patent

Abnormality detection apparatus

disclosed is an abnormality detection apparatus including: a collection unit that collects state information indicating a state of each part of a semiconductor manufacturing apparatus in a predetermined cycle; a storage unit that stores the state information collected by the collection unit as a log for each predetermined unit; an arithmetic unit that generates a monitoring band for monitoring the state of each part of the semiconductor manufacturing apparatus, based on the log; and a determination unit that determines whether the state of each part of the semiconductor manufacturing apparatus is abnormal, based on the state information and the monitoring band.. .
Tokyo Electron Limited

new patent

Low resistance source-drain contacts using high temperature silicides

a semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate.
International Business Machines Corporation

new patent

Semiconductor device and fabricating the same

a semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction..
Samsung Electronics Co., Ltd.

new patent

Method of forming semiconductor device

a semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively.
United Microelectronics Corp.

new patent

Semiconductor structure and forming the same

various embodiments provide semiconductor structures and methods for forming the same. In an exemplary structure, a substrate has a device region, a seal ring region surrounding the device region, and a dielectric layer disposed thereon.
Semiconductor Manufacturing International (shanghai) Corporation

new patent

Substrate and method

in an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug filling a first portion of the via, and a conductive liner layer that lines side walls of a second portion of the via and is electrically coupled to the conductive plug.
Infineon Technologies Ag

new patent

Selective cobalt removal for bottom up gapfill

exemplary methods for removing cobalt material may include flowing a chlorine-containing precursor into a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the chlorine-containing precursor to produce plasma effluents.
Applied Materials, Inc.

new patent

Fan-out semiconductor package

a fan-out semiconductor package includes a first connection member having a through-hole, first and second semiconductor chips disposed in the through-hole, an encapsulant encapsulating at least portions of the first connection member, the first semiconductor chip, and the second semiconductor chip, and a second connection member disposed on the first connection member and on active surfaces of the first semiconductor chip and the second semiconductor chip. A redistribution layer of the second connection member is respectively connected to both the first and second connection pads through first and second conductors, and the second conductor has a height greater than that of the first conductor..
Samsung Electro-mechanics Co., Ltd.

new patent

Air-cavity module with enhanced device isolation

the present disclosure relates to an air-cavity module having a thinned semiconductor die and a mold compound. The thinned semiconductor die includes a back-end-of-line (beol) layer, an epitaxial layer over the beol layer, and a buried oxide (box) layer with discrete holes over the epitaxial layer.
Qorvo Us, Inc.

new patent

Semiconductor structures and fabricating the same

a semiconductor structure is provided. The semiconductor structure includes a first substrate, an oxide layer formed on the first substrate, a second substrate formed on the oxide layer, a plurality of semiconductor devices formed in the second substrate, and a plurality of trenches formed in the second substrate and filled with an insulation material, wherein the trenches are separated from each other and one of the trenches surrounds one of the semiconductor devices.
Vanguard International Semiconductor Corporation

new patent

Handle substrate for use in manufacture of semiconductor-on-insulator structure and manufacturing thereof

a method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (box) of the final semiconductor-on-insulator structure.
Sunedison Semiconductor Limited (uen201334164h)

new patent

Electrically insulated fin structure(s) with alternative channel materials and fabrication methods

semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.. .
Globalfoundries Inc.

new patent

Interconnect structure including air gap

a method of forming a semiconductor structure is provided. A conductive layer is formed over a substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Airgap formation with damage-free copper

processing methods may be performed to remove unwanted materials from a substrate, such as an oxide footing. The methods may include forming an inert plasma within a processing region of a processing chamber.
Applied Materials, Inc.

new patent

Handler bonding and debonding for semiconductor dies

various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler.
International Business Machines Corporation

new patent

Handler bonding and debonding for semiconductor dies

various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler.
International Business Machines Corporation

new patent

Micro-transfer-printable flip-chip structures and methods

in certain embodiments, a method of making a semiconductor structure suitable for transfer printing (e.g., micro-transfer printing) includes providing a support substrate and disposing and processing one or more semiconductor layers on the support substrate to make a completed semiconductor device. A patterned release layer and, optionally, a capping layer are disposed on or over the completed semiconductor device and the patterned release layer or capping layer, if present, are bonded to a handle substrate with a bonding layer.
X-celeprint Limited

new patent

Wafer container with external passive getter module

a semiconductor wafer container assembly includes a container defining an exterior and defining an interior having a wafer storage area adapted to support one or more semiconductor wafers. The container also defines an opening in the container between the exterior and the interior.
Entegris, Inc.

new patent

Substrate liquid processing apparatus and method

the present invention relates to a substrate liquid processing apparatus which etches and cleans a substrate for a semiconductor. The substrate liquid processing apparatus comprises: a substrate supporting unit for supporting a substrate to be spaced apart from an upper portion of a table so that a surface to be processed faces a lower side; a rotational driving unit for driving a rotation axis which rotates the table; and a processing liquid supplying unit for supplying, in a processing space between the table and the substrate, processing liquid that is in a mist state in which a gas is mixed or processing liquid that is in a steam state.
Zeus Co., Ltd.

new patent

Removal methods for high aspect ratio structures

exemplary cleaning or etching methods may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. Methods may include forming a plasma within the remote plasma region to generate plasma effluents of the fluorine-containing precursor.
Applied Materials, Inc.

new patent

Sin spacer profile patterning

processing methods may be performed to form recesses in a semiconductor substrate. The methods may include oxidizing an exposed silicon nitride surface on a semiconductor substrate within a processing region of a semiconductor processing chamber.
Applied Materials, Inc.

new patent

Method and structure to control channel length in vertical fet device

a method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate..
Globalfoundries Inc.

new patent

Semiconductor structures and fabrication methods thereof

a method for fabricating a semiconductor structure includes providing a base structure, forming a dielectric layer on the base structure, forming a plurality of openings in the dielectric layer, forming a gate dielectric layer on bottom and sidewall surfaces of each opening, and forming an aluminum-containing work function layer on the gate dielectric layer in each opening. Along the direction from the gate dielectric layer to the top of the opening, the atomic concentration of aluminum atoms in the aluminum-containing work function layer decreases.
Semiconductor Manufacturing International (beijing) Corporation

new patent

Iii-v semiconductor diode

a stacked iii-v semiconductor diode having a p+ substrate with a dopant concentration of 5*1018 to 5*1020 cm−3, a layer thickness of 50-500 μm, and formed of a gaas compound, an n−-layer with a dopant concentration of 1014-1016 cm−3, a layer thickness of 10-300 μm, and formed of a gaas compound, an n+ layer with a dopant concentration of at least 1019 cm−3, a layer thickness less than 2 μm and formed of a gaas compound, wherein the n− layer and the n+ layer are materially connected to one another, a doped intermediate layer with a layer thickness of 5-50 μm and a dopant concentration of 1015-1017 cm−3 is placed between the p+ substrate and the n− layer, and the intermediate layer is materially connected to the p+ substrate and to the n− layer.. .
3-5 Power Electronics Gmbh

new patent

Methods for integrated circuit design and fabrication

the present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Thin film transistor and manufacturing the same, array substrate and manufacturing the same, display panel and display device

a method for manufacturing a thin film transistor is disclosed. The method includes: manufacturing a gate electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode on a substrate.
South China University Of Technology

new patent

Formation semiconductor device structure using patterning stacks

formation methods of a semiconductor device structure are provided. The method includes forming an under layer over a substrate, forming a middle layer over the under layer, and forming a patterned upper layer over the middle layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Method for cleaning, passivation and functionalization of si-ge semiconductor surfaces

a method for in-situ dry cleaning of a sige semiconductor surface, ex-situ degreases the ge containing semiconductor surface and removes organic contaminants. The surface is then dosed with hf (aq) or nh4f (g) generated via nh3+nh or nf3 with h2 or h2o to remove oxygen containing contaminants.
The Regents Of The University Of California

new patent

Fan-out semiconductor package

a fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The first connection member includes a first electromagnetic interference (emi) blocking part surrounding side surfaces of the semiconductor chip, the second connection member includes a second emi blocking part surrounding the redistribution layer, and the first emi blocking part and the second emi blocking part are connected to each other..
Samsung Electro-mechanics Co., Ltd.

new patent

Controlling etch rate drift and particles during plasma processing

the invention is an plasma processing system with a plasma chamber for processing semiconductor substrates, comprising: a radio frequency or microwave power generator coupled to the plasma chamber; a low pressure vacuum system coupled to the plasma chamber; and at least one chamber surface that is configured to be exposed to a plasma, the chamber surface comprising: a yxoyfz layer that comprises y in a range from 20 to 40%, o in a range from greater than zero to less than or equal to 60%, and f in a range of greater than zero to less than or equal to 75%. Alternatively, the yxoyfz layer can comprise y in a range from 25 to 40%, o in a range from 40 to 55%, and f in a range of 5 to 35% or y in a range from 25 to 40%, o in a range from 5 to 40%, and f in a range of 20 to 70%..
Tokyo Electron Limited

new patent

Switching device

the present disclosure proposes a switching device which, when supplying and interrupting power by combining a mechanical relay with a solid-state relay, suppresses the effects of chattering from the mechanical relay, and thus makes it possible to stably supply and interrupt power. Provided is the switching device including: a semiconductor relay configured to switch between supplying and interrupting power from a power supply; a mechanical relay configured to be connected in parallel to the semiconductor relay and connected at one end to a control terminal of the semiconductor relay; and a switch configured to switch between supplying and interrupting current to the semiconductor relay.
Sony Corporation

new patent

Magnetic pulse inducted transfer-type dc circuit breaker

the present invention discloses a magnetic pulse inducted transfer-type dc circuit breaker. The dc circuit breaker comprises a main current circuit and a transfer current circuit, the main current circuit comprising a combination of a fast mechanical switch or a mechanical switch with a power electronic device; the transfer current circuit comprises an arrester and a mutual inductor.
Xi'an Jiaotong University

new patent

Semiconductor storage device

according to one embodiment, a semiconductor storage device includes: a nand string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set.
Toshiba Memory Corporation

new patent

Semiconductor memory device and operating method thereof

a semiconductor memory device includes a reference voltage generation block suitable for selecting and outputting one of a plurality of reference voltages in response to a voltage division enable signal, as an input reference voltage, in response to a selection enable signal; and a control signal generation block suitable for generating the voltage division enable signal and the selection enable signal in response to a reference voltage information.. .
Sk Hynix Inc.

new patent

Semiconductor memory device and operating the same

provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory blocks, each including dummy cells coupled to dummy word lines and normal memory cells coupled to normal word lines, and a peripheral circuit configured to perform an erase operation on a memory block selected from among the plurality of memory blocks.
Sk Hynix Inc.

new patent

Memory with output control

an apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device.
Conversant Intellectual Property Management Inc.

new patent

Memory cells and semiconductor devices including ferroelectric materials

methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode.
Micron Technology, Inc.

new patent

Receiver circuit, and semiconductor device and system including the same

a receiver circuit may be provided. The receiver circuit may include a delay circuit and a synchronization circuit.
Sk Hynix Inc.

new patent

Semiconductor device and driving method thereof

brightness irregularities that develop in a light emitting device due to is persion among pixels in the threshold values of tfts used for supplying electric current to light emitting devices become obstacles to improved image quality of the light emitting device. As an image signal input to a pixel from a source signal line, a desired electric potential is applied to a gate electrode of a tft for supplying electric current to an el device, through a tft having its gate and drain connected to each other.
Semiconductor Energy Laboratory Co., Ltd.

new patent

System and extracting correlation curves for an organic light emitting device

a system for determining the efficiency degradation of an organic light emitting device (oled) in an array-based semiconductor device having an array of pixels that include oleds. The system determines the relationship between changes in an electrical operating parameter of the oleds and the efficiency degradation of said oleds, for at least one stress condition; measures a change in the electrical operating parameter of the oleds; determines the stress condition of at least one pixel or group of pixels in the semiconductor device; and uses the determined relationship and the determined stress condition to determine the efficiency degradation of the oleds corresponding to the measured change in the electrical operating parameter of the oleds..
Ignis Innovation Inc.

new patent

Semiconductor device and layout design method thereof

a semiconductor device is provided in which, as a result of the number of tap cells being suppressed while the laying out of signal interconnects is made easier, the total layout area can be reduced. The semiconductor device includes: a first logic circuit cell including a plurality of impurity regions that are arranged in a first conductivity type first semiconductor layer and a second conductivity type second semiconductor layer; a first tap cell including a first contact region and a second contact region that are respectively arranged in the first and second semiconductor layers and have a longitudinal direction in a first direction; a second logic circuit cell including a plurality of impurity regions that are arranged in a first conductivity type third semiconductor layer and a second conductivity type fourth semiconductor layer; and a second tap cell including a third contact region and a fourth contact region that are respectively arranged in the third and fourth semiconductor layers and have a longitudinal direction in a second direction that is different from the first direction..
Seiko Epson Corporation

new patent

Media quality aware ecc decoding method selection to reduce data access latency

a memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action..
Sk Hynix Memory Solutions Inc.

new patent

Semiconductor devices and semiconductor systems including the same

a semiconductor device and or system may be provided. The semiconductor system may include a first semiconductor device and a second semiconductor device.
Sk Hynix Inc.

new patent

Semiconductor device

the circuit scale of a semiconductor device that can perform arithmetic processing of analog data is reduced. In the semiconductor device, a memory cell is configured to generate a first current corresponding to first analog data and to generate a second current corresponding to the first analog data and second analog data.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor memory device

provided herein may be a semiconductor memory device. The semiconductor memory device may include a memory cell array including a plurality of memory cells, and a peripheral circuit disposed under the memory cell array.
Sk Hynix Inc.

new patent

Arithmetic circuit and a semiconductor device

a semiconductor device may include an input control circuit, a first operation control circuit, an arithmetic circuit and a second operation control circuit. The input control circuit may generate a read signal, write signal, a read address, and write address based on an external control signal.
Sk Hynix Inc.

new patent

Stripping process

this disclosure relates to a process for stripping an organic film on a patterned semiconductor substrate. The process includes treating the organic film with an aqueous stripper composition to remove the organic film in one step.
Fujifilm Electronic Materials U.s.a., Inc.

new patent

Method for fabricating semiconductor device

a method for fabricating a semiconductor device includes forming a pellicle including an amorphous carbon layer, attaching the pellicle onto a reticle, and forming a photoresist pattern by utilizing euv light transmitted through the pellicle and reflected by the reticle. The forming the pellicle includes forming a first dielectric layer on a first side of the substrate, forming the amorphous carbon layer on the first dielectric layer, forming a second dielectric layer on a second side of the substrate opposite to the first side of the substrate, etching the second dielectric layer overlapping the first region of the substrate to form a mask pattern, and forming a support including the second region of the substrate and the remaining part of the first dielectric layer.
Research & Business Foundation Sungkyunkwan University

new patent

Gate driver on array circuit based on low temperature poly-silicon semiconductor thin film transistor

the present disclosure proposes a goa circuit based on ltps tfts. A ninth tft is introduced to adjust the high and low voltage levels imposed on the second node p(n).
Wuhan China Star Optoelectronics Technology Co., Ltd.

new patent

Semiconductor device and manufacturing method thereof

first, half etching is performed to a semiconductor layer formed on an insulating layer to form trenches at positions of slab-portion regions in which slab portions are to be formed. After filling the trenches with an insulating film, a resist mask which covers the semiconductor layer at a projecting-portion region in which a projecting portion is to be formed and whose pattern ends are located on upper surfaces of the insulating films is formed on upper surfaces of the semiconductor layer and the insulating film, and full etching is performed to the semiconductor layer with using the resist mask and the insulating film as an etching mask, thereby forming an optical waveguide constituted of the projecting portion and the slab portions.
Renesas Electronics Corporation

new patent

Semiconductor device and manufacturing method thereof

in a semiconductor device, first dummy patterns including a different material from transmission lines (first optical waveguide and second optical waveguide) are formed in a first region close to the transmission lines, and second dummy patterns, which include the same material as the transmission lines and do not function as the transmission lines, are formed in a second region apart from the transmission lines.. .
Renesas Electronics Corporation

new patent

Solid state structure and detecting neutrinos

a solid state device and method are described for detecting and using neutrinos. In elementary particle physics there are only three stable particles: the proton, electron and neutrino.

new patent

Semiconductor wafer evaluation standard setting method, semiconductor wafer evaluation method, semiconductor wafer manufacturing process evaluation method, and semiconductor wafer manufacturing method

the method of setting the evaluation standard of a semiconductor wafer includes setting the a and b on the basis of an abnormal substances overlooking rate “a” specific to the light-scattering type surface inspection apparatus specified by an apparatus-induced abnormal substances overlooking rate Φ due to the light-scattering type surface inspection apparatus and a probabilistic abnormal substances overlooking rate, in which a is the number of times of inspection, b is an abnormal substances detection threshold, the apparatus-induced abnormal substances overlooking rate Φ is higher as the target abnormal substances size to be detected is smaller, and the probabilistic abnormal substances overlooking rate is lower as the number of times of inspection increases.. .
Sumco Corporation

new patent

Accurate multi-gas analyzer

a multi-gas analysis includes a semiconductor gas sensor driven by a constant resistance driver circuit with a driving current to obtain a sensing output of a gas in a gas sample. A processing unit is operable, based on a reference voltage from the constant resistance driver circuit associated with the driving current, in one of a gas-identification mode, where the gas is identified based on the sensing output obtained in response to fine variation of the operating temperature of the semiconductor gas sensor, and a gas-detection mode, where an analysis result indicative of the concentration of the gas is obtained based on the sensing output obtained in response to an optimal operating temperature of the semiconductor gas sensor..
Oriental System Technology Inc.

new patent

Gas sensor and using the same

a gas sensor includes: a semiconductor layer; a graphene film provided above the semiconductor layer and having at least a portion in contact with gas; and a barrier film between the semiconductor layer and the graphene film.. .
Fujitsu Limited

new patent

Gas sensor element

gas sensors are described herein that are useful for selectively detecting a second gas (e.g. Isoprene) in the presence of a first gas (e.g.
Nitto Denko Corporation

new patent

Method for evaluating semiconductor wafer

a method for evaluating a semiconductor wafer includes detecting semiconductor wafer lpds as an examination sample in two measurement modes, performing size classification of the lpds, calculating a distance between detection coordinates and a relative angle in the two measurement modes, presetting determination criteria to determine each lpd as a foreign matter or killer defect in accordance with each classified size, detecting semiconductor wafer lpds as an evaluation target in the two measurement modes, performing size classification of the lpds as the evaluation target, calculating a distance between detection coordinates and a relative angle of the evaluation target, and classifying the lpds detected on a surface of the evaluation target into the killer defect and the foreign mater based on a result of the calculation and the determination criteria. The method enables classifying all lpds from which quantitative size information cannot be provided, into the killer defect and foreign matter..
Shin-etsu Handotai Co., Ltd.

new patent

Methods for inspecting semiconductor wafers

methods and systems are presented for analysing semiconductor materials as they progress along a production line, using photoluminescence images acquired using line-scanning techniques. The photoluminescence images can be analysed to obtain spatially resolved information on one or more properties of said material, such as lateral charge carrier transport, defects and the presence of cracks.
Bt Imaging Pty Ltd.

new patent

System and calibration of optical signals in semiconductor process systems

the disclosure provides an optical calibration device for in-chamber calibration of optical signals associated with a processing chamber, a characterization system for plasma processing chambers, methods of characterizing plasma processing chambers, and a chamber characterizer. In one example, the optical calibration device includes: (1) an enclosure, (2) an optical source located within the enclosure and configured to provide a source light having a continuous spectrum, and (3) optical shaping elements located within the enclosure and configured to form the source light into a calibrating light that approximates a plasma emission during an operation within the processing chamber..
Verity Instruments, Inc.

new patent

Method and correction of pressure sensors

a differential pressure sensor includes one or more semiconductor dies which are thinned at portions of the die to create a chamber defining a sensitive diaphragm, having piezoresistive elements defined at a surface of the diaphragm. A first diaphragm is in fluid communication with a first fluid on an upper surface of the first diaphragm and is in fluid communication with a second fluid on a lower surface of the first diaphragm.
Measurement Specialties, Inc.

new patent

Pressure sensor sub assembly and fabrication

a differential pressure sensor includes a first sensor housing member having a first fluid inlet port for receiving a first fluid at a first pressure and a second sensor housing member having a second fluid inlet port for receiving a second fluid at a second pressure. A pressure-sensing subassembly includes a semiconductor pressure-sensing die having a sensitive diaphragm for sensing pressure.
Measurement Specialties, Inc.

new patent

Wireless sensor for detection and measurement of properties in liquids over an internet-based network

the present invention is related to a wireless sensor that combines semiconductor technology with chemical diffusion in order to measure specific chemical and physical properties such as ph, acid level, so2, temperature and liquid level of a target liquid in a container, and wirelessly delivers all the data to an internet-based computing network where the data can be accessed by an end user using a device connected to the internet, and a method to measure and analyze the chemical and physical properties of a target liquid using the wireless sensor, the method comprising immerging the wireless sensor into the target liquid in the container, measuring the chemical and physical properties of the target liquid, obtaining and analyzing data wirelessly through an internet-based computing network, wherein the target liquid can be an aqueous solution such as wine, spirits and beer.. .
Sapere Corporation

new patent

Three-dimensional scatterometry for measuring dielectric thickness

methodologies and an apparatus for enabling three-dimensional scatterometry to be used to measure a thickness of dielectric layers in semiconductor devices are provided. Embodiments include initiating optical critical dimension (ocd) scatterometry on a three-dimensional test structure formed on a wafer, the three-dimensional test structure comprising patterned copper (cu) trenches with an ultra-low k (ulk) dielectric film formed over the patterned cu trenches; and obtaining, by a processor, a thickness of the ulk dielectric film based on results of the ocd scatterometry..
Globalfoundries Inc.

new patent

Sensor

a sensor comprising a light component in support of a light source operable to direct a beam of light onto an imaging device having an image sensor, such as a ccd or cmos or n-type metal-oxide-semiconductor (nmos or live mos) sensor. The sensor can also comprise an imaging device positioned proximate to the light component and operable to receive the beam of light, and to convert this into an electric signal, wherein the light component and the imaging device are movable relative to one another, and wherein relative movement of the light component and the imaging device is determinable in multiple degrees of freedom.
Rememdia Lc

new patent

Lighting systems generating controlled and wavelength-converted light emissions

lighting system including light source having semiconductor light-emitting device configured for emitting light having first spectral power distribution along central axis. System includes volumetric lumiphor located along central axis configured for converting some light emissions having first spectral power distribution into light emissions having second spectral power distribution.
Ecosense Lighting Inc.

new patent

Compact light emitting diode chip and light emitting device including the same

a light emitting diode chip includes: a first conductive type semiconductor layer disposed on a substrate; a mesa disposed on the first conductive type semiconductor layer and including an active layer and a second conductive type semiconductor layer; at least one groove disposed on a side surface of the mesa forming a concave region; an extension electrode forming ohmic contact with the first conductive type semiconductor layer in the concave region; an insulation layer covering the extension electrode, the first conductive type semiconductor layer, and the mesa, and including at least one first opening exposing the extension electrode and a second opening; a first pad electrode disposed on the insulation layer and electrically connected to the first conductive type semiconductor layer through the first opening; and a second pad electrode disposed on the insulation layer and electrically connected to the second conductive type semiconductor layer through the second opening.. .
Seoul Viosys Co., Ltd.

new patent

System and increasing iii-nitride semiconductor growth rate and reducing damaging ion flux

systems and methods are disclosed for rapid growth of group iii metal nitrides using plasma assisted molecular beam epitaxy. The disclosure includes higher pressure and flow rates of nitrogen in the plasma, and the application of mixtures of nitrogen and an inert gas.
Georgia Tech Research Corporation

new patent

Substrate processing apparatus, manufacturing semiconductor device and vaporizer

a vaporization system includes a vaporization chamber having a first portion and a second portion. A first fluid supply part is connected to the first portion of the vaporization chamber, and configured to supply a mixed fluid in which a first carrier gas and a liquid precursor are mixed, toward the second portion.
Hitachi Kokusai Electric Inc.

new patent

Polyimide resin and film using same

this invention relates to a polyimide resin and a film using the same, wherein the polyimide resin is an imidized product of polyamic acid in which a polymerization composition including a diamine-based monomer and a dianhydride-based monomer is copolymerized, at least one of the diamine-based monomer and the dianhydride-based monomer including a monomer containing at least one selected from among an oxy group, a sulfone group and a fluoro group, the diamine-based monomer including at least one selected from among 1,3-bis(4-aminophenoxy)benzene and 2,2-bis[4-(4-aminophenoxy)phenyl]hexafluoropropane, and thus the polyimide resin has improved heat resistance and mechanical properties while being colorless and transparent and can thus be efficiently applied to a variety of fields, including semiconductor insulation layers, tft-lcd insulation layers, passivation layers, liquid crystal alignment layers, optical communication materials, protective layers for solar cells, and flexible display substrates.. .
Kolon Industries, Inc.

new patent

Semiconductor device and manufacturing method thereof

disclosed is a semiconductor device including a conductive shield layer formed within a cavity of a molding part and a manufacturing method thereof. Various aspects of the present invention, for example and without limitation, includes a semiconductor device including a conductive shield layer formed along the wall of a cavity to of a molding part to improve emi shielding performance, and a manufacturing method thereof..
Amkor Technology, Inc.

new patent

Bonding wire for semiconductor device

a bonding wire for a semiconductor device includes a cu alloy core material and a pd coating layer formed on a surface thereof. Containing an element that provides bonding reliability in a high-temperature environment improves the bonding reliability of the ball bonded part in high temperature.
Nippon Steel & Sumikin Materials Co., Ltd.

new patent

Methods of manufacturing semiconductor arrays

a method of manufacturing semiconductor arrays is provided. A method of manufacturing semiconductor arrays may comprise applying a functionalization layer to a semiconductor wafer surface, depositing probes on the functionalized semiconductor wafer surface, and processing the printed semiconductor wafer into individual semiconductor arrays.

Delay line system and switching apparatus with embedded attenuators

systems, methods, and apparatus for reducing standing wave reflections between delay line modules are described. The delay line modules include semiconductor switches, particularly mosfet switches fabricated on silicon-on-insulator (“soi”) and silicon-on-sapphire (“sos”) substrates and embedded attenuators..
Koppe Royalty B.v.

Semiconductor Energy Laboratory Co., Ltd.

. .

Nippon Steel & Sumikin Materials Co., Ltd.

. .

Power conversion device

a power conversion device such that heat dissipation can be improved is obtained. The power conversion device includes a power conversion circuit unit that converts direct current into alternating current using a semiconductor switching element, a heatsink on which the power conversion circuit unit is mounted, and which has a first passage through which a cooling medium is caused to pass, and a frame body that houses the power conversion circuit unit, seals the power conversion circuit unit between the frame body and the heatsink, and has a second passage through which a cooling medium is caused to pass, wherein the first passage and second passage are connected at an interface between the heatsink and frame body, thereby configuring a cooling passage..
Mitsubishi Electric Corporation

Semiconductor memory device performing randomization operation

provided herein is a semiconductor memory device. The semiconductor memory device may include a plurality of planes including a plurality of memory cells, read/write circuits coupled to the plurality of planes, respectively, and temporarily storing normal data inputted from an external device, random data, and parity data, and an error correction circuit generating the random data by randomizing the normal data, generating parity data for the random data during a program operation, correcting an error of the random data by using the parity data and de-randomizing the random data during a read operation..
Sk Hynix Inc.

Method of laying out a semiconductor device based on switching activity and semiconductor device produced thereby

a method of laying out a semiconductor device includes arranging a flip-flop in the semiconductor device, and rearranging the flip-flop to a selected location in the semiconductor device. The flip-flop may be configured to receive a clock from a clock gating cell through a clock line, to receive an input signal through an input line, and to output an output signal through an output line.
Samsung Electronics Co., Ltd.

Highly-efficient near-field thermophotovoltaics using surface-polariton emitters and thin-film photovoltaic-cell absorbers

a near-field thermophotovoltaic system comprises a hot emitter and a cold absorbing photovoltaic cell separated by a small gap. The emitter emits hot photons and includes a polaritonic material that supports a surface-polaritonic mode.
Massachusetts Institute Of Technology

Motor-driven integrated circuit and motor device

a motor-driven integrated circuit can include a bare die having an 8-bit microcontroller. The 8-bit microcontroller is fabricated by a 0.15 μm semiconductor process..
Johnson Electric S.a.

Converter and power conversion device including the same

a converter includes a first diode (d1) having its anode and cathode connected to input terminal (t0) and a first output terminal (t1), respectively, a second diode (d2) having its anode and cathode connected to a second output terminal (t2) and an input terminal (t0), respectively, and a bidirectional switch connected between the input terminal (t0) and a third output terminal (t3). The bidirectional switch includes third to sixth diodes (d3 to d6) and a transistor (q1).
Mitsubishi Electric Corporation

Precharge device and frequency converter

the present disclosure provides a precharge device and a frequency converter. The precharge device is applied in a flying capacitor type multi-level converter circuit, and the multi-level converter circuit includes: a flying capacitor, a bus capacitor, a first and second semiconductor components, wherein the first semiconductor component is electrically connected between a first end of the flying capacitor and a first end of the bus capacitor, and the second semiconductor component is electrically connected between a second end of the flying capacitor and a second end of the bus capacitor; and the precharge device includes: an ac source; and an auxiliary circuit electrically connected with the ac source, wherein the auxiliary circuit reuses the first and second semiconductor components, and the ac source charges the flying capacitor and the bus capacitor through the auxiliary circuit..
Delta Electronics,inc.

Control of electrical converter based on optimized pulse patterns

a method for operating an electrical converter including: determining an optimized pulse pattern from a fundamental voltage reference for the electrical converter, wherein the optimized pulse pattern is determined from a first lookup table and includes discrete voltage amplitude values changing at predefined switching instants; determining a harmonic content reference from the fundamental voltage reference based on a second lookup table, wherein the harmonic content reference is a harmonic current reference determined from the frequency spectrum of a current of the electrical converter or the harmonic content reference is a filtered voltage reference determined by applying a first order frequency filter to a voltage, which current or voltage is generated, when the optimized pulse pattern is applied to the electrical converter; determining a harmonic content error from the harmonic content reference by subtracting an estimated output voltage and/or estimated output current of the electrical converter from the harmonic content reference; modifying the optimized pulse pattern by timeshifting switching instants such that the fundamental voltage reference is tracked and the harmonic content error is corrected by the timeshifted switching instants; applying the modified optimized pulse pattern to semiconductor switches of the electrical converter.. .
Abb Schweiz Ag

Power semiconductor device

an inverter-control element operates with a power-supply potential supplied to an inverter-control-system power-supply terminal to output a signal for controlling an inverter switching element. A brake control element operates with a power-supply potential supplied to a brake-control-system power-supply terminal to output a signal for controlling a brake switching element.
Mitsubishi Electric Corporation

Method and system for a complementary metal oxide semiconductor wireless power receiver

methods and systems for a complementary metal oxide semiconductor wireless power receiver may include a receiver chip with an inductor, a configurable capacitance, and a rectifier. The method may include receiving an rf signal utilizing the inductor, extracting a clock signal from the received rf signal, generating a dc voltage utilizing a rectifier circuit, sampling the dc voltage, and adjusting the configurable capacitance based on the sampled dc voltage.

Nitride semiconductor laser element

a nitride semiconductor laser element includes an electron barrier layer between a p-side light guide layer and a p-type clad layer. The electron barrier layer has a bandgap energy larger than that of the p-type clad layer.
Panasonic Corporation

Photoelectric conversion element and optical communication module

a surface emitting element including a semiconductor substrate and a casing. The substrate includes an optical element having a photoelectric conversion function.
Murata Manufacturing Co., Ltd.

Semiconductor device package and manufacturing the same

various embodiments of the present disclosure relate to a semiconductor device package including a carrier, an electrical component, an antenna, a conductive pad and a conductive line. The carrier includes a top surface.
Advanced Semiconductor Engineering, Inc.

Electronic device and fabricating the same

electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material..
Sk Hynix Inc.

Methods of manufacturing a magnetic field sensor

a semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “z” axis magnetic field onto sensors orientated in the xy plane..
Everspin Technologies, Inc.

Method of manufacturing semiconductor device

a method of manufacturing a semiconductor device includes disposing a substrate metal film on an upper surface of a substrate made of a metal; disposing a first element metal film on a lower surface of a first element; disposing a second element metal film on a lower surface of a second element; bonding the first element and the second element to the substrate so that an upper surface of the substrate metal film is in contact with a lower surface of the first element metal film and a lower surface of the second element metal film; oxidizing at least a portion of a region of the upper surface of the substrate metal film other than regions in contact with the first element metal film and the second element metal film; and disposing a wiring electrically connecting the first element and the second element, across and above the region oxidized.. .
Nichia Corporation

Semiconductor light emitting device

a semiconductor light emitting device includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer; and an insulating layer on the light emitting structure and including first and second through-holes. The insulating layer includes a first lower insulating layer and a second lower insulating layer.
Samsung Electronics Co., Ltd.

Light-emitting device and preparing same, optical semiconductor element mounting package, and optical semiconductor device using the same

an optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes..
Hitachi Chemical Company, Ltd.

Semiconductor light emitting device

to improve light emission efficiency and suppress color unevenness on a light emitting surface. Provided is a semiconductor light emitting device including a light emitting element, a wavelength conversion layer for converting light emitted from the light emitting element to light having a predetermined wavelength, a light reflection member covering at least the side surfaces of the wavelength conversion layer, and a thin film provided on the outermost surface from which the light wavelength-converted by the wavelength conversion layer exits, having a property for shedding the uncured light reflection member, and having a coarse surface..
Stanley Electric Co., Ltd.

Light emitting diode

an led includes a first-type semiconductor layer, a light emitting layer, a second-type semiconductor layer, a first metal layer, a first current conducting layer, a first bonding layer, and a second current conducting layer. The light emitting layer is located between the first-type semiconductor layer and the second-type semiconductor layer.
Genesis Photonics Inc.

Optoelectronic semiconductor device, producing an electrical contact and producing a semiconductor device

an optoelectronic semiconductor device includes a semiconductor body having a semiconductor region and an active region, wherein the semiconductor region has a covering layer forming a radiation passage surface of the semiconductor body on a side facing away from the active region, the semiconductor region has a current-spreading layer arranged between the covering layer and the active region; the semiconductor device has a contact for the electrical contacting of the semiconductor region; the contact adjoins the current-spreading layer in a terminal area; the contact adjoins the covering layer in a barrier region; and the barrier region runs parallel to the active region and is arranged closer to the active region than the radiation passage surface.. .
Osram Opto Semiconductors Gmbh

Light-emitting device and manufacturing method thereof

a light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer and an active layer formed therebetween; a surrounding exposed region formed on peripheries of the semiconductor stack, exposing a surface of the first semiconductor layer; a conductive layer formed on the second semiconductor layer, including a first conductive region extending toward and contacting the surface of the first semiconductor layer in the surrounding exposed region; an electrode layer formed on the surrounding exposed region, surrounding the semiconductor stack, contacting the conductive layer and including an electrode pad not overlapping the semiconductor stack; an outside insulating layer covering a portion of the conductive layer and the electrode layer, including a first opening exposing the other portion of the conductive layer; a bonding layer covering the outside insulating layer and electrically connecting to the other portion of the conductive layer through the first opening; and a conductive substrate.. .
Epistar Corporation

Solar cell having a plurality of sub-cells coupled by a metallization structure

solar cells having a plurality of sub-cells coupled by metallization structures, and singulation approaches to forming solar cells having a plurality of sub-cells coupled by metallization structures, are described. In an example, a solar cell, includes a plurality of sub-cells, each of the sub-cells having a singulated and physically separated semiconductor substrate portion.
Sunpower Corporation

Semiconductor film and semiconductor element

the present invention relates to an application liquid for forming a semiconductor film, the application liquid comprising: an inorganic semiconductor particle; and a compound having a relative permittivity of 2 or more or a compound having reducing power against the inorganic semiconductor particle; a method for producing a semiconductor film comprising a step of applying the application liquid; a semiconductor film and a semiconductor element comprising the semiconductor film; and a method for producing the semiconductor element.. .
Tohoku University

Thin-film transistor substrate

a thin-film transistor (tft) substrate is provided which includes: a substrate; a tft disposed above the substrate; and a capacitor disposed above the substrate and electrically connected with the tft, wherein the capacitor includes: a lower electrode layer disposed above the substrate and including an electrically conductive material as a main component; an upper electrode layer disposed above and opposed to the lower electrode layer and including, as a main component, an oxide semiconductor material to which electrical conductivity is given; and a capacitor insulating layer disposed between the lower electrode layer and the upper electrode layer. An extension extending outward from at least a portion of the outer edge of the lower electrode layer in plan view is provided to the lower electrode layer.
Joled Inc.

Ferroelectric device and manufacturing same

a ferroelectric device and a manufacturing method are provided. While holding a nonvolatile memory retention capability and a multiple rewriting endurance as the distinctive features of a ferroelectric device, the disclosed ferroelectric device is wider in memory window and more adaptively made microfiner than a conventional ferroelectric device that has used a ferroelectric mainly constituted of sr—bi—ta—o as an oxide of strontium, bismuth and tantalum.
Wacom R&d Corporation

Thin film transistor substrate, manufacturing the same, and display apparatus having the same

a thin film transistor substrate includes a thin film transistor including a gate electrode, a semiconductor layer, a source electrode and a drain electrode. Each of the source electrode and the drain electrode includes a wire layer and a protective layer.
Samsung Display Co., Ltd.

Semiconductor substrate structures, semiconductor devices and methods for forming the same

a semiconductor substrate structure includes a substrate having a first conductivity type, an oxide layer disposed on the substrate, and a semiconductor layer disposed on the oxide layer. The semiconductor substrate structure also includes a first buried layer disposed in the semiconductor layer, having a second conductivity type opposite to the first conductivity type.
Vanguard International Semiconductor Corporation

Field effect transistor device with separate source and body contacts and producing the device

the field effect transistor device comprises a substrate (1) of semiconductor material, a body well of a first type of electric conductivity in the substrate, a source region in the body well, the source region having an opposite second type of electric conductivity, a source contact (3) on the source region, a body contact region of the first type of electric conductivity in the body well, a body contact (5) on the body contact region, and a gate electrode layer (2) partially overlapping the body well. A portion (2*) of the gate electrode layer (2) is present between the source contact (3) and the body contact (5)..
Ams Ag

Semiconductor device and fabricating the same

a semiconductor device and a method for fabricating the same are provided. The semiconductor device includes first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent a first channel region and comprises a first gate insulating film having a first thickness formed on the first channel region, a first function film having a second thickness formed on the first gate insulating film and a first filling film having a third thickness formed on the first function film, wherein the second gate stack structure is formed adjacent a second channel region and comprises a second gate insulating film having the first thickness formed on the second channel region, a second function film having the second thickness formed on the second gate insulating film and a second filling film having the third thickness formed on the second function film, wherein the first and second function films, respectively, comprise tin and si concentrations that are different from each other..
Samsung Electronics Co., Ltd.

Power mosfets and methods for manufacturing the same

a semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a substrate, a source region, a drain region, a filed plate and a gate electrode.
Taiwan Semiconductor Manufacturing Company Ltd.

Semiconductor device isolation with resurf layer arrangement

a device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate, a body region disposed in the semiconductor substrate within the doped isolation barrier and in which a channel is formed during operation, an isolation contact disposed at the semiconductor substrate and to which a voltage is applied during operation, and a plurality of reduced surface field (resurf) layers disposed in the semiconductor substrate, the plurality of reduced surface field (resurf) layers being arranged in a stack between the body region and the isolation contact.. .
Nxp Usa, Inc.

Semiconductor device and manufacturing semiconductor device

to provide a semiconductor device having a substrate contact in a deep trench thereof and having an improved characteristic. A pvd-metal film (metal film formed by pvd) is used as a first barrier metal film which is a lowermost layer barrier metal film formed in a deep trench penetrating an n type epitaxial layer and a reaching a layer therebelow.
Renesas Electronics Corporation

Ruggedized symmetrically bidirectional bipolar power transistor

the present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on both sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “b-tran” type.
Ideal Power, Inc.

Semiconductor strips with undercuts and methods for forming the same

an integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip.
Taiwan Semiconductor Manufacturing Company, Ltd.

Methods of forming gate electrodes on a vertical transistor device

one illustrative method of forming a vertical transistor device disclosed herein includes, among other things, forming bottom source/drain (s/d) regions. A plurality of vertically oriented channel semiconductor structures is formed above the bottom source/drain (s/d) regions.
Globalfoundries Inc.

Semiconductor structures having increased channel strain using fin release in gate regions

a method of introducing strain in a channel region of a finfet device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the finfet device so as to release the upper portion of the fin structure from the substrate in the channel region.. .
International Business Machines Corporation

Semiconductor device and fabrication method thereof

semiconductor devices and fabrication methods thereof are provided. An exemplary semiconductor device includes a base substrate; a gate structure group, having a plurality of gate structures, formed over the base substrate; first source/drain doping regions formed in the base substrate between adjacent gate structures; second source/drain doping regions formed in the base substrate at two sides of the gate structure group, respectively; a first conductive layer formed on a surface of each of the first source/drain doping regions.
Semiconductor Manufacturing International (beijing) Corporation

Spatially decoupled floating gate semiconductor device

a method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.. .
International Business Machines Corporation

Gate structures

the present disclosure generally relates to semiconductor structures and, more particularly, to gate structures with minimized gate thickness loss and methods of manufacture. The structure includes: a plurality of gate structures; a film layer provided over the gate structures and adjacent to the gate structures; and a planarized cap layer on the film and over the plurality of gate structures, the planarized cap layer having a different selectivity to slurry of a chemical mechanical polishing (cmp) process than the film..
Globalfoundries Inc.

Semiconductor device and fabricating the same

a semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.. .
Samsung Electronics Co., Ltd.

Self-aligned contact protection using reinforced gate cap and spacer portions

a method includes providing a starting structure, the starting structure including a semiconductor substrate, sources and drains, a hard mask liner layer over the sources and drains, a bottom dielectric layer over the hard mask liner layer, metal gates between the sources and drains, the metal gates defined by spacers, gate cap openings between corresponding spacers and above the metal gates, and a top dielectric layer above the bottom dielectric layer and in the gate cap openings, resulting in gate caps. The method further includes removing portions of the top dielectric layer, the removing resulting in contact openings and divot(s) at a top portion of the spacers and/or gate caps, and filling the divot(s) with etch-stop material, the etch-stop material having an etch-stop ability better than a material of the spacers and gate cap.
Globalfoundries Inc.

Semiconductor device

a semiconductor device includes: a substrate having an active region; a gate structure disposed in the active region; source/drain regions respectively formed within portions of the active region disposed on both sides of the gate structure; a metal silicide layer disposed on a surface of each of the source/drain regions; and contact plugs disposed on the source/drain regions and electrically connected to the source/drain regions through the metal silicide layer, respectively. The metal silicide layer is formed so as to have a monocrystalline structure..
Samsung Electronics Co., Ltd.

Device isolation using preferential oxidation of the bulk substrate

a method includes providing a structure including a substrate, a buffer layer formed on the substrate and a semiconductor layer formed on the buffer layer, etching the semiconductor layer so as to form a fin and exposing the buffer layer, etching the buffer layer such that a portion of the buffer layer, disposed under the fin, is exposed, and oxidizing the buffer layer and fin so as to form an oxide layer under the fin.. .
International Business Machines Corporation

Device isolation using preferential oxidation of the bulk substrate

a structure includes a semiconductor substrate, a semiconductor buffer layer disposed on the semiconductor substrate, an oxide layer disposed on the buffer layer, and a fin including a semiconductor material disposed on the oxide layer. The fin and the buffer layer are epitaxially aligned to the semiconductor substrate..
International Business Machines Corporation

Scandium-containing iii-n etch-stop layers for selective etching of iii-nitrides and related materials

a semiconductor device structure including a scandium (sc)- or yttrium (y)-containing material layer situated between a substrate and one or more overlying layers. The sc- or y-containing material layer serves as an etch-stop during fabrication of one or more devices from overlying layers situated above the sc- or y-containing material layer.
The Government Of The United States Of America, As Represented By The Secretary Of The Navy

Nanotube termination structure for power semiconductor devices

semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes an array of termination cells formed in the termination area, the array of termination cells including a first termination cell at an interface to the active area to a last termination cell, each termination cell in the array of termination cells being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the last termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width..
Alpha And Omega Semiconductor Incorporated

Nanostructure field-effect transistors with enhanced mobility source/drain regions

structures and fabrication methods for vertical-transport field-effect transistors. A nanostructure, a gate structure coupled with the nanostructure, and a source/drain region coupled with an end of the nanostructure are formed.
Globalfoundries Inc.

Laterally diffused metal oxide semiconductor field-effect transistor and manufacturing method therefor

provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first n well (22), a first p well (24) and a channel region shallow trench isolating structure (42) are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (52); performing photoetching and ion injection to form a second n well (32) in the first n well and form a second p well (34) in the first p well; forming a polysilicon gate (62) and a gate oxide layer on the surface of the wafer; and photoetching and injecting n-type ions to form a drain electrode (72) and a source electrode (74)..
Csmc Technologies Fab2 Co., Ltd.

Semiconductor device and manufacturing method therefor

a semiconductor device includes a drift layer formed of a first conductive type semiconductor material, a mosfet part including a p-type base layer provided on a front surface of the drift layer, a first n-type buffer layer provided on a reverse side of the drift layer, and a second n-type buffer layer provided on a reverse side of the first n-type buffer layer and having a high impurity concentration. The first n-type buffer layer has a higher impurity concentration than the drift layer and has a total amount of electrically active impurities per unit area of 1.0×1012 cm−2 or less..
Mitsubishi Electric Corporation

Semiconductor device

a semiconductor device includes a semiconductor layer of a first conductivity type, an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer, a terminal region of the second conductivity type that is formed in the surface layer portion of the semiconductor layer along a peripheral edge of the impurity region and that has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the impurity region, and a surface electrode that is formed on the semiconductor layer and that has a connection portion connected to the impurity region and to the terminal region.. .
Rohm Co., Ltd.

Semiconductor device

in a semiconductor device, an algan layer includes a first algan layer and a second algan layer. The second algan layer is positioned between a gate structure portion and a drain electrode and is divided into multiple parts in an arrangement direction in which the gate structure portion and the drain electrode are arranged.
Denso Corporation

Integrated capacitor with sidewall having reduced roughness

a method of forming an integrated capacitor on a semiconductor surface on a substrate includes etching a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate which is above and electrically isolated from the semiconductor surface to provide at least one defined dielectric feature having sloped dielectric sidewall portion. A dielectric layer is deposited to at least partially fill pits in the sloped dielectric sidewall portion to smooth a surface of the sloped dielectric sidewall portion.
Texas Instruments Incorporated

Integrated trench capacitor with top plate having reduced voids

a method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer.
Texas Instruments Incorporated

High breakdown voltage passive element and high breakdown voltage passive element manufacturing method

warping of a semiconductor wafer occurring due to a difference in the thermal expansion rates of an insulating film and the semiconductor wafer is restricted. Therefore, processing failures and conveying failures in the manufacturing process, as well as cracking of the semiconductor wafer, are restricted.
Fuji Electric Co., Ltd.

Semiconductor device, input/output device, and electronic appliance

a flexible input/output device and an input/output device having high resistance to repeated bending are provided. The input/output device includes a first flexible substrate, a first insulating layer over the first substrate, a first transistor over the first insulating layer, a light-emitting element over and electrically connected to the first transistor and including an el layer between first and second electrodes, a first bonding layer over the light-emitting element, a sensing element and a second transistor over the first bonding layer and electrically connected to each other, a second insulating layer over the sensing element and the second transistor, and a second flexible substrate over the second insulating layer.
Semiconductor Energy Laboratory Co., Ltd.

Solid-state imaging device and imaging system

a solid-state imaging device includes: a first semiconductor substrate including a photoelectric conversion element; and a second semiconductor substrate including at least a part of a peripheral circuit arranged in a main face of the second semiconductor substrate, the peripheral circuit generating a signal based on the charge of the photoelectric conversion element, a main face of the first semiconductor substrate and the main face of the second semiconductor substrate being opposed to each other with sandwiching a wiring structure therebetween; a pad to be connected to an external terminal; and a protection circuit electrically connected to the pad and to the peripheral circuit, wherein the protection circuit is arranged in the main face of the second semiconductor substrate.. .
Canon Kabushiki Kaisha

Semiconductor device

provided is a semiconductor device including: a first substrate having a first primary surface, a second primary surface, and a side surface; a semiconductor element formed on the first primary surface; a first electrode formed on the first primary surface and connected to the semiconductor element on the first primary surface; a second electrode formed on the second primary surface; a through-electrode formed so as to penetrate the first substrate and connecting the first electrode and the second electrode to each other; a second substrate bonded to the first substrate so as to face the first primary surface; and a third electrode formed on the side surface of the first substrate and connected to the second electrode.. .
Canon Kabushiki Kaisha

Image sensor for high photoelectric conversion efficiency and low dark current

example embodiments relate to an image sensor configured to achieve a high photoelectric conversion efficiency and a low dark current. The image sensor includes first and second electrodes, a plurality of photodetection layers provided between the first and second electrodes, and an interlayer provided between the photodetection layers.
Samsung Electronics Co., Ltd.

Semiconductor device and semiconductor-device manufacturing method

it is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line.
Sony Corporation

Solid-state image pickup apparatus and image pickup system using solid-state image pickup apparatus

a solid-state image pickup apparatus includes a photoelectric conversion unit, a charge storage unit, and a floating diffusion unit, all disposed on a semiconductor substrate. The solid-state image pickup apparatus further includes a first gate electrode disposed on the semiconductor substrate and extending between the photoelectric conversion unit and charge storage unit, and a second gate electrode disposed on the semiconductor substrate and extending between the charge storage unit and the floating diffusion unit.
Canon Kabushiki Kaisha

Interconnect structure for stacked device and method

a stacked integrated circuit (ic) device and a method are disclosed. The stacked ic device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element.
Taiwan Semiconductor Manufacturing Company, Ltd.

Image pickup element, manufacturing image pickup element, and electronic apparatus

an image pickup element includes: a semiconductor substrate including a photoelectric conversion section for each pixel; a pixel separation groove provided in the semiconductor substrate; and a fixed charge film provided on a light-receiving surface side of the semiconductor substrate, wherein the fixed charge film includes a first insulating film and a second insulating film, the first insulating film being provided contiguously from the light-receiving surface to a wall surface and a bottom surface of the pixel separation groove, and the second insulating film being provided on a part of the first insulating film, the part corresponding to at least the light-receiving surface.. .
Sony Corporation

Solid-state image pickup unit, manufacturing solid-state image pickup unit, and electronic apparatus

a solid-state image pickup unit includes: a p-type compound semiconductor layer of a chalcopyrite structure; an electrode formed on the p-type compound semiconductor layer; and an n-type layer formed separately for each pixel, on a surface opposite to a light incident side of the p-type compound semiconductor layer.. .
Sony Semiconductor Solutions Corporation

Ltps array substrate and producing the same

an ltps array substrate and a method for producing the same are proposed. The method includes: forming an insulating layer, a semiconductor layer, and a first positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a source and a drain of the tft on the polycrystalline silicon layer; forming a pixel electrode on the insulating layer and part of the source; forming a plain passivation layer on a source-drain electrode layer; forming a transparent electrode layer on the plain passivation layer so that the transparent electrode layer is connected to the gate, the source, and the drain via the contact hole.
Wuhan China Star Optoelectronics Technology Co., L Td

Ltps array substrate and producing the same

an ltps array substrate and a method for producing the same are proposed. The method includes: forming a gate of a thin-film transistor (tft) of the ltps array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a second insulating layer on the substrate of the polycrystalline silicon layer; forming a source and a drain of the tft on the second insulating layer so that the source and the drain is electrically connected to the polycrystalline silicon layer via a contact hole.
Wuhan China Star Optoelectronics Technology Co., Ltd

Printable device wafers with sacrificial layers

methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (soi) substrate, which includes a first portion of the semiconductor active layer.
X-celeprint Limited

Display device

a display device having a gate driver which may reduce generation of ripple at the output of the gate drive includes: a substrate; and a driver circuit including a thin film transistor disposed on the substrate, the thin film transistor including: a first gate electrode disposed on the substrate; a semiconductor layer disposed on the first gate electrode to overlap a part of the first gate electrode, the semiconductor layer including channel, source, and drain regions; a second gate electrode disposed on the semiconductor layer; and a source electrode and a drain electrode disposed on the semiconductor layer and respectively connected to the source region and the drain region, wherein a first area formed by the overlapping portion of the first gate electrode and the drain region has a different size than a second area formed by the overlapping portion of the first gate electrode and the source region.. .
Samsung Display Co., Ltd.

Method of manufacturing top-gate thin film transistor and top-gate thin film transistor thereof

a method of manufacturing a top-gate thin film transistor and a top-gate thin film transistor thereof are described. The method of manufacturing a top-gate thin film transistor includes providing a glass substrate; forming an oxide semiconductor layer on the glass substrate, wherein the oxide semiconductor layer comprises a source region, a drain region and a channel region; forming a gate insulation layer on the oxide semiconductor layer corresponding to a position of the channel region; forming a gate electrode on the gate insulation layer; depositing an interlayer dielectric layer a surface of the gate electrode, a surface of the oxide semiconductor layer, and a surface of the glass substrate by a chemical vapor deposition method; forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are electrically connected to the source region and the drain region of the oxide semiconductor layer..
Shenzhen China Star Optoelectronics Technology Co. Ltd.

Process for fabricating 3d memory

a process for fabricating a 3d memory is shown. Linear stacks, each of which includes alternately stacked gate lines and insulating layers, are formed.
Macronix International Co., Ltd.

Semiconductor memory device

a semiconductor memory device includes a first electrode layer extending in a first direction, a second electrode layer above the first electrode layer and extending in the first direction, a third electrode layer above the first electrode layer and extending in the first direction, an insulating member between the second and third electrode layers and extending in the first direction, first semiconductor members extending in the second direction through the first and second electrodes, second semiconductor members extending in the second direction through the first and third electrode layers, and third semiconductor members extending in the second direction, each having a first portion between the second and third electrode layers and in contact with the insulating member, and a second portion extending through the first electrode layer. In the first direction, an arrangement density of the third semiconductor members is lower than that of the first or second semiconductor member..
Toshiba Memory Corporation

Semiconductor memory device

a semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell array region through bit lines, wherein at least one of the bit lines has a curved structure toward the word line contact region. According to an embodiment, a misalignment between a cell plug and a contact plug caused by a natural cell plug bending phenomenon may be reduced to improve operational reliability of a semiconductor memory device..
Sk Hynix Inc.

Method for manufacturing semiconductor device

provided herein is a method of manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: alternately stacked first material layers and second material layers on a lower structure; forming first holes passing through the first material layers and the second material layers, each of the first holes defining a channel region; removing the second material layers through the first holes such that interlayer spaces between the first material layers are formed; and forming, through the first holes, conductive patterns which fill respective interlayer spaces..
Sk Hynix Inc.

Semiconductor device including channel structure

a semiconductor device includes a stacked structure disposed on a semiconductor substrate. The stacked structure includes interlayer insulating layers and gate electrodes, alternately stacked.

Transistors having dielectric material containing non-hydrogenous ions and methods of their fabrication

methods for fabricating a transistor include forming a dielectric material adjacent to a semiconductor, introducing non-hydrogenous ions into the dielectric material, and forming a control gate adjacent to the dielectric material. Transistors include source/drain regions in a semiconductor, a dielectric material adjacent to the semiconductor and containing non-hydrogenous ions, and a control gate adjacent to the dielectric material.
Micron Technology, Inc.

Semiconductor device and manufacturing method thereof

a semiconductor device includes gate stacked structures surrounding channel layers, a common source line filling a separation area between the gate stacked structures adjacent to each other and having an upper surface including first concave portions, and a support insulating layer filling the first concave portions and having sidewalls facing portions of the channel layers.. .
Sk Hynix Inc.

Semiconductor device and manufacturing the same

a semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first channel layers arranged in a first direction.
Sk Hynix Inc.

Three-dimensional memory device with electrically isolated support pillar structures and making thereof

a first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure.
Sandisk Technologies Llc

Simple integration of non-volatile memory and complementary metal oxide semiconductor

a method that allows integrating complementary metal oxide semiconductor (cmos) transistors and a non-volatile memory (nvm) transistor on a single substrate is provided. The nvm transistor includes a gate stack containing a high-k tunneling gate dielectric, a floating gate electrode, a high-k control gate dielectric and a control gate electrode.
International Business Machines Corporation

Semiconductor memory device and manufacturing the same

a semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part.
Toshiba Memory Corporation

Transistors and memory arrays

some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post region on one side of the trench and a second post region on an opposing side of the trench.
Micron Technology, Inc.

Semiconductor device

a semiconductor device includes a substrate including an active region and an element isolation region defining the active region, a gate trench extending into the element isolation region and penetrating the active region, and a gate structure filling the gate trench and including a first conductivity-type semiconductor layer, a conductive layer, and a second conductivity-type semiconductor layer, sequentially stacked from a lower portion of the gate trench.. .
Samsung Electronics Co., Ltd.

Semiconductor device having buried gate structure and fabricating the same

a semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench..
Samsung Electronics Co., Ltd.

Forming doped regions in semiconductor strips

a method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor integrated circuit device having a standard cell which includes a fin

disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor.
Socionext Inc.

Multi-layer semiconductor device structure

one embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a substrate and a first gate layer disposed on the active layer, where at least one of the first active layer and the first gate layer includes a first layer alignment structure; a first bounding layer disposed over the first device layer, the first bounding layer including an opening arranged to detectably expose the first layer alignment structure; and a second device layer disposed over the bounding layer including a second layer alignment structure, where the second layer alignment structure is substantially aligned to the first layer alignment structure through the opening.. .
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

a semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region.
Samsung Electronics Co., Ltd.

Ultrasonic transducers in complementary metal oxide semiconductor (cmos) wafers and related apparatus and methods

micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (cmos) wafers are described, as are methods of fabricating such devices. A metallization layer of a cmos wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer.
Butterfly Network, Inc.

Semiconductor device and manufacturing semiconductor device

a semiconductor device includes a first active pattern extending in a first direction on a first region and a second region of a substrate, a first dummy gate electrode extending in a second direction crossing the first active pattern between the first region and the second region, a contact structure contacting the first dummy gate electrode and extending in the first direction, and a power line disposed on the contact structure and electrically connected to the contact structure. The power line extends in the first direction.
Samsung Electronics Co., Ltd.

Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same

a semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (fets) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is m3 or higher.
Samsung Electronics Co., Ltd.

Stacked semiconductor package

provided is a stacked semiconductor package, which has various kinds of semiconductor chips with various sizes and is capable of miniaturization. The stacked semiconductor package includes a base substrate layer and a sub semiconductor package disposed on a top surface of the base substrate layer.
Samsung Electronics Co., Ltd.

Semiconductor package and manufacturing the semiconductor package

a semiconductor package includes a package substrate having an upper surface and a lower surface and including a plurality of substrate pads formed on the upper surface, a capacitor structure arranged on the upper surface of the package substrate and including a semiconductor substrate and at least one decoupling capacitor formed in the upper surface of the semiconductor substrate, a plurality of first semiconductor chips mounted on the package and supported by the capacitor structure, first conductive connection members electrically connecting chip pads of the first semiconductor chips to the substrate pads, and second conductive connection members electrically connecting capacitor pads of the decoupling capacitor to the substrate pad.. .
Samsung Electronics Co., Ltd.

Semiconductor light-emitting device

a semiconductor light emitting device (a) includes an elongated substrate (1) formed with a through-hole (11), a first, a second and a third semiconductor light emitting elements (3r, 3g, 3b) mounted on the main surface of the substrate (1), and an electrode (2r) electrically connected to the first semiconductor light emitting element (3r) and extending to the reverse surface of the substrate (1) via the through-hole (11). The first semiconductor light emitting element (3r) and the through-hole (11) are positioned between the second semiconductor light emitting element (3g) and the third semiconductor light emitting element (3b) in the longitudinal direction of the substrate (1).
Rohm Co., Ltd.

Semiconductor die assemblies having molded underfill structures and related technology

a semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die.
Micron Technology, Inc.

Semiconductor structure and manufacturing method thereof

a method of manufacturing a semiconductor structure includes providing a substrate including a redistribution layer (rdl) disposed over the substrate, disposing a first patterned mask over the rdl, disposing a first conductive material over the rdl exposed from the first patterned mask to form a first conductive pillar, removing the first patterned mask, disposing a second patterned mask over the rdl, disposing a second conductive material over the rdl exposed from the second patterned mask to form a second conductive pillar, removing the second patterned mask, disposing a first die over the first conductive pillar, and disposing a second die over the second conductive pillar. A height of the second conductive pillar is substantially greater than a height of the first conductive pillar..
Taiwan Semiconductor Manufacturing Company Ltd.

Substrate based fan-out wafer level packaging

a method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding.
Unisem (m) Berhad

Substrate based fan-out wafer level packaging

a method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding.
Unisem (m) Berhad

Method for making semiconductor device with sidewall recess and related devices

a method is for making a semiconductor device. The method may include providing a lead frame having a recess, forming a sacrificial material in the recess of the lead frame, and mounting an ic on the lead frame.
Stmicroelectronics, Inc.

Method for bonding semiconductor chips to a landing wafer

a method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface.
Katholieke Universiteit Leuven

Bonding wire for semiconductor device

strength ratio=ultimate strength/0.2% offset yield strength.  (1). .

Semiconductor package, manufacturing method thereof, and electronic element module using the same

a semiconductor package includes a board part including a core layer having an element accommodating region disposed therein, and build-up layers disposed on top and bottom surfaces of the core layer; an electronic element disposed in the element accommodating region; and block conductors disposed on the build-up layers and electrically connected to terminals of the electronic element.. .
Samsung Electro-mechanics Co., Ltd.

Semiconductor package and semiconductor manufacturing process

a semiconductor package includes a semiconductor substrate structure, a semiconductor die and an encapsulant. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post.
Advanced Semiconductor Engineering, Inc.

Semiconductor package device and manufacturing the same

the present disclosure provides a semiconductor package device comprising: (1) a substrate comprising a first area and a second area; (2) a semiconductor device on the first area of the substrate; (3) an antenna pattern on the second area of the substrate; (4) a first electronic component on the antenna pattern; and (5) a first package body encapsulating the first area of the substrate and the semiconductor device and exposing the antenna pattern, the first electronic component and the second area of the substrate. An upper surface of the first package body is non-coplanar with the antenna pattern on the second area of the substrate..
Advanced Semiconductor Engineering, Inc.

Semiconductor device structure

a semiconductor device structure is provided. The semiconductor device structure includes a first device.
Taiwan Semiconductor Manufacturing Co., Ltd.

Visual identification of semiconductor dies

systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies.
Texas Instruments Incorporated

Semiconductor device

a semiconductor device includes a substrate including a plurality of chip areas and a scribe line defined thereon, and a mark pattern disposed in the scribe line. The mark pattern includes a plurality of unit cells immediately adjacent to each other, and each unit cell includes a first active region, a second active region isolated from the first active region, a plurality of first gate structures extending along a first direction and arranged along a second direction perpendicular to the first direction, and a plurality of first conductive structures.
United Microelectronics Corp.

Schemes for forming barrier layers for copper in interconnect structures

a method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring.
Taiwan Semiconductor Manufacturing Company, Ltd.

Image sensor device and image sensor module comprising the same

the present disclosure relates to an image sensor device including: a fan-out semiconductor package including a first semiconductor chip having an active surface on which a connection pad is disposed, a first connection member disposed on the active surface and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, and a sealing material disposed on the first connection member and sealing at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the first connection member and electrically connected to the first connection member; and a third semiconductor chip disposed on the second semiconductor chip and electrically connected to the second semiconductor chip, in which at least one of the second semiconductor chip or the third semiconductor chip may be an image sensor. The present disclosure also relates to an image sensor module including the image sensor device..
Samsung Electro-mechanics Co., Ltd.

Semiconductor device

a semiconductor device includes an assembly configured such that a plurality of semiconductor modules is connected by a component. Each of the plurality of semiconductor modules includes a semiconductor element including a front-surface electrode fixing a front-surface electrode plate and a back-surface electrode fixing a back-surface electrode plate, wherein the component is either of a first component and a second component.
Toyota Jidosha Kabushiki Kaisha

Active chip on carrier or laminated chip having microelectronic element embedded therein

a structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity.
Tessera, Inc.

Semiconductor structure and manufacturing the same

the present disclosure provides a semiconductor structure, including a first silicon layer having a through silicon via (tsv), a iii-v structure over the first silicon layer, electrically coupling to the tsv, and a redistribution layer (rdl) under the first silicon layer, electrically coupling to the tsv. The present disclosure also provides a method of manufacturing a semiconductor device.
Taiwan Semiconductor Manufacturing Company Ltd.

Semiconductor device, manufacturing method thereof, and electronic apparatus

a semiconductor device includes a wiring layer that includes at least one low-dielectric rate interlayer insulating film layer; a guard ring that is formed by placing in series a wire and a via so as to be in contact with a through electrode, in a portion in which the through electrode passing through the wiring layer is formed; and the through electrode that is formed by being buried inside the guard ring.. .
Sony Corporation

Method for fabricating semiconductor device having a patterned metal layer embedded in an interlayer dielectric layer

a method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (sti) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ild) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ild layer for forming a recess, and a patterned metal layer is formed in the recess and on the sti..
United Microelectronics Corp.

Wiring with external terminal

apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad formation area including a plurality of pads disposed at an edge of the apparatus; a peripheral circuit area including a plurality of circuit blocks coupled to a memory cell array, each circuit block of the plurality of circuit blocks including a via disposed at a side opposite to the pad formation area with respect to each circuit block; and a plurality of conductors, each conductor coupling the via to the corresponding pad, and crossing over, at least in part, an area in the peripheral circuit area that is outside the circuit block comprising the via..
Micron Technology, Inc.

Apparatuses including stair-step structures and methods of forming the same

methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions.
Micron Technology, Inc.

Semiconductor memory device

provided herein is a semiconductor memory device. The semiconductor memory device may include channel layers protruding away from a substrate.
Sk Hynix Inc.

Separation of integrated circuit structure from adjacent chip

embodiments of the present disclosure relate to separating an integrated circuit (ic) structure from an adjacent chip. An ic structure according to embodiments of the disclosure may include: a semiconductor region including an interconnect pad positioned thereon, the interconnect pad electrically connected to a solder bump; and an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad, wherein the ohmic heating wire is configured to be heated above a melting temperature of the solder bump..
Globalfoundries Inc.

Method for forming semiconductor package

a method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface, in which the interposer layer includes through interposer vias embedded inside, and the through interposer vias extended from the first surface toward the second surface, in which through interposer vias are patterned to form repetitive polygonal-packing units, and part of the through interposer vias can be grouped within at least two distinct said polygonal-packing units; subsequently, forming at least one redistribution layer on the first surface to form terminals on a surface of the redistribution layer away from the interposer layer, in which the terminals are selectively connected to the through interposer vias respectively; and then disposing at least one semiconductor chip on the redistribution layer, wherein the semiconductor chip includes active surfaces electrically connected to the terminals respectively.. .
Nanya Technology Corporation

Ic package

an ic package having a semiconductor body that includes a monolithically integrated circuit and at least two metallic contact surfaces. The integrated circuit being connected to the two electrical contact surfaces via printed conductors, and being disposed on a carrier substrate and connected to the carrier substrate in a force-fitting manner.
Tdk-micronas Gmbh

Cascode semiconductor package and related methods

a semiconductor package includes an electrically conductive base (base) having a source connector. A drain connector and a gate connector are electrically coupled with the base.
Semiconductor Components Industries, Llc

Semiconductor device

[object] a semiconductor device is configured to release heat from semiconductor chips more efficiently. [means for solution] a semiconductor device includes: a die pad 11 which has a die pad main surface 111 and a die pad rear surface 112; a semiconductor chip 41 mounted on the die pad main surface 111; a sealing resin portion 7 formed with a recess 75 for exposure of the die pad rear surface 11 and covering the die pad 11 and the semiconductor chip 41; and a heat releasing layer 6 disposed in the recess 75.
Rohm Co., Ltd.

Semiconductor device, semiconductor device manufacturing method and semiconductor device mounting structure

a semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections, a resin encapsulation portion having a recess portion for exposing at least a portion of the die pad sections, the resin encapsulation portion configured to cover the die pad sections and the semiconductor chips, and a heat radiation layer arranged in the recess portion. The heat radiation layer includes an elastic layer exposed toward a direction in which the recess portion is opened.
Rohm Co., Ltd.

Leadframe substrate with electronic component incorporated therein and semiconductor assembly using the same

the leadframe substrate includes a routing circuitry disposed on a compound layer and electrically connects an electronic component encapsulated in the compound layer to metal leads. The compound layer fills in spaces between the metal leads and provides a dielectric platform for the routing circuitry deposited thereon.
Bridge Semiconductor Corporation

Semiconductor package with grounded fence to inhibit dendrites of die-attach materials

the present disclosure relates to a semiconductor package with at least one grounded fence to inhibit dendrites of die-attach materials. The semiconductor package includes a carrier, a die-attach material, and a wire-bonded die.
Qorvo Us, Inc.

Substrate based fan-out wafer level packaging

a method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding.
Unisem (m) Berhad

Semiconductor device packages and manufacturing the same

a semiconductor device package includes a carrier, a lid, an electronic component and a sealant. The carrier has a first surface and a second surface opposite the first surface, and defines a hole extending from the first surface to the second surface.
Advanced Semiconductor Engineering, Inc.

Semiconductor element package, semiconductor device, and mounting structure

a semiconductor element package includes a base body, a frame member, and a terminal member. The frame member is provided on a main surface of the base body.
Kyocera Corporation

Ion implantation methods and structures thereof

a method for fabricating a semiconductor device using a high-temperature ion implantation process includes providing a substrate including a plurality of fins. In some examples, a mask material is deposited and patterned to expose a group of fins of the plurality of fins and a test structure.
Taiwan Semiconductor Manufacturing Company, Ltd.

Pattern inspection methods and methods of fabricating reticles using the same

a reticle may be fabricated and inspected. The reticle, which may include thin patterns, may be selectively incorporated into a fabricated semiconductor device based on measurement information generated based on the inspecting.
Samsung Electronics Co., Ltd.

Semiconductor devices

a semiconductor device includes a first semiconductor pattern doped with first impurities on a substrate, a first channel pattern on the first semiconductor pattern, second semiconductor patterns doped with second impurities contacting upper edge surfaces, respectively, of the first channel pattern, and a first gate structure surrounding at least a portion of a sidewall of the first channel pattern.. .
Samsung Electronics Co., Ltd.

Semiconductor fin loop for use with diffusion break

a finfet includes a source or a drain including: a first semiconductor fin extending parallel to a second semiconductor fin, and a semiconductor connector fin creating a first semiconductor fin loop by connecting an end of the first semiconductor fin to an end of the second semiconductor fin. A diffusion break isolates the source or the drain, and is positioned about the first semiconductor connector fin and the ends of the first semiconductor fin and the second semiconductor fin.
Globalfoundries Inc.

Bottom-up fill (buf) of metal features for semiconductor structures

bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ild) layer.
Intel Corporation

Cobalt deposition selectivity on copper and dielectrics

a process for forming cobalt on a substrate, comprising: volatilizing a cobalt precursor of the disclosure, to form, a precursor vapor: and contacting the precursor vapor with the substrate under vapor deposition conditions effective for depositing cobalt on the substrate from the precursor vapor, wherein the vapor deposition conditions include temperature not exceeding 200° c., wherein: the substrate includes copper surface and dielectric material, e.g., ultra-low dielectric material. Such cobalt deposition process can be used to manufacture product articles in which the deposited cobalt forms a capping layer, encapsulating layer, electrode, diffusion layer, or seed for electroplating of metal thereon, e.g., a semiconductor device, flat-panel, display, or solar panel.
Entegris, Inc.

Semiconductor device and fabrication method thereof

semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming gate structures over the base substrate; forming doped source/drain regions in the base substrate at two sides of each of the gate structures; forming an oxide layer on each of the doped source/drain regions; forming a metal layer on the oxide layer; and performing a reactive thermal annealing process, such that the metal layer reacts with a material of the oxide layer and a material of the doped source/drain regions to form a metal contact layer on each of the doped source/drain regions.
Semiconductor Manufacturing International (beijing) Corporation

Skip via structures

the present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level..
Globalfoundries Inc.

Method of fabrication of a semiconductor element comprising a highly resistive substrate

a method of fabrication of a semiconductor element includes a step of rapid heat treatment in which a substrate comprising a base having a resistivity greater than 1000 ohm·cm is exposed to a peak temperature sufficient to deteriorate the resistivity of the base. The step of rapid heat treatment is followed by a curing heat treatment in which the substrate is exposed to a curing temperature between 800° c.
Soitec

Semiconductor devices and methods of manufacturing the same

a semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.. .
Samsung Electronics Co., Ltd.

Wafer positioning pedestal for semiconductor processing

an assembly used in a process chamber for depositing a film on a wafer and including a pedestal extending from a central axis. An actuator is configured for controlling movement of the pedestal.
Lam Research Corporation

Magnetically levitated and rotated chuck for processing microelectronic substrates in a process chamber

cleaning systems and methods for semiconductor fabrication use rotatable and optionally translatable chuck assemblies that incorporate magnetic levitation and rotation functionality to cause chuck rotation. The rotating chuck components do not physically contact other chuck components when levitated and rotating.
Tel Fsi, Inc.

Method and stacking devices in an integrated circuit assembly

methods and apparatuses for stacking devices in an integrated circuit assembly are provided. A tray for supporting multiple dies of a semiconductor material enables both topside processing and bottom side processing of the dies.
Invensas Corporation

Package structure, fan-out package structure and the same

a package structure includes a spiral coil, a redistribution layer (rdl) and a molding material. The molding material fills gaps of the spiral coil.
Taiwan Semiconductor Manufacturing Company Ltd.

Method of manufacturing a semiconductor device

a method of manufacturing a semiconductor device includes preparing an object layer on a substrate; polishing the object layer with a first slurry including a first abrasive having a zeta potential of a first polarity; rinsing a surface of the object layer, using a rinsing solution including a chemical of a second polarity, opposite to the first polarity; and polishing the object layer with a second slurry including a second abrasive having a zeta potential of a second polarity, opposite to the first polarity.. .
Samsung Electronics Co., Ltd .

Method of fabricating a semiconductor device

a method of fabricating a semiconductor device, the method including forming a deposition active layer and a guide pattern on a semiconductor substrate such that the guide pattern delimits an exposed surface of the deposition active layer; and selectively depositing a metal-containing layer on the exposed surface of the deposition active layer exposed by the guide pattern, wherein the deposition active layer is a nonmetal layer.. .
Samsung Electronics Co., Ltd.

Method of manufacturing semiconductor device

in a method of manufacturing a semiconductor device, by performing a predetermined number of times a cycle of performing supplying reducing gas to a substrate having an insulating surface and a conductive surface and supplying metal-containing gas to the substrate in a time-division manner, a metal film is formed selectively on an insulating surface.. .
Hitachi Kokusai Electric Inc.

Semiconductor device manufacturing method

a method of manufacturing a semiconductor device includes the following processes. A metal film forming process in which a metal film including cobalt is formed on a surface of silicon.
Mie Fujitsu Semiconductor Limited

Semiconductor device and manufacturing the same

a third semiconductor layer (105) including a third nitride semiconductor is provided between an electrode (110) and a second semiconductor layer (104) including a second nitride semiconductor. The band gap of the second nitride semiconductor is set such that the carrier movement between a first semiconductor layer (103) and the third semiconductor layer (105) via the second semiconductor layer (104) is rate-determined by a diffusion process.
Nippon Telegraph And Telephone Corporation

Semiconductor device having interconnect structure

various embodiments provide semiconductor devices. A base including a substrate and an interlayer dielectric layer is provided.
Semiconductor Manufacturing International (shanghai) Corporation

Symmetric tunnel field effect transistor

the present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped vo2 region..
International Business Machines Corporation

Precursors for silicon dioxide gap fill

a full fill trench structure is described, including a microelectronic device substrate having a high aspect ratio trench therein and filled with silicon dioxide of a substantially void-free character and substantially uniform density throughout its bulk mass. A method of manufacturing a semiconductor product also is described, involving use of specific silicon precursor compositions for forming substantially void-free and substantially uniform density silicon dioxide material in the trench.
Entegris, Inc.

Process feed management for semiconductor substrate processing

embodiments related to managing the process feed conditions for a semiconductor process module are provided. In one example, a gas channel plate for a semiconductor process module is provided.
Asm Ip Holding B.v.

Method and calibrating optical path degradation useful for decoupled plasma nitridation chambers

methods for matching semiconductor processing chambers using a calibrated spectrometer are disclosed. In one embodiment, plasma attributes are measured for a process in a reference chamber and a process in an aged chamber.
Applied Materials, Inc.

High conductance process kit

apparatus for plasma processing of semiconductor substrates. Aspects of the apparatus include an upper shield with a gas diffuser arranged at a center of the upper shield.
Applied Materials, Inc.

Repair control device and semiconductor device including the same

a repair control device for memory cells divided into a plurality of banks may include a failed address storage circuit configured to sort and store a plurality of failed addresses each containing a failed bank address and a failed row address, according to the failed row address, and store the failed row address by matching the failed row address with total failed bank information representing one or more failed banks indicated by the failed row address. The repair control device also includes an address comparison circuit configured to compare an input address to a pair comprised of the failed row address and the total failed bank information, stored in the failed address storage circuit, and generate a hit signal based on the comparison result.
Sk Hynix Inc.

Semiconductor device and operating method thereof

a method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.. .
Sk Hynix Inc.

Semiconductor memory device with improved program verification reliability

a semiconductor memory device includes a memory cell array including first and second groups of memory strings respectively coupled to first and second groups of bit-lines, wherein the first and second groups of memory strings respectively include first and second groups of selection transistor cells; a peripheral circuit suitable for applying a program voltage, and performing program verification operation for the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform a first program verification operation for the first group of selection transistor cells and a second program verification operation for the second group of selection transistor cells.. .
Sk Hynix Inc.

Semiconductor device, electronic component, and electronic device

a highly reliable semiconductor device is provided. A memory cell includes a first transistor and a second transistor.
Semiconductor Energy Laboratory Co., Ltd.

Methods and apparatuses including an asymmetric assist device

apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar.
Micron Technology, Inc.

Semiconductor memory device and operating the same

provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device in accordance with an embodiment may include a memory cell array, a peripheral circuit, and a control circuit.
Sk Hynix Inc.

Semiconductor memory device and reading method thereof

a semiconductor memory device and a reading method thereof are provided. A flash memory includes a memory cell array; a page buffer/reading circuit, holding data of a selected page of the memory cell array; a decoding/selecting circuit, selecting n bits data from the data held by the page buffer based on a column address; and a data bus for n bits, which is connected to the decoding/selecting circuit.
Winbond Electronics Corp.

Semiconductor memory device

according to embodiments, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode and includes a metal film and a resistance change film.
Toshiba Memory Corporation

Semiconductor memory with data line capacitive coupling

a semiconductor memory is disclosed that includes a first data line, a first coupling line, and a second coupling line. The first coupling line is configured to capacitively couple the first coupling line with the first data line.
Taiwan Semiconductor Manufacturing Co., Ltd.

Data output circuit and semiconductor memory device including the same

a data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.. .
Sk Hynix Inc.

Dual interlocked storage cell (dice) latch sharing active region with neighbor dice latch and semiconductor device including the same

a dual interlocked storage cell (dice) latch may be provided. A semiconductor device may be provided.
Sk Hynix Inc.

Semiconductor memory device and operating method thereof

various embodiments of the invention relate generally to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. A semiconductor memory device including a plurality of memory cells using an optimal input buffer reference voltage may include at least one input buffer receiving data to be stored in the plurality of memory cells and an input buffer reference voltage control unit setting one of a plurality of internal voltages having different voltage levels as a reference voltage of the at least one input buffer in response to a control signal..
Sk Hynix Inc.

Training controller, and semiconductor device and system including the same

a training controller, semiconductor device and a system including the same are disclosed, which relates to technology for training a phase of data. The training controller may include a read training circuit configured to control a read training operation based on a read signal and a control signal.
Sk Hynix Inc.

Apparatuses and methods for compute components formed over an array of memory cells

the present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material.
Micron Technology, Inc.

Electronic device and fabricating the same

provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers..
Sk Hynix Inc.

Display driver and semiconductor device

a display driver includes a gamma correction data transmission unit that transmits a plurality of gamma correction data pieces one by one in each predetermined period. A brightness level indicated by a video signal is converted into a gradation voltage with a gamma characteristic based on the gamma correction data piece transmitted from the gamma correction data transmission unit..
Lapis Semiconductor Co., Ltd.

Semiconductor device and system thereof

the semiconductor device includes a transmission/reception circuit, a control circuit, an analog-to-digital converter circuit, a memory device, and a fingerprint sensor. At least one of the control circuit, the analog-to-digital converter circuit, and the memory device includes a transistor including an oxide semiconductor in a channel formation region.

Semiconductor memory system and operating method thereof

a semiconductor memory system and an operating method thereof includes: a one-time-programmable memory device storing at least a customer identification (id) identifying a customer; a memory device; and a memory controller including a processor, and coupled to the memory device, containing instructions executed by the processor, and suitable for authenticating whether a program is authorized by a controller provider for the customer in a first-level signature authentication, in accordance with a customer image format, authenticating whether the program is authorized by the customer in a second-level signature authentication, in accordance with a program image format, after the first-level signature authentication is passed, when the customer image indicates the second-level signature authentication, wherein the program image format is different than the customer image format, storing the program into the memory device after the first-level signature authentication and second-level signature authentication are passed, and executing the program after the program is authenticated.. .
Sk Hynix Memory Solutions Inc.

Design semiconductor integrated circuit layout and fabricating semiconductor device using the same

a design method of a semiconductor integrated circuit layout and a method of fabricating a semiconductor device, the design method including selecting a first cell layout including at least one first gate pattern; selecting a second cell layout including at least one second gate pattern, the at least one second gate pattern having a gate length that is different from a gate length of the at least one first gate pattern; producing a pattern layout from the first and second cell layouts; and producing a mask layout selectively overlapping the first cell layout on the pattern layout.. .
Samsung Electronics Co., Ltd.

Virtual cell model geometry compression

semiconductor designs are large and complex, typically consisting of numerous circuits called cells. To handle complexity, hierarchical structures are imposed on the semiconductor design to help accomplish analysis, simulation, verification, and so on.
Synopsys, Inc.

Semiconductor device and information writing/reading method

disclosed is a semiconductor device that writes, into respective memory spaces of a plurality of divisional memories constituting a search memory mat, an entry address corresponding to key data to be written. In this semiconductor device, pieces of divisional data are assigned respectively to the divisional memories, and, by employing each divisional data as an address, an entry address corresponding to said divisional data is written sequentially into a memory space specified by a memory address of each said divisional memory (first writing process).
Nagase & Co., Ltd.

Memory device and semiconductor package including the same

a semiconductor package includes: memory devices that are stacked one on another; and an inter-layer channel for communication between the memory devices, wherein each memory device includes: a data pad; a memory core; a data input/output circuit that inputs/outputs data through the data pad; an inter-layer channel transfer circuit that transfers a read data transferred from the memory core to the inter-layer channel or transfers a data inputted through the data input/output circuit to the inter-layer channel; an inter-layer channel reception circuit receiving the data of the inter-layer channel; a read error correction circuit correcting an error of the data transferred from the inter-layer channel reception circuit to produce an error-corrected data and transfers the error-corrected data to the data input/output circuit; and a write error correction circuit generating a parity data to be stored in the memory core based on the data transferred from the inter-layer channel reception circuit.. .
Sk Hynix Inc.

Semiconductor memory device, controller, and operating methods thereof

a semiconductor memory device includes a memory cell array, a read/write circuit, a control logic, and a block defect information storage unit. The control logic controls the read/write circuit to perform a read/write operation on the memory cell array.
Sk Hynix Inc.

Storage device, semiconductor device, electronic device, and server system

data corrupted by a soft error is recovered. A storage device includes a first memory cell, a second memory cell, a sense circuit electrically connected to the first memory cell through a first sense line and to the second memory cell through a second sense line, a digital-analog converter circuit electrically connected to the first memory cell and the second memory cell through a bit line, and an analog-digital converter circuit.
Semiconductor Energy Laboratory Co., Ltd.

Method and system for accessing a flash memory device

an apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed.
Conversant Intellectual Property Management Inc.

Display substrate, display panel and display device

provided are a display substrate, a display panel and a display device, among them, the display substrate includes a base substrate and at least a semiconductor pressure sensor disposed in the display substrate; the semiconductor pressure sensor includes a first connection terminal, a second connection terminal, a third connection terminal and a fourth connection terminal, the first and second connection terminals are used to receive the bias voltage signal, the third and fourth connection terminals are used to output the strain voltage signal; the control electrode arranged at a side of the semiconductor pressure sensor is configured to be insulated with the semiconductor pressure sensor and used to control the semiconductor pressure to be turned on and to be turned off; a control signal line is connected to the control electrode.. .
Shanghai Tianma Micro-electronics Co., Ltd.

Mask blank, phase shift mask, manufacturing phase shift mask, and manufacturing semiconductor device

provided is a mask blank including a phase shift film on a transparent substrate. This phase shift film includes a phase shift layer at least containing a transition metal and silicon, and a silicon layer, which is configured to attenuate exposure light with which the phase shift layer is irradiated, and the silicon layer is formed to be in contact with the substrate side of the phase shift layer.
Hoya Corporation

Segmented light or optical power emitting device with fully converting wavelength converting material and methods of operation

a segmented light or optical power emitting device and an illumination device are described. The segmented device includes a die having a light or optical power emitting semiconductor structure that includes an active layer disposed between an n-layer and a p-layer.
Lumileds Llc

Optical semiconductor module

an optical semiconductor module includes a resin body having a first surface and an opposed second surface, an optical device having a third surface and a fourth surface opposite the third surface, the optical device comprising an optical element located at the fourth surface, the optical element capable of at least one of receiving light from, and transmitting light through, the third surface, a first terminal located at the first surface of the resin body, and an electrical connection between the first terminal and the optical device, the electrical connection embedded in the resin body.. .
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing method thereof

a semiconductor device includes: a first substrate; a surface insulating film formed over an upper surface of the first substrate; a box layer formed over the surface insulating film; an optical waveguide made of an soi layer formed on the box layer; and a first interlayer insulating film formed over the box layer so as to cover the optical waveguide. The semiconductor device further includes: a trench formed in the surface insulating film and the first substrate below the optical waveguide; and a cladding layer made of a buried insulating film buried in the trench.
Renesas Electronics Corporation

Receiver device, sensor device and determining distances

in order to measure distances precisely, a receiver device for determining a distance from an object is proposed, comprising: a receiver having a semiconductor structure with a photosensitive region for generating photo-induced charge carriers, which region faces the rear side, and having a transportation region, which faces the front side, wherein the photosensitive region and the transportation region are spatially separated from one another by a separation layer which has a passage between the photosensitive region and the transportation region, wherein the transportation region has an arrangement of at least two gates lying one next to the other, at least one of the gates thereof being located in the overlapping region of the passage.. .
Valeo Schalter Und Sensoren Gmbh

Failure location specifying device and failure location specifying method

a failure location specifying device that can specify a failure location even if the spatial resolution is insufficient includes: an eofm measurement unit that calculates a phase difference between a measurement signal on the basis of reflected light in accordance with the operation of a circuit element arranged in a semiconductor device and a reference signal, and generates a phase map of the circuit element in the semiconductor device. A circuit simulation unit calculates the operation waveform of a circuit element included in the field of view that is extracted by a circuit extraction unit by a simulation.
Renesas Electronics Corporation

Semiconductor device

a semiconductor device includes an external terminal, a switching output stage that performs switching drive of a terminal voltage at the external terminal, an output control unit arranged to generate a drive signal for the switching output stage according to an input pulse signal, a counter arranged to count the number of pulses of the input pulse signal so as to generate a mask signal, a logical gate arranged to mask the input pulse signal according to the mask signal, and a comparator arranged to compare the terminal voltage with a predetermined threshold value voltage so as to generate a reset signal of the counter.. .
Rohm Co., Ltd.

Sensor, sensor module, and detection method

this sensor has: a first capacitance electrode comprising a plate-shaped conductor or semiconductor; a first terminal electrically connected to the first capacitance electrode; a first insulating film disposed at one surface of the first capacitance electrode; a second capacitance electrode comprising a conductor or semiconductor and disposed in a manner so as to oppose a portion of the first capacitance electrode with the first insulating film therebetween; a second terminal electrically connected to the second capacitance electrode; a variable resistance element disposed on the first insulating film; and a reaction section disposed on the other surface of the first capacitance electrode in a direct manner or with a second insulating film therebetween. The variable resistance element includes: a base body disposed on the first insulating film; a third terminal connected to one end of the base body; and a fourth terminal connected to the other end of the base body..
Bio Sensor Inc.

Sensing device

a sensing device includes a semiconductor structure, a substrate, a first electrode and a second electrode, and a heater. A sensing area arranged on the top side of the semiconductor structure.
Epistar Corporation

Metrology inspection apparatus

the present disclosure provides a method and an apparatus for apparatus for inspecting a semiconductor wafer for abnormalities by accurately measuring elemental concentration at a target area. The apparatus includes an x-ray imaging subsystem for measuring an elemental composition at the target area of the semiconductor wafer.
Xwinsys Ltd.

Metrology measuring apparatus

the present disclosure provides a method and an apparatus for apparatus for accurately measuring and calibrating elemental concentration measurements for a semiconductor wafer. The apparatus includes an edxrf system for calculating an elemental concentration at a target area of the semiconductor wafer.
Xwinstys Ltd.

Methods and detection and analysis of nanoparticles from semiconductor chamber parts

methods and apparatuses for identifying contaminants in a semiconductor cleaning solution, including: contacting a semiconductor cleaning solution with a semiconductor manufacturing component to form an effluent including one or more insoluble analytes-of-interest; contacting the effluent including one or more insoluble analytes-of-interest with an optical apparatus configured to sense fluorescence and, optionally, raman signals from the one or more insoluble analytes-of-interest, wherein the apparatus includes an electron multiplying charged couple device and a grating spectrometer to spectrally disperse the fluorescence and project the fluorescence on to the electron multiplying charged couple device; and identifying the one or more analytes of interest.. .
Applied Materials, Inc

Methods and detection and analysis of nanoparticles from semiconductor chamber parts

methods and apparatuses for the analysis and detection of nanoparticles in a liquid from a semiconductor manufacturing component are provided herein. In some embodiments, a method of determining particle count, particle size, and zeta potential of nanoparticles in a substrate processing chamber component cleaning solution, includes (a) filling a sample cell with a cleaning solution from a substrate processing chamber component cleaning tank holding a semiconductor processing chamber component; (b) directing a light from a laser to the sample cell, wherein nanoparticles within the cleaning solution scatter the light from the laser; and (c) detecting the scattered light via one or more detectors proximate the sample cell to determine the zeta potential, the particle size and particle count of nanoparticles in the cleaning solution..
Applied Materials, Inc.

Semiconductor device

a semiconductor device includes a power semiconductor element that is connected between a first terminal on a high potential side and a second terminal on a low potential side and that is controlled to be on or off corresponding to a gate potential, a turn-off condition detector that detects whether a control signal input from a control terminal and controlling the power semiconductor element satisfies a predetermined turn-off condition, a first switching element that controls the gate potential of the power semiconductor element to be an off-potential when the turn-off condition detector detects that the turn-off condition is satisfied, and a detector for a collector current of the power semiconductor element. The turn-off condition detector uses the control signal and the collector current as the turn-off condition..
Fuji Electric Co., Ltd.

Coating device of component for semiconductor manufacturing apparatus and coating method thereof

a coating device of component for semiconductor manufacturing apparatus comprises a source among pulse type plasma source, icp source, ccp source, ccp+icp source and plasma source using a remote plasma to be carried out nitride treatment by a gas among n2, nh3, ch4 and n2o being supplied into a chamber; and a dc voltage for forming a plasma by said source and for supplying 50 kev˜100 kev of voltage toward a susceptor placed thereon with a basic material or a pulse voltage for injecting ion.. .

Coating coating interior fluid wetted surfaces of a component of a semiconductor substrate processing apparatus

a fluid handling component for a vacuum chamber of a semiconductor substrate processing apparatus is provided. The fluid handling component comprises interior fluid wetted surfaces and an atomic layer deposition (ald) or molecular layer deposition (mld) barrier coating on the interior fluid wetted surfaces wherein the fluid wetted surfaces which include the ald or mld barrier coating are configured to be contacted by a process gas and/or fluid during a semiconductor substrate processing process wherein the ald or mld barrier coating protects the underlying fluid wetted surfaces from erosion and/or corrosion..
Lam Research Corporation

Quantum dot and manufacturing the same

a method for manufacturing a quantum dot and a quantum dot are provided. The method includes adding a core semiconductor precursor solution into a seed composition solution.
Industrial Technology Research Institute

Mems structure with bilayer stopper and forming the same

microelectromechanical systems (mems) packages and methods for forming the same are provided. The mems package includes a semiconductor substrate having a metallization layer over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Electromechanical power steering system

an electromechanical power steering system for a vehicle may include an electric motor having a stator fitted with at least two electrical winding sets and having a rotor fitted with permanent magnets. The electric motor may exert a steering movement introduced by a driver on the vehicle.
Thyssenkrupp Ag

Semiconductor element manufacturing method and manufacturing device

a semiconductor element manufacturing method according to the invention is such that a focal spot form of a laser light is an ellipse, and irradiation with the laser light is concentrated on a projected division line of an interface between a semiconductor substrate and a fixing sheet, which is a vaporizing pressure confining sheet, and vaporizing pressure generated by the irradiation is confined between the semiconductor substrate and the fixing sheet, and caused to act as a bending force on the semiconductor substrate, and an initial crack is extended. Because of this, energy of the laser light can be reduced, heat damage to an element region of the semiconductor substrate and debris can be reduced, and a division face with good flatness can be stably obtained..
Mitsubishi Elctric Corporation

Solid-state imaging device and endoscope system

the solid-state imaging device includes a semiconductor layer, an electrode, a wiring layer, a plurality of filters, an input terminal, and a voltage generation circuit. The voltage generation circuit generates a first voltage and a second voltage.
Olympus Corporation

Imaging unit, imaging module, and endoscope

an imaging unit includes: an optical system; a semiconductor package including an image sensor, and a connection electrode formed on a back surface; a cable; an electronic component; and a multi-layer substrate having a rectangular plate shape and including: a first electrode and a second electrode arranged side-by-side with each other on a front surface, the semiconductor package being mounted on the first electrode, and the cable being connected to the second electrode; and a third electrode on a back surface, the electronic component being mounted on the third electrode. The multi-layer substrate includes walls on at least two opposing sides of the back surface, and the semiconductor package is disposed such that a light receiving surface of the image sensor is arranged horizontally with respect to the multi-layer substrate..
Olympus Corporation

Systems and methods for growing a non-phase separated group-iii nitride semiconductor alloy

systems and methods for mbe growing of group-iii nitride alloys, comprising establishing an average reaction temperature range from about 250 c to about 850 c; introducing a nitrogen flux at a nitrogen flow rate; introducing a first metal flux at a first metal flow rate; and periodically stopping and restarting the first metal flux according to a first flow duty cycle. According to another embodiment, the system comprises a nitrogen source that provides nitrogen at a nitrogen flow rate, and, a first metal source comprising a first metal effusion cell that provides a first metal at a first metal flow rate, and a first metal shutter that periodically opens and closes according to a first flow duty cycle to abate and recommence the flow of the first metal from the first metal source.
Longwood Gardens, Inc.

Wiring board and electronic device using the wiring board

a wiring board according to the present disclosure includes an insulating substrate having a semiconductor-element mount portion, a constant-voltage-regulator mount portion, and an external connection surface; semiconductor-element connection pads; constant-voltage-regulator connection pads; external connection pads; and wiring conductors including a wiring conductor for signal connected to the semiconductor-element connection pad for signal in an outer peripheral portion of the insulating substrate and extending in the insulating substrate from an area below the semiconductor-element mount portion to the outer peripheral portion. The wiring conductor for signal extends on a surface of a build-up insulating layer of the insulating substrate, on which the solid conductor for grounding or for power supply extends, to the outer peripheral portion without passing through an area below an intermediate portion between the semiconductor-element mount portion and the constant-voltage-regulator mount portion..
Kyocera Corporation

Piezoelectric mems sensor, such as force, pressure, deformation sensor or microphone, with improved sensitivity

a mems sensor, in particular a microphone, of a piezoelectric type, formed in a membrane of semiconductor material accommodating a compliant portion, which extends from a first surface to a second surface of the membrane. The compliant portion has a young's modulus lower than the rest of the membrane.
Stmicroelectronics S.r.l.

Semiconductor apparatus, solid-state image sensing apparatus, and camera system

a semiconductor apparatus, a solid-state image sensing apparatus, and a camera system capable of reducing interference between signals transmitted through adjacent via holes, preventing an increase in the number of the via holes, reducing the area of a chip having sensors thereon and the number of mounting steps thereof. First and second chips are bonded together to form a laminated structure, a wiring between the first chip and the second chip being connected through via holes, the first chip transmitting signals obtained by time-discretizing analog signals generated by respective sensors to the second chip through the corresponding via holes, the second chip sampling the signals transmitted from the first chip through the via holes at a timing different from a timing at which the signals are sampled by the first chip and quantizing the sampled signals to obtain digital signals..
Sony Corporation

Image sensor modules including primary high-resolution imagers and secondary imagers

image sensor modules include primary high-resolution imagers and secondary imagers. For example, an image sensor module may include a semiconductor chip including photosensitive regions defining, respectively, a primary camera and a secondary camera.
Heptagon Micro Optics Pte. Ltd.

Clock recovery circuit, semiconductor integrated circuit device and radio frequency tag

a clock recovery circuit includes: a multi-phase clock generating circuit configured to generate multi-phase clocks having different phases; a plurality of switch elements configured to control coupling between each of the multi-phase clocks and an output node; and a switch control circuit configured to compare phases of the multi-phase clocks and input data and control, to an on-state, at least two switch elements of the plurality of switch elements corresponding to at least two clocks whose phase difference falls within a given range, wherein the at least two clocks selected through the at least two switch elements controlled to the on-state are subjected to phase interpolation to recover an output clock.. .
Fujitsu Limited

Optical module and optical transmitting apparatus installing a number of optical modules

an optical module installed within an optical transmitter apparatus is disclosed. The optical module provides an electrically insulating carrier, a semiconductor element, and a capacitor.
Sumitomo Electric Device Innovations, Inc.

Method of controlling semiconductor optical device that includes semiconductor optical amplifier

a method of controlling a semiconductor element that includes a semiconductor laser diode (ld), a semiconductor modulator, and a semiconductor optical amplifier (soa) is disclosed. The ld generates cw light supplied with the first bias current.
Sumitomo Electric Device Innovations, Inc.

Semiconductor device and operating method thereof

provided are a semiconductor device and an operating method thereof. A semiconductor device includes a mixer configured to upconvert a baseband signal using a local oscillator (lo) signal; and a notch filter configured to receive the upconverted signal from the mixer and filter notch frequency components, the notch filter further configured to resonate at a fundamental frequency to provide a higher impedance and resonate at a notch frequency different from the fundamental frequency to provide a lower impedance..
Samsung Electronics Co., Ltd

Da converter, ad converter, and semiconductor device

a da converter includes a first da conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second da conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the da converter, the gain control of the analog output signal generated by the first da conversion section is performed on the basis of the gain control output signal generated by the second da conversion section..
Sony Corporation

Clock generation circuit, and semiconductor device and system using the same

a clock generation circuit may include a first clock generator and a second clock generator. The first clock generator may generate a first output clock toggling in synchronization with a rising edge of a first input clock.
Sk Hynix Inc.

Clock recovery circuit, semiconductor integrated circuit device, and radio frequency tag

a clock recovery circuit includes a delay line circuit configured to output a plurality of first clocks having different phases obtained by delaying an input data signal, a register circuit configured to determine and write received data in the input data signal based on the first clocks, and a control circuit configured to control the writing of the data in the register circuit based on transitions of the input data signal.. .
Fujitsu Limited

Power source monitoring circuit, power on reset circuit, and semiconductor device

the present technology relates to a power source monitoring circuit, a power on reset circuit, and a semiconductor device that are capable of reducing a steady-state current. The semiconductor device includes a level shifter circuit that performs level conversion on a digital signal output from a predetermined block and outputs a resultant signal to another block that operates by a power source different from the power source of the predetermined block, and a power source monitoring circuit that controls an operation of the level shifter circuit.
Sony Corporation

Semiconductor switch control device

a semiconductor switch control device includes a bidirectional shutoff circuit that transmits or shuts off a current flowing bidirectionally between a high-voltage battery and a high-voltage load, a resistor that detects a voltage of the bidirectional shutoff circuit, a first voltage detector that detects a voltage applied to the resistor, and a controller configured to determine malfunction of the bidirectional shutoff circuit, based on a first detected voltage detected by the first voltage detector. The bidirectional shutoff circuit includes a first fet and a second fet including respective source terminals connected in series, and a third fet and a fourth fet including respective source terminals connected in series.
Yazaki Corporation

Semiconductor device and generating power-on reset signal

a semiconductor device and a method of generating a power-on reset signal are provided. The semiconductor device includes a regulator configured to generate a regulated power supply voltage having a lower voltage value than a power supply voltage based on the power supply voltage and output the regulated power supply voltage to an internal power supply line, and a power-on reset circuit configured to generate a signal which has a first level at which reset is prompted immediately after power for the power supply voltage is turned on and which transitions to a second level at which reset release is prompted from the first level when a voltage value of the internal power supply line has risen as a power-on reset signal..
Lapis Semiconductor Co., Ltd.

Flip-flop and semiconductor system including the same

a flip-flop generates a first feedback signal using a signal generated inside the flip-flop. The flip-flop includes a first stage circuit, a second stage circuit and a third stage circuit.
Samsung Electronics Co., Ltd.

Power converter, diagnostic system of power converter, and diagnostic method

there is provided a diagnostic system for a power converter which includes a semiconductor device, and performs a switching operation between conduction and interruption of the principal current flowing through the main circuit. The diagnostic system includes a current change amount calculation circuit for obtaining numeric data which reflects a current change amount of the principal current per unit time, a determination circuit for determining a state of the power converter by comparing the numeric data with a reference value, and an output circuit for outputting a determination result of the determination circuit..
Hitachi, Ltd.

Central control system

provided is a structure which is capable of central control of an electric device and a sensor device and a structure which can reduce power consumption of an electric device and a sensor device. A central control system includes at least a central control device, an output unit, and an electric device or a sensor device.
Semiconductor Energy Laboratory Co., Ltd.

Control method and control device

a control method, which is applied to a conversion circuit including at least one bridge arm and an inductor, the bridge arm including an upper semiconductor switch and a lower semiconductor switch connected in series, and one end of the inductor being connected to a midpoint of the bridge arm, includes: judging a direction of current of the inductor when a scram event occurs in the conversion circuit; turning on the upper semiconductor switch and turning off the lower semiconductor switch when the direction of current of the inductor is judged as a first direction, wherein the first direction is a forward conduction direction of the lower semiconductor switch; and turning off the upper semiconductor switch and turning on the lower semiconductor switch when the direction of current of the inductor is judged as a second direction.. .
Delta Electronics,inc.

Control device

the present invention is concerning the control device equipped with a motor 2 and a control unit 1 which is coaxial to the motor 2. An upper frame 40 is arranged at a boundary between the motor 2 and the control unit 1.
Mitsubishi Electric Corporation

Wirelessly electrically chargeable device having a coating that looks metallic

an electronic device, including at least one electronic component that can be used as an electrically and wirelessly chargeable terminal or as a transmitting device for such a terminal. The electronic device has a plastic surface that enables electromagnetic interaction between the electronic component and an external electronic component in the frequency range of 110 to 205 khz.
Oerlikon Surface Solutions Ag, Pfaffikon

Semiconductor integrated circuit, operating method thereof, and electronic device including the same

a semiconductor integrated circuit may include a recharge switch and a wireless recharge/mst unit. The recharge switch is connected with a battery through an intermediate node and provides a current path for wirely charging the battery in a wired charging mode.
Samsung Electronics Co., Ltd.

Multi-laser package using shared optics

an optical device may include a semiconductor laser chip to independently generate four laser beams at different wavelengths. Each laser beam, of the four laser beams, may be directed to a respective optical output of the optical device with a sub-micron level of tolerance of each laser beam relative to the respective optical outputs of the optical device, and each laser beam, of the four laser beams, may be associated with a different optical path from the semiconductor laser chip to the respective optical output of the optical device.
Lumentum Operations Llc

Semiconductor laser diode having multi-quantum well structure

a semiconductor laser diode (ld) having an optical grating is disclosed. The ld includes a lower cladding layer that buries the optical grating, an active layer, and an upper cladding layer.
Sumitomo Electric Device Innovations, Inc.

Surface emitting laser, information obtaining apparatus, and imaging apparatus

the present invention provides a surface emitting laser the wavelength-tunable band of which is wide. The wavelength-tunable surface emitting laser includes a first reflector (101), an active layer (103) disposed on the first reflector (101), a beam portion (110) disposed over the active layer (103) with an air gap therebetween, and a second reflector (120) disposed on the beam portion (110).
Canon Kabushiki Kaisha

Method, system and higher order mode suppression

a laser diode vertical epitaxial structure, comprising a transverse waveguide comprising an active layer between an n-type semiconductor layer and a p-type semiconductor layer wherein the transverse waveguide is bounded by a lower index n-cladding layer on an n-side of the transverse waveguide and a lower index p-cladding layer on a p-side of the transverse waveguide, a lateral waveguide that is orthogonal to the transverse waveguide, wherein the lateral waveguide is bounded in a longitudinal direction at a first end by a facet coated with a high reflector (hr) coating and at a second end by a facet coated with a partial reflector (pr) coating and a higher order mode suppression layer (homsl) disposed adjacent to at least one lateral side of the lateral waveguide and that extends in a longitudinal direction.. .
Nlight, Inc.

Active cable heat sink

a cable, system, and method for cooling a semiconductor chip on an active cable. The active cable includes a heat sink that is thermally coupled to the semiconductor chip and movable from a retracted position to an extended position.
International Business Machines Corporation

Method of manufacturing thin film transistor, thin film transistor, and electronic device comprising the thin film transistor

a method of manufacturing an organic thin film transistor includes forming a gate insulating layer on a gate electrode, forming a mold on the gate insulating layer, the mold including a void, forming a self-assembled layer from a self-assembled layer precursor in the void of the mold, removing the mold, and forming an organic semiconductor on the gate insulating layer.. .
Samsung Electronics Co., Ltd.

Self-assembled monolayer overlying a carbon nanotube substrate

one example includes a semiconductor device. The semiconductor device include a carbon nanotube substrate, a self-assembled monolayer, and a gate oxide.
Northrop Grumman Systems Corporation

Semiconductor structures including multi-portion liners

a method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate.
Micron Technology, Inc.

Magnetic random access memory device having magnetic tunnel junction

the disclosed technology generally relates to semiconductor devices and more particularly to semiconductor devices comprising a magnetic tunnel junction (mtj). In an aspect, a method of forming a magnetoresistive random access memory (mram) includes forming a layer stack above a substrate, where the layer stack includes a ferromagnetic reference layer, a tunnel barrier layer and a ferromagnetic free layer and a spin-orbit-torque (sot)-generating layer.
Imec Vzw

Electronic device and fabricating the same

a method for fabricating an electronic device including a semiconductor memory includes: forming an etching target layer over a substrate; forming an initial hard mask pattern including a carbon-containing material over the etching target layer; forming a hard mask pattern by doping an impurity which increases a hardness of the carbon-containing material into a surface portion of the initial hard mask pattern; and etching the etching target layer by using the hard mask pattern as an etching barrier.. .
Sk Hynix Inc.

Eutectic electrode structure of flip-chip led chip and flip-chip led chip

a flip-chip led chip includes: a substrate; a first semiconductor layer; a second semiconductor layer; a local defect region over part of the second semiconductor layer, which extends downward to the first semiconductor layer; a first metal layer over part of the first semiconductor layer; a second metal layer over part of the second semiconductor layer; an insulating layer covering the first metal layer, the second metal layer, the second semiconductor layer and the first semiconductor layer in the local defect region, with opening structures over the first metal layer and the second metal layer respectively; an eutectic electrode structure over the insulating layer, including a first eutectic layer and a second eutectic layer at vertical direction, and a first-type electrode region and a second-type electrode region at horizontal direction. Poor packaging caused by high eutectic void content during eutectic bonding process can therefore be reduced..
Xiamen Sanan Optoelectronics Technology Co., Ltd.

Radiation-emitting semiconductor component and production a plurality of semiconductor components

a radiation-emitting semiconductor component and a method for producing a plurality of semiconductor components are disclosed. In an embodiment the component includes a semiconductor chip comprising a semiconductor layer sequence, a front side and a rear side opposite the front side, and a molded body molded on to the semiconductor chip at least in some places.
Osram Opto Semiconductors Gmbh

Display device

a display device includes a display and at least one light source. The display displays image.
Funai Electric Co., Ltd.

Light source

proposed is a light source comprising: a plurality of led light sources, each of the plurality of led light sources having: a semiconductor diode structure adapted to generate light; and a light output section above the semiconductor diode structure adapted to output light from the semiconductor diode structure, the area of the light output section being less than the area of the semiconductor diode structure; and an optically transmissive structure overlapping the light output sections of the plurality of led light sources so as to receive light from the light output sections of the plurality of led light sources and having a light exit section adapted to output the received light. The area of the light exit section of the optically transmissive structure is less than the footprint area of the plurality of led light sources..
Koninklijke Philips N.v.

Semiconductor light-emitting device

a semiconductor light-emitting device includes a substrate, an led chip mounted on the substrate, and a resin package covering the led chip. The substrate includes a base and a wiring pattern formed on the base.
Rohm Co., Ltd.

Method of producing optoelectronic components and surface-mounted optoelectronic component

a method of producing optoelectronic components includes a) providing a carrier and optoelectronic semiconductor chips including contact elements arranged on a contact side of the semiconductor chip; b) applying the semiconductor chips laterally next to one another on to the carrier, wherein the contact sides face the carrier during application; c) applying an electrically-conductive layer at least on to subregions of the sides of the semiconductor chip not covered by the carrier; d) applying a protective layer at least on to subregions of side surfaces of the semiconductor chips running transversely to the contact surface; e) electrophoretically depositing a converter layer on to the electrically-conductive layer, wherein the converter layer is configured to convert at least part of radiation emitted by the semiconductor chip into radiation of a different wavelength range; and f) removing the electrically-conductive layer from regions between the converter layer and the semiconductor chips.. .
Osram Opto Semiconductors Gmbh

Semiconductor light emitting apparatus, stem part

a semiconductor light emitting apparatus includes: a stem part having a stem base, a lead terminal, and a metal member having a closed shape, the stem base having an inner portion having a first face, a second face and an opening extending in a first direction from the first face to the second face, and an outer portion surrounding the inner portion, the inner and outer portions being arranged along a reference plane intersecting the first direction, the lead terminal being supported in the opening, and the metal member being disposed on the outer portion so as to surround the inner portion and having a first portion supported by a top face of the outer portion, and a second portion extending outward with reference to an edge of the outer portion; a semiconductor optical element disposed on the inner portion; and a cap disposed on the metal member.. .
Sumitomo Electric Industries, Ltd.

Flip-chip light emitting diode chip and fabrication method

a flip-chip light-emitting diode chip with a patterned transparent bonding layer includes: an epitaxial laminated layer, having an upper surface and a lower surface opposite to each other, which further includes an n-type semiconductor layer, an active layer and a p-type semiconductor layer. Part of the n-type semiconductor layer and the active layer are etched to expose part of the p-type semiconductor layer.
Xiamen Sanan Optoelectronics Technology Co., Ltd.

Light emitting diode and fabrication method thereof

a light-emitting diode chip includes a first semiconductor layer, a second semiconductor layer and an active layer between them; an dielectric layer having a conductive through-hole array over the lower surface of the light-emitting epitaxial laminated layer; a metal conductive layer over the lower surface of the dielectric layer, which fills up the conductive through-hole, and forms ohmic contact with the light-emitting epitaxial laminated layer; a conductive substrate over the lower surface of the metal conductive layer for supporting the light-emitting epitaxial laminated layer; a first electrode comprising a bonding pad electrode and a finger-shape electrode over the upper surface of the light-emitting epitaxial laminated layer, wherein, a rotation angle is formed between the conductive through-hole array and the finger-shape electrode, which is selected to prevent a preferred number of conductive through-holes from being shielded by the bonding pad electrode and the finger-shape electrode.. .
Xiamen Sanan Optoelectronics Technology Co., Ltd.

Light-emitting device and light-emitting device package

a light-emitting device in an embodiment includes a substrate, a light-emitting structure which is disposed on the substrate and includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, first and second electrodes which are respectively connected to the first and second conductive semiconductor layers, first and second bonding pads respectively connected to the first and second electrodes, and an insulating layer disposed between the first bonding pad and the second electrode, and between the second bonding pad and the first electrode. The first thickness of the first electrode may be ⅓ or less of the second thickness of the insulating layer disposed between the second bonding pad and the first electrode..
Lg Innotek Co., Ltd.

Device and producing a device

a device and a method for producing a device are disclosed. In an embodiment the device includes a carrier and a semiconductor body arranged in a vertical direction on the carrier.
Osram Opto Semiconductors Gmbh

Light emitting diode and fabrication method thereof

a light-emitting diode (led) epitaxial structure includes, from bottom to up, a substrate, a first conductive type semiconductor layer, a super lattice, a multi-quantum well layer with v pits, a hole injection layer and a second conductive type semiconductor layer. The hole injection layer appears in the shape of dual hexagonal pyramid, which fills up the v pits and embeds in the second conductive type semiconductor layer.
Xiamen Sanan Optoelectronics Technology Co., Ltd.

Semiconductor structure with stress-reducing buffer structure

a semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 gpa and 2.0 gpa.
Sensor Electronic Technology, Inc.

Light-emitting device and manufacturing method thereof

a light-emitting device including a substrate; a first conductivity semiconductor layer on the substrate; a first barrier on the first conductivity semiconductor layer; a well on the first barrier and including a first region having a first energy gap and a second region having a second energy gap and closer to the semiconductor layer than the first region; a second barrier on the well; and a second conductivity semiconductor layer on the second barrier; wherein the first energy gap decreases along a stacking direction of the light-emitting device and has a first gradient, the second energy gap increases along the stacking direction and has a second gradient, and an absolute value of the first gradient is smaller than an absolute value of the second gradient.. .
Epistar Corporation

Advanced electronic device structures using semiconductor structures and superlattices

semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a p-type or n-type semiconductor structure is disclosed.
The Silanna Group Pty Ltd

Method for manufacturing light emitting unit

a method for manufacturing a light emitting unit is provided. A semiconductor structure including a plurality of light emitting dice separated from each other is provided.
Genesis Photonics Inc.

Method of manufacturing solar cell

a method of manufacturing a solar cell, the method includes forming a protective film over a semiconductor substrate, the semiconductor substrate including a base area of a first conductive type and formed of crystalline silicon, wherein the forming of the protective film includes a heat treatment process performed at a heat treatment temperature of approximately 600 degrees celsius or more under a gas atmosphere including nitrogen, and wherein the heat treatment process includes: a main section, during which the heat treatment temperature is maintained, a temperature increase section before the main section, during which an increase in temperature occurs from an introduction temperature to the heat treatment temperature, and a temperature reduction section after the main section, during which a decrease in temperature occurs from the heat treatment temperature to a discharge temperature.. .
Lg Electronics Inc.

Semiconductor stack, light-receiving device, and producing semiconductor stack

a semiconductor stack includes a first-conductivity-type layer of a first conductivity type, the first-conductivity-type layer being formed of a iii-v compound semiconductor; a quantum well light-receiving layer formed of a iii-v compound semiconductor; and a second-conductivity-type layer of a second conductivity type different from the first conductivity type, the second-conductivity-type layer being formed of a iii-v compound semiconductor. The first-conductivity-type layer, the quantum well light-receiving layer, and the second-conductivity-type layer are stacked in this order.
Sumitomo Electric Industries, Ltd.

Light detection device

disclosed herein is a light detection device. The light detection device includes a base layer, an electrostatic discharge (esd) prevention layer disposed on the base layer and including an undoped nitride-based semiconductor, a light absorption layer disposed on the esd prevention layer, a schottky junction layer disposed on the light absorption layer, and a first electrode and a second electrode electrically connected to the schottky junction layer and the base layer, respectively, wherein the esd prevention layer has a lower average n-type dopant concentration than the base layer..
Seoul Viosys Co., Ltd.

Method of patterning an amorphous semiconductor layer

methods of patterning an amorphous semiconductor layer according to a predetermined pattern via laser ablation with a pulsed laser having a laser wavelength are disclosed. In one aspect, a method may include providing the amorphous semiconductor layer on a substrate, providing a distributed bragg reflector on the amorphous semiconductor layer, wherein the distributed bragg reflector is reflective at the laser wavelength, providing an absorbing layer on the distributed bragg reflector, wherein the absorbing layer is absorptive at the laser wavelength, patterning the absorbing layer by laser ablation, in accordance with the predetermined pattern, patterning the distributed bragg reflector by performing an etching step using the patterned absorbing layer as an etch mask, and etching the amorphous semiconductor layer using the patterned distributed bragg reflector as an etch mask.
Katholieke Universiteit Leuven

Diffuse omni-directional back reflectors and methods of manufacturing the same

ultra-high reflectivity is projected for internal reflectors comprised of a metal film and nanostructured transparent conductive oxide (tco) bi-layer on the back side of a semiconductor device. Oblique-angle deposition can be used to fabricate indium tin oxide (ito) and other tco optical thin-film coatings with a porous, columnar nanostructure.
Magnolia Solar, Inc.

Solar cell composite utilizing molecule-terminated silicon nanoparticles

nano particles obtained by terminating surfaces of silicon nanoparticles having a diameter of not more than 5 nm with molecules of hydrocarbon are disposed on the outermost surface of a semiconductor forming a p-n junction solar cell that uses silicon or the like. These silicon nanoparticles absorb energy of ultraviolet light, and the energy is transferred to the p-n junction solar cell.

Optical component packaging structure

the instant disclosure provides an optical component packaging structure which includes a far-infrared sensor chip, a first metal layer, a packaging housing and a covering member. The far-infrared sensor chip includes a semiconductor substrate and a semiconductor stack structure.
Pixart Imaging Inc.

Deposition of charge trapping layers

a semiconductor device and method for manufacturing the semiconductor device are disclosed. Specifically, the semiconductor device may include a charge trapping layer with improved retention and speed for vnand applications.
Asm Ip Holding B.v.

Oxide semiconductor film and semiconductor device

it is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed.
Semiconductor Energy Laboratory Co., Ltd.

Thick fdsoi source-drain improvement

a method of forming a semiconductor device is disclosed including providing a semiconductor-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulating layer positioned on the semiconductor bulk substrate and a semiconductor layer positioned on the buried insulating layer, providing at least one metal-oxide semiconductor gate structure positioned above the semiconductor layer comprising a gate electrode and a spacer formed adjacent to the gate electrode, selectively removing an upper portion of the semiconductor layer so as to define recessed portions of the semiconductor layer and epitaxially forming raised source/drain regions on the recessed portions of the semiconductor layer.. .
Globalfoundries Inc.

Semiconductor device and manufacturing same

a semiconductor device includes at least one thin film transistor (100, 200), the at least one thin film transistor including a semiconductor layer (3a, 3b) which includes a channel region (31a, 31), a high-concentration impurity region, and a low-concentration impurity region (32a, 32b) which is located between the channel region and the high-concentration impurity region, a gate electrode (7a, 7b) provided on a gate insulating layer (5), an interlayer insulating layer (11) provided on the gate electrode, and a source electrode (8a, 8b) and a drain electrode (9a, 9b), wherein the interlayer insulating layer and the gate insulating layer have a contact hole extending to the semiconductor layer, at least one of the source electrode (8a, 8b) and the drain electrode (9a, 9b) being in contact with the high-concentration impurity region inside the contact hole, at a side wall of the contact hole, a side surface of the gate insulating layer is aligned with a side surface of the interlayer insulating layer, and at an upper surface of the semiconductor layer, an edge of the contact hole aligned with an edge of the high-concentration impurity region.. .
Sharp Kabushiki Kaisha

Thin film transistor and display substrate having the same

a display substrate including a base substrate, a first thin film transistor disposed on the base substrate and including a first gate electrode and a first semiconductor active layer; a second thin film transistor electrically connected to the first thin film transistor, the second thin film transistor including a second gate electrode and a second semiconductor active layer; and an organic light emitting device electrically connected to the second thin film transistor. The first semiconductor active layer includes a first material and the second semiconductor active layer includes a second material different from the first material..
Samsung Display Co., Ltd.

Finfet transistor gate and epitaxy formation

embodiments are directed to a method of forming a semiconductor device and resulting structures that reduce shallow trench isolation (sti) undercutting, floating gates, and gate voids without degrading epitaxy quality. The method includes forming a first and second semiconductor fin on a substrate.
International Business Machines Corporation

Semiconductor device

an object is to stabilize electric characteristics of a semiconductor device including an oxide semiconductor to increase reliability. The semiconductor device includes an insulating film; a first metal oxide film on and in contact with the insulating film; an oxide semiconductor film partly in contact with the first metal oxide film; source and drain electrodes electrically connected to the oxide semiconductor film; a second metal oxide film partly in contact with the oxide semiconductor film; a gate insulating film on and in contact with the second metal oxide film; and a gate electrode over the gate insulating film..
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and manufacturing method thereof

a semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator over a substrate; a first oxide over the first insulator; a second oxide in contact with at least a portion of the top surface of the first oxide; a second insulator over the second oxide; a first conductor over the second insulator; a second conductor over the first conductor; a third insulator over the second conductor; a fourth insulator in contact with side surfaces of the second insulator, the first conductor, the second conductor, and the third insulator; and a fifth insulator in contact with the top surface of the second oxide and a side surface of the fourth insulator.
Semiconductor Energy Laboratory Co., Ltd.

Bottom-gate transistor formed in surface recess

a bottom-gate transistor has a channel in a recess of a substrate surface. A gate electrode is disposed in and in contact with the recess.
Eastman Kodak Company

Method to improve finfet device performance

a method for manufacturing a semiconductor device includes providing a substrate structure having pmos and nmos regions. The pmos region includes a first region, a first gate structure on the first region, and first source and drain regions on opposite sides of the first gate structure.
Semiconductor Manufacturing International (beijing) Corporation

Semiconductor device and forming the semiconductor device

a semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate.. .
International Business Machines Corporation

Semiconductor devices and finfets

semiconductor devices and fin field effect transistors (finfets) are disclosed. In some embodiments, a representative semiconductor device includes a group iii material over a substrate, the group iii material comprising a thickness of about 2 monolayers or less, and a group iii-v material over the group iii material..
Taiwan Semiconductor Manufacturing Company, Ltd.

Dielectric isolated fin with improved fin profile

a method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer.
International Business Machines Corporation

Memory device comprising an electrically floating body transistor and methods of using

a semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed..
Zeno Semiconductor, Inc.

Fdsoi ldmos semiconductor device

semiconductor devices are provided that use both silicon on insulator region and bulk region of a fully depleted silicon on insulator (fdsoi) device. For example, a semiconductor device includes a drain region that is disposed above a first type well and a first drain extension region that is disposed above the first type well and laterally spaced apart from the drain region.
Broadcom Corporation

Wrap around silicide for finfets

a method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device and producing semiconductor device

a semiconductor device includes a planar semiconductor layer formed on a substrate; a pillar-shaped semiconductor layer formed on the planar semiconductor layer; a gate insulating film surrounding the pillar-shaped semiconductor layer; a first metal surrounding the gate insulating film, the first metal being in contact with an upper portion of the planar semiconductor layer; a gate formed above the first metal so as to surround the gate insulating film, the gate being electrically insulated from the first metal; and a second metal formed above the gate so as to surround the gate insulating film, the second metal being electrically insulated from the gate, the second metal having an upper portion electrically connected to an upper portion of the pillar-shaped semiconductor layer.. .
Unisantis Electronics Singapore Pte. Ltd.

Semiconductor device

a semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side.
Panasonic Intellectual Property Management Co., Ltd.

Methods of manufacturing a semiconductor device with a buried doped region and a contact structure

a method of manufacturing a semiconductor device includes: forming a doped region in a semiconductor substrate at a first distance to a main surface plane of the semiconductor substrate, wherein the doped region is a first section of a semiconductor column extending from the main surface plane into the semiconductor substrate; forming an insulator structure surrounding at least a second section of the semiconductor column between the main surface plane and the first section in planes parallel to the main surface plane; removing the second section of the semiconductor column; and forming a contact structure extending from the main surface plane to the doped region, wherein the contact structure includes a fill structure and a contact layer, the contact layer formed from a metal semiconductor alloy and directly adjoining the doped region and the fill structure formed from a metal and/or a conductive metal compound.. .
Infineon Technologies Dresden Gmbh

Semiconductor device having a trench gate

a semiconductor device includes a gate structure extending from a first surface into a semiconductor portion and having a metal gate electrode and a gate dielectric separating the metal gate electrode from the semiconductor portion. An interlayer dielectric separates a first load electrode from the semiconductor portion, and includes a screen oxide layer thinner than the gate dielectric.
Infineon Technologies Austria Ag

High voltage semiconductor devices and methods of making the devices

a multi-cell mosfet device including a mosfet cell with an integrated schottky diode is provided. The mosfet includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer.
Monolith Semiconductor Inc.

Semiconductor device and transistor cell having a diode region

according to an embodiment of a semiconductor device, the device includes a semiconductor body with a drift region and neighboring device cells integrated in the semiconductor body. Each device cell includes: a body region arranged between a source region and the drift region; a diode region and a pn junction between the diode region and the drift region; a trench with first and second opposing sidewalls and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the bottom; and a gate electrode arranged in the trench and dielectrically insulated from the semiconductor body by a gate dielectric.
Infineon Technologies Ag

Semiconductor device and manufacturing the semiconductor device

there is improved performance of a semiconductor device including a fin-type low-withstand-voltage transistor and a fin-type high-withstand-voltage transistor. A low-withstand-voltage transistor is formed on each of a plurality of first fins isolated from each other by a first element isolation film, and a high-withstand-voltage transistor, which has a channel region including tops and side surfaces of a plurality of second fins and a top of a semiconductor substrate between the second fins adjacent to each other, is formed.
Renesas Electronics Corporation

Iii-nitride semiconductor structures comprising spatially patterned implanted species

iii-nitride materials are generally described herein, including material structures comprising iii-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates..
Macom Technology Solutions Holdings, Inc.

Semiconductor device

a semiconductor device includes a semiconductor element, a laminated substrate including an insulating board and a circuit board disposed on the insulating board, the semiconductor element being mounted on the circuit board, a surrounding case having an opening, and being disposed on the outer peripheral portion of the insulating board to surround the circuit board, a relay substrate having a through hole and being disposed on the surrounding case to cover the opening, and an external connection terminal including a first end portion bonded to the circuit board, a second end portion, opposite to the first end portion, inserted into the through hole of the relay substrate from the rear surface of the relay substrate so as to be in contact with the front surface of the relay substrate, and an elastically deformable elastic portion between the first end portion and the second end portion.. .
Fuji Electric Co., Ltd.

Vertical channel semiconductor device with a reduced saturation voltage

a vertical channel semiconductor device including: a semiconductor body including a substrate having a first conductivity type and a front layer having a second conductivity type; a first portion of trench and a second portion of trench; and, within the first and second portions of trench, a corresponding conductive region and a corresponding insulating layer. The first and second portions of trench delimit laterally a first semiconductor region and a second semiconductor region, the first semiconductor region having a maximum width greater than the maximum width of the second semiconductor region.
Stmicroelectronics S.r.l.

Superlattice lateral bipolar junction transistor

a bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material.
International Business Machines Corporation

Array substrate and manufacturing the same, and display device

embodiments of the disclosure provide an array substrate and a manufacturing method thereof, and a display device. The method includes: forming a semiconductor material film, a first insulation material film and a first conductive material film successively on a base substrate, and processing these films through a single patterning process to form an active pattern, a gate insulation pattern and a gate electrode; forming a second insulation layer and forming two contact holes in the second insulation layer and gate insulation pattern; forming a second conductive material film and forming two contact structures from portions of this layer; and forming a third conductive material film, and processing this layer through a single patterning process to form a pixel electrode, and source and drain electrodes being in direct contact with the two contact structures respectively, the pixel electrode and one contact structure being integrated into one piece..
Boe Technology Group Co., Ltd.

Semiconductor devices

disclosed is a semiconductor device. The semiconductor device comprises a fin structure on a substrate, device isolation patterns provided on the substrate and disposed on opposite sides of the fin structure, a gate electrode running across the fin structure and the device isolation patterns, a gate dielectric pattern between the gate electrode and the fin structure and between the gate electrode and the device isolation patterns, and a capping layer between the substrate and the device isolation patterns and between the fin structure and the device isolation patterns.
Samsung Electronics Co., Ltd.

Laterally diffused metal-oxide-semiconductor field-effect transistor

provided is a laterally diffused metal-oxide-semiconductor field-effect transistor, comprising a substrate (110), a source (150), a drain (140), a body region (160), a p-type field-limiting ring (135), and a well region on the substrate (110); the well region comprises an inserted well (122), which has p-type doping and is disposed below the drain and connected to the drain; n wells (124) disposed at the two sides of the inserted well (122); a p well (126) disposed next to the n well (124) and connected to the n well (124); a p-type field-limiting ring (135), which is disposed inside the n well (124), is a closed ring-shaped structure, and is located at the periphery below the drain (140); the inserted well (122) extends in its longitudinal direction to the position where it is in contact with said p-type field-limiting ring (135); the source (150) and the body region (160) are disposed inside the p well (126).. .
Csmc Technologies Fab2 Co., Ltd.

Gap fill of metal stack in replacement gate process

a method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer.
International Business Machines Corporation

Methods for forming a plurality of semiconductor devices on a plurality of semiconductor wafers

a method for forming a plurality of semiconductor devices on a plurality of semiconductor wafers is provided. The method includes forming an electrically conductive layer on a surface of a first semiconductor wafer so that a schottky-contact is generated between the electrically conductive layer formed on the first semiconductor wafer and the first semiconductor wafer.
Infineon Technologies Ag

Transistors, memory cells and semiconductor constructions

some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate.
Micron Technology, Inc.

Nanolaminate structure, semiconductor device and forming nanolaminate structure

the present disclosure provides a method of forming a nanolaminate structure. First, a pre-treatment is performed on a semiconductor substrate, in which the semiconductor substrate includes sige.
The Regents Of The University Of California

Method and structure for forming mosfet with reduced parasitic capacitance

a method (and structure) of fabricating an mosfet (metal-oxide-semiconductor field-effect transistor), includes, on a gate structure coated with a high-k sidewall spacer film, etching off the high-k sidewall spacer film from a top surface of the gate structure and from a portion of vertical walls of the gate structure. The etched-off high-k sidewall spacer film on the vertical walls is replaced with an ultra low-k material..
International Business Machines Corporation

Thin-film transistor (tft) array substrate, manufacturing method thereof, and display device

a method of manufacturing a thin-film transistor (tft) array substrate, including: forming a gate layer, a gate insulating layer, an oxide semiconductor layer, a source/drain electrode layer and a pixel electrode layer on a base substrate. The step of forming the source/drain electrode layer and the pixel electrode layer includes: forming a transparent conductive film and a first metallic film on the oxide semiconductor layer in sequence, to form a stack layer of the transparent conductive film and the first metallic film, in which the transparent conductive film contacts the oxide semiconductor layer; and forming source electrodes, drain electrodes and pixel electrodes by a single patterning process on the stack layer of the transparent conductive film and the first metallic film.
Beijing Boe Display Technology Co., Ltd.

Integration of vertical-transport transistors and electrical fuses

structures for a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit, and methods of fabricating a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit. A doped semiconductor layer that includes a first region with a first electrode of the vertical electrical fuse and a second region with a first source/drain region of the vertical-transport field effect transistor.
Globalfoundries Inc.

Semiconductor device and manufacturing the same

a semiconductor device according to an exemplary embodiment of the present invention includes: a current applying region; and a termination region disposed at an end portion of the current applying region. The termination region includes: an n− type layer disposed on a first surface of an n+ type silicon carbide substrate; a p type termination structure disposed in the n− type layer; and a lower gate runner disposed on the p type termination structure such that the lower gate runner overlaps the p type termination structure..
Hyundai Motor Company

Semiconductor device and formation

a semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate.
National Taiwan University

Silicon germanium alloy fin with multiple threshold voltages

a semiconductor structure is provided that includes a strained silicon germanium alloy fin structure and a relaxed silicon germanium alloy fin structure located in different device regions of a substrate. The relaxed silicon germanium alloy fin provides a higher threshold voltage than the strained silicon germanium alloy fin structure..
International Business Machines Corporation

Semiconductor devices and manufacturing the same

a semiconductor device includes a substrate, a plurality of gate electrodes extending in a first direction parallel to an upper surface of a substrate on the substrate, and alternately arranged with an interlayer insulating layer in a second direction perpendicular to the upper surface of the substrate, a vertical channel layer on a sidewall of a vertical channel hole extending in the second direction by penetrating through the plurality of gate electrodes and the interlayer insulating layer, and connected to the upper surface of the substrate, and a first gap-fill insulating layer formed in the vertical channel hole and including an outer wall contacting the vertical channel layer and an inner wall opposite the outer wall, wherein a part of the inner wall forms a striation extending in the second direction.. .

Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device

the contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers.
Sandisk Technologies Llc

Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device

sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions.
Sandisk Technologies Llc

Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device

a etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail.
Sandisk Technologies Llc

Integration methods to fabricate internal spacers for nanowire devices

a nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack.
Intel Corporation

Semiconductor device with air gap and fabricating the same

a semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.. .
Sk Hynix Inc.

Semiconductor device and fabricating the same

a method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask on the substrate and the gate structure, patterning the hard mask to form trenches exposing part of the substrate, and forming raised epitaxial layers in the trenches. Preferably, the gate structure is extended along a first direction on the substrate and the raised epitaxial layers are elongated along a second direction adjacent to two sides of the gate structure..
United Microelectronics Corp.

Novel channel stop imp for the finfet device

a method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, a semiconductor fin on the substrate, and an isolation region on opposite sides of the semiconductor fin, the isolation region having an upper surface substantially flush with an upper surface of the at least one semiconductor fin. The method also includes implanting ions into the substrate structure to form a doped region in the semiconductor fin and in the isolation region, etching back the isolation region to expose a portion of the semiconductor fin, and performing an annealing process to activate the implanted ions in the doped region.
Semiconductor Manufacturing International (beijing) Corporation

Method of manufacturing semiconductor devices and semiconductor device containing hydrogen-related donors

crystal lattice defects are generated in a horizontal surface portion of a semiconductor substrate and hydrogen-related donors are formed in the surface portion. Information is obtained about a cumulative dopant concentration of dopants, including the hydrogen-related donors, in the surface portion.
Infineon Technologies Ag

Semiconductor device and manufacturing the same

according to one embodiment, a semiconductor device includes first to fourth semiconductor regions, a first electrode, and a first insulating film. The first semiconductor region includes a first partial region and a second partial region.
Kabushiki Kaisha Toshiba

Beol capacitor through airgap metallization

a backend-of-the-line (beol) semiconductor capacitor made by method, apparatus, or computer program product, through an airgap metallization process, patterning a first electrode by removing a portion of inter-layer dielectric for a desired capacitor area, depositing a dielectric for a capacitor insulator, filling the desired capacitor area to form a second electrode, polishing and capping the second electrode, and interconnecting the first electrode and the second electrode. The manufactured product has a bottom electrode, composed of a conductor, electrically connected to upward conductive prominences; a low-k layer, above and conjoined to the bottom layer and surrounding the prominences, composed of a low-k dielectric; an isolation layer, above the low-k layer and surrounding the prominences, composed of a high-k insulator material, where modulating its material and thickness controls the capacitance; and a top electrode, composed of a conductor and electrically connected to downward prominences, where the bottom and top electrodes are interconnected..
International Business Machines Corporation

Semiconductor device resistor structure

a resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate.
Globalfoundries Inc.

Organic light-emitting display device

an organic light-emitting display device is discussed, which reduces the area of a pixel drive circuit and increases the aperture ratio of a pixel by forming lines inside the pixel using a semiconductor pattern that forms a channel of each thin-film transistor array. The light-emitting display device includes a plurality of pixels arranged in a matrix form and a plurality of lines configured to supply a signal for driving each pixel, each pixel includes a thin-film transistor including an active layer having a first area and a second area, which are configured as conductors, and a gate electrode, and at least one of the first area and the second area is directly connected to a corresponding line among the lines..
Lg Display Co., Ltd.

Semiconductor device

semiconductor elements deteriorate or are destroyed due to electrostatic discharge damage. The present invention provides a semiconductor device in which a protecting means is formed in each pixel.
Semiconductor Energy Laboratory Co., Ltd.

Light emitting device including tandem structure

a light emitting device comprising: a pair of electrodes; two or more light emitting elements disposed between the electrodes in a stacked arrangement, wherein a light emitting element comprises a layer comprising an emissive material, and a charge generation element disposed between adjacent light emitting elements in the stacked arrangement, the charge generation element comprising a first layer comprising an inorganic n-type semiconductor material, and a second layer comprising a hole injection material. A charge generation is also disclosed..
Samsung Electronics Co., Ltd.

Arrays of memory cells and methods of forming an array of memory cells

an array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines.
Micron Technology, Inc.

Magnetic random access memory and manufacture thereof

a magnetic random access memory and its manufacturing method related to semiconductor techniques. The magnetic random access memory comprises a word line, a bit line, and a memory unit positioned between the word line and the bit line, wherein the memory unit comprises a fixture layer connecting the bit line, a free layer connecting the word line, and an insulation layer positioned between the fixture layer and the free layer.
Semiconductor Manufacturing International (beijing) Corporation

Electronic device and fabricating the same

this technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a substrate; an interlayer dielectric layer over the substrate and patterned to include a contact hole; a lower contact structure formed over the substrate in the contact hole; and a variable resistance element formed over and electrically coupled to the lower contact structure, wherein the lower contact structure may include: a spacer formed on sidewalls of the contact hole in the interlayer dielectric layer and having a substantially uniform thickness along a direction perpendicular to a surface of the substrate; a contact plug filling a portion of the contact hole; and a contact pad formed over the contact plug and filling a remaining portion of the contact hole..
Sk Hynix Inc.

Light-emitting diode chip

a light-emitting diode (led) chip includes a substrate, a light-emitting component, an electrical static discharge (esd) protection component, and a conductive layer. The light-emitting component is disposed on the substrate and includes a first semiconductor layer, a first quantum well layer, and a second semiconductor layer, in which the first quantum well layer is disposed between the first and second semiconductor layers.
Lextar Electronics Corporation

Photoelectric conversion apparatus and image pickup system

a photoelectric conversion apparatus includes a plurality of units each including a charge generation region disposed in a semiconductor layer. Each of a first unit and a second unit of the plurality of units includes a charge storage region configured to store charges transferred thereto from the charge generation region, a dielectric region located above the charge generation region and surrounded by an insulator layer, and a first light-shielding layer covering the charge storage region that is located between the insulator layer and the semiconductor layer, and the first light-shielding layer having an opening located above the charge generation region.
Canon Kabushiki Kaisha

Low noise ingaas photodiode array

a photodiode pixel structure for imaging short wave infrared (swir) and visible light built in a planar structure and may be used for one dimensional and two dimensional photodiode arrays. The photodiode arrays may be hybridized to a read out integrated circuit (roic), for example, a silicon complementary metal-oxide-semiconductor (cmos) circuit.
Princeton Infrared Technologies, Inc.

Semiconductor device, solid-state imaging device and electronic apparatus

a semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.. .
Sony Corporation

Systems and methods for imaging using single photon avalanche diodes

single-photon avalanche diode includes a central junction having a central p+ area and a deep-n well in contact with the central p+ area, a p-type guard ring disposed between the central junction and the deep-n well, and a shallow trench isolation separated from the central p+ area. Imaging apparatus includes a plurality of pixels, each pixel comprising a complementary metal-oxide-semiconductor-implemented single photon avalanche device and one or more signal converters electrically coupled thereto and configured to detect changes in output therefrom..
The Trustees Of Columbia University In The City Of New York

Semiconductor module, mos type solid-state image pickup device, camera and manufacturing camera

a back-illuminated type mos (metal-oxide semiconductor) solid-state image pickup device 32 in which micro pads 34, 37 are formed on the wiring layer side and a signal processing chip 33 having micro pads 35, 38 formed on the wiring layer at the positions corresponding to the micro pads 34, 37 of the mos solid-state image pickup device 32 are connected by micro bumps 36, 39. In a semiconductor module including the mos type solid-state image pickup device, at the same time an image processing speed can be increased, simultaneity within the picture can be realized and image quality can be improved, a manufacturing process can be facilitated, and a yield can be improved.
Sony Corporation

Trench between stacked semiconductor substrates making contact with source-drain region

a semiconductor device includes a first semiconductor substrate with a first transistor therein. The first transistor includes a first source-drain formed by a doped region in the first semiconductor substrate.
Stmicroelectronics (crolles 2) Sas

Substrate bonding apparatus and manufacturing semiconductor device using the same

disclosed are a substrate bonding apparatus and a method of manufacturing a semiconductor device. The substrate bonding apparatus comprises vacuum pumps, a first chuck engaged with the vacuum pumps and adsorbing a first substrate at vacuum pressure of the vacuum pumps, and a pushing unit penetrating a center of the first chuck and pushing the first substrate away from the first chuck.
Samsung Electronics Co., Ltd.

Selective deposition and planarization for a cmos image sensor

the present application relates to a method to simplify the scribe line opening filling processes, and to further improve the surface uniformity of the conductive pad fabrication process. A passivation layer is formed over a semiconductor substrate, and a scribe line opening is formed through the passivation layer and the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device with a radiation sensing region and forming the same

a semiconductor device includes a semiconductor substrate, a radiation-sensing region, at least one isolation structure, and a doped passivation layer. The radiation-sensing region is present in the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Imaging panel and x-ray imaging device including same

a shift of a threshold voltage of a thin film transistor upon x-ray irradiation is suppressed. An imaging panel having a plurality of pixels, for picking up scintillation light obtained by converting x-ray projected from an x-ray source, with use of a scintillator, includes photodiodes 15, tfts 14, and an organic film 43.
Sharp Kabushiki Kaisha

Display device

a display device comprising: a first tft using silicon (si) and a second tft using oxide semiconductor are formed on a substrate, a distance between the silicon (si) and the substrate is smaller than a distance between the oxide semiconductor and the substrate, a drain source electrode of the first tft connects with the silicon (si) via a first through hole, a drain source electrode of the second tft connects with the oxide semiconductor via a second through hole, metal films are made on the oxide semiconductor sandwiching a channel of the oxide semiconductor in a plan view, the channel has a channel width, an alo layer is formed on the metal films and the oxide semiconductor, the second source drain electrode and the metal films are connected via the second through hole formed in the alo layer.. .
Japan Display Inc.

Semiconductor device and manufacturing method thereof

as a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount ic chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased.
Semiconductor Energy Laboratory Co., Ltd.

Thin film transistor substrate having bi-layer oxide semiconductor

the present disclosure relates to a thin film transistor substrate having a bi-layer oxide semiconductor. The present disclosure provides a thin film transistor substrate comprising: a substrate; and an oxide semiconductor layer on the substrate, wherein the oxide semiconductor layer includes: a first oxide semiconductor layer having indium, gallium and zinc; and a second oxide semiconductor layer stacked on the first oxide semiconductor layer having the indium, gallium and zinc, wherein any one layer of the first and the second oxide semiconductor layers has a first composition ratio of the indium, gallium and zinc of 1:1:1; and wherein other layer has a second composition ratio of the indium, gallium and zinc in which the indium ratio is higher than the zinc ratio..
Lg Display Co. , Ltd.

Ultra high resolution liquid crystal display

the present disclosure relates to an ultra high resolution liquid crystal display having a compensation thin film transistor. The present disclosure provides an ultra high density liquid crystal display comprising: a gate line on a substrate; a first gate insulating layer on the gate line; a first semiconductor layer crossing the gate line on the first gate insulating layer; a second gate insulating layer on the first semiconductor layer; a second semiconductor layer crossing the gate line on the second gate insulating layer; an intermediate insulating layer on the second semiconductor layer; a data line connected to the first semiconductor layer on the intermediate insulating layer; and a drain electrode connected to the second semiconductor layer on the intermediate insulating layer..
Lg Display Co., Ltd.

Display device and manufacturing display device

a highly flexible display device and a method for manufacturing the display device are provided. A transistor including a light-transmitting semiconductor film, a capacitor including a first electrode, a second electrode, and a dielectric film between the first electrode and the second electrode, and a first insulating film covering the semiconductor film are formed over a flexible substrate.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and manufacturing the same

a semiconductor device using an soi (silicon on insulator) substrate, capable of preventing malfunction of misfets (metal insulator semiconductor field effect transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the misfets is reduced, and the performance of the semiconductor device is improved.
Renesas Electronics Corporation

Standard cell architecture with m1 layer unidirectional routing

a standard cell cmos device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction.
Qualcomm Incorporated

Vertical memory devices and methods of manufacturing the same

a vertical memory device includes a first structure having a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate, the lower semiconductor pattern structure including a first undoped semiconductor pattern, a doped semiconductor pattern, and a second undoped semiconductor pattern sequentially stacked, and a lower surface of the doped semiconductor pattern being lower than the upper surface of the substrate, and an upper semiconductor pattern extending in the first direction on the lower semiconductor pattern structure, and a plurality of gate electrodes surrounding a sidewall of the first structure, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction.. .

Method of manufacturing semiconductor device

a method of manufacturing a semiconductor device includes forming a mold structure including alternately stacked mold insulating and sacrificial layers on a substrate, forming a vertical structure through the mold structure, forming side openings by removing the sacrificial, forming a preliminary dielectric layer in the side openings, forming a dielectric layer by heat-treating the preliminary dielectric layer, removing a surface layer of the dielectric layer, forming a first conductive layer covering the dielectric layer in the side openings, and forming a second conductive layer covering the first conductive layer and filling the side openings.. .

Method for forming flash memory structure

methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a control gate over a substrate and forming a dielectric layer covering the control gate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Vertical memory device

a vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region.

Memory device and fabricating thereof

a memory device includes a semiconductor substrate having a cell region and a peripheral region surrounding the cell region and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

a semiconductor device is provided. The semiconductor device includes an upper interlayer insulating layer disposed on a substrate.
Samsung Electronics Co., Ltd.

Methods and apparatuses including an active area of a tap intersected by a boundary of a well

apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity.
Micron Technology, Inc.

Semiconductor device and forming the semiconductor device

a semiconductor device includes a semiconductor fin formed on a substrate, a first gate formed around the semiconductor fin, and a second gate formed around the semiconductor fin below the first gate and separated from the first gate.. .
International Business Machines Corporation

Method to improve the high k quality for finfet

a method of manufacturing a semiconductor device includes providing a substrate structure including pmos and nmos regions having respective first and second trenches, a high-k dielectric layer in the first and second trenches, and a first p-type work function adjustment layer on the high-k dielectric layer, sequentially forming first and second protective layers and a mask layer on the substrate structure, removing a portion of the mask layer exposing a portion of the second protective layer on the nmos region, removing the exposed portion of the second protective layer on the nmos region exposing a portion of the first protective layer on the nmos region, removing the mask layer exposing the second protective layer on the pmos region, removing portions of the first protective layer and first p-type work function adjustment layer on the nmos region and removing the second and first protective layers on the pmos region.. .
Semiconductor Manufacturing International (beijing) Corporation

Semiconductor device and fabricating the same

the present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (mos) regions.
Taiwan Semiconductor Manufacturing Company, Ltd.

Circuit arrangement having a first semiconductor switch and a second semiconductor switch

a circuit has first and second semiconductor switches, each of which has a load path and control terminal connected in series. Each switch includes a first semiconductor device having a load path and a control terminal coupled to the control terminal of its switch, and a second semiconductor device having a load path between first and second load terminals, and a control terminal.
Infineon Technologies Dresden Gmbh

Methods for fabricating fin field effect transistors

methods for fabricating fin field effect transistors (finfets) are disclosed. First and second semiconductor fins and an insulator therebetween are formed.
Taiwan Semiconductor Manufacturing Co., Ltd.

Fin cut during replacement gate formation

a method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins.
International Business Machines Corporation

Forming on-chip metal-insulator-semiconductor capacitor

a method is presented for forming a semiconductor structure. The method includes forming a plurality of fins on a first region of the semiconductor substrate, forming a bi-polymer structure, selectively removing the first polymer of the bi-polymer structure and forming deep trenches in the semiconductor substrate resulting in pillars in a second region of the semiconductor structure.
International Business Machines Corporation

Forming on-chip metal-insulator-semiconductor capacitor

a method is presented for forming a semiconductor structure. The method includes forming a plurality of fins on a first region of the semiconductor substrate, forming a bi-polymer structure, selectively removing the first polymer of the bi-polymer structure and forming deep trenches in the semiconductor substrate resulting in pillars in a second region of the semiconductor structure.
International Business Machines Corporation

Vertical transistors with merged active area regions

a semiconductor device includes a substrate and an active area region forming a bottom source/drain region on the substrate. Vertical transistors are formed on the bottom source/drain region, where the bottom source/drain region is shared between the vertical transistors..
International Business Machines Corporation

Semiconductor package

a semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1a semiconductor chip, a 1b semiconductor chip, a 2a semiconductor chip, and a 2b semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1a semiconductor chip, the 1b semiconductor chip, the 2a semiconductor chip, and the 2b semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.. .
Samsung Electronics Co., Ltd.

Semiconductor package and manufacturing the semiconductor package

a semiconductor package includes a mold substrate, at least one first semiconductor chip in the mold substrate and including chip pads, wiring bonding pads formed at a first surface of the mold substrate and connected to the chip pads by bonding wires, and a redistribution wiring layer covering the first surface of the mold substrate and including redistribution wirings connected to the wiring bonding wirings.. .
Samsung Electronics Co., Ltd.

Light emitting device and manufacturing method thereof

a light emitting diode includes a semiconductor structure, a first electrode, a second electrode, and an extending electrode. The semiconductor structure has at least one sidewall and includes a light emitting layer, a first semiconductor layer, and a second semiconductor layer.
Au Optronics Corporation

Direct bandgap semiconductor bonded to silicon photonics

according to an example of the present disclosure a direct bandgap (dbg) semiconductor structure is bonded to an assembly comprising a silicon photonics (sip) wafer and a complementary metal-oxide-semiconductor (cmos) wafer. The sip wafer includes photonics circuitry and the cmos wafer includes electronic circuitry.
Hewlett Packard Enterprise Development Lp

Semiconductor device and manufacture

a semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (rdl), the first set of through vias in physical contact with a molding compound and separated from a die.
Taiwan Semiconductor Manufacturing Company, Ltd.

Hybrid micro-circuit device with stacked chip components

a hybrid micro-circuit device has multiple layers overlying a printed circuit board (pcb), including a first semiconductor chip component that is electrically connected to the pcb, and a second semiconductor chip component that is electrically connected to first semiconductor chip component. A molding compound surrounds the stack of components that includes the semiconductor chip components.
Raytheon Company

Semiconductor device structure

a semiconductor device structure is provided. The semiconductor device structure has a first surface and a second surface.
Taiwan Semiconductor Manufacturing Co., Ltd.

Redistribution layers in semiconductor packages and methods of forming same

an embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, a conductive line electrically connecting a first conductive via to a second conductive via, the conductive line including a first segment over the first integrated circuit die and having a first width, and a second segment over the first integrated circuit die having a second width larger than the first width, the second segment extending over a first boundary between the first integrated circuit die and the encapsulant.. .
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device

a semiconductor device includes: a first chip including one of a logic circuit and a memory circuit and mounted over a substrate with a circuit surface of the first chip facing up; a second chip including the other of the logic circuit and the memory circuit and mounted over the first chip with a circuit surface of the second chip facing down such that the logic circuit and the memory circuit are coupled via a first connection electrode; and a third chip mounted between the substrate and the second chip with a circuit surface of the third chip facing down and includes: an interface circuit that converts between a first signal which is transmitted with the logic circuit or memory circuit and a second signal which is transmitted with an outside; and a first through electrode coupling the logic circuit or memory circuit and the interface circuit.. .
Fujitsu Limited

Semiconductor packages

a semiconductor package includes a first package and a second package stacked on the first package. The first package includes a redistribution substrate, a first semiconductor chip on the redistribution substrate, a connection substrate provided on the redistribution substrate to surround the first semiconductor chip as viewed in plan, and an inductor structure provided within a first region of the connection substrate and electrically connected to the first semiconductor chip through the redistribution substrate.

Semiconductor packages having asymmetric chip stack structure

a semiconductor package may include first chip stack including first chips which are stacked on a package substrate and offset to form a first reverse stepwise sidewall. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate and offset to form a second reverse stepwise sidewall.
Sk Hynix Inc.

Spring element for a power semiconductor module

the present invention relates to a spring element for a power semiconductor module, wherein the spring element includes a first part made from a first material and a second part made from a second material, the first material being different from the second material, wherein the first part comprises both a first contact portion having a first contact and a second contact portion having a second contact, wherein the first part comprises an electrically conductive path formed from the first contact portion to the second contact portion, and wherein the second part is adapted for exerting a spring force (fs) onto the first contact portion and the second contact portion for pressing the first contact to a first contact area of a power semiconductor module and the second contact to a second contact area of a power semiconductor module. Such a spring element may form a press contact in a power semiconductor module and may be less bulky compared to solutions in the prior art and may be formed cost-sparingly..
Abb Schweiz Ag

Electronic device

an electronic device includes: a substrate having an upper surface (front surface) on which a semiconductor chip is mounted, and a lower surface (back surface) opposite to the upper surface; and a housing (case) fixed to the substrate through an adhesive material. The housing has through-holes each formed on one short side and the other short side in an x direction.
Renesas Electronics Corporation

Semiconductor device

a performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip.
Renesas Electronics Corporation

Bonding wire for semiconductor device

a bonding wire for a semiconductor device includes a cu alloy core material and a pd coating layer on a surface of the cu alloy core material, and contains ga and ge of 0.011 to 1.2% by mass in total, which is able to increase bonding longevity of the ball bonded part in the high-temperature, high-humidity environment, and thus to improve the bonding reliability. The thickness of the pd coating layer is preferably 0.015 to 0.150 μm.
Nippon Steel & Sumikin Materials Co., Ltd.

Leadless package with non-collapsible bump

a leadless package semiconductor device has a top surface, a bottom surface opposite to the top surface, and multiple sidewalls between the top and bottom surfaces. At least one connection pad is disposed on the bottom surface.
Nexperia B.v.

Semiconductor devices with underfill control features, and associated systems and methods

semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface.
Micron Technology, Inc.

Semiconductor device package and forming the same

a semiconductor device package ready for assembly includes: a semiconductor substrate; a first under-bump-metallurgy (ubm) layer disposed on the semiconductor substrate; a first conductive pillar disposed on the first ubm layer; and a second conductive pillar disposed on the first conductive pillar. A material of the first conductive pillar is different from a material of the second conductive pillar, and the material of the second conductive pillar includes an antioxidant..
Advanced Semiconductor Engineering, Inc.

Semiconductor device and manufacturing the same

a semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.. .
Socionext Inc.

Fan-out semiconductor package and manufacturing the fan-out semiconductor

a fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, the semiconductor chip having an active surface with connection pads disposed thereon and the semiconductor chip having an inactive surface opposing the active surface, an encapsulant, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, wherein the first connection member and the second connection member include redistribution layers electrically connected to the connection pads, wherein the semiconductor chip includes a first passivation layer disposed on the active surface and the semiconductor chip includes a second passivation layer disposed on the first passivation layer, and wherein the redistribution layer of the second connection member is directly formed on one surface of the second passivation layer and extends onto one surface of the first connection member.. .
Samsung Electro-mechanics Co., Ltd.

Radio frequency (rf) apparatus

a radio-frequency (rf) apparatus that reduces signal reflections at input and output terminals is disclosed. The rf apparatus includes an assembly base and a semiconductor chip mounted on the assembly base in upside down.
Sumitomo Electric Industries. Ltd.

On-die seal rings

aspects of the disclosure provide an integrated circuit (ic) formed on a die. The ic includes first one or more electronic circuits and a seal ring structure.
Marvell Israel (m.i.s.l) Ltd.

Ic with insulating trench and related methods

a method of making an integrated circuit (ic) includes forming circuitry over a top surface of a semiconductor substrate having the top surface and an opposite bottom surface. An antenna is formed in an interconnect layer formed above the semiconductor substrate, where the antenna is coupled to circuitry.
Stmicroelectronics S.r.i.

Semiconductor package structure and manufacturing the same

various embodiments relate to a semiconductor package structure. The semiconductor package structure includes a first chip having a first surface and a second surface opposite the first surface.
Advanced Semiconductor Engineering, Inc.

Semiconductor wafer, semiconductor package and manufacturing the same

a semiconductor wafer includes a substrate structure, a first insulation layer, a conductive layer and a second insulation layer. The substrate structure defines a via.
Advanced Semiconductor Engineering, Inc.

Semiconductor package assembly

the invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate, a semiconductor die, a base and a first inductor structure.
Mediatek Inc.

Cooler with emi-limiting inductor

a power device package includes a dielectric substrate having an upper conductor layer and a lower conductor layer, a semiconductor die coupled to the upper conductor layer of the dielectric substrate via conductive adhesive, a cooler including a protruding hillock having a top surface and outer sides, the lower conductor layer of the dielectric substrate being coupled to the surface of the protruding hillock via an adhesive, and a magnetic material attached mateably around the protruding hillock. The magnetic material includes inner sides abutting the outer sides of the protruding hillock..
Virginia Tech Intellectual Properties, Inc.

Method for fabricating a local interconnect in a semiconductor device

a semiconductor device includes a first transistor having a first gate, a first source and a first drain, a second transistor having a second gate, a second source and a second drain, an isolation region separating the first transistor from the second transistor, and a local interconnect connecting at least one of the first source and the first drain to at least the second source and the second drain. The local interconnect is in contact with a surface of the at least one of the first source and the first drain, a surface of the at least the second source and the second drain and a surface of a part of the isolation region..
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor memory devices

a memory device includes a vertical string of nonvolatile memory cells on a substrate, along with a ground selection transistor extending between the vertical string of nonvolatile memory cells and the substrate. The ground selection transistor can have a current carrying terminal electrically coupled to a channel region of a nonvolatile memory cell in the vertical string of nonvolatile memory cells.

Semiconductor device and semiconductor package including the same

a semiconductor device includes a substrate having a cell region and a circuit region, an upper wiring layer on the substrate, and a redistribution wiring layer on the upper wiring layer. The upper wiring layer includes a secondary uppermost wiring in the circuit region and an uppermost wiring on the secondary uppermost wiring.

Structure and formation semiconductor device structure

structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device and manufacturing method thereof

a semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings.
Taiwan Semiconductor Manufacturing Co., Ltd.

Plated ditch pre-mold lead frame, semiconductor package, and making same

an integrated circuit chip package and method for making the same, wherein the integrated circuit chip package includes conductive leads. The method includes trenching a plurality of conductive lead structures along a parting line, plating the trenches with a plating layer, and singulating the lead frame assembly along the parting line to produce an integrated circuit chip package with conductive leads having unplated side portions and plated recessed portions..
Texas Instruments Incorporated

High power and high frequency plastic pre-molded cavity package

a cavity package is set forth along with a method of manufacturing thereof. According to one embodiment, the method comprises attaching a metal heat sink to a leadframe using an intermediate structure that is thermally conductive and electrically insulating; molding a plastic body around the heat sink and exposed leads of the leadframe to form a cavity, with partially and selectively exposed lead top surfaces, heat sink top surface, and heat sink bottom surface; attaching a semiconductor device die within cavity on to the exposed top surface of the heat sink using a thermal conductive material; wire bonding respective wire bond pads of the semiconductor device die to the exposed lead top surfaces and to the heat sink for grounding; and attaching a lid to the plastic molded body to protect the wire bonded device within cavity..
Ubotic Company Limited

Semiconductor packages and methods for forming same

one or more embodiments are directed to a semiconductor package that includes an integrated heatsink and methods of forming same. In one embodiment, the semiconductor package includes a semiconductor die coupled to a first surface of a die pad.
Stmicroelectronics Pte Ltd

Semiconductor device

to improve the reliability of a semiconductor device. A chip mounting portion tab5 is arranged to be shifted to the +x direction side.
Renesas Electronics Corporation

Semiconductor device

a semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof..
Rohm Co., Ltd.

Semiconductor die package and manufacturing method

in a general aspect, an apparatus can include a semiconductor die, a substrate, and a leadframe coupled to the substrate. The apparatus can include a conductive clip coupled to the semiconductor die.
Fairchild Korea Semiconductor Ltd.

Semiconductor device having leadframe with pressure-absorbing pad straps

a leadframe (300) for use in semiconductor devices, comprising an assembly pad (3010 having rectangular sides, the pad extending, on one pad side (301b), into a lead (302) and, on the opposite pad side (301a), into straps (350) oriented normal to the side (301a) and anchored in adjacent tie bars (313), strap surfaces having recesses (501, 502) suitable for interlocking with packaging materials. The leadframe further includes a plurality of leads (303) parallel to and alternating with the straps..

Semiconductor device

a semiconductor device is provided, including: a bottom portion having a pad formed of a conductive material; a lid portion covering at least a part of the bottom portion; and a first terminal portion and a second terminal portion which are provided in parallel with each other, are fixed to the lid portion, and each contact a corresponding pad, wherein: the first terminal portion is provided with a first plate-shaped portion; the second terminal portion is provided with a second plate-shaped portion; and each of the first plate-shaped portion and the second plate-shaped portion has a principal surface in a direction facing the pad and is flexible in a direction toward the pad.. .
Fuji Electric Co., Ltd.

Semiconductor device and process for fabricating the same

a thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode.
Lapis Semiconductor Co., Ltd.

Plug structure of a semiconductor chip and manufacturing the same

a plug structure of a semiconductor chip includes a substrate, an insulating interlayer disposed on the substrate, wherein the insulating interlayer includes a pad structure disposed therein, a via hole penetrating the substrate and the insulating interlayer, wherein the via hole exposes the pad structure, an insulating pattern formed on an interior surface of the via hole, wherein the insulating pattern includes a burying portion, and the burying portion fills a notch disposed in the substrate at the interior surface of the via hole, and a plug formed on the insulating pattern within the via hole, wherein the plug is electrically connected with the pad structure.. .
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing the same

a semiconductor device includes: a semiconductor substrate; a gate electrode on the semiconductor substrate; a sin film on the semiconductor substrate and the gate electrode; and an oxide film on the sin film, wherein the oxide film is an atomic layer deposition film including atomic layers alternately deposited.. .
Mitsubishi Electric Corporation

Method of manufacturing semiconductor device

a method of manufacturing a semiconductor device, the method may include: forming a sog film on a wafer, the wafer including a semiconductor substrate and a polyimide film exposed on a surface of the wafer, and the sog film being formed so as to cover the polyimide film; applying a protection tape on a surface of the sog film; processing the wafer on which the protection tape is applied; and peeling the protection tape from the wafer.. .
Toyota Jidosha Kabushiki Kaisha

Environmental protection for wafer level and package level applications

a method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die..
Qorvo Us, Inc.

Semiconductor device

a semiconductor device is provided. The semiconductor device includes a terminal portion and a casing portion.
Fuji Electric Co., Ltd.

Gate height and spacer uniformity

embodiments are directed to a method of forming a semiconductor device and resulting structures having self-aligned spacer protection layers. The method includes forming a first sacrificial gate adjacent to a second sacrificial gate on a substrate.
International Business Machines Corporation

Methods for forming a semiconductor device and related semiconductor device structures

methods for forming a semiconductor device and related semiconductor device structures are provided. In some embodiments, methods may include forming an nmos gate dielectric and a pmos gate dielectric over a substrate and forming a first work function metal over the nmos gate dielectric and over the pmos gate dielectric.
Asm Ip Holding B.v.

Fin cut during replacement gate formation

a method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins.
International Business Machines Corporation

Method for forming semiconductor device

the present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a nmos region and a pmos region defined thereon, next, a gate structure is formed on the substrate within the nmos region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the pmos region to expose the nmos region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the nmos region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.. .
United Microelectronics Corp.

Method for fabricating semiconductor device

first, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ild) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different.
United Microelectronics Corp.

Dummy gate structures and manufacturing methods thereof

a semiconductor device includes a semiconductor substrate, a fin protruding from the semiconductor substrate, a trench on opposite sides of the fin, a first insulator layer partially filling the trench, a second insulator layer on the fin, a plurality of dummy gate structures for the fin and including a first dummy gate structure on the first insulator layer and a second dummy gate structure on the second insulator layer, the first dummy gate structure adjacent to a portion of the second insulator layer on a side surface of the one or more fins, a spacer on side surfaces of the dummy gate structures, and a source or drain in the fin and between the dummy gate structures. The fin protrudes from the first insulator layer.
Semiconductor Manufacturing International (beijing) Corporation

Stacked transistors with different channel widths

a semiconductor device includes a first gate stack arranged about a first nanowire and a second nanowire, the first nanowire is arranged above a second nanowire, the first nanowire is connected to a first source/drain region and a second source/drain region. A second gate stack is arranged about a third nanowire and a fourth nanowire, the third nanowire is arranged above a fourth nanowire, the third nanowire is connected to a third source/drain region and a fourth source/drain region.
International Business Machines Corporation

Semiconductor structure and fabrication method thereof

a semiconductor structure and a fabrication method are provided. A fabrication method includes providing a substrate including an nmos region and a pmos region; forming a first high-k gate dielectric layer on the nmos region of the substrate; forming an interfacial layer on the pmos region of the substrate; forming a second high-k gate dielectric layer on the interfacial layer and the first high-k gate dielectric layer; forming a metal layer on the second high-k gate dielectric layer..
Semiconductor Manufacturing International (beijing) Corporation

Through substrate via (tsv) and method therefor

a through substrate via (tsv) and method of forming the same are provided. The method of making the tsv may include etching a via opening into the backside of semiconductor substrate, the via opening exposing a surface of a metal landing structure.
Freescale Semiconductor, Inc.

Semiconductor device and forming the semiconductor device

a method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second dielectric layer on the first dielectric layer, and forming a second contact hole in the second dielectric layer, the second contact hole being aligned with the first contact hole, removing the sacrificial layer from the first contact hole, and forming a copper contact in the first and second contact holes.. .
International Business Machines Corporation

Semiconductor device having interconnection structure

a semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure.

Method for forming semiconductor structure

a method for forming a semiconductor structure is provided, including the following steps. A first dielectric layer is formed on a substrate.
United Microelectronics Corp.

Structure and method to improve fav rie process margin and electromigration

a method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ild), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.. .
International Business Machines Corporation

Structure and method to improve fav rie process margin and electromigration

a method of forming fully aligned vias in a semiconductor device, the method including recessing a first level interconnect line below a first interlevel dielectric (ild), laterally etching the exposed upper portion of the first interlevel dielectric bounding the recess, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.. .
International Business Machines Corporation

Image tone-reversal with a dielectric using bottom-up cross-linking for back end of line (beol) interconnects

image tone-reversal with a dielectric using bottom-up cross-linking for back end of line (beol) interconnects is described. In an example, a semiconductor structure including a metallization layer includes a plurality of trenches in an interlayer dielectric (ild) layer above a substrate.
Intel Corporation

3d semiconductor device and structure

a 3d device, the device including: a first stratum including an array of memory bit cells, the array of memory bit cells is controlled via a plurality of bit-lines and a plurality of word-lines; and a second stratum overlaying the first stratum, the second stratum including memory control circuits, where the control circuits provide control of the plurality of bit-lines and the plurality of word-lines.. .
Monolithic 3d Inc.

Apparatus for picking semiconductor devices

an apparatus for picking up one or more semiconductor devices includes a body having an air chamber that communicates with surroundings outside of the body and at least a first supply line through which compressed air is supplied into the air chamber, a pickup cylinder penetrating through the body and movably installed in the body, a suction pad being provided at an end portion of the pickup cylinder, and a power transformer secured to the pickup cylinder and transforming an air pressure of the air chamber to a driving force for driving the pickup cylinder.. .
Samsung Electronics Co., Ltd.

Electrostatic chuck assembly and semiconductor manufacturing apparatus including the same

an electrostatic chuck assembly includes an electrostatic chuck including a circular-shaped electrostatic dielectric layer on which a wafer is mounted and an adsorption electrode in the electrostatic dielectric layer, and a control part configured to control the electrostatic chuck, wherein the adsorption electrode comprises a plurality of sub-adsorption electrodes separated from each other in an x direction and a y direction perpendicular to the x direction on a plane level from a central portion of the electrostatic dielectric layer.. .
Samsung Electronics Co., Ltd.

Compliant needle for direct transfer of semiconductor devices

an apparatus includes a needle and a needle actuator to move the needle to a position at which the needle presses an electrically-actuatable element into contact with a circuit trace. When the needle presses the electrically-actuatable element into contact with the circuit trace, a dampener, arranged with the needle and the needle actuator, dampens a force applied to the electrically-actuatable element..
Rohinni, Llc

Transferring manufacturing an integrated circuit device

in one embodiment a transferring apparatus comprises a rail connected to a frame, a travelling part including a wheel that travels along the rail and a loading part for loading an object, and a particle collection receptacle provided at a side of the rail and configured to collect particles generated due to friction between the wheel and the rail when the wheel travels along the rail. A method of manufacturing an integrated circuit device using the transferring apparatus includes moving the travelling part to the object, picking up the object with the loading part thereby loading the object on the loading part, using the travelling part to move the object to a chamber, and forming a semiconductor device using the object..
Samsung Electronics Co., Ltd.

Heating device and semiconductor manufacturing apparatus

a heating device is provided. The heating device includes a conveyance member that conveys a substrate between a heating position and a non-heating position, a support member that is provided on the conveyance member and that supports the substrate, a heater provided at the heating position and operable to heat a first surface of the substrate, and a heat reflecting plate attached to the conveyance member in facing relation to a second surface of the substrate opposite to the first surface..
Nissin Ion Equipment Co., Ltd.

Manufacturing semiconductor device

in a mold die, a tip-end surface of each push-up pin provided on the rear surface side of a lower die cavity block and a part of the rear surface of the lower die cavity block with which the tip-end surface of each push-up pin is contacted are inclined in such a manner that a distance to a top surface of the lower die cavity block becomes longer towards the pot side where mold resin is supplied. When the lower die cavity block is returned to the initial position, the lower die cavity block is lifted while being slightly moved towards the pot block side.
Renesas Electronics Corporation

Semiconductor structure

a semiconductor structure includes a substrate; a chip disposed over the substrate; and a molding disposed over the substrate and surrounding the chip at a molding temperature. The warpage of the substrate is convex or about zero at the molding temperature or 10° c.
Nanya Technology Corporation

Hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication

in one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices.
Zeon Corporation

Low resistance source-drain contacts using high temperature silicides

a semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate.
International Business Machines Corporation

Hard mask layer to reduce loss of isolation material during dummy gate removal

a method includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with active region(s) separated by isolation regions, the active region(s) including source/drain regions of epitaxial semiconductor material, dummy gate structures adjacent each source/drain region, the dummy gate structures including dummy gate electrodes with spacers adjacent opposite sidewalls thereof and gate caps thereover, and openings between the dummy gate structures. The method further includes filling the openings with a dielectric material, recessing the dielectric material, resulting in a filled and recessed structure, and forming a hard mask liner layer over the filled and recessed structure to protect against loss of the recessed dielectric material during subsequent removal of unwanted dummy gate electrodes.
Globalfoundries Inc.

Method and structure for enabling high aspect ratio sacrificial gates

sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate.
International Business Machines Corporation

Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures

methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures are provided. In some embodiments, methods may include contacting a substrate with a first vapor phase reactant comprising a transition metal precursor and contacting the substrate with a second vapor phase reactant comprising an alkyl-hydrazine precursor.
Asm Ip Holding B.v.

Manufacturing semiconductor device

the present disclosure is directed to a manufacturing method of a semiconductor device. The manufacturing method includes: providing an initial structure including a to-be-etched material layer and a mask structure located on the to-be-etched material layer, the mask structure including a hydrophilic first mask layer; patterning the mask structure to form a patterned mask structure; etching the to-be-etched material layer by using the patterned mask structure as a mask; performing hydrophobic processing on the first mask layer; and performing cleaning processing.
Semiconductor Manufacturing International (beijing) Corporation

Semiconductor device and manufacturing semiconductor device

provided is a highly reliable semiconductor device which includes a transistor including an oxide semiconductor. The semiconductor device includes an oxide semiconductor layer; a gate insulating layer provided over the oxide semiconductor layer; a gate electrode layer overlapping with the oxide semiconductor layer with the gate insulating layer provided therebetween; an insulating layer being in contact with part of an upper surface of the oxide semiconductor layer, covering a side surface of the gate insulating layer and a side surface and an upper surface of the gate electrode layer, and having a lower oxygen-transmitting property than the gate insulating layer; a sidewall insulating layer provided on the side surface of the gate electrode layer with the insulating layer provided therebetween; a source electrode layer and a drain electrode layer which are electrically connected to the oxide semiconductor layer..
Semiconductor Energy Laboratory Co., Ltd.

Interrupter device for interrupting a direct current

an interrupter device for interrupting a direct current between a direct current source and an electrical device, for example, between a photovoltaic generator and an inverter. The interrupter device has a mechanical switch which has a first fixed contact, a second fixed contact, and a contact bridge that can be moved between a first position and a second position.
Ellenberger & Poensgen Gmbh

Electromechanical power switch integrated circuits and devices and methods thereof

an electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer.
Inoso, Llc

Dispersion liquid for formation of semiconductor electrode layer, and semiconductor electrode layer

the present invention relates to a slurry for forming a semiconductor electrode layer to obtain a dye-sensitized solar cell containing a porous layer, which is not susceptible to cracking and is capable of providing a higher conversion efficiency. The slurry for forming a semiconductor electrode layer contains two types of metal-oxide semiconductor particles having different particle sizes.
Mikuni Shikiso Kabushiki Kaisha

Semiconductor memory device for storing multivalued data

data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line.
Toshiba Memory Corporation

Apparatus and methods including source gates

apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described..
Micron Technology, Inc.

Control circuit, semiconductor storage device, and controlling semiconductor storage device

a control circuit that controls a memory including a storage region and a redundant region, the control circuit includes a detector that detects a defective block in the memory, and a controller that switches, when the detector has detected the defective block, a data storage scheme of the first block detected as the defective block from a first storage scheme to a second storage scheme in which the number of bits of data to be stored in each of memory elements is smaller than the number of bits of data to be stored in each of the memory elements in the first storage scheme, and that stores a portion of data stored in the first block in the first storage scheme to be stored in the first block in the second storage scheme.. .
Fujitsu Limited

Semiconductor device and error correction method

a device with error correction is provided. The device includes a plurality of memory cells, and reference read write circuit, a plurality of sense amplifiers, and an error-correction code control block.
Micron Technology, Inc.

Electronic device

an electronic device including a semiconductor memory the semiconductor memory includes one or more resistive storage cells; at least one reference resistance block including at least two reference resistance transistors which are coupled in series; a data sensing block suitable for comparing resistance values of a resistive storage cell selected among the one or more resistive storage cells and the reference resistance block, and sensing data of the selected resistive storage cell; and a reference resistance adjustment block suitable for adjusting the resistance value of the reference resistance block by adjusting gate voltages of the reference resistance transistors.. .
Sk Hynix Inc.

Multi-port memory and semiconductor device

in a multi-port memory, a first pulse signal generator circuit generates a first pulse signal following input of a clock signal. A first latch circuit sets a first start signal to a first state in response to generation of the first pulse signal, and resets the first start signal to a second state in response to a first delayed signal obtained by delaying the first start signal by a delay circuit.
Renesas Electronics Corporation

Semiconductor memory

a semiconductor memory includes j×k first memory cells, j upper bit lines, (½)j sense amplifiers, j×k lower first bit lines, k first word lines, k pairs of plate lines, each pair having first and second plate lines, each being connected to odd-numbered and even-numbered first memory cells of one of the k columns, a pair of discharge signal lines having a first discharge signal line and a second discharge signal line respectively connecting two of the j upper lines in each sense amplifier to a prescribed potential, j×m second memory cells, j lower second bit lines, m second word lines, m third plate lines each connected to the j second memory cells of one of the m columns, and j shield lines each provided at positions respectively corresponding to the j upper bit lines, which are parallel to one another.. .
Lapis Semiconductor Co., Ltd.

Semiconductor memory devices and memory systems including the same

a semiconductor memory device and method of operation that is capable of reducing disturbance of adjacent word lines. A memory cell array includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines.
Samsung Electronics Co., Ltd.

Semiconductor device

a semiconductor device includes an input/output control circuit configured to generate a first driving signal and a second driving signal by shifting a latency signal in synchronization with a clock, and generating a strobe signal which toggles according to logic levels of the first driving signal and the second driving signal; and a data input/output circuit configured to latch input data in synchronization with the strobe signal, and outputting the latched input data as output data.. .
Sk Hynix Inc.

Clocked commands timing adjustments method in synchronous semiconductor integrated circuits

a method in a clocked integrated circuit receiving an input clock signal having a clock frequency and a command signal for accessing a memory element in the clocked integrated circuit. The method detects the input clock signal having a clock frequency above or below a frequency threshold.
Integrated Silicon Solution, Inc.

Clocked commands timing adjustments in synchronous semiconductor integrated circuits

a clock timing adjust circuit is incorporated in a clocked integrated circuit to detect an input clock frequency and to adjust the timing latency of an internal control signal for accessing a memory element in the clocked integrated circuit. The clock timing adjust circuit introduces an adjustable timing latency to an internal control signal derived from the command signal.
Integrated Silicon Solution, Inc.

Power control device and semiconductor memory device including the same

a power control device and a semiconductor memory device including the same may be provided. The power control device, may include an amplifier configured to amplify an input signal having a second power-supply voltage level to a first power-supply voltage level having a voltage level different from the second power-supply voltage level.
Sk Hynix Inc.

Microphone manufacturing the same

a microphone system may include a measuring device that includes a plurality of sound elements and a semiconductor chip connected to the sound elements and receives a vibration signal and a noise signal from the outside to cancel the vibration signal and changes a phase of the noise signal to output a reverse phase noise signal; and a driver that is connected to the semiconductor chip and is included in a front glass of a vehicle and vibrates in response to the reverse phase noise signal to cancel a noise signal inputted from the outside.. .
Kia Motors Corporation

Semiconductor device, manufacturing method thereof, display device, and electronic device

a method for transmitting image data to a display device at high speed is provided. Image data to be transmitted is input to a phase modulation portion, and is mixed with a high-frequency carrier wave.
Semiconductor Energy Laboratory Co., Ltd.

Sensor device

a sensor device includes: a first portion that is formed of an inorganic semiconductor material, includes a control module, and is reusable; a second portion that is formed of an organic material and separably coupled to the first portion; and a sensor that is disposed in at least one of the first and second portions.. .
Fujitsu Limited

Display device and fabricating a display device

the present disclosure relates to a display device and a method for fabricating a display device. The display device includes a display layer and a base layer under the display layer.
Beijing Boe Optoelectronics Technology Co., Ltd.

Vertical transistors with merged active area regions

a method for device layout with vertical transistors includes identifying active area regions in a layout of a semiconductor device with vertical transistors. Sets of adjacent active area regions having a same electrical potential are determined.
International Business Machines Corporation

Simulation methods and systems for predicting ser

a soft error rate (ser) associated with a design of a semiconductor circuit may be predicted based on implementing a simulation associated with the design. The simulation may include generating a simulation environment based on information indicating the design, performing a particle strike simulation based on the simulation environment to generate charge deposition information, and calculating a collected charge quantity from the charge deposition information.
Samsung Electronics Co., Ltd.

Enhanced memory reliability in stacked memory devices

the invention pertains to semiconductor memories, and more particularly to enhancing the reliability of stacked memory devices. Apparatuses and methods are described for implementing raid-style error correction to increase the reliability of the stacked memory devices..
Invensas Corporation

Integrated piezoelectric cantilever actuator and transistor for touch input and haptic feedback applications

user feedback may be generated and user input received through a single semiconductor component integrated into the electronic device. The single semiconductor component may include a piezoelectric cantilever actuator integrated with a transistor, such as a thin-film transistor, such that the actuator is electrically isolated from the transistor but mechanically attached to the transistor.
Sabic Global Technologies B.v.

Replacement physical layer (phy) for low-speed peripheral component interconnect (pci) express (pcie) systems

a replacement physical layer (phy) for low-speed peripheral component interconnect (pci) express (pcie) systems is disclosed. In one aspect, an analog phy of a conventional pcie system is replaced with a digital phy.
Qualcomm Incorporated

Reference voltage generation circuit, regulator, and semiconductor device

as one example of the invention disclosed herein, a reference voltage generation circuit has: a first reference voltage source generating a first reference voltage; a second reference voltage source generating a second reference voltage having a temperature response different from that of the first reference voltage; a first comparator comparing the first and second reference voltages to generate a first comparison signal; and a selector selectively outputting one of the first and second reference voltages as a reference voltage according to the first comparison signal.. .
Rohm Co., Ltd.

Composition for coating photoresist pattern and forming fine pattern using the same

disclosed are a composition for coating a photoresist pattern and a method for forming a fine pattern using the same. The composition for coating a photoresist pattern includes a polymer compound containing a hydroxyl group and an ammonium base, and a solvent.
Sk Hynix Inc.

Photoresist topcoat compositions and methods of processing photoresist compositions

wherein: r3 independently represents h, f or optionally fluorinated c1 to c4 alkyl; r4 represents linear, branched or cyclic c1 to c20 alkyl; r5 represents linear, branched or cyclic c1 to c20 fluoroalkyl; l2 represents a single bond or a multivalent linking group; and n is an integer of from 1 to 5; and a solvent. Coated substrates coated with the described topcoat compositions and methods of processing a photoresist composition are also provided.

Method for application of an overgrowth layer on a germ layer

a method for applying a masked overgrowth layer onto a seed layer for producing semiconductor components, characterized in that a mask for masking the overgrowth layer is imprinted onto the seed layer.. .
Ev Group E. Thallner Gmbh

Reflective mask blank, reflective mask, manufacturing reflective mask blank, and manufacturing semiconductor device

a reflective mask blank that comprises a multilayer reflective film 13, protective film 14, and phase-shift film 16 for shifting a phase of the euv light, which are formed in said order on a substrate 12. The protective film 14 is made of a material containing ruthenium as a main component, and an anti-diffusion layer 15 which is an oxidized layer containing ruthenium as a main component is formed on a surface of the protective film 14, or as a part of the protective film 14 on a side adjacent to the phase-shift layer 16, so as to inhibit counter diffusion in relation to the phase- shift film 16, thereby inhibiting the thermal diffusion between the protective film 14 and the material of the phase-shift film pattern.
Hoya Corporation

Display device and wiring structure

according to one embodiment, a display device includes a first substrate including a semiconductor layer, a first inorganic insulating film provided above the semiconductor layer and including a first opening, an organic insulating film provided above the semiconductor layer and including a second opening in a region which overlaps the first opening, a metal film stacked on the semiconductor layer and a pixel electrode provided in the first opening and the second opening to be in contact with the metal film and the semiconductor layer, and the metal film is spaced from a first side surface of the first opening and a second side surface of the second opening.. .
Japan Display Inc.

Liquid crystal display device

a first substrate (10) of a liquid crystal display device (100) includes a tft (2) that includes an oxide semiconductor layer (2a). A second substrate (20) includes a color filter layer (22) and a light-shielding layer (21).
Sharp Kabushiki Kaisha

Liquid crystal display device

a liquid crystal display device includes a first substrate; a thin film transistor on the first substrate; a first passivation layer on the thin film transistor; a first electrode on the first passivation layer; a second passivation layer on the first electrode; a second electrode of an oxide semiconductor on the second passivation layer; and an alignment layer on the second electrode. The second electrode includes first portions and second conductive portions alternating with the first portions.
Lg Display Co., Ltd.

Thin film transistor substrate having color filter

the present disclosure relates to a thin film transistor substrate having a color filter layer. The present disclosure provides a thin film transistor substrate comprising: a plurality of pixel areas disposed in a matrix manner on a substrate, each pixel area including an aperture area and a non-aperture area; a first color filter and a second color filter stacked at the non-aperture area on the substrate; an overcoat layer disposed on the first color filter and the second color filter; a semiconductor layer disposed at the non-aperture area on the overcoat layer; a gate insulating layer and a gate electrode stacked on a middle portion of the semiconductor layer; a third color filter at the non-aperture area on the semiconductor layer and the gate electrode; and a source electrode and a drain electrode disposed on the third color filter..
Lg Display Co., Ltd.

Display device

a display device is disclosed, which includes: a first substrate; a first transistor disposed on the first substrate, wherein the first transistor comprises a first semiconductor layer; a second transistor disposed on the first substrate, wherein the second transistor includes a second semiconductor layer; and a first insulating layer disposed under the first semiconductor layer; wherein a thickness of the first insulating layer is greater than or equal to 200 nm and less than or equal to 500 nm; and wherein one of the first semiconductor layer and the second semiconductor layer comprises a silicon semiconductor layer, and the other comprises an oxide semiconductor layer.. .
Innolux Corporation

Multi-chip module

one example of a multi-chip module includes a substrate, a semiconductor chip, and an optical transceiver. The substrate has a first side and a second side opposite the first side.
Hewlett Packard Enterprise Development Lp

Optical coupler having subwavelength grating

a semiconductor photonic device includes a substrate, facet(s), and optical coupler(s) associated with the facet(s). Each optical coupler can couple an electromagnetic field incident on the respective facet towards a buried waveguide as the electromagnetic field proceeds into the semiconductor photonic device.

Radiometric measuring device

a radiometric measuring device includes a scintillator, at least one semiconductor photodiode, wherein the at least one semiconductor photodiode is optically coupled to the scintillator, a signal evaluation unit which is electrically coupled to the at least one semiconductor photodiode and is designed to determine a measurement variable on the basis of a measurement signal produced by way of the at least one semiconductor photodiode, and an interface. The radiometric measuring device can be coupled to at least one receiver by way of the interface for the purpose of interchanging data.
Berthold Technologies Gmbh & Co. Kg

Wafer burn-in test circuit and semiconductor memory including the same

a wafer burn-in test circuit may be provided. The wafer burn-in test circuit may include a timing correction unit configured to generate a plurality of timing-compensated input signals by synchronizing a plurality of pulse signals generated according to a plurality of input signals with an input signal among the plurality of input signals.
Sk Hynix Inc.

Quick change small footprint testing system and use

a testing system for semiconductor chips having a removable device under test printed circuit board (dut pcb) that electrically connects with the electrical testing components of the system. A removable top plate is placed on top of the dut pcb and is locked in place by a plurality of locking posts that selectively connect to cam surfaces in the top plate that pull the top plate down sandwiching the dut pcb between the top plate and the electrical testing components of the system.

Short-wave infrared super-continuum lasers for natural gas leak detection, exploration, and other active remote sensing applications

a measurement system includes a light source having semiconductor sources configured to generate an input optical beam, a multiplexer configured form an intermediate optical beam from the input optical beam, fibers including a fused silica fiber configured to receive the intermediate optical beam and to form an output optical beam. The output optical beam comprises wavelengths between 700 and 2500 nanometers with a bandwidth of at least 10 nanometers.
Omni Medsci, Inc.

Light induced dielectrophoresis (lidep) device

a light induced dielectrophoresis (lidep) device is configured to perform a sorting process on a liquid including plural first micro-particles and plural second micro-particles. The lidep device includes a lidep chip and an opaque cartridge.
Techtron Technology Co., Ltd.

Semiconductor differential pressure sensor and manufacturing the same

a semiconductor differential pressure sensor element is such that as strain sensitive elements are disposed only inside a diaphragm, and strain relaxation grooves are provided along the diaphragm, it is difficult for thermal stress caused by expansion or contraction of a case to propagate to the strain sensitive elements, thus suppressing characteristic fluctuations resulting from a change in external temperature. Also, as a configuration is such that a sacrificial column is provided inside a depressed portion, and that the diaphragm is held by the sacrificial column in a diaphragm formation step which thins a second semiconductor substrate and a functional element formation step which repeatedly implements a cleaning step, breakage of the diaphragm can be prevented, thus achieving a significant improvement in yield..
Mitsubishi Electric Corporation

Optoelectronic arrangement

an optoelectronic arrangement includes an optoelectronic semiconductor chip, a wavelength-converting element and a detector component, wherein the optoelectronic arrangement is configured to emit light with a first peak wavelength and to emit light with a second peak wavelength, the first peak wavelength is in the visible spectral range and the second peak wavelength is in the non-visible spectral range or the first peak wavelength is in the non-visible spectral range and the second peak wavelength is in the visible spectral range, and the optoelectronic arrangement emits the light whose peak wavelength is in the non-visible spectral range into a target area, and the detector component is configured to detect light backscattered from the target area and the peak wavelength of which is in the non-visible spectral range.. .
Osram Opto Semiconductors Gmbh

Valve assemblies and fluid storage and dispensing packages comprising same

fluid dispensing assemblies are disclosed, for use in fluid supply packages in which such fluid dispensing assemblies as coupled to fluid supply vessels, for dispensing of fluids such as semiconductor manufacturing fluids. The fluid dispensing assemblies in specific implementations are configured to prevent application of excessive force to valve elements in the fluid dispensing assemblies, and/or for avoiding inadvertent or accidental open conditions of vessels that may result in leakage of toxic or otherwise hazardous or valuable gas.
Entegris, Inc.

Method of forming a pipe joint, pipe joint component, and pipe joint, fluid control device, fluid control unit and semiconductor fabrication apparatus including the pipe joint component

a method of forming a pipe joint includes: preparing a first pipe member, a second pipe member, a casing, and a pressing member to be arranged in the casing to press a second flange portion of the second pipe member against a first flange portion of the first pipe member, the casing having a first opening, a second opening, a third opening, a flange receiving space, and a receiving space in communication with the flange receiving space and adapted to receive the pressing member; inserting the first pipe member from the second opening toward the first opening until the first flange portion comes to rest within the flange receiving space; inserting the second pipe member into the second opening with the second flange portion ahead until the second flange portion comes into contact with the first flange portion.. .
Fujikin Incorporated

Method for maintaining contained volume of molten material from which material is depleted and replenished

a main crucible of molten semiconductor is replenished from a supply crucible maintained such that there are always two phases of solid and liquid semiconductor within the supply crucible. Heat added to melt the solid material results in the solid material changing phase to liquid, but will not result in any significant elevation in temperature of the liquid within the supply crucible.
1366 Technologies, Inc.

Hybrid photo-electrochemical and photo-voltaic cells

this disclosure provides systems, methods, and apparatus related to a hybrid photo-electrochemical and photo-voltaic cell. In one aspect, device includes a substrate comprising a semiconductor, a transparent conductor disposed on the second surface of the substrate, a photoanode disposed on the transparent conductor, an electrolyte in electrical communication with the photoanode, and an electrode in contact with the electrolyte.
Technion - Israel Institute Of Technology

Template and manufacturing semiconductor device

according to one embodiment, a template forming method is provided. In the template forming method, a template pattern is formed on a first surface of a substrate.
Toshiba Memory Corporation

Topcoat compositions and pattern-forming methods

wherein: r1 represents h, f, methyl or fluorinated methyl; r2 represents optionally substituted c1 to c8 alkylene or optionally substituted c1 to c8 fluoroalkylene, optionally comprising one or more heteroatom; r3 represents h, f, optionally substituted c1 to c10 alkyl or optionally substituted c5 to c15 aryl, optionally comprising one or more heteroatom; r4 represents optionally substituted c1 to c8 alkyl, optionally substituted c1 to c8 fluoroalkyl or optionally substituted c5 to c15 aryl, optionally comprising one or more heteroatom; x represents o, s or nr5, wherein r5 is chosen from hydrogen and optionally substituted c1 to c5 alkyl; and a is 0 or 1; and a solvent. Also provided are coated substrates and pattern-forming methods which make use of the topcoat compositions.

Topcoat compositions containing fluorinated thermal acid generators

provided are topcoat compositions that include: a matrix polymer; a surface active polymer; an ionic thermal acid generator comprising an anion and a cation, wherein the anion, the cation, or the anion and the cation are fluorinated; and a solvent. Also provided are coated substrates and pattern-forming methods which make use of the topcoat compositions.
Rohm And Haas Electronic Materials Llc

Precursor composition, photosensitive resin composition, producing precursor composition, cured film, producing cured film, and semiconductor device

provided are photosensitive resin compositions having a wide exposure latitude, a precursor composition for providing such a photosensitive resin composition, a method for producing a precursor composition, a cured film, a method for producing a cured film; and a semiconductor device. The precursor composition is a precursor composition containing at least one kind of heterocycle-containing polymer precursor, in which the heterocycle-containing polymer precursor is selected from a polyimide precursor and a polybenzoxazole precursor; and the dispersity which is a weight-average molecular weight/a number-average molecular weight of the heterocycle-containing polymer precursor is 2.5 or more..
Fujifilm Corporation

Novel dihydropyrrolo[2,3-f] indole-diketopyrrolopyrrole semiconducting materials, and methods and uses thereof

described herein are heterocyclic organic compounds. More specifically, described herein are compounds based on the combination of fused pyrrole structures with diketopyrrolopyrrole structures, methods for making these compounds, and uses thereof.
Corning Incorporated

Novel glasses

glasses are disclosed having a composition comprising the following oxides (in weight %): sio2 61 to 70%, al2o3 0 to 9%, na2o 10 to 13%, k2o 0 to 1%, mgo 2 to 6%, cao 6 to 16%, sro 0 to 1%, zro2 0 to 1%, tio2 2 to 15%, the glasses having a strain point greater than 570° c. The glasses have good dimensional stability at high temperatures, making them suitable for fire protection glazings and substrates which are processed at elevated temperatures, e.g.
Pilkington Group Limited

Temperature-compensated micro-electromechanical device, and temperature compensation in a micro-electromechanical device

a micro-electromechanical device includes a semiconductor substrate, in which a first microstructure and a second microstructure of reference are integrated. The first microstructure and the second microstructure are arranged in the substrate so as to undergo equal strains as a result of thermal expansions of the substrate.
Stmicroelectronics S.r.l.

Method and unpacking semiconductor wafer container

an automated method of unpacking a container containing semiconductor wafers from a sealed bag is provided. The method includes inflating the bag with a gas using an automated gas dispenser.
Taiwan Semiconductor Manufacturing Co., Ltd.

Molding apparatus including a compressible structure

the invention provides a molding apparatus comprising a first mold part operative to hold a semiconductor substrate, and a second mold part having a main surface facing the first mold part. The first and second mold parts are movable relative to each other between an open arrangement and a closed arrangement.
Asm Technology Singapore Pte Ltd

Wafer swapper

the present disclosure generally relates to semiconductor process equipment used to transfer semiconductor substrates between process chambers. More specifically, embodiments described herein are related to systems and methods used to transfer, or swap, semiconductor substrates between process chambers using a transport device that employs at least two blades for the concurrent transfer of substrates between processing chambers..
Applied Materials, Inc.

Method for dividing a composite into semiconductor chips, and semiconductor chip

the invention relates to a method for dividing a composite into a plurality of semiconductor chips along a dividing pattern. A composite, which comprises a substrate, a semiconductor layer sequence, and a functional layer, is provided.
Osram Opto Semiconductors Gmbh

Nanostructured photocatalysts and doped wide-bandgap semiconductors

photocatalysts for reduction of carbon dioxide and water are provided that can be tuned to produce certain reaction products, including hydrogen, alcohol, aldehyde, and/or hydrocarbon products. These photocatalysts can form artificial photosystems and can be incorporated into devices that reduce carbon dioxide and water for production of various fuels.
The Regents Of The University Of Colorado A Body Corporate

Systems and acoustic power scalable charge-redistribution ultrasonic system with on-chip aberration compensation for portable ultrasonic applications

the present disclosure is generally directed to an ultrasonic transducer interface system for use within portable 2-d ultrasonic imagers and includes an on-chip adaptive beamformer and charge-redistribution tx (cr-tx) to provide a drive strength of up to 500 pf/channel at 5 mhz (or 10 nf at 250 khz) while reducing the tx drive power by at least 30% compared to other ultrasonic transducer tx drivers. The ultrasonic transducer interface system can be implemented in a single chip via, for example, a complementary metal oxide semiconductor (cmos) process..
Khalifa University Of Science And Technology

Renesas Electronics Corporation

. .

. .

. .

Isolated driver

the invention describes an isolated driver (2) comprising a converter module (21) realized to provide voltage and current output to a load (3); a feedback arrangement (22) realized to monitor voltage and/or current during operation of the driver (2); and a converter controller (1) for providing converter control signals (ci, cf, vcon) to the converter module (21), and wherein the converter controller (1) comprises a single optocoupler (10) connected by input terminals to the feedback arrangement (22); and a switching circuit arrangement (11) connected to output terminals of the optocoupler (10), comprising a number of semiconductor switches (q20, q23, q30, . .
Philips Lighting Holding B.v.

Semiconductor device, broadcasting system, and electronic device

a semiconductor device that is suitable for high-speed operation is provided. The semiconductor device includes a decoder.
Semiconductor Energy Laboratory Co., Ltd.

Decoder, receiver, and electronic device

a decoder with reduced power consumption is provided. The decoder includes a first circuit and a second circuit for holding data.
Semiconductor Energy Laboratory Co., Ltd.

Solid state image sensor, semiconductor device, and electronic device

a solid state image sensor of the present disclosure includes: a first semiconductor substrate provided with at least a pixel array unit in which pixels that perform photoelectric conversion are arranged in a matrix form; and a second semiconductor substrate provided with at least a control circuit unit that drives the pixels. The first semiconductor substrate and the second semiconductor substrate are stacked, with first surfaces on which wiring layers are formed facing each other, the pixel array unit is composed of a plurality of divided array units, the control circuit unit is provided corresponding to each of the plurality of divided array units, and electrical connection is established in each of the divided array units, through an electrode located on each of the first surfaces of the first semiconductor substrate and the second semiconductor substrate, between the pixel array unit and the control circuit unit..
Sony Corporation

Solid state image sensor, semiconductor device, and electronic device

a solid state image sensor of the present disclosure includes: a first semiconductor substrate provided with at least a pixel array unit in which pixels that perform photoelectric conversion are arranged in a matrix form; and a second semiconductor substrate provided with at least a control circuit unit that drives the pixels. The first semiconductor substrate and the second semiconductor substrate are stacked, with first surfaces on which wiring layers are formed facing each other, the pixel array unit is composed of a plurality of divided array units, the control circuit unit is provided corresponding to each of the plurality of divided array units, and electrical connection is established in each of the divided array units, through an electrode located on each of the first surfaces of the first semiconductor substrate and the second semiconductor substrate, between the pixel array unit and the control circuit unit..
Sony Corporation

Method and system for a distributed receiver

a first semiconductor die may comprise an interface circuit and a demodulation circuit. The interface circuit may be operable to receive an externally generated signal and recover decisions of a symbol de-mapper carried in the externally generated signal.
Maxlinear, Inc.

Semiconductor device, wireless sensor, and electronic device

an object is to reduce power consumption of an analog-digital converter circuit. An analog potential obtained in a sensor or the like is held in a sample-and-hold circuit including a transistor with an extremely low off-state current.
Semiconductor Energy Laboratory Co., Ltd.

Techniques for handling high voltage circuitry in an integrated circuit

an integrated circuit formed using a semiconductor substrate may include a logic circuit and a switch circuit, whereby the logic circuit operates at a first power supply voltage and the switch circuit operates at a second power supply voltage that is greater than the first power supply voltage. The logic circuit may be formed within a first triple well structure within the semiconductor substrate and is supplied with a first bias voltage.
Altera Corporation

Electric power conversion apparatus

an electric power conversion apparatus includes at least one semiconductor module, a capacitor, a pair of positive and negative busbars and an insulator. The positive busbar includes a positive busbar base protruding from the capacitor in a y direction and at least one positive busbar terminal extending perpendicular to an x direction.
Denso Corporation

Phase shifter, semiconductor integrated circuit, and phased array system

a phase shifter includes a first variable amplifier circuit configured to receive and amplify a first signal having a first phase; and a second variable amplifier circuit configured to receive and amplify a second signal having a second phase different from the first phase. The phase shifter is configured to generate an output signal having a desired phase by phase combination of an output of the first variable amplifier circuit and an output of the second variable amplifier circuit, and the first variable amplifier circuit and the second variable amplifier circuit each includes a plurality of amplifier circuit units.
Fujitsu Limited

Semiconductor device

the semiconductor device includes a power amplifier that amplifies an output from a transmission circuit and a regulator that supplies power to the power amplifier. The regulator includes an operational amplifier comprising a loop gain control circuit and a loop gain control voltage generation circuit that supplies control voltage to the loop gain control circuit.

Phase noise reduction in voltage controlled oscillators

a voltage controlled oscillator (vco), a method of designing a voltage controlled oscillator, and a design structure comprising a semiconductor substrate including a voltage controlled oscillator are disclosed. In one embodiment, the vco comprises an lc tank circuit for generating an oscillator output at an oscillator frequency, and an oscillator core including cross-coupled semiconductor devices to provide feedback to the tank circuit.
International Business Machines Corporation

Dual active signal path power transmission and reception

an efficient method and device for power transmission is provided by using a transmitting system having two active signal path that are generated by a ground-less complimentary oscillator, which uses complementary configuration using complementary semiconductor devices/pair and amplified by single or cascaded ground-less complimentary amplifiers, which uses complementary configuration using complementary semiconductor devices/pair, directly connected to a symmetric antenna system. At the reception, signals are detected by a symmetric antenna and amplified by a similar single or cascaded ground-less complimentary amplifiers..

Semiconductor light emitting element

in a semiconductor light emitting element provided with an active layer 4, a pair of cladding layers 2, 7 between which the active layer 4 is interposed, and a phase modulation layer 6 optically coupled to the active layer 4, the phase modulation layer 6 includes a base layer 6a and a plurality of different refractive index regions 6b having different refractive indices from the base layer 6a. When an xyz orthogonal coordinate system having a thickness direction of the phase modulation layer 6 as a z-axis direction is set and a square lattice of a virtual lattice constant a is set in an xy plane, each of the different refractive index regions 6b is disposed so that a centroid position g thereof is shifted from a lattice point position in a virtual square lattice by a distance r, and the distance r is 0<r≤0.3a..
Hamamatsu Photonics K.k.

Laser oscillator

to provide a laser oscillator allowing the use of a plastic lens in a semiconductor laser module for a high-output laser oscillator while being unlikely to reduce the efficiency of coupling to an optical fiber even if a laser output changes. A laser oscillator comprises a semiconductor laser module with multiple semiconductor laser elements.
Fanuc Corporation

Printed circuit boards and solid state drives including the same

printed circuit hoards and solid state drives including the same are provided. The printed circuit boards may include a base portion including chip pads that are configured to be connected to semiconductor chips, an edge portion extending from one side of the base portion and including it pads, guide portions, and, protrusions.
Samsung Electronics Co., Ltd.

Cooling and heating system

a cooling and heating system includes a battery pack, a temperature sensing module, a semiconductor cooling chip, a current adjustment module, and a control module. The control module controls the current adjustment module to make a current flowed into the semiconductor cooling chip in a first direction, when a temperature of the battery pack is greater than a first reference temperature; and controls the current adjustment module to make the current flowed into the semiconductor cooling chip in a second direction opposite to the first direction, when the temperature of the battery pack is less than a second reference temperature.
Optimum Battery Co., Ltd.

Organic light emitting display device

an oled device includes a substrate, a semiconductor element on the substrate and including an active layer, a first gate electrode on the active layer, a second gate electrode on the first gate electrode, and source and drain electrodes, a wiring connection structure electrically connected to the semiconductor element and including an active layer pattern spaced from the active layer and corresponding to a first region, a second region, a third region between the first region and the second region, and a fourth region, a first gate electrode pattern overlapping the active layer pattern and expose active pattern layer at the first region and the second region, and a second gate electrode pattern contacting a portion of the first gate electrode pattern in the third region, and contacting the active layer pattern in the first region, and a sub-pixel structure on the semiconductor element and the wiring connection structure.. .
Samsung Display Co., Ltd.

Display device and a manufacturing the same

the display device includes a first base portion; a semiconductor layer disposed on the first base portion and including a source region, a drain region and a channel region; a first insulating layer disposed on the semiconductor layer; a gate line disposed on the first insulating layer extending in a first direction and overlapping the channel region; a second insulating layer disposed on the gate line; a first connection plug formed in the first and second insulating layer filling a first connection hole exposing the source region; a second connection plug formed in the first and second insulating layer filling a second connection hole exposing the drain region; a first and second conductive pattern disposed on the second insulating layer; a pixel electrode disposed on the second insulating layer and electrically connected to the first conductive pattern; and a data line disposed on the second insulating layer to extend in a second direction.. .
Samsung Display Co., Ltd.

Peeling method and manufacturing semiconductor device

there is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high yield.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device having memory cell structure and manufacturing the same

a semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (tmo) layer formed on the bottom electrode, a tmo sidewall oxides formed at sidewalls of the tmo layer, a top electrode formed on the tmo layer, and spacers formed on the bottom electrode.
United Microelectronics Corp.

Method of forming a bottom electrode of a magnetoresistive random access memory cell

a method of fabricating a semiconductor device is disclosed. The method includes forming an opening with a tapered profile in a first material layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor structure and forming the same

the present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a memory region.
Taiwan Semiconductor Manufacturing Company Ltd.

Method for producing optical semiconductor device and optical semiconductor device

a method is provided for making optical semiconductor devices collectively. Led chips are arranged on a material substrate, and the substrate is sandwiched by a common mold and a first cooperating mold formed with a cavity.
Rohm Co., Ltd.

Light emitting devices having closely-spaced broad-spectrum and narrow-spectrum luminescent materials and related methods

a semiconductor light emitting device includes an led and an associated recipient luminophoric medium that includes respective first through fourth luminescent materials that down-convert respective first through fourth portions of the radiation emitted by the led to radiation having respective first through fourth peak wavelengths. The first peak wavelength is in the green color range and the second through fourth peak wavelengths are in the red color range.
Cree, Inc.

Light emitting device, light emitting device package including the device, and lighting apparatus including the package

a light emitting device of an embodiment includes a substrate, a light emitting structure disposed under the substrate, the light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, first and second electrodes respectively connected to the first and second conductive semiconductor layers, a metal reflecting layer disposed under the light emitting structure, and a first insulating layers disposed between the first electrode and the light emitting structure, between the first electrode and the second electrode, and between the first electrode and the metal reflecting layer, wherein the metal reflecting layer includes a first segment overlapped with the second electrode in a thickness direction of the light emitting structure and a second segment disposed with extending from the first segment.. .
Lg Innotek Co., Ltd.

Optoelectronic semiconductor chip

an optoelectronic semiconductor chip is disclosed. In an embodiment the chip includes at least one n-doped semiconductor layer, at least one p-doped semiconductor layer and an active layer arranged between the at least one n-doped semiconductor layer and the at least one p-doped semiconductor layer, wherein the p-doped semiconductor layer is electrically contacted by a p-type connection contact, wherein a first trench extending at least partially into the p-doped semiconductor layer is arranged below the p-type connection contact, wherein an electrically insulating first blocking element arranged at least partially below the p-type connection contact and at least partially within the trench is arranged at least between the n-doped semiconductor layer and the p-type connection contact, and wherein the electrically insulating first blocking element is configured to prevent a direct current flow between the p-type connection contact and the p-doped and n-doped semiconductor layers and the active layer..
Osram Opto Semiconductors Gmbh

Flip-chip light emitting diode and fabrication method

a flip-chip light-emitting diode structure includes a substrate; an epitaxial layer over the substrate, which includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer; a first electrode structure over the first semiconductor layer; a second electrode structure over the second semiconductor layer; wherein, the first electrode structure includes a first electrode body and a first electrode ring; the second electrode structure includes a second electrode body and a second electrode ring; the thickness of the first electrode ring is greater than or equal to that of the first electrode body and the thickness of the second electrode ring is greater than or equal to that of the second electrode body. As barrier structures, the first and the second electrode rings are used for avoiding short circuit during packaging and usage of the light-emitting diode due to overflow of solid crystal conductive materials, thus improving reliability..
Xiamen Sanan Optoelectronics Technology Co., Ltd.

Light emitting device

the light emitting device includes a substrate, and an n-type conductive type semiconductor layer, a light emitting layer and a p-type conductive type semiconductor layer laminated in series on a surface of the substrate. The light emitting layer, the p-type conductive type semiconductor layer, and a portion of the n-type conductive type semiconductor layer excluding the vicinity of the peripheral portion compose a semiconductor laminate structure portion.
Rohm Co., Ltd.

Light-emitting devices

a light-emitting device comprises a semiconductor layer sequence comprising a first semiconductor layer having a first electrical conductivity, a second semiconductor layer having a second electrical conductivity, and an active layer interposed between the first semiconductor layer and the second semiconductor layer; a plurality of beveled trenches formed in the semiconductor layer sequence; a plurality of protruding structures respectively formed in the plurality of beveled trenches; a dielectric layer formed on the second semiconductor layer and an inner sidewall of the plurality of beveled trenches; a reflecting layer interposed between the semiconductor layer sequence and the dielectric layer; and a metal layer formed along the inner sidewall of the plurality of beveled trenches, wherein the dielectric layer, the reflecting layer and the metal layer are overlapping, the plurality of protruding structures and the reflecting layer are not overlapping.. .
Epistar Corporation

Patterned layer design for group iii nitride layer growth

a device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group iii nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings.
Sensor Electronic Technology, Inc.

Semiconductor material doping

a solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier.
Sensor Electronic Technology, Inc.

Photo-detection apparatus and photo-detection system

an apparatus wherein, in plane view, a first semiconductor region of a first conductivity type overlaps at least a portion of a third semiconductor region, a second semiconductor region overlaps at least a portion of a fourth semiconductor region of a second conductivity type, a height of a potential of the third semiconductor region with respect to an electric charge of the first conductivity type is lower than that of the fourth semiconductor region, and a difference between a height of a potential of the first semiconductor region and that of the third semiconductor region is larger than a difference between a height of a potential of the second semiconductor region and that of the fourth semiconductor region.. .
Canon Kabushiki Kaisha

Solar cell

a solar cell comprising a semiconductor substrate, an intrinsic semiconductor layer, a second conductive type semiconductor layer, a transparent conductive layer, a metal electrode, a light reflective unit, and a transparent packaging layer. The semiconductor substrate has an illuminated surface, which includes an effective absorption region and an ineffective absorption region.
Neo Solar Power Corp.

Method for manufacturing an edge termination for a silicon carbide power semiconductor device

a method for manufacturing an edge termination structure for a silicon carbide power semiconductor device having a central region and an edge region is provided. The following manufacturing steps are performed: a) providing an n-doped silicon carbide substrate, b) epitaxially growing a silicon carbide n-doped drift layer on the substrate, which has a lower doping concentration than the substrate, c) creating at least one p-doped termination layer by implanting a second ion up to a maximum termination layer depth and annealing on the first main side, d) forming a doping reduction layer having a depth range, which doping reduction layer comprises at least one doping reduction region, wherein a depth of a doping concentration minimum of the doping reduction layer is greater than the maximum termination layer depth, wherein for the creation of each doping reduction region: implanting a first ion with an implantation energy in the drift layer at least in the edge region, wherein the first ion and the at least one implantation energy are chosen such that the doping reduction layer depth range is less than 10 μm, e) annealing the doping reduction layer, wherein step d) and e) are performed such that the doping concentration of the drift layer is reduced in the doping reduction layer..
Abb Schweiz Ag

Perfectly symmetric gate-all-around fet on suspended nanowire

a semiconductor device including a plurality of suspended nanowires and a gate structure that is present on a channel region portion of the plurality of suspended nanowires. The gate structure includes a uniform length extending from an upper surface of the gate structure to the base of the gate structure.
International Business Machines Corporation

Semiconductor device

high field-effect mobility is provided for a transistor including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided.
Semiconductor Energy Laboratory Co., Ltd.

Preparation methods for semiconductor layer and tft, tft, array substrate

embodiments of the present disclosure provide preparation methods for a semiconductor layer and a tft, a tft and an array substrate. The preparation method for a semiconductor layer: includes forming a silicon dioxide film on a substrate; forming sidewalls at two ends of the semiconductor layer to be formed by patterning process; performing amination treatment on the sidewalls so that an aminosiloxane monolayer self-assembly is formed on the surface of the sidewalls; carboxylating a carbon nanotube solution and making the carboxylated carbon nanotube solution on the surface of the substrate with the sidewalls formed to form a carbon nanotube film; removing portions of the carbon nanotube film other than the portion between the sidewalls to form a semiconductor layer..
Boe Technology Group Co., Ltd.

Thin film transistor and manufacture method thereof

the disclosure provides a thin film transistor (tft) and a manufacture method thereof. The tft includes: a substrate; a gate electrode, formed on the substrate; a gate insulating layer, formed on the gate electrode; a semiconductor layer, formed on the gate insulating layer and corresponding to the gate electrode; a pixel electrode, disposed on the same layer with the semiconductor layer; an ohmic contact layer, formed on the same layer with the semiconductor layer and formed on the same layer with the pixel electrode; a source electrode and a drain electrode, disposed on the ohmic contact layer.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Semiconductor devices and methods of fabricating the same

a semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region.
Samsung Electronics Co., Ltd.

Semiconductor device having first and second epitaxial materials

a semiconductor device includes a first gate stack over a substrate. The semiconductor device further includes a first epitaxial (epi) material in the substrate on a first side of the first gate stack.
Taiwan Semiconductor Manufacturing Company, Ltd.

Vertical transistors stressed from various directions

a vertical transistor includes a semiconductor substrate, and fin(s) over the semiconductor substrate (n-type fin(s) and/or p-type fin(s)), the fin(s) acting as vertical transistor channels for vertical transistors. Each of the fin(s) is lattice mismatched at one or more interface(s), being stressed from below, from above, from fin sidewalls or combination(s) thereof.
Globalfoundries Inc.

Structure of semiconductor device with source/drain structures

structures of a semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, and a first recess and a second recess in the substrate and at opposite sides of the gate structure.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device and manufacturing same

a semiconductor device includes an n+ type silicon carbide substrate, an n− type layer, an n type layer, a plurality of trenches, a p type region, an n+ type region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and a channel. The plurality of trenches is disposed in a planar matrix shape.
Hyundai Motor Company

Split fin field effect transistor enabling back bias on fin type field effect transistors

a method of forming the semiconductor device that may include forming a trench in a substrate, and forming a metal nitride in the trench. The method may further include forming a split fin structure from the substrate.
International Business Machines Corporation

Self-aligned gate cut with polysilicon liner oxidation

a method of forming a semiconductor device that includes forming a gate structure over a plurality of fin structures, wherein the gate structure provides a first fill pinch off between the fin structures separated by a first pitch; and forming a material stack of a silicon containing layer, and a dielectric layer over the plurality of fin structures, wherein the dielectric provides a second fill pinch off between fin structures separated by a second pitch. The silicon containing layer is converted into an oxide material layer.
International Business Machines Corporation

Forming strained channel with germanium condensation

a method for forming a semiconductor device includes forming a strained fin on a substrate, a sacrificial gate on a channel region of the fin, a first spacer adjacent to a sidewall of the fin, and a second spacer adjacent to the first spacer. A source/drain region is grown on an exposed portion of the fin.
International Business Machines Corporation

Compound semiconductor device and manufacturing compound semiconductor device

a compound semiconductor device disclosed herein includes: a gan carrier transit layer formed on a substrate; a barrier layer formed on the carrier transit layer; a first recess and a second recess formed in the barrier layer; a first inaln layer and a second inaln layer formed in the first recess and the second recess respectively, a composition ratio of in in the inaln layers being equal to or more than 17% and equal to or less than 18%; a source electrode formed on the first inaln layer; a drain electrode formed on the second inaln layer; and a gate electrode formed on the barrier layer.. .
Fujitsu Limited

Method for manufacturing a hemt transistor and hemt transistor with improved electron mobility

a method for manufacturing a hemt transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of groups iii-v of the periodic table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of groups iii-v of the periodic table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.. .
Stmicroelectronics S.r.l.

Semiconductor device and producing the same

a method of producing a semiconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region.
Fuji Electric Co., Ltd.

Semiconductor device

in an active region, a mos gate of an igbt is provided on a front surface side of a semiconductor substrate. In an edge termination region, a zener diode is provided on the front surface of the semiconductor substrate, via a field oxide film.
Fuji Electric Co., Ltd.

Semiconductor-on-insulator lateral heterojunction bipolar transistor having epitaxially grown intrinsic base and deposited extrinsic base

after forming a trench extending through an insulator layer and an underlying top semiconductor portion that is comprised of a first semiconductor material and a dopant of a first conductivity type to define an emitter and a collector on opposite sides of the trench in the top semiconductor portion, an intrinsic base comprising a second semiconductor material having a bandgap less than a bandgap of the first semiconductor material and a dopant of a second conductivity type opposite the first conductivity type is formed in a lower portion the trench by selective epitaxial growth. The intrinsic base protrudes above the top semiconductor portion and is laterally surrounded by entire top semiconductor portion and a portion of the insulator layer.
International Business Machines Corporation

Bipolar transistor and manufacturing the same

a bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region.
Stmicroelectronics Sa

Semiconductor device and manufacturing method thereof

a minute transistor is provided. A transistor with low parasitic capacitance is provided.
Semiconductor Energy Laboratory Co., Ltd.

Thin film transistor, fabrication method thereof, and array substrate

a thin film transistor, a fabrication method thereof, and an array substrate are provided. The fabrication method includes: forming a semiconductor layer and a photoresist layer on a substrate, dividing the substrate, the semiconductor layer and the photoresist layer into a first, second and third regions; performing ladder exposure on the photoresist layer, then developing, completely removing the photoresist layer of the first region and partly removing the photoresist layer of the second region; removing the semiconductor layer of the first region, and forming a pattern including an active region; thinning the photoresist layer: completely removing the photoresist layer of the second region, and partly removing a part of the photoresist layer of the third region; allowing the active region of the second region to be metalized and forming an ohmic contact layer; removing the photoresist layer of the third region; and forming a pattern including a source and a drain..
Boe Technology Group Co., Ltd.

Self-aligned channel-only semiconductor-on-insulator field effect transistor

in one example, a field effect transistor includes a fin. The fin includes a conducting channel formed from semiconductor-on-insulator and source/drain regions formed on opposite ends of the conducting channel, wherein the source/drain regions are formed from a material other than semiconductor-on-insulator.
International Business Machines Corporation

Finfet ldmos devices with improved reliability

a finfet ldmos semiconductor device includes a first well disposed adjacent to a second well on a substrate and a third well disposed on the substrate, wherein the second well is disposed between the first well and the third well. Additionally, the finfet ldmos semiconductor device includes a source disposed on the first well, a fin at least partially disposed on the first well and adjacent to the source, a drain disposed on the third well, a shallow trench isolation (sti) disposed at least partially in the third well, and a sti protection structure disposed on the substrate between the second well and the third well and along a side of the sti that is closest to the source, wherein the sti protection structure is configured to discourage a drain to source current from flowing along the side of the sti that is closest to the source..
Avago Technologies General Ip (singapore) Pte. Ltd

Vertical transistor with variable gate length

a method includes forming a plurality of fins on a substrate. The method further includes forming a plurality of deep trenches in the substrate and interposed between each fin of the plurality of fins.
International Business Machines Corporation

Hemts with an alxga1-xn barrier layer grown by plasma enhanced atomic layer deposition

in a method of manufacturing a high-electron mobility transistor (hemt), a first group iii-v semiconductor layer is formed on a substrate. The first group iii-v semiconductor layer is patterned to form a fin and a recessed surface.
National Taiwan University

Integrated strained stacked nanosheet fet

transistors include stress liners, with one or more semiconductor structures between the stress liners. The stress liners provide a stress on the one or more semiconductor structures.
International Business Machines Corporation

Trench silicide contacts with high selectivity process

a method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible.
Globalfoundries Inc.

Iii-v semiconductor layers, iii-v semiconductor devices and methods of manufacturing thereof

in a method of forming a group iii-v semiconductor layer on a si substrate, a first source gas containing a group v element is supplied to a surface of the si substrate while heating the substrate at a first temperature, thereby terminating the si surface with the group v element. Then, a second source gas containing a group iii element is supplied to the surface while heating the substrate at a second temperature, thereby forming a nucleation layer directly on the surface of the si substrate.
Taiwan Semiconductor Manufacturing Company

Semiconductor structures and fabrication methods thereof

a method for fabricating a semiconductor structure includes providing a base structure including an nmos region, forming an interlayer dielectric layer on the base structure with a plurality of openings formed in the nmos region through the interlayer dielectric layer, forming a high-k dielectric layer on a bottom and sidewall surfaces of each opening of the nmos region, forming an n-type work function layer on the high-k dielectric layer in each opening of the nmos region, forming a diffusion barrier layer on the n-type work function layer, performing a hydrogenation process on the diffusion barrier layer, and forming a metal gate electrode on the diffusion barrier layer to fill up each opening in the nmos region. The disclosed method and semiconductor structure improve the ability of the barrier layer to protect the n-type work function layer, and thus improve the electrical performance of the semiconductor device..
Semiconductor Manufacturing International (beijing) Corporation

Method of manufacturing semiconductor memory device

a method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure.
United Microelectronics Corporation

Semiconductor device and forming the same

a semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication

a method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening.. .
Taiwan Semiconductor Manufacturing Company, Ltd.

Handle for semiconductor-on-diamond wafers and manufacture

methods for mounting and dismounting thin and/or bowed semiconductor-on-diamond wafers to a carrier are disclosed that flatten said wafers and provide mechanical support to enable efficient semiconductor device processing on said semiconductor-on-diamond wafers.. .
Rfhic Corporation

Semiconductor device

a semiconductor device is provided, including: a first conductivity-type drift region formed in the semiconductor substrate; a second conductivity-type base region formed between the upper surface of the semiconductor substrate and the drift region; a first conductivity-type accumulation region formed between the drift region and the base region and having a higher doping concentration than the drift region; and a dummy trench portion formed to penetrate the base region from the upper surface of the semiconductor substrate, wherein at least one of the accumulation region and the dummy trench portion has a suppressing structure that suppresses formation of a second conductivity-type inversion layer in a first conductivity-type region adjacent to the dummy trench portion.. .
Fuji Electric Co., Ltd.

Semiconductor device

a semiconductor device is provided, including: a semiconductor substrate; a transistor section provided in the semiconductor substrate; and a diode section provided in the semiconductor substrate being adjacent to the transistor section, wherein the diode section includes: a second conductivity-type anode region; a first conductivity-type drift region; a first conductivity-type cathode region; a plurality of dummy trench portions arrayed along a predetermined array direction; a contact portion provided along an extending direction of the plurality of dummy trench portions that is different from the array direction; and a lower-surface side semiconductor region provided directly below a portion of the contact portion at an outer end in the extending direction.. .
Fuji Electric Co., Ltd.

Compressive strain semiconductor substrates

a method for forming a compressively strained semiconductor substrate includes forming a lattice adjustment layer on a semiconductor substrate by forming compound clusters within an epitaxially grown semiconductor matrix. The lattice adjustment layer includes a different lattice constant than the semiconductor substrate.
International Business Machines Corporation

Semiconductors with increased carrier concentration

within examples, a semiconductor device includes a first structure that includes a first doped semiconductor material of a first doping type. The semiconductor device further includes a metal in contact with the first structure, and a second structure that includes a second doped semiconductor material of the first doping type in contact with the first structure.
Katholieke Universiteit Leuven, Ku Leuven R&d

Process for fabricating a field effect transistor having a coating gate

a process for fabricating a gate-wrap-around field-effect transistor is provided, including: providing a superposition of first to third nanowires, each made of a semiconductor, the second nanowire being subjected to a strain along its longitudinal axis, a median portion of the first to third nanowires being covered by a sacrificial gate; forming voids by removing a portion of the first and third nanowires that is intermediate between their ends and their median portion, while preserving the superposition of the first to third nanowires level with the ends and under the sacrificial gate; forming an electrical insulator in the voids around the second nanowire; removing the sacrificial gate and the median portion of the first and third nanowires; and forming a gate electrode wrapped around the median portion of the second nanowire.. .
Commissariat A L'energie Atomique Et Aux Energies Alternatives

Notched fin structures and methods of manufacture

the present disclosure relates to semiconductor structures and, more particularly, to notched fin structures and methods of manufacture. The structure includes: a fin structure composed of a substrate material and a stack of multiple epitaxially grown materials on the substrate material; a notch formed in a first epitaxially grown material of the stack of multiple epitaxially grown materials of the fin structure; an insulator material within the notch of the fin structure; and an insulator layer surrounding the fin structure and above a surface of the notch..
Globalfoundries Inc.

Method for local isolation between transistors produced on an soi substrate, in particular an fdsoi substrate, and corresponding integrated circuit

an integrated circuit may include an soi substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first mos transistors and also first dummy gate regions.
Stmicroelectronics (crolles 2) Sas

Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device

a method for manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate having a first main surface and a second main surface located on a side opposite to the first main surface, forming an epitaxial layer on the first main surface, the epitaxial layer having a first conductivity type and having a third main surface located on a side opposite to a side on which the silicon carbide substrate is located, forming a trench, which includes side walls intersecting with the third main surface and a bottom portion connected to the side walls, in the epitaxial layer, widening an opening of the trench, and forming an embedded region, which has a second conductivity type different from the first conductivity type, in the trench. The epitaxial layer adjacent to the embedded region and the embedded region constitute a superjunction structure..
Sumitomo Electric Industries, Ltd.

Structures to avoid floating resurf layer in high voltage lateral devices

a semiconductor device contains an ldnmos transistor with a lateral n-type drain drift region and a p-type resurf region over the drain drift region. The resurf region extends to a top surface of a substrate of the semiconductor device.
Texas Instruments Incorporated

Method of fabricating semiconductor devices

provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole..
Samsung Electronics Co., Ltd.

Organic light-emitting display device

an organic light-emitting diode (oled) display device includes a substrate, a first gate electrode on the substrate, a second gate electrode on the first gate electrode and at least partially overlapping the first gate electrode, a semiconductor pattern between the first gate electrode and the second gate electrode and at least partially overlapping the first and second gate electrodes, a connecting electrode on the second gate electrode and electrically connected to the semiconductor pattern, and a pixel electrode on the connecting electrode and electrically connected to the connecting electrode.. .
Samsung Display Co., Ltd.

Wafer level light-emitting diode array

a light emitting diode array is provide to include: a substrate; light emitting diodes positioned over the substrate, each including a first semiconductor layer, an active layer, and a second semiconductor layer, wherein each light emitting diode is disposed to form a first via hole structure exposing a portion of the corresponding first semiconductor layer; lower electrodes disposed over the second semiconductor layer; a first interlayer insulating layer disposed over the lower electrodes and configured to expose the portion of the first semiconductor layer of corresponding light emitting diodes; upper electrodes electrically connected to the first semiconductor layer through the first via hole structure, wherein the first via hole structure is disposed in parallel with one side of the corresponding second semiconductor layer and the first interlayer insulating layer is disposed to form a second via hole structure exposing a portion of the lower electrodes.. .
Seoul Viosys Co., Ltd.

Methods of making semiconductor x-ray detector

disclosed herein is a method of making an apparatus suitable for detecting x-ray, the method comprising: attaching a chip comprising an x-ray absorption layer to a surface of a substrate, wherein the surface is electrically conductive; thinning the chip; forming an electrical contact in the chip; bonding an electronic layer to the chip such that the electrical contact of the chip is electrically connected to an electrical contact of the electronic layer.. .
Shenzhen Xpectvision Technology Co., Ltd.

Infrared detector, infrared detection sensor having an infrared detector and manufacturing the same

an infrared detector includes a substrate, a light blocking layer on the substrate, a lower electrode on the light blocking layer, the lower electrode electrically connected to the light blocking layer, a lower insulating layer on the light blocking layer, a first semiconductor layer on the lower insulating layer, a first source electrode and a first drain electrode on the first semiconductor layer, an upper insulating layer on the first semiconductor layer, and a first gate electrode on the upper insulating layer, the first gate electrode electrically connected to the lower electrode, where the first semiconductor layer includes a zinc and a nitrogen, and the first semiconductor layer is configured to generate electric charges by reacting with an infrared ray.. .
Samsung Display Co., Ltd.

Cmos image sensor

a method for manufacturing a semiconductor device includes providing a substrate structure including a substrate having a front side and a back side and a pixel region having a plurality of pixels in the front side, each pixel including a sensor element, forming a metal reflective layer in the front side of the substrate and on the pixel region, thinning the back side of the substrate, doping the thinned back side of the substrate with a dopant, and laser annealing the doped back side of the substrate. The sensor element is configured to receive incident light to the thinned back side of the semiconductor substrate.
Semiconductor Manufacturing International (beijing) Corporation

Optoelectronic semiconductor component and producing an optoelectronic semiconductor component

the invention relates to an optoelectronic semiconductor component (100) comprising the following —an optoelectronic semiconductor chip (2), the lateral surfaces (2c) and lower face (2b) of which are at least partly covered by a molded body (3) that is electrically conductive and is designed to electrically contact the optoelectronic semiconductor chip (2), —at least one via (6) which comprises an electrically conductive material and is laterally spaced from the semiconductor chip (2), said via (6) completely passing through the molded body (3), wherein the via (6) extends from an upper face (3a) of the molded body (3) to a lower face (3b) of the molded body (3), —at least one insulating element (9) which is arranged within the molded body (3) between the via (6) and the semiconductor chip (2) and extends from the upper face (3a) of the molded body (3) to the lower face (3b) of the molded body (3), and —an electrically conductive connection (7) which is connected to the semiconductor chip (2) and the via (6) in an electrically conductive manner.. .
Osram Opto Semiconductors Gmbh

Optical sensor device and manufacturing the optical sensor device

an optical sensor device includes a semiconductor substrate comprising a conversion region to convert an electromagnetic signal into photo-generated charge carriers, a read-out node configured to read-out a first portion of the photo-generated charge carriers, a control electrode, which is formed in a trench extending into the semiconductor substrate, and a doping region in the semiconductor substrate, wherein the doping region is adjacent to the trench, and wherein the doping region has a doping type different from the read out node, wherein the doping region has a doping concentration so that the doping region remains depleted during operation.. .
Pmdtechnologies Ag

Method for manufacturing semiconductor device

an object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer..
Semiconductor Energy Laboratory Co., Ltd.

Integrated circuit including buried cavity and manufacturing method

in accordance with an embodiment of an integrated circuit, a cavity is buried in a semiconductor body below a first surface of the semiconductor body. An active area portion of the semiconductor body is arranged between the first surface and the cavity.
Infineon Technologies Ag

Semiconductor device and manufacturing method thereof

a semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction, a plurality of channel layers disposed under the bit lines, the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines, and a contact plug extending, from the channel layer, toward one of the bit lines overlapped with the channel layer.. .
Sk Hynix Inc.

Semiconductor device and manufacturing method thereof

a semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction, a plurality of channel layers disposed under the bit lines, the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines, and a contact plug extending, from the channel layer, toward one of the bit lines overlapped with the channel layer.. .
Sk Hynix Inc.

Semiconductor device including dielectric layer

a semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.. .

Three-dimensional memory device with leakage reducing support pillar structures and making thereof

memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings.
Sandisk Technologies Llc

Semiconductor devices and methods of fabrication

some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source.

Flash memory device

an integrated circuit product includes a silicon-on-insulator (soi) substrate and a flash memory device positioned in a first area of the soi substrate. The soi substrate includes a semiconductor bulk substrate, a buried insulating layer positioned above the semiconductor bulk substrate, and a semiconductor layer positioned above the buried insulating layer, and the flash memory device includes a flash transistor device and a read transistor device.
Globalfoundries Inc.

Flash memory device and manufacture thereof

a flash memory device and its manufacturing method, which is related to semiconductor techniques. The flash memory device comprises: a substrate; and a memory unit on the substrate, comprising: a channel structure on the substrate, wherein the channel structure comprise, in an order from inner to outer of the channel structure, a channel layer, an insulation layer wrapped around the channel layer, and a charge capture layer wrapped around the insulation layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure, wherein there exist cavities between neighboring gate structures; a support structure supporting the gate structures; and a plurality of gate contact components each contacting a gate structure.
Semiconductor Manufacturing International (shanghai) Corporation

Convex shaped thin-film transistor device having elongated channel over insulating layer

the present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines and in a groove in the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed..
Monterey Research, Llc

Semiconductor devices and methods for manufacturing the same

a semiconductor device includes a substrate including first and second active patterns thereon, a first gate electrode intersecting the first and second active patterns, first and second source/drain regions on the first and second active patterns, respectively, at one side of the first gate electrode, and an active contact on the first source/drain region so as to be electrically connected to the first source/drain region. The active contact includes a first sub-contact and a second sub-contact.
Samsung Electronics Co., Ltd.

Semiconductor device

a semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.. .
Samsung Electronics Co., Ltd.

Modulating transistor performance

a method of forming an improved field-effect transistor device is provided. The method includes forming a tensile stressor near a first semiconductor fin.
International Business Machines Corporation

Spacer formation preventing gate bending

a method of forming a semiconductor structure includes depositing a spacer material over a top surface of a substrate and two or more spaced-apart gates formed on the top surface of the substrate. The method also includes depositing a sacrificial liner over the spacer material and etching the sacrificial liner and the spacer material to expose portions of the top surface of the substrate between the two or more spaced-apart gates.
International Business Machines Corporation

Semiconductor device and forming the semiconductor device

a semiconductor device includes a first vertical field effect transistor (vfet) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second vfet formed on the substrate and connected in parallel with the first vfet, and including a second fin and a second gate formed on the second fin, a third vfet formed on the substrate and including a third fin, the first and second gates being formed on the third fin, and a fourth vfet formed on the substrate and connected in series with the third vfet, and including a fourth fin, the first and second gates being formed on the fourth fin.. .
International Business Machines Corporation

Preserving channel strain in fin cuts

a method of forming a semiconductor structure includes forming a fin cut mask over a region in a fin field-effect transistor (finfet) structure. The finfet structure includes one or more fins and one or more gates and source/drain regions formed over the one or more fins in active regions of the finfet structure.
International Business Machines Corporation

Finfet device with low resistance fins

a method of forming a finfet device includes ion implanting a diffusion-inhibiting species such as carbon into source and drain regions of a semiconductor fin prior to a dopant activating anneal. The implanted carbon, which can be incorporated into the fin in conjunction with a replacement metal gate process after defining a sacrificial gate but prior to forming sidewall spacers on the gate, forms a barrier that impedes dopant diffusion across the barrier, which enables abrupt junctions and higher overall dopant concentrations within the semiconductor fin..
Globalfoundries, Inc.

Semiconductor structure

a semiconductor structure includes a pair of gate structures and an isolation structure. Each of the gate structures includes a work function metal, a gate, and a barrier layer between the work function metal and the gate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor integrated circuit device having an esd protection circuit

diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a y direction.
Socionext Inc.

Electrostatic discharge protection structure, manufacturing an electrostatic discharge protection structure, and vertical thyristor structure

according an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first well region extending from a surface of the semiconductor layer into the semiconductor layer, wherein the first well region is doped with a dopant of a second doping type opposite the first doping type; a second well region next to the first well region and extending from the surface of the semiconductor layer into the semiconductor layer, wherein the second well region is doped with a dopant of the first doping type; an isolation structure extending from the surface of the semiconductor layer into the semiconductor layer with a depth similar to the depth of at least one of the first well region or the second well region, wherein the isolation structure is arranged laterally adjacent to the first well region and the second well region.. .
Infineon Technologies Ag

Semiconductor device and manufacturing the same

a transistor includes a first insulator over a substrate; a first oxide thereover; a second oxide in contact with at least part of the top surface of the first oxide; a first conductor and a second conductor each in contact with at least part of the top surface of the second oxide; a third oxide that is over the first conductor and the second conductor and is in contact with at least part of the top surface of the second oxide; a second insulator thereover; a third conductor which is over the second insulator and at least part of which overlaps with a region between the first conductor and the second conductor; and a third insulator which is over the third conductor and at least part of which is in contact with the top surface of the first insulator. The thickness of a region of the first insulator that is in contact with the third insulator is less than the thickness of a region of the first insulator that is in contact with the first oxide..
Semiconductor Energy Laboratory Co., Ltd.

Integrated circuit and semiconductor device

in one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region..
Samsung Electronics Co., Ltd.

Methods of manufacturing semiconductor packages

a method of manufacturing a semiconductor package, the method including forming a hole that penetrates an interconnect substrate; providing a first carrier substrate below the interconnect substrate; providing a semiconductor chip in the hole; forming a molding layer by coating a molding composition on the semiconductor chip and the interconnect substrate; adhering a second carrier substrate onto the molding layer with an adhesive layer; removing the first carrier substrate to expose a bottom surface of the semiconductor chip and a bottom surface of the interconnect substrate; forming a redistribution substrate below the semiconductor chip and the interconnect substrate; detaching the second carrier substrate from the adhesive layer; and removing the adhesive layer.. .
Samsung Electronics Co., Ltd.

High frequency integrated circuit and emitting device for irradiating the integrated circuit

what is described is a high-frequency integrated circuit provided on a iii-v compound semiconductor, wherein an emitting device is radiation-coupled with the integrated circuit such that the emitting device irradiates the integrated circuit, and wherein the integrated circuit has at least one of an oscillator, a mixer, a phase shifter, a frequency divider or an amplifier.. .
Advantest Corporation

Method of manufacturing semiconductor package

a method of manufacturing a semiconductor package includes providing a substrate including a mounting region having a recess space for accommodating a semiconductor chip and a connection region surrounding the mounting region, providing a semiconductor chip in the mounting region, the semiconductor chip including a connection pad provided on a top surface of the semiconductor chip, forming a protective layer covering a top surface of the substrate and the top surface of the semiconductor chip, forming a photosensitive insulating layer on the protective layer after forming the protective layer, patterning the photosensitive insulating layer thereby exposing the protective layer, removing the exposed protective layer, and forming a redistribution line to be electrically connected to the connection pad.. .
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing the same

some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via.
Taiwan Semiconductor Manufacturing Company Ltd.

Methods of packaging semiconductor devices and packaged semiconductor devices

methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies.
Taiwan Semiconductor Manufacturing Company, Ltd.

Connecting techniques for stacked cmos devices

in some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a semiconductor substrate, and an inter-tier interconnecting structure disposed within the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor package, interposer and semiconductor process for manufacturing the same

a semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first main body, at least one first columnar portion and at least one first conductive layer.
Advanced Semiconductor Engineering, Inc.

Semiconductor device

a semiconductor device includes a semiconductor chip, pads provided on the semiconductor chip, and insulating patterns provided on the semiconductor chip. The insulating patterns having openings exposing the pads, and conductive patterns are provided in the openings and coupled to the pads.
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing the same

the semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad formed on an uppermost wiring layer of the plurality of wiring layers, a surface protection film which includes an opening on the pad and is made of an inorganic insulating film, a rewiring formed on the surface protection film; a pad electrode formed on the rewiring, and a wire connected to the pad electrode. The rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion which couples the pad electrode mounting portion and the connection portion, and the pad electrode mounting portion has a rectangular shape when seen in a plan view..

Final passivation for wafer level warpage and ulk stress reduction

embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular pspi region formed under a blm pad. An annular region is formed under a barrier layer metallurgy (blm) pad.
International Business Machines Corporation

Semiconductor device and manufacturing method thereof

a semiconductor device includes a semiconductor substrate in which a through hole is formed, a first wiring that is provided on a first surface of the semiconductor substrate, an insulating layer provided on an inner surface of the through hole and a second surface of the semiconductor substrate, and a second wiring that is provided on a surface of the insulating layer and electrically connected to the first wiring in an opening. The surface of the insulating layer includes a first region, a second region, a third region, a fourth region that is curved to continuously connect the first and the second regions, and a fifth region that is curved to continuously connect the second and the third regions.
Hamamatsu Photonics K.k.

Semiconductor package with three-dimensional antenna

a semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region, a semiconductor die disposed on the package substrate in the first region, a conductive shielding element disposed on the package substrate and covering the semiconductor die, and a three-dimensional (3d) antenna.
Mediatek Inc.

Rf module

in accordance with an embodiment, an rf module includes a bulk semiconductor substrate with at least one integrated rf component integrated in a first main surface region of the bulk semiconductor substrate; an insulator structure surrounding a side surface region of the bulk semiconductor substrate; a wiring layer stack including at least one structured metallization layer embedded into an insulation material, the wiring layer stack being arranged on the first main surface region of the bulk semiconductor substrate and a first main surface region of the insulator structure; and a carrier structure at a second main surface region of the insulator structure, wherein the carrier structure and the insulator structure include different materials.. .
Infineon Technologies Ag

Cavity formation in backside interface layer for radio-frequency isolation

a semiconductor device includes a transistor device implemented over an oxide layer, an interface layer applied below at least a portion of the oxide layer, the interface layer having a trench formed therein, and a substrate layer covering at least a portion of the interface layer and the trench to form a cavity.. .
Skyworks Solutions, Inc.

Substrate structure, packaging method and semiconductor package structure

a substrate structure includes a substrate body, at least one first mold area and at least one second mold area. The substrate body has a first surface and a second surface opposite to the first surface, and defines at least one first through hole extending through the substrate body.
Advanced Semiconductor Engineering, Inc.

Structure and formation chip package with fan-out structure

structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive feature and a protection layer surrounding the semiconductor die.
Taiwan Semiconductor Manufacturing Co., Ltd.

Structure and formation chip package with fan-out structure

structures and formation methods of a chip package are provided. The method includes disposing a semiconductor die over a carrier substrate and forming a protection layer over the carrier substrate to surround the semiconductor die.
Taiwan Semiconductor Manufacturing Co., Ltd.

Split rail structures located in adjacent metal layers

a first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines.
Taiwan Semiconductor Manufacturing Co., Ltd.

Sensor device

a sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor.
Renesas Electronics Corporation

Ic structure including tsv having metal resistant to high temperatures and forming same

an integrated circuit (ic) structure including: a first layer including a first plurality of active devices in a first semiconductor layer over a substrate; a first wiring layer over the first layer; a second layer including a second plurality of active devices within a second semiconductor layer over the first wiring layer; and a second wiring layer over the second layer, wherein the first wiring layer and the second wiring layer each including a first metal resistant to high temperature.. .
Globalfoundries Inc.

Fully molded miniaturized semiconductor module

a semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion.
Deca Technologies Inc.

Semiconductor device and wiring board design method

the present disclosure provides a semiconductor device including: a semiconductor chip; a substrate including a first region where the semiconductor chip is mounted and a second region separated from the first region; a conductive member provided at a second face of the substrate, the second face of the substrate is a face opposite to a first face to which the semiconductor chip is mounted; a protecting member, provided at the second face of the substrate to cover the conductive member, and including an opening partially exposing a portion of the conductive member placed at the second region; and an external connection terminal connected to the conductive member through the opening, wherein the protecting member contacts the substrate at a portion corresponding to an outer edge of the first region.. .
Lapis Semiconductor Co., Ltd.

Molded intelligent power module and making the same

an intelligent power module (ipm) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (mosfets), a tie bar, a metal slug, a plurality of spacers, a plurality of leads and a molding encapsulation. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth mosfets, the tie bar and the plurality of spacers.
Alpha And Omega Semiconductor (cayman) Ltd.

Semiconductor device and manufacturing method thereof

a semiconductor device of the present invention includes: a plurality of wiring boards disposed separately from one another; a plurality of semiconductor elements disposed on first main surfaces of the wiring boards and electrically connected to the wiring boards; a plurality of terminals electrically connected to the wiring boards; a sealing resin sealing the wiring boards and the semiconductor elements so that second main surfaces of the wiring boards are exposed.. .
Shindengen Electric Manufacturing Co., Ltd.

Die pad, semiconductor device, and producing semiconductor device

the specification discloses a technique for preventing a bonding material from reaching the upper and lower surfaces of a semiconductor chip in bonding the semiconductor chip using the bonding material. A die pad of the technique disclosed in the specification includes the following: a die pad substrate; a first projection disposed on the upper surface of the die pad substrate, the first projection having a pedestal shape; a second projection disposed on the upper surface of the die pad substrate so as to surround at least part of the first projection in a plan view, the second projection having a bank shape; and a third projection disposed on the upper surface of the die pad substrate so as to surround at least part of the second projection in a plan view, the third projection having a bank shape..
Mitsubishi Electric Corporation

Molded intelligent power module

an intelligent power module (ipm) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (mosfets), a tie bar, an ic, a plurality of leads and a molding encapsulation. The first mosfet is attached to the first die paddle.
Alpha And Omega Semiconductor (cayman) Ltd.

Air gap and air spacer pinch off

embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench.
International Business Machines Corporation

Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill

semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies.
Micron Technology, Inc.

Semiconductor device

a semiconductor device includes a semiconductor module and a cooler. The semiconductor device includes semiconductor element(s) within a molded resin and a heat sink plate exposed on the molded resin.
Toyota Jidosha Kabushiki Kaisha

Semiconductor device and manufacturing the same

a semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that generates compressive stress and has low density and a second insulation film that generates compressive stress and has high density.
Murata Manufacturing Co., Ltd.

Semiconductor device and manufacturing the same

a semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that has larger tensile stress and a second insulation film that has smaller tensile stress.
Murata Manufacturing Co., Ltd.

Method for passivating a surface of a semiconductor and related systems

a system and a method for passivating a surface of a semiconductor. The method includes providing the surface of the semiconductor to a reaction chamber of a reactor, exposing the surface of the semiconductor to a gas-phase metal containing precursor in the reaction chamber and exposing the surface of the semiconductor to a gas-phase chalcogenide containing precursor.
Asm Ip Holding B.v.

Semiconductor substrate

a semiconductor substrate includes a device carrier, a plurality of stiffener structures and a plurality of spaced areas. The device carrier includes a plurality of trace layout units and a periphery around the trace layout units.
Advanpack Solutions Pte. Ltd.

Semiconductor device and manufacturing the same

a semiconductor device includes a substrate with a recess subsiding from a selected surface of the substrate to accommodate a semiconductor element. Connected to the semiconductor element, an electroconductive portion extends from the recess onto the selected surface.
Rohm Co., Ltd.

Method for manufacturing a semiconductor product wafer

improved methods for manufacturing semiconductor product wafer with the additional use of non-product masks are described. According to certain aspects of the invention, an evaluation wafer is first manufactured by utilizing at least one non-product mask to process one or more layer(s) on the evaluation wafer, and subsequently utilizing at least one unaltered product mask to process an evaluation-region-of-interest on the evaluation wafer.
Pdf Solutions, Inc.

Metrology process control

methods and systems for estimating values of parameters of interest based on repeated measurements of a wafer during a process interval are presented herein. In one aspect, one or more optical metrology subsystems are integrated with a process tool, such as an etch tool or a deposition tool.
Kla-tencor Corporation

Semiconductor arrangement and forming

a semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the guard region.
Taiwan Semiconductor Manufacturing Company Limited

Finfet device and fabrication method thereof

a finfet device and fabrication method thereof is provided. The fabrication method include: providing a semiconductor substrate with a fin protruding from the semiconductor substrate, and a gate structure across a length portion of the fin and covering a portion of the fin; etching a partial thickness of the fin on both sides of the gate structure to form grooves; forming a doped layer in a bottom and sidewalls of the grooves; annealing the doped layer to allow the doping ions to diffuse into the fin and to form a lightly doped source/drain region; removing the doped layer after the annealing; and forming epitaxial layers to fill up the grooves..
Semiconductor Manufacturing International (beijing) Corporation

Semiconductor device and manufacturing method therefor

the present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device includes a substrate; two fins located on the substrate and extending along a first direction; an isolation material layer surrounding the fins, comprising a first isolation regions located at an end region between the two fins along the first direction, and a second isolation region located at sides of the fins along a second direction that is different from the first direction, wherein an upper surface of the first isolation region substantially align with an upper surfaces of the fins, and an upper surface of the second isolation region is lower than the upper surface of the fins; and a first insulating layer on the first isolation region.
Imec International

Semiconductor apparatus and manufacturing method

a semiconductor apparatus and its manufacturing method are presented. The method entails providing a substrate structure comprising a substrate, one or more fins positioned along a first direction on the substrate, and a separation region surrounding the fins.
Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor device and a forming a semiconductor device

a method for forming a semiconductor device comprises forming an insulation trench structure comprising insulation material extending into the semiconductor substrate from a surface of the semiconductor substrate. The insulation trench structure laterally surrounds a portion of the semiconductor substrate.
Infineon Technologies Ag

Member for semiconductor manufacturing producing the same

a method for producing a member for a semiconductor manufacturing apparatus 10 includes (a) a step of providing an electrostatic chuck 20, a supporting substrate 30, and a metal bonding material 401, the electrostatic chuck being made of a ceramic and having a form of a flat plate, the supporting substrate including a composite material having a difference in linear thermal expansion coefficient at 40 to 570° c. From the ceramic of 0.2×10−6/k or less in absolute value, and (b) a step of interposing the metal bonding material 401 between a concave face 32 of the supporting substrate 30 and a face 23 of the electrostatic chuck 20 opposite to a wafer mounting face 22, and thermocompression bonding the supporting substrate 30 and the electrostatic chuck 20 at a predetermined temperature to deform the electrostatic chuck 20 to the shape of the concave face 32..
Ngk Insulators, Ltd.

Semiconductor wafer transportation

a method includes causing a carrier of an overhead hoist transfer system (oht) to latch onto a top latch of a first semiconductor wafer transportation pod, the first semiconductor wafer transportation pod comprising a top latching mechanism configured to selectively connect to another pod or a carrier mechanism of an overhead hoist transfer (oht) system, and a bottom latching mechanism configured to selectively connect to another pod. The method further includes rotating the first semiconductor wafer transportation pod such that the top latching mechanism of the first semiconductor wafer transportation pod latches on to a second semiconductor wafer transportation pod..
Taiwan Semiconductor Manufacturing Co., Ltd.

Systems and methods for workpiece processing

systems and methods for processing workpieces, such as semiconductor workpieces are provided. One example embodiment is directed to a processing system for processing a plurality of workpieces.
Mattson Technology, Inc.

Semiconductor bonding apparatus and related techniques

a semiconductor structure bonding apparatus is disclosed. The apparatus may include a leveling adjustment system configured to provide leveling adjustment of upper and lower block assemblies of the apparatus.
Suss Microtec Lithography Gmbh

Semiconductor device and forming interposer with opening to contain semiconductor die

a semiconductor device has an interposer mounted over a carrier. The interposer includes tsv formed either prior to or after mounting to the carrier.
Stats Chippac Pte. Ltd.

Method of forming an interposer and a manufacturing a semiconductor package including the same

a method of manufacturing a semiconductor package including forming a photoresist pattern on a first surface of an interposer substrate. The interposer substrate includes an electrode zone and a scribe line zone.
Samsung Electronics Co., Ltd.

Controlling of etch depth in deep via etching processes and resultant structures

the present disclosure relates to semiconductor structures and, more particularly, to a method to control depth of etch in deep via etching and related structures. The method includes: forming an interface within the substrate between an etch control dopant and material of the substrate; etching a via within substrate; and terminating the etching of the via at the interface upon detection of the interface..
Globalfoundries Inc.

Method of forming nanowires

the disclosed technology generally relates semiconductor devices and more particularly to semiconductor devices comprising nanowires. In one aspect, a method of fabricating a semiconductor device includes providing a semiconductor substrate having one or more elongated structures thereon and forming a strained layer of semiconductor material on at least one surface of the elongated structures, and annealing the strained layer to form a semiconductor nanowire..
Imec Vzw

Method for forming a thin film comprising an ultrawide bandgap oxide semiconductor

a method is disclosed for depositing a high-quality thin films of ultrawide bandgap oxide semiconductors at growth rates that are higher than possible using prior-art methods. Embodiments of the present invention employ lpcvd deposition using vapor formed by evaporating material as a precursor, where the material has a low vapor pressure at the growth temperature for the thin film.
Case Western Reserve University

Bonded semiconductor structures

a method is disclosed that includes operations as follows. With an ion-implanted layer which is disposed between an epitaxial layer and a first semiconductor substrate, the epitaxial layer is bonded directly to a second semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Perovskite photovoltaic device

a photovoltaic device, comprises (1) a first conductive layer, (2) an optional blocking layer, on the first conductive layer, (3) a semiconductor layer, on the first conductive layer, (4) a light-harvesting material, on the semiconductor layer, (5) a hole transport material, on the light-harvesting material, and (6) a second conductive layer, on the hole transport material. The light-harvesting material comprises a perovskite absorber, and the second conductive layer comprises nickel.
Board Of Trustees Of Northern Illinois University

Semiconductor device for directly converting radioisotope emissions into electrical power

a device for producing electricity. In one embodiment, the device comprises a doped germanium or a doped gaas substrate and a plurality of stacked material layers (some of which are doped) above the substrate.
City Labs, Inc.

Test mode circuit for memory apparatus

apparatuses for error detection and correction for a semiconductor device are described. An example apparatus includes: at least one memory cell array including a plurality of memory cells; and a control circuit that receives read data from the plurality of memory cells, compares the read data with reference data, and further provides an error signal.
Micron Technology, Inc.

Input/output terminal characteristic calibration circuit and semiconductor apparatus including the same

an input/output terminal characteristic calibration circuit may include a plurality of input/output terminals a subset of which is configured to partially and selectively receive a characteristic calibration signal according to an external input, such that characteristics of the input/output terminals corresponding to the characteristic calibration signal are calibrated. The input/output terminal characteristic calibration circuit may also include a characteristic calibration signal generation circuit coupled to the plurality of input/output terminals in common through a test signal line, and configured to provide the characteristic calibration signal to the plurality of input/output terminals in common through the test signal line..
Sk Hynix Inc.

Semiconductor memory apparatus

a semiconductor memory apparatus may include a control circuit, a decoding circuit, and a memory circuit. The control circuit may output one of bank group signals as either a first bank group distribution signal or a second bank group distribution signal and output one of data designation addresses as either a first data designation distribution address or a second data designation distribution address, in response to a first test signal and a second test signal.
Sk Hynix Inc.

Semiconductor device and operating the same

a semiconductor device includes a fuse array section suitable for performing program and read operations; a control signal generation section suitable for generating a precharge control signal and a word line control signal; a bit line control section suitable for controlling a precharge operation of a bit line in response to the precharge control signal and a source signal; and a word line control section suitable for controlling activation of a program word line and a read word line for performing the program and read operations in response to the word line control signal, wherein the control signal generation section controls the word line control signal to be activated after a predetermined time from the activation of the precharge control signal.. .
Sk Hynix Inc.

Semiconductor memory device

a semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line..
Toshiba Memory Corporation

Three-dimensional vertical nor flash thin-film transistor strings

a memory structure includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions.
Sunrise Memory Corporation

Nonvolatile memory control method, control device, and semiconductor storage device

disclosed is a nonvolatile memory control method in which a unit of erase and a unit of read are different from each other. The control method includes: allocating a physical address of the nonvolatile memory to a logical address in a predetermined unit; and controlling a size of the unit of erase in which a physical address allocated to a logical address is included according to a write access state with respect to the logical address in the predetermined unit..
Hitachi, Ltd.

Data sense amplification circuit and semiconductor memory device including the same

a semiconductor memory device includes: a first memory cell coupled to a first bit line; a second memory cell coupled to a second bit line; and a sense amplification circuit for sensing and amplifying a voltage difference between the first and second bit lines, wherein the sense amplification circuit includes: a first sense amplifier including a cross-coupled pair of first and second transistors coupled to the first bit line and the second bit line, respectively; a second sense amplifier including a cross-coupled pair of third and fourth transistors coupled to the first and second bit lines, respectively; and an offset supplier for controlling a timing for supplying a voltage of the first bit line to the first transistor and a timing for supplying a voltage of the second bit line to the second transistor according to a selected memory from the first and second memory cells.. .
Sk Hynix Inc.

Method and decoding commands

method and apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles: validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle..
Micron Technology, Inc.

Semiconductor storage device and writing of the same

a semiconductor storage device includes a memory cell, a switch, a source driver, a drain driver, a voltage measurement circuit and a control electrode driver. The memory cell has a control electrode, a floating electrode, a source and a drain.
Denso Corporation