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Semiconductor patents

      

This page is updated frequently with new Semiconductor-related patent applications.




 Electronic apparatus patent thumbnailElectronic apparatus
An electronic apparatus includes a conductive member and a printed circuit board, wherein the printed circuit board includes a printed wiring board having a signal wiring formed thereon, a first semiconductor device configured to output a digital signal to the signal wiring, and a second semiconductor device configured to input the digital signal output from the first semiconductor device via the signal wiring, wherein the signal wiring has a signal wiring pattern formed on a surficial layer located opposite the conductive member in the printed wiring board, and wherein the conductive member has an aperture formed therein and located opposite the signal wiring pattern or includes a flat plate portion and a recessed portion recessed in a direction more away from the printed wiring board than the flat plate portion.. .
Canon Kabushiki Kaisha


 Organic tft array inspection device and method patent thumbnailOrganic tft array inspection device and method
To provide an inspection device and an inspection method which are capable of detecting a disconnection defect in an organic tft array and/or evaluating a variation in the output properties and response speed of each organic tft element. There are provided a device and a method of optically measuring the presence or absence of the accumulation of carriers in an organic semiconductor thin film which provides a channel layer of an organic tft element.
National Institute Of Advanced Industrial Science And Technology


 Data management apparatus and monitoring  same patent thumbnailData management apparatus and monitoring same
A data management apparatus according to an embodiment of the present invention includes a data analyzing unit that processes operation data transferred from a data collecting unit that collects the operation data of a semiconductor manufacturing apparatus, and a state monitoring unit that monitors a state of the data analyzing unit based on monitoring time. The monitoring time is the sum of first time that is time required for transferring the operation data to the data analyzing unit and second time that is time required for processing the operation data in the data analyzing unit..
Hitachi High-technologies Corporation


 Coherent optical spectrum analyser for monitoring a spectrum of a fibre link patent thumbnailCoherent optical spectrum analyser for monitoring a spectrum of a fibre link
A coherent optical spectrum analyser for monitoring a spectrum of a fibre link is provided. The coherent optical spectrum analyser comprises an input connectable to the fibre link, the input being connected to a first input of a coherent detector having at least two input, the first and a second input, and an output.
Telefonaktiebolaget Lm Ericsson (publ)


 Semiconductor device patent thumbnailSemiconductor device
A delay time is set only within the variable delay time of a clock driver and cannot be set longer than the variable delay time of the clock driver. A control circuit adjusts the delay amount of a variable delay circuit so as to synchronize a pulse phase after a first pulse outputted from a pulse generation circuit passes through the variable delay circuit n times and a second pulse outputted from the pulse generation circuit..
Renesas Electronics Corporation


 Semiconductor device, electronic component, and electronic device patent thumbnailSemiconductor device, electronic component, and electronic device
Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential.
Semiconductor Energy Laboratory Co., Ltd.


 Clock generating circuit and semiconductor apparatus including the same patent thumbnailClock generating circuit and semiconductor apparatus including the same
A clock generation circuit may include a first clock generator, a second clock generator, and a common mode generator. The first clock generator may generate a multi-phase clock signal from a first clock signal.
Sk Hynix Inc.


 Fully integrated low-noise amplifier patent thumbnailFully integrated low-noise amplifier
A low-noise amplifier device includes an inductive input element, an amplifier circuit, an inductive output element and an inductive degeneration element. The amplifier device is formed in and on a semiconductor substrate.
Stmicroelectronics Sa


 Vapor chamber amplifier module patent thumbnailVapor chamber amplifier module
In one embodiment, an electronic system includes a printed circuit board, one or more packaged semiconductor devices, and a vapor chamber having a top and a bottom and enclosing a sealed cavity that is partially filled with a coolant. The vapor chamber comprises a thermo-conductive and electro-conductive material.
Commscope Technologies Llc


 Semiconductor device and semiconductor module patent thumbnailSemiconductor device and semiconductor module
A semiconductor device includes: a voltage-dividing resistor circuit including first and second resistors connected in series between a power supply potential and a reference potential and outputting a potential at a point of connection between the first and second resistors; a transient response detection circuit including a third resistor having a first end connected to the power supply potential and a capacitor connected between a second end of the third resistor and the reference potential, and outputting a potential at a point of connection between the third resistor and the capacitor; an and circuit anding an output signal of the voltage-dividing resistor circuit and an output signal of the transient response detection circuit; and an output circuit, wherein switching of the output circuit is controlled by an output signal of the and circuit.. .
Mitsubishi Electric Corporation


Waveguide embedded plasmon laser with multiplexing and electrical modulation

This disclosure provides systems, methods, and apparatus related to nanometer scale lasers. In one aspect, a device includes a substrate, a line of metal disposed on the substrate, an insulating material disposed on the line of metal, and a line of semiconductor material disposed on the substrate and the insulating material.
The Regents Of The University Of California

Semiconductor laser with external resonator

A semiconductor laser device with external resonator with stable longitudinal mode regardless of variation of drive current is disclosed. The device includes: a semiconductor light-emitting element having a pair of end faces with a light emitting section disposed therebetween, and an external resonator configured to oscillate light emitted from the semiconductor light-emitting element, the external resonator being formed by a resonator mirror disposed outside the semiconductor light-emitting element and one of the pair of end faces that is farther from the resonator mirror, wherein, as the semiconductor light-emitting element, a semiconductor light-emitting element having a structure which does not oscillate light emitted therefrom by itself is used.
Showa Optronics Co., Ltd.

Broadband back mirror for a iii-v chip in silicon photonics

A semiconductor laser has a mirror formed in a gain chip. The mirror can be placed in the gain chip to provide a broadband reflector to support multiple lasers using the gain chip.
Skorpios Technologies, Inc.

Hybrid on-chip and package antenna

Antenna devices, antenna systems and methods of their fabrication are disclosed. One such antenna device includes a semiconductor chip and a chip package.
International Business Machines Corporation

Antenna module and circuit module

An antenna that is formed of a conductor pattern is disposed on a dielectric substrate. A high-frequency semiconductor device that supplies a high-frequency signal to the antenna is mounted on the bottom surface of the dielectric substrate.
Murata Manufacturing Co., Ltd.

Plating methods for modular and/or ganged waveguides for automatic test equipment for semiconductor testing

Embodiments of the present disclosure perform incisions along the direction of the long axis of the waveguide, thereby exposing a trench structure which can be readily plated. Once divided and plated, the individual cut pieces can then be secured together to restore the original waveguide structure.
Advantest Corporation

Wave interface assembly for automatic test equipment for semiconductor testing

Embodiments of the present disclosure utilize customizable waveguide fabrication technologies (e.g., 3d printer technology) and patch antenna arrays to create adaptable wave interfaces that can provide efficient signal routing for an ate system. In this fashion, embodiments of the present disclosure allow for arbitrary waveguide routing from port to port and create high density port spacing at the pcb level and which specifically eliminates the large flange required of prior art waveguides.
Advantest Corporation

Multiple waveguide structure with single flange for automatic test equipment for semiconductor testing

Embodiments of the present disclosure use customizable waveguides that can be positioned next to each other in a structure that contains one single flange to provide a physical connection for the waveguides. In this fashion, many waveguides can be positioned within a small area to accommodate a tightly packed patch antenna array so that the waveguides can be positioned very close to the socket.
Advantest Corporation

Organic semiconductor element, manufacturing method thereof, composition for forming organic semiconductor film, compound, and organic semiconductor film

The organic semiconductor element according to the present invention includes a compound represented by formula 1 below included in an organic semiconductor layer.. .

Organic semiconductor element, manufacturing method thereof, compound, composition for forming organic semiconductor film, and organic semiconductor film

The organic semiconductor element according to the invention includes an organic semiconductor layer containing an organic semiconductor having a repeating unit represented by formula 1.. .

Semiconductor structure and manufacturing method thereof

The present disclosure provides a semiconductor structure, including an nth metal layer, a planar bottom barrier layer over and in contact with the nth metal layer, a data storage layer over the planar bottom barrier layer, an electrode over the data storage layer, and an (n+1)th metal layer over the electrode. N is a positive integer.
Taiwan Semiconductor Manufacturing Company Ltd.

Lead frame and semiconductor device

A light emitting device includes a resin package and a light emitting element. The resin package has a cavity.
Nichia Corporation

Lead frame and semiconductor device

A lead frame includes a plurality of units connected together. Each unit includes a pair of lead portions spaced apart from and opposite to each other.
Nichia Corporation

Semiconductor light-emitting device and manufacturing the same

A semiconductor light-emitting device, and a method of manufacturing the same. The semiconductor light-emitting device includes a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked on a substrate, a first contact that passes through the substrate to be electrically connected to the first electrode layer, and a second contact that passes through the substrate, the first electrode layer, and the insulating layer to communicate with the second electrode layer.
Samsung Electronics Co., Ltd.

Light emitting device and producing the same

A light emitting device includes a semiconductor light emitting element; and a light reflective member having a multilayer structure and covering the side faces of the semiconductor light emitting element. The light reflective member includes: a first layer disposed on an inner, semiconductor light emitting element side, the first layer comprising a light-transmissive resin containing a light reflective substance, and a second layer disposed in contact with an outer side of the first layer, the second layer comprising a light-transmissive resin containing the light reflective substance at a lower content than that of the first layer..
Nichia Corporation

Method for producing semiconductor light-emitting device

A method for producing a semiconductor light-emitting device involves applying a silicone resin composition to a surface of a semiconductor light-emitting element and forming an encapsulating portion covering the surface of the light-emitting element by heat curing the applied resin composition. The silicone resin composition contains at least 60% by mass of a silicone resin in which the constituent silicon atoms are substantially only silicon atoms to which three oxygen atoms are bonded.
Sumitomo Chemical Company, Limited

Light emitting device with beam shaping structure and manufacturing the same

A chip scale packaging (csp) light emitting diode (led) device includes a flip-chip led semiconductor die and a beam shaping structure (bss) to form a monochromatic csp led device. A photoluminescent structure can be disposed on the led semiconductor die to form a phosphor-converted white-light csp led device.
Maven Optronics Co., Ltd.

Nitride nanowires and producing such

The present invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, leds and transistors. According to the method of the invention nitride semiconductor nanowires are grown utilizing a cvd based selective area growth technique.
Qunano Ab

Patterned substrate design for layer growth

A patterned surface for improving the growth of semiconductor layers, such as group iii nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings.
Sensor Electronic Technology, Inc.

Stress relieving semiconductor layer

A semiconductor structure, such as a group iii nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer.
Sensor Electronic Technology, Inc.

Semiconductor material doping

A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier.
Sensor Electronic Technology, Inc.

Nitride semiconductor light-emitting element

A nitride semiconductor light-emitting element includes an n-side layer; a p-side layer; and a light-emitting layer having a multiple quantum well structure, the light-emitting layer being located between the n-side layer and the p-side layer. The light-emitting layer includes: an n-side first barrier layer, a plurality of well layers, including an n-side first well layer, an n-side second well layer, and one or more additional well layers, and a plurality of intermediate layers, including an n-side first intermediate barrier layer and one or more additional intermediate barrier layers.
Nichia Corporation

Laser scribing of thin-film solar cell panel

The present invention describes an apparatus for a first laser scribing (p1) on the front electrode of a thin film solar cell panel and a similar apparatus for subsequent laser scribing (p2,p3) on the semiconductor layer and semiconductor layer/rear electrode. Before starting scribing process (p1), the left hand edge or reference line on the left hand edge on a workpiece is aligned substantively parallel to the linear drive before translating the workpiece on the apparatus.
Manufacturing Integration Technology Ltd

Photodiode, photodiode array, and solid-state imaging device

A photodiode that multiplies a charge generated by photoelectric conversion in an avalanche region includes: a p− type semiconductor layer having interfaces; an n+ type semiconductor region located inside the p− type semiconductor layer and in contact with the interface; an n+ type semiconductor region located inside the p− type semiconductor layer and connected to the n+ type semiconductor region; and a p type semiconductor region located between the n+ type semiconductor region and the interface, wherein the n+ type semiconductor region, the n+ type semiconductor region, and the p type semiconductor region each have a higher impurity concentration than the p− type semiconductor layer, the avalanche region is a region between the n+ type semiconductor region and the p type semiconductor region inside the p− type semiconductor layer, and the n+ type semiconductor region has a smaller area than the n+ type semiconductor region in planar view.. .
Panasonic Intellectual Property Management Co., Ltd.

Semiconductor element with a single photon avalanche diode and manufacturing such semiconductor element

A method for manufacturing a semiconductor element comprising a single photon avalanche diode having a multiplication zone (ar) a guard ring structure with a second type of electrical conductivity comprises providing a semiconductor wafer with a first region (r) comprising a semiconductor material with the first type of conductivity. The method further comprises generating by a first doping process a first well (w1) of the guard ring structure having a first vertical depth, the first well (w1) laterally surrounding the multiplication zone (ar) and having a lateral distance (a) from the multiplication zone (ar).
Ams Ag

Increasing capture of electron hole pairs in a photovoltaic cell structure

A photovoltaic cell structure for converting light energy into electrical energy is provided herein. One of skill will appreciate having, for example, a photovoltaic cell structure configured to increase capture of electron hole pairs.
Qsolar Technology, Inc.

Systems and methods for monolithically isled solar photovoltaic cells and modules

According to one aspect of the disclosed subject matter, a monolithically isled solar cell is provided. The solar cell comprises a semiconductor layer having a light receiving frontside and a backside opposite the frontside and attached to an electrically insulating backplane.
Solexel, Inc.

Power generation battery

Provided is a power generation battery capable of improving power generation efficiency. The power generation battery includes a first layer, a second layer, and a filter layer.
Honda Motor Co.,ltd.

Self-aligned heterojunction field effect transistor

A junction field effect transistor (jfet) comprises an insulating carrier substrate, a base semiconductor substrate formed on the insulating carrier substrate and a gate region formed on the base semiconductor substrate. The gate region forms a junction with the base semiconductor substrate.
International Business Machines Corporation

Semiconductor device and manufacturing the same

A metal element of a metal film is introduced into the oxide semiconductor film by performing heat treatment in the state where the oxide semiconductor film is in contact with the metal film, so that a low-resistance region having resistance lower than that of a channel formation region is formed. A region of the metal film, which is in contact with the oxide semiconductor film, becomes a metal oxide insulating film by the heat treatment.
Semiconductor Energy Laboratory Co., Ltd.

Thin-film transistor

According to one embodiment, a thin-film transistor includes a polycrystalline semiconductor layer, a gate electrode opposing the polycrystalline semiconductor layer, a gate insulating film provided between the gate electrode and the polycrystalline semiconductor layer and in contact with the gate electrode, and an amorphous layer provided between the gate insulating film and the polycrystalline semiconductor layer, and in contact with the gate insulating film and the polycrystalline semiconductor layer.. .
Japan Display Inc.

Thin film transistor and manufacturing thin film transistor

According to one embodiment, a manufacturing method of thin film transistor includes forming an oxide semiconductor layer on a first insulating film, forming a first conductive layer formed of molybdenum or a molybdenum alloy on the oxide semiconductor layer, forming a second conductive layer on the first conductive layer, forming a resist mask on the second conductive layer, and forming a first conductive portion and a second conductive portion by performing dry etching of the second conductive layer using the resist mask.. .
Japan Display Inc.

Fin field effect transistor and fabricating method thereof

A finfet including a substrate, a plurality of insulators and a gate stack is provided. The substrate includes a plurality of trenches and at least one semiconductor fin between the trenches.
Taiwan Semiconductor Manufacturing Co., Ltd.

Iii-v fins by aspect ratio trapping and self-aligned etch to remove rough epitaxy surface

A semiconductor device that includes a fin structure of a type iii-v semiconductor material that is substantially free of defects, and has sidewalls that are substantially free of roughness caused by epitaxially growing the type iii-v semiconductor material abutting a dielectric material. The semiconductor device further includes a gate structure present on a channel portion of the fin structure; and a source region and a drain region present on opposing sides of the gate structure..
International Business Machines Corporation

Device with diffusion blocking layer in source/drain region

A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a source/drain region.
Globalfoundries Inc.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a pillar structure, at least one charge storage film, and a first electrode. The stacked body includes electrode films stacked separately from each other.
Kabushiki Kaisha Toshiba

Semiconductor structure and associated fabricating method

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (rpo) layer formed on a top surface of the second region.
Taiwan Semiconductor Manufacturing Company Ltd.

Semiconductor device

A semiconductor apparatus includes: a gate electrode in a trench and facing a p type base region with a gate insulating film interposed therebetween on a portion of a side wall; a shield electrode in the trench and between the gate electrode and a bottom of the trench; an electric insulating region in the trench, the electric insulating region extending between the gate electrode and the shield electrode, and further extending along the side wall and the bottom of the trench to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an n+ type source region and the shield electrode. The shield electrode has high resistance regions at positions where the high resistance regions face the side walls of the trench, and a low resistance region at a position where the low resistance region is sandwiched between the high resistance regions..
Shindengen Electric Manufacturing Co., Ltd.

Semiconductor device

A mos gate structure is provided on a p-type base layer side of a silicon carbide semiconductor base formed by sequentially forming on a front surface of an n+-type silicon carbide substrate, an n-type drift layer and a p-type base layer by epitaxial growth. On the base front surface, in an edge termination structure region, a step portion occurring between the p-type base layer and the n-type drift layer, and a flat portion farther outward than the step portion are provided.
Fuji Electric Co., Ltd.

Semiconductor device and manufacturing same

To provide a semiconductor device equipped with a snubber portion having an improved withstand voltage and capable of reducing a surge voltage at turn-off of an insulated gate field effect transistor portion. The concentration of a first conductivity type impurity in a snubber semiconductor region is greater than that in a drift layer.
Renesas Electronics Corporation

Thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, and display device

Provided are a thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, and display device. The thin film transistor comprises: an active layer, an etch stop layer disposed on the active layer, an overcoating layer disposed on the etch stop layer, and a source electrode and a drain electrode disposed on the overcoating layer, wherein the overcoating layer comprises at least one of a conductive material layer, a non-transparent insulation layer and a non-transparent semiconductor layer, and the source electrode and the drain electrode are electrically connected with the active layer..
Boe Technology Group Co., Ltd.

Semiconductor structure and associated fabricating method

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate.
Taiwan Semiconductor Manufacturing Company Ltd.

Iii-nitride based n polar vertical tunnel transistor

A semiconductor structure, device, or n-polar ill-nitride vertical field effect transistor. The structure, device, or transistor includes a current blocking layer and an aperture region.
Arizonaa Board Of Regents On Behalf Of Arizona State University

Semiconductor structure and manufacturing method thereof

The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first iii-v compound layer over the substrate, a second iii-v compound layer on the first iii-v compound layer, a third iii-v compound layer on the second iii-v compound layer, a source region on the third iii-v compound layer, and a drain region on the third iii-v compound layer.
Taiwan Semiconductor Manufacturing Company Ltd.

Enhanced normally-off high electron mobility heterojunction transistor

A high electron mobility field-effect transistor of normally-off type, including a first layer of gan with p-type doping; a second layer of gan with n-type doping formed on the first layer of gan; a third layer of unintentionally doped gan formed on the second layer of gan; a semiconductor layer formed to form an electron gas layer; a cavity formed through the third layer of gan, without reaching the bottom of the second layer of gan; a gate including a conductive gate material and a gate insulation layer arranged in the cavity, the gate insulation layer electrically insulating the conductive gate material relative to the second and third layers of gan.. .
Commissariat A L'energie Atomique Et Aux Energies Alternatives

Semiconductor device, power-supply device, and amplifier

A semiconductor device includes a substrate, a buffer layer including a nitride semiconductor and formed over the substrate, a composition gradient layer including a nitride semiconductor and formed over the buffer layer, a first semiconductor layer including a nitride semiconductor and formed over the composition gradient layer, a second semiconductor layer including a nitride semiconductor and formed over the first semiconductor layer, and a gate electrode, a source electrode, and a drain electrode that are formed over the second semiconductor layer. The buffer layer is formed of a material including gan, the composition gradient layer is formed of a material including al, and the proportion of al in the composition gradient layer increases from a first side of the composition gradient layer closer to the buffer layer toward a second side of the composition gradient layer closer to the first semiconductor layer..
Fujitsu Limited

Semiconductor device and manufacturing method thereof

When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device manufacturing method

When forming a misfet by replacing a dummy gate electrode with a metal gate electrode in a gate last process, formation caused by polishing of an interlayer insulation film of a silicide layer over an upper surface of the dummy gate electrode to result in hampering the removal of the dummy gate is prevented. In the gate last process, when an interlayer insulation film is polished to expose an upper surface of a dummy gate electrode, a slurry mixed with an acidic aqueous solution is used to prevent silicide layer formation over the upper surface of the dummy gate electrode..
Renesas Electronics Corporation

Finfet device and fabricating same

Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (finfets). An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor structure and fabrication method thereof

The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate, each fin having a first sidewall surface and an opposing second sidewall surface; performing an asymmetric oxidation process on the fins to oxidize the first sidewall surfaces of the fins to form a first oxide layer, and to oxidize the second sidewall surfaces of the fins to form a second oxide layer, a thickness of the first oxide layer being different from a thickness of the second oxide layer, and un-oxidized portions of the fins between the first oxide layer and the second oxide layer being configured as channel layers; removing the second oxide layer and a partial thickness of the first oxide layer; and forming a gate structure crossing over the channel layers over the semiconductor substrate..
Semiconductor Manufacturing International (beijing) Corporation

Finfet devices having a material formed on reduced source/drain region

A semiconductor device includes a fin structure of a first semiconductor material on a substrate. The fin structure has a source region, a drain region, and a channel region between the source region and the drain region.
Semiconductor Manufacturing International (shanghai) Corporation

Vertical transistor device

According to an embodiment of the present invention, a method for forming a semiconductor device includes pattering a first fin in a semiconductor substrate, and forming a liner layer over the first fin. The method further includes removing a first portion of the liner layer, and removing a portion of the exposed semiconductor substrate to form a first cavity.
International Business Machines Corporation

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device includes carrying out a first heat treatment accompanied by nitration on a first insulating film and a silicon carbide substrate in a first gas atmosphere, after the carrying out of the first heat treatment and after a temperature of the silicon carbide substrate has become 700° c. Or less, removing the silicon carbide substrate from a processing apparatus and exposing the silicon carbide substrate to air in an atmosphere outside of the processing apparatus, and after the exposing of the silicon carbide substrate to air in the atmosphere, carrying out a second heat treatment on the first insulating film and the silicon carbide substrate in a second gas atmosphere which is an inert gas..
Renesas Electronics Corporation

Vertical transistor device

According to an embodiment of the present invention, a method for forming a semiconductor device includes pattering a first fin in a semiconductor substrate, and forming a liner layer over the first fin. The method further includes removing a first portion of the liner layer, and removing a portion of the exposed semiconductor substrate to form a first cavity.
International Business Machines Corporation

Replacement iii-v or germanium nanowires by unilateral confined epitaxial growth

A lateral epitaxial growth process is employed to facilitate the fabrication of a semiconductor structure including a stack of suspended iii-v or germanium semiconductor nanowires that are substantially defect free. The lateral epitaxial growth process is unidirectional due to the use of masks to prevent epitaxial growth in both directions, which would create defects when the growth fronts merge.
International Business Machines Corporation

Nanowire semiconductor device including lateral-etch barrier region

A semiconductor device includes a semiconductor-on-insulator wafer having a buried layer. The buried layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions.
International Business Machines Corporation

Semiconductor device and manufacturing the same

A semiconductor device having electrodes of three or more levels, includes: a semiconductor substrate; an epitaxial layer formed on the semiconductor substrate; a transistor formed on the epitaxial layer; a source electrode formed on the epitaxial layer and electrically connected to a source of the transistor; and a gate drawing electrode formed on the epitaxial layer and electrically connected to a gate of the transistor, wherein the source electrode includes a first source electrode, a second source electrode which is an electrode at a second or higher level on the first source electrode, and a third source electrode which is an electrode at a third or higher level on the second source electrode and above the gate drawing electrode, and the gate drawing electrode is an electrode at a second or higher level on the first source electrode and surrounded with the first, second, and third source electrodes.. .
Mitsubishi Electric Corporation

Semiconductor device and manufacturing same

To provide a highly reliable semiconductor device having both an improved breakdown voltage and a reduced withstand voltage leakage current. An intermediate resistive field plate is comprised of a first intermediate resistive field plate coupled, at one end thereof, to an inner-circumferential-side resistive field plate and, at the other end, to an outer-circumferential-side resistive field plate and a plurality of second intermediate resistive field plates.
Renesas Electronics Corporation

Electron gas confinement heterojunction transistor

A high electron mobility heterojunction transistor, including a first gan layer; a second, p-doped gan layer on top of the first layer, including magnesium as a p-type dopant, the concentration of which is at least equal to 5*1016 cm−3 and at most equal to 2*1018 cm−3, the thickness of the second gan layer being between 20 and 50 nm; a third, n-doped gan layer on top of the second gan layer in order to form a depleted p-n junction; a fourth gan layer, which is not intentionally doped, on top of the third gan layer; a semiconductor layer plumb with the fourth gan layer, which is not intentionally doped, in order to form an electron gas layer.. .
Commissariat A L'energie Atomique Et Aux Energies Alternatives

Semiconductor structure comprising an active semiconductor layer of the iii-v type on a buffer layer stack and producing semiconductor structure

A semiconductor structure includes a buffer layer stack comprising a plurality of iii-v material layers, and the buffer layer stack includes at least one layered substructure. Each layered substructure comprises a compressive stress inducing structure between a respective first buffer layer and a respective second buffer layer positioned higher in the buffer layer stack than the respective first buffer layer.
Epigan Nv

Semiconductor component with a multi-layered nucleation body

There are disclosed herein various implementations of a semiconductor component with a multi-layered nucleation body and method for its fabrication. The semiconductor component includes a substrate, a nucleation body situated over the substrate, and a group iii-v semiconductor device situated over the nucleation body.
Infineon Technologies Americas Corp.

Silicon carbide semiconductor device and manufacturing the same

A silicon carbide semiconductor device includes: n type regions formed on a surface of the n− type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p− type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p− type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p− type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p− type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.. .
Shindengen Electric Manufacturing Co., Ltd.

Method for forming a semiconductor device and a semiconductor device

A method for forming a semiconductor device includes incorporating first dopant atoms of a first conductivity type into a semiconductor substrate to form a first doping region of the first conductivity type. Further, the method includes forming an epitaxial semiconductor layer on the semiconductor substrate and incorporating second dopant atoms of a second conductivity type before or after forming the epitaxial semiconductor layer to form a second doping region including the second conductivity type adjacent to the first doping region so that a pn-junction is located between the first doping region and the second doping region.
Infineon Technologies Ag

Stacked nanowire devices

A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.. .
International Business Machines Corporation

Mechanical stress-decoupling in semiconductor device

According to a method in semiconductor device fabrication, a first trench and a second trench are concurrently etched in a semi-finished semiconductor device. The first trench is a mechanical decoupling trench between a first region of an eventual semiconductor device and a second region thereof.
Infineon Technologies Ag

Power device on bulk substrate

A metal-oxide-semiconductor field-effect transistor (mosfet) power device includes an active region formed on a bulk semiconductor substrate, the active region having a first conductivity type formed on at least a portion of the bulk semiconductor substrate. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region.
Silanna Asia Pte Ltd

Semiconductor device

A source region of a mosfet includes a source contact region connected to a source electrode, a source extension region adjacent to a channel region of a well region, and a source resistance control region provided between the source extension region and the source contact region. The source resistance control region includes a low concentration source resistance control region which has an impurity concentration lower than that of the source contact region or the source extension region and a high concentration source resistance control region which is formed between the well region and the low concentration source resistance control region and has an impurity concentration higher than that of the low concentration source resistance control region..
Mitsubishi Electric Corporation

Semiconductor device and integrated inductor

A semiconductor structure includes a first magnetic layer, an insulative oxide layer, an oxygen trapping layer and a cap layer. The insulative oxide layer is over the first magnetic layer.
Taiwan Semiconductor Manufacturing Company Ltd.

Superlattice memory and crosspoint memory device

According to one embodiment, a memory includes a resistance change layer includes a first chalcogenide layer, and a second chalcogenide layer having a composition different from that of the first chalcogenide layer which are stacked alternately, and the resistance change layer having a superlattice structure, and a semiconductor layer of a first conductivity type provided on a one of main surfaces of the resistance change layer.. .
Kabushiki Kaisha Toshiba

Solid-state image sensing device

A solid-state image sensing device capable of suppressing a dark current and transfer failure during a global shutter operation is provided. The solid-state image sensing device according to one embodiment includes: a semiconductor substrate having a main surface and a back surface being on the opposite side of the main surface; a well region arranged in contact with the main surface in the semiconductor substrate; a photoelectric conversion region arranged in contact with the main surface in the well region; a charge holding region arranged in contact with the main surface in the well region; a floating diffusion region arranged in contact with the main surface in the well region; a first transfer gate so formed as to face the well region and the charge holding region; and a second transfer gate so formed as to face the well region..
Renesas Electronics Corporation

Pixel and circuit design for image sensors with hole-based photodiodes

In order to reduce dark current and pixel readout noise in an image sensor, pixels may include a p-type hole-based pinned photodiode. Charge stored in the p-type pinned photodiode may be transferred to a p-type floating diffusion (fd) node and read out by pixel circuitry that uses p-channel metal oxide-semiconductor field-effect transistors (p-channel mosfet).
Semiconductor Components Industries, Llc

Monolithic visible-infrared focal plane array on silicon

A structure includes a silicon substrate; silicon readout circuitry disposed on a first portion of a top surface of the substrate and a radiation detecting pixel disposed on a second portion of the top surface of the substrate. The pixel has a plurality of radiation detectors connected with the readout circuitry.
International Business Machines Corporation

Solid-state imaging device

A solid-state imaging device includes a plurality of photoelectric converting units and a plurality of charge-accumulating units each accumulating a charge generated in the corresponding photoelectric converting unit. The photoelectric converting unit includes a photosensitive region that generates the charge in accordance with light incidence, and an electric potential gradient forming unit that accelerates migration of charge in a second direction in the photosensitive region.
Hamamatsu Photonics K.k.

Image pickup device and manufacturing the same

A p-type well is defined by an isolation region formed in a semiconductor substrate. A pixel region and a ground region are defined in the p-type well.
Renesas Electronics Corporation

Voltage biased metal shielding and deep trench isolation for backside illuminated (bsi) image sensors

A backside illuminated (bsi) image sensor for biased backside deep trench isolation (bdti) and/or biased backside shielding is provided. A photodetector is arranged in a semiconductor substrate, laterally adjacent to a peripheral opening in the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Display device and electronic device including the display device

To provide a display device including a transistor that includes an oxide semiconductor and has favorable characteristics, a pixel electrode electrically connected to the transistor, and a capacitor electrically connected to the pixel electrode. To provide a display device that can be manufactured at low cost.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and electronic device

To provide a semiconductor device capable of retaining data for a long period. The semiconductor device includes a memory circuit and a retention circuit.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device, display device, and electronic appliance

In case the size of the transistor is enlarged, power consumption of the transistor is increased. Thus, the present invention provides a display device capable of preventing a current from flowing to a display element in signal writing operation without varying potentials of power source lines for supplying a current to the display element per row.
Semiconductor Energy Laboratory Co., Ltd.

Pixel structure and fabricating method thereof

A pixel structure includes a scan line, a data line, a bump, an active device, and a pixel electrode electrically connected to the active device. The active device includes a gate, a semiconductor layer, a gate insulation layer between the gate and the semiconductor layer, a source, and a drain.
Au Optronics Corporation

Semiconductor device including a high-electron-mobility transistor (hemt) and manufacturing the same

A semiconductor device comprises a substrate and a high-electron-mobility transistor (hemt). The substrate is formed with a recess.
Taiwan Semiconductor Manufacturing Company Limited

Semiconductor device

Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction..
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing the same

A semiconductor device may include pipe channel layer, and a pipe gate surrounding the pipe channel layer. The semiconductor device may include an oxidization layer formed between the pipe gate and the pipe channel layer.
Sk Hynix Inc.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, and a charge storage film. The stacked body is provided on the substrate.
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing same

A semiconductor memory device according to one embodiment includes a stacked body, a semiconductor pillar and a plurality of charge storage films. The stacked body includes a plurality of electrode films and air gaps.
Kabushiki Kaisha Toshiba

Semiconductor memory device having voids between word lines and a source line

According to an embodiment, a semiconductor memory device includes first and second stacked bodies, first and second memory parts, and an insulating part. The first stacked body includes first conductive layers and first insulating layers alternately arranged in a first direction.
Kabushiki Kaisha Toshiba

Multi-tier replacement memory stack structure integration scheme

A memory opening can be formed through a multiple tier structure. Each tier structure includes an alternating stack of sacrificial material layers and insulating layers.
Sandisk Technologies Inc.

Single poly nonvolatile memory cells, arrays thereof, and methods of operating the same

A single poly nvm cell includes a first n-type well region and a second n-type well region spaced apart from each other by a p-type semiconductor layer, a first active region and a second active region disposed in the first n-type well region and the second n-type well region, respectively, a p-channel floating gate transistor including a floating gate disposed in the first active region, a p-type drain region disposed in the first active region, and a p-type junction region disposed in the first active region, wherein the floating gate extends to over the second active region, a p-channel read selection transistor including a read selection gate electrode disposed in the first active region, the p-type junction region disposed in the first active region, and a p-type source region disposed in the first active region, and an interconnection line connecting the first n-type well region to the p-type source region of the p-channel read selection transistor.. .
Sk Hynix Inc.

Semiconductor device

A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction.
Renesas Electronics Corporation

Memory cell comprising first and second transistors and methods of operating

semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series..
Zeno Semiconductor, Inc.

Single spacer for complementary metal oxide semiconductor process flow

A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed.
International Business Machines Corporation

Semiconductor device

A semiconductor device includes first and second active regions and a field insulating film contacting between the first and second active regions, and a gate electrode structure traversing the first and second active regions and the field insulating film, wherein the gate electrode structure includes a first portion positioned across the first active region and the field insulating film, a second portion positioned across the second active region and the field insulating film, and a third portion contacting the first and second portions. The gate electrode structure includes a gate electrode having an insertion film traversing the first and second active regions and the field insulating film second active region, and a filling film on the insertion film.
Samsung Electronics Co., Ltd.

Semiconductor device and a fabricating the same

A semiconductor device includes first-type-channel field effect transistors (fets) including a first first-type-channel fet including a first gate structure and a second first-type-channel fet including a second gate structure. The first first-type-channel fet has a smaller threshold voltage than the second first-type-channel fet.
Taiwan Semiconductor Manufacturing Co., Ltd.

Fabricating a dual gate stack of a cmos structure

A dual gate cmos structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including sixge1−x where x=0 to 1 and the second semiconductor material including a group iii-v compound material.
International Business Machines Corporation

Iii-v semiconductor cmos finfet device

A method for forming a semiconductor device comprises forming an insulator layer on a semiconductor substrate, removing portions of the insulator layer to form a first cavity and a second cavity, the first cavity exposing a first portion of the semiconductor substrate an the second cavity exposing a second portion of the semiconductor substrate, growing a first semiconductor material in the first cavity and the second cavity. Growing a second semiconductor material on the first semiconductor material in the first cavity and the second cavity, growing a third semiconductor material on the second semiconductor material in the first cavity and the second cavity.
International Business Machines Corporation

Semiconductor integrated circuit

A semiconductor integrated circuit comprises first and second transistors, and a resistive element. The first transistor includes first and second regions of first conductivity type in a first well region of opposite conductivity type, and a first gate electrode on the first well region between the first and second regions.
Kabushiki Kaisha Toshiba

Minimizing shorting between finfet epitaxial regions

The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (finfets). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure.
International Business Machines Corporation

Semiconductor device and a fabricating the same

A semiconductor device includes a first fin field effect transistor (finfet) and a contact bar (source/drain (s/d) contact layer). The first finfet includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first s/d structure.
Taiwan Semiconductor Manufacturing Co., Ltd.

Iii-v fins by aspect ratio trapping and self-aligned etch to remove rough epitaxy surface

A semiconductor device that includes a fin structure of a type iii-v semiconductor material that is substantially free of defects, and has sidewalls that are substantially free of roughness caused by epitaxially growing the type iii-v semiconductor material abutting a dielectric material. The semiconductor device further includes a gate structure present on a channel portion of the fin structure; and a source region and a drain region present on opposing sides of the gate structure..
International Business Machines Corporation

Fin field effect transistor and fabricating the same

Fin field effect transistors (finfets) and method for fabricating the same are disclosed. One of the finfets includes a substrate, an insulator, a first gate, a second gate, an opening and a first dielectric layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

Fin field effect transistor and fabricating the same

Fin field effect transistors (finfets) and method for fabricating the same are disclosed. One of the finfets includes a substrate, an insulator, first and second gates, an opening, first and second dielectric layers.
Taiwan Semiconductor Manufacturing Co., Ltd.

Field effect transistors

A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.. .
Globalfoundries Inc.

Vertical field-effect-transistors having multiple threshold voltages

Various embodiments disclose a method for fabricating a semiconductor structure including a plurality of vertical transistors each having different threshold voltages. In one embodiment the method includes forming a structure having at least a substrate, a source contact layer on the substrate, a first spacer layer on the source contact layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer.
International Business Machines Corporation

Semiconductor device and semiconductor device manufacturing method

To provide a semiconductor device with a high degree of flatness, provided is a semiconductor device including a semiconductor substrate; an element insulating film that is formed on a front surface side of the semiconductor substrate and includes a groove; and a semiconductor element provided in the groove of the element insulating film. The semiconductor device further comprises a withstand voltage structure farther to the outside than the active region, the withstand voltage structure includes a field insulating film formed on the front surface of the semiconductor substrate, and film thickness of a region of the element insulating film where the groove is not provided is the same as film thickness of the field insulating film..
Fuji Electric Co., Ltd.

Protection element, protection circuit, and semiconductor integrated circuit

Provided is the protection element including: a clamp mos transistor that has a drain coupled to a power supply line and a source coupled to a ground line; and a potential increasing circuit that increases a potential of a diffusion layer at the ground line side of the clamp mos transistor, more than a potential of the ground line. In this protection element, the potential of the diffusion layer coupled to the ground line of the clamp mos transistor is increased from the potential of the ground line, whereby an increase in current due to off-state leakage can be reduced while a sufficient drive current is ensured during an esd operation..

Electrostatic discharge (esd) protection device

A semiconductor device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. The semiconductor device also includes a first doping region formed in a portion of at least one portion of the semiconductor substrate separating the pair of first well regions, and a pair of second doping regions, respectively formed in one of the pair of first well regions, having the first conductivity type.
Mediatek Inc.

Method and structure for semiconductor mid-end-of-line (meol) process

A semiconductor device includes a substrate having first and second regions. The first region includes an insulator and the second region includes source, drain, and channel regions of a transistor.
Taiwan Semiconductor Manufacturing Company, Ltd.

Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies.
Micron Technology, Inc.

Power converter monolithically integrating transistors, carrier, and components

A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (tsvs, 110). The chip embedding a high-side (hs) field-effect transistor (fet) interconnected with a low side (ls) fet.
Texas Instruments Incorporated

Semiconductor device and manufacture

A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device and electronic apparatus

For example, a semiconductor device capable of achieving a high performance applicable to an sr motor is provided. The semiconductor device includes a chip mounting portion tab1 on which a semiconductor chip chp1 having an igbt is mounted, and a chip mounting portion tab2 on which a semiconductor chip chp2 having a diode is formed.
Renesas Electronics Corporation

Semiconductor module and stack arrangement of semiconductor modules

A semiconductor module and a stack arrangement of semiconductor modules is proposed. The semiconductor module comprises an insulated gate bipolar transistor, a wide band-gap switch, a base plate, and a press device.
Abb Schweiz Ag

Method of controlling bump height variation

A method of making a semiconductor device includes patterning a photoresist on a substrate to form a plurality of openings in the photoresist. A first opening is near a center of the substrate and has a first width.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices

semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. A method of forming a device includes forming a conductive trace over a first substrate, the conductive trace having first tapering sidewalls, forming a conductive bump over a second substrate, the conductive bump having second tapering sidewalls and a first surface distal the second substrate, and attaching the conductive bump to the conductive trace via a solder region.
Taiwan Semiconductor Manufacturing Company, Ltd.

Method of manufacturing semiconductor device having base and semiconductor element and semiconductor device

In a method of manufacturing a semiconductor device of one embodiment, support members and a film which is formed of a paste containing metal particles and surrounds the support members are provided above a surface of a base. Then a semiconductor element is provided above the support members and the film.
Kabushiki Kaisha Toshiba

Semiconductor device and method

A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor chip, semiconductor package including the same, and manufacturing semiconductor chip

The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (tsv) structures in the pad region.
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The semiconductor device further has a molding compound surrounding the semiconductor substrate, the conductive pad and the conductor.
Taiwan Semiconductor Manufacturing Company Ltd.

Package substrate differential impedance optimization for 25 to 60 gbps and beyond

Package design method for semiconductor chip package for high speed serdes signals for optimization of package differential impedance and reduction of package differential insertion loss and differential return loss at data rates of 25 to 60 gb/s and beyond. The method optimizes parameters of vertical interconnections of bga ball, via, and pth, and around the joint between vertical and horizontal interconnections of traces.
Sarcina Technology Llc

Rf switch on high resistive substrate

A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor substrate having stress-absorbing surface layer

An assembly (101) comprising a semiconductor device (110) with solderable bumps (112); a substrate (120) with a layer (130) of a first insulating compound and an underlying metal layer (140) patterned in contact pads (141) and connecting traces (142), the insulating layer having openings (132) to expose the surface (142a) and sidewalls (142b) of underlying traces; the device bumps soldered onto the contact pads, establishing a gap (150) between device and top insulating layer; and a second insulating compound (160) cohesively filling the gap and the second openings, thereby touching the underlying traces, the second insulating compound having a higher glass transition temperature, a higher modulus, and a lower coefficient of thermal expansion than the first insulating compound.. .
Texas Instruments Incorporated

Package structure and forming the same

A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Packages with interposers and methods for forming the same

A package structure includes an interposer, a die over and bonded to the interposer, and a printed circuit board (pcb) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor package and semiconductor device including an electromagnetic wave shielding member

A semiconductor package includes a semiconductor chip mounted on a substrate. The semiconductor package further includes an electromagnetic wave shielding member.
Samsung Electronics Co., Ltd.

Light emitting device, light emitting device package comprising light emitting device, and light emitting apparatus comprising light emitting device package

A light emitting device according to an embodiment includes a substrate; first to mth light emitting cells (where m is a positive integer of two or more) which are arranged on the substrate so as to be spaced apart from each other; and first to (m−1)th interconnection wires which electrically connect the first to mth light emitting cells in series, wherein an mth light emitting cell (where 1≦m≦m) includes a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, which are sequentially arranged on the substrate, and wherein an nth interconnection wire (where 1≦n≦m−1) interconnects the first conductive type semiconductor of the nth light emitting cell with the second conductive type semiconductor of the (n+1)th light emitting cell, and has a plurality of first branch wires which are spaced apart from each other.. .
Lg Innotek Co., Ltd.

Novel patterning approach for improved via landing profile

The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device structure and forming the same

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and an interconnect structure formed over the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method and structure for forming on-chip anti-fuse with reduced breakdown voltage

A fully depleted field effect transistor (fet) and an anti-fuse structure are provided on a same chip. The fully depleted fet and the anti-fuse structure share a same high dielectric (k) constant dielectric material.
International Business Machines Corporation

Semiconductor devices

A semiconductor device includes a substrate and at least one inductor on the substrate. The inductor includes top portions separated from one another, bottom portions separated from one another, and side portions separated from one other.
Advanced Semiconductor Engineering, Inc.

Method for making semiconductor device with stacked analog components in back end of line (beol) regions

A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member..
Stmicroelectronics, Inc.

Interconnection and manufacturing method thereof

An interconnection and a method for manufacturing thereof are provided. The interconnection includes a first conductive layer, a dielectric layer, a second conductive layer, an insulation layer, and a plurality of air gaps.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

In a semiconductor device, a first end of a first lead frame is connected via solder to a first circuit pattern and another end extends outside from a case. In the same way, a first end of a second lead frame is connected via solder to a third circuit pattern and another end extends outside from a case.
Fuji Electric Co., Ltd.

Wiring substrate and semiconductor device

A wiring substrate includes a core substrate and a cavity extending through the core substrate. The cavity has a planar shape that is rectangular, and includes corners and sides connecting the corners in a plan view.
Shinko Electric Industries Co., Ltd.

Semiconductor package and fabricating the same

A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads.
Siliconware Precision Industries Co., Ltd.

Semiconductor device

A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat dissipation member for dissipating heat from the island portions, a bonding layer bonding the island portions and the heat dissipation member, and a sealing resin covering the semiconductor elements, the island portions and a part of the heat dissipation member. The bonding layer includes mutually spaced individual regions provided for the island portions, respectively..
Rohm Co., Ltd.

Semiconductor device

A semiconductor device includes: a semiconductor substrate through which a via hole is formed from a back surface to a front surface of the semiconductor substrate; an electrode provided on the front surface of the semiconductor substrate and closing the via hole; and a metal film provided on the back surface of the semiconductor substrate, a side wall of the via hole and a lower surface of the electrode, wherein an opening is provided in the metal film on the back surface of the semiconductor substrate, and the opening abuts on only part of a circumference of the via hole.. .
Mitsubishi Electric Corporation

Thermoelectric cooling packages and thermal management methods thereof

A method for managing a temperature of a device includes determining a temperature of a circuit or a package including the circuit, and selectively operating a thermoelectric semiconductor based on the determined temperature to adjust the temperature of the circuit or the package.. .

Semiconductor device with interconnect structure having catalys layer

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor structure and fabrication method thereof

The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary semiconductor structure includes an insulation material layer having a top semiconductor layer having transistor regions formed on a top surface of the insulation material layer; isolation structures formed in the top semiconductor layer between adjacent transistor regions; a first dielectric layer formed over the top semiconductor layer; a first heat-conducting layer having a thermal conductivity higher than a thermal conductivity of the isolation structure and passing through the insulation material layer, the top semiconductor layer and the first dielectric layer; a second dielectric layer formed over the first dielectric layer; an interconnect structure formed in the second dielectric layer; and a bottom layer conductive via passing through the heat-conducting layer and a partial thickness of the second dielectric layer, and electrically connected with the interconnect structure..
Semiconductor Manufacturing International (beijing) Corporation

Fabrication semiconductor package

A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible ctes..
Siliconware Precision Industries Co., Ltd.

Corrosion resistant chip sidewall connection with crackstop and hermetic seal

The present disclosure relates to semiconductor structures and, more particularly, to corrosion resistant chip sidewall connections with crackstop structures with a hermetic seal, and methods of manufacture. The structure includes: a guard ring structure surrounding an active region of an integrated circuit chip; an opening formed in the guard ring structure; and a hermetic seal encapsulating the opening and a portion of the guard ring structure, the hermetic seal being structured to prevent moisture ingress to the active region of the integrated circuit chip through the opening..
Globalfoundries Inc.

Cover lid with selective and edge metallization

A cover lid for use with a semiconductor package is disclosed. First, a polyamide mask is applied to one surface of the lid plate.
Materion Corporation

Ceramic combo lid with selective and edge metallizations

A frame lid for use with a semiconductor package is disclosed. First, a mask is applied to a top surface of the lid and over a central area of the top surface to define a peripheral area.
Materion Corporation

Semiconductor device with bond pad wiring lead-out arrangement avoiding bond pad probe mark area

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip.
Renesas Electronics Corporation

Assessment method, and semiconductor device manufacturing method

Assessing the feedback capacitance based on the first characteristic and the second characteristic. The first characteristic may be a characteristic that corresponds to a withstanding voltage of the semiconductor element, and the second characteristic may be an on-resistance of the semiconductor element.

Method of manufacturing semiconductor device having semiconductor chip mounted on lead frame

A semiconductor device uses a lead frame, in which an outer lead is electrically connected to an inner lead suspension lead via an inner lead. An encapsulating resin covers the inner lead and part of the outer lead, and a plated film is formed on an outer lead cut surface so that a solder layer is easily formed on all surfaces of the outer lead extending from the encapsulating resin.
Sii Semiconductor Corporation

Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture

Architectures and techniques for co-integration of heterogeneous materials, such as group iii-v semiconductor materials and group iv semiconductors (e.g., ge) on a same substrate (e.g. Silicon).
Intel Corporation

Fabricating a dual gate stack of a cmos structure

A dual gate cmos structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including sixge1-x where x=0 to 1 and the second semiconductor material including a group iii-v compound material.
International Business Machines Corporation

Fin profile improvement for high performance transistor

A finfet semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first fin formed in a first semiconducting layer, a second fin formed in a second semiconducting layer, and an insulating layer disposed between the first fin and the second fin.
Taiwan Semiconductor Manufacturing Company, Ltd.

Single spacer for complementary metal oxide semiconductor process flow

A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed.
International Business Machines Corporation

Self-aligned nanowire formation using double patterning

A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface.
Taiwan Semiconductor Manufacturing Company,ltd

Methods for forming fin field-effect transistors

A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching.
Taiwan Semiconductor Manufacturing Company, Ltd.

Method for forming a semiconductor structure containing high mobility semiconductor channel materials

A method of forming a semiconductor structure is provided. The method includes providing a substrate comprising, from bottom to top, a handle substrate, an insulator layer and a germanium-containing layer.
International Business Machines Corporation

Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices

semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a trench in a substrate, the trench being formed within a first side of the substrate and disposed around a portion of the substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor structure with resist protective oxide on isolation structure and manufacturing the same

A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.. .
Taiwan Semiconductor Manufacturing Co., Ltd.

Method of forming trenches

A method of forming a semiconductor device fabrication is described that includes forming a material layer over a substrate, forming a first trench in the material layer, forming a first dielectric capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer disposed along sidewalls of the first trench, forming a second dielectric capping layer along sidewalls of the second trench and along the sidewalls of the first trench and forming a conductive feature within the second trench and the first trench.. .
Taiwan Semiconductor Manufacturing Company, Ltd.

Method of forming shallow trench isolation (sti) structures

A method of forming a trench isolation (e.g., an sti) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.. .
Microchip Technology Incorporated

Method of manufacturing semiconductor integrated circuit device

The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset sti insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.. .

Temperature sensing system for rotatable wafer support assembly

A semiconductor processing apparatus includes a wafer support assembly, a temperature sensor integrated in the wafer support assembly for measuring a temperature of the wafer support assembly, and a signal transmission device that wirelessly transmits a signal relating to a temperature measurement obtained by the temperature sensor to an external control module.. .
Watlow Electric Manufacturing Company

Producing power-module substrate

To prevent braze stain and improve solder bondability of a semiconductor chip without deteriorating bondability between a metal plate and a ceramic substrate: a producing method of a power-module substrate by braze-bonding a metal plate which is blanked by press working on a metal raw-plate on one surface of a ceramic substrate: in the metal plate, a height of burrs is 0.021 mm or smaller, a thickness of a fracture surface is 0.068 mm or larger; the metal plate is stacked on the ceramic substrate so as to stack a surface thereof on a side at which the burrs are generated is in contact with the one surface of the ceramic substrate and brazed.. .
Mitsubishi Materials Corporation

Nitrogen-containing compounds for etching semiconductor structures

A method for etching silicon-containing films is disclosed. The method includes the steps of introducing a vapor of a nitrogen containing etching compound into a reaction chamber containing a silicon-containing film on a substrate, wherein the nitrogen containing etching compound is an organofluorine compound containing at least one c≡n or c═n functional group; introducing an inert gas into the reaction chamber; and activating a plasma to produce an activated nitrogen containing etching compound capable of etching the silicon-containing film from the substrate..
American Air Liquide, Inc.

Atomic layer etching 3d structures: si and sige and ge smoothness on horizontal and vertical surfaces

Methods and apparatuses for etching semiconductor material on substrates using atomic layer etching by chemisorption, by deposition, or by both chemisorption and deposition mechanisms in combination with oxide passivation are described herein. Methods involving atomic layer etching using a chemisorption mechanism involve exposing the semiconductor material to chlorine to chemisorb chlorine onto the substrate surface and exposing the modified surface to argon to remove the modified surface.
Lam Research Corporation

Method of plasma etching and fabricating semiconductor device using the same

Disclosed are a method of plasma etching and a method of fabricating a semiconductor device including the same. The method of plasma etching includes loading a substrate including an etch target onto a first electrode in a chamber, the chamber including the first electrode and a second electrode arranged to face each other, and etching the target.
Samsung Electronics Co., Ltd.

Fin profile improvement for high performance transistor

A finfet semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first fin formed in a first semiconducting layer, a second fin formed in a second semiconductor layer, and an insulating layer disposed between the first fin and the second fin.
Taiwan Semiconductor Manufacturing Co., Ltd.

Flow distribution plate for surface fluorine reduction

A method and apparatus for processing a semiconductor substrate are described herein. A process system described herein includes a plasma source and a flow distribution plate.
Applied Materials, Inc.

Silicon carbide semiconductor device and manufacturing same

The second side wall portion has one end and the other end, the one end being connected to the second bottom portion of the second insulating film, the other end being located on one of the first and second regions, the other end being separated from the third region.. .

Strain relaxed buffer layers with virtually defect free regions

A strain relaxed buffer layer of a second semiconductor material and of a second lattice constant and containing misfit dislocation defects and threading dislocation defects is formed atop a surface of a first semiconductor material of a first lattice constant that differs from the second lattice constant. The surface of the first semiconductor material includes at least one recessed region and adjoining non-recessed regions.
International Business Machines Corporation

Semiconductor chip carriers with monolithically integrated quantum dot devices and manufacture thereof

A three-dimensional polycrystalline semiconductor material provides a major ingredient forming individual crystalline grains having a nominal maximum grain diameter less than or equal to 50 nm, and a minor ingredient forming boundaries between the individual crystalline grains.. .

Methods and systems to enhance process uniformity

A semiconductor processing chamber may include a remote plasma region, and a processing region fluidly coupled with the remote plasma region. The processing region may be configured to house a substrate on a support pedestal.
Applied Materials, Inc.

Semiconductor processing systems having multiple plasma configurations

An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access.
Applied Materials, Inc.

Board, semiconductor fabrication plant (fab) and fabrication facility

A board includes a first magnetic conductive plate and a second magnetic conductive plate. The first magnetic conductive plate has a first magnetic conductive direction.
Taiwan Semiconductor Manufacturing Co., Ltd.

Disconnecting device for galvanic direct current interruption

A disconnecting device for interrupting a direct current between a direct current source and an electric apparatus, having a current-conducting mechanical switch, a power electronics unit connected thereto, and an energy store which is charged by an arcing voltage generated on the switch by an arc as the switch is being disconnected. A pulse generator that is connected to the energy store triggers at least one semiconductor switch of the power electronics unit in such a way that the power electronics unit short-circuits the switch and the arc is extinguished..
Ellenberger & Poensgen Gmbh

A blank suitable for use as a body of a supercapacitor, a supercapacitor, and a manufacturing a porous silicon volume

A blank suitable for use as a body of a supercapacitor comprises a first porous semiconductor volume and a second porous semiconductor volume, the second porous semiconductor volume laterally surrounded by the first porous semiconductor volume and separated from it by a trench that is suitable for receiving an electrolyte, whereby the first and second porous semiconductor volume comprise channels opening to the trench. A supercapacitor comprises a body formed by using the blank according to any one of the preceding claims, so that the first porous semiconductor volume acts as one electrode and the second porous semiconductor volume acts as another electrode, with an electrolyte in the trench..
Teknologian Tutkimuskeskus Vtt Oy

Thin film production

The present invention relates to a process for producing a layer of a crystalline material, which process comprises disposing on a substrate: a first precursor compound comprising a first cation and a sacrificial anion, which first cation is a metal or metalloid cation and which sacrificial anion comprises two or more atoms; and a second precursor compound comprising a second anion and a second cation, which second cation can together with the sacrificial anion form a first volatile compound. The invention also relates to a layer of a crystalline material obtainable by a process according to the invention.
Oxford University Innovation Limited

Semiconductor ceramic composition and ptc thermistor

A semiconductor ceramic composition which is a batio3 based semiconductor ceramic composition, wherein, part of ba is replaced by at least a (at least one alkali metal element selected from na and k), bi and re (at least one element selected from rare earth elements including y), and part of ti is replaced by at least tm (at least one element selected from the group including of v, nb and ta), the relationships of 0.7≦{(the content of bi)/(the content of a)}≦1.43, 0.017≦{(the content of bi)+(the content of a)}≦0.25, and 0<{(the content of re)+(the content of tm)}≦0.01 are satisfied when the total content of ti and tm is set as 1 mol, the grain sizes have a maximum peak in a grain size distribution in a range of 1.1 μm to 4.0 μm or less, and the distribution frequency of the peak is 20% or more.. .
Tdk Corporation

Semiconductor memory device and operating method thereof

There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and one or more programs.
Sk Hynix Inc.

Nand flash memory having multiple cell substrates

A nand flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where nand cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage.
Conversant Intellectual Property Management Inc.

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation or erase operation of the memory cell array, and a control logic controlling the peripheral circuit. The control logic controls the peripheral circuit such that a first program allowable voltage applied to bit lines of the memory cell array during a first program operation of the program operation and a second program allowable voltage applied during a second program operation of the program operation are different from each other..
Sk Hynix Inc.

Semiconductor memory device, erasing method and programing method thereof

A semiconductor memory device, an erasing method and a programming method thereof which can improve yields and utilization efficiency of a memory array are provided. The semiconductor memory device includes a memory array, which includes a plurality of nand strings; a page buffer/sensing circuit (170), which is connected to the nand strings of the memory array through bit lines and outputs whether the nand strings include failures; and a detecting circuit (200), which is connected to the plurality of page buffer/sensing circuits (170) and detects a number of the failures among the nand strings of a selected block.
Winbond Electronics Corp.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors.
Kabushiki Kaisha Toshiba

A semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and operating

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.. .
Zeno Semiconductor, Inc.

Semiconductor storage device, and storage device using same

In a semiconductor recording device, a writing time as long as in the case where the number of bits to be subjected to ‘0’ writing is large even in the case where the number of bits to be subjected to ‘0’ writing in page writing is small. A population counter that controls the number of ‘0’ bits is provided.
Hitach, Ltd.

3d memory device and structure

A semiconductor device including: a first memory cell including a first transistor; and a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor is self-aligned to the first transistor, where access to the first memory cell is controlled by at least one junction-less transistor, and where the junction-less transistor is not part of the first memory cell and the second memory cell.. .
Monolithic 3d Inc.

Semiconductor device

Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command: and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle, to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups..
Micron Technology, Inc.

Refresh verification circuit, semiconductor apparatus and semiconductor system

A refresh verification circuit may include a filtering circuit configured to receive a refresh pulse and to generate a filtering pulse in response to a duration of the enable period of the refresh pulse.. .
Sk Hynix Inc.

Semiconductor device and electronic appliance

The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output.
Semiconductor Energy Laboratory Co., Ltd.

Scan driving circuit and nand logic operation circuit thereof

The invention provides a scan driving circuit for an oxide semiconductor thin film transistor and a nand logic operation circuit thereof. The nand logic operation circuit includes: a first inverter and a second inverter applied to a pull-down holding circuit of a goa circuit, and multiple transistors.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Semiconductor integrated circuit, self-luminous display panel module, electronic apparatus, and method, for driving power supply line

A semiconductor integrated circuit and corresponding display panel and electronic apparatus. A pixel element includes a self-luminous element and a drive transistor connected to a power supply line.
Sony Corporation



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