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Semiconductor patents

      

This page is updated frequently with new Semiconductor-related patent applications.




new patent Semiconductor packages and display devices including the same
Provided are a semiconductor package and a display device including the same. In some aspects, the semiconductor package may include a film substrate including a base film including cavities and a wiring layer on the base film, a semiconductor chip connected to the wiring layer and mounted on a surface of the base film, and passive devices accommodated in the cavities of the base film and electrically connected to the semiconductor chip through the wiring layer.
Samsung Electronics Co., Ltd.


new patent Semiconductor integrated circuit device, printed board and manufacturing the semiconductor integrated circuit device
A semiconductor integrated circuit device includes a component built-in board in which at least a first core layer on which a first electronic component is mounted, a second core layer on which a second electronic component is mounted, an adhesive layer arranged between the first core layer and the second core layer, and wiring layers are stacked; a third electronic component mounted in a first core layer side of the component built-in board and electrically connected to the at least one of the first and second electronic components through the wiring layers; and an external connection terminal formed in a second core layer side of the component built-in board and electrically connected to at least one of the first and second electronic components.. .
Renesas Electronics Corporation


new patent Semiconductor device, video display system, and processing signal
A semiconductor device includes a first input unit for receiving a first signal; a first processing unit configured to perform a frequency dispersion processing on the first signal; a first output unit configured to output the first signal or the first signal on which the first processing unit performs the frequency dispersion processing; a second input unit configured to receive a second signal generated through performing a predetermined image processing with an image processing unit on the first signal output from the first output unit; a second processing unit configured to perform the frequency dispersion processing on the second signal; an enable signal input unit configured to receive an enable signal; and a second output unit configured to output one of the first signal and the second signal as an output signal according to the enable signal.. .
Lapis Semiconductor Co., Ltd.


new patent Semiconductor device, radio communication device, and control radio communication device
A semiconductor device includes a receiving unit that receives a radio signal, which includes a quadrature conversion circuit and an analog-to-digital converter, a received signal strength measurement unit, a threshold comparison unit, a demodulation unit, and a threshold setting unit. The analog-to-digital converter converts a received radio signal from the quadrature conversion circuit to a received signal.
Renesas Electronics Corporation


new patent Memory controller, semiconductor memory system and operating method thereof
An operation method of a memory controller includes: reading a second data from memory cells when a hard decision error correction decoding operation based on a first data read from the memory cells fails; calculating a llr of each bit-data included in the first data by using the first and second data; and performing a soft decision error correction decoding operation based on the llr, wherein the memory cells include a first and second memory cell, wherein the first data includes first-bit-data read from the first and second memory cell, wherein the second data includes second-bit-data read from the first and second memory cell, wherein the llr is a llr of the first-bit-data read from the first memory cell calculated based on the first bit and a second bit read from the first memory cell and a first bit and a second bit read from the second memory cell.. .
Korea Advanced Institute Of Science And Technology


new patent Semiconductor switching string
A semiconductor switching string including a series-connected switching assemblies. Each assembly has a main switching element including first and second connection terminals which current flows between when the main switching element is on.
General Electric Technology Gmbh


new patent Switching device for operating at least one load
Switching device (1) for operating at least one load, comprising at least one switching unit (7; 8; 9), which switches a tapped current phase (l) to a load (2-1; 2-2; 2-3) connectable to the switching unit (7; 8; 9) to supply said load with current and which has a measurement unit (7c; 8c; 9c) which measures a current phase progression of the at least one current phase (l); a local control unit (18), which after receiving a control command from an external control system (24) actuates a semiconductor switch (7b; 8b; 9b) of the switching unit (7; 8; 9) in such a way that the semiconductor switch (7b; 8b; 9b) switches at a zero of the current phase (l) measured by the measurement unit (7c; 8c; 9c), and a local monitoring unit (20), which evaluates the current phase progression, measured by the measurement unit (7c; 8c; 9c), of the at least one current phase (l) to detect an operational deviation from a normal current supply to the associated load (2-1; 2-2; 2-3) connected to the switching unit (7; 8; 9), and reports any detected operational deviation.. .
Woehner Gmbh & Co. Kg Elektrotechnische Systeme


new patent Drive circuit and semiconductor device
A drive circuit includes one constant voltage circuit for generating a first voltage and a second voltage, a first output circuit connected to the constant voltage circuit to receive the first voltage and the second voltage and receive a gate drive signal, a second output circuit connected to the constant voltage circuit to receive the first voltage and the second voltage and receive the gate drive signal, a first terminal connected to an output of the first output circuit, and a second terminal connected to an output of the second output circuit, wherein a voltage generated by the constant voltage circuit is applied to a plurality of semiconductor switching elements connected in parallel during switching.. .
Mitsubishi Electric Corporation


new patent Method and system for reliable bootstrapping switches
Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (mos) transistor having a pull-down path coupled to a gate terminal of the switching mos transistor, wherein: source terminals of both a diode-connected transistor and a second mos transistor are coupled to the gate terminal of the switching mos transistor; drain terminals of both the diode-connected transistor and the second mos transistor are coupled to a source terminal of a third mos transistor, the third mos transistor coupled in series with a fourth mos transistor; and a drain terminal of the fourth mos transistor is coupled to ground. The third and fourth mos transistors may be in series with the second mos transistor.
Maxlinear, Inc.


new patent Semiconductor power module and drive system for electric motor
Erroneous mounting of a semiconductor power module can be more easily detected. A semiconductor power module (9) according to the present invention includes: a status signal generation unit (90) configured to detect a status in the semiconductor power module (9) and generate and output a status signal indicating the detected status; an identification information storage unit (91) configured to preliminarily store identification information for identifying the semiconductor power module (9) and output an identification signal indicating the identification information; and a switching unit (92) configured to select one of the status signal output from the status signal generation unit (90) and the identification signal output from the identification information storage unit (91) and output the selected signal to an outside of the semiconductor power module (9)..
Renesas Electronics Corporation


new patent

Method for operating an electrical machine and electrical machine

A method for operating an electric machine with a power source, an electric motor, and an intermediary power converter, in which an input current of the power source is converted to a multi-phase output current for the electric motor by a pulse width modulated control of a number of semiconductor switches of the converter, wherein the or each pulse is generated at a first point in time and terminated after a pulse duration at a second point in time, in which for each alternating current component, which is generated in the course of the pulse-width-modulated driving of the semiconductor switches in an intermediate circuit of the power source, a frequency spectrum is determined, and in which the pulse durations of the pulses of the pulse width modulated control can be set such that the sum of the frequency spectra of the alternating current components is minimal.. .
Brose Fahrzeugteile Gmbh & Co. Kommanditgesellschaft, Wuerzburg

new patent

Power converter

Provided is a power converter which is applied to a power converter equipped with a switching element provided on a line, and a radiator connected to a predetermined potential such as a ground potential. A noise eliminator in which a conductive member is covered with insulator is provided between the switching element (semiconductor switch) and the radiator (heatsink).
Omron Corporation

new patent

Hexagonal semiconductor package structure

Coil structures and methods of forming are provided. The coil structure includes a substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Power module

When a short-circuit failure has occurred in a power semiconductor device provided in a power module, a radical and rapid temperature increase is prevented by instantly interrupting a short-circuit current. A power module 10 has a package 10a.
Shindengen Electric Manufacturing Co., Ltd.

new patent

Semiconductor apparatus

A semiconductor apparatus is provided, comprising: a power semiconductor element which is connected between a first terminal on a high-potential side and a second terminal on a low-potential side; a first gate control section which controls a gate potential of the power semiconductor element according to a control signal; a discharge circuit which is discharges charges that are charged by the gate of the power semiconductor element; a second gate control section which controls the gate potential of the power semiconductor element according to a collector current of the power semiconductor element; a feedback section which feedbacks the charges to the gate of the power semiconductor element according to the collector potential of the power semiconductor element; and a current cutting off section which cuts off currents flowing from the first terminal to the gate of the power semiconductor element according to the control signal.. .
Fuji Electric Co., Ltd.

new patent

Light emitting element array and optical transmission device

A light emitting element array includes plural semiconductor stacking structures and a light screening portion. The plural semiconductor stacking structures each include a light emitting portion and a light receiving portion that receives light propagated in a lateral direction via a semiconductor layer from the light emitting portion.
Fuji Xerox Co., Ltd.

new patent

Integrated quantum cascade laser, semiconductor optical apparatus

An integrated quantum cascade laser includes: a laser structure including first to third regions arranged in a direction of a first axis, the laser structure including a substrate and a laminate including a core layer; first and second metal layers disposed on the third region; the third and fourth metal layers disposed on the first region; first to fourth bump electrodes disposed on the first to fourth metal layers, respectively; first and second semiconductor mesas provided in the first region, each of the first and second semiconductor mesas including the core layer; and a distribute bragg reflector provided in the second region, the distribute bragg reflector having one or more semiconductor walls. The first and second metal layers are electrically connected to the first and second semiconductor mesas, respectively.
Sumitomo Electric Industries, Ltd.

new patent

Semiconductor light emitting device

According to one embodiment, a semiconductor light emitting device includes a substrate, a semiconductor light emitting structure including an active layer, a first light reflecting structure disposed between the substrate and the semiconductor light emitting structure, a second light reflecting structure disposed on an upper side of the semiconductor light emitting structure and a pair of electrodes applying a current to the semiconductor light emitting structure. At least one of the first and second light reflecting structures is a multilayer reflective film including a plurality of structure layers, each structure layer including a high refractive index region and a low refractive index region which are disposed such that a refractive index of the structure layer is periodically changed, and a low refractive index layer disposed between two adjacent structure layers..
Kabushiki Kaisha Toshiba

new patent

Quantum cascade laser with angled active region and related methods

A qcl may include a substrate, an emitting facet, and semiconductor layers adjacent the substrate and defining an active region. The active region may have a longitudinal axis canted at an oblique angle to the emitting facet of the substrate.
University Of Central Florida Research Foundation, Inc.

new patent

Method to tune emission wavelength of wavelength tunable laser apparatus and laser apparatus

A method to tune an emission wavelength of a wavelength tunable laser apparatus is disclosed. The laser apparatus implements, in addition to a wavelength tunable laser diode (t-ld) integrating with a semiconductor optical amplifier (soa), a wavelength monitor including an etalon filter.
Sumitomo Electric Device Innovations, Inc.

new patent

Semiconductor optical device, optical module, and manufacturing semiconductor optical device

A semiconductor optical device includes: a first conductive type semiconductor layer; an active layer; a second conductive type semiconductor layer including a ridge portion; a pair of first grooves, formed on bottom surfaces of both sides of the ridge portion and dividing the active layer; an optical functioning part including the first and second conductive type semiconductor layers, converting a state of light, and having a height higher than a height of the bottom surface of the ridge portion; and a second groove, at least a part thereof being formed on the optical functioning part, an end portion thereof being connected to the first groove, the second conductive type semiconductor layer being divided, and the maximum height of an inner wall surface thereof being higher than the maximum height of an inner wall surface of the first groove.. .
Oclaro Japan, Inc.

new patent

Vcsel structure with embedded heat sink

An optoelectronic device includes a semiconductor substrate, having front and back sides and having at least one cavity extending from the back side through the semiconductor substrate into proximity with the front side. At least one optoelectronic emitter is formed on the front side of the semiconductor substrate in proximity with the at least one cavity.
Apple Inc.

new patent

Edge-emitting semiconductor laser and the production thereof

An edge-emitting semiconductor laser includes a semiconductor structure laterally bounded by first and second facets and having a central section and a first edge section, a layer sequence offset relative to the central section in the growth direction in the first edge section such that, in the first edge section, one of the cladding layers or one of the waveguide layers is arranged in the growth direction at a height of the active layer in the central section, the layer sequence includes an epitaxially grown additional layer arranged between the upper side and the lower cladding layer, the additional layer is not arranged between the upper side and the lower cladding layer in the central section, and the additional layer is electrically insulating or has doping with the opposite sign to the lower cladding layer.. .
Osram Opto Semiconductors Gmbh

new patent

Ruby laser pumped ultrashort pulse laser

An apparatus and method are provided for producing an ultrashort pulsed output beam. A 694 nm pump beam from a first gan semiconductor laser diode pumped, q-switched ruby laser is directed into at least one amplifier that includes a broadband gain element doped with trivalent chromium ions (cr3+).
Wfk Lasers, Llc.

new patent

Oled with a flattening layer between two barrier layers

According to one embodiment, an organic semiconductor device includes a supporting substrate, a plurality of organic el light emitting elements, a first barrier layer, a flattening layer, and a second barrier layer. The flattening layer exists sporadically and makes gentle in inclination steep elevation change present in the surface of the first barrier layer.
Japan Display Inc.

new patent

Electrode contacts

A device structure providing contact to conductive layers via a deep trench structure is disclosed. The device includes a first dielectric layer including a first opening.
Ignis Innovation Inc.

new patent

Separation method, light-emitting device, module, and electronic device

A method for manufacturing a flexible semiconductor device is disclosed. The method includes: forming a separation layer of a metal over a substrate; treating the separation layer with plasma under an atmosphere containing nitrogen, oxygen, silicon, and hydrogen; forming a layer over the plasma-treated separation layer, the layer being capable of supplying hydrogen and nitrogen to the separation layer; forming a functional layer over the separation layer; performing heat treatment to promote the release of hydrogen and nitrogen from the layer; and separating the substrate at the separation layer.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Hall effect device

A hall effect device includes an active hall region in a semiconductor substrate, and at least four terminal structures, each terminal structure including a switchable supply contact element and a sense contact element, wherein each supply contact element includes a transistor element with a first transistor terminal, a second transistor terminal, and a control terminal, wherein the second transistor terminal contacts the active hall region or extends in the active hall region; and wherein the sense contact elements are arranged in the active hall region and neighboring to the switchable supply contact elements.. .
Infineon Technologies Ag

new patent

Semiconductor package

Provided is a magnetic shield having improved shielding properties from an external magnetic field. A magnetic shield ms1 has in-plane magnetization as remanent magnetization, and is adapted to generate a perpendicular component in the magnetization direction by applying a magnetic field in the perpendicular direction to the magnetic shield..
Renesas Electronics Corporation

new patent

Light emitting element with light transmissive substrate having recess in cross-sectional plane

A light-emitting element includes a light transmissive substrate, a semiconductor layered body, and first and second light reflecting members. The semiconductor layered body is formed on a first main surface of the light transmissive substrate.
Nichia Corporation

new patent

Method of fabricating light emitting device package

A method of fabricating a light emitting device package includes forming a plurality of semiconductor light emitting parts, each having a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on a growth substrate, forming a partition structure having a plurality of light emitting windows on the growth substrate, filling each of the plurality of light emitting windows with a resin having a phosphor, and forming a plurality of wavelength conversion parts by planarizing a surface of the resin.. .
Samsung Electronics Co., Ltd.

new patent

Cadmium-free quantum dot nanoparticles

Quantum dot semiconductor nanoparticle compositions that incorporate ions such as zinc, aluminum, calcium, or magnesium into the quantum dot core have been found to be more stable to ostwald ripening. A core-shell quantum dot may have a core of a semiconductor material that includes indium, magnesium, and phosphorus ions.
Nanoco Technologies Ltd.

new patent

Semiconductor light-emitting element and manufacturing the same

A transparent electrode is made of a first transparent electrode and a second transparent electrode containing a metal atom whose concentration is 10 wt % or less. The first transparent electrode is provided in a region which is overlapped with a p-side pad electrode when seen in a plane view, and the second transparent electrode is provided in a region except for the region which is overlapped with the p-side pad electrode when seen in the plane view.
Renesas Electronics Corporation

new patent

Light engine array

The invention discloses a light engine array having at least an anode and a cathode comprising: a first type semiconductor layer; an active layer; and a second type semiconductor layer; a cathode electrode has a conductive metal layer in electrical contact with a portion of the first type semiconductor layer, and the second type semiconductor layer to form a short circuit structure in a common cathode region; and an anode electrode has the conductive metal layer and coupled to a portion of the first type semiconductor layer; wherein, the anode electrode is electrically isolated with the active layer and the second type semiconductor layer in a sub-pixel region.. .
Hiphoton Co., Ltd

new patent

Protective capping layer for spalled gallium nitride

A method of producing a semiconductor device includes forming a stack including a semiconductor material having a group iii nitride semiconductor material formed on a growth substrate, a protective layer formed over the group iii nitride semiconductor material, and a handle layer and a stressor layer formed over the protective layer. The stack is spalled to separate the growth substrate from the stack..
International Business Machines Corporation

new patent

Nitride semiconductor element and manufacturing the same

A nitride semiconductor element includes a sapphire substrate including: a main surface extending in a c-plane of the sapphire substrate, and a plurality of projections disposed at the main surface, the plurality of projections including at least one projection having an elongated shape in a plan view; and a nitride semiconductor layer disposed on the main surface of the sapphire substrate. The at least one projection has an outer edge extending in a longitudinal direction of the elongated shape, the outer edge extending in a direction oriented at an angle in a range of −10° to +10° with respect to an a-plane of the sapphire substrate in the plan view..
Nichia Corporation

new patent

Semiconductor device including oxide current aperture

A method for fabricating a semiconductor device includes generating a wafer by generating an n-type semiconductor layer and an active region on the n-type semiconductor layer. The n-type semiconductor layer is located on a first side of the active layer.
X Development Llc

new patent

Light emitting device and manufacturing method therefor

A light emitting device and a manufacturing method therefor are disclosed. The light emitting device comprises: a patterned sapphire substrate (pss) including a plurality of concave parts and protruding parts on the upper surface thereof; a buffer layer including a concave part buffer layer, which is positioned on the concave part, and a protruding part buffer layer, which is positioned on the side surface of the protruding part and dispersed and arranged in a plurality of island shapes; a lower nitride layer positioned on the buffer layer and the pss and covering the protruding part; a void positioned on an interface between the side surface of the protruding part and the lower nitride layer; a first conductive type semiconductor layer positioned on the lower nitride layer; a second conductive type semiconductor layer positioned on the first conductive type semiconductor layer; and an active layer interposed between the first and second conductive type semiconductor layers..
Seoul Viosys Co., Ltd.

new patent

Patterned layer design for group iii nitride layer growth

A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group iii nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings.
Sensor Electronic Technology, Inc.

new patent

Nitride semiconductor structure and semiconductor light emitting device including the same

A nitride semiconductor structure and a semiconductor light emitting device are revealed. The semiconductor light emitting device includes a substrate disposed with a first type doped semiconductor layer and a second type doped semiconductor layer.
Genesis Photonics Inc.

new patent

Light-emitting device and light unit comprising same

The light emitting device disclosed includes a first conductive semiconductor layer; an active layer that is disposed on a first conductive semiconductor layer and generates ultraviolet wavelength; an electron blocking layer that is disposed on the active layer; a second conductive semiconductor layer that is disposed on the electron blocking layer; a third conductive semiconductor layer that is disposed on the second conductive semiconductor layer; and an electrode that is disposed on the third conductive semiconductor layer, in which the second and third conductive semiconductor layers include an algan semiconductor, and in which the third conductive semiconductor layer has a lower aluminum composition than that of the second conductive semiconductor layer and has an electrical contact resistance with the electrode that is lower than that of the second conductive semiconductor layer.. .

new patent

Micro-light-emitting diode device

A micro-light-emitting diode device includes a first semiconductor layer, an active layer, and a second semiconductor layer. The first semiconductor layer has a first bottom surface.
Au Optronics Corporation

new patent

Method of manufacturing a semiconductor device

Provided is a method of manufacturing a semiconductor device having a photodiode that has a shallow p-n junction and thus achieves high sensitivity to an ultraviolet ray, in which an oxide containing impurities at high concentration is deposited on the surface of the silicon substrate, and thereafter a diffusion region is formed to have a shallow junction by performing thermal diffusion of a rapid temperature change, with the use of a high-speed temperature rising and falling apparatus without using ion implantation into the silicon substrate.. .
Sii Semiconductor Corporation

new patent

Back-illuminated sensor with boron layer

An inspection system including an optical system (optics) to direct light from an illumination source to a sample, and to direct light reflected/scattered from the sample to one or more image sensors. At least one image sensor of the system is formed on a semiconductor membrane including an epitaxial layer having opposing surfaces, with circuit elements formed on one surface of the epitaxial layer, and a pure boron layer on the other surface of the epitaxial layer.
Kla-tencor Corporation

new patent

Power semiconductor element and power semiconductor module using same

In a schottky barrier diode comprising silicon carbide: an active region includes a first semiconductor region of a first conductivity type configuring a first schottky junction having a plurality of linear patterns between a first electrode and the first semiconductor region and a second semiconductor region of a second conductivity type adjacent to the first schottky junction and connected to the first electrode; at the border of the active region and a periphery region, a second schottky junction comprising the first electrode and the first semiconductor region and having at least one annular pattern surrounding the linear patterns is provided and the second semiconductor region is adjacent to the second schottky junction and is connected to the first electrode; and the first and second schottky junctions are conductive parts and the second semiconductor region is a nonconductive part in a forward bias state.. .
Hitachi, Ltd.

new patent

Bidirectional zener diode

A bidirectional zener diode of the present invention includes a semiconductor substrate of a first conductivity type, a first electrode and a second electrode which are defined on the semiconductor substrate, and a plurality of diffusion regions of a second conductivity type, which are defined at intervals from one another on a surface portion of the semiconductor substrate, to define p-n junctions with the semiconductor substrate, and the plurality of diffusion regions include diode regions which are electrically connected to the first electrode and the second electrode, and pseudo-diode regions which are electrically isolated from the first electrode and the second electrode.. .
Rohm Co., Ltd.

new patent

Nanosheet and nanowire mosfet with sharp source/drain junction

A semiconductor device that includes a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer includes a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of at least two suspended channel structures.
International Business Machines Corporation

new patent

Semiconductor device

It is an object to provide a semiconductor device typified by a display device having a favorable display quality, in which parasitic resistance generated in a connection portion between a semiconductor layer and an electrode is suppressed and an adverse effect such as voltage drop, a defect in signal wiring to a pixel, a defect in grayscale, and the like due to wiring resistance are prevented. In order to achieve the above object, a semiconductor device according to the present invention may have a structure where a wiring with low resistance is connected to a thin film transistor in which a source electrode and a drain electrode that include metal with high oxygen affinity are connected to an oxide semiconductor layer with a suppressed impurity concentration.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Method for manufacturing semiconductor device and manufacturing apparatus of semiconductor device

A semiconductor device including an oxide semiconductor and an organic resin film is manufactured in the following manner. Heat treatment is performed on a first substrate provided with an organic resin film over a transistor including an oxide semiconductor in a reduced pressure atmosphere; handling of the first substrate is performed in an atmosphere containing moisture as little as possible in an inert gas (e.g., nitrogen) atmosphere with a dew point of lower than or equal to −60° c., preferably with a dew point of lower than or equal to −75° c.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Method of fabricating semiconductor device

A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate.
United Microelectronics Corp.

new patent

Structure and forming strained finfet by cladding stressors

Various methods and structures for fabricating a strained semiconductor fin of a finfet device. A strained semiconductor fin structure includes a substrate, a semiconductor fin disposed on the substrate, the semiconductor fin having two fin ends, and a stressor material cladding wrapped around a portion of each of the two fin ends forming a strained semiconductor fin that includes at least one strained channel fin having stressor cladding wrapped around at least one end of the strained channel fin thereby straining the at least one strained channel fin.
International Business Machines Corporation

new patent

Power mosfet, an igbt, and a power diode

Super-junction mosfets by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction.
Renesas Electronics Corporation

new patent

Semiconductor structure and forming the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, at least a first cell, and at least a second cell.
United Microelectronics Corp.

new patent

Method of forming a semiconductor device with multiple etch stop layers and inter-layer dielectrics

An embodiment is a semiconductor device comprising a first gate structure over a semiconductor substrate, a first etch stop layer (esl) over the semiconductor substrate and the first gate, the first esl having a curved top surface, and a first inter-layer dielectric (ild) on the first esl, the first ild having a curved top surface. The semiconductor device further comprises a second esl on the first ild, the second esl having a curved top surface, and a second ild on the second esl..
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Semiconductor device and semiconductor device manufacturing method

A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor above a substrate, a second semiconductor layer formed of a material including inaln or inalgan above the first semiconductor layer, a third semiconductor layer formed of a material including aln above the second semiconductor layer, a fourth semiconductor layer formed of a material including gan above the third semiconductor layer, a gate electrode formed above the fourth semiconductor layer, and a source electrode and a drain electrode formed on any one of the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer.. .
Fujitsu Limited

new patent

Techniques for forming non-planar germanium quantum well devices

Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group iv or iii-v semiconductor materials and includes a germanium fin structure.
Intel Corporation

new patent

Semiconductor device

A linear active cell region is formed from a plurality of divided active cell regions arranged apart from each other in a second direction (y direction). The linear hole collector cell region is formed from a plurality of divided hole collector cell regions arranged apart from each other in the second direction (y direction).
Renesas Electronics Corporation

new patent

Bipolar junction transistor (bjt) base conductor pullback

Some embodiments are directed to a bipolar junction transistor (bjt) with a collector region formed within a body of a semiconductor substrate, and an emitter region arranged over an upper surface of the semiconductor substrate. The bjt includes a base region arranged over the upper surface of the semiconductor substrate, which vertically separates the emitter and collector regions.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Self-aligned inner-spacer replacement process using implantation

A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the channel region.. .
International Business Machines Corporation

new patent

Self-aligned inner-spacer replacement process using implantation

A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the channel region.. .
International Business Machines Corporation

new patent

Semiconductor device and manufacturing method thereof

A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure. The first fin structure and the second fin structure are both disposed over the substrate, and extend in a first direction in plan view.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Extension region for a semiconductor device

A method of forming a semiconductor device having a channel and a source-drain coupled to the channel. The method includes etching a channel region such that an end of the channel region forms a recess within a gate structure surrounding the channel region.
Tokyo Electron Limited

new patent

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a plurality of dummy gates on a substrate, a capping layer on each dummy gate, and a dielectric layer over the substrate, wherein the dielectric layer has a top surface above each dummy gate.
Semiconductor Manufacturing International (beijing) Corporation

new patent

Low temperature polycrystalline silicon thin film transistor and manufacturing thereof

The disclosure relates to a low temperature polycrystalline silicon thin film transistor including: a substrate; a buffer layer formed on the substrate; a semiconductor layer formed on the buffer layer; a gate insulation layer formed on the buffer layer and the semiconductor layer; gates formed on the gate insulation layer; a dielectric layer formed on the gate insulation layer and the gates; a passivation layer formed on the dielectric layer; a first contact hole and a second contact hole formed respectively inside the passivation layer, the dielectric layer and the gate insulation layer, and sources ad drains formed respectively on the first contact hole and the second contact hole; the semiconductor layer being a low temperature poly silicon layer, and a reflective layer and/or an insulation layer disposed between the buffer layer and the semiconductor layer. The disclosure further relates to a manufacturing method for aforementioned thin film transistor..
Wuhan China Star Optoelectronics Technology Co., Ltd.

new patent

Semiconductor structure and fabrication method thereof

The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a substrate having a first region and a second region; forming a trench in the substrate in the first region; forming a compensation doping region in a side surface of the trench adjacent to the second region; forming an isolation structure in the trench; forming a well region in the substrate in the second region; forming a drift region in the substrate in the first region; forming a gate structure over the substrate in a boundary region between the first region and the second region, and covering a portion of the isolation structure; and forming a source region in the well region at one side of the gate structure and a drain region in the drift region at another side of the gate structure..
Semiconductor Manufacturing International (beijing) Corporation

new patent

Semiconductor structure and forming the same

A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes: a substrate, at least a part of an upper surface of the substrate being a nonpolar surface or a semi-polar surface including nitride semiconductor crystals; an interface layer formed on the nonpolar surface or the semi-polar surface, and including at least one selected from a nitride and an oxynitride; and a metal layer formed on a surface of the interface layer away from the substrate..
Tsinghua University

new patent

Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts

An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill.
Globalfoundries Inc.

new patent

Semiconductor device

A semiconductor device includes a pillar-shaped semiconductor layer formed on a substrate; a first insulator surrounding the pillar-shaped semiconductor layer; a first gate surrounding the first insulator and made of a metal having a first work function; a second gate surrounding the first insulator and made of a metal having a second work function different from the first work function, the second gate being located below the first gate; a third gate surrounding the first insulator and made of a metal having the first work function, the third gate being located below the second gate; and a fourth gate surrounding the first insulator and made of a metal having the second work function different from the first work function, the fourth gate being located below the third gate. The first gate, the second gate, the third gate, and the fourth gate are electrically connected together..
Unisantis Electronics Singapore Pte. Ltd.

new patent

Semiconductor device

A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a gate metal layer, a via, a first source metal layer, a drain metal layer, and a second source metal layer. The source electrode, the drain electrode, and the gate electrode are present on the active layer.
Delta Electronics, Inc.

new patent

Semiconductor device and manufacturing the same

A method of manufacturing a semiconductor device, the method comprising: forming trenches in an upper surface of a semiconductor substrate, the semiconductor substrate comprising a first region and a second region, the trenches in the first region having a wide width, and the trenches in the second region having a narrow width; forming insulating films on inner surfaces of the trenches; filling conductive material inside the trenches; etching the conductive material until each of upper surfaces of the conductive material filled inside the trenches becomes lower than the upper surface of the semiconductor substrate; and forming, after the etching of the conductive material, an impurity layer by implanting impurities to a predetermined depth range, the impurity layer having a concentration by which a conductivity type of a region opposed to the conductive material via each insulating film is inverted by a potential applied to the conductive material.. .
Toyota Jidosha Kabushiki Kaisha

new patent

Semiconductor device

The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in x-direction; and a gate electrode arranged thereon via a gate insulating film and extending in y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in y-direction.
Renesas Electronics Corporation

new patent

Semiconductor device and manufacturing the same

A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a series of steps including: forming a transistor having source/drain regions within a fin structure and adjacent to a gate structure across over the fin structure; forming first source/drain contacts right above and electrically connected to the source/drain regions; depositing a composite barrier structure over the transistor and the first source/drain contacts; and forming second source/drain contacts right above and electrically connected to the first source/drain contacts.
Taiwan Semiconductor Manufacturing Company Limited

new patent

Semiconductor device including metal-semiconductor junction

A semiconductor device includes a silicon semiconductor layer including at least one region doped with a first conductive type dopant, a metal material layer electrically connected to the doped region, and a self-assembled monolayer (sam) between the doped region and the metal material layer, the sam forming a molecular dipole on an interface of the silicon semiconductor layer in a direction of reducing a schottky barrier height (sbh).. .
Samsung Electronics Co., Ltd.

new patent

Metallization and its use in, in particular, an igbt or a diode

A vertical power semiconductor component includes a semiconductor chip, the semiconductor chip having a top main surface and a bottom main surface. Each of said top main surface and said bottom main surface is in a heat exchanging relationship with a top metallization layer and a bottom metallization each of which serving as a heat sink.
Infineon Technologies Ag

new patent

Methods of forming substrate structures and semiconductor components

In an embodiment, a method includes forming an intentionally doped superlattice laminate on a support substrate, forming a group iii nitride-based device having a heterojunction on the superlattice laminate layer, and forming a charge blocking layer between the heterojunction and the superlattice laminate.. .
Infineon Technologies Austria Ag

new patent

Semiconductor device and manufacturing the same

A semiconductor device manufacturing method includes preparing a semiconductor substrate of a first conductivity type, forming a semiconductor layer of the first conductivity type over a main surface of the semiconductor substrate, forming a plurality of first ditches in an upper surface portion of the semiconductor layer such that the first ditches are arranged in a first direction extending along an upper surface of the semiconductor substrate, forming a plurality of second ditches in bottom surface portions of each of the first ditches such that the second ditches are arranged in a second direction perpendicular to the first direction, and covering a side wall of each of the first ditches with a first insulating film and a side wall and a bottom surface of each of the second ditches with a second insulating film thicker than the first insulating film.. .
Renesas Electronics Corporation

new patent

Semiconductor device and fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a recess is formed adjacent to the gate structure, a buffer layer is formed in the recess, and an epitaxial layer is formed on the buffer layer.
United Microelectronics Corp.

new patent

Bipolar junction transistor device and fabricating the same

A bipolar junction transistor (bjt) device includes a semiconductor substrate, a first doping region with a first conductivity, a second doping region with a second conductivity, a third doping region with the first conductivity, at least one stacked block and a conductive contact. The first doping region is formed in the semiconductor substrate.
United Microelectronics Corp.

new patent

Self-aligned gate edge and local interconnect and method to fabricate same

Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction.
Intel Corporation

new patent

Method for producing an optoelectronic component and an optoelectronic component

An optoelectronic component and a method for producing an optoelectronic component are disclosed. In embodiments, the method includes a) providing an auxiliary carrier; b) applying a sacrificial layer on the auxiliary carrier; c) applying a converter layer on the sacrificial layer, which includes quantum dots embedded in a matrix material or a luminescent polymer; d) providing a semiconductor layer sequence; e) optionally applying an adhesive layer on the semiconductor layer sequence; f) optionally bonding the converter layer on the semiconductor layer sequence by means of an adhesive layer, wherein the semiconductor layer sequence is configured to emit radiation; and g) removing the auxiliary carrier by means of optical, mechanical and/or chemical treatment and at least partially destroying the sacrificial layer..
Osram Opto Semiconductors Gmbh

new patent

Organic transistor, producing the same and oled display device

Embodiments of the present disclosure provide an organic transistor, a method for producing the same and an oled display device. The organic transistor includes: a collector and an emitter stacked above a substrate; a first organic semiconductor layer, a second organic semiconductor layer and a base between the first and second organic semiconductor layers, stacked and provided between the collector and the emitter; wherein the base forms a schottky contact with the first organic semiconductor layer and forms a schottky contact with the second organic semiconductor layer..
Ordos Yuansheng Optoelectronics Co., Ltd.

new patent

Imaging device

An imaging device includes: pixels arranged one-dimensionally or two-dimensionally, each of the pixels including an electrode that is electrically connected to the other pixels, a charge capturing unit that is separated from the other pixels, and a photoelectric conversion layer that is located between the electrode and the charge capturing unit, the photoelectric conversion layer being continuous among the pixels. The photoelectric conversion layer contains semiconductor carbon nanotubes, and one of a first substance and a second substance, the first substance having an electron affinity larger than that of the semiconducting carbon nanotubes, the second substance having a ionization energy smaller than that of the semiconductor carbon nanotubes..
Panasonic Intellectual Property Management Co., Ltd.

new patent

Semiconductor memory device and manufacturing the same

According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction.
Toshiba Memory Corporation

new patent

Semiconductor apparatus

A semiconductor apparatus may include a first circuit forming region formed over a substrate, a first interlayer dielectric layer formed over the first circuit forming region, a first metal layer formed over the first interlayer dielectric layer, a second interlayer dielectric layer formed over the first metal layer, and a second circuit forming region formed over the second interlayer dielectric layer. A first circuit and a second circuit that are included in the first circuit forming region and a third circuit that is included in the second circuit forming region may be electrically coupled to each other..
Sk Hynix Inc.

new patent

Methods and improving micro-led devices

A μled device comprising: a substrate and an epitaxial layer grown on the substrate and comprising a semiconductor material, wherein at least a portion of the substrate and the epitaxial layer define a mesa; an active layer within the mesa and configured, on application of an electrical current, to generate light for emission through a light emitting surface of the substrate opposite the mesa, wherein the crystal lattice structure of the substrate and the epitaxial layer is arranged such that a c-plane of the crystal lattice structure is misaligned with respect to the light emitting surface.. .
Oculus Vr, Llc

new patent

Light emitting device package and display device using the same

A light emitting device package includes a substrate for growth having a plurality of light-emitting windows, a plurality of semiconductor light-emitting units corresponding to the plurality of light-emitting windows, each semiconductor light-emitting unit having a first surface contacting the substrate for growth and a second surface opposite the first surface, and each semiconductor light-emitting unit having a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer stacked on each other, a plurality of wavelength conversion units respectively disposed inside the plurality of light-emitting windows, each wavelength conversion unit is configured to provide light having a wavelength different from light emitted by the respective semiconductor light-emitting unit, a metal support layer disposed on at least one surface of each of the plurality of semiconductor light-emitting units and having a lateral surface coplanar with a lateral surface of the substrate for growth, and an insulating layer disposed between each of the plurality of semiconductor light-emitting units and a respective metal support layer.. .
Samsung Electronics Co., Ltd.

new patent

Light-emitting diode

A light-emitting diode comprises: a first light-emitting structure, comprising: a first area comprising a side wall; a second area; and a first isolation path having an electrode isolation layer between the first area and the second area, wherein the side wall of the first area is in the first isolation path; an electrode contact layer covering the side wall of the first area, wherein the electrode contact layer is separated from electrode isolation layer; an electrical connecting structure covering the second area; and an electrical contact layer under the electrical connecting structure, wherein the electrical contact layer directly contacts the electrical connecting structure; wherein each of the first area and the second area sequentially comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer.. .
Epistar Corporation

new patent

Deep trench isolation structure and forming same

Deep trench isolation (dti) structures and methods of forming the same are provided. A method includes forming a plurality of photosensitive regions in a substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Solid-state imaging device, manufacturing a solid-state imaging device, and electronic apparatus

Disclosed is a solid-state imaging device including a plurality of pixels and a plurality of on-chip lenses. The plurality of pixels are arranged in a matrix pattern.
Sony Corporation

new patent

Optoelectronic device

The optoelectronic device includes a matrix of optoelectronic components including semiconductor optical amplifiers soas, the semiconductor optical amplifiers soas containing an active layer of gallium nitride gan having multiple ingan/gaasn or ingan/algan quantum wells on a substrate of p-doped gallium nitride and covered with a layer of n-doped gallium nitride. The p-doped gallium nitride gan substrate forms a column of p-gan covered with a layer of an insulator in biocompatible material.
Alcatel Lucent

new patent

Semiconductor device

A semiconductor device includes a pixel array, a plurality of column circuits, an amplifier, switch arrays of a first layer to an nth layer, and signal lines of the first layer to the nth layer. N is an integer of two or more.
Olympus Corporation

new patent

Back-side illuminated pixel

A back-side illuminated pixel including a semiconductor substrate of a first conductivity type coated, on the front side of the pixel, with a three-layer assembly successively including a first layer of the second conductivity type, an insulating layer, and a second semiconductor layer. The three-layer assembly is interrupted in a central portion of the pixel by a transfer region of the first conductivity type laterally delimited by an insulated conductive wall extending from the front surface, transistors are formed in the second semiconductor layer..
Stmicroelectronics (crolles 2) Sas

new patent

Gateless reset for image sensor pixels

Some embodiments of the present disclosure are directed to an image sensor pixel that is configured for gateless reset of a floating diffusion. Some embodiments are directed to an image sensor comprising a plurality of pixels, at least one pixel comprising a floating diffusion formed in a semiconductor substrate; a transfer gate configured to selectively cause transfer of photocharge stored in the pixel to the floating diffusion; and a reset drain formed in the semiconductor substrate and spaced away from the floating diffusion by an intervening semiconductor region having a dopant type opposite to the dopant type of the reset drain and the floating diffusion, wherein the reset drain is configured to selectively reset the electrostatic potential of the floating diffusion in response to a voltage pulse applied to the reset drain..
Dartmouth College

new patent

Image sensor, manufacturing the same, and camera

An image sensor includes a plurality of pixels. At least a pixel of the plurality of pixels includes a plurality of photoelectric converters arranged in a semiconductor substrate and a light waveguide provided for the plurality of photoelectric converters.
Canon Kabushiki Kaisha

new patent

Semiconductor device and electronic apparatus

The present disclosure relates to a semiconductor device and an electronic apparatus which is capable of reducing variations and deterioration of transistor characteristics. A first connection pad connected with a first wiring and a first floating metal greater than the first connection pad are formed at a bonding surface of a first substrate, whereas a second connection pad connected with a second wiring and a second floating metal greater than the second connection pad are formed at a bonding surface of a second substrate.
Sony Corporation

new patent

Image sensors

Image sensors are provided. An image sensor includes a semiconductor substrate including a pixel region.
Samsung Electronics Co., Ltd.

new patent

Thin film transistor array substrate and manufacture thin film transistor array substrate

Provided are a thin film transistor array substrate and a manufacture method thereof, comprising: providing a substrate, and the substrate comprises a first surface and a second surface, which are oppositely located; forming a gate on the first surface; forming a first insulative layer, which covers on the gate; forming a metal oxide semiconductor layer on the first insulative layer; implementing ion implantation to two end regions of the metal oxide semiconductor layer, and the two end regions after the ion implantation respectively are a source and a drain, and a region without the ion implantation is an active layer; forming a second insulative layer, which covers the source, the drain and the active layer; opening a via exposing the source or the drain in the second insulative layer; forming a pixel electrode on the second insulative layer, and connected with the source or the drain through the via.. .
Shenzhen China Star Optoelectronics Technology Co., Ltd.

new patent

Display device, semiconductor device, and manufacturing display device

A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.. .
Sony Corporation

new patent

Semiconductor layer structure and fabricating the same

The present disclosure a semiconductor layer structure having an insulating substrate and a semiconductor layer formed on the insulating substrate. The semiconductor layer includes a source signal access terminal, a drain signal access terminal, a first semiconductor layer pattern and a second semiconductor layer pattern; the first semiconductor layer pattern and the second semiconductor layer pattern formed between the source signal access terminal and the drain signal access terminal in parallel.
Wuhan China Star Optoelectronics Technology Co., Ltd.

new patent

Isolated circuit formed during back end of line process

A semiconductor die is disclosed upon which is formed direct current (dc) isolated first and second circuits. The first circuit is configured for electrical connection to a first ground.
Renesas Electronics America Inc.

new patent

Bridging local semiconductor interconnects

A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. Cmos/pmos areas, source/drain regions, etc.) and one or more inner active areas.
Stmicroelectronics, Inc.

new patent

Semiconductor device

A nitride insulating film which prevents diffusion of hydrogen into an oxide semiconductor film in a transistor including an oxide semiconductor is provided. Further, a semiconductor device which has favorable electrical characteristics by using a transistor including a silicon semiconductor and a transistor including an oxide semiconductor is provided.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Lateral bipolar junction transistor with multiple base lengths

A method comprises forming shallow trenches in an intrinsic base semiconductor layer and forming a first base layer thereon; applying a first mask to the layer; etching the first base layer; forming a second base layer on the intrinsic base semiconductor layer adjacent the first base layer; removing the first mask; applying a second mask to the base layers; simultaneously etching the layers to produce extrinsic bases of reduced cross dimensions; disposing spacers on the extrinsic bases; etching around the bases leaving the intrinsic base semiconductor layer under the bases and spacers; implanting ions into sides of the intrinsic base semiconductor layer under the first extrinsic base to form a first emitter/collector junction and into sides of the intrinsic base semiconductor layer under the second extrinsic base to form a second emitter/collector junction; depositing semiconductor material adjacent to the junctions and the trenches; and removing the applied second mask.. .
International Business Machines Corporation

new patent

Semiconductor device and manufacturing method thereof

Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-demensional vertical structure by the plasma-enhanced atomic layer deposition (peald) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced.
Asm Ip Holding B.v.

new patent

Semiconductor device and manufacturing the same

Deterioration in reliability is prevented regarding a semiconductor device. The deterioration is caused when an insulating film for formation of a sidewall is embedded between gate electrodes at the time of forming sidewalls having two kinds of different widths on a substrate.
Renesas Electronics Corporation

new patent

Semiconductor device and production method thereof

A semiconductor device includes: a memory transistor including a first silicon oxide film, a first silicon nitride film, a second silicon oxide film, and a first gate electrode that are disposed in sequence on a substrate; and a mos transistor including a third silicon oxide film and a second gate electrode that are disposed in sequence on the substrate. The memory transistor has a side wall including an extending portion of the first silicon oxide film, a second silicon nitride film that is in contact with the first silicon nitride film, and a fourth silicon oxide film that are disposed in sequence on the substrate, and the mos transistor has a side wall including a fifth silicon oxide film that is disposed on the substrate..
Seiko Epson Corporation

new patent

Semiconductor memory device

A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction.
Toshiba Memory Corporation

new patent

3d ctf integration using hybrid charge trap layer of sin and self aligned sige nanodot

Provided are an improved memory device and a method of manufacturing the same. In one embodiment, the memory device may include a vertical stack of alternating oxide layer and nitride layer, the vertical stack having a channel region formed therethrough, a plurality of nanostructures selectively formed on nitride layer of the vertical stack, and a gate oxide layer disposed on exposed surfaces of the channel region, the gate oxide layer encapsulating the plurality of nanostructures formed on the nitride layer.
Applied Materials, Inc.

new patent

Method of manufacturing semiconductor device

An improvement is achieved in the reliability of a semiconductor device. A structure is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate located in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage misfet is formed over the semiconductor substrate located in a lower-breakdown-voltage misfet formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage misfet is formed over the semiconductor substrate located in a higher-breakdown-voltage misfet formation region.
Renesas Electronics Corporation

new patent

Semiconductor memory device and manufacturing same

A semiconductor memory device includes a stacked body including a plurality of word lines; a semiconductor layer extending through the word lines; a memory cell provided at a part where the semiconductor layer crosses one of the word lines, the memory cell including a plurality of cell layers, the cell layers including a first insulating layer; and at least one of a first structural body and a second structural body provided around the stacked body. The first structural body includes a plurality of monitor layers including same materials respectively as materials of the cell layers.
Toshiba Memory Corporation

new patent

Semiconductor structure and forming the same

A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, and at least one memory cell. The raised dummy feature is present on the semiconductor substrate and defines a cell region and a non-cell region outside of the cell region on the semiconductor substrate, and the raised dummy feature has at least one opening communicating the cell region with the non-cell region.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Semiconductor device comprising a floating gate flash memory device

A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (soi) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the soi substrate in a logic area of the soi substrate, removing the semiconductor layer and the buried insulation layer from a memory area of the soi substrate, forming a dielectric layer on the exposed semiconductor bulk substrate, forming a floating gate layer on the first dielectric layer, forming an insulating layer on the floating gate layer and forming a control gate layer on the insulating layer, wherein an upper surface of the floating gate layer is substantially at the same height level as an upper surface of the semiconductor layer remaining in the logic area.. .
Globalfoundries Inc.

new patent

Otp cell having a reduced layout area

An anti-fuse device includes: a well region disposed in a semiconductor substrate; a gate electrode disposed on a gate insulating film on the semiconductor substrate; and a first well bias tap region disposed below the gate insulating film and the gate electrode in the well region, wherein the well bias tap region is doped with dopants of a same conductivity type as the well region.. .
Magnachip Semiconductor, Ltd.

new patent

One time programmable (otp) cell having improved programming reliability

A non-volatile semiconductor storage device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and first and second spaced apart doped regions formed below the gate insulating film and the gate electrode in the semiconductor substrate, wherein a grounded region of the first and second spaced apart doped regions is grounded via a contact.. .
Magnachip Semiconductor, Ltd.

new patent

Transistor structure having n-type and p-type elongated regions intersecting under common gate

A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region intersect at a common area, and a shared gate structure over each common area.. .
Globalfoundries Inc.

new patent

Embedded sram and methods of forming the same

A chip includes a semiconductor substrate, and a first n-type metal oxide semiconductor field effect transistor (nmosfet) at a surface of the semiconductor substrate. The first nmosfet includes a gate stack over the semiconductor substrate, a source/drain region adjacent to the gate stack, and a dislocation plane having a portion in the source/drain region.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Memory device having vertical structure

A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating the plurality of conductive line structures from the substrate, a contact plug between every two adjacent conductive line structures, an insulating spacer structure between each conductive line structure and a corresponding contact plug, a landing pad connected to each contact plug, and a landing pad insulation pattern separating every two adjacent landing pads from each other, each of the landing pad insulation patterns having an asymmetrical shape based on a vertical axis of the landing pad that extends along a normal to the substrate.. .
Samsung Electronics Co., Ltd.

new patent

Dual-port semiconductor memory and first in first out (fifo) memory having electrically floating body transistor

Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region.
Zeno Semiconductor, Inc.

new patent

Semiconductor device

The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Preventing shorting between source and/or drain contacts and gate

Electrical shorting between source and/or drain contacts and a conductive gate of a finfet-based semiconductor structure are prevented by forming the source and drain contacts in two parts, a bottom contact part extending up to a height of the gate cap and an upper contact part situated on at least part of the bottom contact part.. .
Globalfoundries Inc.

new patent

Integrated circuit having oxidized gate cut region and method to fabricate same

A method includes epitaxially depositing source/drains on parallel semiconductor fins having parallel polysilicon gate precursor structures disposed thereon orthogonally to the fins, where two adjacent polysilicon gate precursor structures are joined together and connected at ends thereof by a polysilicon loop portion. The method further includes oxidizing the ends of the polysilicon precursor gate structures, the connecting polysilicon loop portion and any semiconductor nodules that formed on the connecting polysilicon loop portion during the step of epitaxially depositing the source/drains.
International Business Machines Corporation

new patent

Semiconductor device

On a front surface side of an n− semiconductor substrate, an emitter electrode and trench gates each including a p base layer, a trench, a gate oxide film and a gate electrode are provided in an igbt region and a fwd region. Among p base layers each between adjacent trenches, p base layers having an n+ emitter region are the igbt emitter region and the p base layers not having the n+ emitter region are the fwd anode region.
Denso Corporation

new patent

Integrated semiconductor device and manufacturing method therefor

An integrated device includes a field effect transistor formed within and upon, an active region of a substrate and a resistor formed on an isolation region of the substrate. The field effect transistor includes a gate stacked structure having respective portions of a dielectric layer, a first conductive layer and a second conductive layer arranged in order from bottom to top.
Semiconductor Manufacturing International (beijing) Corporation

new patent

Method for manufacturing a semiconductor device

The improvement of the reliability of a semiconductor device having a split gate type monos memory is implemented. An ono film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode.
Renesas Electronics Corporation

new patent

Semiconductor device

In a semiconductor device having an sj structure, the reverse breakdown voltage decrease is suppressed while a main body region and a current detecting region are separated. Provided is a semiconductor device that has a semiconductor substrate, a main body region including one or more operation cells formed inside the semiconductor substrate, a current detecting region including one or more current detecting cells formed inside the semiconductor substrate, and an intermediate region that is provided between the main body region and the current detecting region and inside the semiconductor substrate and that includes an edge termination structure unit.
Fuji Electric Co., Ltd.

new patent

Semiconductor device

To suppress the reverse breakdown voltage decrease while separating a main body region from a current detecting region. To provide a semiconductor device comprising a semiconductor substrate, a main body region having one or more operation cells formed inside the semiconductor substrate, a current detecting region having one or more current detecting cells formed inside the semiconductor substrate, an intermediate region formed between the main body region and the current detecting region and inside the semiconductor substrate, an upper surface side electrode formed above at least part of the main body region, a current detecting electrode that is formed above at least part of the current detecting region and is separate from the upper surface side electrode, and an additional electrode that is formed above at least part of the intermediate region and is connected to either the upper surface side electrode or the current detecting electrode..
Fuji Electric Co., Ltd.

new patent

Cross-domain esd protection

semiconductor devices with cross-domain electrostatic discharge (esd) protection and related fabrication methods are provided. An exemplary semiconductor device includes first domain circuitry, second domain circuitry, and an interface coupled between an output node of the first domain driver circuitry and second domain receiver circuitry.
Nxp B.v.

new patent

Method of manufacturing a semiconductor die

A method of manufacturing a semiconductor die includes: forming a power hemt (high-electron-mobility transistor) in a iii-nitride semiconductor substrate, the power hemt having a gate, a source and a drain; monolithically integrating a first gate driver hemt with the power hemt in the iii-nitride semiconductor substrate, the first gate driver hemt having a gate, a source and a drain and logically forming part of a driver; and electrically connecting the first gate driver hemt to the gate of the power hemt so that the first gate driver hemt is operable to turn the power hemt off or on responsive to an externally-generated control signal received from the driver or other device.. .
Infineon Technologies Austria Ag

new patent

Semiconductor structure of esd protection device and manufacturing the same

Disclosed are a semiconductor structure of an esd protection device with low capacitance and a method for manufacturing the same. The method for manufacturing a semiconductor structure of an esd protection device, comprising: forming a buried layer with a first doping type and a buried layer with a second doping type in a first region and a second region at a top surface of a semiconductor substrate with a first doping type, respectively; forming an epitaxial layer with a second doping type on the buried layer with the first doping type and the buried layer with the second doping type, wherein the buried layer with the first doping type and the buried layer with the second doping type are buried between the semiconductor substrate and the epitaxial layer, a first doped region with a first doping type is formed at a top of a third region on the buried layer with the second doping type located on the epitaxial layer..
Silergy Semiconductor Technology (hangzhou) Ltd.

new patent

Esd protection device and manufacturing the same

Disclosed is a method for manufacturing an esd protection device. The esd protection device includes a rectifier diode and an open-base bipolar transistor, the anode of the rectifier diode is the first doped region and the cathode of the rectifier diode is the semiconductor substrate, the emitter region, base region and collector region of the open-base bipolar transistor are the second doped region, the epitaxial semiconductor layer and semiconductor substrate, respectively, the first doped region and the second doped region extend through the doped region into the epitaxial semiconductor layer by a predetermined depth.
Silergy Semiconductor Technology (hangzhou) Ltd.

new patent

Semiconductor packaging structure and method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

3d semiconductor device and structure

An integrated circuit device, the device including: a base wafer including a single crystal layer, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors, where the base wafer includes a memory bit-cell array including the first transistors and control bit-lines and word-lines; and a second layer including a plurality of second transistors, the second layer overlying the at least one metal layer, where the second layer includes a connecting via to the bit-lines or the word-lines, the connecting via has a diameter of less than 200 nm, and where the second layer includes control circuits to control the memory bit-cell array, the control circuits include the second transistors.. .
Monolithic 3d Inc.

new patent

Vertical semiconductor device

A semiconductor device vertically mounted on a medium such as a printed circuit board, and a method of its manufacture, are disclosed. The semiconductor device includes a stack of semiconductor die having contact pads which extend to an active edge of the die aligned on one side of the stack.
Sandisk Information Technology (shanghai) Co., Ltd.

new patent

Integrated circuits and methods for fabricating integrated circuits and electrical interconnects for iii-v semiconductor devices

Integrated circuits, methods for fabricating integrated circuits, and methods for fabricating electrical interconnects for iii-v devices are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a iii-v device over and/or within a semiconductor substrate.
Globalfoundries Singapore Pte. Ltd.

new patent

Method of manufacturing semiconductor structure

A method of manufacturing a semiconductor structure, including receiving a first substrate including a plurality of conductive bumps disposed over the first substrate; receiving a second substrate; disposing an adhesive over the first substrate; removing a portion of the adhesive to expose at least one of the plurality of conductive bumps; and bonding the first substrate with the second substrate.. .
Taiwan Semiconductor Manufacturing Company Ltd.

new patent

Semiconductor device

An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.. .
Rohm Co., Ltd.

new patent

Semiconductor integrated circuit device

A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by fc bonding to form a bga package by being integrated with the substrate. In such a structure, power consumption is increased, and hence the power supplied only from a peripheral portion of the chip is insufficient, so that a power supply pad is also provided in the chip central portion.
Renesas Electronics Corporation

new patent

Semiconductor device and manufacturing method thereof

In a semiconductor device (sp1) according to an embodiment, a solder resist film (first insulating layer, sr1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2cr) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body.
Renesas Electronics Corporation

new patent

Semiconductor device

A first surface of a first substrate included in a semiconductor device includes a first area in which a plurality of first connecting portions are disposed and a second area in which a plurality of second connecting portions are disposed. A second surface of a second substrate included in the semiconductor device includes a third area in which the plurality of first connecting portions are disposed and a fourth area in which the plurality of second connecting portions are disposed.
Olympus Corporation

new patent

Lps solder paste based low cost fine pitch pop interconnect solutions

Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste.
Intel Corporation

new patent

Method and system for packing optimization of semiconductor devices

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently..
Amkor Technology, Inc.

new patent

Semiconductor device and manufacturing method thereof

A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a cu pillar. In a semiconductor device to be coupled to a mounting board via a cu pillar, the cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer..
Renesas Electronics Corporation

new patent

Zn doped solders on cu surface finish for thin fli application

Embodiments of the invention include a semiconductor device and methods of forming the semiconductor device. In an embodiment the semiconductor device comprises a semiconductor die with one or more die contacts.
Intel Corporation

new patent

Single-shot encapsulation

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer.
Semtech Corporation

new patent

Semiconductor assembly and making same

A semiconductor device according to some examples of the disclosure may include a package substrate, a semiconductor die coupled to one side of the package substrate with a first set of contacts on an active side of the semiconductor die and coupled to a plurality of solder prints with a second set of contacts on a back side of the semiconductor die. The semiconductor die may include a plurality of vias connecting the first set of contacts to the second set of contacts and configured to allow heat to be transferred from the active side of the die to the plurality of solder prints for a shorter heat dissipation path..
Qualcomm Incorporated

new patent

Method of forming a semiconductor device including strain reduced structure

A method of forming a device includes forming conductive pads on a semiconductor die. The conductive pads include a first conductive pad having a first width on a first region of the semiconductor die; and a second conductive pad having a second width on a second region of the semiconductor die.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Semiconductor device

A slit is formed along a coupling portion at which a second interconnect is connected to a relatively large area interconnect or pad. Since tensile stress of a resist that is caused due to baking, uv curing, or other treatments in photolithography can be dispersed, contraction and deformation of the resist at an end of the second interconnect can be alleviated, and dimensions and shape of a interconnect, which is formed by etching, can be stabilized..
Sii Semiconductor Corporation

new patent

Fan-out semiconductor package

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface disposed to oppose the active surface; a dummy chip disposed in the through-hole and spaced apart from the semiconductor chip; a second connection member disposed on the first connection member, the dummy chip, and the active surface of the semiconductor chip; and an encapsulant encapsulating at least portions of the first connection member, the dummy chip, and the inactive surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads..
Samsung Electro-mechanics Co., Ltd.

new patent

Composite bond structure in stacked semiconductor structure

A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Semiconductor device

A semiconductor device includes an annular seal ring formed in a seal ring region surrounding a circuit forming region. The seal ring includes a box layer, an n-type semiconductor layer, and an annular electrode portion comprised of multiple layers of wirings.
Renesas Electronics Corporation

new patent

Method of manufacturing a semiconductor device

A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body.
Renesas Electronics Corporation

new patent

Iii-v compatible anti-fuses

An anti-fuse is provided above a semiconductor material. The anti-fuse includes a first end region including a first metal structure; a second end region including a second metal structure; and a middle region located between the first end region and the second end region.
International Business Machines Corporation

new patent

Semiconductor resistor structures embedded in a middle-of-the-line (mol) dielectric

A resistor structure composed of a metal liner is embedded within a mol dielectric material and is located, at least in part, on a surface of a doped semiconductor material structure. The resistor structure is located on a same interconnect level of the semiconductor structure as a lower contact structure and both structures are embedded within the same mol dielectric material.
International Business Machines Corporation

new patent

Semiconductor device

A semiconductor device is provided with a soi substrate including a semiconductor substrate, a box layer on the semiconductor substrate, and a semiconductor layer on the box layer, a multilayer wiring formed over a main surface of the soi substrate, and an inductor comprised of the multilayer wiring. In a region located below the inductor, the box layer and the semiconductor layer are separated into a plurality of regions by an element isolation portion, and a dummy gate electrode is formed on a part of the semiconductor layer, which is located in each of the plurality of regions, via a dummy gate insulating film..
Renesas Electronics Corporation

new patent

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a conductive structure, a dielectric layer, and a plurality of conductive features. The dielectric layer is present on the conductive structure.
Taiwan Semiconductor Manufacturing Company Limited

new patent

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate including a device region and a peripheral region.
Semiconductor Manufacturing International (beijing) Corporation

new patent

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes: receiving a first substrate with a surface; receiving a second substrate; determining a pad array on the surface of the first substrate, wherein the pad array includes a first type pad and a second type pad; forming a via pattern underlying the pad array in the first substrate according to the location of each via, wherein the first type pad in the pad array is directly contacting a via of the via pattern and the second type pad in the pad array is clear of any via of the via pattern; laterally connecting the second type pad with a conductive trace, wherein the conductive trace connects to another via that is same level with the via contacting the first type pad; and disposing a first conductive bump and a second conductive bump between the first substrate and the second substrate.. .
Taiwan Semiconductor Manufacturing Company Ltd.

new patent

Support terminal integral with die pad in semiconductor package (as amended)

A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad.
Rohm Co., Ltd.

new patent

Semiconductor device with lead terminals having portions thereof extending obliquely

A semiconductor device includes a semiconductor chip and a plurality of leads. The leads include a first lead including a supporting portion for mounting the semiconductor chip, and a projecting portion which projects in a first direction from the supporting portion.
Rohm Co., Ltd.

new patent

Power semiconductor device and manufacturing such a power semiconductor device

A power semiconductor device is provided comprising a wafer, wherein in a termination region of the device a passivation layer structure is formed at least on a portion of a surface of the wafer and the passivation layer structure comprises in an order from the surface of the wafer in a direction away from the wafer a semi insulating layer, a silicon nitride layer, an undoped silicate glass layer and an organic dielectric layer. The silicon nitride layer has a layer thickness of at least 0.5 μm.
Abb Schweiz Ag

new patent

Molding for large panel fan-out package

The present disclosure relates to wafer level packages including one or more semiconductor dies and a method of manufacturing the same. A method comprises: providing a carrier having a predetermined area, disposing a semiconductor device on the predetermined area, and forming a sacrificial wall on a periphery of the predetermined area..
Advanced Semiconductor Engineering, Inc.

new patent

Electronic device

Each of first and second semiconductor devices mounted on a substrate includes an emitter terminal electrically connected with a front surface electrode of a semiconductor chip and exposed from a main surface of a sealing body located on a front surface side of the semiconductor chip. Each of the first and second semiconductor devices includes a collector terminal electrically connected with a back surface electrode of the semiconductor chip and exposed from the main surface of the sealing body located on a back surface side of the semiconductor chip.
Renesas Electronics Corporation

new patent

Air gap spacer implant for nzg reliability fix

A method of forming a semiconductor device includes providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, providing at least one n-type metal-oxide semiconductor gate structure being an nzg gate structure having a gate insulation layer over the semiconductor layer and at least one p-type metal-oxide semiconductor gate structure being a pzg gate structure having a gate insulation layer over the semiconductor layer, the nzg and pzg gate structures being electrically separated from each other.. .
Globalfoundries Inc.

new patent

Transistor device structures with retrograde wells in cmos applications

A device includes a substrate having an n-active region and a p-active region, a layer of silicon-carbon positioned on an upper surface of the n-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the p-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An n-type transistor is positioned in and above the n-active region and a p-type transistor is positioned in and above the p-active region..
Globalfoundries Inc.

new patent

Field effect transistor stack with tunable work function

A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pfet) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.. .
International Business Machines Corporation

new patent

Field effect transistor stack with tunable work function

A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pfet) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.. .
International Business Machines Corporation

new patent

Semiconductor structures and fabrication methods thereof

A method for fabricating a semiconductor structure includes forming a plurality of dummy gate structures on a substrate. Each dummy gate structure includes a gate dielectric layer, a dummy gate electrode, and two sidewall spacers.
Semiconductor Manufacturing International (beijing) Corporation

new patent

Method of fabricating finfet structure

A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line..

new patent

Semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure.
United Microelectronics Corp.

new patent

Semiconductor device including contact structure

A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region.
Samsung Electronics Co., Ltd.

new patent

Method for forming semiconductor device structure with gate

A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Semiconductor structure and fabrication method thereof

semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate; forming gate structures over the base substrate; forming source/drain doping regions in the base substrate at two sides of each of the gate structures; forming an interlayer dielectric layer over the base substrate and the source/drain doping regions; forming a mask layer having a plurality of first openings there-through and over the interlayer dielectric layer, the first opening having a first length; performing a surface treatment process to remove portions of the mask layer from the first openings and to increase the first length of the first openings; forming contact through holes passing through the interlayer dielectric layer and exposing the source/drain doping regions using the mask layer with the first openings having the increased first length as an etching mask; and forming a contact via in each of the contact through holes..
Semiconductor Manufacturing International (beijing) Corporation

new patent

Semiconductor structures and fabrication methods thereof

semiconductor structure and fabrication method thereof are provided. An exemplary method includes providing a semiconductor substrate including a plurality of first fin structures, each having a first width, and a plurality of second fin structures, each having a second width greater than the first width.
Semiconductor Manufacturing International (beijing) Corporation

new patent

Method for manufacturing semiconductor substrate

A method for manufacturing a semiconductor substrate according to the present invention includes a hydrogen layer forming step of forming a hydrogen layer on a first substrate formed of single crystal of a first semiconductor material, a bonding step of bonding the first substrate and a temporary substrate, a first separation step of separating the first substrate with the hydrogen layer as a boundary and leaving a separated surface side of the first substrate as a first thin film layer on the temporary substrate, a support layer forming step of forming a support layer formed of a second semiconductor material on the temporary substrate on which the first thin film layer is left, a second separation step of removing the temporary substrate, and a cutting step of cutting a peripheral edge portion of the substrate.. .
Mtec Corporation

new patent

Method of manufacturing semiconductor device

A semiconductor device has a first lead group comprised of a plurality of first leads, a second lead group comprised of a plurality of second leads, and a first suspension lead arranged between the first lead group and the second lead group. Further, the semiconductor device has a first tape attached to each of the first leads, the first suspension lead, and some of the second leads, and a second tape attached to each of the second leads.

new patent

Method for singulating an assemblage into semiconductor chips, and semiconductor chip

A method for singulating an assemblage into a plurality of semiconductor chips is specified, wherein an assemblage comprising a carrier, a semiconductor layer sequence and a metallic layer is provided. Separating trenches are formed in the carrier.
Osram Opto Semiconductors Gmbh

new patent

Cu wiring forming method and semiconductor device manufacturing method

A method of forming, on a substrate having on a surface thereof a film having a trench of a preset pattern and a via at a bottom of the trench, a cu wiring by burying cu or cu alloy in the trench and the via includes forming a barrier film (process 2); forming, on a surface of the barrier film, a wetting target layer of ru or the like (process 3); forming, on a surface of the wetting target layer, a cu-based seed film by pvd (process 4); filling the via by heating the substrate and flowing the cu-based seed film into the via (process 5); and forming, on the substrate surface, a cu-based film made of the cu or cu alloy by pvd under a condition where the cu-based film is flown on the wetting target layer to bury the cu-based film in the trench (process 6).. .
Tokyo Electron Limited

new patent

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a base substrate, including a substrate, a gate structure on the substrate, source and drain doped regions in the substrate on both sides of the gate structure, and a dielectric layer on the substrate and on top of the gate structure.
Semiconductor Manufacturing International (beijing) Corporation

new patent

Semiconductor device and manufacturing method thereof

The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed..
Renesas Electronics Corporation

new patent

Method of manufacturing a template wafer

A method for manufacturing a semiconductor device includes providing a carrier wafer; and forming a semiconductor device layer on the carrier wafer. After front side processing of the semiconductor device layer, the carrier wafer is removed by cutting along a plane which is parallel to the semiconductor device layer..
Infineon Technologies Ag

new patent

Air gap spacer formation for nano-scale semiconductor devices

semiconductor devices having air gap spacers that are formed as part of beol or mol layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures.
International Business Machines Corporation

new patent

Method of forming inter-level dielectric structures on semiconductor devices

A semiconductor device and a method for making the semiconductor device are provided. The method of making the semiconductor device may include patterning a layer for a first conductor and a second conductor, plating patterned portions of the layer to form the first conductor and the second conductor, removing patterned material to form an air gap between the first conductor and the second conductor, applying a self-supporting film on top of the first conductor and the second conductor to enclose the air gap, and reacting the self-supporting film causing the self-supporting film to be substantially non-conductive..
Nxp Usa Inc.

new patent

Air gap spacer formation for nano-scale semiconductor devices

semiconductor devices having air gap spacers that are formed as part of beol or mol layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures.
International Business Machines Corporation

new patent

Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures

A single crystal semiconductor handle substrate for use in the manufacture of semiconductor-on-insulator (e.g., silicon-on-insulator (soi)) structure is etched to form a porous layer in the front surface region of the wafer. The etched region is oxidized and then filled with a semiconductor material, which may be polycrystalline or amorphous.
Sunedison Semiconductor Limited

new patent

Semiconductor device and fabrication method thereof

A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes providing a semiconductor substrate including a first region and a second region, and forming a plurality of fins on the semiconductor substrate in the first region and the second region.
Semiconductor Manufacturing International (beijing) Corporation

new patent

Semiconductor wafer device and manufacturing method thereof

A method of dies singulation includes providing a carrier, disposing a plurality of dies over a surface of the carrier according to a plurality of scribe lines comprising a plurality of continuous lines along a first direction and a plurality of discontinuous lines along a second direction, cutting the carrier according to the plurality of continuous lines along the first direction, and cutting the carrier according to the plurality of discontinuous lines along the second direction.. .
Taiwan Semiconductor Manufacturing Company Ltd.

new patent

Manufacturing semiconductor device

The yield of a manufacturing process of a display device is increased. The productivity of a display device is increased.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Process kit erosion and service life prediction

Embodiments of the present disclosure provide a method, system, and computer program product for monitoring a service life of a chamber component. In one example, the method includes receiving one or more power measurements of a semiconductor processing chamber from one or more sensors positioned about the semiconductor processing chamber.
Applied Materials, Inc.

new patent

Limiting electronic package warpage

An electronic package includes a carrier, semiconductor chip, a lid, and a lid-ring. The carrier includes a top surface and a bottom surface configured to be electrically connected to a system board.
International Business Machines Corporation

new patent

Lead carrier with print formed package components and conductive path redistribution structures

A lead carrier includes a temporary support layer, member, medium, or carrier upon which are dispersed a plurality of package sites, organized in a predetermined pattern such as a matrix or array. Each package site within a continuous sheet of mold compound of the lead carrier includes a semiconductor die; a set of terminal structures, each having a top side and an opposing back side that is exposed at a back side of the continuous sheet of mold compound; and a set of electrical current path redistribution structures, each formed as an elongate wiring structure having a first end, a second end distinct from the first end, a top surface, an opposing bottom surface, a width, and a thickness between its top and bottom surfaces.
Eoplex Limited

new patent

Lead carrier structure and packages formed therefrom without die attach pads

A lead carrier includes a continuous sheet of mold compound having a top side and an opposing back side, and forms an array of package sites corresponding to semiconductor packages. Each package site when fabricated includes a semiconductor die having a top side, and an opposing treated base exposed at the back side of the continuous sheet of mold compound; a set of terminal pads, each having a top side and an opposing back side exposed at the back side of the continuous sheet of mold compound; a plurality of wire bonds formed between a set of input/output junctions on the top side of the semiconductor die and the top side of each terminal pad; and hardened mold compound encapsulating the semiconductor die, the set of terminal pads, and the plurality of wire bonds.
Eoplex Limited

new patent

Transistor and manufacturing the same

A method of manufacturing a transistor, includes: (i) forming a metal-oxide semiconductor layer over a substrate; (ii) forming a source electrode and a drain electrode on different sides of the metal-oxide semiconductor layer; (iii) forming a dielectric layer over the source electrode, the drain electrode, and the metal-oxide semiconductor layer; (iv) forming a hydrogen-containing insulating layer over the dielectric layer, in which the hydrogen-containing insulating layer has an aperture exposing a surface of the dielectric layer, and the aperture is overlapped with the metal-oxide semiconductor layer when viewed in a direction perpendicular to the surface; (v) increasing a hydrogen concentration of a portion of the metal-oxide semiconductor layer by treating the hydrogen-containing insulating layer so to form a source region and a drain region; and (vi) forming a gate electrode in the aperture.. .
E Ink Holdings Inc.

new patent

Epitaxially coated semiconductor wafer, and producing an epitaxially coated semiconductor wafer

Epitaxial wafers with a high concentration of bmd nuclei or developed bmds just below a denuded zone, and having low surface roughness, are produced by forming an oxynitride layer on a purposefully oxidized epitaxial layer by a short rta treatment in a nitriding atmosphere, removing the oxynitride layer, and then polishing the epitaxial surface.. .
Siltronic Ag

new patent

Method of fabricating a semiconductor structure

A method of making a semiconductor structure, the method including forming a conductive layer over a substrate. The method further includes forming a first imaging layer over the conductive layer, where the first imaging layer comprises a plurality of layers.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Semiconductor device and manufacturing the semiconductor device

A method of manufacturing a semiconductor device includes forming an etching mask over a semiconductor body, forming a plurality of trenches in the semiconductor body to define a plurality of protruding semiconductor portions between adjacent trenches, and forming a protection layer in contact with a semiconductor material of the protruding semiconductor portions. The method further includes performing a wet etching step to remove portions of the etching mask and, thereafter, treating the semiconductor body with a mixture of hydrofluoric acid and ethylene glycol and bringing the semiconductor material of sidewalls of the plurality of protruding semiconductor portions into contact with the mixture of hydrofluoric acid and ethylene glycol..
Infineon Technologies Dresden Gmbh

new patent

Photoresist removal

Among other things, one or more systems and techniques for removing a photoresist from a semiconductor wafer are provided. The photoresist is formed over the semiconductor wafer for patterning or material deposition.
Taiwan Semiconductor Manufacturing Company Limited

new patent

Manufacturing semiconductor device

In order to provide a semiconductor device with high reliability while manufacturing cost is being suppressed, dry etching for an insulating film is performed by using mixed gas containing at least cf4 gas and c3h2f4 gas as its components.. .
Renesas Electronics Corporation

new patent

Self-aligned single dummy fin cut with tight pitch

A method of forming a semiconductor device and resulting structures having a dummy semiconductor fin removed from within an array of tight pitch semiconductor fins by forming a first spacer including a first material on a substrate; forming a second spacer including a second material on the substrate, the second spacer adjacent to the first spacer; and applying an etch process to the first spacer and the second spacer; wherein the etch process removes the first spacer at a first etch rate; wherein the etch process removes the second spacer at a second etch rate; wherein the first etch rate is different than the second etch rate.. .
International Business Machines Corporation

new patent

Semiconductor device packages and stacked package assemblies including high density interconnections

A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device.
Advanced Semiconductor Engineering, Inc.

new patent

Multilayer dielectric structures with graded composition for nano-scale semiconductor devices

Multilayer dielectric structures are provided with graded composition. For example, a multilayer dielectric structure includes a stack of dielectric films, wherein the dielectric films include at least a first sicno (silicon carbon nitride oxide) film and a second sicno film.
International Business Machines Corporation

new patent

Method to tune contact cd and reduce mask count by tilted ion beam

A novel method of processing and fabricating semiconductor devices is provided to reduce critical dimensions inherent in a given photolithography process. A patterned mask layer generated via transfer of the pattern to the masking layer (e.g., printing) has a given set of dimensions.
Globalfoundries, Inc.

new patent

Differentially pumped reactive gas injector

One process used to remove material from a surface is ion etching. In certain cases, ion etching involves delivery of both ions and a reactive gas to a substrate.
Lam Research Corporation

new patent

Gate-all-around fin device

A gate-all around fin double diffused metal oxide semiconductor (dmos) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate.
International Business Machines Corporation

new patent

Semiconductor memory device and test method therefor

A test method for a semiconductor memory device having a plurality of memory cells arranged in a matrix form, the test method including writing first data into a plurality of memory cells, while a plurality of word lines disposed in the columns of the memory cells are deselected, driving the low-potential side bit line of a bit line pair in the selected column, which is among a plurality of bit line pairs disposed in the columns of the memory cells, to a negative voltage level in accordance with second data complementary to the first data, and reading the data written into the memory cells.. .
Renesas Electronics Corporation

new patent

Semiconductor device

A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a mos type first transistor section (3) used for information storage, and a mos type second transistor section (4) which selects the first transistor section.
Renesas Electronics Corporation

new patent

Semiconductor memory device

A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells.
Toshiba Memory Corporation

new patent

Semiconductor memory device

Provided herein is a semiconductor memory device including a memory cell array including a drain select transistor and a plurality of memory cells, a voltage generator configured to apply a program voltage, first and second pass voltages, and a drain control voltage to the memory cell array, a control logic configured to control the voltage generator so that during a program operation, after the program voltage is applied to a selected one of the plurality of memory cells, the program voltage applied to the selected memory cell is discharged while the first pass voltage or the second pass voltage is applied to memory cells adjacent to the selected memory cell.. .
Sk Hynix Inc.

new patent

Current driver, write driver, and semiconductor memory apparatus using the same

A current driver may include a current applying circuit and a current adjusting circuit. The current applying circuit may include a threshold switching element, and may provide unlimited amount of current while occupying small circuit area therefor.
Sk Hynix Inc.

new patent

Semiconductor memory apparatus

A semiconductor memory apparatus may be provided. The semiconductor memory apparatus may include a memory element.
Sk Hynix Inc.

new patent

Semiconductor integrated circuit device

A semiconductor integrated circuit device includes a control unit which causes a column selection circuit to separate bit line pairs from a common bit line pair and causes a sense amplifier circuit to amplify a potential difference between the common bit line pair precharged by a precharge circuit, in response to a unique id generation instruction.. .
Renesas Electronics Corporation

new patent

Semiconductor memory apparatus

A semiconductor memory apparatus includes a bias voltage generation circuit configured to generate a bias voltage according to a read voltage or a write voltage in response to a read signal and a write signal, a data discrimination circuit configured to generate a set enable signal and a reset enable signal in response to data and the write signal. The semiconductor memory apparatus also includes a current selection circuit configured to generate a first current in response to the read signal, the set enable signal, and the reset enable signal.
Sk Hynix Inc.

new patent

Semiconductor memory device including output buffer

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.. .
Micron Technology, Inc.

new patent

Semiconductor device

A semiconductor device may be provided. The semiconductor device may include a signal mixing circuit suitable for generating a strobe signal which toggles in synchronization with a divided clock.
Sk Hynix Inc.

new patent

Semiconductor layered device with data bus

Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (tsvs) provided in one of the first semiconductor chip and the second semiconductor chip.
Micron Technology, Inc.

new patent

Control device for controlling semiconductor memory device

A control device includes: a dummy memory cell group; a transistor having a first terminal, a grounded second terminal and a control terminal; an adjustor providing a resistance between the dummy memory cell group and the first terminal of the transistor; an inverter generating, based on a voltage at the first terminal of the transistor, a sense start signal that is associated with switching of a sense amplifier circuit of a semiconductor memory device from a disabled state to an enabled state; and a controller generating, based on the sense start signal, a control signal for controlling the transistor such that switching of the transistor from conduction into non-conduction is associated with the sense start signal.. .
M31 Technology Corporation

new patent

System and electronic die inking after automatic visual defect inspection

A method of providing a semiconductor device and a computer-readable medium having instructions for performing the method are disclosed. The method includes receiving a first wafer defect map that defines comparison regions and identifies visual defect locations for a wafer.
Texas Instruments Incorporated



Semiconductor topics:
  • Semiconductor
  • Semiconductor Substrate
  • Semiconductor Device
  • Semiconductor Material
  • Electric Conversion
  • Conductive Layer
  • Molybdenum
  • Camera Module
  • Semiconductor Devices
  • Semiconductors
  • Integrated Circuit
  • Surfactant
  • Photoelectric Conversion
  • Electronic Device
  • Transparent Conductive Oxide


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