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Semiconductor patents

      

This page is updated frequently with new Semiconductor-related patent applications.




 Apparatus and  processing authentication information patent thumbnailApparatus and processing authentication information
Provided is an information processing apparatus including a physical unclonable function (puf) to generate a unique key using a process variation in a semiconductor manufacturing process, and an encryption unit to encrypt a password and/or bio-information received from a user using the unique key.. .
Ictk Co., Ltd.


 Soft shutdown modular circuitry for power semiconductor switches patent thumbnailSoft shutdown modular circuitry for power semiconductor switches
Circuitry for soft shutdown of a power switch and a power converters that includes circuitry for soft shutdown are described. In one aspect, circuitry for soft shutdown of a power switch includes a sense input to be coupled to a power switch receive a signal representative of current passing through the power switch, a comparator to compare the signal with an overcurrent threshold indicative of an overcurrent condition of the power switch and to output a triggering signal in response to the comparison indicating the overcurrent condition, and a gating transistor to be coupled to a control terminal of the power switch, the gating transistor configured to divert a portion of a drive signal away from the control terminal of the power switch in response to the triggering signal..
Power Integrations Switzerland Gmbh


 Electronic device with substrate current management patent thumbnailElectronic device with substrate current management
An electronic device with substrate current management. The electronic device has a semiconductor substrate in which a schottky diode is formed.
Monolithic Power Systems, Inc.


 Periodic signal generation circuit and semiconductor system including the same patent thumbnailPeriodic signal generation circuit and semiconductor system including the same
A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a period signal, the period signals periodically toggled in response to the command, output the data in response to the period signal, and discharge the charges of an internal node if the period signal is not toggled during a predetermined section..
Sk Hynix Inc.


 Semiconductor device patent thumbnailSemiconductor device
A semiconductor device includes: a semiconductor substrate whose contour is a pentagon; a front-stage amplifier formed relatively near a vertex of the pentagon of the semiconductor substrate; and a rear-stage amplifier formed relatively near a side opposed to the vertex of the semiconductor substrate and amplifying an output from the front-stage amplifier.. .
Mitsubishi Electric Corporation


 Multiphase dc power supply with high switching frequency patent thumbnailMultiphase dc power supply with high switching frequency
A multiphase dc power supply with high switching frequency of 1 mhz comprising three parallel connected three phase dc power supply. Each of the d parallel connected three phase dc power supply comprises a boost power factor corrector to convert an ac power source to a rectified and filtered dc voltage, an isolation transformer connected to the boost power factor corrector to generate a full wave rectified dc voltage having stable voltage level, a duck switching circuit consisting a first, a second and a third semiconductor switches to regulate the voltage level of the output of said isolation transformer and a phase controller to manage an interleaved phase of the output of said three semiconductor switches.
Chyng Hong Electronic Co., Ltd.


 Self-oscillating  resonant power converter patent thumbnailSelf-oscillating resonant power converter
The present invention relates to resonant power converters and inverters comprising a self-oscillating feedback loop coupled from a switch output to a control input of a switching network comprising one or more semiconductor switches. The self-oscillating feedback loop sets a switching frequency of the power converter and comprises a first intrinsic switch capacitance coupled between a switch output and a control input of the switching network and a first inductor.
Danmarks Tekniske Universitet


 Dc-dc voltage conversion device patent thumbnailDc-dc voltage conversion device
In a dc-dc voltage conversion device, overheat of a diode element connected in anti-parallel with a semiconductor switching element is a problem, and in order to resolve this, a temperature of a semiconductor switching element of a main conversion circuit is detected, a temperature of a diode element connected in parallel with the semiconductor switching element is calculated using a correction calculation of the detected semiconductor switching element temperature value in accordance with a step-up ratio of the dc-dc voltage conversion device, and diode element overheat protection is carried out in accordance with the calculated temperature value.. .
Mitsubishi Electric Corporation


 Semiconductor device, control  semiconductor device, and feeding system patent thumbnailSemiconductor device, control semiconductor device, and feeding system
Provided is a semiconductor device including: a first power source circuit that generates an output voltage supplied to a usb device coupled to a usb connector; an abnormality detection circuit that determines the state of a supply route of the output voltage generated by the first power source circuit; and a control circuit that controls supply of the output voltage from the first power source circuit to the usb device on the basis of a determination result of the abnormality detection circuit.. .

 Rotating electrical machine system patent thumbnailRotating electrical machine system
A rotating electrical machine system integrally includes a rotating electrical machine housed in a first chamber of a housing and a semiconductor module housed in a second chamber of the housing and electrically coupled to the rotating electrical machine. The rotating electrical machine includes a stator secured to an inner circumference surface of the first chamber and a rotor rotatably disposed with respect to the stator.
Nissan Motor Co., Ltd.


Laser manufacturing the same

Provided is a laser device according to an embodiment of the inventive concept. The laser device includes: a semiconductor substrate; a germanium single crystal layer on the semiconductor substrate; and a pumping light source disposed on the germanium single crystal layer and configured to emit light toward the germanium single crystal layer, wherein the germanium single crystal layer receives the light to thereby output laser..
Electronics And Telecommunications Research Institute

Laser diode

A laser diode with an improved kink level in the l-i characteristic and capable of obtaining a stable high output in a horizontal transverse mode is provided. The laser diode includes an active layer made of nitride iii-v compound semiconductor containing at least gallium (ga) in 3b-group elements and at least nitrogen (n) in 5b-group elements, an n-type compound semiconductor layer provided on one of faces of the active layer, and a p-type compound semiconductor layer provided on the other face of the active layer.
Sony Corporation

Hybrid optical source with optical proximity coupling provided by an external reflector

A hybrid optical source comprises an optical gain chip containing an optical gain material that provides an optical signal, and an optical reflector chip including an optical reflector. It also includes a semiconductor-on-insulator (soi) chip, which comprises a semiconductor layer having a planarized surface facing the semiconductor reflector.
Oracle International Corporation

Microscale three-dimensional electric devices and methods of making the same

Functionalized microscale 3d devices and methods of making the same. The 3d microdevice can be realized with the combination of top-down (lithographic) and bottom-up (origami-inspired self-assembly) processes.
Regents Of The University Of Minnesota

Integrated fan-out package including dielectric waveguide

A semiconductor structure includes a dielectric waveguide, a driver die, a first transmission electrode, a second transmission electrode, and a receiver die. The driver die is configured to generate a driving signal.
Taiwan Semiconductor Manufacturing Co., Ltd.

Composite containing silver nanoparticles and antibacterial agent, photoelectric converter, photosensitive pointing device, and thin-film photovoltaic cell using this composite

[problem] the purpose of the present invention is to provide a novel optical functional material in which silver nanoparticles are used. [solution] according to the present invention, a ternary composite formed by mixing silver nanoparticles, an organic semiconductor, and a clay in a liquid phase is provided.
Ito Research Institute Co., Ltd.

Organic thin film transistor and manufacturing method thereof, array substrate

An organic thin film transistor, a manufacturing method thereof and an array substrate are provided. The manufacturing method of an organic thin film transistor includes: forming an organic semiconductor layer; partially sheltering the organic semiconductor layer, so that a sheltered region and an unsheltered region are formed on the organic semiconductor layer, the sheltered region corresponding to a region where an active layer of the organic thin film transistor needs to be formed; and doping the organic semiconductor layer, so that the organic semiconductor layer in correspondence with the sheltered region is not doped, and the organic semiconductor layer in correspondence with the unsheltered region is doped..
Boe Technology Group Co., Ltd.

Carbon nanotube semiconductor device and manufacturing method thereof

The present disclosure pertains to the field of carbon nanotube technologies, and provides a carbon nanotube semiconductor device and a manufacturing method thereof. The manufacturing method of a carbon nanotube semiconductor device provided in the present disclosure comprises: forming a carbon nanotube layer with a carbon nanotube solution; and treating the carbon nanotube layer with an acidic solution.
Peking University

Semiconductor device including an etching stop layer and manufacturing the same

A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.. .
Sk Hynix Inc.

Magnetic sensor and manufacturing the same

Provided are a magnetic sensor and a method of manufacturing the same. In the magnetic sensor and the method of manufacturing the same, a magnetic converging plate holder with a recessed pattern having the same shape and size as those of a magnetic converging plate is formed in a die pad of a package on which a semiconductor substrate having hall elements, a circuit, and the like is to be arranged, the magnetic converging plate manufactured through processes different from those of the semiconductor substrate on which the hall elements and the circuit are formed is inserted into the magnetic converging plate holder, and the semiconductor substrate having the hall elements, the circuit, and the like is arranged on the resultant so that a back surface thereof faces the die pad and the magnetic converging plate..
Sii Semiconductor Corporation

Method of forming a bottom electrode of a magnetoresistive random access memory cell

A method of fabricating a semiconductor device is disclosed. The method includes forming an opening with a tapered profile in a first material layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

Light element doped low magnetic moment material spin torque transfer mram

Techniques relate to forming a semiconductor device. A magnetic pinned layer is formed adjacent to a tunnel barrier layer.
Samsung Electronics Co., Ltd.

Light-emitting device

This disclosure discloses a light-emitting device includes a semiconductor stack, an electrode, an electrode post, a reflective insulating layer, an extending electrode, and a supporting structure. The electrode is disposed on a lower surface of the semiconductor stack, and electrically connected to the semiconductor stack.
Epistar Corporation

Semiconductor package device and manufacturing the same

A semiconductor package device includes an electronic device. The electronic device includes a first carrier, a first electronic component, a second carrier, a second electronic component, an encapsulant, and a lens.
Advanced Semiconductor Engineering, Inc.

Semiconductor device package and a manufacturing the same

At least some embodiments of the present disclosure relate to a lid for covering an optical device. The lid includes a metal member and a transparent encapsulant.
Advanced Semiconductor Engineering, Inc.

Semiconductor device

The semiconductor device includes: an algan layer; a contact electrode; an insulating film; and a passivation film. The semiconductor device further includes: an extended wire extending over the contact electrode and the insulating film; and a pad electrode electrically connected to the extended wire.
Panasonic Intellectual Property Management Co., Ltd.

Light-emitting diode chips with enhanced brightness

According to at least some embodiments of the present disclosure, a light-emitting diode (led) chip includes a semiconductor material portion, a transparent conductive layer disposed above the semiconductor material portion, a current blocking layer disposed above the transparent conductive layer, one or more electrodes disposed above the current blocking layer, and a plurality of electron outflow channels that electrically interconnect at least one electrode and the semiconductor material portion across the transparent conductive layer and the current blocking layer.. .
Xiamen Changelight Co., Ltd.

Light emitting diode and manufacturing the same

A light emitting diode and a method of manufacturing the light emitting diode are provided. The light emitting diode includes an n-type semiconductor layer, an inclined type superlattice thin film layer, an active layer, and a p-type semiconductor layer.
Industry Foundation Of Chonnam National University

Semiconductor structure

A semiconductor structure includes a first-type doped semiconductor layer, a light emitting layer, a second-type doped semiconductor layer comprising alxinygal-x-yn layers, at least one gan based layer, and an ohmic contact layer. The light emitting layer is disposed on the first-type doped semiconductor layer, and the second-type doped semiconductor layer is disposed on the light emitting layer.
Genesis Photonics Inc.

Nitride semiconductor light-emitting element

A nitride semiconductor light-emitting element includes at least an n-type nitride semiconductor layer, a light-emitting layer, and a p-type nitride semiconductor layer. A multilayer body is provided between the n-type nitride semiconductor layer and the light-emitting layer, having at least one stack of first and second semiconductor layers.
Sharp Kabushiki Kaisha

Manufacturing light-emitting device

A manufacturing method of light-emitting device is disclosed. The method includes providing an led wafer comprising a substrate and a semiconductor stack formed on the substrate, wherein the semiconductor stack has a lower surface facing the substrate and an upper surface opposite to the lower surface; providing a first laser to the led wafer and irradiating the led wafer from the upper surface to form a plurality of scribing lines on the upper surface; providing and focusing a second laser on an interior of the substrate to form a plurality of textured areas in the substrate; and providing force on the led wafer to separate the led wafer into a plurality of led chips..
Epistar Corporation

Optoelectronic semiconductor component

An optoelectronic semiconductor component includes an optoelectronic semiconductor chip having a top area at a top side, a bottom area at an underside, and side areas connecting the top area and the bottom area; electrical contact locations at the top area or at the bottom area of the optoelectronic semiconductor chip; and an electrically insulating shaped body, wherein the optoelectronic semiconductor chip is a flip-chip having the electrical contract locations only at one side, either the underside or the top side, the shaped body surrounds the optoelectronic semiconductor chip at its side areas, and the shaped body is free of a via that electrically connects the optoelectronic semiconductor chip.. .
Osram Opto Semiconductor Gmbh

Thermo-electrically pumped light-emitting diodes

Contrary to conventional wisdom, which holds that light-emitting diodes (leds) should be cooled to increase efficiency, the leds disclosed herein are heated to increase efficiency. Heating an led operating at low forward bias voltage (e.g., v<kbt/q) can be accomplished by injecting phonons generated by non-radiative recombination back into the led's semiconductor lattice.

Multi-wafer based light absorption apparatus and applications thereof

Structures and techniques introduced here enable the design and fabrication of photodetectors (pds) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on pds' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-pd homogeneous wafer bonding technique, a pre-pd heterogeneous wafer bonding technique, a post-pd wafer bonding technique, their combinations, and a number of mirror equipped pd structures.
Artilux Corporation

Semiconductor layered structure, photodiode and sensor

A semiconductor layered structure includes a base layer, a quantum well structure, and a contact layer. The base layer, the quantum well structure, and the contact layer are disposed so as to be stacked in this order.
Sumitomo Electric Industries, Ltd.

Transistor and manufacturing the same

An object is to provide a highly reliable transistor. In a bottom-gate transistor including an oxide semiconductor layer as a semiconductor layer where a channel is formed, an insulating layer containing excess oxygen is formed over the oxide semiconductor layer, and then an insulating layer through which impurities do not easily pass is formed without exposure to the air.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and manufacturing the same

A transistor with stable electrical characteristics is provided. The transistor includes a first insulator over a substrate; first to third oxide insulators over the first insulator; a second insulator over the third oxide insulator; a first conductor over the second insulator; and a third insulator over the first conductor.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and manufacturing method thereof

A highly reliable semiconductor device includes a first insulator, a second insulator, a first conductor, a third insulator, an oxide semiconductor, second and third conductors, a fourth insulator, a fourth conductor overlapping with a region between the second and third conductors, a fifth insulator, and a sixth insulator in this order. The fourth insulator is in contact with top and side surfaces of the oxide semiconductor, and a top surface of the third insulator.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor structure and manufacturing the same

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor includes a substrate, two source/drain regions, a gate structure and two salicide layers.
United Microelectronics Corp.

Semiconductor device and fabricating semiconductor device

The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.. .
United Microelectronics Corp.

Semiconductor device and a manufacturing a semiconductor device

The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film.
Renesas Electronics Corporation

Vertical fets with high density capacitor

A technique relates to semiconductors. A bottom terminal of a transistor and bottom plate of a capacitor are positioned on the substrate.
International Business Machines Corporation

Semiconductor device and fabrication method thereof

A semiconductor device and fabrication method thereof are provided. The method includes forming at least one dummy gate structure and sidewall spacers of the dummy gate structure in a first dielectric layer, together on a substrate, and removing the dummy gate structure, thereby forming a first opening between the sidewall spacers.
Semiconductor Manufacturing International (beijing) Corporation

Bulk to silicon on insulator device

A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin.
International Business Machines Corporation

Bulk to silicon on insulator device

A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin.
International Business Machines Corporation

Protective insulator for hfet devices

A high-voltage field effect transistor a heterojunction is disposed between the first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and a second composite passivation layer includes a second insulation layer and a second passivation layer.
Power Integrations, Inc.

Semiconductor devices with integrated schotky diodes and methods of fabrication

An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a schottky metal layer disposed over the substrate adjacent the gate electrode. The schottky metal layer includes a schottky contact electrically coupled to the channel which provides a schottky junction and at least one alignment mark disposed over the semiconductor substrate.
Nxp Usa, Inc.

Electronic device including a hemt with a segmented gate electrode and a process of forming the same

An electronic device can include a low-side hemt including a segmented gate electrode; and a high-side hemt coupled to the low-side hemt, wherein the low-side and high voltage hemts are integrated within a same semiconductor die. In another aspect, an electronic device can include a source electrode; a low-side hemt; a high-side hemt coupled to the low-side hemt; and a resistive element.
Semiconductor Components Industries, Llc

High electron mobility transistors with improved heat dissipation

Iii-nitride based high electron mobility transistors (hemts), such as algan/gan hemts on silicon substrates, with improved heat dissipation are described herein. A semiconductor device having improved heat dissipation may include a substrate having a top surface and a bottom surface, a nucleation layer on the top surface of the substrate, a transition layer on the nucleation layer, a buffer layer on the transition layer, a barrier layer on the buffer layer, and a metal layer filling a via hole that extends from the bottom surface of the substrate to a bottom surface of the transition layer..
University Of Florida Research Foundation, Incorporated

Semiconductor device and manufacturing the same

An insulated gate bipolar transistor (igbt) includes: a p base layer disposed close to a front surface of an n-type silicon substrate; and a deep n+ buffer layer and a shallow n+ buffer layer disposed close to a back surface of the n-type silicon substrate. The p base layer has a higher impurity concentration than the n-type silicon substrate.
Mitsubishi Electric Corporation

Reverse-conducting semiconductor device

A reverse-conducting mos device is provided having an active cell region and a termination region. Between a first and second main side.
Abb Schweiz Ag

Iii-v lateral bipolar junction transistor

A lateral bipolar junction transistor (lbjt) device that includes an intrinsic iii-v semiconductor material having a first band gap; and a base region present on the intrinsic iii-v semiconductor material. The base region is composed of an iii-v semiconductor material having a second band gap that is less than the first band gap.
International Business Machines Corporation

Directional deposition of protection layer

A method for forming a fin device includes forming semiconductor fins over a first dielectric layer. A second dielectric layer is directionally deposited into or on the first dielectric layer and on tops of the fins on horizontal surfaces.
International Business Machines Corporation

Method for fabricating semiconductor device

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form a patterned second organic layer on the substrate..
United Microelectronics Corp.

Methods of forming source/drain regions on finfet devices

One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, forming a gate structure around the fin and, after forming the gate structure, forming a final source/drain cavity in the fin, wherein the source/drain cavity comprises an upper innermost edge and a lower innermost edge, both of which extend laterally under at least a portion of the gate structure, and wherein the lower innermost edge extends laterally further under the gate structure than does the upper innermost edge. The method also includes performing an epitaxial growth process to form an epi semiconductor material in the final source/drain cavity.
Globalfoundries Inc.

Method for manufacturing a semiconductor device having a super junction mosfet

A method of manufacturing a super junction mosfet, which includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a mos gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region.
Fuji Electric Co., Ltd.

Thin film transistor substrate, a display device including the same, and a manufacturing the same

A thin film transistor substrate including a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer including a channel region, and a source region and a drain region at first and second sides of the channel region; a gate electrode disposed on the semiconductor layer; a gate insulating layer disposed between the gate electrode and the semiconductor layer; and a first insulating layer disposed on the substrate, the first insulating layer exposes the upper surface of the gate electrode and surrounds the gate electrode.. .
Samsung Display Co., Ltd.

Semiconductor device and manufacturing the same

A semiconductor device including, a semiconductor layer including a plurality of first trenches formed therein and a second trench formed in a region between the first trenches, channel regions formed in regions between the first and second trenches in a surface layer portion of the semiconductor layer, field plate electrodes embedded at bottom portion sides of the respective first trenches, first gate electrodes embedded at opening portion sides of the respective first trenches so as to face the channel regions across first gate insulating films above the field plate electrodes, second insulating films interposed between the field plate electrodes and the first gate electrodes, an embedded insulating film embedded to an intermediate portion of the second trench, and a second gate electrode embedded in the second trench so as to face the channel regions across a second gate insulating film above the embedded insulating film.. .
Rohm Co., Ltd.

Recess liner for silicon germanium fin formation

semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure.
Globalfoundries Inc.

Semiconductor devices with enhanced deterministic doping and related methods

A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region, and performing an anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region..
Atomera Incorporated

Semiconductor device and manufacturing the same

A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the soi substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed.

Methods, devices, and systems related to forming semiconductor power devices with a handle substrate

Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate.
Micron Technology, Inc.

Method of forming epitaxial buffer layer for finfet source and drain junction leakage reduction

A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion.
Renesas Electronics Corporation

Semiconductor device and fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate.
United Microelectronics Corp.

Bulk to silicon on insulator device

A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin.
International Business Machines Corporation

High voltage electronic device and method associated therewith

An electronic device including a substrate, a semiconductor element disposed on the substrate, and a plurality of guard rings at least partially surrounding the semiconductor element, wherein adjacent guard rings are spaced apart by a substantially uniform distance as measured along an entire length of the guard rings, and at least one of the plurality of guard rings has a flared portion. In an embodiment, at least one of the plurality of guard rings electrically floats.
Littelfuse, Inc.

Gate electrode structure and high voltage semiconductor device having the same

A gate electrode structure and a high voltage semiconductor device having the same are disclosed. The gate electrode structure includes a gate insulation layer pattern disposed on a substrate, a gate electrode disposed on the gate insulating layer pattern and having at least one opening at a first side portion thereof, and at least one insulating pattern disposed in the at least one opening.
Dongbu Hitek Co., Ltd.

Transistor array panel, manufacturing method thereof, and display device including the same

A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.. .
Samsung Display Co., Ltd.

Display device

A display device is disclosed, which includes: a substrate; a light emitting diode disposed above the substrate; a first transistor disposed above the substrate; and a second transistor disposed above the substrate. The first transistor includes: a first semiconductor layer; a first top gate electrode disposed above the first semiconductor layer; a first bottom gate electrode disposed under the first semiconductor layer; a first source electrode electrically connected to the first semiconductor layer; and a first drain electrode electrically connected to the first semiconductor layer, wherein the first drain electrode is electrically connected to the light emitting diode.
Innolux Corporation

Image sensor, manufacturing the same, and image processing device having the image sensor

An image sensor comprising: a first layer having a plurality of groups of photodiodes formed in a semiconductor substrate, each group representing a 2×2 array of photodiodes, with 2 first pixels configured to detect light of a first wavelength and 2 second pixels configured to detect light of a second wavelength, each first pixel positioned adjacent to the second pixels; and a second layer overlapping the first layer, the second layer is organic, having a plurality of organic photodiodes configured to detect light of a third wavelength, each organic photodiode positioned to partially overlap 2 first photodiodes and 2 second photodiodes of the first layer.. .
Samsung Electronics Co., Ltd.

Solid-state image pickup unit and electronic apparatus

A solid-state image pickup unit includes: a substrate made of a first semiconductor; a substrate made of a first semiconductor; a photoelectric conversion device provided on the substrate and including a first electrode, a photoelectric conversion layer, and a second electrode in order from the substrate; and a plurality of field-effect transistors configured to perform signal reading from the photoelectric conversion device. The plurality of transistors include a transfer transistor and an amplification transistor, the transfer transistor includes an active layer containing a second semiconductor with a larger band gap than that of the first semiconductor, and one terminal of a source and a drain of the transfer transistor also serves the first electrode or the second electrode of the photoelectric conversion device, and the other terminal of the transfer transistor is connected to a gate of the amplification transistor..
Sony Corporation

Imaging device, manufacturing device, and manufacturing method

The present technology relates to an imaging device, a manufacturing device, and a manufacturing method capable of preventing a substance such as hydrogen from entering and preventing change in performance. The imaging device includes an organic photoelectric conversion film, an upper electrode provided in an upper portion of the organic photoelectric conversion film, a lower electrode provided in a lower portion of the organic photoelectric conversion film, and a metal thin film provided between the organic photoelectric conversion film and the upper electrode or between the organic photoelectric conversion film and the lower electrode.
Sony Semiconductor Solutions Corporation

Electronic device including metal-insulator-semiconductor structure and fabricating the same

A method for fabricating an electronic device that includes a metal-insulator-semiconductor (m-i-s) structure includes: providing a semiconductor layer; forming a primary insulation layer of a first thickness over the semiconductor layer; forming a reactive metal layer of a second thickness over the primary insulation layer, where the second thickness is greater than the first thickness; forming a primary capping layer of a third thickness over the reactive metal layer, where the third thickness is greater than the second thickness; and performing a thermal treatment.. .
Sk Hynix Inc.

Light emitting diode module, display panel having the same and manufacturing the same

In some examples, a semiconductor device may comprise a semiconductor chip including a plurality of pixels, each pixel formed of a plurality of sub-pixels, such as a red sub-pixel, green sub-pixel and blue sub-pixel. Each sub-pixel may comprise a light emitting diode.
Samsung Electronics Co., Ltd.

Photoelectric conversion device, manufacturing photoelectric conversion device, and imaging system

Provided is a photoelectric conversion device including: a semiconductor substrate having a photoelectric conversion unit; a first conductive layer formed over the semiconductor substrate; a first diffusion prevention layer formed over the first conductive layer; and a light guide that guides an incident light into the photoelectric conversion unit, in which the first diffusion prevention layer contains hydrogen atoms and carbon atoms, and a composition ratio of the hydrogen atoms is greater than or equal to 46 at % and less than or equal to 50 at %.. .
Canon Kabushiki Kaisha

Solid-state image pickup apparatus and manufacturing the same

Provided are a solid-state image pickup apparatus which includes: a semiconductor substrate having a plurality of photoelectric converters; a first and a second insulating layers formed on the semiconductor substrate; an optical waveguide formed above each of the plurality of photoelectric converters and in an opening portion of the first and the second insulating layers, and has a refractive index higher than a refractive index of the first insulating layer; and a light reflecting layer formed at a boundary between the optical waveguide and the second insulating layer, and has a refractive index lower than a refractive index of the optical waveguide, where the following expression is satisfied: α<90°, where a represents an angle formed by a boundary surface between the light reflecting layer and the second insulating layer with respect to a boundary surface between the first insulating layer and the second insulating layer.. .
Canon Kabushiki Kaisha

Solid-state imaging device

A solid-state imaging device includes a first semiconductor substrate in which first photoelectric conversion layers photoelectrically converting incident light in a first wavelength band are formed, a second semiconductor substrate in which second photoelectric conversion layers photoelectrically converting incident light are formed, a conductive layer disposed between the first semiconductor substrate and the second semiconductor substrate and having conductivity, an insulation film disposed between the second semiconductor substrate and the conductive layer and having an insulation property, in which light passing through the first photoelectric conversion layer, the conductive layer, and the insulation film is incident on the second semiconductor substrate, a predetermined voltage is applied to the conductive layer, and a wavelength of light in a second wavelength band photoelectrically converted by the second photoelectric conversion layer when the predetermined voltage is applied to the conductive layer is longer than when the predetermined voltage is not applied.. .
Olympus Corporation

Transistor display panel, manufacturing method thereof, and display device including the same

A transistor display panel including: a driving voltage line and a first electrode disposed on a substrate; a semiconductor overlapping the first electrode; and an electrode layer overlapping the semiconductor, the electrode layer including a drain electrode, a gate electrode, and a source electrode. The first electrode and the semiconductor are connected through the source electrode..
Samsung Display Co., Ltd.

Peeling method and manufacturing flexible device

A peeling method at low cost with high mass productivity is provided. An oxide layer is formed over a formation substrate, a first layer is formed over the oxide layer using a photosensitive material, an opening is formed in a portion of the first layer that overlaps with the oxide layer by a photolithography method and the first layer is heated to form a resin layer having an opening, a transistor including an oxide semiconductor in a channel formation region is formed over the resin layer, a conductive layer is formed to overlap with the opening of the resin layer and the oxide layer, the oxide layer is irradiated with light using a laser, and the transistor and the formation substrate are separated from each other..
Semiconductor Energy Laboratory Co., Ltd.

Peeling method and manufacturing flexible device

A peeling method at low cost with high mass productivity is provided. A resin layer having a thickness greater than or equal to 0.1 μm and less than or equal to 3 μm is formed over a formation substrate using a photosensitive and thermosetting material, a transistor including an oxide semiconductor in a channel formation region is formed over the resin layer, the resin layer is irradiated with light using a linear laser device, and the transistor and the formation substrate are separated from each other.
Semiconductor Energy Laboratory Co., Ltd.

Manufacturing array substrate, array substrate and display device

A manufacturing method of an array substrate is provided. The method includes sequentially depositing a first electrode layer and a gate metal layer on a base substrate, the first electrode layer including at least two conductive layers, formation materials of the at least two conductive layers having different etching rates.
Boe Technology Group Co., Ltd.

Semiconductor device, display module, and electronic appliance

The circuit includes a first transistor; a second transistor whose first terminal is connected to a gate of the first transistor for setting the potential of the gate of the first transistor to a level at which the first transistor is turned on; a third transistor for setting the potential of a gate of the second transistor to a level at which the second transistor is turned on and bringing the gate of the second transistor into a floating state; and a fourth transistor for setting the potential of the gate of the second transistor to a level at which the second transistor is turned off. With such a configuration, a potential difference between the gate and a source of the second transistor can be kept at a level higher than the threshold voltage of the second transistor, so that operation speed can be improved..
Semiconductor Energy Laboratory Co., Ltd.

Transistor and display device

It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material.
Semiconductor Energy Laboratory Co., Ltd.

Oxide semiconductor-based transistor and manufacturing the same

Disclosed are an oxide semiconductor-based transistor and a method of manufacturing the same. The oxide semiconductor-based transistor includes: a substrate provided with a bottom electrode; an insulator layer formed on the substrate; an active layer formed on the insulator layer; an electron transport layer formed on the active layer; and a top electrode formed on the electron transport layer.
Chungbuk National University Industry Academic Cooperation Foundation

Method for manufacturing semiconductor device

An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer..
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device, display device, and electronic device

A semiconductor device including: one or more pieces of first wiring having a main wiring section and a bifurcation wiring section; one or a plurality of pieces of second wiring having a trunk wiring section and a plurality of branch wiring sections within a gap region between the main wiring section and the bifurcation wiring section; one or a plurality of transistors each divided and formed into a plurality of pieces, the plurality of branch wiring sections individually functioning as a gate electrode and the one or plurality of transistors having a source region formed within the main wiring section and within the bifurcation wiring section and having a drain region formed between the plurality of branch wiring sections; and one or a plurality of pieces of third wiring electrically connected to the drain region of the one or plurality of transistors.. .
Japan Display Inc.

Display substrate, display device containing the same, and fabricating the same

The present disclosure provides a display substrate, including: a wiring mounting region. The wiring mounting region includes first wires and second wires, each of the first wires intersecting with one or more of the second wires, thereby defining one or more intersectional regions; and a semiconductor pattern between the first wire and the one or more second wires, the semiconductor pattern having at least one cross-sectional width covering at least a portion of at least one of the intersectional regions..
Beijing Boe Display Technology Co., Ltd.

Three-dimensional structured memory devices

A 3d structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region.
Micron Technology, Inc.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and at least one columnar member. The stacked body is provided on the substrate.
Toshiba Memory Corporation

Nonvolatile semiconductor devices including non-circular shaped channel patterns and methods of manufacturing the same

A non-volatile memory structure can include a substrate extending horizontally and a filling insulating pattern extending vertically from the substrate. A plurality of active channel patterns can extend vertically from the substrate in a zig-zag pattern around a perimeter of the filling insulating pattern, where each of the active channel patterns having a respective non-circular shaped horizontal cross-section.

Semiconductor structure having gate replacement and manufacturing the same

A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first stacked structures and two second stacked structures disposed on the substrate.
Macronix International Co., Ltd.

Self-aligned multiple patterning semiconductor device fabrication

Various embodiments provide a self-merged profile (smp) method for fabricating a semiconductor device and a device fabricated using an smp method. In an example embodiment, a semiconductor device is provided.
Macronix International Co., Ltd.

Method of forming semiconductor device including edge chip and related device

A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer..
Samsung Electronics Co., Ltd.

Semiconductor devices and methods of fabricating the same

semiconductor devices and method of manufacturing the same are provided. The devices may include a substrate including a first impurity region and second impurity regions spaced apart from the first impurity region and a conductive line.
Samsung Electronics Co., Ltd.

Nand string utilizing floating body memory cell

Nand string configurations and semiconductor memory arrays that include such nand string configurations are provided. Methods of making semiconductor memory cells used in nand string configurations are also described..
Zeno Semiconductor, Inc.

Semiconductor devices and methods of fabricating the same

A semiconductor device includes a substrate with an nmosfet region and a pmosfet region, a first active pattern on the nmosfet region, a second active pattern on the pmosfet region, a dummy pattern between the nmosfet and pmosfet regions, and device isolation patterns on the substrate that fill trenches between the first active pattern, the second active pattern, and the dummy pattern. Upper portions of the first and second active patterns have a fin-shaped structure protruding between the device isolation patterns.
Samsung Electronics Co., Ltd.

Fin field effect transistor and semiconductor device

A finfet including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively.
Taiwan Semiconductor Manufacturing Co., Ltd.

Bidirectional power semiconductor

A bidirectional power semiconductor device with full turn-off control in both current directions and improved electrical and thermal properties is provided, the device comprises a plurality of first gate commutated thyristor (gct) cells and a plurality of second gct cells alternating with each other, a first base layer of each first gct cell is separated from a neighbouring second anode layer of a neighbouring second gct cell by a first separation region, and a second base layer of each second gct cell is separated from a neighbouring first anode layer of a neighbouring first gct cell by a second separation region.. .
Abb Schweiz Ag

Method and system for a semiconductor device with integrated transient voltage suppression

A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (tvs) device formed of a wide band gap material, the tvs device formed with the transistor as a single semiconductor device, the tvs device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the tvs device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value..
General Electric Company

Semiconductor device having multiple gate pads

Disclosed are semiconductor devices that include additional gate pads, and methods of fabricating and testing such devices. A device may include a first gate pad, a second gate pad, and a third gate pad.
Vishay-siliconix

Semiconductor device in a level shifter with electrostatic discharge (esd) protection circuit and semiconductor chip

The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (esd) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static esd stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the esd stress by using esd stress blocking region adjacent to a gate electrode of the semiconductor device.
Magnachip Semiconductor, Ltd.

Semiconductor layout structure

A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged.
United Microelectronics Corp.

Fabricating a semiconductor light emitting device

A fabricating method of a semiconductor light emitting device includes disposing a plurality of non-conductive walls on a substrate. An alignment position is formed between every two adjacent non-conductive walls.
Industrial Technology Research Institute

Semiconductor device and structure

A 3d semiconductor device and structure, including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, and where the second die has a thickness of less than four microns.. .
Monolithic 3d Inc.

Computer modules with small thicknesses and associated methods of manufacturing

Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material.
Micron Technology, Inc.

Stack-type semiconductor package

A semiconductor package includes a lower package including a lower package substrate, a lower semiconductor chip disposed on the lower package substrate, and a lower mold layer disposed on the lower package substrate, and an upper package disposed on the lower package. The upper package includes an upper package substrate and an upper semiconductor chip disposed on the upper package substrate.

Semiconductor package and manufacturing method thereof

Provided are a semiconductor package and a manufacturing method thereof for securing a space for mounting a semiconductor device by etching a temporary metal plate to form a plurality of conductive posts.. .
Amkor Technology, Inc.

Semiconductor packages including chip enablement pads

A semiconductor package includes a package substrate and semiconductor chips stacked on the package substrate. The package substrate may include at least one first chip enablement finger, at least one second chip enablement finger, and a chip enablement pad selection finger.
Sk Hynix Inc.

Semiconductor device that includes a molecular bonding layer for bonding elements

A semiconductor device includes a semiconductor chip covered with a resin layer, the semiconductor chip including an electrode pad at a surface of the semiconductor chop, a first insulating layer covering the surface of the semiconductor chip and having a via hole at a region corresponding to the electrode pad, a conductive layer extending along a surface of the electrode pad, a side surface of the via hole, and a planar surface the first insulating layer to a region beyond a planar region defined by the semiconductor chip. A molecular bonding layer is between the first insulating layer and the conductive layer and includes a molecular portion covalently bonded to a material of the first insulating layer and a material of the first insulating layer.
Kabushiki Kaisha Toshiba

Passive element package and semiconductor module comprising the same

A passive element package includes a first substrate, first passive elements disposed on the first substrate, a second substrate disposed on the first passive elements, second passive elements disposed on the second substrate, and a sealant that seals the first passive elements and the second passive elements. The passive element package can reduce the size of a semiconductor module that includes the passive element package..
Samsung Electronics Co., Ltd.

Semiconductor device and using a standardized carrier to form embedded wafer level chip scale packages

A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material.
Stats Chippac Pte. Ltd.

Sinterable bonding material and semiconductor device using the same

An objective of the present invention is to provide a sinterable bonding material capable of providing a bonded article having a long-term reliability. The present invention relates to a sinterable bonding material comprising a silver filler and resin particles, wherein the silver filler comprises a flake-shaped filler having an arithmetic average roughness (ra) of 10 nm or less; and the resin particles have an elastic modulus (e) of 10 gpa or less, and a heat decomposition temperature of 200° c.
Henkel Ip & Holding Gmbh

Semiconductor packages and methods for forming semiconductor package

semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof.
Utac Headquarters Pte. Ltd.

Semiconductor device and manufacturing the same

A semiconductor device includes a semiconductor substrate with a wiring layer formed thereon, an insulating film formed on the semiconductor substrate so as to cover the wiring layer and having a pad opening exposing a portion of the wiring layer as a pad, a front surface protection film formed on the insulating film and being constituted of an insulating material differing from the insulating film and having a second pad opening securing exposure of at least a portion of the pad, a seed layer formed on the pad, and a plating layer formed on the seed layer.. .
Rohm Co., Ltd.

Semiconductor device that includes a molecular bonding layer for bonding of elements

A semiconductor device includes a semiconductor chip covered with a resin layer, the semiconductor chip including an electrode pad at a surface of the semiconductor chip, a first insulating layer covering the surface of the semiconductor chip and having a via hole at a region corresponding to the electrode pad, a conductive layer extending along a surface of the electrode pad, a side surface of the via hole, and a planar surface the first insulating layer, to a region beyond a planar region defined by the semiconductor chip, a second insulating layer on the first insulating layer and covering the conductive layer; and a molecular bonding layer formed between the first insulating layer and the second insulating layer and including a molecular portion covalently bonded to a material of the conductive layer and a material of the second insulating layer.. .
Kabushiki Kaisha Toshiba

Sinterable bonding material and semiconductor device using the same

An objective of the present invention is to provide a sinterable bonding material excellent in sinterability. The present invention relates to a sinterable bonding material comprising a silver filler and an organic base compound as a sintering promoter..
Henkel Ip & Holding Gmbh

Semiconductor device that includes a molecular bonding layer for bonding elements

A semiconductor device includes a base, a semiconductor chip on the base, a conductive bonding layer between a surface of the base and a surface of the semiconductor chip, the conductive bonding layer including a resin and a plurality of conductive particles contained in the resin, and a molecular bonding layer between the surface of the semiconductor chip and a surface of the conductive bonding layer, and including a molecular portion covalently bonded to a material of the semiconductor chip and a material of the conductive bonding layer.. .
Kabushiki Kaisha Toshiba

Semiconductor device having a molecular bonding layer for bonding elements

A semiconductor device includes a substrate including, on a surface thereof, a first conductive pad and a first insulating layer formed around the first conductive pad, a semiconductor chip including, on a surface thereof, a second conductive pad and a second insulating layer around the second conductive pad, an intermediate layer formed between the substrate and the semiconductor chip, and including a conductive portion between the first and second conductive pads, and an insulating portion between the first and second insulating layers, and a molecular bonding layer formed between the substrate and the intermediate layer, and including at least one of a first molecular portion covalently bonded to a material of the first conductive pad and a material of the conductive portion, and a second molecular portion covalently bonded to a material of the first insulating layer and a material of the insulating portion.. .
Kabushiki Kaisha Toshiba

Pre-plated substrate for die attachment

A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer.
Freescale Semiconductor, Inc.

Semiconductor structures and fabrication methods thereof

A method for fabricating a semiconductor structure includes providing a wafer and a carrier wafer. The wafer includes a first bonding surface and a plurality of radio-frequency (rf) devices and the carrier wafer includes a second bonding surface.
Semiconductor Manufacturing International (beijing) Corporation

Semiconductor package structure, package on package structure and packaging method

A semiconductor package structure includes a substrate, a first semiconductor device, a first encapsulant and a second encapsulant. The substrate has a first coefficient of thermal expansion cte1.
Advanced Semiconductor Engineering, Inc.

Field-effect transistor, manufacturing the same, and radio-frequency device

There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.. .
Sony Corporation

Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s)

Disclosed are semiconductor structures comprising a field effect transistor (fet) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region.
Globalfoundries Inc.

Semiconductor structure having etching stop layer and manufacturing the same

A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a stack structure, an etching stop layer, and a conductive structure.
Macronix International Co., Ltd.

Semiconductor device structures including staircase structures, and related methods and electronic systems

A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers.
Micron Technology, Inc.

Semiconductor interconnect structure with double conductors

Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between.
International Business Machines Corporation

Semiconductor interconnect structure with double conductors

Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between.
International Business Machines Corporation

Semiconductor device and forming the same

A semiconductor device with a ring structure surrounding a through silicon via (tsv) electrode and a method for forming the same are disclosed. The method includes receiving a substrate including a back side and a front side having a conductor thereon, forming a via hole in the substrate and exposing the conductor, forming a groove extending from the back side into the substrate and surrounding the via hole, forming a first material layer in the via hole, and forming a second material layer in the groove.
Nanya Technology Corporation

Method for forming an electrical contact between a semiconductor film and a bulk handle wafer, and resulting structure

A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer.
Stmicroelectronics (crolles 2) Sas

Method to fabricate a high performance capacitor in a back end of line (beol)

A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the patterned mask a material formation trench intermediate first and second spaced apart metal formations formed in the dielectric layer, and disposing a dielectric material formation in the material formation trench.. .
Globalfoundries Inc.

Multi-tier three-dimensional memory devices including vertically shared source lines and making thereof

A multi-tier memory device includes a first tier structure overlying a substrate and containing a first alternating stack of first insulating layers and first electrically conductive layers, and first memory stack structures each including a first memory film and a first vertical semiconductor channel, a source line overlying the first tier structure, and a second tier structure overlying the source line and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory stack structures each including a second memory film and a second vertical semiconductor channel.. .
Sandisk Technologies Llc

Reliable packaging and interconnect structures

Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material.
Tessera, Inc.

Robust low inductance power module package

A method and system for a power module is provided. The power module includes a first substrate including a first conductive substrate having a first plurality of power semiconductor switches arranged thereon, and at least one second conductive substrate electrically coupled to the first conductive substrate.
General Electric Company

Fabrication semiconductor package

A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods..
Siliconware Precision Industries Co., Ltd.

Semiconductor package and a substrate for packaging

A semiconductor package is provided, which includes: a substrate having a metal pattern layer; a semiconductor die formed on the substrate; and an underfill filled between the substrate and the semiconductor die. At least an opening is formed in the metal pattern layer to reduce the area of the metal pattern layer on the substrate, thereby reducing the contact area between the underfill and the metal pattern layer, hence eliminating the underfill delamination..
Siliconware Precision Industries Co., Ltd.

Method of producing lead frames for electronic components, corresponding component and computer program product

An electronic component, in one embodiment, includes a semiconductor die, a die pad supporting the semiconductor die, and a plurality of leads that include a first set of metal lines and a second set of metal lines. The first set of metal lines cross over the second set of metal lines at crossings.
Stmicroelectronics S.r.l.

Power semiconductor device and manufacturing the same

A power semiconductor device includes a power semiconductor element, a controlling element, a first lead frame and a second lead frame, respectively, a first metal wire electrically connecting the power semiconductor element and the first lead frame, and a sealing body covering these components. The first lead frame includes a first inner lead having a connecting surface to which one end of the first metal wire is connected.
Mitsubishi Electric Corporation

Semiconductor device

A semiconductor part includes a resin package and an exposed portion exposed from a bottom surface of the resin package. The exposed portion has a first diagonal line perpendicular to both first and third sides of the package as viewed from the bottom surface.
Rohm Co., Ltd.

Semiconductor device

A semiconductor device includes: a semiconductor element disposed on a semiconductor substrate; a first insulating film disposed on the semiconductor substrate, the first insulating film having an upper surface and an edge; a resin layer disposed on the semiconductor substrate, the resin layer covering the semiconductor element; and a second insulating film disposed on the semiconductor substrate, the second insulating film covering the upper and side surfaces of the resin layer, wherein the second insulating film has an edge arranged apart from the side surface of the resin layer by a distance, and the distance between the edge of the second insulating film and the side surface of the resin layer is greater than a film thickness of the second insulating film.. .
Sumitomo Electric Industries, Ltd.

Formation of getter layer for memory device

A method includes providing a semiconductor device disposed on a substrate, wherein the semiconductor device includes a semiconductor device feature, forming a conductive layer over the substrate such that the conductive layer is electrically coupled to the semiconductor device feature, forming a getter layer over the conductive layer, wherein the getter layer includes a first layer that is formed of titanium and a second layer overlying the first layer that is formed of tantalum nitride, and forming an interconnect layer over the getter layer such that the interconnect layer is electrically coupled to the semiconductor device feature.. .
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor package with elastic coupler and related methods

Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.. .
Semiconductor Components Industries, Llc

Semiconductor device

Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.. .
Samsung Electronics Co., Ltd.

Semiconductor device including a field effect transistor and manufacturing the same

A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern..
Samsung Electronics Co., Ltd.

Stacked nanowire devices

A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.. .
International Business Machines Corporation

Co-integration of silicon and silicon-germanium channels for nanosheet devices

Nanosheet semiconductor devices and methods of forming the same include forming a first stack in a first device region, the first stack including layers of a first channel material and layers of a sacrificial material. A second stack is formed in a second device region, the second stack including layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material.
International Business Machines Corporation

Semiconductor devices including active fins and methods of manufacturing the same

semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate.
Samsung Electronics Co., Ltd.

Integration of nominal gate width finfets and devices having larger gate width

A starting semiconductor structure includes a layer of filler material (e.g., amorphous silicon), a hard mask layer over the layer of filler material, and filler material lines over the hard mask layer. A protective layer is formed over one or more, but less than all of the filler material lines, at least one protected filler material line and at least one unprotected filler material line have a same width, and, after forming the protective layer, oxidizing unprotected filler material lines, such that the oxidized unprotected line(s) have a larger width than the protected filler material line(s)..
Globalfoundries Inc.

Semiconductor device and manufacturing method thereof

A semiconductor device with a through via penetrating a semiconductor substrate, in which shorting between a wiring and a semiconductor element is prevented to improve the reliability of the semiconductor device. A liner insulating film as a low-k film, which has a function to insulate the semiconductor substrate and a through-silicon via from each other and is thick enough to reduce capacitance between the semiconductor substrate and the through-silicon via, is used as an interlayer insulating film for a first wiring layer over a contact layer.
Renesas Electronics Corporation

Electrical conductive vias in a semiconductor substrate and a corresponding manufacturing method

A method is provided for producing at least one electrical via in a substrate, the method comprising: producing a protective layer over a component structure which has been produced or is present on a front side of the substrate; forming at least one contact hole which extends from a surface of a backside of the substrate to a contact surface of the component structure; forming a metal-containing and thus conductive lining in the at least one contact hole creating a hollow electrically conductive structure in the at least one contact hole; and applying a passivation layer over the backside of the substrate, the passivation layer spanning over the hollow electrically conductive structure for forming the at least one electrical via. Also provided is a micro-technical component comprising at least one electrical via..
X-fab Semiconductor Foundries Ag

Gate aligned contact and method to fabricate same

Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate.
Intel Corporation

Two-dimensional self-aligned super via integration on self-aligned gate contact

Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts.
Globalfoundries, Inc.

Two-dimensional self-aligned super via integration on self-aligned gate contact

Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts.
Globalfoundries, Inc.

Method and manufacturing semiconductor device

Provided are a method and an apparatus for manufacturing a semiconductor device. The method comprises: forming a first wiring layer on a base substrate; forming an interlayer dielectric layer on the first wiring layer, with contact holes being provided in the interlayer dielectric layer; subjecting bottoms of the contact holes to a dry cleaning process; and forming a second wiring layer on the interlayer dielectric layer, wherein the second wiring layer is electrically connected to the first wiring layer via the contact holes..
Boe Technology Group Co., Ltd.

Semiconductor device manufacturing method, coating formation method, and coating formation device

In the present method, a substrate to be processed, having an interlayer insulation film, is prepared (step 1). The interlayer insulation film is subjected to dry etching, while using a mask layer, thereby forming recesses (step 2).
Tokyo Electron Limited

Etching method and fabrication semiconductor structures

An etching method and a fabrication method of semiconductor structures are provided. The etching method includes forming trenches in a to-be-etched structure, and forming a dielectric layer in the trenches.
Semiconductor Manufacturing International (beijing) Corporation

Bulk to silicon on insulator device

A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin.
International Business Machines Corporation

Methods for sio2 filling of fine recessed features and selective sio2 deposition on catalytic surfaces

Methods for void-free sio2 filling of fine recessed features and selective sio2 deposition on catalytic surfaces are described. According to one embodiment, the method includes providing a substrate containing recessed features, coating surfaces of the recessed features with a metal-containing catalyst layer, in the absence of any oxidizing and hydrolyzing agent, exposing the substrate at a substrate temperature of approximately 150° c.
Tokyo Electron Limited

Semiconductor devices

semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom.
Samsung Electronics Co., Ltd.

Devices and methods for dynamically tunable biasing to backplates and wells

Devices and methods of fabricating integrated circuit devices for dynamically applying bias to back plates and/or p-well regions are provided. One method includes, for instance: obtaining a wafer with a silicon substrate, at least one first oxide layer, at least one silicon layer, and at least one second oxide layer; forming at least one recess in the wafer; depositing at least one third oxide layer over the wafer and filling the at least one recess; depositing a silicon nitride layer over the wafer; and forming at least one opening having sidewalls and a bottom surface within the filled at least one recess.
Globalfoundries Inc.

Semiconductor processing chamber

A semiconductor processing apparatus is described that has a body with a wall defining two processing chambers within the body; a passage through the wall forming a fluid coupling between the two processing chambers; a lid removably coupled to the body, the lid having a portal in fluid communication with the passage; a gas activator coupled to the lid outside the processing chambers, the gas activator having an outlet in fluid communication with the portal of the lid; a substrate support disposed in each processing chamber, each substrate support having at least two heating zones, each with an embedded heating element; a gas distributor coupled to the lid facing each substrate support; and a thermal control member coupled to the lid at an edge of each gas distributor.. .
Applied Materials, Inc.

Collection chamber apparatus to separate multiple fluids during the semiconductor wafer processing cycle

The wafer processing system includes a rotatable wafer support member for supporting a wafer and a plurality of collections trays disposed about a peripheral edge of the wafer support member. The collection trays are arranged in a stacked configuration, each collection tray having an inner wall portion and an outer wall portion that converge to define a trough section for collecting fluid.
Veeco Precision Surface Processing Llc

Hkmg integration

A method for processing a semiconductor substrate is described herein. The method described herein includes generating fluorine radicals and ions, delivering the fluorine radicals through an ion blocker to a processing region, and removing one or more portions of a gate structure to expose one or more portions of a gate dielectric material disposed thereunder.
Applied Materials, Inc.

Substrate processing device, manufacturing semiconductor device, and reaction tube

A substrate processing apparatus includes: a substrate holding member configured to hold a plurality of substrates; a reaction tube configured to accommodate the substrate holding member and process the substrates; a processing gas supply system configured to supply a processing gas into the reaction tube; and an exhaust system configured to exhaust an internal atmosphere of the reaction tube. The reaction tube includes: a cylindrical portion; a gas supply area formed outside one side wall of the cylindrical portion and connected to the processing gas supply system; and a gas exhaust area formed outside the other side wall of the cylindrical portion opposed to the gas supply area and connected to the exhaust system.
Hitachi Kokusai Electric Inc.

Hydrogenation annealing method using microwave

Provided is a hydrogenation annealing method using a microwave, which performs hydrogenation annealing at a low temperature and with low power in a manufacturing process of a thin film transistor (tft) for a display device. The hydrogenation annealing method is constituted by a loading step of loading a device requiring hydrogenation annealing into a chamber and an annealing step of irradiating a microwave having a frequency in an industrial scientific medical (ism) band into the chamber into which the device is loaded.
Cmtech21 Co., Ltd.

Semiconductor structure and fabrication method thereof

A method is provided for fabricating a semiconductor structure. The method includes providing a substrate having a dielectric layer formed on the substrate, where an opening is formed in the dielectric layer, and bottom of the opening exposes surface of the substrate.
Semiconductor Manufacturing International (beijing) Corporation

Oxidizing and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines

A method includes, for example, providing a starting semiconductor structure having a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a protective layer over a portion of at least one material line, the at least one protected material line and at least one unprotected material line having a same critical dimension, oxidizing the at least one unprotected material line to increase the critical dimension compared to the first critical dimension of the at least one protected material line, and etching at least a portion of the oxidized unprotected material line so that the etched critical dimension of the at least one etched material line is different from the first critical dimension of the at least one protected material line.. .
Globalfoundries Inc.

Protecting, oxidizing, and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines

A method includes, for example, a starting semiconductor structure comprising a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a first protective layer over some of the plurality of material lines, the protected material lines and the unprotected material lines having a same corresponding first critical dimension, oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased second critical dimension greater than the first critical dimension, removing the first protective layer, forming a second protective layer over some of the plurality of protected material lines having the first critical dimension and some of the oxidized material lines having the second critical dimension, and oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased third critical dimension greater than the first critical dimension.. .
Globalfoundries Inc.

Fabrication of semiconductor structures

The invention relates to a method for fabricating a semiconductor circuit comprising providing a semiconductor substrate; fabricating a first semiconductor device comprising a first semiconductor material on the substrate and forming an insulating layer comprising a cavity structure on the first semiconductor device. The cavity structure comprises at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening.
International Business Machines Corporation

Formation of a layer on a semiconductor substrate

Described herein are techniques for forming an epitaxial iii-v layer on a substrate. In a pre-clean chamber, a native oxygen layer may be replaced with a passivation layer by treating the substrate with a hydrogen plasma (or products of a plasma decomposition).
Aixtron Se

Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium

There is provided a method of manufacturing a semiconductor device, comprising forming a film on a substrate in a process chamber by performing a cycle a predetermined number of times. The cycle includes alternately performing supplying a halogen-based first process gas to the substrate in the process chamber, and supplying a non-halogen-based second process gas to the substrate in the process chamber.
Hitachi Kokusai Electric Inc.

Oxidizing filler material lines to increase width of hard mask lines

A starting semiconductor structure includes a layer of filler material, a hard mask layer over the layer of filler material, and filler material lines over the hard mask layer. The starting semiconductor structure is placed in an etching chamber, and oxygen gas and high plasma power are inserted into the etching chamber and oxidizing, resulting in one or more of the filler material lines being oxidized, the filler material line(s) increasing in width from oxidizing, and etching the hard mask layer with a chemistry that is non-selective to the oxidized filler material lines and hard mask layer, and which has a stronger lateral etch selectivity to the oxidized filler material lines than the hard mask layer..
Globalfoundries Inc.

Semiconductor device manufacturing method, substrate processing apparatus, and recording medium

A method includes forming a film on a substrate by performing a cycle n times (where n is an integer equal to or greater than 1), the cycle including alternately performing: performing a set m times (where m is an integer equal to or greater than 1), the set including supplying a precursor to the substrate and supplying a borazine compound to the substrate; and supplying an oxidizing agent to the substrate.. .
Hitachi Kokusai Electric Inc.

Method of growing a high quality iii-v compound layer on a silicon substrate

The present disclosure involves a method of fabricating a semiconductor device. A surface of a silicon wafer is cleaned.
Epistar Corporation

Semiconductor device and related manufacturing method

A semiconductor device may include the following elements: a semiconductor substrate, an insulator positioned on the substrate, a source electrode positioned on the insulator, a drain electrode positioned on the insulator, a gate electrode positioned between the source electrode and the drain electrode, a hallow channel surrounded by the gate electrode and positioned between the source electrode and the drain electrode, a dielectric member positioned between the hollow channel and the gate electrode, a first insulating member positioned between the gate electrode and the source electrode, and a second insulating member positioned between the gate electrode and the drain electrode.. .
Semiconductor Manufacturing International (shanghai) Corporation

Memory cells, memory cell arrays, methods of using and methods of making

A semiconductor memory cell and arrays of memory cells are provided in at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.. .
Zeno Semiconductor, Inc.

Electronic device

An electronic device including a semiconductor memory. The semiconductor memory may include a cell array including a plurality of resistive storage cells; a current code generation block suitable for generating a current code which has a value corresponding to an average value of current amounts of test currents respectively flowing through at least two first resistive storage cells among the plurality of resistive storage cells, in a test operation; and a sensing block suitable for comparing a read current flowing through a second resistive storage cell selected among the plurality of resistive storage cells with a reference current, and thereby sensing data of the second resistive storage cell, wherein the semiconductor memory is operable to adjust a current amount of at least one current flowing through the sensing block based on the value of the current code..
Sk Hynix Inc.

Semiconductor structure and memory device including the structure

A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region.
Stmicroelectronics (rousset) Sas



Semiconductor topics:
  • Semiconductor
  • Semiconductor Substrate
  • Semiconductor Device
  • Semiconductor Material
  • Electric Conversion
  • Conductive Layer
  • Molybdenum
  • Camera Module
  • Semiconductor Devices
  • Semiconductors
  • Integrated Circuit
  • Surfactant
  • Photoelectric Conversion
  • Electronic Device
  • Transparent Conductive Oxide


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