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Semiconductor patents

      

This page is updated frequently with new Semiconductor-related patent applications.




 Semiconductor integrated circuit device, printed board and manufacturing  the semiconductor integrated circuit device patent thumbnailSemiconductor integrated circuit device, printed board and manufacturing the semiconductor integrated circuit device
A semiconductor integrated circuit device (101) includes a component built-in board (21) in which at least a first core layer (co21) on which a first electronic component (c21) is mounted, a second core layer (co22) on which a second electronic component (c22) is mounted, an adhesive layer (ad21) arranged between the first core layer (co21) and the second core layer (co22), and wiring layers (l21-l28) are stacked; a third electronic component (soc) mounted in a first core layer (co21) side of the component built-in board (21) and electrically connected to at least one of the first and second electronic components (c21, c22) through the wiring layers (l21 to l28); and an external connection terminal (be) formed in a second core layer (co22) side of the component built-in board (21) and electrically connected to at least one of the first and second electronic components (c21, c22).. .
Renesas Electronics Corporation


 Illuminator with engineered illumination pattern patent thumbnailIlluminator with engineered illumination pattern
Techniques for tuning the illumination pattern of a light emitting diode (led) are described. An example image capture system incorporates an led with an integrated micro-reflector.
Intel Corporation


 Isolating noise sources and coupling fields in rf chips patent thumbnailIsolating noise sources and coupling fields in rf chips
A semiconductor die comprises a first active device, at least one of a second active device and a passive component, and electromagnetic shielding configured to at least partially electromagnetically isolate the first active device from the at least one of the second active device and the passive component. The electromagnetic shielding includes one of a grounded metal layer and via stack, and a grounded metal layer disposed one of above and below the first active device..
Skyworks Solutions, Inc.


 Series regulator and semiconductor integrated circuit patent thumbnailSeries regulator and semiconductor integrated circuit
The series regulator has: a differential amplifier; a level shifter including a level shift transistor with a drain connected to a gate; and a source follower including an output transistor. The differential amplifier includes an amplification stage having a non-inverting input terminal for input of a reference voltage, an inverting input terminal for input of a feedback voltage, and an amplifier output terminal.
Synaptics Japan Gk


 Semiconductor device including buffer circuit patent thumbnailSemiconductor device including buffer circuit
A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal.
Micron Technology, Inc.


 Semiconductor device, power conversion apparatus, and vehicle patent thumbnailSemiconductor device, power conversion apparatus, and vehicle
A semiconductor device according to an embodiment includes: a first transistor having a first electrode, a second electrode, and a first control electrode, the first transistor performing a switching operation; a second transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, the second transistor performing an analog operation; and a third transistor having a fifth electrode electrically connected to the fourth electrode, a sixth electrode, and a third control electrode.. .
Kabushiki Kaisha Toshiba


 Power conversion device patent thumbnailPower conversion device
An object of the invention is to suppress that resistance against vibrations is reduced, while reducing the number of components. A power conversion device according to the present invention includes: a power semiconductor module that converts a dc current into an ac current; a plate conductor that transfers the dc current or the ac current; a resin sealing material that seals the plate conductor; and an electric component that is used to control the power semiconductor module, wherein the resin sealing material includes a supporting member that supports the electric component, and wherein the plate conductor is buried in a portion of the resin sealing material that is disposed to face the electric component..
Hitachi Automotive Systems, Ltd.


 Non-isolated power supply device patent thumbnailNon-isolated power supply device
The present invention addresses the problem of detecting the timing at which an inductor current becomes zero, turning on a switching element at the optimal timing, and enhancing power efficiency without increasing part quantity or external terminal quantity. A control circuit is configured from a semiconductor integrated circuit; is provided with a first external terminal to which a voltage produced by the conversion of the current flowing through a switching element by a current-to-voltage conversion element is input, a second external terminal to which the voltage of a point of contact of an inductor and rectification element or a voltage proportional thereto is input, a filter for smoothing the voltage input into the second external terminal, and a voltage comparison circuit for comparing the voltage smoothed by the filter and the voltage input into the second external terminal; and performs control such that the switching element is switched from off to on near the point where the inductor current becomes zero on the basis of the voltage comparison circuit output and the switching element is switched from on to off in response to the voltage applied to the first external terminal reaching a prescribed voltage..
Mitsumi Electric Co., Ltd.


 Integrated circuits patent thumbnailIntegrated circuits
A semiconductor integrated circuit device comprises at least first and second circuits said first and second circuits being connected to a shared external connection. The device further comprises a voltage clamp that is operable to limit a voltage at the shared external connection.
Nordic Semiconductor Asa


 Semiconductor optical device patent thumbnailSemiconductor optical device
A semiconductor optical device includes an active layer, the active layer including a plurality of quantum well layers having gain peak wavelengths different from one another in a layering direction thereof, and a plurality of barrier layers, wherein the quantum well layers and the barrier layers are alternately layered over each other, and an n-type dopant has been added in the plurality of quantum well layers having gain peak wavelengths different from one another and in the plurality of barrier layers.. .
Furukawa Electric Co., Ltd.


Surface emitting laser, information acquiring apparatus, imaging apparatus, laser array, and manufacturing surface emitting laser

A surface emitting laser includes a first reflecting mirror (102); a second reflecting mirror (116); and an active layer (104) arranged between the first reflecting mirror (102) and the second reflecting mirror (116), a gap being formed between the second reflecting mirror (116) and the active layer (104), an oscillation wavelength being tunable. The second reflecting mirror (116) includes a beam (108) comprising a single-crystal semiconductor, and a dielectric multilayer film (110) supported by the beam (108), and the dielectric multilayer film (110) is arranged in an opening (118) formed in the beam (108)..

Quantum cascade laser integrated device

A quantum cascade laser integrated device includes: first and second lower semiconductor mesas extending in a direction of a first axis; a covering region disposed on top and side faces of the first and second lower semiconductor mesas, and including a first and second upper semiconductor mesas, the first and second upper semiconductor mesas extending in the direction of the first axis on the first and second lower semiconductor mesas, respectively; and a first and second electrodes disposed on the second upper semiconductor mesa, the first lower semiconductor mesa and the second lower semiconductor mesa each including a quantum cascading core layer, the covering region including a current blocking semiconductor region embedding the first and second lower semiconductor mesas, and a first conductivity-type semiconductor region disposed on the first and second lower semiconductor mesas and the current blocking semiconductor region, and the conductivity-type semiconductor region including an upper cladding region.. .
Sumitomo Electric Industries, Ltd.

Tunable laser source

The invention relates to a tunable laser source, and the reduction in the loss and the size can both be achieved in a tunable laser source having a power monitor and a wavelength locker function. A tunable laser is formed of a semiconductor optical amplifier and a resonator, and one of the two output light beams split from part of the light within the tunable laser by a 2×2 type optical splitter is incident into a light intensity monitor, and the other is incident into a wavelength locker..
Fujitsu Optical Components Limited

Semiconductor laser light source device, semiconductor laser light source system, and image display apparatus

The object is to provide a technique that allows a semiconductor laser to be efficiently cooled. A semiconductor laser light source device includes: a semiconductor laser; a cooler that cools the semiconductor laser; and a driving substrate that drives the semiconductor laser.
Mitsubishi Electric Corporation

Rare earth pnictides for strain management

Systems and methods described herein may include a first semiconductor layer with a first lattice constant, a rare earth pnictide buffer epitaxially grown over the first semiconductor, wherein a first region of the rare earth pnictide buffer adjacent to the first semiconductor has a net strain that is less than 1%, a second semiconductor layer epitaxially grown over the rare earth pnictide buffer, wherein a second region of the rare earth pnictide buffer adjacent to the second semiconductor has a net strain that is a desired strain, and wherein the rare earth pnictide buffer may comprise one or more rare earth elements and one or more group v elements. In some examples, the desired strain is approximately zero..
Iqe, Plc

Tunable laser

A tunable laser includes a semiconductor optical amplifier, a waveguide wavelength-tunable filter that forms the tunable laser with the semiconductor optical amplifier, an optical splitting mechanism set on a coupling optical waveguide that couples the wavelength-tunable filter and the semiconductor optical amplifier, a first optical splitter of a waveguide type that splits at least part of a light beam split by the optical splitting mechanism into two light beams, a first optical waveguide coupled to one output end of the first optical splitter, a second optical waveguide that is coupled to another output end of the first optical splitter and includes a delay waveguide, a 90° hybrid waveguide that includes two input ports to which an output light beam from the first optical waveguide and an output light beam from the second optical waveguide are input and four output ports that output four output light beams.. .
Fujitsu Limited

Apparatus and forming organic thin film transistor

A method for forming an organic thin film transistor is provided. An organic semiconductor layer, a source electrode, a drain electrode, a gate electrode, and an insulating layer are formed on an insulating substrate.
Hon Hai Precision Industry Co., Ltd.

Electronic device and fabricating the same

An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer..
Sk Hynix Inc.

Method for manufacturing semiconductor structure

A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a substrate; forming an mram structure over the substrate; forming a first dielectric layer over the mram structure; forming a stop layer over the first dielectric layer; forming a second dielectric layer over the stop layer; and removing the second dielectric layer, the stop layer and at least a portion of the first dielectric layer through a planarization operation without exposing a top electrode of the mram structure.
Taiwan Semiconductor Manufacturing Company Ltd.

Semiconductor memory device

A semiconductor memory device that includes at least a lower contact plug on a semiconductor substrate, a magnetic tunnel junction of the lower contact plug, and a barrier pattern on a sidewall of the lower contact plug may further include an insulation pattern on the sidewall of the lower contact plug. The insulation pattern may be between the barrier pattern and the magnetic tunnel junction pattern.

Flexible peltier device and temperature regulation apparatus

A flexible peltier device in which emitting heat conversion properties between peltier elements and an object transferring heat may be improved and a flexible heat-emitting sheet having the peltier elements bonded thereto may be bent without worrying the separation there between. A flexible peltier device includes a single or plural peltier element which is disposed on one surface side of a heat-emitting sheet having flexibility made from heat-conductive rubber containing a heat conductive filler and each semiconductor element which has a heating side and a cooling side and composes the peltier element at least one of the heating side and the cooling side is bonded integrally to the heat-emitting sheet by a direct covalent bond and/or by an indirect covalent bond through a molecular adhesive at active groups existing on each other surfaces..
Asahi Fr R&d Co., Ltd.

Semiconductor light source

A light source may comprise a thermally conductive frame comprising a base and a faceted portion extending from the base. The faceted portion may comprise a plurality of facets spaced circumferentially thereabout.
Epistar Corporation

Light emitting device with wavelength converting side coat

Embodiments of the invention include a semiconductor light emitting device, a first wavelength converting member disposed on a top surface of the semiconductor light emitting device, and a second wavelength converting member disposed on a side surface of the semiconductor light emitting device. The first and second wavelength converting members include different wavelength converting materials..
Koninklijke Philips N.v.

Light emitting diode for surface mount technology, manufacturing the same, and manufacturing light emitting diode module

A light emitting diode (led) includes a substrate, a first semiconductor layer disposed on the substrate, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer, a first conductive layer disposed on a portion of the second semiconductor layer, a second conductive layer disposed on the second semiconductor layer, and an insulation layer including a first insulating layer and a second insulating layer disposed on the first insulating layer, and overlapping the first semiconductor layer, the second semiconductor layer, and the second conductive layer, in which the insulation layer has a first region having different thicknesses and a second region having a substantially constant thickness.. .
Seoul Viosys Co., Ltd.

Light emitting device, light emitting device package, light unit, and manufacturing same

The embodiment relates to a light emitting device, a method of fabricating the same, a light emitting device package, and a lighting system. According to the embodiment, a light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, a first electrode electrically connected with the first conductive semiconductor layer, a second electrode electrically connected with the second conductive semiconductor layer, an insulating member provided on the light emitting structure while exposing the first electrode and the second electrode, a third electrode provided on the first electrode, and a fourth electrode provided on the second electrode.
Lg Innotek Co., Ltd.

Light-emitting device and manufacturing light-emitting device

A light-emitting device including a window layer-cum-support substrate, a light-emitting portion provided on the window layer-cum-support substrate and including a second semiconductor layer of a second conductivity type, an active layer, and first semiconductor layer of a first conductivity type in stated order, a first ohmic electrode provided on the first semiconductor layer, and insulator top coat at least partially coating the first semiconductor layer surface and light-emitting portion side surface, wherein the first semiconductor layer surface and surface of the window layer-cum-support substrate are roughened, and the first semiconductor layer includes at least two layers of an active-layer-side layer and roughened-side layer, and roughened-side layer is formed of material having lower al content than the active-layer-side layer. This light-emitting device can reduce etching depth required to obtain desired roughened shape and inhibit occurrence of chip cracks during wire bonding, while keeping effect of trapping carriers in the clad layer..
Shin-etsu Handotai Co., Ltd.

Light-emitting device and manufacturing method thereof

The present disclosure provides a light-emitting device and manufacturing method thereof. The light-emitting device comprising: a light-emitting stack; and a semiconductor layer having a first surface connecting to the light-emitting stack, a second surface opposite to the first surface, and a void; wherein the void comprises a bottom part near the first surface and an opening on the second surface, and a dimension of the bottom part is larger than the dimension of the opening..
Epistar Corporation

Semiconductor light emitting element and manufacturing method thereof

A semiconductor light emitting element is disclosed. The element includes a substrate including a first surface, a second surface opposite to the first surface, and a side surface that connects the first surface and the second surface; a semiconductor layer formed on the first surface of the substrate and configured to generate light; and a light reflective layer formed on the second surface of the substrate to cover an entire region of the second surface of the substrate and configured to reflect the light generated by the semiconductor layer toward the semiconductor layer.
Rohm Co., Ltd.

High-voltage driven light emitting element and manufacturing same

Provided is a semiconductor layer light-emitting element having tunneling blocking layers interposed between adjacent active regions, wherein the tunneling blocking layers are semiconductor layers, which do not allow the movement of an electron or a hole at an applied voltage sufficient to activate only one active region among all active regions, and independently separate two adjacent active regions in a quantum region range, so that the semiconductor light-emitting element comprises multiple independent active regions in a vertical direction in a single chip and thus can be driven at high voltages.. .
Constantec Co., Ltd.

Nanoparticle phosphor element and light emitting element

A nanoparticle phosphor element includes a capsule-shaped material that has a plurality of concave portions in a surface, a medium that is sealed in the capsule-shaped material, and a semiconductor nanoparticle phosphor that is dispersed in the medium, and a light emitting element includes a sealing material, and the nanoparticle phosphor element of the disclosure that is dispersed in the sealing material.. .
Sharp Kabushiki Kaisha

Semiconductor device and manufacturing the same

Disclosed is a semiconductor device comprising a thin film transistor and wirings connected to the thin film transistor, in which the thin film transistor has a channel formation region in an oxide semiconductor layer, and a copper metal is used for at least one of a gate electrode, a source electrode, a drain electrode, a gate wiring, a source wiring, and a drain wiring. The extremely low off current of the transistor with the oxide semiconductor layer contributes to reduction in power consumption of the semiconductor device.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor heterostructure with at least one stress control layer

A semiconductor heterostructure for an optoelectronic device is disclosed. The semiconductor heterostructure includes at least one stress control layer within a plurality of semiconductor layers used in the optoelectronic device.
Sensor Electronic Technology, Inc.

Photovoltaic devices including an interfacial layer

A photovoltaic cell can include an interfacial layer in contact with a semiconductor layer.. .
First Solar, Inc.

Semiconductor device manufacturing method

Provided is a semiconductor device manufacturing method. The device has a substrate including one and another surfaces.
Fuji Electric Co., Ltd.

Electronic memory devices

A memory cell for storing one or more bits of information has a control gate, a source terminal and a drain terminal. A semiconductor substrate is located between the source and drain terminals, and a floating gate is disposed between the control gate and the semiconductor substrate.
Lancaster University Business Enterprises Limited

Semiconductor device

A semiconductor device (100) includes: a substrate (10); and a thin film transistor (5) supported on the substrate, the thin film transistor including a gate electrode (12), an oxide semiconductor layer (18), a gate insulating layer (20) provided between the gate electrode and the oxide semiconductor layer, and a source electrode (14) and a drain electrode (16) electrically connected to the oxide semiconductor layer, wherein: the drain electrode is shaped so as to project toward the oxide semiconductor layer; a width w1 and a width w2 satisfy a relationship . .
w1−w2

Sputtering target, oxide semiconductor, oxynitride semiconductor, and transistor

A novel oxide semiconductor, a novel oxynitride semiconductor, a transistor including them, or a novel sputtering target is provided. A composite target includes a first region and a second region.
Semiconductor Energy Laboratory Co., Ltd.

Methods for reducing contact resistance in semiconductor manufacturing process

A method of forming a semiconductor device includes forming a fin on a substrate and forming a source/drain region on the fin. The method further includes forming a doped metal silicide layer on the source/drain region and forming a super-saturated doped interface between the doped metal silicide and the source/drain region.
Taiwan Semiconductor Manufacturing Co., Ltd.

Field effect transistor and fabricating the same

The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate.

Method of forming strained structures of semiconductor devices

A method of fabricating a semiconductor device comprises providing a substrate with a shallow trench isolation (sti) within the substrate and a gate stack. A cavity is formed between the gate stack and the sti.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device

A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.. .
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing method therefor

The present disclosure relates to the technical field of semiconductors and discloses a semiconductor device and a manufacturing method therefor. Forms of the method may include: providing a substrate structure, where the substrate structure includes: a semiconductor substrate, a semiconductor fin on the semiconductor substrate, isolation regions at two sides of the semiconductor fin, a gate dielectric layer on a surface of the semiconductor fin above the isolation regions, and a gate on a part of the gate dielectric layer; and performing threshold voltage adjustment ion implantation on a part of the semiconductor fin that is not covered by the gate, so as to enable implanted impurities to diffuse into a part of the semiconductor fin that is covered by the gate.
Semiconductor Manufacturing International (beijing) Corporation

Semiconductor device and making

A semiconductor device is disclosed that includes a first region of a first conductivity type that includes a drain, a region of a second conductivity type abutting the first region in a lateral direction and a vertical direction to form an interface between the first conductivity type and the second conductivity type, wherein the drain region is spaced apart from the interface. A source region of the first conductivity type abuts the second region in the lateral direction and vertical directions.
Freescale Semiconductor, Inc.

Semiconductor device, fabrication semiconductor device, power supply apparatus and high-frequency amplifier

A semiconductor device is configured including a p-type back barrier layer provided over a substrate and formed from a p-type nitride semiconductor in which mg or zn is doped, a nitride semiconductor stacked structure provided over the p-type back barrier layer, the nitride semiconductor stacked structure including an electron transit layer and an electron supply layer, a source electrode, a drain electrode and a gate electrode provided over the nitride semiconductor stacked structure, and a groove extending to the p-type back barrier layer.. .
Fujitsu Limited

Multi-step surface passivation structures and methods for fabricating same

A gallium nitride (gan) transistor which includes two or more insulator semiconductor interface regions (insulators). A first insulator disposed between the gate and drain (near the gate) minimizes the gate leakage and fields near the gate that cause high gate-drain charge (qgd).
Efficient Power Conversion Corporation

Field-effect transistor

A field-effect transistor includes: a nitride semiconductor layer that includes a heterojunction; a source electrode and a drain electrode that are disposed on the nitride semiconductor layer at an interval; a first gate electrode that is located between the source electrode and the drain electrode and performs a normally-on operation; and a second gate electrode that is located between the first gate electrode and the source electrode and performs a normally-off operation. The first gate electrode is disposed to surround the drain electrode in plan view.
Sharp Kabushiki Kaisha

Semiconductor device and producing the same, power supply device, and high-frequency amplifier

A semiconductor device includes: a nitride semiconductor multilayer; an insulating film disposed on the nitride semiconductor multilayer; and a gate electrode disposed on the insulating film, wherein the nitride semiconductor multilayer has a first oxidized region near an interface with a region of the insulating film below the gate electrode, the first oxidized region having an oxygen concentration higher than an oxygen concentration of a region near an interface with a region of the insulating film other than below the gate electrode.. .
Fujitsu Limited

Single-electron transistor with self-aligned coulomb blockade

semiconductor devices and methods of making the same include forming a gate structure on a thin semiconductor layer. Additional semiconductor material is formed on the thin semiconductor layer.
International Business Machines Corporation

Neuromorphic devices and circuits

Provided are a neuromorphic device and a neuromorphic circuit using the neuromorphic device. The neuromorphic device is configured to include a first semiconductor region formed on a substrate in a wall shape or a dumbbell shape; first, second, third, and fourth doped regions sequentially formed in the first semiconductor region; first and second gate insulating film stacks disposed on the respective side surfaces of the second doped region; first and second gate electrodes respectively disposed on the respective side surfaces of the second doped region; the first and second gate electrodes disposed on the respective side surface of the second doped region, the first and second gate electrodes being electrically insulated from the second doped, region by the first and second gate insulating film stacks; and first and second electrodes electrically connected to the first and fourth doped regions, respectively..
Seoul National University R&db Foundation

Semiconductor device

A semiconductor device includes: a semiconductor substrate having a drift layer; a base layer on the drift layer; a collector layer and a cathode layer arranged on the drift layer opposite to the base layer; multiple trenches penetrating the base layer and reaching the drift layer, and arranged along one direction; a gate electrode arranged in each trench via a gate insulating film; and an emitter region arranged in a surface portion of the base layer, and contacting with each trench. The semiconductor substrate includes an igbt region having the emitter region and an fwd region in which an injection limiting region and a contact region are arranged in the surface portion of the base layer alternately along the one direction..
Denso Corporation

Semiconductor device

A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. Oxygen is introduced into a surface of an insulating film, and then, an oxide semiconductor, a layer which is capable of blocking oxygen, a gate insulating film, and other films which composes a transistor are formed.
Semiconductor Energy Laboratory Co., Ltd.

Method of manufacturing semiconductor device

Described is a technique for uniformly doping a silicon substrate having a fin structure with a dopant. A method of manufacturing a semiconductor device may includes: (a) forming a dopant-containing film containing a dopant on a silicon film by performing a cycle a predetermined number of times, the, cycle including: (a-1) forming a first dopant-containing film by supplying a first dopant-containing gas containing the dopant and a first ligand to a substrate having thereon the silicon film and one of a silicon oxide film and a silicon nitride film; and (a-2) forming a second dopant-containing film by supplying a second dopant-containing gas containing the dopant and a second ligand different from and reactive with the first ligand to the substrate; and (b) forming a doped silicon film by annealing the substrate having the dopant-containing film thereon to diffuse the dopant into the silicon film..
Hitachi Kokusai Electric Inc.

Semiconductor device structure with fin structure and forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method and device for compound semiconductor fin structure

A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate, forming a stack of semiconductor layer structures on the first semiconductor layer, and etching the stack to form a fin structure. Each of the semiconductor layer structures includes a first insulator layer and a second semiconductor layer on the first insulator layer.
Semiconductor Manufacturing International (beijing) Corporation

Semiconductor process

A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure.
United Microelectronics Corp.

Semiconductor memory device and manufacturing same

A semiconductor memory device according to an embodiment, includes a pair of first electrodes, a semiconductor pillar, an inter-pillar insulating member, a first insulating film, a second electrode, and a second insulating film. The pair of first electrodes are separated from each other, and extend in a first direction.
Toshiba Memory Corporation

Spatially decoupled floating gate semiconductor device

A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.. .
International Business Machines Corporation

Semiconductor device and manufacturing semiconductor device

In a semiconductor device, an interlayer insulating film electrically insulating a gate electrode and a source electrode has a structure in which a bpsg film and a nsg film are sequentially stacked. Further, the interlayer insulating film has a structure in which the bpsg film, the nsg film, and a sin film are sequentially stacked, or a structure in which the bpsg film, the sin film, and the nsg film are sequentially stacked.
Fuji Electric Co., Ltd.

Semiconductor device

The present invention relates to a vertical semiconductor device such as an igbt or a diode which includes an n buffer layer formed in the undersurface of and adjacent to an n− drift layer. A concentration slope δ, which is derived from displacements in a depth tb (μm) and an impurity concentration cb (cm−3), from the upper surface to the lower surface in a main portion of the n buffer layer satisfies a concentration slope condition defined by {0.03≦δ≦0.7}..
Mitsubishi Electric Corporation

Semiconductor structure with a silicon germanium alloy fin and silicon germanium alloy pad structure

A semiconductor structure is provided that includes a silicon germanium alloy fin having a second germanium content located on a first portion of a substrate. The structure further includes a laterally graded silicon germanium alloy material portion located on a second portion of the substrate.
International Business Machines Corporation

Semiconductor devices including contact structures that partially overlap silicide layers

semiconductor devices are provided. A semiconductor device includes a substrate.
Samsung Electronics Co., Ltd.

Methods for forming fin structures with desired profile for 3d structure semiconductor applications

Methods for forming fin structures with desired profile and dimensions for three dimensional (3d) stacking of fin field effect transistor (finfet) for semiconductor chips are provided. The methods include a structure reshaping process to reshape a shaped structure, such as a diamond like structure formed on a fin structure.
Applied Materials, Inc.

Power semiconductor device and fabricating the same

Provided is a power semiconductor device comprising a gate electrode in a trench of a substrate; a body region having a first conductivity type on one side of the gate electrode; a source region having a second conductivity type adjacent to the gate electrode; a floating region having a first conductivity type on the other side of the gate electrode; an edge doped region having a first conductivity type spaced apart from the floating region and electrically connected to the source region; an edge junction isolation region having a second conductivity type between the floating region and the edge doped region; and a drift region having a second conductivity type below the floating, edge doped, and edge junction isolation regions, wherein the doping concentration of a second conductivity type in the edge junction isolation region is higher than the doping concentration of a second conductivity type in the drift region.. .
Hyundai Autron Co., Ltd

Power semiconductor devices, methods, and structures with embedded dielectric layers containing permanent charges

Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region..
Maxpower Semiconductor, Inc.

Combined gate trench and contact etch process and related structure

A method of forming a semiconductor device, the method comprises forming a gate trench and a contact trench concurrently in a semiconductor substrate using a patterned masking layer, forming a gate conductive filler in the gate trench, forming a deep body region below the contact trench, and forming a contact conductive filler in the contact trench. The method further comprises forming a gate trench dielectric liner in the gate trench, forming a gate trench dielectric liner in the gate trench, and forming an interlayer dielectric layer (idl) over the gate conductive filler.
Infineon Technologies Americas Corp.

Semiconductor rectifier and manufacturing method thereof

A semiconductor rectifying device and a method of manufacturing the same. The semiconductor rectifying device includes: a substrate of a first conductivity type (100), an epitaxial layer of a first conductivity type (200) formed on the substrate of the first conductivity type (100), wherein the epitaxial layer of the first conductivity type (200) defines a plurality of trenches (310) thereon; a filling structure (300) comprising an insulating material formed on the inner surface of the trench (310) and a conductive material filled in the trench (310); a doped region of a second conductivity type (400) formed in the surface of the epitaxial layer of the first conductivity type (200) located between the filling structures (300); an upper electrode (600) formed on a surface of the epitaxial layer of the first conductivity type (200); a guard ring (700) formed in the surface layer of the epitaxial layer of the first conductivity type (200); and a guard layer (800)..
Csmc Technologies Fab1 Co., Ltd.

C-plane gan substrate

A c-plane gan substrate only mildly restricts the shape and dimension of a nitride semiconductor device formed on the substrate. The variation of an off-angle on the main surface of the substrate is suppressed.
Mitsubishi Chemical Corporation

Organic light emitting diode display device and manufacturing method thereof

An organic light emitting diode display includes a substrate, a semiconductor, a gate electrode, a source electrode connected to a first portion of the semiconductor, a drain electrode connected to a second portion of the semiconductor, and a pixel electrode connected to the drain electrode. Each of the source electrode, the drain electrode, and the pixel electrode includes a barrier metal layer, a low resistance metal layer, a metal oxide layer, and a contact assistant layer disposed between the low resistance metal layer and the metal oxide layer.
Samsung Display Co., Ltd.

Manufacturing tft backplane and tft backplane

The present invention provides a manufacture method of a tft backplate and a tft backplate. By utilizing the oxide semiconductor to manufacture the switch tft, and utilizing the advantages of rapid switch and lower leakage current of the oxide semiconductor, the switch speed of the switch tft is raised and the leakage current is lowered; by utilizing the polysilicon to manufacture the drive tft, and utilizing the properties of higher electron mobility and the uniform grain of the polysilicon, the electron mobility and the current output consistency of the drive tft is promoted.
Shenzhen China Star Optoelectronics Technology Co. Ltd.

Method for fabricating an array of diodes, in particular for a non-volatile memory, and corresponding device

The array of diodes comprises a matrix plane of diodes arranged according to columns in a first direction and according to rows in a second direction orthogonal to the first direction. The said diodes comprise a cathode region of a first type of conductivity and an anode region of a second type of conductivity, the said cathode and anode regions being superposed and disposed on an insulating layer situated on top of a semiconductor substrate..
Stmicroelectronics (rousset) Sas

Display device and producing a display device

A display device with a semiconductor layer sequence includes an active region provided for generating radiation and a plurality of pixels. The display device also includes a carrier.
Osram Opto Semiconductors Gmbh

Image sensor chip scale packages and related methods

Methods of forming an image sensor chip scale package. Implementations may include providing a semiconductor wafer having a pixel array, forming a first cavity through the wafer and/or one or more layers coupled over the wafer, filling the first cavity with a fill material, planarizing the fill material and/or the one or more layers to form a first surface of the fill material coplanar with a first surface of the one or more layers, and bonding a transparent cover over the fill material and the one or more layers.
Semiconductor Components Industries, Llc

Image-sensing device

An image-sensing device includes a semiconductor substrate, a passive layer, and a light-collecting element. The semiconductor substrate includes a photo-sensing element, and the passive layer is disposed over the semiconductor substrate.
Visera Technologies Company Limited

Element substrate and display device

An element substrate and a display device are provided. The element substrate includes a substrate and an element layer, and the element layer is disposed on the substrate, wherein the element layer includes a plurality of active elements, each of the active elements includes a gate, a gate insulating layer, a metal oxide semiconductor layer, a source and a drain.
Innolux Corporation

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device including: preparing a substrate in which an insulating layer, a semiconductor layer, and an insulating film are laminated on a semiconductor substrate, and a device isolation region is embedded in a trench. The insulating film in a bulk region is removed; the semiconductor layer in the bulk region is removed; and thereafter the insulating film in the soi region and the insulating layer in the bulk region are thinned.
Renesas Electronics Corporation

Semiconductor device

A semiconductor device includes an insulating layer on a substrate, a first channel pattern on the insulating layer and contacting the insulating layer, second channel patterns on the first channel pattern and being horizontally spaced apart from each other, a gate pattern on the insulating layer and surrounding the second channel patterns, and a source/drain pattern between the second channel patterns.. .
Samsung Electronics Co., Ltd.

Semiconductor device with high integration

The present disclosure may provide a semiconductor device having a stable structure and a low manufacturing degree of the difficulty. The device may include conductive layers and insulating layers which are alternately stacked; a plurality of pillars passing through the conductive layers and the insulating layers; and a plurality of deposit inhibiting patterns, each deposit inhibiting pattern being formed along a portion of an interface between a side-wall of each of the pillars and each of the conductive layers and along a portion of an interface between each of the insulating layers and each of the conductive layers..
Sk Hynix Inc.

Semiconductor device with high integration

The present disclosure may provide a semiconductor device having a stable structure and a low manufacturing degree of the difficulty. The device may include conductive layers and insulating layers which are alternately stacked; a plurality of pillars passing through the conductive layers and the insulating layers; and a plurality of deposit inhibiting patterns, each deposit inhibiting pattern being formed along a portion of an interface between a side-wall of each of the pillars and each of the conductive layers and along a portion of an interface between each of the insulating layers and each of the conductive layers..
Sk Hynix Inc.

Memory device

In one embodiment, the semiconductor device includes a substrate having an impurity region, and the substrate and the impurity region have a different impurity characteristic. The semiconductor device further includes a stack of alternating first interlayer insulating layers and gate electrode layers on the substrate; at least one second interlayer insulating layer formed on the stack; a plurality of bit lines formed on the second interlayer insulating layer; and a first plurality of channel structures formed through the stack on the substrate.

Three-dimensional semiconductor device

A 3d semiconductor device is provided, including several memory layers vertically stacked on a substrate, an upper selection layer formed on the memory layers, a lower selection layer formed above the substrate, several strings formed vertically to the memory layers and the substrate, several bit lines parallel to each other and disposed above the substrate. The memory layers are parallel to each other, and the strings are electrically connected to the upper selection layer and the lower selection layer.
Macronix International Co., Ltd.

Through-memory-level via structures between staircase regions in a three-dimensional memory device and making thereof

Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures.
Sandisk Technologies Llc

Semiconductor device and manufacturing method thereof

An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A first memory cell includes a first control gate electrode and a first memory gate electrode which are formed over a semiconductor substrate to be adjacent to each other.
Renesas Electronics Corporation

Semiconductor device and manufacturing the same

To improve reliability of a semiconductor device, a control transistor and a memory transistor formed in a memory cell region are configured to have a double-gate structure, and a transistor formed in a peripheral circuit region is configured to have a triple-gate structure. For example, in the memory transistor, a gate insulating film formed by an ono film is provided between a memory gate electrode and sidewalls of a fin, and an insulating film (a stacked film of a multilayer film of an insulating film/an oxide film and the ono film) thicker than the ono film is provided between the memory gate electrode and a top surface of the fin.
Renesas Electronics Corporation

Three-dimensional semiconductor devices

A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.. .
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a second channel layer in a first column and a second channel layer in a second column disposed biased to one side of a first channel layer in a first column and a first channel layer in a second column, respectively. The one side of the first channel layer in the first column and the one side of the first channel layer in the second column face directions opposite to each other..
Sk Hynix Inc.

Semiconductor memory device

A semiconductor memory device according to an embodiment includes first and second semiconductor pillars extending in a first direction and being arranged along a second direction, first and second interconnects extending in a third direction and being provided between the first semiconductor pillar and the second semiconductor pillar, a first electrode provided between the first semiconductor pillar and the first interconnect, a second electrode provided between the second semiconductor pillar and the second interconnect, third and fourth interconnects extending in the second direction, a first contact contacting the first semiconductor pillar and being connected to the third interconnect, and a second contact contacting the second semiconductor pillar and being connected to the fourth interconnect. The third and fourth interconnects each pass through both a region directly above the first semiconductor pillar and a region directly above the second semiconductor pillar..
Toshiba Memory Corporation

Semiconductor memory device and manufacturing same

A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, a second insulating film provided between the second electrode and the first insulating film and on two first-direction sides of the second electrode, a third insulating film provided between the second electrode and the semiconductor pillar, and a conductive film provided inside a region interposed between the first insulating film and the second insulating film.. .
Toshiba Memory Corporation

Three-dimensional memory device having multilayer word lines containing selectively grown cobalt or ruthenium and making the same

A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulating layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulating layers, a backside blocking dielectric layer may be formed in the backside recesses and sidewalls of the memory stack structures.
Sandisk Technologies Llc

Method and device for finfet sram

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of the trenches; forming a high-k dielectric layer on the interface layer and sidewalls of the trenches; forming a first pmos work function adjustment layer on the high-k dielectric layer of the third trench; forming a second pmos work function adjustment layer in the trenches after forming the first pmos work function adjustment layer; forming an nmos work function layer in the trenches after forming the second pmos work function adjustment layer; and forming a barrier layer in the trenches after forming the nmos work function layer and a metal gate layer on the barrier layer.. .
Semiconductor Manufacturing International (beijing) Corporation

Pattern forming method and semiconductor device manufacturing method using the same

A method for forming patterns includes forming an etch target layer; etching the etch target layer to form a pre-pattern having a line forming portion and a plurality of pad portions; forming a plurality of spacers which extend across the pad portions and the line forming portion; forming, over the spacers, a blocking layer having an opening which blocks the pad portions and exposes the line forming portion; and etching the line forming portion by using the blocking layer and the spacers as a barrier, to form a plurality of line portions.. .
Sk Hynix Inc.

Semiconductor device and manufacturing the same

A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer.
Samsung Electronics Co., Ltd.

Semiconductor device having contact plugs and forming the same

A semiconductor device including a first fin active area substantially parallel to a second fin active area, a first source/drain in the first fin active area, a second source/drain in the second fin active area, a first contact plug on the first source/drain, and a second contact plug on the second source/drain. The center of the second contact plug is offset from the center of the second source/drain..
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing method therefor

The present disclosure provides a semiconductor device and a manufacturing method therefor. The device may include: a semiconductor substrate; a fin projecting from the semiconductor substrate, where trenches are formed on sides of the fin; a first insulator layer partially filling the trenches, where the fin protrudes from the first insulator layer; a second insulator layer covering the fin; a plurality of pseudo gate structures on the second insulator layer, where each pseudo gate structure wraps a part of the fin, where each pseudo gate structure includes a pseudo gate located on the second insulator layer, the plurality of pseudo gate structures includes at least a first pseudo gate structure and a second pseudo gate structure that are spaced from each other, the second pseudo gate structure is located at an edge corner of the fin, and a part of the second pseudo gate structure is on the first insulator layer; spacers, on the first insulator layer and the second insulator layer, at two sides of each of the plurality of pseudo gate structures; and a source or a drain located among the plurality of pseudo gate structures.
Semiconductor Manufacturing International (beijing) Corporation

Complementary metal oxide semiconductor (cmos) devices employing plasma-doped source/drain structures and related methods

Complementary metal oxide semiconductor (cmos) devices employing plasma-doped source/drain structures and related methods are disclosed. In certain aspects, a source and drain of a cmos device are formed at end portions of a channel structure by plasma doping end portions of the channel structure above solid state solubility of the channel structure, and annealing the end portions for liquid phase epitaxy and activation (e.g., superactivation).
Qualcomm Incorporated

Semiconductor devices

The present disclosure relates to semiconductor structures and, more particularly, to segmented or cut finfet structures and methods of manufacture. The structure includes at least one logic finfet device having a fin of a first length, and at least one memory finfet device having a fin of a second length.
Globalfoundries Inc.

Buried channel semiconductor device and manufacturing the same

A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method for forming finfet device

A method includes providing a semiconductor structure including an active region having a first doped region, a first contact member on the first doped region, first and second gates on opposite sides of the first contact member, an interlayer dielectric layer surrounding the first and second gates and the first contact member. The method also includes forming a first insulator layer having first and second contact holes, forming a second insulator layer on sidewalls of the first and second contact holes, filling the first and second contact holes with a first conductive material to form first and second contacts to the first and second gates, forming a third insulator layer on the first and second contacts, selectively etching the first insulator layer to form a third contact hole, and filling the third contact hole with a second conductive material to form a third contact to the first contact member..
Semiconductor Manufacturing International (beijing) Corporation

Air gap spacer for metal gates

A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure.
International Business Machines Corporation

Semiconductor device structure and forming the same

A method includes forming a gate, a first dielectric layer, a first contact structure, and a second contact structure over a substrate. The first contact structure and the second contact structure are over a source region and a drain region respectively.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device, manufacturing same, and semiconductor module

In order to form, in a wide band gap semiconductor device, a high field resistant sealing material having a large end portion film thickness, said high field resistant sealing material corresponding to a reduced termination region having a high field intensity, and to improve accuracy and shorten time of manufacturing steps, this semiconductor device is configured as follows. At least a part of a cross-section of a high field resistant sealing material formed close to a termination region at the periphery of a semiconductor chip has a perpendicular shape at a chip outer peripheral end portion, said shape having, on the chip inner end side, a film thickness that is reduced toward the inner side.
Hitachi, Ltd.

Micro-transfer-printed light-emitting diode device

A compound light-emitting diode (led) device includes a semiconductor substrate having an active electronic circuit formed in or on the semiconductor substrate. Two or more electrically conductive circuit connection pads are formed in or on the semiconductor substrate and are electrically connected to the active electronic circuit.
X-celeprint Limited

Thermal pads between stacked semiconductor dies and associated systems and methods

Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies.
Micron Technology, Inc.

Apparatus for bonding a semiconductor chip and forming a semiconductor device

An apparatus for bonding a semiconductor chip to a package substrate, the apparatus comprising: a die-bonding unit configured to attach the semiconductor chip to the package substrate; a load-measuring unit installed at the die-bonding unit, the load-measuring unit including a panel having a plurality of regions and a plurality of load-measuring members with at least one load-measuring member arranged in each of the regions of the panel to measure load values applied to each of the regions; and a controller configured to determine a load and a flatness of the semiconductor chip based on the load values measured by the load-measuring members.. .
Sk Hynix Inc.

Method and system for mounting components in semiconductor fabrication process

A method for mounting components on a substrate is provided. The method includes providing a positioning plate which has a plurality of through holes.
Taiwan Semiconductor Manufacturing Co., Ltd.

Removal apparatuses for semiconductor chips and methods of removing semiconductor chips

A removal apparatus for a semiconductor chip may include a stage configured to support a board on which the semiconductor chip is mounted by bumps, a laser configured to irradiate a laser beam into the board over an area larger than the semiconductor chip, and a picker configured to cause the laser beam to penetrate the semiconductor chip locally and to separate the semiconductor chip from the board. A method of removing a semiconductor chip from a board may include loading the board, on which the semiconductor chip is mounted by bumps, on a stage; irradiating a laser beam into the semiconductor chip to melt the bumps and to separate the semiconductor chip from the board; continuously irradiating the laser beam into the board on which solder pillars, that are residues of the bumps, remain to melt the solder pillars; and removing the solder pillars..
Samsung Electronics Co., Ltd.

Semiconductor device including antistatic die attach material

A semiconductor device includes a substrate, a semiconductor die, and an antistatic die attach material between the substrate and the semiconductor die. The antistatic die attach material includes a mixture of a nonconductive adhesive material and carbon black or graphite.
Infineon Technologies Ag

Semiconductor device and manufacturing method thereof

A semiconductor device includes a first die, a second die bonding to the first die thereby forming a bonding interface, and a pad of the first die and exposed from a polymeric layer of the first die. The semiconductor device further has a conductive material on the pad and extended from the pad in a direction parallel to a stacking direction of the first die and the second die.
Taiwan Semiconductor Manufacturing Company Ltd.

Collars for under-bump metal structures and associated systems and methods

The present technology is directed to manufacturing collars for under-bump metal (ubm) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material.
Micron Technology, Inc.

Connector formation methods and packaged semiconductor devices

Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device

Provided is a semiconductor device including a substrate, a pad, a protective layer, a plurality of convex patterns, a redistribution layer (rdl), and a bump. The pad is disposed on the substrate.
Chipmos Technologies Inc.

Integrated circuits and methods of manufacturing

A technique for making high performance low noise amplifiers, low cost high performance rf, microwave circuits and other devices by using a minimum of costly high performance semiconductors is described. By combining a single discrete portion of an expensive semiconductor with a less expensive gaas carrier, mmic devices with improved performance over their discrete counterparts are achieved..
Leonardo Mw Ltd.

Power module

A power module includes a power semiconductor element, an interconnection material, a circuit board, an external terminal, a joining material, and a sealing resin. A clearance portion is continuously formed between the sealing resin and each of an end surface of the joining material and a surface of the interconnection material so as to extend from the end surface of the joining material to the surface of the interconnection material, the end surface of the joining material being located between the power semiconductor element and the interconnection material, the surface of the interconnection material being located between the end surface and a predetermined position of the interconnection material separated by a distance from the end surface..
Mitsubishi Electric Corporation

Wiring board and semiconductor device

A wiring board includes a first insulating layer made of a single layer of non-photosensitive resin including a reinforcing member, a center position of the reinforcing member being positioned on a side toward a first surface with respect to a center of the first insulating layer in a thickness direction; a layered structure of a wiring layer and an insulating layer, stacked on the first surface of the first insulating layer; a through wiring provided to penetrate the first insulating layer, the through wiring and the first insulating layer forming a first concave portion at a second surface of the first insulating layer, in which the second end surface of the through wiring is exposed; and a pad for external connection formed at the second surface of the first insulating layer at a position corresponding to the through wiring and having a second concave portion.. .
Shinko Electric Industries Co., Ltd.

Self-aligned vertical transistor with local interconnect

A metallization scheme for vertical field effect transistors (fets) is provided. By forming lower-level local interconnects connecting source regions located at bottom portions of semiconductor fins, and upper-level interconnects connecting adjacent metal gates located along sidewalls of channel regions of the semiconductor fins, electrical connections to the source regions and the metal gates can be provided through the lower-level local interconnects and the upper-level local interconnects, respectively.
International Business Machines Corporation

Semiconductor device and manufacturing method thereof

A semiconductor device according to this embodiment includes a semiconductor layer, a plurality of diffusion layers in the semiconductor layer, a gate insulating film, a gate electrode, first contacts, and second contacts. The gate insulating film is on the semiconductor layer between the plurality of diffusion layers.
Toshiba Memory Corporation

Methods for semiconductor component design and for semiconductor component production and corresponding semiconductor components

Methods for designing semiconductor components, for fabricating semiconductor components, and corresponding semiconductor components are provided. In this case, capacitance structures are either coupled to a supply network or used for rectifying design violations..
Infineon Technologies Ag

Semiconductor constructions, patterning methods, and methods of forming electrically conductive lines

Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region.
Micron Technology, Inc.

Semiconductor device and manufacturing method thereof

An electronic device and a method of manufacturing an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing metal studs to further set a semiconductor die into the encapsulant..
Amkor Technology, Inc.

Semiconductor packages including heat spreaders and methods of manufacturing the same

There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball connectors (tmbcs) on a first surface of an interconnection structure layer, forming a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the tmbcs, attaching outer connectors to the exposed portions of the tmbcs, mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer, and attaching a heat spreader to the second surface of the interconnection structure layer to overlap with a portion of the first semiconductor device..
Sk Hynix Inc.

Semiconductor package with multiple molding routing layers and a manufacturing the same

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package..
Utac Headquarters Pte. Ltd.

Electronic device for vehicle

An electronic device for a vehicle includes a substrate and a semiconductor package. The substrate is arranged to extend along a flowing path of wind produced by a fan unit.
Denso Corporation

Lighting device using short thermal path cooling technology and other device cooling by placing selected openings on heat sinks

A novel heat sinking technology, uniquely adaptive to led lighting devices in a generally led array format containing multiple openings on said heat sink's base portions and optionally fin portions providing “short path cooling” technology. The “short path cooling” technology is thoroughly taught with multiple examples.
Greentech Led

Semiconductor device and power conversion device using same

In order to improve productivity of a semiconductor device, while improving stability of the blocking voltage of the semiconductor device, this semiconductor device is characterized by having a semiconductor element, and a laminated structure having three resin layers, said laminated structure being in a peripheral section surrounding a main electrode on one surface of the semiconductor element. The semiconductor device is also characterized in that the laminated structure has, on the center section side of the semiconductor element, a region where a lower resin layer is in contact with an intermediate resin layer, and a region where the lower resin layer is in contact with an upper resin layer..
Hitachi, Ltd.

Sensor for a semiconductor device

A semiconductor arrangement is presented. The semiconductor arrangement comprises a semiconductor body, the semiconductor body including a semiconductor drift region, wherein the semiconductor drift region has dopants of a first conductivity type; a first semiconductor sense region and a second semiconductor sense region, wherein each of the first semiconductor sense region and the second semiconductor sense region is electrically connected to the semiconductor drift region and has dopants of a second conductivity type different from said first conductivity type; a first metal contact comprising a first metal material, the first metal contact being in contact with the first semiconductor sense region, wherein a transition between the first metal contact and the first semiconductor sense region forms a first metal-to-semiconductor transition; a second metal contact comprising a second metal material different from said first metal material, the second metal contact being separated from the first metal contact and in contact with the second semiconductor sense region, a transition between the second metal contact and the second semiconductor sense region forming a second metal-to-semiconductor transition different from said first metal-to-semiconductor transition; first electrical transmission means, the first electrical transmission means being arranged and configured for providing a first sense signal derived from an electrical parameter of the first metal contact to a first signal input of a sense signal processing unit; and second electrical transmission means separated from said first electrical transmission means, the second electrical transmission means being arranged and configured for providing a second sense signal derived from an electrical parameter of the second metal contact to a second signal input of said sense signal processing unit..
Infineon Technologies Ag

Semiconductor device and producing the same

Provided is a semiconductor device capable of measuring a depth of removal of a silicon carbide (sic) wafer with high accuracy through simple steps, and a method for producing the semiconductor device. The semiconductor device according to an aspect of the present invention includes at least one evaluation element disposed on a sic wafer.
Mitsubishi Electric Corporation

Double sided nmos/pmos structure and methods of forming the same

A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first metal oxide-semiconductor (mos) transistor of a first conductivity type. The first mos transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric.
Taiwan Semiconductor Manufacturing Company, Ltd.

Low resistance dual liner contacts for fin field-effect transistors (finfets)

A semiconductor device includes first and second gate structures on a substrate respectively corresponding to an n-type and a p-type transistor, a first source/drain on the substrate corresponding to the n-type transistor, a second source/drain on the substrate corresponding to the p-type transistor, a first contact trench over the first source/drain and adjacent the first gate structure, a second contact trench over the second source/drain and adjacent the second gate structure, a first liner layer in the first trench positioned at a bottom part of the first trench, a second liner layer in the second trench and on the first liner layer in the first trench, a metallization layer in the first and second trenches on the second liner layer, and a first silicide contact between the first liner layer and the first source/drain and a second silicide contact between the second liner layer and the second source/drain.. .
International Business Machines Corporation

Finfets with strained well regions

A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band.
Taiwan Semiconductor Manufacturing Company, Ltd.

Method for reducing n-type finfet source and drain resistance

A method of manufacturing a semiconductor device includes providing a substrate structure, the substrate structure having a semiconductor substrate including a first semiconductor fin, a first gate structure, and a first mask layer on a first semiconductor region. The method includes forming a second mask layer on the substrate structure, etching first mask layer and second mask layer to expose a portion of a first semiconductor fin not covered by the first gate structure, performing a first ion implantation on an exposed portion of the first semiconductor fin to introduce impurities into a portion of the first semiconductor fin located below the first gate structure, etching the first semiconductor fin to remove a portion of an exposed portion of the first semiconductor fin, and epitaxially growing a first semiconductor material on the remaining portions of the first semiconductor fin to form a first source region and a first drain region..
Semiconductor Manufacturing International (beijing) Corporation

Hardmask layer for 3d nand staircase structure in semiconductor applications

Embodiments of the present disclosure provide an apparatus and methods for forming a hardmask layer that may be utilized to transfer patterns or features to a film stack with accurate profiles and dimension control for manufacturing three dimensional (3d) stacked semiconductor devices. In one embodiment, a method of forming a hardmask layer on a substrate includes forming a seed layer comprising boron on a film stack disposed on a substrate by supplying a seed layer gas mixture in a processing chamber, forming a transition layer comprising born and tungsten on the seed layer by supplying a transition layer gas mixture in the processing chamber, and forming a bulk hardmask layer on the transition layer by supplying a main deposition gas mixture in the processing chamber..
Applied Materials, Inc.

Semiconductor wafer and manufacturing the same

A semiconductor wafer in accordance with an embodiment includes: a support substrate semiconductor wafer having a first surface and a second surface opposite to the first surface; and an active layer formed on the first surface. The support substrate semiconductor wafer includes a support substrate semiconductor and an insulating film which is formed on a first surface side and a second surface side of the support substrate semiconductor.
Renesas Electronics Corporation

Methods of forming one or more covered voids in a semiconductor substrate, methods of forming field effect transistors, methods of forming semiconductor-on-insulator substrates, methods of forming a span comprising silicon dioxide, methods of cooling semiconductor devices, methods of forming electromagnetic radiation emitters and conduits, methods of forming imager systems, methods of forming nanofluidic channels, fluorimetry methods, and integrated circuitry

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials.
Micron Technology, Inc.

Methods of forming one or more covered voids in a semiconductor substrate, methods of forming field effect transistors, methods of forming semiconductor-on-insulator substrates, methods of forming a span comprising silicon dioxide, methods of cooling semiconductor devices, methods of forming electromagnetic radiation emitters and conduits, methods of forming imager systems, methods of forming nanofluidic channels, fluorimetry methods, and integrated circuitry

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials.
Micron Technology, Inc.

Methods of forming one or more covered voids in a semiconductor substrate

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials.
Micron Technology, Inc.

Methods of forming one or more covered voids in a semiconductor substrate

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials.
Micron Technology, Inc.

Circular support substrate for semiconductor

An object of the present invention is to provide a circular support substrate that allows for positioning based solely on its outer periphery shape. As a means for solving the problems, a circular support substrate is provided that has at least three chords along its circumference, wherein the chords are provided at positions where they do not run linearly symmetrical to the straight line passing through the center axis of the circular support substrate..
National Institute Of Advanced Industrial Science And Technology

Semiconductor method and associated apparatus

A semiconductor method is disclosed. The semiconductor method is performed upon semiconductor wafers, wherein each of the semiconductor wafers includes a first exposure field and a second exposure field, and each of the first exposure field and the second exposure field includes a first alignment mark and a second alignment mark.
Taiwan Semiconductor Manufacturing Company Ltd.

Fluorine contamination control in semiconductor manufacturing process

A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor.
Taiwan Semiconductor Manufacturing Co., Ltd.

Substrate-processing apparatus and manufacturing semiconductor device

A substrate processing apparatus includes a process chamber and a transfer device configured to transfer a plurality of substrates to a substrate retainer. The transfer device includes a base; a first moving unit capable of linear motion; a first drive unit to drive the first moving unit.
Hitachi Kokusai Electric Inc.

Semiconductor package with multiple molding routing layers and a manufacturing the same

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package..
Utac Headquarters Pte. Ltd.

Semiconductor package with multiple molding routing layers and a manufacturing the same

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to activate areas of each molding compound layer of the semiconductor package.
Utac Headquarters Pte. Ltd.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device may include forming a first stack structure by alternately stacking first material layers and second material layers, forming first holes penetrating the first stack structure and a first slit located between the first holes, forming channel patterns in the first holes and a dummy channel pattern in the first slit, selectively removing the dummy channel pattern from the first slit, and replacing the first material layers with third material layers through the first slit.. .
Sk Hynix Inc.

Semiconductor device and manufacturing method thereof

A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.

Vapor phase etching of hafnia and zirconia

A method is described for vapor phase etching of oxide material including at least one of hafnia (hfo2) and zirconia (zro2), in the absence of plasma exposure of the oxide material. The method involves contacting the oxide material with an etching medium including at least one of phosphorus chloride and tungsten chloride under conditions producing a removable fluid reaction product, and removing the removable fluid reaction product.
Entegris, Inc.

Method of etching semiconductor structures with etch gas

Disclosed are sulfur-containing compounds for plasma etching channel holes, gate trenches, staircase contacts, capacitor holes, contact holes, etc., in si-containing layers on a substrate and plasma etching methods of using the same. The plasma etching compounds may provide improved selectivity between the si-containing layers and mask material, less damage to channel region, a straight vertical profile, and reduced bowing in pattern high aspect ratio structures..
American Air Liquide, Inc.

Method of producing semiconductor epitaxial wafer and producing solid-state image sensor

Provided is a method of producing a semiconductor epitaxial wafer having enhanced gettering ability. The method of producing a semiconductor epitaxial wafer includes: a first step of irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer that is located in a surface portion of the semiconductor wafer and that includes a constituent element of the cluster ions in solid solution; and a second step of forming an epitaxial layer on the modified layer of the semiconductor wafer.
Sumco Corporation

Composition for manufacturing semiconductor device and manufacturing semiconductor device using the composition

A composition for manufacturing a semiconductor device includes at least one carbon-based compound that includes at least one of an alkyne group and an azide group, and a solvent. A method of manufacturing a semiconductor device includes forming a feature layer on a substrate, coating the feature layer with a composition including alkyne and azide, forming a carbon-containing layer including a triazole compound by performing a heat treatment on the coated composition, forming a photoresist film on the carbon-containing layer, forming photoresist patterns by exposing and developing the photoresist film, and patterning the carbon-containing layer and the feature layer using the photoresist patterns..
Samsung Electronics Co., Ltd.

Sputtering apparatus, sputtering target, and forming semiconductor film with the sputtering apparatus

To provide a sputtering apparatus capable of forming a semiconductor film in which impurities such as hydrogen or water are reduced. The sputtering apparatus is capable of forming a semiconductor film and includes a deposition chamber, a gas supply device connected to the deposition chamber, a gas refining device connected to the gas supply device, a vacuum pump for evacuating the deposition chamber, a target disposed in the deposition chamber, and a cathode disposed to face the target.
Semiconductor Energy Laboratory Co., Ltd.

A epitaxial growth of a material interface between group iii-v materials and silicon wafers providing counterbalancing of residual strains

The present invention relates to a method of manufacturing semiconductor materials comprising interface layers of group iii-v materials in combination with si substrates. Especially the present invention is related to a method of manufacturing semiconductor materials comprising gaas in combination with si(111) substrates, wherein residual strain due to different thermal expansion coefficient of respective materials is counteracted by introducing added layer(s) compensating the residual strain..
Integrated Solar

Method of producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip

A method of producing an optoelectronic semiconductor chip includes in order: a) creating a nucleation layer on a growth substrate, b) applying a mask layer on to the nucleation layer, c) growing a coalescence layer, wherein the coalescence layer is grown starting from regions of the nucleation layer not covered by mask islands having a first main growth direction perpendicular to the nucleation layer so that ribs are formed, d) further growing the coalescence layer with a second main growth direction parallel to the nucleation layer to form a contiguous and continuous layer, e) growing a multiple quantum well structure on the coalescence layer, f) applying a mirror having metallic contact regions that impress current into the multiple quantum well structure and mirror islands for the total reflection of radiation generated in the multiple quantum well structure, and g) detaching the growth substrate and creating a roughening by etching.. .
Osram Opto Semiconductors Gmbh

Integrated circuit die having reduced defect group iii-nitride layer and methods associated therewith

Embodiments of the present disclosure are directed towards an integrated circuit (ic) die. In embodiments, an ic die may include a semiconductor substrate, a group iii-nitride or ii-vi wurtzite layer disposed over the semiconductor substrate, and a plurality of buffer structures at least partially embedded in the group iii-nitride or ii-vi wurtzite layer.
Intel Corporation

Advanced exhaust system

An apparatus for a semiconductor process includes an exhaust pipe coupled to a reaction chamber and a pump; a pressure control valve that is coupled to the exhaust pipe and configured to control a pressure value in the reaction chamber; a first pipe that is coupled to the exhaust pipe and etching gas source such that the first pipe is configured to provide an etching gas into the exhaust pipe; a second pipe that is coupled to the exhaust pipe and a radical generator such that the second pipe is configured to provide a radical into the exhaust pipe; and a third pipe that is coupled to the exhaust pipe and a diluted gas source such that the third pipe is configured to provide diluted gas into the exhaust pipe.. .
Taiwan Semiconductor Manufacturing Co., Ltd.

Energy filter for processing a power semiconductor device

A method of producing an implantation ion energy filter, suitable for processing a power semiconductor device. In one example, the method includes creating a preform having a first structure; providing an energy filter body material; and structuring the energy filter body material by using the preform, thereby establishing an energy filter body having a second structure..
Infineon Technologies Ag

Ruthenium complex dye, dye solution, photoelectric conversion element, and dye-sensitized solar cell

Provided are a ruthenium complex dye having a water content of 0.2% to 4.0% by mass; a dye solution including the ruthenium complex dye; a photoelectric conversion element having semiconductor fine particles having the ruthenium complex dye carried thereon; and a dye-sensitized solar cell including the photoelectric conversion element.. .
Fujifilm Corporation

Graphene-semiconductor based wavelength selective photodetector for sub-bandgap photo detection

Graphene photodetectors capable of operating in the sub-bandgap region relative to the bandgap of semiconductor nanoparticles, as well as methods of manufacturing the same, are provided. A photodetector can include a layer of graphene, a layer of semiconductor nanoparticles, a dielectric layer, a supporting medium, and a packaging layer.
The University Of Hong Kong

Planar coil

Individual coils as well as two or more coils arranged one over the other or one coil in combination with a sensor, which can be integrated into planar semiconductor technology are described. A coil comprises a turn and two supply lines for supplying current to the coil.
X-fab Semiconductor Foundries Ag

Semiconductor device using a parallel bit operation and operating the same

A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.. .
Samsung Electronics Co., Ltd.

Nonvolatile semiconductor storage device

A non-volatile semiconductor memory device in which, while voltage from a first control line is applied, as a memory gate voltage, to a sub control line through a switching transistor, another switching transistor can block voltage application to a corresponding sub control line. Thus, while a plurality of memory cells are arranged in one direction along the first control line, the number of memory cells to which a memory gate voltage is applied can reduced by the switching transistor, which reduces the occurrence of disturbance, accordingly.
Floadia Corporation

Self pre-charging memory circuits

The present disclosure relates to semiconductor structures and, more particularly, to sensing circuit for a memory and methods of use. The memory includes a self-referenced sense amp that is structured to calibrate its individual pre-charge based on a trip-point, with autonomous pre-charge activation circuitry that starts pre-charging a sense-line on each unique entry as soon as a sense has been performed or completed..
Globalfoundries Inc.

Semiconductor device and semiconductor system

A semiconductor system includes a semiconductor device suitable for not performing an internal refresh operation when entering a self-refresh mode in response to a self-refresh command, and cutting off input of an auto-refresh command when exiting the self-refresh mode.. .
Sk Hynix Inc.

Timing control circuit shared by a plurality of banks

Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal.
Micron Technology, Inc.

Memory with termination circuit

A semiconductor integrated circuit is described. A.
Renesas Electronics Corporation

Semiconductor memory device and refresh semiconductor memory device

A semiconductor memory device may include a row address generating circuit, a row active pulse generating circuit and a word line activating circuit. The row address generating circuit may generate a row address in response to a refresh command, a row active pulse, and a normal address.
Sk Hynix Inc.

Memory macro and semiconductor integrated circuit device

Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit.
Renesas Electronics Corporation

Stacked semiconductor device and system including the same

A stacked semiconductor device includes a plurality of semiconductor dies stacked in a vertical direction, first and second signal paths, a transmission unit and a reception unit. The first and second signal paths electrically connect the plurality of semiconductor dies, where each of the first signal path and the second signal path includes at least one through-substrate via.
Samsung Electronics Co., Ltd.

Word line voltage generator for multiple-time programmable memory

A word line voltage generator circuit, a semiconductor device, and an electronic device are provided. The word line voltage generator circuit includes a switch circuit connected to a high-level signal and a low-level signal and configured to output the high-level signal or the low-level signal as a word line voltage signal based on an input signal, and a drive signal control circuit configured to provide a drive signal connected to the switch circuit in response to the input signal.
Semiconductor Manufacturing International (beijing) Corporation

Light emitting period setting method, driving display panel, driving backlight, light emitting period setting apparatus , semiconductor device, display panel and electronic apparatus

Disclosed herein is a light emitting period setting method for a display panel wherein the peak luminance level is varied through control of a total light emitting period length which is the sum total of period lengths of light emitting periods arranged in a one-field period, including a step of setting period lengths of n light emitting periods, which are arranged in a one-field period, in response to the total light emitting period length such that the period lengths of the light emitting periods continue to keep a fixed ratio thereamong, n being equal to or higher than 3.. .
Sony Corporation

Semiconductor wafer inspection using care area group-specific threshold settings for detecting defects

In the methods and systems, optical images of inspection care areas on a semiconductor wafer are acquired and analyzed to detect defects. However, during this analysis, the same threshold setting is not used for all inspection care areas.
Globalfoundries Inc.

Part selling system

A person in charge of a company, a user of a semiconductor manufacturing apparatus, uses an information terminal to log in via the internet to a server of a part selling company selling, in an electronic shop, parts of the semiconductor manufacturing apparatus, and specifies a predetermined keyword for a part search. The person in charge specifies a sell-candidate part displayed as a search result, and requests detailed information to be displayed.
Screen Holdings Co., Ltd.



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  • Electric Conversion
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  • Semiconductor Devices
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  • Photoelectric Conversion
  • Electronic Device
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