|| List of recent Semiconductor-related patents
|Integrating optimal planar and three-dimensional semiconductor design layouts|
An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., finfet) semiconductor layout design, and combining the planar design and the finfet design in a common graphic data system..
A present design support method includes: arranging capacitance cells in an entire area of a cell arrangement area of a semiconductor integrated circuit , before arranging logic cells; upon detecting that a position at which a certain logic cell will be arranged is designated, calculating a total sum of capacitance for a first capacitance check area that includes the position among plural capacitance check areas that are included in the cell arrangement area, while assuming that a capacitance cell at the position is removed; calculating a total sum of necessary capacitance for the first capacitance check area, while assuming that the certain logic cell is arranged at the position and outputting information that represents a relationship between the total sum of capacitance and the total sum of necessary capacitance for the first capacitance check area.. .
|Deriving effective corners for complex correlations|
Systems and methods are described for simultaneously deriving an effective x-sigma corner for multiple, different circuit and/or process metrics for a semiconductor device. The result is an effective sigma that is representative of design intent.
|Method of designing arrangement of tsv in stacked semiconductor device and designing system for arrangement of tsv in stacked semiconductor device|
A method of designing arrangement of through silicon vias (tsvs) in a stacked semiconductor device is provided the method includes: determining a plurality of tsv candidate grids representing positions, into which the tsvs are insertable, in each of a plurality of semiconductor dies stacked mutually and included in a stacked semiconductor device; creating a plurality of path graphs representing linkable signal paths for a plurality of signals transmitted through the stacked semiconductor device, respectively, based on the tsv candidate grids; determining initial tsv insertion positions corresponding to shortest signal paths for the signals based on the path graphs; and determining final tsv insertion positions by verifying the initial tsv insertion positions so that a plurality of signal networks corresponding to the shortest signal paths for the signals have routability.. .
|Automated test equipment and control method thereof|
An automated test system for a semiconductor device to concurrently perform multiple device tests is provided. The system may include at least one test client, at least one test site and a test server.
|Semiconductor device and semiconductor system including the same|
A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to input/output a normal data synchronized with a center of a source clock, in response to data input/output commands; and a data recovery information signal input/output block configured to receive and store a data recovery information signal synchronized with an edge of the source clock and having a predetermined pattern, in response to either a command of the data input/output commands or the predetermined command upon entry to a data recovery operating mode, and to output the data recovery information signal after the passage of a predetermined time period.. .
|Electronic devices having semiconductor memory unit|
An electronic device includes: a variable resistance element having a first electrode, a variable resistance layer, and a second electrode which are sequentially stacked therein; a spacer formed on the sidewall of the variable resistance element; and a conductive line covering the variable resistance element including the spacer.. .
|Semiconductor memory device|
A semiconductor memory device includes a memory cell array having a plurality of memory cells, each memory cell configured to store plural bits of data, and a controller. The controller is configured to execute a write operation on the memory cells such that user data are written in at least one of the plural bits of data and prescribed data are written in the remaining bits of the plural bits of data.
|Semiconductor device and method of operating the same|
A semiconductor device includes a memory cell array includes a plurality of memory blocks, each of the memory blocks including a plurality of pages, wherein at least one of the plurality of memory blocks functions as a first storage unit to store a plurality of page addresses associated with the plurality of pages. A second storage unit loads a page address stored in the first storage unit.
|Semiconductor memory device and method of operating the same|
A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a buffer that inputs a first signal and outputs a first delay signal, a command decoder that outputs a second signal, a mask pulse signal generator that inputs the first delay signal and the second signal and generates a mask pulse signal, and a signal reshaper that inputs the first delay signal, the second signal and the mask pulse signal and reshapes the first delay signal or the second signal..
|Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks|
A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area..
|Semiconductor device with vias on a bridge connecting two buses|
A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses.
|System for simulating semiconductor device and related method of operation|
A system for simulating a semiconductor device comprises a data input module configured to receive structural data of the semiconductor device comprising a first region and a second region, and a spatial discretization generating module configured to divide a space of the semiconductor device using the structural data through division of the first region into first type meshes and division of the second region into second type meshes different from the first type meshes.. .
|Hybrid focus-exposure matrix|
A method for controlling semiconductor production through use of a hybrid focus exposure matrix (fem) model includes taking measurements of a set of structures formed onto a substrate. The method further includes using a fem model to determine focus and exposure conditions used to form the structure the model was created through use of measurements of structures formed on a substrate under varying focus and exposure conditions, the measurements being taken using both an optical measurement tool and a scanning electron microscope..
|Multi-functional hybrid devices/structures using 3d printing|
A bioelectronic device and method of making is disclosed. The device includes a scaffold formed via 3d printing.
|Difluoro benzotriazolyl organic semiconductor material, preparation method and use thereof|
Wherein both r1 and r2 are c1 to c20 alkyl, and n is an integer from 10 to 50. In the difluoro benzotriazolyl organic semiconductor material, since the 1,2,3-benzotriazole organic semiconductor material contains two fluorine atoms, the homo energy level is reduced by 0.11 ev, while the fluorine-substituted 1,2,3-benzotriazole has two imido groups with electron-withdrawing ability; the fluorine-substituted 1,2,3-benzotriazole is a heterocyclic compound with strong electron-withdrawing ability, and an alkyl chain can be easily introduced to the n-position of the n—h bond of the benzotriazole.
|Silanol condensation catalyst, heat-curable silicone resin composition for sealing photosemiconductors and sealed photosemiconductor using same|
A silanol condensation catalyst including at least the zirconium metal salt expressed by formula (i) below (wherein n is an integer from 1 to 3; each r1 is a hydrocarbon group having from 1 to 16 carbons; and each r2 is a hydrocarbon group having from 1 to 18 carbons. A heat-curable silicone resin composition for sealing optical semiconductors includes 100 parts by mass of a polysiloxane containing two or more silanol groups in the molecule; from 0.1 to 2,000 parts by mass of a silane compound containing two or more alkoxy groups that are bonded to a silicon atom in the molecule; and a zirconium metal salt expressed by formula (i).
|Oriented photocatalytic semiconductor surfaces|
The present disclosure relates to oriented photocatalytic semiconductor surfaces which may include photocatalytic capped colloidal nanocrystals (pccns) positioned all in the same orientation. The photoactive material may be employed in a plurality of photocatalytic energy conversion applications such as the photocatalytic reduction of carbon dioxide and water splitting, among others.
|Reducing insertion loss in lna bypass mode by using a single-pole-triple-throw switch in a rf front end module|
A microwave radio frequency (rf) front end module (fem) having a low noise amplifier (lna) with a bypass mode uses a single-pole-triple-throw rf switch that reduces insertion loss to about 1 db and thereby improves rf receiver sensitivity over existing technology two series connected single-pole-double throw rf switches. The single-pole-triple-throw rf switch may be three metal oxide semiconductor field effect transistor (mosfet) rf switches that may be arranged with a common source input and isolated independent drain outputs.
|Broad spectrum, endpoint detection window chemical mechanical polishing pad and polishing method|
A chemical mechanical polishing pad is provided, comprising: a polishing layer having a polishing surface; and, a broad spectrum, endpoint detection window block having a thickness along an axis perpendicular to a plane of the polishing surface; wherein the broad spectrum, endpoint detection window block, comprises an olefin copolymer; wherein the olefin copolymer, comprises, as initial components: ethylene, a branched or straight chain c3-30 α-olefin; a silane; and, optionally, a polyolefin; wherein the broad spectrum, endpoint detection window block exhibits a uniform chemical composition across its thickness; wherein the broad spectrum, endpoint detection window block exhibits a spectrum loss ≦60%; and, wherein the polishing surface is adapted for polishing a substrate selected from a magnetic substrate, an optical substrate and a semiconductor substrate.. .
|Chemical mechanical polishing pad with broad spectrum, endpoint detection window and method of polishing therewith|
A chemical mechanical polishing pad is provided, comprising: a polishing layer having a polishing surface; and, a broad spectrum, endpoint detection window block having a thickness along an axis perpendicular to a plane of the polishing surface; wherein the broad spectrum, endpoint detection window block, comprises a cyclic olefin addition polymer; wherein the broad spectrum, endpoint detection window block exhibits a uniform chemical composition across its thickness; wherein the broad spectrum, endpoint detection window block exhibits a spectrum loss ≦40%; and, wherein the polishing surface is adapted for polishing a substrate selected from a magnetic substrate, an optical substrate and a semiconductor substrate.. .
|Process sheet resistance uniformity improvement using multiple melt laser exposures|
Embodiments described herein relate to apparatus and methods of thermal processing. More specifically, apparatus and methods described herein relate to laser thermal treatment of semiconductor substrates by increasing the uniformity of energy distribution in an image at a surface of a substrate..
|Apparatus for manufacturing semiconductor device, method of manufacturing semiconductor device, and recording medium|
An apparatus for manufacturing semiconductor devices is provided with a processing liquid supply part for supplying processing liquid into a processing chamber which houses a substrate, a heater part for heating the processing liquid in the processing chamber, and a substrate support part which is provided in the processing chamber and supports the substrate.. .
A method of producing silicon containing thin films by the thermal polymerization of a reactive gas mixture bisaminosilacyclobutane and source gas selected from a nitrogen providing gas, an oxygen providing gas and mixtures thereof. The films deposited may be silicon nitride, silicon carbonitride, silicon dioxide or carbon doped silicon dioxide.
|Imprint mask, method for manufacturing the same, and method for manufacturing semiconductor device|
According to one embodiment, an imprint mask includes a quartz plate. The quartz plate has a plurality of concave sections formed in part of an upper surface on the quartz plate, and impurities are contained in a portion between the concave sections in the quartz plate..
|Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium|
A method of manufacturing a semiconductor device, includes treating a surface of an insulating film formed on a substrate by supplying a first precursor including a predetermined element and a halogen group to the substrate; and forming a thin film including the predetermined element on the treated surface of the insulating film by performing a cycle a predetermined number of times, the cycle comprising: supplying a second precursor including the predetermined element and the halogen group to the substrate; and supplying a third precursor to the substrate.. .
|Multilayer dielectric structures for semiconductor nano-devices|
Multilayer dielectric structures are provided having silicon nitride (sin) and silicon oxynitride (sino) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more sin layers and one or more sino layers.
|Substrate processing apparatus, substrate processing method, method of manufacturing semiconductor device and recording medium|
A substrate processing apparatus comprising: a processing chamber that can accommodate a plurality of substrates, the interior of which is divided into a plurality of zones; a gas supply system that supplies a first reactive gas, a second reactive gas, and an inert gas to each of the plurality of zones; and an exhaust system for removing the gas from the zones. A thin film is formed on the substrates in the zones by repeatedly executing a plurality of steps in relation to the zones, these steps include the following: a first reactive gas supply step; a first purge step; a second reactive gas supply step; and a second purge step.
|Semiconductor fin formation method and mask set|
A mask set and method for forming finfet semiconductor devices provides a complementary set of fin-cut masks that are used in dpt (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks..
|Methods for fabricating integrated circuits utilizing silicon nitride layers|
A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (pecvd) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval.
|Self-aligned trench over fin|
A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch.
|Method and equipment for removing photoresist residue after dry etch|
A method for removing photoresist residue includes etching a photoresist layer disposed over a front side of a semiconductor substrate during fabrication of a semiconductor device, and exposing at least one of the front side and the back side of the semiconductor substrate to an atmosphere comprising active oxygen. The method further includes cleaning at least one of the front side and the back side of the semiconductor substrate with a cleaning fluid..
|Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material|
A method includes providing a semiconductor structure including a substrate and a transistor element. A layer of a spacer material is deposited over the substrate and the gate structure, wherein the deposited layer of spacer material has an intrinsic stress.
|Method and apparatus for improving cmp planarity|
Provided is a method of planarizing a semiconductor device. A dielectric layer is formed over a substrate.
|Method for patterning semiconductor structure|
A method for patterning a semiconductor structure is provided. The method comprises following steps.
|Semiconductor film deposition apparatus and method with improved heater cooling efficiency|
Provided is a physical vapor deposition apparatus with one or multiple deposition chambers for depositing films on substrates. The deposition chambers includes a heater and various cooling features to cool the chamber, the heater and the substrate.
|Semiconductor device and method for fabricating the same|
A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer.. .
|In-situ metal gate recess process for self-aligned contact application|
A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (cmp) processes to planarize the formed gate structure using a cmp tool.
|Method for forming polysilicon using high energy radiation source|
A method for forming polysilicon using high energy sources of radiation includes the steps of providing a laser system which has at least two laser sources with different wavelengths, a dichroic mirror, a reflecting mirror and a substrate; generating a laser beam by the laser sources to irradiate towards the substrate perpendicularly by the dichroic mirror and the reflecting mirror which are faced to the laser source and meet the laser sources at a certain angle; placing the reflecting mirror above the dichroic mirror; placing the a semiconductor thin-film material on the substrate. The advantages of the above technical solution are that as follows: the crystallization rate of poly-silicon is effectively increased; the usage frequency of the excimer laser is reduced; the cost thereof is reduced; the throughput of annealing is affectively improved..
|Semiconductor device and manufacturing method thereof|
There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly w, a material film containing mainly al, and a material film containing mainly ti to reduce a wiring resistance.
A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material.
|Semiconductor device and method for forming the same|
A method includes forming a recess in a substrate and filling a dielectric layer in the recess. The method further includes forming a capping layer over the substrate and the dielectric layer.
|Semiconductor devices and methods of fabricating the same|
Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate.
|Method for manufacturing semiconductor device|
A method for manufacturing a semiconductor device is disclosed. In one aspect the method includes forming a gate stack over a substrate.
|High gate density devices and methods|
A method of forming a semiconductor device includes providing a semiconductor substrate and forming a plurality of dummy gate structures in the substrate. The method further includes forming sidewall spacers on sidewalls of the dummy gate structures and forming a plurality of epitaxial growth regions between the dummy gate structures.
|Prevention of fin erosion for semiconductor devices|
A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer.
|Self-aligned passivation of active regions|
A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin.
|Manufacturing method of vertical channel transistor array|
A manufacturing method of a vertical channel transistor array is provided. The method includes following steps.
|Method for fabricating electronic devices having semiconductor memory unit|
Devices and methods based on disclosed technology include, among others, an electronic device including silicide layers capable of effectively reducing contact resistance in the electronic device including buried gates and a method for fabricating the electronic device. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate and silicide layers formed over the substrate between the buried gates and protruding upwardly from the buried gates..
|Methods of fabricating three dimensional semiconductor memory devices|
A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates.
|Memories with memory arrays extending in opposite directions from a semiconductor and their formation|
Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor.
|Methods for forming integrated circuit systems employing fluorine doping|
A method for forming a semiconductor device is provided which includes providing a gate structure in an active region of a semiconductor substrate, wherein the gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to the gate structure and, thereafter, performing a fluorine implantation process. Also a method for forming a cmos integrated circuit structure is provided which includes providing a semiconductor substrate with a first active region and a second active region, forming a first gate structure in the first active region and a second gate structure in the second active region, wherein each gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to each of the first and second gate structures and, thereafter, performing a fluorine implantation process..
|Semiconductor device and method for manufacturing semiconductor device|
A semiconductor device is provided, which includes a single crystal semiconductor layer formed over an insulating surface and having a source region, a drain region, and a channel formation region, a gate insulating film covering the single crystal semiconductor layer and a gate electrode overlapping with the channel formation region with the gate insulating film interposed therebetween. In the semiconductor device, at least the drain region of the source and drain regions includes a first impurity region adjacent to the channel formation region and a second impurity region adjacent to the first impurity region.
|Method for manufacturing semiconductor device|
To provide a manufacturing method of a highly reliable tft, by which a more refined pattern can be formed through a process using four or three masks, and a semiconductor device. A channel-etched bottom gate tft structure is adopted in which a photoresist is selectively exposed to light by rear surface exposure utilizing a gate wiring to form a desirably patterned photoresist, and further, a halftone mask or a gray-tone mask is used as a multi-tone mask.
|Finfets and methods for forming the same|
Methods for forming a semiconductor device and a finfet device are disclosed. A method comprises forming a dummy gate electrode layer over a substrate, the dummy gate electrode layer having a first height, forming a first etch stop layer on the dummy gate electrode layer, forming a first hard mask layer on the first etch stop layer, and patterning the first hard mask layer.
|Finfet device structure and methods of making same|
Embodiments of the present disclosure are a method of forming a semiconductor device and a method of forming a finfet device. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first hardmask layer on the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width.
|Methods for bonding a die and a substrate|
Embodiments of methods for forming a semiconductor device that includes a die and a substrate include pressing together the die and the substrate such that a first gold layer and one or more additional material layers are between the die and the substrate, and performing a bonding operation to form a die attach layer between the die and the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold.
|Stacked semiconductor packages|
Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device..
|Semiconductor device having chip mounted on an interposer|
A semiconductor device 100 includes: a first semiconductor package 10; a first interposer 12 having an upper surface on which the first semiconductor package 10 is mounted; a first molding resin 14 that is provided on the upper surface of the first interposer 12 and seals the first semiconductor package 10; a second semiconductor package 20 mounted on an upper surface of the first molding resin 14; a second interposer 22 on which the second semiconductor package 20 is mounted by flip chip bonding; and a second molding resin 40 that is provided on the upper surface of the first interposer 12 and seals the first molding resin 14, the second semiconductor package 20, and the second interposer 22. The second semiconductor package 20 is mounted, with a surface thereof opposite to another surface mounted on the second interposer 22 faced down, on the upper surface of the first molding resin 14 via an adhesive 30..
|Manufacturing method of semiconductor device|
A transistor with superior electric characteristics is manufactured. An oxide insulating film is formed over a substrate, an oxide semiconductor film is formed over the oxide insulating film, heat treatment is then conducted at a temperature at which hydrogen contained in the oxide semiconductor film is desorbed and part of oxygen contained in the oxide insulating film is desorbed, then the heated oxide semiconductor film is etched into a predetermined shape to form an island-shaped oxide semiconductor film, a pair of electrodes is formed over the island-shaped oxide semiconductor film, a gate insulating film is formed over the pair of electrodes and the island-shaped oxide semiconductor film, and a gate electrode is formed over the gate insulating film..
|Method of manufacturing an organic semiconductor thin film|
A method of manufacturing an organic semiconductor thin film includes coating an organic semiconductor solution on a substrate, and shearing the organic semiconductor solution in a direction that results in a shearing stress being applied to the organic semiconductor solution to form the organic semiconductor thin film, wherein a speed of the shearing is controlled such that an intermolecular distance of the organic semiconductor solution is adjusted.. .
|Semiconductor device pn junction fabrication using optical processing of amorphous semiconductor material|
Systems and methods for semiconductor device pn junction fabrication are provided. In one embodiment, a method for fabricating an electrical device having a p-n junction comprises: depositing a layer of amorphous semiconductor material onto a crystalline semiconductor base, wherein the crystalline semiconductor base comprises a crystalline phase of a same semiconductor as the amorphous layer; and growing the layer of amorphous semiconductor material into a layer of crystalline semiconductor material that is epitaxially matched to the lattice structure of the crystalline semiconductor base by applying an optical energy that penetrates at least the amorphous semiconductor material..
|Semiconductor processing by magnetic field guided etching|
Methods, systems, and devices are described for slicing and shaping materials using magnetically guided chemical etching. In one aspect, a method includes forming a pattern on a substrate by a mask, depositing a catalytic etcher layer on the patterned substrate, a magnetic guide layer on the etcher layer, and a protection layer on the guide layer, etching the substrate by applying an etching solution to the substrate that chemically reacts with the etcher layer and etches material from the substrate at exposed regions not covered by the mask, steering the composite etching structure into the substrate during the etching by an applied magnetic field that creates a force on the guide layer to direct the etching, in which the steering defines the shape of the sliced regions of the etched substrate, and removing the etched material, the mask, and the composite etching structure to produce a sliced material structure..
|Display device and method for manufacturing the same|
A display device includes a substrate; a gate wire including a gate electrode and a first capacitor electrode formed on the substrate; a gate insulating layer formed on the gate wire; a semiconductor layer pattern formed on the gate insulating layer, and including an active region overlapping at least a part of the gate electrode and a capacitor region overlapping at least a part of the first capacitor electrode; an etching preventing layer formed on a part of the active region of the semiconductor layer pattern; and a data wire including a source electrode and a drain electrode formed over the active region of the semiconductor layer from over the etching preventing layer, and separated with the etching preventing layer therebetween, and a second capacitor electrode formed on the capacitor region of the semiconductor layer.. .
|Semiconductor light emitting device packages and methods|
A submount for a light emitting device package includes a substrate with a first bond pad and a second bond pad on a first surface. The first bond pad includes a die attach region offset toward a first end of the substrate and configured to receive a light emitting diode.
|Structure and method for e-beam in-chip overlay mark|
The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction.
|Radiofrequency adjustment for instability management in semiconductor processing|
Methods, systems, and computer programs are presented for reducing chamber instability while processing a semiconductor substrate. One method includes an operation for identifying a first recipe with steps having an operating frequency equal to the nominal frequency of a radiofrequency (rf) power supply.
|Contactless communications using ferromagnetic material|
A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil.
|Semiconductor micro-analysis chip and sample liquid flowing method|
According to one embodiment, a semiconductor micro-analysis chip for detecting fine particles in sample liquid includes a semiconductor substrate, a flow channel formed in the semiconductor substrate and having a sample liquid inlet and sample liquid outlet at end portions thereof, and an absorber provided on at least part of the sample outlet of the flow channel to absorb the sample liquid.. .
|Semiconductor micro-analysis chip and manufacturing method thereof|
According to one embodiment, a semiconductor micro-analysis chip for detecting fine particles in sample liquid includes a semiconductor substrate, a first flow channel that is formed in the semiconductor substrate and into which the sample liquid is introduced, and a plurality of columnar structures fully arranged in the first flow channel at regulation distance.. .