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Semiconductor patents



      

This page is updated frequently with new Semiconductor-related patent applications.




Date/App# patent app List of recent Semiconductor-related patents
05/19/16
20160143193 
 Vehicular power conversion device patent thumbnailVehicular power conversion device
A vehicular power conversion device is provided with a semiconductor that converts power. The power conversion device is provided with: coolers that are arranged in an array in a vehicle advancement direction and cool the semiconductor; and a cooler cover having the coolers located therein and provided with ventilation openings serving as an intake port and a discharge port for travel-generated airflow.
Mitsubishi Electric Corporation


05/19/16
20160143187 
 Semiconductor device and  manufacturing the same patent thumbnailSemiconductor device and manufacturing the same
A semiconductor device includes a semiconductor module which has an external terminal protruding from one surface thereof; a printed circuit board which is electrically and mechanically connected to the external terminal of the semiconductor module; a heatsink which abuts against the other surface of the semiconductor module opposite to the one surface; and a joint member which serves as an elastic support column having a first head portion and a second head portion. The first head portion is shaped like a truncated cone and disposed at one end of the elastic support column, and the second head portion is disposed at the other end of the elastic support column.
Fuji Electric Co., Ltd.


05/19/16
20160143156 
 Reflow treating unit and substrate treating apparatus patent thumbnailReflow treating unit and substrate treating apparatus
Provided are a semiconductor substrate manufacturing apparatus and a substrate treating method, and more particularly, an apparatus and method for performing a reflow treating process on a semiconductor wafer. The apparatus treating apparatus includes a load port on which a carrier accommodating a substrate is seated, a substrate treating module including one reflow treating unit or a plurality of reflow treating units for performing a reflow process on the substrate, and a substrate transfer module including a transfer robot transferring the substrate between the load port and the substrate treating module, the substrate transfer module being disposed between the load port and the substrate treating module.
Semigear, Inc


05/19/16
20160143155 
 Reflow treating unit and substrate treating apparatus patent thumbnailReflow treating unit and substrate treating apparatus
Provided are a semiconductor substrate manufacturing apparatus and a substrate treating method, and more particularly, an apparatus and method for performing a reflow treating process on a semiconductor wafer. The apparatus treating apparatus includes a load port on which a carrier accommodating a substrate is seated, a substrate treating module including one reflow treating unit or a plurality of reflow treating units for performing a reflow process on the substrate, and a substrate transfer module including a transfer robot transferring the substrate between the load port and the substrate treating module, the substrate transfer module being disposed between the load port and the substrate treating module.
Semigear, Inc.


05/19/16
20160143149 
 Semiconductor package structure and semiconductor process patent thumbnailSemiconductor package structure and semiconductor process
Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias.
Advanced Semiconductor Engineering, Inc.


05/19/16
20160143133 
 Printed wiring board, semiconductor device and printed circuit board patent thumbnailPrinted wiring board, semiconductor device and printed circuit board
A printed wiring board includes conductive layers laminated with insulator layers interposed. A land group including a plurality of lands arranged with intervals between each other, is formed in a rectangular region on a surface layer, among the plurality of conductive layers, when viewed in a direction perpendicular to the surface layer.
Canon Kabushiki Kaisha


05/19/16
20160143100 
 Semiconductor light source driving apparatus and projection type display apparatus patent thumbnailSemiconductor light source driving apparatus and projection type display apparatus
A semiconductor light source driving apparatus includes a light source unit which has a plurality of series-connected light source modules. Each light source module includes: a switching element which is controlled to turn on/off by a control signal; series-connected light source elements; and an overvoltage detection circuit in which a zener diode and a light emitting element are connected in series and a light detecting element is disposed to face the light emitting element, the switching element, the light source elements, and the overvoltage detection circuit being connected in parallel to each other.
Panasonic Intellectual Property Management Co., Ltd.


05/19/16
20160142828 
 Micro phone sensor patent thumbnailMicro phone sensor
A microphone, that increases sensitivity without a separate circuit is provided. The microphone includes an audio detection module having a vibration film that outputs capacitance signals by vibrating audio introduced from the exterior and a piezoresistive element that outputs a piezoresistive signal by a sound pressure of the audio.
Hyundai Motor Company


05/19/16
20160142630 
 Image sensor,  manufacturing the same, and image processing device having the image sensor patent thumbnailImage sensor, manufacturing the same, and image processing device having the image sensor
An image sensor comprising: a first layer having a plurality of groups of photodiodes formed in a semiconductor substrate, each group representing a 2×2 array of photodiodes, with 2 first pixels configured to detect light of a first wavelength and 2 second pixels configured to detect light of a second wavelength, each first pixel positioned adjacent to the second pixels; and a second layer overlapping the first layer, the second layer is organic, having a plurality of organic photodiodes configured to detect light of a third wavelength, each organic photodiode positioned to partially overlap 2 first photodiodes and 2 second photodiodes of the first layer.. .
Samsung Electronics Co., Ltd.


05/19/16
20160142155 
 Semiconductor packages with optical interconnection structures, memory cards including the same, and electronic systems including the same patent thumbnailSemiconductor packages with optical interconnection structures, memory cards including the same, and electronic systems including the same
A semiconductor package includes a first transceiver disposed on a top surface of a substrate; and a second transceiver disposed on a bottom surface of the substrate. The first and second transceivers optically communicate with each other through optical signals that permeate the substrate..
Sk Hynix Inc.


05/19/16
20160142055 

Semiconductor device


A semiconductor device includes a first circuit applying an enable signal having a first logic level and a clock signal having the first logic level, supplying a first voltage to a first node and converting a voltage level of the first node into a second logic level different from the first logic level, and a second circuit applying an enable signal having the second logic level and a clock signal having the first logic level, supplying a second voltage to a second node different from the first node and converting a voltage level of the second node into the second logic level. The second circuit includes an operation circuit performing a nand operation on the logic level of the enable signal and the voltage level of the second node, and a switch turned on in response to an output of the operation circuit and supplying the second voltage to the second node..

05/19/16
20160142050 

Multiple-unit semiconductor device and controlling the same


Provided are a multiple-unit semiconductor device that enables space savings and a method for controlling such a semiconductor device. A multiple-unit semiconductor device is brought into conduction by a si-fet being brought into conduction first and a gan device being brought into conduction after the si-fet has been brought into conduction..
Sharp Kabushiki Kaisha


05/19/16
20160142047 

Semiconductor device


A sample-and-hold circuit including a transistor and a capacitor is connected to the differential circuit. The sample-and-hold circuit acquires voltage for correcting the offset voltage of the differential circuit by charging or discharging the capacitor through sampling operation.
Semiconductor Energy Laboratory Co., Ltd.


05/19/16
20160142015 

High frequency amplifier


A high frequency amplifier includes a high frequency amplifier transistor integrated in a first die of a first semiconductor technology and a matching circuit. The high frequency amplifier transistor has an input terminal, an output terminal and a reference terminal.
Freescale Semiconductor, Inc.


05/19/16
20160142011 

Semiconductor device


A semiconductor device is formed by sealing, with a resin, a semiconductor chip (cp1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
Renesas Electronics Corporation


05/19/16
20160141890 

Wireless power transfer - near field communication enabled communication device


Various configurations and arrangements of various communication devices are disclosed. Various integrated circuits that form these communication devices can be fabricated onto one or more semiconductor substrates, chips, and/or dies using a high voltage semiconductor process, a low voltage semiconductor process, or any combination thereof.
Broadcom Corporation


05/19/16
20160141883 

Control circuit, resonance circuit, electronic device, control method, control program, and semiconductor element


A control circuit, resonant circuit, electronic device, control method, control program, and a semiconductor element, which enable a circuit to be measured and tuned within a short time even in consideration of a time constant when a control voltage is applied to a variable capacitance capacitor. A control circuit for a variable capacitance capacitor includes: a digital-analog converter that outputs a control voltage consisting of a variable dc voltage; the variable capacitance capacitor that has a capacitance varying with an application of the control voltage; a phase detector that acquires a characteristic of a circuit containing the variable capacitance capacitor; an analog-digital converter that subjects an analog signal from the phase detector to a digital conversion; a comparing section that compares a target value with a detected value; and a control section that sets the control voltage for the digital-analog converter on the basis of the comparison result..
Dexerials Corporation


05/19/16
20160141870 

Multilevel power convertor


Basic circuit of u phase includes first to fourth semiconductor elements (su1.1 to su1.4) connected between positive and negative ends of dc voltage source (dcc1), fifth semiconductor element (su1.5) connected to a common connection point of the first and second semiconductor elements (su1.1, su1.2), and sixth semiconductor element (su1.6) connected to a common connection point of the third and fourth semiconductor elements (su1.3, su1.4). Flying capacitor (fc1) is inserted between the fifth semiconductor element (su1.5) and the sixth semiconductor element (su1.6).
Meidensha Corporation


05/19/16
20160141837 

Edge-emitting semiconductor laser and the production thereof


An edge-emitting semiconductor laser includes a semiconductor structure having a waveguide layer with an active layer, the waveguide layer extending in a longitudinal direction between first and second side facets of the semiconductor structure, the semiconductor structure has a tapering region adjacent to the first side facet, a thickness of the waveguide layer in the tapering region increases longitudinally, the waveguide layer is arranged between first and second cladding layers, a thickness of the second cladding layer in the tapering region of the semiconductor structure increases longitudinally, the tapering region includes first and second subregions, the first subregion is arranged closer to the first side facet than the second subregion, thickness of the waveguide layer increases longitudinally in the first subregion, thickness of the waveguide layer is constant in the longitudinal direction in the second subregion, and thickness of the second cladding layer increases longitudinally in the second subregion.. .
Osram Opto Semiconductors Gmbh


05/19/16
20160141836 

Monolithic nano-cavity light source on lattice mismatched semiconductor substrate


An optoelectronic light emission device is provided that includes a gain region of at least one type iii-v semiconductor layer that is present on a lattice mismatched semiconductor substrate. The gain region of the type iii-v semiconductor layer has a nanoscale area using nano-cavities.
International Business Machines Corporation


05/19/16
20160141834 

Method for controlling amplifying unit including variable optical attenuator and semiconductor optical amplifier


A method to control an amplifying unit including a variable optical attenuator voa and a semiconductor optical amplifier soa is disclosed. The method first sets the attenuation of the voa in a value realizable in the voa and the optical gain of the soa in a value where the soa may operate in an optimum range.
Sumitomo Electric Device Innovations, Inc.


05/19/16
20160141832 

Laser apparatus and optical transmitter


A laser apparatus includes a semiconductor laser of which a drive condition is controlled according to a plurality of types of drive currents and a controller which controls the drive condition such that a sum of the drive currents is equal to or less than a predetermined threshold value.. .
Fujitsu Optical Components Limited


05/19/16
20160141829 

Laser support for semiconductor laser fixation and laser support element assembly


Simultaneously setting the adhesive in said windows (51, 52) by means of ultraviolet light penetrating simultaneously into said windows (51, 52).. .

05/19/16
20160141770 

Electrical connection module, semiconductor module and producing a semiconductor module


An electrical connection module system includes a first connection plate with a first connection end and at least one first foot section, a first screw nut, and a dielectric holder. The dielectric holder has a first reception region for receiving the first screw nut.
Infineon Technologies Ag


05/19/16
20160141531 

Thin film transistor


A thin film transistor includes: a gate electrode; a gate insulating layer that covers the gate electrode; a source electrode and a drain electrode that are provided on the gate insulating layer; and an organic semiconductor layer that has a channel region between the source electrode and the drain electrode. The source electrode and the drain electrode each include a first conductive layer that increases adhesion with the gate insulating layer; a second conductive layer that has low electrical resistance; and a third conductive layer that make ohmic contact with the organic semiconductor layer.
Sharp Kabushiki Kaisha


05/19/16
20160141530 

Semiconductor element and semiconductor element manufacturing method


In an organic tft (1), a material used for uppermost layers (14b, 15b) of a source electrode (14) and a drain electrode (15) has a smaller difference in work function relative to a material used for a semiconductor layer (16) than does a material used for layers of the source electrode (14) and the drain electrode (15) other than the uppermost layers (14a, 14b). The top surfaces and side faces of the uppermost layers of the source electrode (14) and the drain electrode (15) contact the semiconductor layer (16) directly, and the layers of the source electrode (14) and the drain electrode (15) other than the uppermost layers are separated from the semiconductor layer (16) by a second gate insulating layer (12)..
Sharp Kabushiki Kaisha


05/19/16
20160141529 

Method for producing an organic cmos circuit and organic cmos circuit protected against uv radiation


An organic cmos circuit including a substrate having an n-type organic transistor and a p-type organic transistor formed thereon, the transistors respectively including a layer of n-type semiconductor material and a layer of p-type semiconductor material. A surface of each of the semiconductor material layers, opposite to the substrate, is covered with an anti-ultraviolet layer made of electrically-insulating material absorbing and/or reflecting ultra-violet rays..
Commissariat A L'energie Atomique Et Aux Energies Alternatives


05/19/16
20160141500 

Solar cell


An solar cell of an embodiment includes a first electrode, an electron transport layer containing a metal oxide, a self-assembled monolayer, a photoelectric conversion layer including a p-type semiconductor and an n-type semiconductor, and a second electrode. The self-assembled monolayer includes a fullerene-containing compound having a fullerene portion including a fullerene or a fullerene derivative, an absorption group to the metal oxide, and a bond group bonding the fullerene portion and the absorption group.
Kabushiki Kaisha Toshiba


05/19/16
20160141495 

Memory device constructions, memory cell forming methods, and semiconductor construction forming methods


Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a schottky diode having a semiconductor anode and a metal cathode and the second diode is a schottky diode having a metal anode and a semiconductor cathode..
Micron Technology, Inc.


05/19/16
20160141482 

Manufacturing process of the thermoelectric conversion element


A manufacturing process of a thermoelectric conversion element is provided, which is characterized of applying the semiconductor technology to construct the thermoelectric conversion element with a nano/micro gap to reduce the heat conduction coefficient of the thermoelectric conversion element, so as to significantly enhance the thermoelectric conversion efficiency of the thermoelectric conversion element. In addition, by adding a nano additive in the nano/micro gap of the thermoelectric conversion element, the conductivity of the thermoelectric conversion element can be increased and the efficiency of the heat power conversion can further be promoted..
National Tsing Hua University


05/19/16
20160141469 

Optoelectronic device with light-emitting diodes


An optoelectronic device including an array of light-emitting diodes and photoluminescent blocks opposite at least part of the light-emitting diodes, each light-emitting diode having a lateral dimension smaller than 30 μm, each photoluminescent block including semiconductor crystals having an average size smaller than 1 μm, dispersed in a binding matrix.. .
Alcatel Lucent


05/19/16
20160141466 

Thin film light emitting diode


Light emitting devices comprise a substrate having a surface and a side surface; a semiconductor structure on the surface of the substrate, the semiconductor structure having a first surface, a second surface and a side surface, wherein the second surface is opposite the first surface, wherein the first surface, relative to the second surface, is proximate to the substrate, and wherein the semiconductor structure comprises a first-type layer, a light emitting layer and a second-type layer; a first and a second electrodes; and a wavelength converting element arranged on the side surface of the semiconductor structure, wherein the wavelength converting element has an open space, and wherein the open space is a portion not covered by the wavelength converting element.. .
Lg Innotek Co., Ltd.


05/19/16
20160141463 

Composite having semiconductor structures embedded in a matrix


semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot.

05/19/16
20160141457 

Light-emitting device


A light-emitting device includes: a substrate; a light-emitting structure including first and second nitride-based semiconductor layers on the substrate and an active layer between the first and second nitride-based semiconductor layers; an insulating layer on a top surface of the light-emitting structure; a protrusion on the insulating layer, a top surface of the protrusion being larger than a bottom surface thereof, the protrusion having a trapezoidal cross-section; a transparent conductive layer covering a top surface of the light-emitting structure, a top surface of the insulating layer, and the top surface of the protrusion and having a constant thickness along the top surface of the light-emitting structure, the top surface of the insulating layer, and the top surface of the protrusion; and an electrode covering at least one of inclined surfaces of the protrusion on the transparent conductive layer.. .
Samsung Electronics Co., Ltd.


05/19/16
20160141455 

Light emitting device and manufacturing the same


A light-emitting device includes a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer and having a plurality of v-pits. The light-emitting device further includes a layer-quality improvement layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer and having a plurality of v-pits with substantially same size and shape as the plurality of v-pits of the active layer, wherein layer-quality improvement layer is a group iii-v semiconductor layer including al or in.

05/19/16
20160141451 

Method for manufacturing a semiconductor structure and semiconductor component comprising such a semiconductor structure


A method for manufacturing at least one semiconductor structure, and a component including a structure formed with the method, the method including: providing a substrate including at least one semiconductor silicon surface; forming an amorphous silicon carbide layer in contact with at least one part of the semiconductor silicon surface; forming the at least one semiconductor structure in contact with the silicon carbide layer, the structure including at least one part, as a contact part, in contact with the surface of the silicon carbide layer, which includes gallium.. .
Commissariat A L'energie Atomique Et Aux Energies Alternatives


05/19/16
20160141448 

Monolithic nano-cavity light source on lattice mismatched semiconductor substrate


An optoelectronic light emission device is provided that includes a gain region of at least one type iii-v semiconductor layer that is present on a lattice mismatched semiconductor substrate. The gain region of the type iii-v semiconductor layer has a nanoscale area using nano-cavities.
International Business Machines Corporation


05/19/16
20160141447 

Nitride semiconductor device and producing the same


A method for producing a nitride semiconductor device. The method comprises providing a substrate made of a material other than a nitride semiconductor.
Nichia Corporation


05/19/16
20160141446 

Method for manufacturing light emitting device


A method for manufacturing a light emitting device is provided. Step (a): a semiconductor wafer having a substrate and at least one epitaxial structure is provided.
Playnitride Inc.


05/19/16
20160141439 

Light detection device


A semiconductor light detection element includes a plurality of avalanche photodiodes operating in geiger mode and formed in a semiconductor substrate, quenching resistors connected in series to the respective avalanche photodiodes and arranged on a first principal surface side of the semiconductor substrate, and a plurality of through-hole electrodes electrically connected to the quenching resistors and formed so as to penetrate the semiconductor substrate from the first principal surface side to a second principal surface side. A mounting substrate includes a plurality of electrodes arranged corresponding to the respective through-hole electrodes on a third principal surface side.
Hamamatsu Photonics K.k.


05/19/16
20160141431 

Integrated solar collectors using epitaxial lift off and cold weld bonded semiconductor solar cells


There is disclosed ultrahigh-efficiency single- and multi-junction thin-film solar cells. This disclosure is also directed to a substrate-damage-free epitaxial lift-off (“elo”) process that employs adhesive-free, reliable and lightweight cold-weld bonding to a substrate, such as bonding to plastic or metal foils shaped into compound parabolic metal foil concentrators.
The Regents Of The University Of Michigan


05/19/16
20160141428 

Process for manufacturing a semiconductor device comprising an empty trench structure and semiconductor device manufactured thereby


The process is based upon the steps of: forming a trench in a body including a substrate and at least one insulating layer; and depositing a metal layer above the body for closing the open end or mouth of the trench. The trench is formed by selectively etching the body, wherein the reaction by-products deposit on the walls of the trench and form a passivation layer along the walls of the trench and a restriction element in proximity of the mouth of the trench..
Stmicroelectronics S.r.l.


05/19/16
20160141427 

Multi-channel field effect transistors using 2d-material


A device includes a semiconductor substrate, a buried oxide over the substrate, a first transition metal dichalcogenide layer over the buried oxide, an insulator over the first transition metal dichalcogenide layer, and a second transition metal dichalcogenide layer over the insulator. A gate dielectric is over the second transition metal dichalcogenide layer, and a gate is over the gate dielectric..
National Taiwan University


05/19/16
20160141423 

Contacts for highly scaled transistors


A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (s/d) regions, a channel between the first and second s/d regions, a gate engaging the channel, and a contact feature connecting to the first s/d region.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/19/16
20160141422 

Semiconductor device


A semiconductor device in which deterioration of electrical characteristics which becomes more noticeable as the transistor is miniaturized can be suppressed is provided. The semiconductor device includes an oxide semiconductor stack in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are stacked in this order from the substrate side over a substrate; a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor stack; a gate insulating film over the oxide semiconductor stack, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating film.
Semiconductor Energy Laboratory Co., Ltd.


05/19/16
20160141421 

Gate-all-around fin device


A gate-all around fin double diffused metal oxide semiconductor (dmos) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate.
International Business Machines Corporation


05/19/16
20160141417 

Semiconductor device and fabricating the same


A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction..
Samsung Electronics Co., Ltd.


05/19/16
20160141416 

Semiconductor devices and fabrication methods


Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material.
Micron Technology, Inc.


05/19/16
20160141415 

Semiconductor device and fabrication method thereof


A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a p type well region and an n type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the p type well region and the n type well region, a gate electrode formed on the gate insulating layer, a p type well pick-up region formed in the p type well region, and a field relief oxide layer formed in the n type well region between the gate electrode and the drain region..
Magnachip Semiconductor, Ltd.


05/19/16
20160141414 

Method and power device with depletion structure


A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate.
Vanguard International Semiconductor Corporation


05/19/16
20160141413 

Semiconductor devices


semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region..

05/19/16
20160141412 

Silicon carbide semiconductor device and manufacture thereof


A silicon carbide semiconductor device and method of manufacture thereof is made by providing a channel control zone which has impurity concentration distribution increased gradually from a first doping boundary to reach a maximum value between the first doping boundary and a second doping boundary, then decreased gradually toward the second doping boundary, so that the silicon carbide semiconductor device is formed with a lower conduction resistance and increased drain current without sacrificing threshold voltage.. .
Hestia Power Inc.


05/19/16
20160141410 

Semiconductor component with dynamic behavior


One embodiment provides a semiconductor component including a semiconductor body having a first side and a second side and a drift zone; a first semiconductor zone doped complementarily to the drift zone and adjacent to the drift zone in a direction of the first side; a second semiconductor zone of the same conduction type as the drift zone adjacent to the drift zone in a direction of the second side; at least two trenches arranged in the semiconductor body and extending into the semiconductor body and arranged at a distance from one another; and a field electrode arranged in the at least two trenches adjacent to the drift zone. The at least two trenches are arranged at a distance from the second semiconductor zone in the vertical direction, a distance between the trenches and the second semiconductor zone is greater than 1.5 times the mutual distance between the trenches, and a doping concentration of the drift zone in a section between the trenches and the second semiconductor zone differs by at most 35% from a minimum doping concentration in a section between the trenches..
Infineon Technologies Ag


05/19/16
20160141409 

Semiconductor device and manufacturing semiconductor device


A semiconductor device provided herein includes a trench in which a gate insulating layer (gil) and a gate electrode are located. A step is provided in a lateral surface of the trench.
Toyota Jidosha Kabushiki Kaisha


05/19/16
20160141408 

Super junction field effect transistor with internal floating ring


A super junction field effect transistor (fet) device includes a charge compensation region disposed on a substrate of semiconductor material. The charge compensation region includes a set of strip-shaped p− type columns, a floating ring-shaped p− type column that surrounds the set of strip-shaped p− type columns, and a set of ring-shaped p− type columns that surrounds the floating ring-shaped p− type column.
Ixys Corporation


05/19/16
20160141407 

Semiconductor device and manufacturing semiconductor device


A method of manufacturing a semiconductor device is provided, the method including forming a first gate member on a semiconductor substrate through a gate insulating film, forming a spacer on the first gate member, flattening a surface of the spacer, forming a first gate by partially etching the first gate member using the spacer as a mask, forming a second gate member so as to cover the first gate and the spacer having the flattened surface, forming a first insulating film on a surface of the second gate member, and forming a second gate by causing the second gate member to retreat while removing the first insulating film by etching.. .
Lapis Semiconductor Co., Ltd.


05/19/16
20160141406 

Semiconductor to metal transition


A semiconductor device includes a diffusion barrier layer, a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers. The first semiconductor region includes a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers, a contact region in contact with the diffusion barrier layer, the contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration, and a damage region between the contact region and the transition region.
Infineon Technologies Ag


05/19/16
20160141405 

Semiconductor field plate for compound semiconductor devices


A transistor includes a source, a drain spaced apart from the source, and a heterostructure body having a two-dimensional charge carrier gas channel for connecting the source and the drain. The transistor further includes a semiconductor field plate disposed between the source and the drain.
Infineon Technologies Austria Ag


05/19/16
20160141403 

Semiconductor device and insulated gate bipolar transistor with transistor cells and sensor cell


A transistor cell region of a semiconductor device includes transistor cells that are electrically connected to a first load electrode. An idle region includes a gate wiring structure that is electrically connected to gate electrodes of the transistor cells.
Infineon Technologies Ag


05/19/16
20160141402 

Semiconductor device


A semiconductor substrate is provided with a first cell region, the first cell region including: an n-type emitter region; a p-type first top body region; an n-type first barrier region; an n-type first pillar region; and a p-type first bottom body region, the semiconductor substrate may further comprise: an n-type drift region; a p-type collector region; an n-type cathode region, the n-type first barrier region may include a first peak position where a peak of the n-type impurity density is present within a part linked to the n-type first pillar region, and a second peak position where a peak of the n-type impurity density is present within a part in contact with the gate insulating layer, and a depth of the first peak position from a front surface of the semiconductor substrate is different from a depth of the second peak position from the front surface of the semiconductor substrate.. .
Toyota Jidosha Kabushiki Kaisha


05/19/16
20160141401 

Semiconductor device


A semiconductor device has emitter regions disposed in at least one cell region in a first inter-trench region, not disposed in a middle inter-trench region, and disposed in at least one cell region in the second inter-trench region. Each of the emitter regions is disposed at a position that is not in contact with first trenches but is in contact with two second trenches defining the corresponding cell region..
Toyota Jidosha Kabushiki Kaisha


05/19/16
20160141400 

Semiconductor device


A semiconductor device is configured such that the distance between the trench gate in the igbt and the trench gate in the diode is reduced or a p-well layer is provided between the trench gate in the igbt and the trench gate in the diode.. .
Mitsubishi Electric Corporation


05/19/16
20160141399 

Method for forming a semiconductor device and a semiconductor device


A method for forming a semiconductor device comprises implanting a defined dose of protons into a semiconductor substrate and tempering the semiconductor substrate according to a defined temperature profile. At least one of the defined dose of protons and the defined temperature profile is selected depending on a carbon-related parameter indicating information on a carbon concentration within at least a part of the semiconductor substrate..
Infineon Technologies Ag


05/19/16
20160141397 

Semiconductor device and manufacturing the same


A semiconductor device including a transistor having a reduced number of oxygen vacancies in a channel formation region of an oxide semiconductor with stable electrical characteristics or high reliability is provided. A gate insulating film is formed over a gate electrode; an oxide semiconductor layer is formed over the gate insulating film; an oxide layer is formed over the oxide semiconductor layer by a sputtering method to form an stacked-layer oxide film including the oxide semiconductor layer and the oxide layer; the stacked-layer oxide film is processed into a predetermined shape; a conductive film containing ti as a main component is formed over the stacked-layer oxide film; the conductive film is etched to form source and drain electrodes and a depression portion on a back channel side; and portions of the stacked-layer oxide film in contact with the source and drain electrodes are changed to an n-type by heat treatment..
Semiconductor Energy Laboratory Co., Ltd.


05/19/16
20160141396 

Semiconductor device and manufacturing same


To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration.
Renesas Electronics Corporation


05/19/16
20160141395 

Sige and si finfet structures and methods for making the same


Finfet structures and methods for making the same. A method includes: creating a plurality of silicon fins on a first region of a substrate, creating a plurality of silicon-germanium fins on a second region of the substrate, adjusting a silicon fin pitch of the plurality of silicon fins to a predetermined value, and adjusting a silicon-germanium fin pitch of the plurality of silicon-germanium fins to a predetermined value, where the creating steps are performed in a manner that silicon material and silicon-germanium material used in making the plurality of fins will be on the semiconductor structure at a same time..
International Business Machines Corporation


05/19/16
20160141394 

Semiconductor device and making


A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ild) layer proximate the gate structure, an ild stress layer proximate the top portion of gate structure and over the ild layer.
Taiwan Semiconductor Manufacturing Company Limited


05/19/16
20160141393 

Meander resistor


A method includes forming a plurality of fins in a semiconductor substrate using a common patterning process. A conductive layer is formed above the plurality of fins.
Globalfoundries Inc.


05/19/16
20160141392 

Methods of manufacturing finfet semiconductor devices using sacrificial gate patterns and selective oxidization of a fin


A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.. .
Samsung Electronics Co., Ltd.


05/19/16
20160141391 

Method for reducing contact resistance in mos


A method for growing a iii-v semiconductor structure on a singe1-n substrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a singe1-n substrate to a high temperature; (b) exposing the area to a group v precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the singe1-n substrate to a low temperature; (d) exposing the doped region to a group iii precursor in a carrier gas and to a group v precursor in a carrier gas until a nucleation layer of iii-v material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the singe1-n substrate to an intermediate temperature; and (f) exposing the nucleation layer to a group iii precursor in a carrier gas and to a group v precursor in a carrier gas..
Imec Vzw


05/19/16
20160141390 

Method for manufacturing display panel


A method for manufacturing display panel is disclosed, which comprises: (a) providing a substrate, an oxide semiconductor layer disposed on the substrate, and a gate electrode disposed on the substrate and corresponding to the oxide semiconductor layer; (b) forming a metal layer on the oxide semiconductor layer; (c) forming a photoresist on the metal layer, and etching the metal layer to form a source electrode and a drain electrode; (d) heating the photoresist and the photoresist covers at least partial of side walls of the source electrode and the drain electrode; (e) applying an alkaline solution on the substrate; and (f) removing the photoresist to expose the source electrode and the drain electrode.. .
Innolux Corporation


05/19/16
20160141388 

Methods of manufacturing semiconductor devices using masks having varying widths


In a method, a dummy gate layer structure and a mask layer are formed on a substrate. The mask layer is patterned to form masks.
Samsung Electronics Co., Ltd.


05/19/16
20160141386 

Method for forming semiconductor device with low sealing loss


A method for forming a semiconductor device, includes steps of: providing a substrate; forming a first seal layer over the substrate; forming a second seal layer atop the first seal layer; forming a patterned photoresist layer on the second seal layer; implanting a dopant into the substrate by using the patterned photoresist layer as a mask; executing a first removing process to remove the patterned photoresist layer, wherein the first seal layer has a higher etch rate than that of the second seal layer in the first removing process; and removing the second seal layer after removing the patterned photoresist layer.. .
United Microelectronics Corporation


05/19/16
20160141385 

Method of manufacturing nitride semiconductor device


A method of manufacturing a nitride semiconductor device includes: forming a transistor having a gate electrode schottky-joined to a nitride semiconductor layer; performing high-temperature annealing at a temperature of 200 to 360° c. For 8 to 240 hours on the transistor; and after the high-temperature annealing, performing rf burn-in by applying radiofrequency power to the transistor at a channel temperature of 180 to 360° c..
Mitsubishi Electric Corporation


05/19/16
20160141384 

Mask-less dual silicide process


A method of forming a semiconductor device is provided. The method includes forming a mask layer, such as an oxidized layer, over first source/drain regions in a first device region.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/19/16
20160141383 

Interlayer dielectric layer with two tensile dielectric layers


A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first tensile dielectric layer on the substrate; a metal gate in the first tensile dielectric layer; a second tensile dielectric layer on the first tensile dielectric layer; and a contact plug in the first tensile dielectric layer and the second tensile dielectric layer.
United Microelectronics Corp.


05/19/16
20160141381 

Semiconductor devices and methods for fabricating the same


semiconductor devices and methods for fabricating the same are provided. The semiconductor devices include a fin active pattern formed to project from a substrate, a gate electrode formed to cross the fin active pattern on the substrate, a gate spacer formed on a side wall of the gate electrode and having a low dielectric constant and an elevated source/drain formed on both sides of the gate electrode on the fin active pattern.
Samsung Electronics Co., Ltd.


05/19/16
20160141380 

Method for manufacturing a semiconductor device, and semiconductor device


A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a main surface and a gate electrode which is within a trench between neighboring semiconductor mesas. The gate electrode is electrically insulated from the neighboring semiconductor mesas by respective dielectric layers.
Infineon Technologies Austria Ag


05/19/16
20160141379 

Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods


Devices and methods for forming semiconductor devices with middle of line capacitance reduction in self-aligned contact process flow and fabrication are provided. One method includes, for instance: obtaining a wafer with at least one source, drain, and gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; and forming at least one first and second small contact over the first and second contact regions.
Globalfoundries Inc.


05/19/16
20160141378 

Thin film transistor substrate


A thin film transistor includes a gate electrode, a semiconductor layer, and source and drain electrodes contacting the semiconductor layer. The source and drain electrodes include a metal oxide having a crystal size in a c-axis direction lc(002) that ranges from 67 Å or more to 144 Å or less..
Samsung Display Co., Ltd.


05/19/16
20160141377 

Low temperature spacer for advanced semiconductor devices


Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (bn) spacer on a gate stack, such as a gate stack of a planar fet or finfet. The boron nitride spacer is fabricated using atomic layer deposition (ald) and/or plasma enhanced atomic layer deposition (peald) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (si), silicon germanium (sige), germanium (ge), and/or iii-v compounds.
International Business Machines Corporation


05/19/16
20160141376 

Vertical semiconductor device and manufacturing therefor


A vertical semiconductor device includes a semiconductor body having a front side, a backside arranged opposite to the front side and a lateral edge delimiting the semiconductor body in a horizontal direction perpendicular to the front side, a gate metallization arranged on the front side and extending at least close to the lateral edge; a contact metallization arranged on the front side and between the lateral edge and the gate metallization, and a backside metallization arranged on the backside and in electric contact with the contact metallization. The gate metallization is arranged around at least two sides of the contact metallization when viewed from above..
Infineon Technologies Austria Ag


05/19/16
20160141374 

Aspect ratio trapping and lattice engineering for iii/v semiconductors


A method of forming a semiconductor structure. The method may include; forming a hardmask on a strained semiconductor, the strained semiconductor is on a substrate; relaxing edges of the strained semiconductor by forming first trenches through the hardmask and through the strained semiconductor; forming barrier layers in the first trenches; forming a second trench between adjacent barrier layers; and growing a second semiconductor layer on the strained semiconductor having relaxed edges..
International Business Machines Corporation


05/19/16
20160141373 

Semiconductor devices including field effect transistors and methods of forming the same


A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern.

05/19/16
20160141372 

Ga2o3 semiconductor element


Provided is a ga2o3-based semiconductor element having less leak current and a large on/off ratio. In one embodiment, provided is a ga2o3-based misfet having a β-ga2o3 single crystal layer formed on a high-resistance β-ga2o3 substrate, a source electrode and drain electrode formed on the β-ga2o3 single crystal layer, a gate electrode formed between the source electrode and drain electrode on the β-ga2o3 single crystal layer, and an insulating film that has an oxide insulator as the primary component and that covers the surface of the β-ga2o3 single crystal layer at the region between the drain electrode and the gate electrode and the region between the gate electrode and the source electrode..
National Institute Of Information And Communicatio Ns Technology


05/19/16
20160141371 

Silicon carbide semiconductor device and manufacturing the same


In order to provide a high-performance and reliable silicon carbide semiconductor device, in a silicon carbide semiconductor device including an n-type sic epitaxial substrate, a p-type body layer, a p-type body layer potential fixing region and a nitrogen-introduced n-type first source region formed in the p-type body layer, an n-type second source region to which phosphorus which has a solid-solubility limit higher than that of nitrogen and is easily diffused is introduced is formed inside the nitrogen-introduced n-type first source region so as to be separated from both of the p-type body layer and the p-type body layer potential fixing region.. .
Hitachi, Ltd.


05/19/16
20160141370 

High aspect ratio trapping semiconductor with uniform height and isolated from bulk substrate


A semiconductor structure having an isolated device region separated from channel defects formed during aspect ratio trapping (art). The structure includes: an isolated device region of a semiconductor channel separated from a defect region of a semiconductor channel by a barrier layer, the isolated device region is free of formation defects, the defect region includes formation defects; a substrate directly below the defect region of the semiconductor channel; and a dielectric layer adjacent to the defect region, below the barrier layer, and above the substrate..
International Business Machines Corporation


05/19/16
20160141369 

Semiconductor and fabricating the same


Provided is a semiconductor and method of manufacturing the same, and a method of forming even doping concentration of respective semiconductor device when manufacturing multiple semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable in example by using ion injected blocking pattern.
Magnachip Semiconductor, Ltd.


05/19/16
20160141368 

Tall strained high percentage silicon-germanium fins


The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming one or more tall strained silicon germanium (sige) fins on a semiconductor on insulator (soi) substrate. The fins have a germanium (ge) concentration which may differ from the ge concentration within the top layer of the soi substrate.
Globalfoundries Inc.


05/19/16
20160141367 

Semiconductor devices including channel dopant layer


A semiconductor device includes a semiconductor substrate including a well dopant layer having a first conductivity type, a gate electrode on the well dopant layer, a channel dopant layer in the well dopant layer and spaced apart from a top surface of the semiconductor substrate, a channel region between the gate electrode and the channel dopant layer, and source/drain regions in the well dopant layer at both sides of the gate electrode. The channel dopant layer and the channel region have the first conductivity type.
Samsung Electronics Co., Ltd.


05/19/16
20160141366 

Field effect transistors and methods of forming same


semiconductor devices and methods of forming the same are provided. A first gate stack is formed over a substrate, wherein the first gate stack comprises a first ferroelectric layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/19/16
20160141365 

Gate-all-around fin device


A gate-all around fin double diffused metal oxide semiconductor (dmos) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate.
International Business Machines Corporation


05/19/16
20160141364 

Semiconductor device and manufacturing semiconductor device


Provided is a semiconductor device comprising: a first conductivity type base layer having a mos gate structure formed on its front surface side; a second conductivity type first collector layer formed on a rear surface side of the base layer; a second conductivity type second collector layer formed on a rear surface side of the first collector layer with a material the same with that of the base layer, the second collector layer formed to be thinner than the first collector layer and having a higher impurity concentration than that of the first collector layer; a collector electrode formed on a rear surface side of the second collector layer; and a second conductivity type separation layer surrounding the mos gate structure on a front surface side of the base layer and formed from a front surface of the base layer to a front surface of the first collector layer.. .
Fuji Electric Co., Ltd.


05/19/16
20160141361 

Nanowire mosfet with support structures for source and drain


Transistor devices and methods for forming transistor devices are provided. A transistor device includes a semiconductor substrate and a device layer.
Taiwan Semiconductor Manufacturing Company Limited


05/19/16
20160141360 

Iii-v semiconductor devices with selective oxidation


Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer..
International Business Machines Corporation


05/19/16
20160141359 

Semiconductor structure with silicon oxide layer having a top surface in the shape of continuous hills and fabricating the same


A semiconductor structure is provided. The semiconductor structure includes a substrate, a silicon oxide layer disposed on the substrate, and at least part of a gate electrode covering the silicon oxide layer.
United Microelectronics Corp.


05/19/16
20160141358 

Apparatus and methods for transceiver interface overvoltage clamping


Apparatus and methods for transceiver interface overvoltage clamping are provided. In certain configurations, an interface device includes a first p-type well region and a second p-type well region in an n-type isolation structure.
Analog Devices, Inc.


05/19/16
20160141357 

Semiconductor device and method


A semiconductor device and a method of making the same. The device includes a semiconductor substrate including a body region having a first conductivity type.
Nxp B.v.


05/19/16
20160141356 

Semiconductor device


A semiconductor device includes: a first conductivity type semiconductor substrate; and a plurality of second conductivity type semiconductor regions, the respective second conductivity type semiconductor regions being embedded in a plurality of stripe shaped trenches formed in the semiconductor substrate so that the respective second conductivity type semiconductor regions are extended in the row direction or the column direction in parallel with a first principal surface of the semiconductor substrate and are spaced in a fixed gap mutually. The semiconductor substrate and the plurality of the semiconductor regions are depleted by a depletion layer extended in the direction in parallel to the first principal surface from a plurality of pn junction interfaces, and the respective pn junction interfaces are formed between the semiconductor substrate and the plurality of the semiconductor regions..
Rohm Co., Ltd.


05/19/16
20160141355 

Active device and semiconductor device with the same


A semiconductor device is provided, comprising a substrate; a first well having a first conductive type and extending down from a surface of the substrate; a diffusion region doped with impurity of the first conductive type and extending down from a surface of the first well; and a plurality of active devices formed within the diffusion region, and the active devices arranged separately from each other. The active devices are electrically isolated from each other by the diffusion region.
Macronix International Co., Ltd.


05/19/16
20160141354 

Patterned back-barrier for iii-nitride semiconductor devices


A compound semiconductor device includes a iii-nitride buffer and a iii-nitride barrier on the iii-nitride buffer. The iii-nitride barrier has a different band gap than the iii-nitride buffer so that a two-dimensional charge carrier gas channel arises along an interface between the iii-nitride buffer and the iii-nitride barrier.
Infineon Technologies Austria Ag


05/19/16
20160141349 

Organic light-emitting diode display having high aperture ratio and manufacturing the same


An organic light-emitting diode display can include a substrate in which an emission area and a non-emission area are defined; a first transparent conductive layer, a light shielding layer, a buffer layer and a semiconductor layer sequentially laminated on the non-emission area; a gate electrode superposed on the center region of the semiconductor layer, having a gate insulating layer interposed therebetween; a drain electrode coming into contact with one side of the semiconductor layer, having an interlevel insulating layer covering the gate electrode interposed therebetween, and formed of a second transparent conductive layer and a metal layer laminated thereon; a first storage capacitor electrode disposed under the interlevel insulating layer in the emission area and formed of the first transparent conductive layer; and a second storage capacitor electrode superposed on the first storage capacitor electrode, having the interlevel insulating layer interposed therebetween, and formed of the second transparent conductive layer.. .
Lg Display Co., Ltd.


05/19/16
20160141347 

Organic light emitting display device


Disclosed herein is an oled (organic light emitting display) device. A switching thin-film transistor configured to be an oxide semiconductor thin-film transistor is disposed in a first pixel.
Lg Display Co., Ltd.


05/19/16
20160141335 

Diamond like carbon (dlc) in a semiconductor stack as a selector for non-volatile memory application


Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching.
Intermolecular, Inc.


05/19/16
20160141332 

Emissive device including first and second adjacent pixels sharing the same semiconductor light-emitting stack


The emissive device includes first and second adjacent pixels (1a, 1b) sharing a common semiconductor light-emitting stack (2) and each defining an area (4a, 4b) of photon emission. The first and second pixels (1a, 1b) are configured in such a way that supplying current to the first pixel (1a) causes photons to be emitted, by the light-emitting stack (2), only in the emission area (4a) of said first pixel (1a)..
Alcatel Lucent


05/19/16
20160141331 

Light-emitting diode


A light-emitting diode is provided. The light-emitting diode comprises: a first light-emitting structure, comprising: a first area; a second area; a first isolation path having an electrode isolation layer between the first area and the second area; an electrode contact layer covering the first area; and an electrical connecting structure covering the second area; wherein each of the first area and the second area sequentially comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, and the electrode contact layer covers a sidewall of the first area..
Epistar Corporation


05/19/16
20160141330 

Method for semiconductor selective etching and bsi image sensor


A method of selectively etching a semiconductor device and manufacturing a bsi image sensor device includes etching a doped silicon substrate with an hna solution for a predetermined time duration to obtain an etching solution having a concentration c1 of nitrite ions, etching the semiconductor device using the obtained etching solution. Etching the semiconductor device requires an initial concentration c0 of nitride ions that is lower than c1.
Semiconductor Manufacturing International (shanghai) Corporation


05/19/16
20160141324 

Semiconductor image sensor module, manufacturing the same as well as camera and manufacturing the same


A semiconductor image sensor module 1 at least includes a semiconductor image sensor chip 2 having a transistor forming region on a first main surface of a semiconductor substrate and having a photoelectric conversion region with a light incident surface formed on a second main surface on the side opposite to the first main surface and an image signal processing chip 3 for processing image signals formed in the semiconductor image sensor chip 2, wherein a plurality of bump electrodes 15a are formed on a first main surface, a plurality of bump electrodes 15b are formed on the image signal processing chip 3, both the chips 2 and 3 are formed to be laminated through heat dissipating means 4 and the plurality of bump electrodes 15a of the semiconductor image sensor chip 2 and the plurality of bump electrodes 15b on the image signal processing chip 3 are electrically connected.. .
Sony Corporation


05/19/16
20160141320 

Wafer-level encapsulated semiconductor device, and fabricating same


A method of encapsulating semiconductor devices formed on a device wafer includes forming an assembly including a carrier wafer and a plurality of dams thereon. After the step of forming, the method attaches the plurality of dams to the device wafer to form a respective plurality of encapsulated semiconductor devices..

05/19/16
20160141316 

Low full-well capacity image sensor with high sensitivity


Image sensor pixels having low full-well capacity and high sensitivity for applications such as dis, qdis, single/multi bit qis. Some embodiments provide an image sensor pixel architecture, comprises a transfer gate, a floating diffusion region both formed on a first surface of a semiconductor substrate and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially or entirely beneath the transfer gate.
Dartmouth College


05/19/16
20160141308 

Display device


By applying an ac pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an ac pulse.
Semiconductor Energy Laboratory Co., Ltd.


05/19/16
20160141303 

Semiconductor memory device


According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit..
Kabushiki Kaisha Toshiba


05/19/16
20160141302 

Semiconductor device and manufacturing the same


A semiconductor device includes stacked groups each including interlayer insulating patterns and conductive patterns and stacked in at least two tiers, wherein the insulating patterns and the conductive patterns are alternately stacked over a substrate and separated by slits, and a support body including holes and formed between the stacked groups.. .
Sk Hynix Inc.


05/19/16
20160141298 

Sti recess method to embed nvm memory in hkmg replacement gate technology


The present disclosure relates to a structure and method for reducing contact over-etching and high contact resistance (rc) on an embedded flash memory hkmg integrated circuit. In one embodiment, an sti region underlying a memory contact pad region is recessed to make the sti surface substantially co-planar with the rest of the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


05/19/16
20160141297 

Semiconductor device and manufacturing the same


In one embodiment, a semiconductor device includes a substrate, and first to fourth interconnects provided on the substrate to be adjacent to one another. The device includes a first pad portion connected with the first or second interconnect, and a second pad portion adjacent to the first pad portion in a first direction.
Kabushiki Kaisha Toshiba


05/19/16
20160141294 

Three-dimensional memory structure with multi-component contact via structure and making thereof


A contact via structure can include a ruthenium portion formed by selective deposition of ruthenium on a semiconductor surface at the bottom of a contact trench. The ruthenium-containing portion can reduce contact resistance at the interface with an underlying doped semiconductor region.
Sandisk Technologies Inc.


05/19/16
20160141293 

Semiconductor memory device and manufacturing same


According to one embodiment, a semiconductor memory device includes a memory cell; and a peripheral transistor. The memory cell includes a first channel, a first insulating film provided on the first channel, a charge storage film provided on the first insulating film, a second insulating film provided on the charge storage film, a first semiconductor film provided on the second insulating film, and a first electrode film provided on the first semiconductor film and containing a metal.
Kabushiki Kaisha Toshiba


05/19/16
20160141292 

Cmos gate stack structures and processes


A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface..
Mie Fujitsu Semiconductor Limited


05/19/16
20160141289 

Semiconductor device and manufacturing same


To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate.
Renesas Electronics Corporation


05/19/16
20160141286 

Carrier for an optoelectronic semiconductor chip and optoelectronic component


A carrier (1) for an optoelectronic semiconductor chip comprising: (2) base body (10), which comprises a first main surface (10a) and a second main surface (10b), at least one recess (11), which is introduced into the base body (10) and completely penetrates the base body (10) from the first main surface to the second main surface, and a filler material (12), which is introduced into the at least one recess (11). The base body (10) is formed using silicon of a first conductivity type.
Osram Opto Semiconductors Gmbh


05/19/16
20160141285 

Electrostatic discharge (esd) protection device


An electrostatic discharge (esd) protection device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. In addition, the esd protection device further includes a first doping region formed in a portion of the at least one portion of the semiconductor substrate separating the pair of first well regions, having a second conductivity type opposite to the first conductivity type.
Mediatek Inc.


05/19/16
20160141284 

Semiconductor device


A transistor (2) is provided on a semiconductor substrate (8). A temperature detection diode (4) for monitoring temperature of an upper surface of the semiconductor substrate (8) is provided on the semiconductor substrate (8).
Mitsubishi Electric Corporation


05/19/16
20160141283 

Integrated thinfilm resistor and mim capacitor with a low serial resistance


An electronic device comprising a semiconductor structure having a back end capacitor and a back end thin film resistor and a method of manufacturing the same. The semiconductor structure includes a first dielectric layer, a bottom plate of the capacitor and a thin film resistor body.
Texas Instrumentsdeutschland Gmbh


05/19/16
20160141282 

Method of fabricating multi-substrate semiconductor devices


A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer.
Samsung Electronics Co., Ltd.


05/19/16
20160141281 

Fabrication semiconductor package having embedded semiconductor elements


A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement..
Siliconware Precision Industries Co., Ltd.


05/19/16
20160141280 

Device-embedded image sensor, and wafer-level fabricating same


A device-embedded image sensor includes an image sensor formed in a first semiconductor substrate; a top conductive pad formed on a top surface of the first semiconductor substrate; and a semiconductor device formed in a second semiconductor substrate bonded to a bottom surface of the first semiconductor substrate, the semiconductor device electrically connected to the top conductive pad. A method for fabricating a device-embedded image sensor from a cmos image sensor wafer assembly that includes an image sensor and a conductive pad.
Omnivision Technologies, Inc.


05/19/16
20160141278 

Light emitting device


A light emitting device includes a substrate, a plurality of micro light emitting chips and a plurality of conductive bumps. The substrate has a plurality of pads.
Playnitride Inc.


05/19/16
20160141277 

Arrangement and generating mixed light


The invention relates to an arrangement for generating mixed light, which comprises three semiconductor chips, emitting in the blue spectral range, of three devices. Arranged in the light paths of the individual semiconductor chips are different conversion elements which are configured to convert primary radiation into secondary radiation.
Osram Opto Semiconductors Gmbh


05/19/16
20160141275 

Semiconductor power module using discrete semiconductor components


An electronic power module is disclosed. The module includes a baseplate and a plurality of internally isolated discrete electronic devices mounted to the baseplate such that their electrical leads are oriented away from the baseplate.
Littelfuse, Inc.


05/19/16
20160141274 

Novel semiconductor device and structure


An integrated circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a first wire structure constructed to provide power to a portion of the first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and a second wire structure constructed to provide power to a portion of the second transistors, where the second wire structure is isolated from the first wire structure to provide a different power voltage to the portion of the second transistors.. .
Monolithic 3d Inc.


05/19/16
20160141273 

Semiconductor device


This semiconductor device is formed by stacking a plurality of semiconductor chips that each have a plurality of bump electrodes, each of the plurality of semiconductor chips being provided with an identification section formed on a respective side face. Each semiconductor chip has a similar arrangement for its respective plurality of bump electrodes, and each identification section is formed so that the positional relationship with a respective reference bump electrode provided at a specific location among the respective plurality of bump electrodes is the same in each semiconductor chip.
Ps4 Luxco S.a.r.l.


05/19/16
20160141272 

Semiconductor device and manufacturing same


A semiconductor device which is provided with: a wiring substrate which has a first region, and a relay pad and a connection pad that are arranged outside the first region; a first semiconductor chip which has an electrode pad that is formed on one surface, and which is mounted on the first region of the wiring substrate; a first wire that connects the electrode pad and the relay pad with each other; and a second wire that connects the relay pad and the connection pad with each other.. .
Ps4 Luxco S.a.r.l.


05/19/16
20160141271 

Semiconductor packages and methods of fabricating the same


A semiconductor package including a lower package and an upper package provided may be provided. The lower package includes a lower package substrate, a lower semiconductor chip mounted thereon, and a lower mold layer provided on the lower package substrate.

05/19/16
20160141270 

Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods


Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a stack of semiconductor dies and a thermally conductive casing at least partially enclosing the stack of semiconductor dies within an enclosure.
Micron Technology, Inc.


05/19/16
20160141269 

Multi-chip semiconductor device


A multi-chip semiconductor device includes a plate-shaped first semiconductor chip having a first connection portion in which a first semiconductor chip electrode is formed on a first main surface of the first semiconductor chip or on a first side surface vertical to the first main surface, and a plate-shaped second semiconductor chip having a second connection portion in which a second semiconductor chip electrode is formed on a second side surface vertical to a second main surface of the second semiconductor chip. Each of the first and second connection portions includes at least an inclined surface that is inclined with respect to each of the first and second main surfaces.
Olympus Corporation


05/19/16
20160141268 

Method for manufacturing semiconductor apparatus and semiconductor apparatus


A method for manufacturing a semiconductor-apparatus, including an encapsulating step of a device mounting surface of a substrate having semiconductor-devices mounted thereon with a base-attached encapsulant having a base and a thermosetting resin layer formed on one surface of the base, the semiconductor-devices being mounted by flip-chip bonding, the encapsulating step including a unifying stage of the substrate having the semiconductor-devices mounted thereon and the base-attached encapsulant under a reduced pressure condition with a vacuum of 10 kpa or less and a pressing stage of the unified substrate with a pressure of 0.2 mpa or more. A method for manufacturing a semiconductor-apparatus that can inhibit warping even when a thin substrate with a large area is encapsulated, sufficiently perform underfilling of semiconductor-devices mounted by flip-chip bonding, and provide a semiconductor-apparatus excellent in encapsulating performance such as heat and moisture resistance reliabilities without void and non-filling portion of the encapsulating layer..
Shin-etsu Chemical Co., Ltd.


05/19/16
20160141267 

Semiconductor device, manufacturing semiconductor device, and electronic apparatus


There is provided a semiconductor device, including a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a bonding electrode formed on a surface of the interlayer insulating layer, and a metal film which covers an entire surface of a bonding surface including the interlayer insulating layer and the bonding electrode.. .
Sony Corporation


05/19/16
20160141266 

Method of bonding with silver paste


A method for bonding with a silver paste includes coating a semiconductor device or a substrate with the silver paste. The silver paste contains a plurality of silver particles and a plurality of bismuth particles.
Hyundai Motor Company


05/19/16
20160141263 

Semiconductor device including built-in crack-arresting film structure


According to at least one embodiment of the present invention, a wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer.
International Business Machines Corporation


05/19/16
20160141261 

Ball amount process in the manufacturing of integrated circuit


An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a post-passivation interconnect (ppi) over the polymer layer. The ppi is electrically connected to the metal pad.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/19/16
20160141260 

Pre-package and methods of manufacturing semiconductor package and electronic device using the same


Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate..

05/19/16
20160141256 

Method for manufacturing a semiconductor device, and semiconductor device


According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.. .
Infineon Technologies Ag


05/19/16
20160141255 

Semiconductor package and fabrication method thereof


A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.. .
Siliconware Precision Industries Co., Ltd.


05/19/16
20160141254 

Chip package and forming the same


An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.. .
Xintec Inc.


05/19/16
20160141253 

Display substrate and manufacturing method thereof as well as display device


The embodiments of the present invention provide a display substrate and a manufacturing method thereof, as well as a display device including the display substrate. The display substrate may include a base substrate and a thin film transistor arranged on the base substrate, the thin film transistor having a gate, a gate insulating layer, an oxide semiconductor active layer as well as a source electrode and a drain electrode arranged on the base substrate sequentially; the display substrate may further include an ultraviolet blocking layer, the ultraviolet blocking layer having a first portion arranged between the base substrate and the oxide semiconductor active layer.
Boe Technology Group Co., Ltd.


05/19/16
20160141252 

Methods of forming alignment marks and overlay marks on integrated circuit products employing finfet devices and the resulting alignment/overlay mark


A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to define an alignment/overlay mark trench. An alignment/overlay mark includes at least one insulating material positioned within the alignment/overlay mark trench.
Globalfoundries Inc.


05/19/16
20160141251 

Wafer with die map


Embodiments of the invention provide a semiconductor wafer with information for detecting a die attach pick error on the semiconductor wafer. The semiconductor wafer has a plurality of electrical chips.
Texas Instruments Incorporated


05/19/16
20160141250 

Barrier structure


A semiconductor device includes a dielectric material and an interconnect structure. The semiconductor device further includes a barrier layer positioned between the dielectric material and the interconnect structure.
Qualcomm Incorporated


05/19/16
20160141249 

Semiconductor devices


semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure.
Samsung Electronics Co., Ltd.


05/19/16
20160141248 

Chip card module arrangement, chip card arrangement and producing a chip card arrangement


A chip card module arrangement may include a first surface and a second surface, which are opposite from one another, and a chip receptacle for one or more semiconductor chips on the surfaces. The chip card module arrangement may further include a connecting material receiving area on one of the two surfaces, the connecting material receiving area only taking up a portion of the surface..
Infineon Technologies Ag


05/19/16
20160141247 

Semiconductor device and manufacturing method thereof


A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal.
Kabushiki Kaisha Toshiba


05/19/16
20160141246 

Semiconductor device


A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of international union of pure and applied chemistry (iupac) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench..

05/19/16
20160141243 

Semiconductor device and fabricating the same


A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed on the first region and the second region, respectively, a first contact formed on the first transistor, and a second contact formed on the second transistor.
Samsung Electronics Co., Ltd.


05/19/16
20160141241 

Semiconductor device and its manufacturing method


The reliability of a copper wire is improved without inhibiting the wiring resistance of the copper wire. For example, another metallic element segregates in the boundary region between a copper film cuf1 and a copper film cuf2, and at the upper side face part of a wiring gutter leading to the boundary region.
Renesas Electronics Corporation


05/19/16
20160141240 

Field-effect transistor, manufacturing the same, and radio-frequency device


There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.. .
Sony Corporation


05/19/16
20160141238 

Semiconductor device and forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp)


A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant.
Stats Chippac, Ltd.


05/19/16
20160141232 

Integrated circuit package


An integrated circuit package comprising a semiconductor die, a lead frame lying in a first plane, at least one conductive pillar structure extending outwardly from the first plane, wherein the lead frame and the at least one conductive pillar structure are formed of sintered conductive material, encapsulation material which encapsulates the semiconductor die, the lead frame and the at least one conductive pillar structure, a conductive layer on an upper face of the package, the conductive layer conductively connecting to the at least one conductive pillar. Methods of manufacturing are also disclosed..
Cambridge Silicon Radio Limited


05/19/16
20160141231 

Power module and fabrication the same


A power module includes: an insulating layer; a leadframe disposed on the insulating layer; a semiconductor chip disposed on the leadframe; and a mold resin formed so as to cover the semiconductor chip and at least a part of the metal layer, wherein a groove into which a part of the insulating layer is inserted is formed on a surface of the leadframe facing the insulating layer. Accordingly, there can be provided the power module with improved reliability so that the insulating layer and the leadframe may be hardly deviated from each other even if external force is applied thereon; and a fabrication method for such a power module..
Rohm Co., Ltd.


05/19/16
20160141230 

Semiconductor device and lead frame having vertical connection bars


A semiconductor device includes a lead frame having a die support area and a plurality of inner and outer row leads surrounding the die support area, and a semiconductor die mounted on the die support area and electrically connected to the leads with bond wires. A molding material encapsulates the semiconductor die, the bond wires, and the leads, and defines a package body.

05/19/16
20160141229 

Semiconductor package with semiconductor die directly attached to lead frame and method


In one embodiment, a semiconductor package includes a semiconductor die having conductive pads. A lead frame is directly connected to the conductive pads using an electrochemically formed layer or a conductive adhesive layer thereby facilitating an electrical connection between the conductive pads of the semiconductor die and the lead frame without using separate wire bonds or conductive bumps..
Amkor Technology, Inc.


05/19/16
20160141228 

Device connection through a buried oxide layer in a silicon on insulator wafer


An approach to forming a semiconductor structure for a semiconductor device with connections through a buried oxide layer in a silicon on insulator wafer. A buried oxide layer is formed on a semiconductor substrate and at least one semiconductor device is formed on the buried oxide layer.
International Business Machines Corporation


05/19/16
20160141226 

Device connection through a buried oxide layer in a silicon on insulator wafer


An approach to forming a semiconductor structure for a semiconductor device with connections through a buried oxide layer in a silicon on insulator wafer. A buried oxide layer is formed on a semiconductor substrate and at least one semiconductor device is formed on the buried oxide layer.
International Business Machines Corporation


05/19/16
20160141224 

Power module and fabrication the same


A power module includes: an insulating layer; a leadframe (metal layer) disposed on the insulating layer; a semiconductor chip disposed on the leadframe; and a mold resin formed so as to cover the semiconductor chip, at least a part of the metal layer, and at least a part of the insulating layer, wherein the insulating layer includes a relatively-soft insulating layer disposed at a side of the leadframe and a relatively-hard insulating layer disposed at an opposite side of the leadframes. Accordingly, there can be provided the power module with improved cooling capability and improved reliability, and the fabrication method for such a power module..
Rohm Co., Ltd.


05/19/16
20160141222 

Electronic device and manufacturing the same


In manufacturing an electronic device in which a semiconductor chip including an element layer formed on a front surface of a substrate and a heat sink to perform heat radiation of the semiconductor chip are connected via a heat spreader, a first heat spreader is formed on a rear surface of the semiconductor chip using a first carbon nanotube, a second heat spreader is formed on the heat sink using a second carbon nanotube, and the first heat spreader and the second heat spreader are caused to adhere to each other. With this configuration, a highly reliable electronic device that has very low heat resistance and achieves efficient heat radiation with a relatively simple configuration is fabricated..
Fujitsu Limited


05/19/16
20160141221 

Electronic device having heat conducting member


An electronic device includes a semiconductor module, a wiring substrate, a case member and a heat conducting member. The heat conducting member thermally connects predetermined portions of wiring patterns and a heat conducting pattern of the wiring substrate to a predetermined heat conduction region of a surface of the case member opposing to the wiring substrate.
Denso Corporation


05/19/16
20160141220 

Hetero-bipolar transistor and producing the same


A semiconductor device provided with a substrate made of material except for semiconductors and having thermal conductivity greater than that of the semiconductor material. The semiconductor device provides, on the support, a metal layer, a primary mesa, and electrodes formed on the primary mesa.
Sumitomo Electric Industries, Ltd.


05/19/16
20160141218 

Circuit module and manufacturing method thereof


There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip.
International Business Machines Corporation


05/19/16
20160141215 

Method for manufacturing semiconductor device


The reliability of multipoint contact by a contact pin with an external terminal is improved while achieving an improvement in easiness of manufacture of the contact pin. The contact pin includes first and second contact pins.
Renesas Electronics Corporation


05/19/16
20160141214 

Method for manufacturing semiconductor module and intermediate assembly unit of the same


A method for manufacturing a semiconductor module includes the step of soldering two or more semiconductor elements having substrate materials and heights different from each other to a metal foil disposed at one side of an insulating substrate; connecting a plurality of wiring members, not interconnecting the semiconductor elements, to front face electrodes of the semiconductor elements through solder so that heights from a surface of the insulating substrate to top faces of the wiring members become same level with each other; inspecting a leakage current while applying electricity on each one of semiconductor elements individually through the wiring members; and connecting the top faces of the wiring members with a bus bar.. .
Fuji Electric Co., Ltd.


05/19/16
20160141213 

Automated optical inspection of unit specific patterning


A method of automated optical inspection (aoi) for a plurality of unique semiconductor packages can comprise providing a plurality of semiconductor die formed as a reconstituted wafer. A plurality of unit specific patterns can be formed by forming a unit specific pattern over each of the plurality of semiconductor die, wherein each of the unit specific patterns is customized to fit its respective semiconductor die.
Deca Technologies Inc.


05/19/16
20160141211 

Semiconductor device including power and logic devices and related fabrication methods


semiconductor device structures and related fabrication methods are provided. An exemplary fabrication method involves forming a layer of gate electrode material overlying a semiconductor substrate, forming a layer of masking material overlying the gate electrode material, and patterning the layer of masking material to define a channel region within a well region in the semiconductor substrate that underlies the gate electrode material.

05/19/16
20160141210 

Wafer dicing using femtosecond-based laser and plasma etch


Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits.

05/19/16
20160141208 

Method for processing a semiconductor substrate and a processing a semiconductor wafer


According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies.. .
Infineon Technologies Ag


05/19/16
20160141207 

Method of making semiconductor structure having contact plug


The present invention provides a method of forming a semiconductor structure including a substrate, a transistor, a first ild layer, a second ild layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region.
United Microelectronics Corp.


05/19/16
20160141205 

Finfets with different fin height and epi height setting


An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/19/16
20160141204 

Trench having thick dielectric selectively on bottom portion


A method of fabricating a semiconductor device includes etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from the top surface into the semiconductor substrate. A dielectric liner of a first dielectric material is formed on the bottom surface and sidewalls of the trench to line the trench.
Texas Instruments Incorporated


05/19/16
20160141202 

Air gap formation in interconnection structure by implantation process


Methods for forming air gaps in an interconnection structure with desired materials formed on different locations of the interconnection structure using an ion implantation process to define an etching boundary followed by an etching process for semiconductor devices are provided. In one embodiment, a method for forming air gaps in an interconnection structure on a substrate, the method includes implanting ions in a first region of an insulating material disposed on a substrate, leaving a second region without implanted ions, the second region having a first surface interfaced with the first region and a second surface interfaced with the substrate, and performing an etching process to selectively etch the second region away from the substrate, forming an air gap between the first region and the substrate..
Applied Materials, Inc.


05/19/16
20160141188 

Internal plasma grid for semiconductor fabrication


The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers.
Lam Research Corporation


05/19/16
20160141186 

Decapsulation method and decapsulation system for plastic molded ic package


A plastic mold decapsulation method and decapsulation system is provided for decapsulating a semiconductor device molded by plastic. A plastic mold decapsulation method and decapsulation system for decapsulating a plastic molded semiconductor device includes decapsulating the molded semiconductor device using a solution having dissolved metal in a liquid including acid.
Nippon Scientific Co., Ltd.


05/19/16
20160141182 

Slurry compositions and methods of fabricating semiconductor devices using the same


Provided are slurry compositions for polishing a germanium-containing layer and methods of fabricating a semiconductor device using the same. The slurry composition may include a polishing particle, an oxidizing agent, a polishing accelerator, and a selectivity control agent.
Samsung Electronics Co., Ltd.


05/19/16
20160141181 

Semiconductor device, fabricating the same, and apparatus used in fabrication thereof


A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided..

05/19/16
20160141180 

Sonos stack with split nitride memory layer


A semiconductor device includes a polysilicon substrate, a first oxide layer formed on the polysilicon substrate, an oxygen-rich nitride layer formed on the first oxide layer, a second oxide layer formed on the oxygen-rich nitride layer, and an oxygen-poor nitride layer formed on the second oxide layer.. .
Cypress Semiconductor Corporation


05/19/16
20160141179 

Selective growth for high-aspect ration metal fill


An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/19/16
20160141176 

Process for forming silicon-filled openings with a reduced occurrence of voids


In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon.
Asm Ip Holding B.v.


05/19/16
20160141173 

Method of manufacturing semiconductor device, substrate processing apparatus, gas supply system, and recording medium


A method of manufacturing a semiconductor device includes alternately performing supplying a first process gas containing silicon and a halogen element to a substrate having a surface on which monocrystalline silicon and an insulation film are exposed and supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing silicon to the substrate, whereby a first silicon film is homo-epitaxially grown on the monocrystalline silicon and a second silicon film differing in crystal structure from the first silicon film is grown on the insulation film.. .
Hitachi Kokusai Electric Inc.


05/19/16
20160141171 

Photoresist pattern trimming methods


Provided are methods of trimming photoresist patterns. The methods involve coating a photoresist trimming composition over a photoresist pattern, wherein the trimming composition includes a matrix polymer, a thermal acid generator and a solvent, the trimming composition being free of cross-linking agents.
Rohm And Haas Electronic Materials Llc


05/19/16
20160141169 

Substrate backside texturing


Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized.
Tokyo Electron Limited


05/19/16
20160141144 

Method and electron beam lithography


Disclosed is an apparatus in a semiconductor lithography system. The apparatus comprises a multiplexer and a plurality of imaging elements.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/19/16
20160141043 

Semiconductor device


A semiconductor device is provided. The semiconductor device may include a memory block including memory strings connected to respective bit lines coupled to a substrate and commonly connected to a common source line coupled to the substrate.
Sk Hynix Inc.


05/19/16
20160141039 

Non-volatile semiconductor memory device


A semiconductor memory device, which restrains a breakdown of a low-voltage transistor constructing a bit line selecting circuit, is provided. An nand string unit and transistors (blse, blso, biase, biaso) that construct bit line selecting circuit are formed in a p-well.
Winbond Electronics Corp.


05/19/16
20160141038 

Semiconductor device


A semiconductor device includes memory blocks including a plurality of memory cells, wherein the plurality of memory cells are divided into a plurality of pages, and an operation circuit suitable for outputting operating voltages to local lines of the memory blocks to perform a program loop, an erase loop and a read operation on the plurality of memory cells, wherein the operation circuit is suitable for applying a dummy pulse having a positive potential to the local lines after the program loop or the erase loop is completed.. .
Sk Hynix Inc.


05/19/16
20160141037 

Semiconductor memory system and operating the same


A method of operating a semiconductor memory system includes: programming lsb data into a memory cell of a selected word line included in a memory block; storing msb data to be programmed into the memory cell of the selected word line, from a controller into a page buffer; reading the programmed lsb data from the memory cell of the selected word line; performing an ecc operation on the read lsb data when a difference between a reference amount and an amount of bit line current, which flows through bit lines included in the memory block, does not fall in a predetermined range from a first current amount to a second current amount; and programming the msb data stored in the page buffer into the memory cell of the selected word line based on the ecc-corrected lsb data.. .
Sk Hynix Inc.


05/19/16
20160141035 

Semiconductor memory device and operating the same


A semiconductor memory device and a method of operating the same are provided. The device may include a memory cell array including a plurality of memory blocks and a peripheral circuit configured for selecting one of the plurality of memory blocks and performing a program operation on selected memory cells of the selected memory block when the program operation is performed.
Sk Hynix Inc.


05/19/16
20160141030 

Semiconductor memory device


A semiconductor memory device has at least one memory cell using a resistance variable element, and a control circuit which controls writing to and reading from the memory cell. Operations by the control circuit include a first writing operation, a second writing operation, and a rewriting operation.
Renesas Electronics Corporation


05/19/16
20160141014 

Semiconductor integrated circuit


A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a ddr (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.. .
Sk Hynix Inc.


05/19/16
20160141011 

Semiconductor device and operating method thereof


Provided is a semiconductor device and an operating method thereof. The operating method of the semiconductor device includes performing an erase operation on a memory block including bottom dummy cells, a plurality of memory cells, top dummy cells and selection transistors arranged in a vertical direction with respect to a pipe gate, increasing threshold voltages of the top and bottom dummy cells at substantially a same time by applying a first soft program voltage to a bottom dummy word line coupled to the bottom dummy cells and a second soft program voltage greater than the first soft program voltage to the top dummy word line coupled to the top dummy cells, verifying the top and bottom dummy cells, and repeatedly performing the erase operation and increasing the threshold voltages by gradually increasing the first and second soft program voltages until the verifying of the top and bottom dummy cells passes..
Sk Hynix Inc.


05/19/16
20160141010 

Semiconductor memory apparatus and system including the same


A semiconductor memory apparatus includes a dbi calculation block, an inversion latch block, an inverted data selective output block, and a pipe latch block. The dbi calculation block performs a dbi calculation and outputs a dbi result signal based on a result of the dbi calculation.
Sk Hynix Inc.


05/19/16
20160141009 

Semiconductor apparatus and operating method thereof


A semiconductor apparatus including a register input selection block configured to serially receive input data and output the input data in parallel as first and second data sets, or receive register selection output signals and output the register selection output signals as the first and second data sets, in response to a shift control signal and a capture control signal; a first data register configured to receive and store the first data set and output stored data as first register output signals; a second data register configured to receive and store the first and second data sets and output stored data as second register output signals; a register output selection block configured to output ones of the first and second register output signals as the register selection output signals; and a data output selection block configured to serially output one of the first and second data sets as output data.. .
Sk Hynix Inc.


05/19/16
20160141005 

Semiconductor integrated circuit and driving the same


Provided is a semiconductor integrated circuit including a plurality of memory chips stacked therein, each of the memory chips may include: a pumping enable signal control unit suitable for generating a pumping enable signal in response to a power-up signal or a trigger signal received from a first adjacent memory chip, delaying the pumping enable signal by a given time, and outputting the delayed pumping enable signal to a second adjacent memory chip; and a pumping unit suitable for generating a pumping voltage by performing a pumping operation in response to the pumping enable signal.. .
Sk Hynix Inc.


05/19/16
20160141003 

Semiconductor memory device


According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array disposed on the semiconductor substrate, a capacitor and a control circuit. The memory cell array includes a plurality of memory cells.
Kabushiki Kaisha Toshiba




Semiconductor topics: Semiconductor, Semiconductor Substrate, Semiconductor Device, Semiconductor Material, Electric Conversion, Conductive Layer, Molybdenum, Camera Module, Semiconductor Devices, Semiconductors, Integrated Circuit, Surfactant, Photoelectric Conversion, Electronic Device, Transparent Conductive Oxide

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