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Semiconductor patents



      
           
This page is updated frequently with new Semiconductor-related patent applications. Subscribe to the Semiconductor RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor RSS RSS


Semiconductor light emitting device and fabrication method thereof

Samsung Electronics

Semiconductor light emitting device and fabrication method thereof

Semiconductor devices and methods for fabricating the same

Semiconductor devices and methods for fabricating the same

Semiconductor devices and methods for fabricating the same

D2s

Method for fracturing and forming a pattern using shaped beam charged particle beam lithography

Date/App# patent app List of recent Semiconductor-related patents
04/16/15
20150106780
 Semiconductor device reliability model and methodologies for use thereof patent thumbnailnew patent Semiconductor device reliability model and methodologies for use thereof
Systems and methods for semiconductor device reliability qualification during semiconductor device design. A method is provided that includes defining performance process window bins for a performance window.
International Business Machines Corporation
04/16/15
20150106777
 Method and system for three-dimensional layout design of integrated circuit elements in stacked cmos patent thumbnailnew patent Method and system for three-dimensional layout design of integrated circuit elements in stacked cmos
A method includes providing a design of a semiconductor device such as a stacked cmos device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based on at least one predetermined criterion. Each respective one of the at least one first type of circuit element is to be assigned to a respective designated one of the plurality of tiers.
Taiwan Semiconductor Manufacturing Co., Ltd.
04/16/15
20150106774
 High-level synthesis data generation apparatus, high-level synthesis apparatus, and high-level synthesis data generation method patent thumbnailnew patent High-level synthesis data generation apparatus, high-level synthesis apparatus, and high-level synthesis data generation method
An analysis unit analyzes a source code representing design data of a semiconductor device, and generates information (cdfg information) indicating the data and control flow of the semiconductor device. A high-level synthesis data generation unit acquires intermediate data (an object file), which is obtained by compiling the source code, generates intermediate data (an object file) by incorporating the cdfg information generated by the analysis unit into the acquired intermediate data, and outputs the generated intermediate data as high-level synthesis data..
Fujitsu Semiconductor Limited
04/16/15
20150106772
 Method for fracturing and forming a pattern using shaped beam charged particle beam lithography patent thumbnailnew patent Method for fracturing and forming a pattern using shaped beam charged particle beam lithography
In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a series of curvilinear character projection shots are determined for a charged particle beam writer system, such that the set of shots can form a continuous track, possibly of varying width, on a surface. A method for forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed.
D2s, Inc.
04/16/15
20150106678
 Semiconductor device and semiconductor system including the same patent thumbnailnew patent Semiconductor device and semiconductor system including the same
A semiconductor system includes a memory configured to output a parity bit during a read operation and receive a data mask (dm) signal during a write operation. The semiconductor system also includes a system on chip (soc) configured to detect errors by decoding the parity bit during the read operation, and output the dm signal to the memory during the write operation.
Sk Hynix Inc.
04/16/15
20150106635
 Semiconductor integrated circuit and  controlling the same patent thumbnailnew patent Semiconductor integrated circuit and controlling the same
A semiconductor integrated circuit includes a system bus configured to operate at a first clock, a plurality of arithmetic processing units including a first arithmetic processing unit which is connected to the system bus and operates at a second clock, and a control circuit controlling the system bus and the arithmetic processing units. After checking that an access from the arithmetic processing units to the system bus is not generated, the control circuit changes frequency of the first clock or the second clock..
Fujitsu Limited
04/16/15
20150106558
 Semiconductor device and data processing method patent thumbnailnew patent Semiconductor device and data processing method
A semiconductor device has: as security states to which the nonvolatile memory device can transition, an unprotected state in which, when secret information is not set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted, and reading the stored information is permitted; a protection unlocked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted on condition that a result of authentication using the secret information is correct, and reading the stored information is permitted; and a protection locked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is inhibited until correctness as a result of authentication using the secret information is confirmed, and reading the stored information is inhibited under a predetermined condition.. .
Renesas Electronics Corporation
04/16/15
20150106555
 Nonvolatile semiconductor storage system patent thumbnailnew patent Nonvolatile semiconductor storage system
A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus.
Hitachi, Ltd.
04/16/15
20150106551
 Semiconductor device and operating method thereof patent thumbnailnew patent Semiconductor device and operating method thereof
A semiconductor device remaps the relationship between logical addresses and physical addresses of a semiconductor memory device at each first interval. The semiconductor device may include a wear leveling controller configured to select a first physical address of the semiconductor memory device to remap a logical address corresponding to the first physical address of the semiconductor memory device to a second physical address of the semiconductor memory device, and to adjust the first interval..
Sk Hynix Inc.
04/16/15
20150106550
 Information processing apparatus,  controlling the same and  storage medium patent thumbnailnew patent Information processing apparatus, controlling the same and storage medium
An information processing apparatus determines, when data is written to a semiconductor storage including a plurality of flash memories, whether or not the data to be written is specific data (data associated with the complete erasure) for which it is set that unnecessary data relating to the data is made to be erasable so that the unnecessary data does not remain in the semiconductor storage. In a case where it is determined that the data to be written is not the specific data, the information processing apparatus performs data write processing in a state where an interleave is enabled.
Canon Kabushiki Kaisha
04/16/15
20150105668
new patent

Endoscopic, exoscopic or microscopic fluorescence diagnosis


An endoscopic, exoscopic or microscopic apparatus for fluorescence diagnosis comprises a light source designed to emit light in a first spectral range and light in a second spectral range in a fluorescence mode the second spectral range is at least partly separate from the first spectral range. The light source has at least one first semiconductor illuminant which emits the light in the first spectral range in the fluorescence mode.
Karl Storz Gmbh & Co. Kg
04/16/15
20150105308
new patent

Aqua regia and hydrogen peroxide hcl combination to remove ni and nipt residues


A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The sc2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate..
Globalfoundries, Inc.
04/16/15
20150104971
new patent

Connecting module, power supply module and connecting set for light strips


Various embodiments may relate to a connecting module for mechanically connecting two light strips each having at least one semiconductor light source and having at least two electrical contacts arranged in a housing, which electrical contacts each have two contact sections for making electrical contact with the light strips. The electrical contacts in each case pass through the housing with a further contact section for connection to a power supply..
Osram Gmbh
04/16/15
20150104953
new patent

High uv curing efficiency for low-k dielectrics


One embodiment is a method for semiconductor processing. In this method, a precursor film is provided over a semiconductor substrate, where the precursor film is made of a structural former and porogen.
Taiwan Semiconductor Manufacturing Co., Ltd.
04/16/15
20150104952
new patent

Method and composition for selectively removing metal hardmask and other residues from semiconductor device substrates comprising low-k dielectric material and copper


An aqueous removal composition having a ph in the range of from 2 to 14 and method for selectively removing an etching mask consisting essentially of tin, tan, tinxoy, tiw, w, or alloy of ti or w relative to low-k materials from a semiconductor substrate comprising said low-k materials having a tin, tan, tinxoy, tiw, w, or alloy of ti or w etching mask thereon wherein the removal composition comprises at least one oxidizing agent and a carboxylate compound.. .
Ekc Technology, Inc.
04/16/15
20150104949
new patent

Semiconductor manufacturing apparatus and method thereof


In some embodiments of the present disclosure, an apparatus includes an ionizer. The ionizer is configured to dispatch a reactive ion on a surface.
Taiwan Semiconductor Manufacturing Company Ltd.
04/16/15
20150104947
new patent

Methods of forming semiconductor devices using hard masks


Methods of forming a semiconductor device are provided. The methods may include forming an insulating layer including silicon on a substrate and sequentially forming a first hard mask layer and a second hard mask layer on the substrate.
Samsung Electronics Co., Ltd.
04/16/15
20150104946
new patent

Methods of forming fine patterns for semiconductor devices


Methods of forming fine patterns for semiconductor devices are provided. A method may include sequentially forming a lower layer and a mask layer having first openings on a substrate, forming pillars to fill the first openings and protrude upward from a top surface of the mask layer, forming a block copolymer layer on the substrate with the pillars, performing a thermal treatment to the block copolymer layer to form a first block portion and second block portions, removing the second block portions to form guide openings exposing the mask layer, and etching the mask layer exposed by the guide openings to form second openings..
Samsung Electronics Co., Ltd.
04/16/15
20150104945
new patent

Methods of fabricating a semiconductor device


A method for fabricating a semiconductor device is provided. In the method, a first hard mask layer is formed on a stepped structure.
04/16/15
20150104944
new patent

Method of forming patterns for semiconductor device


There is provided a method of forming patterns for a semiconductor device. The method sequentially forming a first mask layer and a second mask layer on a substrate.
Samsung Electronics Co., Ltd.
04/16/15
20150104943
new patent

Method for forming semiconductor structure


A method for forming a semiconductor structure. A dielectric layer including adjacent first and second dielectric regions is formed on a substrate.
United Microelectronics Corp.
04/16/15
20150104942
new patent

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device includes processing a semiconductor substrate using a plasma etching apparatus provided with a processing chamber. The semiconductor substrate has an uneasily-etched material formed thereabove and at least an upper layer film formed above the uneasily-etched material.
Kabushiki Kaisha Toshiba
04/16/15
20150104939
new patent

Wet-process ceria compositions for polishing substrates, and methods related thereto


Disclosed are a chemical-mechanical polishing composition and a method of polishing a substrate. The polishing composition comprises low average particle size (e.g., 30 nm or less) wet-process ceria abrasive particles, at least one alcohol amine, and water, wherein said polishing composition has a ph of about 6.
Cabot Miroelectronics Corporation
04/16/15
20150104938
new patent

Method for forming damascene opening and applications thereof


A method for forming a damascene opening, wherein the method comprises steps as follows: firstly, a semiconductor structure comprising an inter-metal dielectric (imd), a first hard mask layer and a second hard mask layer stacked in sequence is provided, wherein the semiconductor structure has at least one trench extending downwards from the second hard mask layer to the imd. A plasma treatment is then performed to modify a portion of the first hard mask layer exposed from the trench.
United Microelectronics Corporation
04/16/15
20150104934
new patent

Semiconductor device and fabricating the same


A semiconductor device includes a substrate including an active region, an insulation layer formed over the substrate, a plurality of openings formed in the insulation layer, a plurality of contact plugs filling the plurality of openings, a silicide layer formed over the substrate and between the substrate and each contact plug of the contact plugs in order to cover a bottom of each contact plug. The semiconductor device may decrease contact resistance by forming a silicide layer before the formation of openings regardless of the linewidth and aspect ratio of the openings.
Sk Hynix Inc.
04/16/15
20150104933
new patent

Systems and methods for annealing semiconductor device structures using microwave radiation


Systems and methods are provided for annealing a semiconductor device structure using microwave radiation. For example, a semiconductor device structure is provided.
Taiwan Semiconductor Manufacturing Company Limited
04/16/15
20150104932
new patent

Compositions for etching and methods of forming a semiconductor device using the same


Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound.
Soulbrain Co., Ltd.
04/16/15
20150104929
new patent

Method and dicing wafers having thick passivation polymer layer


Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a front surface having a plurality of integrated circuits thereon involves forming a mask layer above the front surface of the semiconductor wafer.
04/16/15
20150104927
new patent

Semiconductor structure and manufacturing method thereof


A method for fabricating a semiconductor device is provided. The method includes: providing a first wafer having a first active surface and a first rear surface opposite to the first active surface, the first wafer comprising a first circuit formed therein; providing a second wafer having a second active surface and a second rear surface opposite to the second active surface, the second wafer comprising a second circuit formed therein; bonding the first active surface of the first wafer with the second active surface of the second wafer so as to electrically connecting the first circuit and the second circuit; thinning the second wafer from the second rear surface; and forming at least a conductive through via in the second wafer, wherein the conductive through via is electrically connected to the first circuit through the second circuit..
Industrial Technology Research Institute
04/16/15
20150104926
new patent

Method of manufacturing high resistivity soi substrate with reduced interface conducitivity


A method of preparing a high resistivity single crystal semiconductor handle wafer comprising implanting he ions through a front surface of the high resistivity single crystal semiconductor handle wafer, which is followed by an anneal sufficient to form a nanocavity layer in the damage region formed by he ion implantation. The anneal may be prior to or concurrent with thermal oxidation to prepare a front oxidized surface layer..
Sunedison Semiconductor Limited (uen201334164h)
04/16/15
20150104920
new patent

Semiconductor device and related fabrication methods


semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region.
04/16/15
20150104919
new patent

Three-dimensional semiconductor device, variable resistive memory device including the same, and manufacturing the same


A three-dimensional semiconductor device, a resistive variable memory device including the same, and a method of manufacturing the same are provided. The method may include forming a source on a semiconductor substrate, sequentially forming a first semiconductor layer formed of a first material, a second semiconductor layer formed of a second material having a higher oxidation rate than that of the first material, and a third semiconductor layer formed of the first material on the source; patterning the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; forming a lightly doped drain (ldd) region in the second semiconductor layer and a drain in the third semiconductor layer; oxidizing outer circumferences of the first semiconductor layer, the ldd region and the drain region to form a gate insulating layer; forming a gate on an outer circumference of the gate insulating layer to overlap the first semiconductor layer and a portion of the ldd region; foaming a heating electrode on the drain; and forming a variable resistance layer on the heating electrode..
Sk Hynix Inc.
04/16/15
20150104918
new patent

Facilitating fabricating gate-all-around nanowire field-effect transistors


Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s).
Globalfoundries Inc.
04/16/15
20150104917
new patent

Power mosfet and methods for forming the same


A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region.
Taiwan Semiconductor Manufacturing Company, Ltd.
04/16/15
20150104916
new patent

Method of manufacturing three dimensional semiconductor memory device


A method of manufacturing a three-dimensional semiconductor memory device is provided. The method includes alternately stacking a first insulation film, a first sacrificial film, alternating second insulation films and second sacrificial films, a third sacrificial film and a third insulation film on a substrate.
04/16/15
20150104914
new patent

Semiconductor process


A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate.
United Microelectronics Corp.
04/16/15
20150104913
new patent

Simultaneous formation of source/drain openings with different profiles


A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.
04/16/15
20150104911
new patent

Semiconductor device and method


A semiconductor device is disclosed. One embodiment includes a lateral hemt (high electron mobility transistor) structure with a heterojunction between two differing group iii-nitride semiconductor compounds and a layer arranged on the heterojunction.
Infineon Technologies Austria Ag
04/16/15
20150104906
new patent

Package for high-power semiconductor devices


Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier.
Triquint Semiconductor, Inc.
04/16/15
20150104905
new patent

Method of manufacturing a semiconductor package


A semiconductor package includes a circuit board having an inner circuit pattern and a plurality of contact pads connected to the inner circuit pattern, at least one integrated circuit (ic) device on the circuit board and making contact with the contact pads, a mold on the circuit board, the mold fixing the ic device to the circuit board, and a surface profile modifier on a surface of the ic device and a surface of the mold, and the surface profile modifier enlarging a surface area of the ic device and the mold to dissipate heat.. .
Samsung Electronics Co., Ltd.
04/16/15
20150104904
new patent

Method of manufacturing a semiconductor device


Provided is a semiconductor device characterized by that first to fourth semiconductor chips are mounted on first to fourth electrodes formed by plating, respectively; the surface of the first semiconductor chip and the upper surface of a fifth electrode, the surface of the second semiconductor chip and the upper surface of the first electrode, the surface of the third semiconductor chip and the upper surface of the fourth electrode, the surface of the fourth semiconductor chip and the upper surface of the fifth electrode, and the upper surface of the second electrode and the upper surface of the third electrode are coupled to each other by first to fifth conductive members, respectively; and the back surfaces of the first to fifth electrodes are exposed from a resin molding. The invention makes it possible to reduce the size and the thickness of a semiconductor device configuring a diode bridge circuit..
Renesas Electronics Corporation
04/16/15
20150104901
new patent

Oxide semiconductor film and semiconductor device


It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed.
Semiconductor Energy Laboratory Co., Ltd.
04/16/15
20150104899
new patent

Manufactoring semiconductor-based multi-junction photovoltaic devices


Manufacture of multi-junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields and lower costs.
Epiworks, Inc.
04/16/15
20150104898
new patent

Method for manufacturing inverted metamorphic multijunction solar cells


A method of fabricating both a multijunction solar cell and an inverted metamorphic multijunction solar cell in a single process using a mocvd reactor by forming a first multijunction solar cell on a semiconductor substrate; forming a release layer over the first solar cell; forming an inverted metamorphic second solar cell over the release layer; and etching the release layer so as to separate the multijunction first solar cell and the inverted metamorphic second solar cell.. .
Emcore Solar Power, Inc.
04/16/15
20150104890
new patent

Semiconductor light emitting device and fabrication method thereof


A semiconductor light emitting device includes a substrate having first and second electrode patterns on at least one surface thereof, a light emitting structure on a surface of the substrate, a first electrode structure, a second electrode structure, an insulating layer, a first connection portion connecting the first electrode structure and the first electrode pattern, and a second connection portion connecting the second electrode structure extending outwardly from the light emitting structure and the second electrode pattern.. .
Samsung Electronics Co., Ltd.
04/16/15
20150104889
new patent

Semiconductor device, manufacturing semiconductor device, semiconductor manufacturing and inspecting apparatus, and inspecting apparatus


A semiconductor device having cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (csl) boundary having a grain boundary sigma value 27 or less to all crystal grain boundaries of a cu wiring to 60% or higher.
Renesas Electronics Corporation
04/16/15
20150104888
new patent

System for determining presence of abnormality of heater for semiconductor thin film deposition apparatus


The present invention relates, in general, to an apparatus for determining the presence of abnormality of a heater for a semiconductor thin film deposition apparatus, such as an aluminum or ceramic heater and, more particularly, to a technique for monitoring a phenomenon occurring in an apparatus during a semiconductor thin film deposition process and a phenomenon occurring in a heater, thereby determining the presence of abnormality of the heater. The present invention also relates to a technique for measuring, in real time, a thickness of a thin film deposited by driving of a heater during a thin film deposition process in a chamber, thereby determining the presence of abnormality of a wafer and the presence of abnormality of the heater, based on the measurement result..
04/16/15
20150104887
new patent

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device includes generating a mask layout of patterns in which the distance between adjacent ones of the patterns is equal to or less than a resolution of a lithography process, the patterns are apportioned among a plurality of masks such that in each of the masks the space between adjacent ones of the patterns is greater than the resolution, and a dual pattern is added to one of the masks. A semiconductor pattern is formed on a substrate using the mask(s) and the mask to which the dual pattern has been added.
Samsung Electronics Co., Ltd.
04/16/15
20150104886
new patent

Semiconductor device arrangement, a analysing a performance of a functional circuit on a semiconductor device and a device analysis system


A semiconductor device arrangement comprising a functional circuit comprising a plurality of timing components and a reference module comprising a plurality of reference components is described. Each reference component comprises a reference timing component corresponding to a timing component of the plurality of timing components and a controllable timing component.
Freescale Semiconductor, Inc.
04/16/15
20150104884
new patent

Semiconductor memory device and manufacturing method thereof


A method for manufacturing a semiconductor memory device includes forming a magnetic tunnel junction layer on a lower electrode, forming a spacer having an annular shape on the magnetic tunnel junction layer, forming upper electrodes on both sidewall surfaces of the annular shaped spacer, removing the spacer, and etching the magnetic tunnel junction layer by using the upper electrodes as an etch mask.. .
Sk Hynix Inc.
04/16/15
20150104883
new patent

Semiconductor devices and methods for fabricating the same


A method of fabricating a semiconductor device includes providing a wafer in a chamber of a point-cusp magnetron physical vapor deposition (pcm-pvd) apparatus, the chamber including a metal target. The method further includes providing an inert gas and a reactive gas in the chamber and forming an amorphous conductive layer on the wafer by reacting the reactive gas with a metal atom separated from the metal target by the inert gas..
04/16/15
20150104745
new patent

Tool configuration and extreme ultra-violet (euv) patterning with a deformable reflective surface


Some embodiments of the present disclosure relates to a tool configuration and method for euv patterning with a deformable reflective surface comprising a mirror or reticle. A radiation source provides euv radiation which is reflected off the deformable reflective surface to transfer a reticle pattern a semiconductor workpiece.
Taiwan Semiconductor Manufacturing Co., Ltd.
04/16/15
20150104657
new patent

Lead, wiring member, package part, metal part provided with resin and resin-sealed semiconductor device, and methods for producing same


A semiconductor device and manufacturing method therefor, provided with the aims of constraining resin burr formation while having good electric connectivity and joining strength, and led device, provided with the aim of improving adhesion between silicon resin and leads while having good luminescent characteristics. For these purposes, an organic film is formed through self-assembly by functional organic molecules at surface border regions of outer leads of a qfp.
Panasonic Intellectual Property Management Co., Ltd.
04/16/15
20150104649
new patent

Laminated sheet and manufacturing semiconductor device using the laminated sheet


The present invention provides a laminated sheet that can prevent the decrease in adhering strength of a resin composition layer and the deterioration in electrical reliability and in which a back grinding tape can be peeled from a plurality of semiconductor elements collectively after dicing. The laminated sheet has a back grinding tape in which a pressure-sensitive adhesive layer is formed on a base, and a resin composition layer that is provided on the pressure-sensitive adhesive layer of the back grinding tape, wherein the tensile modulus of the pressure-sensitive adhesive layer at 23° c.
Nitto Denko Corporation
04/16/15
20150104569
new patent

Barrier layers for silver reflective coatings and hpc workflows for rapid screening of materials for such barrier layers


Provided is high productivity combinatorial (hpc) testing methodology of semiconductor substrates, each including multiple site isolated regions. The site isolated regions are used for testing different compositions and/or structures of barrier layers disposed over silver reflectors.
Intermolecular Inc.
04/16/15
20150104083
new patent

Thin biometric detection module


There is provided a thin biometric detection module, which is advantageous in being able to detect scattered light from body tissue after the light transmitting in the body tissue without additional optical mechanism placed on the semiconductor optical detection pixel of the detection module for biometric detection.. .
Pixart Imaging Inc.


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Semiconductor topics: Semiconductor, Semiconductor Substrate, Semiconductor Device, Semiconductor Material, Electric Conversion, Conductive Layer, Molybdenum, Camera Module, Semiconductor Devices, Semiconductors, Integrated Circuit, Surfactant, Photoelectric Conversion, Electronic Device, Transparent Conductive Oxide

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