|| List of recent Semiconductor-related patents
|Revising layout design through opc to reduce corner rounding effect|
The present disclosure provides a method of fabricating a semiconductor device. A first layout design for a semiconductor device is received.
|Encoder, decoder and semiconductor device including the same|
Provided is a semiconductor device configured to encode input data into a codeword including m different symbols, each of which includes nm symbols. The semiconductor device including a first storage unit configured to store a first state value which is reset according to m and nm; a second storage unit corresponding to any one of the m different symbols and configured to store m second state values determined through the corresponding symbol and the first state value; a third storage unit configured to store a third state value..
|Semiconductor memory devices including separately disposed error-correcting code (ecc) circuits|
A semiconductor memory device may comprise: at least one bank, each of the at least one bank including a plurality of memory cells; an error-correcting code (ecc) calculator configured to generate syndrome data for detecting an error bit from among parallel data bits read out from the plurality of memory cells of each of the at least one bank; an ecc corrector separated from the ecc calculator, the ecc corrector configured to correct the error bit from among the parallel data bits by using the syndrome data and configured to output error-corrected parallel data bits; and/or a data serializer configured to receive the error-corrected parallel data bits and configured to convert the error-corrected parallel data bits into serial data bits.. .
|Encoder, decoder and semiconductor device including the same|
A semiconductor device may include a first encoding unit configured to encode first data into an anti-drift code, and a second encoding unit configured to add parity information to the anti-drift code.. .
A semiconductor device may include a storage unit configured to store a number of times a first command has been provided to a memory cell array, a control unit configured to generate a second command operable to activate at least one word line in the memory cell array based on a comparison of the number stored at the storage unit with a threshold value, when the first command is received, and a selection unit configured to select one of the first command and the second command based on a result of the comparison and transmit the selected command to the memory cell array.. .
|Semiconductor device for performing test and repair operations|
A semiconductor device may include: a storage unit configured to store program codes provided through control of a processor core; and a control unit configured to perform a control operation on a semiconductor memory device according to the program codes.. .
Methods and systems for performing semiconductor metrology directly on device structures are presented. A measurement model is created based on measured training data collected from at least one device structure.
|Connector with air extraction|
An electrical connector a semiconductor processing tool is provided. The electrical connector comprises a male connector part having pins and a first holder in which the pins are mounted and a female connector part having sockets and a second holder in which the sockets are mounted.
|Process for smoothing a surface via heat treatment|
The process for smoothing a rough surface of a first substrate made of a semiconductor alloy based on at least two elements chosen from ga, as, al, in, p and n is implemented by placing a second substrate facing the first substrate so that the rough surface is placed facing a surface of the second substrate. The first and second substrates are separated by a distance d of at least 10 μm, the facing portions of the two substrates defining a confinement space.
|Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium|
A method of manufacturing a semiconductor device includes: pre-treating a surface of a substrate by supplying an oxygen-containing gas and a hydrogen-containing gas to the substrate heated in a process chamber under a pressure less than atmospheric pressure; and forming a film on the pre-treated substrate by performing a cycle a predetermined number of times. The cycle includes: supplying a precursor gas to the substrate in the process chamber; and supplying a reaction gas to the substrate in the process chamber..
|Cold spray barrier coated component of a plasma processing chamber and method of manufacture thereof|
A cold spray barrier coated component of a semiconductor plasma processing chamber comprises a substrate having at least one metal surface wherein a portion of the metal surface is configured to form an electrical contact. A cold spray barrier coating is formed from a thermally and electrically conductive material on at least the metal surface configured to form the electrical contact of the substrate.
|Method of manufacturing a semiconductor device including a stress relief layer|
A method of manufacturing a semiconductor device includes providing a layered structure having a hard dielectric layer containing a first dielectric material having a young's modulus greater than 10 gpa in a central portion of a main surface of a main body comprising a single crystalline semiconductor body, and providing a dielectric stress relief layer containing a second dielectric material having a lower young's modulus than the first dielectric material, the stress relief layer covering the layered structure and extending beyond an outer edge of the layered structure.. .
|Method of manufacturing semiconductor device|
A method of manufacturing a semiconductor device includes forming a second insulating layer over a first insulating layer, forming a mask over the second insulating layer, after the forming the mask, a first etching of the second insulating layer which is not covered by the mask, and after the first etching, a second etching of the second insulating layer and the first insulating layer which are not covered by the mask. At the first etching, the second insulating layer left over the first insulating layer and the first insulating layer is not exposed.
|Interconnection wires of semiconductor devices|
A method of forming a semiconductor device includes forming a plurality of substantially equal-spaced first spacers having a first pitch over a substrate and forming first metal interconnecting wires utilizing the first spacers. The method also includes forming a plurality of substantially equal-spaced second spacers in such a way to abut, respectively, the plurality of first metal interconnecting wires and define a plurality of substantially equal-spaced trenches.
|Interconnect fabrication at an integrated semiconductor processing station|
A stand-alone processing station of a semiconductor manufacturing system may be configured to fabricate interconnects on a semiconductor wafer. The stand-alone processing station may include a chemical mechanical polishing (cmp) module and an electro-chemical deposition (ecd) module.
|Nonvolatile semiconductor memory device and method of manufacturing|
A nonvolatile semiconductor memory device includes a first insulating layer on a semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The charge storage layer includes a floating gate layer on the first insulating layer, an interface insulating layer on the floating gate layer, and a charge trap layer on the interface insulating layer, and a lower end of a conduction band of the interface insulating layer is higher than a trap level of the charge trap layer and is lower than a lower end of a conduction band of the charge trap layer..
|Work function adjustment with the implant of lanthanides|
Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal.
|Selective epitaxial growth of semiconductor materials with reduced defects|
A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls.
|Methods of forming isolation regions for bulk finfet semiconductor devices|
One method disclosed herein includes forming a plurality of fin-formation trenches in a semiconductor substrate that define a plurality of spaced-apart fins, forming a patterned liner layer that covers a portion of the substrate positioned between the fins while exposing portions of the substrate positioned laterally outside of the patterned liner layer, and performing at least one etching process on the exposed portions of the substrate through the patterned liner layer to define an isolation trench in the substrate, wherein the isolation trench has a depth that is greater than a depth of the fin-formation trenches.. .
|Resistive random access memory cells having metal alloy current limiting layers|
Provided are semiconductor devices, such as resistive random access memory (reram) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon.
|Semiconductor device and method of making|
The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by concurrently formed metal-semiconductor compound contact regions at the source and drain and metal-semiconductor compounds in vias formed at positions corresponding to the source and drain.
|Method of forming semiconductor device|
A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate.
|6t sram architecture for gate-all-around nanowire devices|
A memory device includes a first plurality of semiconductor nanowires tethered between landing pads and suspended over a substrate. A first gate electrode surrounds each of the first plurality of semiconductor nanowires, making them gate-all-around, (gaa) semiconductor nanowires.
|Replacement metal gate process for cmos integrated circuits|
A complementary metal-oxide-semiconductor (cmos) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel mos transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness.
|Method of scavenging impurities in forming a gate stack having an interfacial layer|
A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a gate stack disposed over a semiconductor substrate includes an interfacial dielectric layer disposed over the semiconductor substrate, a high-k dielectric layer disposed over the interfacial dielectric layer, a first conductive layer disposed over the high-k dielectric layer, and a second conductive layer disposed over the first conductive layer.
|Semiconductor device manufacturing method|
A semiconductor device includes a p-type semiconductor layer, n-type column regions formed of columnar thermal donors exhibiting an n-type property, a p-type column region interposed between the n-type column regions, the n-type column regions configured to form a super-junction structure in cooperation with the p-type column region, a channel region formed in the semiconductor layer, a source region formed in the channel region, a gate insulator film formed on the semiconductor layer, and a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film.. .
|Semiconductor device and method for manufacturing the same|
In a manufacturing method of a semiconductor device, a semiconductor chip is sealed with a resin, and then a laser is applied to remove the resin so that a part of the semiconductor chip is exposed. The semiconductor chip is made of a material that has a lower absorptivity of the laser than the resin and is not melted by the laser.
|Manufacturing method of wafer level package|
The present invention provides a method for manufacturing a semiconductor package structure, including (i) providing a carrier plate; (ii) disposing a die on the carrier plate; (iii) forming a plurality of bonding wires having a first end and a second end; (iv) forming an encapsulant covering the die and the bonding wires and exposing a portion of each of the bonding wires from a first surface thereof; (v) removing the carrier plate; (vi) forming a patterned conductive layer on a second surface of the encapsulant opposite to the first surface; (vii) electrically connecting the second ends of the bonding wires to the active surface of the die via the patterned conductive layer; and (viii) forming a plurality of first external connection terminals on the first surface of the encapsulant respectively covering the portions of the bonding wires exposed from the encapsulant.. .
|Fabrication method of packaging substrate, and fabrication method of semiconductor package|
A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant in the first openings; a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.. .
|Semiconductor device fabricating method|
A semiconductor device fabricating method includes forming device chip regions and a monitor chip region for processing management, on a substrate surface layer on one main surface side of a semiconductor substrate wafer, each device chip region having an active region and an edge region; after forming metal films on front surface of the device chip regions and the monitor chip region by vapor deposition and photolithography, forming protective films on the front surfaces of the device chip regions and monitor chip region; and grinding and polishing another main surface side of the semiconductor substrate wafer to thin the semiconductor substrate wafer. A difference between an area of one chip occupied by the protective film of the monitor chip region and an area of one chip occupied by the protective film of the device chip region is 20% or less..
|Fabrication method of semiconductor package without chip carrier|
A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves.
|Semiconductor device and method for manufacturing the same|
A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region.
|Methods for thick films thermoelectric device fabrication|
Solid state thermoelectric energy conversion devices can provide electrical energy from heat flow, creating energy, or inversely, provide cooling through applying energy. Thick film methods are applied to fabricate thermoelectric device structures using microstructures formed through deposition and subsequent thermal processing conditions.
|Light-emitting device and method for manufacturing same|
Disclosed is a light-emitting device comprising a light-emitting element (10) composed of a gallium nitride compound semiconductor having an emission peak wavelength of not less than 430 nm; a molded body (40) provided with a recessed portion having a bottom surface on which the light-emitting element (10) is mounted and a lateral surface; and a sealing member (50) containing an epoxy resin including a triazine derivative epoxy resin, or a silicon-containing resin. The molded body (40) is obtained by using a cured product of a thermosetting epoxy resin composition essentially containing an epoxy resin including a triazine derivative epoxy resin, and has a reflectance of not less than 70% at the wavelengths of not less than 430 nm..
|Semiconductor device and method for manufacturing the same|
According to one embodiment, a semiconductor device includes first, second, and third molded bodies. The first molded body covers a first light emitting element, a part of a lead electrically connected to the first light emitting element, a first light receiving element configured to detect a light emitted from the first light emitting element, and a part of a lead electrically connected to the first light receiving element with a first resin.
|Measurement device, measurement method, and method for manufacturing semiconductor device|
There is provided a measuring apparatus including: an illuminator configured to illuminate, with an illumination light, a substrate having a pattern formed by exposure on a surface; a detector configured to detect the illumination light modulated by the pattern to output a detection signal; and a measuring unit configured to measure an exposure condition of the pattern of a desired portion by using the detection signals detected at a plurality of portions of the pattern.. .
|Optical semiconductor apparatus|
An optical semiconductor device includes a silicon oxide layer configured to be formed on a substrate; an optical waveguide part configured to be formed on the silicon oxide layer; a cladding layer configured to be formed covering the optical waveguide part; and a semiconductor laser configured to be disposed on the substrate. Laser light emitted from the semiconductor laser enters the optical waveguide part.
|Micromechanical detection structure for a mems acoustic transducer and corresponding manufacturing process|
A micromechanical structure for a mems capacitive acoustic transducer, has: a substrate made of semiconductor material, having a front surface lying in a horizontal plane; a membrane, coupled to the substrate and designed to undergo deformation in the presence of incident acoustic-pressure waves; a fixed electrode, which is rigid with respect to the acoustic-pressure waves and is coupled to the substrate by means of an anchorage structure, in a suspended position facing the membrane to form a detection capacitor. The anchorage structure has at least one pillar element, which is at least in part distinct from the fixed electrode and supports the fixed electrode in a position parallel to the horizontal plane..
|X-ray diffraction apparatus, x-ray diffraction measuring method, and control program|
The x-ray diffraction apparatus irradiates a sample with an x-ray and performs frame photographing in each x-ray diffraction angle, and includes a control section (141) controlling the frame photographing by scanning without closing a shutter, a data acquisition section (142) acquiring detection data of each frame which has been detected by a semiconductor pixel detector in the frame photographing, a frame integration section (146) integrating the detection data which has been acquired in each scanning for each frame, and a determination section (147) determining whether the integrated detection data has a sufficient intensity or not, and the control section (141) controls so as to finish measurement when the integrated detection data has a sufficient intensity and so as to perform the scanning again when the integrated detection data does not have a sufficient intensity.. .
|Semiconductor laser with varied-width waveguide and semiconductor laser module including the same|
A semiconductor laser outputs a laser light from an output facet of a waveguide having an index waveguide structure, via a lens system. The waveguide includes, in order from a rear facet opposite to the output facet, a first narrow portion, a wide portion that is wider than the first narrow portion, a second narrow portion narrower than the wide portion, a first tapered portion formed between the first narrow portion and the wide portion, which expands toward the wide portion, and a second tapered portion formed between the wide portion and the second narrow portion, which narrows toward the second narrow portion.