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This page is updated frequently with new Semiconductor-related patent applications. Subscribe to the Semiconductor RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor RSS RSS


Triple-pattern lithography layout decomposition

Triple-pattern lithography layout decomposition

Method and system for a gallium nitride vertical jfet with self-aligned source and gate

Method and system for a gallium nitride vertical jfet with self-aligned source and gate

Method and system for a gallium nitride vertical jfet with self-aligned source and gate

Micro electro mechanical system, semiconductor device, and manufacturing method thereof

Date/App# patent app List of recent Semiconductor-related patents
12/18/14
20140372959
 Analytical model for predicting current mismatch in metal oxide semiconductor arrays patent thumbnailnew patent Analytical model for predicting current mismatch in metal oxide semiconductor arrays
A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (mos) array. A first subset of cells in the mos array is selected and current measured for each of these cells.
12/18/14
20140372958
 Triple-pattern lithography layout decomposition patent thumbnailnew patent Triple-pattern lithography layout decomposition
Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity.
12/18/14
20140372839
 Semiconductor device, semiconductor system and control method of semiconductor device patent thumbnailnew patent Semiconductor device, semiconductor system and control method of semiconductor device
A semiconductor device includes a mode register set suitable for generating a first internal control signal and a second internal control signal, a per-dram addressability (pda) driving unit suitable for resetting the mode register set in response to the first internal control signal and an input value of data inputted through a data pad, and a cycle redundancy check (crc) driving unit suitable for performing a crc operation by checking whether or not data are correctly inputted through the data pad without an error in response to the first internal control signal and the second internal control signal.. .
12/18/14
20140372837
 Semiconductor integrated circuit and method of processing in semiconductor integrated circuit patent thumbnailnew patent Semiconductor integrated circuit and method of processing in semiconductor integrated circuit
A semiconductor integrated circuit includes: a first-combinational-circuit to output a state-value depending on an input signal and a parity-value of the state-value which are stored by a first-flip-flop-circuit; a first-parity-check-circuit to perform a parity check based on the state-value and the parity-value and output a first-parity-error; a second-flip-flop-circuit to store the state-value and the parity-value output by the first-combinational-circuit; a second-parity-check-circuit to perform a parity check based on the state-value and the parity-value stored in the second-flip-flop-circuit and output a second-parity-error; and a selector to, when the first-parity-error is not output but the second-parity-error is output, output the state-value stored in the first-flip-flop-circuit to the first-combinational-circuit, and when the first-parity-error is output but the second-parity-error is not output, output the state-value stored in the second-flip-flop-circuit to the first-combinational-circuit, wherein the first-combinational-circuit outputs a current state-value depending on the state-value output by the selector and the input signal.. .
12/18/14
20140372780
 Power supply device patent thumbnailnew patent Power supply device
In a power supply device, the bridge circuit is configured by connecting, in parallel, a plurality of series circuits of an inverse-parallel connection circuit of a semiconductor switch and a diode. A control unit controls switching of a semiconductor switch so that a voltage v between ac terminals becomes zero voltage in equal periods α before and after a center point shifted from one zero crossing point in one cycle of the input current by a compensation period (angle) β calculated from a voltage applied to a resonance circuit constituted by the power receiving coil and a resonance capacitor cr and an induced voltage of the power receiving coil, and becomes a positive-negative voltage whose peak value is the voltage vo between dc terminals in other periods..
12/18/14
20140372690
 Memory system, semiconductor device and methods of operating the same patent thumbnailnew patent Memory system, semiconductor device and methods of operating the same
A memory system, a semiconductor memory device and methods of operating the same may perform a read operation on the basis of flag data stored in a flag register, without reading the flag data stored in a memory array, when performing the read operation, so that a time taken for the read operation may be reduced.. .
12/18/14
20140372666
 Semiconductor device with configurable support for multiple command specifications, and method regarding the same patent thumbnailnew patent Semiconductor device with configurable support for multiple command specifications, and method regarding the same
A device includes a nand flash memory, and a generic command interface configured to interpret both an open nand flash interface specification and a first nand flash specification to perform an associated one of command operations on the nand flash memory, the open nand flash interface specification and the first nand flash specification being different from each other.. .
12/18/14
20140372664
 Semiconductor memory device and memory system patent thumbnailnew patent Semiconductor memory device and memory system
A semiconductor memory device and a memory system are disclosed. The semiconductor memory device includes: a memory bank configured to include a first section and a second section, each of which is comprised of a plurality of memory cells; an lio line switching circuit configured to generate first and second selection signals on the basis of page-size information; and an input/output (i/o) circuit configured to access the first section, the second section, or the first and second sections on the basis of the first and second selection signals, wherein the page-size information includes first and second information.
12/18/14
20140372656
 Data processing device, semiconductor external view inspection device, and data volume increase alleviation method patent thumbnailnew patent Data processing device, semiconductor external view inspection device, and data volume increase alleviation method
Provided is a data processing device with which, when a temporary network congestion occurs, it is possible to avoid a buffer overflow and sustain a process. When a request for retransmission of the same data with respect to a processor element from a buffer occurs continuously a prescribed number of iterations, a data processing device according to the present invention determines that it is possible that a buffer overflow occurs, and suppresses an increase in the volume of data which is accumulated in the buffer (see fig.
12/18/14
20140371555
 System and method for voice control of medical devices patent thumbnailnew patent System and method for voice control of medical devices
A diagnostic system includes a plurality of semiconductor diodes, a multiplexer, and one or more waveguide structures to form an output beam. A lens system communicates some of the output beam onto a part of a user's body comprising blood to perform a measurement.
12/18/14
20140371124
new patent Cleaning liquid for semiconductor device and method for cleaning substrate for semiconductor device
(4)′ water.. .
12/18/14
20140370787
new patent Vacuum-grooved membrane abrasive polishing wafer workholder
Hard-material, flat-surfaced workpieces such as semiconductor wafers or sapphire disks are attached with vacuum to the flexible elastomeric membrane of a wafer carrier that allows one surface of the workpiece to be in conformal abrading contact with a moving flat-surfaced abrasive. The elastomeric membrane external wafer attachment surface has a pattern of recessed vacuum grooves and vacuum is supplied to the grooves to firmly attach the rigid-material silicon wafer in flat-surfaced contact with the membrane.
12/18/14
20140370786
new patent Method for the double-side polishing of a semiconductor wafer
A method of simultaneous double-side polishing of at least one semiconductor material wafer includes disposing each wafer in a respective suitably dimensioned cutout in a carrier plate having a front and rear side. The at least one wafer is polished between an upper polishing plate covered with a first polishing pad and a lower polishing plate covered with a second polishing pad while supplying a polishing agent.
12/18/14
20140370719
new patent Method of focus measurement, exposure apparatus, and method of manufacturing semiconductor device
A method of focus measurement of the embodiment irradiates exposure light from a first direction and projects first and second line-and-space patterns on a substrate. Further, exposure light is irradiated from a second direction and third and fourth line-and-space patterns are projected on the substrate.
12/18/14
20140370713
new patent Method of forming fine patterns of a semiconductor device
A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region, where the widths of the narrow-width patterns are smaller than the resolution limitations in a photolithography process used to make the semiconductor device. The first and second regions may comprise cell array regions, with memory cells in the first region and peripheral circuits for operating the memory cells in the second region.
12/18/14
20140370711
new patent Nitrogen doped amorphous carbon hardmask
Embodiments described herein generally relate to the fabrication of integrated circuits and more particularly to nitrogen doped amorphous carbon layers and processes for depositing nitrogen doped amorphous carbon layers on a semiconductor substrate. In one embodiment, a method of forming a nitrogen doped amorphous carbon layer on a substrate is provided.
12/18/14
20140370706
new patent Semiconductor device and method for manufacturing the same
By using a conductive layer including cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a tft is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of cu can be prevented; thus, a highly reliable semiconductor device can be manufactured.
12/18/14
20140370704
new patent Methods of forming semiconductor devices including low-k dielectric layer
Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate.
12/18/14
20140370702
new patent Semiconductor device and method for fabricating the same
A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment.
12/18/14
20140370701
new patent Method of fabricating semiconductor patterns
A method of fabricating semiconductor patterns includes steps as follows: firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed.
12/18/14
20140370699
new patent Method for fabricating semiconductor device
A method of fabricating a semiconductor device includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench and a second trench, forming a first conductive layer along sidewall surfaces and bottom surface of the first trench and forming a second conductive layer along sidewall surfaces and bottom surface of the second trench, forming a mask pattern on the second conductive layer, the mask pattern filling the second trench and being a bottom anti-reflective coating (barc), and removing the first conductive layer using the mask pattern.. .
12/18/14
20140370695
new patent Method for fabricating a semiconductor device
The present invention relates to a method for fabricating a semiconductor structure comprising a semiconductor layer and a metallic layer, to improve the breakdown voltage properties of the device and reduce leakage currents, the method comprises the steps of a) providing a semiconductor layer comprising defects and/or dislocations; b) removing material at one or more locations of the defects and/or dislocations thereby forming pits in the semiconductor layer, c) passivating the pits, and c) providing the metallic layer over the semiconductor layer. The invention also relates to a corresponding semiconductor structure..
12/18/14
20140370694
new patent Process for the manufacture of a semiconductor device
A method for the manufacture of at least part of a thin-film device including forming one or more indentations in a substrate, preferably a plastic substrate, an indentation having sidewalls and a base; filling at least one of the one or more indentations with a first ink, the first ink having a first material precursor, preferably a first metal-, semiconductor-, or a metal-oxide precursor; and, annealing at least a portion of the first ink such that a surface of the base inside the indentation is dewetted and a narrowed first structure of the first material inside of the indentation is formed.. .
12/18/14
20140370693
new patent Method for manufacturing a semiconductor device having a channel region in a trench
A method of manufacturing a semiconductor device includes forming a semiconductor diode by forming a drift region, forming a first semiconductor region of a first conductivity type in or on the drift region and electrically coupling the first semiconductor region to a first terminal via a first surface of a semiconductor body, etching a trench into the semiconductor body, and forming a channel region of a second conductivity type in the trench and electrically coupling the channel region to the first terminal via the first surface of the semiconductor body. A first side of the channel region adjoins the first semiconductor region..
12/18/14
20140370692
new patent Method of manufacturing semiconductor device, substrate processing apparatus and non-transitory computer-readable recording medium
Provided is a method of manufacturing a semiconductor device, which is capable of increasing the controllability of the concentration of carbon in a film by increasing the yield when a boron carbonitride film or a boron nitride film is formed. The method includes forming a film containing boron, carbon and nitrogen or a film containing boron and nitrogen on the substrate by performing, a predetermined number of times, a cycle including supplying a source gas consisting of boron and a halogen element to a substrate and supplying a reactive gas consisting of carbon, nitrogen and hydrogen to the substrate..
12/18/14
20140370690
new patent Quantum dots made using phosphine
A process is disclosed for producing quantum dots (qds) by reacting one or more core semiconductor precursors with phosphine in the presence of a molecular cluster compound. The core semiconductor precursor(s) provides elements that are incorporated into the qd core semiconductor material.
12/18/14
20140370688
new patent Method for separating and transferring ic chips
A method for separating a multiple number of semiconductor devices or semiconductor integrated circuits from a wafer on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed is provided. The method includes forming a mask pattern on a surface of the wafer, and separating each of the semiconductor devices or semiconductor integrated circuits along the mask pattern formed on the surface of the wafer.
12/18/14
20140370686
new patent Soi structure for signal isolation and linearity
Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer.
12/18/14
20140370685
new patent Method for forming a groove on a surface of flat plate formed of a nitride semiconductor crystal
Provided is a novel method for forming a groove composed of two smooth inclined surfaces on a surface of a flat plate formed of a nitride semiconductor crystal having an a, c, m-axes. In the present invention, a disk-shaped dicing blade is moved along a direction of the a-axis to form first and second inclined surfaces on the surface of the flat plate.
12/18/14
20140370684
new patent Methods for forming sub-resolution features in semiconductor devices
Methods of forming semiconductor devices and features in semiconductor device structures include conducting an anti-spacer process to remove portions of a first mask material to form first openings extending in a first direction. Another anti-spacer process is conducted to remove portions of the first mask material to form second openings extending in a second direction at an angle to the first direction.
12/18/14
20140370683
new patent T-shaped compound semiconductor lateral bipolar transistor on semiconductor-on-insulator
A base region extends upward from a recessed semiconductor surface of a semiconductor material portion present on an insulator. The base region includes a vertical stack of, an extrinsic base region and an intrinsic base region.
12/18/14
20140370682
new patent Method of manufacturing semiconductor device
Extension regions 7 are formed through implantation using offset sidewalls 6a of a footing profile as a mask, and sidewalls 9 are formed on the offset sidewalls 6a so that source and drain regions 10 are formed into the sidewall through implantation, so that the extension regions 7 are made separated away from both edges of the gate, contributing to enlargement in an effective gate length, and dealing with the narrowed gate pitch, without increasing the number of processes.. .
12/18/14
20140370679
new patent Semiconductor device and method of manufacturing the same
A semiconductor device according an aspect of the present disclosure may include an isolation layer formed within a substrate and formed to define an active region, a junction formed in the active region, well regions formed under the isolation layer, and a plug embedded within the substrate between the junction and the well regions and formed extend to a greater depth than the well regions.. .
12/18/14
20140370677
new patent Semiconductor structure and method of forming the same
A method of forming a semiconductor structure includes forming a second iii-v compound layer over a first iii-v compound layer, wherein a carrier channel is located between the first iii-v compound layer and the second iii-v compound layer. The method further includes forming a source feature and a drain feature over the second iii-v compound layer.
12/18/14
20140370676
new patent Semiconductor device, memory system including the same, and method of manufacturing the same
The semiconductor device includes a vertical channel layer formed on a substrate; conductive layer patterns and insulating layer patterns alternately formed around a length of each of the vertical channel layer; and a charge storing layer pattern formed between each of the vertical channel layers and the conductive layer patterns, where each of the charge storing layer patterns is isolated by the insulating layer patterns.. .
12/18/14
20140370675
new patent Semiconductor device
A semiconductor device includes a plurality of conductive layers and a plurality of insulating layers formed alternately with each other, at least one channel layer passing through the plurality of conductive layers and the plurality of insulating layers, and at least one first charge blocking layer surrounding the at least one channel layer, wherein a plurality of first regions, interposed between the at least one channel layer and the plurality of conductive layers, and a plurality of second regions, interposed between the at least one channel layer and the plurality of insulating layers, are alternately defined on the at least one first charge blocking layer, and each of the plurality of first regions has a greater thickness than each of the plurality of second regions.. .
12/18/14
20140370674
new patent Semiconductor device and manufacturing method thereof
A vertical super junction mosfet and a lateral mosfet are integrated on the same semiconductor substrate. The lateral mosfet is electrically isolated from the vertical super junction mosfet by an n-buried isolating layer and an n-diffused isolating layer.
12/18/14
20140370672
new patent Method for fabricating semiconductor device
In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode.
12/18/14
20140370671
new patent Reliable electrical fuse with localized programming and method of making the same
An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact.
12/18/14
20140370670
new patent Semiconductor device and manufacturing method thereof
It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed.
12/18/14
20140370669
new patent Method and system for a gallium nitride vertical jfet with self-aligned source and gate
A semiconductor device includes a iii-nitride substrate, a first iii-nitride epitaxial layer coupled to the iii-nitride substrate and having a mesa, and a second iii-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a iii-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second iii-nitride epitaxial layer and the iii-nitride gate structure..
12/18/14
20140370668
new patent Method of making a transitor
The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack..
12/18/14
20140370667
new patent Tapered nanowire structure with reduced off current
Non-planar semiconductor devices including at least one semiconductor nanowire having a tapered profile which widens from the source side of the device towards the drain side of the device are provided which have reduced gate to drain coupling and therefore reduced gate induced drain tunneling currents.. .
12/18/14
20140370666
new patent Method of making a semiconductor layer having at least two different thicknesses
A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions.. .
12/18/14
20140370665
new patent Power semiconductor device and method for manufacturing such a power semiconductor device
A method for manufacturing a power semiconductor device is disclosed which can include: providing a wafer of a first conductivity type; and applying on a second main side of the wafer at least one of a dopant of the first conductivity type for forming a layer of the first conductivity type and a dopant of a second conductivity type for forming a layer of the second conductivity type. A titanium layer with a metal having a melting point above 1300° c.
12/18/14
20140370663
new patent Method for producing a semiconductor module
A semiconductor module is produced by providing a circuit carrier having a metallization, an electrically conductive wire and a bonding device. With the aid of the bonding device, a bonding connection is produced between the metallization and a first section of the wire.
12/18/14
20140370662
new patent Copper post solder bumps on substrates
A method comprises forming semiconductor flip chip interconnects having electrical connecting pads and electrically conductive posts terminating in distal ends operatively associated with the pads. We solder bump the distal ends by injection molding, mask the posts on the pads with a mask having a plurality of through hole reservoirs and align the reservoirs in the mask to be substantially concentric with the distal ends.
12/18/14
20140370661
new patent Dual lead frame semiconductor package and method of manufacture
A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip.
12/18/14
20140370660
new patent Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate.
12/18/14
20140370659
new patent Singulation apparatus and method
A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon.
12/18/14
20140370657
new patent Method of manufacturing semiconductor device
In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed.
12/18/14
20140370656
new patent Semiconductor device and manufacturing method thereof
A semiconductor device using an oxide semiconductor, with stable electric characteristics and high reliability. In a process for manufacturing a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation is performed by heat treatment and oxygen doping treatment is performed.
12/18/14
20140370655
new patent Gate insulator loss free etch-stop oxide thin film transistor
A method is provided for fabricating a thin-film transistor (tft). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator.
12/18/14
20140370654
new patent Semiconductor device and manufacturing method thereof
A step for forming an island-shaped semiconductor layer of a semiconductor device used in a display device is omitted in order to manufacture the semiconductor device with high productivity and low cost. The semiconductor device is manufactured through four photolithography processes: four steps for forming a gate electrode, for forming a source electrode and a drain electrode, for forming a contact hole, and for forming a pixel electrode.
12/18/14
20140370653
new patent Sputtering target and method for manufacturing semiconductor device
An object is to provide a deposition technique for depositing an oxide semiconductor film. Another object is to provide a method for manufacturing a highly reliable semiconductor element using the oxide semiconductor film.
12/18/14
20140370651
new patent Method of manufacturing semiconductor device
A semiconductor device includes a substrate made of a semiconductor material, an n-type semiconductor layer arranged on a portion of one principal surface of the substrate, and a p-type semiconductor layer arranged on a portion of the one principal surface of the substrate, the portion not provided with the n-type semiconductor layer. The n-type semiconductor layer includes a portion located right above the p-type semiconductor layer..
12/18/14
20140370650
new patent Monolithically isled back contact back junction solar cells using bulk wafers
According to one aspect of the disclosed subject matter, a method for forming a monolithically isled back contact back junction solar cell using bulk wafers is provided. Emitter and base contact regions are formed on a backside of a semiconductor wafer having a light receiving frontside and a backside opposite said frontside.
12/18/14
20140370647
new patent Polycrystalline cdte thin film semiconductor photovoltaic cell structures for use in solar electricity generation
Solar cell structures formed using molecular beam epitaxy (mbe) that can achieve improved power efficiencies in relation to prior art thin film solar cell structures are provided. A reverse p-n junction solar cell device and methods for forming the reverse p-n junction solar cell device using mbe are described.
12/18/14
20140370645
new patent Method of manufacturing semiconductor device
An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, in an n-type semiconductor substrate, a p-type well as a p-type semiconductor region forming a part of a photodiode is formed and a gate electrode of a transfer transistor is formed.
12/18/14
20140370644
new patent Method of manufacturing solar cell
A method of manufacturing a solar cell including a crystalline semiconductor substrate, includes: etching or washing at least part of a first principal surface of the substrate by treatment with an aqueous alkaline solution; and depositing a p-type semiconductor layer containing boron on at least part of a second principal surface of the substrate before the treatment with the aqueous alkaline solution.. .
12/18/14
20140370642
new patent Process of forming a back side illumination image sensor
A process of forming a back side illumination (bsi) image sensor is disclosed. An n-type implant is formed in a semiconductor substrate, and a p-type implant region, surrounding n-type in each pixel, is formed in the n-type implant such that in cross sectional view an n-type implant region is sandwiched between the two p-type implant regions.
12/18/14
20140370639
new patent Micro electro mechanical system, semiconductor device, and manufacturing method thereof
The present invention provides a mems and a sensor having the mems which can be formed without a process of etching a sacrifice layer. The mems and the sensor having the mems are formed by forming an interspace using a spacer layer.
12/18/14
20140370634
new patent Method for fabricating nitride semiconductor thin film and method for fabricating nitride semiconductor device using the same
A method for fabricating a nitride semiconductor thin film includes preparing a first nitride single crystal layer doped with an n-type impurity. A plurality of etch pits are formed in a surface of the first nitride single crystal layer by applying an etching gas thereto.
12/18/14
20140370631
new patent Removal of 3d semiconductor structures by dry etching
Various embodiments include methods of fabricating a semiconductor device that include providing a plurality of nanostructures extending away from a support, forming a flowable material layer between the nanostructures, forming a patterned mask over a first portion of the flowable material and the first portion of the plurality of nanostructures, such that a second portion of the flowable material and a second portion of the plurality of nanostructures are not located under the patterned mask and etching the second portion of the flowable material and the second portion of the plurality of nanostructures to remove the second portion of the flowable material and the second portion of the plurality of nanostructures to leave the first portion of the flowable material and the first portion of the plurality of nanostructures unetched.. .
12/18/14
20140370630
new patent Method for manufacturing semiconductor light emitting device
A semiconductor light emitting device having high reliability and excellent light distribution characteristics can be provided with an n-electrode arranged on a light extraction surface on the side opposite to the surface whereupon a semiconductor stack is mounted on a substrate. A plurality of convexes are arranged on a first convex region and a second convex region on the light extraction surface.
12/18/14
20140370628
new patent Substrate processing apparatus, semiconductor device manufacturing method, substrate processing method, and recording medium
According to the present disclosure, it is possible to prevent particles from being generated and to improve substrate processing quality. A substrate processing apparatus includes cassette mounting unit on which process substrate cassette and dummy substrate cassette are mounted, the process substrate cassette being configured to accommodate a plurality of process substrates, and the dummy substrate cassette being configured to accommodate a plurality of dummy substrates, process chamber configured to process the process substrates and the dummy substrates, substrate support unit installed within the process chamber and provided with a plurality of substrate mounting portions where the process substrates and the dummy substrates are mounted, transfer unit configured to transfer the process substrates and the dummy substrates between the cassette mounting unit and the process chamber, and control unit configured to control substrate processing and to transfer processing of the process substrates and the dummy substrates..
12/18/14
20140370627
new patent Monitoring laser processing of semiconductors by raman spectroscopy
A raman probe is used to detect crystal structure of a substrate undergoing thermal processing in a thermal processing system. The raman probe may be coupled to a targeting system of a laser thermal processing system.
12/18/14
20140370624
new patent Wafer alignment and bonding tool for 3d integration
A bonding apparatus for 3d integration may include a plurality of infrared microscopes that emit and receive infrared light for imaging, a first bonding chuck that holds a first semiconductor structure, and a second bonding chuck that holds a second semiconductor structure, whereby the second bonding chuck has a plurality of openings that are transparent to the received infrared light. A force pin is coupled to the first bonding chuck for applying a predetermined force to the first semiconductor structure for bonding to the second semiconductor structure.
12/18/14
20140370447
new patent Semiconductor device resolution enhancement by etching multiple sides of a mask
A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions.
12/18/14
20140370445
new patent Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes a photolithography process having steps of a developing solution immersing process. The steps of the developing solution immersing process includes step (a) of dropping a developing solution on a silicon carbide semiconductor substrate and forming a developing solution film so as to have a film thickness of more than 6 μm and step (b) of reducing the film thickness of the developing solution film to 6 μm or less..
12/18/14
20140370424
new patent Substrate with multilayer reflective film, reflective mask blank for euv lithography, method of manufacturing reflective mask for euv lithography and method of manufacturing semiconductor device
An object of the present invention is to provide a substrate with a multilayer reflective film and the like used in the manufacturing of a reflective mask blank for euv lithography which is to be subjected to dry etching with a cl-based gas, wherein in the substrate with the multilayer reflective film, the loss of protective films by the dry etching and subsequent wet cleaning is very limited. The present invention is a substrate with a multilayer reflective film used in the manufacturing of a reflective mask blank for euv lithography, comprising a substrate, a multilayer reflective film disposed on the substrate to reflect euv light, and a protective film disposed on the multilayer reflective film to protect the multilayer reflective film, the protective film includes an alloy containing at least two metals, the alloy being an all-proportional solid solution..
12/18/14
20140370423
new patent Extreme ultraviolet (euv) radiation pellicle formation method
An extreme ultraviolet (euv) photolithography pellicle with at least 70% transmissivity to euv can be formed from a layer of semiconductor material applied to a substrate. The bottom surface of the layer can be exposed by forming support structure(s) from the substrate.
12/18/14
20140370381
new patent Secondary battery
A secondary battery includes: a negative electrode; a positive electrode containing a p-type semiconductor material; and an isolation layer configured to isolate the negative electrode from the positive electrode and including a hole transmission member. The isolation layer is layered by being applied to at least one of the negative electrode and the positive electrode.
12/18/14
20140370360
new patent Secondary battery
A secondary battery includes a first electrode, a second electrode, an ion transmission member in contact with the first electrode and the second electrode, and a hole transmission member in contact with the first electrode and the second electrode. Suitably, the first electrode contains a composite oxide.
12/18/14
20140370322
new patent Shell activated sintering of core-shell particles
A sintered structure and method for forming it are disclosed. The method includes obtaining core-shell particles having a core material and a shell material, forming the particles into a powder compact, and annealing the powder compact at an annealing temperature.
12/18/14
20140370241
new patent Method for making glass substrate for display, glass substrate and display panel
A method for manufacturing a glass substrate for a display includes a step of producing a glass substrate and a step of performing a surface treatment on one glass surface of major surfaces of the glass substrate to form surface unevenness. The surface treatment is performed such that protruded portions having a height of 1 nm or more from the surface roughness central plane of the surface unevenness are dispersedly provided on the glass surface after the surface treatment and the area ratio of the protruded portions with respect to the area of the glass surface is 0.5-10%.
12/18/14
20140370114
new patent Homopolymer nanoparticles by self-emulsion polymerization reaction and preparation method thereof
Disclosed herein is a preparation method of homopolymer nanoparticles without using a surfactant. The homopolymer nanoparticles prepared thereby are expected to be widely used not only as a template of a semiconductor metal oxide, a drug delivery system (dds), an electron transport layer (etl), and a seed having vertical structural shape, but also in a high precision field such as replacement of an organic device polystyrene bead film..


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Semiconductor topics: Semiconductor, Semiconductor Substrate, Semiconductor Device, Semiconductor Material, Electric Conversion, Conductive Layer, Molybdenum, Camera Module, Semiconductor Devices, Semiconductors, Integrated Circuit, Surfactant, Photoelectric Conversion, Electronic Device, Transparent Conductive Oxide

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