|| List of recent Semiconductor-related patents
| Detection arrangement|
There is provided a detection arrangement for detecting an attack to internal signals in a semiconductor device. The detection arrangement comprises a first input terminal, a second input terminal, and a comparison unit.
| Access arbitration module and system for semiconductor fabrication equipment and methods for using and operating the same|
An access arbitration module includes a plurality of active component communication ports for communicating with a plurality of active components, and includes a passive component communication port for communicating with a passive component. The access arbitration module also includes switching logic defined to control transmission of access communication protocol signals between each of the plurality of active component communication ports and the passive component communication port, such that an authorized one of the plurality of active component communication ports is connected in communication with the passive component communication port at a given time, and such that non-authorized ones of the plurality of active component communication ports are prevented from communication with the passive component communication port at the given time..
| Interconnect structures and methods for back end of the line integration|
A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer.
| System and method for modifying a data set of a photomask|
The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.. .
| Memory controller, semiconductor storage device, and memory control method|
According to one embodiment, a memory controller including a syndrome calculation unit which calculates syndrome based on code word which have the ability to correct t bits, an error locator polynomial calculation unit, and a chien search unit, wherein the chien search unit includes a root shift block which shifts all roots, a division block which divides the output from the root shift block by a predetermined polynomial, of which the order is smaller than t, and substitution block which substitutes elements into the remainder polynomial to examine if they are the roots of the remainder, and wherein the predetermined polynomial has at least one root which value is the same as one of the substituted elements.. .
| Semiconductor storage device and memory controller|
According to an embodiment, a semiconductor storage device includes a memory, an encoding unit that generates a parity, and a decoding unit that includes a syndrome calculating unit, an error position polynomial calculating unit, and an error searching and correcting unit, and performs an error correcting process based on data and the parity read from the memory. At the time of performing a compaction process, a process of the error searching and correcting unit is not performed, when the number of error bits acquired by an error position polynomial is equal to or less than a first threshold value based on valid data..
| Semiconductor memory device and method of operating the same|
Semiconductor memory device and method of operating same includes reading data stored in memory cells of a page; performing an error correction loop (ecc loop) including performing an error checking and correcting operation (ecc) on the read data; determining a number of bit errors in the read data; and when the number of bit errors is greater than a maximum number of correctable bits, incrementing the number of ecc iterations (ecc count) and increasing the maximum number of correctable bits; storing the ecc count until the number of bit errors is less than the maximum number of correctable bits; and programming corrected data to the memory cells when the stored ecc count is more than preset number.. .
| Memory controller and semiconductor storage device|
According to one embodiment, a decoder of a memory controller includes: a syndrome calculating unit configured to calculate a syndrome based upon a code word read from the memory; an error locator polynomial generating unit configured to generate an error locator polynomial based upon the syndrome, and to obtain a number of errors based upon the generated error locator polynomial; and an error location calculating unit configured to calculate an error location based upon the error locator polynomial, wherein the process of the error location calculating unit is not executed, when the number of errors is not less than the maximum number of bits that can be corrected by the error locator polynomial generating unit.. .
| Semiconductor test system and method|
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel.
| Semiconductor device and memory device|
A memory device includes a command decoder for generating a test selection code and a test setup data by decoding an external command and an external address, a non-volatile memory for storing an internal setup data, a counter for generating an internal selection code by counting a clock, a first selector for selecting the test selection code during a test mode operation, selecting the internal selection code during a boot-up operation, and transferring the selected selection code through a selection code transfer bus, a second selector for selecting the test setup data during the test mode operation, selecting the internal setup data that is outputted from the non-volatile memory during the boot-up operation, and transferring the selected selection code through a setup data transfer bus; and setup circuits for performing a setup operation based on the information transferred through the selection code transfer bus and the setup data transfer bus.. .
| Circuit system and semiconductor device|
A circuit system includes: a plurality of memory blocks; a power supply circuit configured to supply operating power and substrate power to the plurality of memory blocks; a plurality of first power supply switches configured to control whether or not the operating power is supplied from the power supply circuit to the plurality of memory blocks; and a control circuit configured to control the power supply circuit and the plurality of first power supply switches, wherein the control circuit changes a voltage of the operating power to be supplied by the power supply circuit and a voltage of the substrate power to be supplied by the power supply circuit, based on a state of whether the first power supply switches are in a supplying state or a blocking state.. .
| Semiconductor device and electronic device|
To reduce a variation in the electrical characteristics of a transistor. A potential generated by a voltage converter circuit is applied to a back gate of a transistor included in a voltage conversion block.
| Semiconductor memory device and method of operating the same|
A semiconductor memory device is operated by, inter alia, performing least significant bit programs for pages in a first page group, performing least significant bit programs for pages in a second page group, and performing most significant bit programs for the pages in the first page group. The distance between the second page group and the common source line is greater than that between the first page group and the common source line..
| Semiconductor device and memory test method|
An address range of an l2 cache is divided into sets of a predetermined number of ways. A ram-bist pattern generating unit generates a memory address corresponding to a way, a test pattern, and an expected value with respect to the test pattern.
| Refresh control circuit and semiconductor memory device including the same|
A refresh control circuit includes an internal chip information unit configured to provide internal chip information related to a retention characteristic of a memory cell, a mode information modification unit configured to output modified mode information based on the internal chip information, wherein the modified mode information represent a number of memory banks for refresh operation, and a selection signal activation unit configured to activate one or more of selection signals for selecting corresponding one or more of the memory banks in response to the modified mode information.. .
| Semiconductor memory device|
According to one embodiment, a semiconductor memory device includes a first memory circuit and a first controller. The first memory circuit includes a register in which a read page size is stored, and a memory cell array.
| Memory system|
According to one embodiment, a memory system includes a nonvolatile semiconductor storage device, a first storage module, a second storage module, a controller, a random number generator, and a randomizing module. The first storage module stores a plurality of management data.
| Semiconductor device and operation method thereof|
A semiconductor device includes a characteristic code storage unit configured to store signal transfer characteristic information input through a given pad and output a control code corresponding to the signal transfer characteristic information, and a characteristic reflection unit configured to reflect the signal transfer characteristic information in an input signal input through the given pad, in response to the control code, and to output the reflected input signal.. .
| Synaptic semiconductor device and operation method thereof|
Disclosed is a semiconductor device used to embody a neuromorphic computation system and operation method thereof. By comprising a floating body as a short-term memory means electrically isolated from the surroundings and a long-term memory means formed at one side of the floating body not formed of a source, a drain and a gate, a low power synaptic semiconductor device is provided, which can be mimic not only the short-term memory in a nervous system of a living body by an impact ionization, but also the short- and long-term memory transition property and the causal inference property of a living body due to the time difference of signals of the pre- and post-synaptic neurons..
| Systems and methods for dynamic semiconductor process scheduling|
Embodiments of the present disclosure can help increase throughput and reduce resource conflicts and delays in semiconductor processing tools. An exemplary method according to various aspects of the present disclosure includes analyzing, by a computer program operating on a computer system, a plurality of expected times to complete each of a respective plurality of actions to be performed by a semiconductor processing tool, the semiconductor processing tool including a first process module and a second process module..
| Thermosetting light-reflective resin composition, method for preparing the same, optical semiconductor element-mounted reflector produced therefrom, and optical semiconductor device comprising the same|
Disclosed are a thermosetting light-reflective resin composition, a method for preparing the same, an optical semiconductor element-mounted reflector produced therefrom, and an optical semiconductor device including the same. More specifically, disclosed are a thermosetting light-reflective resin composition which includes a polyhydric polyol having two or more hydroxyl groups and thus exhibits superior discoloration resistance and entails little deterioration in reflectance, a method for preparing the same, an optical semiconductor element-mounted reflector produced therefrom and an optical semiconductor device including the same..
| Lead-free glass for semiconductor encapsulation and encapsulator for semiconductor encapsulation|
The present invention provides a lead-free glass for semiconductor encapsulation, which can encapsulate semiconductor devices at a low temperature and has an excellent acid durability, and an encapsulator for semiconductor encapsulation made of the glass. The glass comprises, as a glass composition, from 46 to 60% of sio2, from 0 to 6% of al2o3, from 13 to 30% of b2o3, from 0 to 10% of mgo, from 0 to 10% of cao, from 0 to 20% of zno, from 9 to 25% of li2o, from 0 to 15% of na2o, from 0 to 7% of k2o, and from 0 to 8% of tio2, in terms of % by mol, wherein a ratio by mol of li2o to (li2o+na2o+k2o) is in the range from 0.48 to 1.00..
| Elastic membrane and substrate holding apparatus|
An elastic membrane is used in a substrate holding apparatus for holding a substrate such as a semiconductor wafer and pressing the substrate against a polishing surface. The elastic membrane includes a plurality of concentrically circumferential walls configured to define a plurality of pressurizing areas for pressing the substrate.
| Method of forming a photoresist layer|
A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer.
| Methods and apparatus for forming tantalum silicate layers on germanium or iii-v semiconductor devices|
Described are apparatus and methods for forming tantalum silicate layers on germanium or iii-v materials. Such tantalum silicate layers may have si/(ta+si) atomic ratios from about 0.01 to about 0.15.
| Method for manufacturing semiconductor device and substrate processing apparatus|
To form an insulating film with extremely low concentration of impurities such as carbon, hydrogen, nitrogen, chlorine, etc in a film. There are provided the steps of forming a specific element-containing layer on a substrate by supplying source gas containing a specific element into a processing container in which the substrate is accommodated; changing the specific element-containing layer into a nitride layer, by activating and supplying gas containing nitrogen into the processing container; and changing the nitride layer into an oxide layer or an oxynitride layer, by activating and supplying gas containing oxygen into the processing container; with this cycle set as one cycle and performed for at least one or more times..
| Method of bonding layers for thin film deposition|
A method of bonding together at least two aligned layers, at least one having an active surface, in a semiconductor manufacturing process using a holding member having spaced sections. Each layer has a bonding surface opposite a back surface.
| Texturing of monocrystalline semiconductor substrates to reduce incident light reflectance|
Monocrystalline semiconductor substrates are textured with alkaline solutions to form pyramid structures on their surfaces to reduce incident light reflectance and improve light absorption of the wafers. The alkaline baths include hydantoin compounds and derivatives thereof in combination with alkoxylated glycols to inhibit the formation of flat areas between pyramid structures to improve the light absorption..
| Protective coating for a plasma processing chamber part and a method of use|
A flexible polymer or elastomer coated rf return strap to be used in a plasma chamber to protect the rf strap from plasma generated radicals such as fluorine and oxygen radicals, and a method of processing a semiconductor substrate with reduced particle contamination in a plasma processing apparatus. The coated rf strap minimizes particle generation and exhibits lower erosion rates than an uncoated base component.
| Method for manufacturing semiconductor device|
According to one embodiment, a method for manufacturing a semiconductor device includes forming a film having different filling properties dependent on space width above the patterning film to cover the first line patterns and the second line patterns to form the film on the first line patterns and on the first inter-line pattern space while making a cavity in the first inter-line pattern space and to form the film on at least a bottom portion of the second inter-line pattern space and a side wall of each of the second line patterns. The method includes performing etch-back of the film to remove the film on the first line patterns and on the first inter-line pattern space while causing the film to remain on at least the side wall of the second line patterns..
| Trench formation method and method for manufacturing semiconductor device|
| Selective fin cut process|
A process is provided for selective removal of one or more unwanted fins during finfet device fabrication. In one aspect, the process includes: providing a conformal protective layer over multiple fin structures on a substrate; patterning one or more openings over the unwanted fin structure(s); and removing at least a top portion of the unwanted fin structure(s) exposed through the opening(s), the removing including removing at least a portion of the conformal protective layer over the unwanted fin structure(s) exposed through the opening(s).
| Pattern structures in semiconductor devices and methods of forming pattern structures in semiconductor devices|
A pattern structure in a semiconductor device includes an extending line and a pad connected with an end portion of the extending line. The pad may have a width that is larger than a width of the extending line.
| Methods and systems for low resistance contact formation|
Methods for improving contact resistance, for example, to a semiconductor region such as a source or a drain region, are disclosed. The methods can include depositing a layer on a substrate, wherein the layer can include a first element to form a silicide with the substrate and a second element to lower a contact resistance between the silicide and the substrate.
| Method of semiconductor integrated circuit fabrication|
A method of fabricating a semiconductor integrated circuit (ic) is disclosed. The method includes providing a substrate.
| High performance on-chip vertical coaxial cable, method of manufacture and design structure|
A high performance on-chip vertical coaxial cable structure, method of manufacturing and design structure thereof is provided. The coaxial cable structure includes an inner conductor and an insulating material that coaxially surrounds the inner conductor.
| Manufacturing method of semiconductor storage device|
In a manufacturing method, gate electrode materials and a hard-mask material are deposited above a substrate. First mandrels are formed on the hard-mask material in a region of cell array.
| Replacement metal gate semiconductor device formation using low resistivity metals|
Embodiments of the present invention relate to approaches for forming rmg finfet semiconductor devices using a low-resistivity metal (e.g., w) as an alternate gap fill metal. Specifically, the semiconductor will typically comprise a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels).
| Method of forming nonvolatile memory device|
A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.. .
| Semiconductor device and method for fabricating the same|
A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.. .
| Method of forming a material layer in a semiconductor structure|
A method comprises depositing a first portion of a first material layer on a semiconductor structure. A first run of a post-treatment process is performed for modifying at least the first portion of the first material layer.
| Partially-blocked well implant to improve diode ideality with sige anode|
A method of manufacturing a semiconductor device is disclosed. A p-type substrate is doped to form an n-well in a selected portion of a p-type substrate adjacent an anode region of the substrate.
| Manufacturing method of semiconductor device and semiconductor manufacturing apparatus|
According to one embodiment, a manufacturing method of a semiconductor device includes forming a crystal film on a semiconductor substrate by irradiating the semiconductor substrate with a first microwave, obtained by providing frequency modulation or phase modulation of a first carrier wave which is a sine wave with a first frequency, using a first signal wave which is a sine wave or a pulse wave with a third frequency lower than a first frequency, and irradiating the semiconductor substrate with a second microwave, obtained by providing frequency modulation or phase modulation of a second carrier wave, which is a sine wave with a second frequency higher than the first frequency, using a second signal wave which is a sine wave or a pulse wave with a fourth frequency lower than the second frequency.. .
| Group iii-v substrate material with particular crystallographic features and methods of making|
A method of forming a semiconductor substrate including providing a base substrate including a semiconductor material, and forming a first semiconductor layer overlying the base substrate having a group 13-15 material via hydride vapor phase epitaxy (hvpe), the first semiconductor layer having an upper surface having a n-face orientation.. .
| Method for manufacturing silicon carbide semiconductor device|
Gas containing si, gas containing c and gas containing cl are introduced into a reacting furnace. Sic epitaxial film is grown on the surface of a 4h—sic substrate by cvd in a gas atmosphere including raw material gas, additive gas, doping gas and carrier gas.
| Methods and systems for low resistance contact formation|
Methods for improving contact resistance, for example, to a semiconductor region such as a source or a drain region, are disclosed. The methods can include exposing the substrate to an activated hydrogen species to remove contaminant layers such as native oxide layers followed by exposing the substrate to plasma activated dopant species to passivate the surface.
| Method for forming a buried dielectric layer underneath a semiconductor fin|
Disclosed are methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device. In some embodiments, the method may include providing a substrate comprising a bulk semiconductor material and forming at least two trenches in the substrate, thereby forming at least one fin.
| Methods of manufacturing a semiconductor device|
An alignment mark is formed on a substrate including a first region and a second region. The alignment mark is formed in the second region.
| High breakdown voltage embedded mim capacitor structure|
Methods and devices related to a plurality of high breakdown voltage embedded capacitors are presented. A semiconductor device may include gate material embedded in an insulator, a plurality of metal contacts, and a plurality of capacitors.
| Allotropic or morphologic change in silicon induced by electromagnetic radiation for resistance turning of integrated circuits|
An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region.
| Nonvolatile semiconductor memory device and manufacturing method thereof|
In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an off current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers.
| Large dimension device and method of manufacturing same in gate last process|
An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a capacitor having a doped region disposed in a semiconductor substrate, a dielectric layer disposed over the doped region, and an electrode disposed over the dielectric layer.
| Semiconductor devices including a support for an electrode and methods of forming semiconductor devices including a support for an electrode|
Semiconductor devices are provided. Each of the semiconductor devices may include a plurality of electrodes.
| Methods of fabricating a semiconductor device with capacitors using mold structure and protection layer|
A method of fabricating a semiconductor device with capacitors may include forming a mold structure on a lower structure, patterning the mold structure to form a plurality of holes exposing the lower structure, forming a protection layer on sidewalls of the mold structure exposed by the holes, forming lower electrodes in the holes provided with the protection layer, removing the mold structure to expose the protection layer, removing the protection layer to expose sidewalls of the lower electrodes, and sequentially forming a dielectric film and an upper electrode on the lower electrodes.. .
| Oxygen scavenging spacer for a gate electrode|
At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer.
| Method of making a finfet device|
A finfet device is fabricated by first receiving a finfet precursor. The finfet precursor includes a substrate and fin structures on the substrate.
| Ultra-high voltage n-type-metal-oxide-semiconductor (uhv nmos) device and methods of manufacturing the same|
An ultra-high voltage n-type-metal-oxide-semiconductor (uhv nmos) device with improved performance and methods of manufacturing the same are provided. The uhv nmos includes a substrate of p-type material; a first high-voltage n-well (hvnw) region disposed in a portion of the substrate; a source and bulk p-well (pw) adjacent to one side of the first hvnw region, and the source and bulk pw comprising a source and a bulk; a gate extended from the source and bulk pw to a portion of the first hvnw region, and a drain disposed within another portion of the first hvnw region that is opposite to the gate; a p-top layer disposed within the first hvnw region, the p-top layer positioned between the drain and the source and bulk pw; and an n-type implant layer formed on the p-top layer..
| Method for manufacturing finfet|
Designs and fabrication of a finfet are provided. In one implementation, the fabrication can include forming a dielectric stripe on a substrate; implanting ions to the substrate by using the dielectric stripe as a mask so as to convert a surface layer of the substrate to an amorphous layer; forming an amorphous semiconductor layer on the substrate covering the dielectric stripe and recrystallizing each of the amorphous layer and the amorphous semiconductor layer to be a monocrystalline layer; processing regions beside two ends of the dielectric stripe to form a protective layer, the regions being predesigned as source and drain regions; forming recrystallized semiconductor spacers at two sides of the dielectric stripe uncovered by the protective layer, and forming recrystallized semiconductor blocks on regions covered by the protective layer; removing the dielectric stripe between the spacers so that the spacers can be formed as fin bodies..
| Low loss sic mosfet|
A vertical multiple implanted silicon carbide power mosfet (vmimosfet) includes a first conductivity semiconductor substrate, a first conductivity semiconductor drift layer on the top of the substrate, a multitude of second conductivity layers implanted in the drift layer. The body layer is where the channel is formed.
| Dram with dual level word lines|
A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer.
| Method for manufacturing a semiconductor device|
The improvement of the reliability of a semiconductor device having a split gate type monos memory is implemented. An ono film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode.
| Fabrication method for semiconductor devices|
A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon.
| Embedded planar source/drain stressors for a finfet including a plurality of fins|
Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed.
| Chip package and fabrication method thereof|
An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region; and an auxiliary pattern having a hollow pattern formed in the spacing layer, a material pattern located between the spacing layer and the device region, or combinations thereof.. .
| Method of manufacturing semiconductor device|
In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip..
| Methods of treating a semiconductor layer|
Methods for treating a semiconductor layer including a semiconductor material are presented. A method includes contacting at least a portion of the semiconductor material with a passivating agent.
| Method for manufacturing solar cell|
A method for manufacturing a solar cell includes performing a dry etching process to form a textured surface including a plurality of minute protrusions on a first surface of a semiconductor substrate, performing a first cleansing process for removing damaged portions of surfaces of the minute protrusions using a basic chemical and removing impurities adsorbed on the surfaces of the minute protrusions, performing a second cleansing process for removing impurities remaining or again adsorbed on the surfaces of the minute protrusions using an acid chemical after performing the first cleansing process, and forming an emitter region at the first surface of the semiconductor substrate.. .
| Method of manufacturing solid-state image sensor|
A method of manufacturing a solid-state image sensor having a pixel region and a peripheral circuit region, includes forming an oxide film on a semiconductor substrate, forming an insulating film on the oxide film, forming a first opening in the insulating film and the oxide film in the peripheral circuit region, forming a trench in the semiconductor substrate in the peripheral circuit region by etching the semiconductor substrate through the first opening using the insulating film as a mask, forming a second opening in the insulating film to penetrate through the insulating film in the pixel region and to reach a predetermined depth of the oxide film, and forming insulators in the trench and the second opening.. .
| Thin film transistor array panel and manufacturing method thereof|
A thin film transistor array panel includes: a substrate including a display area and a drive region in which a driving chip for transmitting a driving signal to the pixels is located; a gate line in the display area; a storage electrode line; a gate driving pad coupled to the driving chip; a gate insulating layer; a first semiconductor layer on the gate insulating layer and overlapped with a gate electrode protruding from the gate line; a second semiconductor layer formed on the gate insulating layer and overlapped with a sustain electrode protruding from the storage electrode line; a data line crossing the gate line in an insulated manner and a drain electrode separated from the data line; and a pixel electrode coupled to the drain electrode, and the drain electrode comprises a drain bar facing the source electrode, and a drain extender overlapped with the second semiconductor layer.. .
| Supporting substrate for preparing semiconductor light-emitting device and semiconductor light-emitting device using supporting substrates|
A method may be provided for preparing a semiconductor light-emitting device. The method may include: preparing a first wafer in which a semiconductor multi-layered light-emitting structure is disposed on an upper part of an initial substrate; preparing a second wafer which is a supporting substrate; bonding the second wafer on an upper part of the first wafer; separating the initial substrate of the first wafer from a result of the bonding; and fabricating a single-chip by severing a result of the passivation.
| Method for making light emitting diode|
A method for making a light emitting diode includes the following steps. A first epitaxial substrate having a first epitaxial growth surface is provided.
| Leakage measurement of through silicon vias|
A method of testing a semiconductor substrate having through substrate vias for current leakage which includes: forming a current leakage measurement structure that includes substrate contacts, sensing circuits to sense current leakage from the through substrate vias, the sensing circuits connected to the through substrate vias and to the substrate contacts so that there is a one-to-one correspondence of a substrate contact and sensing circuit to each through substrate via, and a built-in self test (bist) engine to sense one of the through substrate vias for current leakage. A reference current is applied to the sensing circuits to set a current leakage threshold for the through substrate vias.
| Imprint apparatus, imprint method, and manufacturing method of semiconductor device|
An imprint apparatus according to embodiments includes a stage, a dropping unit that drops resist, an imprinting unit that presses a circuit pattern of a template against the resist on a transfer target substrate, an underlying position detecting unit, a correcting unit, and a dropping position control unit. The underlying position detecting unit detects a position of an underlying pattern on the transfer target substrate.
| Method and system for determining overlap process windows in semiconductors by inspection techniques|
The formation of overlap areas in sophisticated semiconductor devices is a critical aspect which may not be efficiently evaluated on the basis of conventional measurement and design strategies. For this reason, the present disclosure provides measurement techniques and systems in which overlying device patterns are transformed into the same material layer, thereby forming a combined pattern which is accessible by well-established defect inspection techniques.
| Semiconductor manufacturing process system and method|
According to one embodiment, a wafer processing device includes a processed number counting unit that counts a number of processed wafers, and a maintenance post-processing unit that executes a dummy lot process and a qc lot process after a maintenance process. A wafer preparation device prepares the dummy lot and the qc lot, when a first processed number is counted by the processed number counting unit.
| In-line metrology system|
A metrology system for gauging and spatially mapping a semiconductor material on a substrate can be used in controlling deposition and thermal activation processes.. .
| Semiconductor apparatus having tsv and testing method thereof|
A semiconductor apparatus includes: a through-silicon via (tsv) formed in a silicon substrate; a first insulating layer formed to surround side and bottom portions of the tsv such that the tsv is isolated from the silicon substrate; a first conductive layer interposed between the first insulating layer and the silicon substrate and formed outside the tsv to surround the tsv.. .
| Manufacturing method of semiconductor device|
According to one embodiment, a manufacturing method includes forming a desired pattern containing an uneven pattern on a substrate, subjecting the surface of the desired pattern to a water repellent treatment, forming a resist film on the desired pattern, performing an exposure treatment to expose the uneven pattern, rinsing the substrate with water, and drying the substrate.. .
| Method and apparatus for developing process|
The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a material layer formed thereon; depositing a photoresist layer on the material layer, the photoresist layer having a vertical dimension; exposing a region of the photoresist layer to radiation, the exposed region having a horizontal dimension, wherein a first ratio of the vertical dimension to the horizontal dimension exceeds a predetermined ratio; and developing the photoresist layer to remove the exposed region at least in part through applying a developer solution containing a first chemical and a second chemical, wherein: the first chemical is configured to dissolve the exposed region of the photoresist layer through a chemical reaction; the second chemical is configured to enhance flow of the first chemical that comes into contact with the photoresist layer; and an optimized second ratio exists between the first chemical and the second chemical..
| Chuck and semiconductor process using the same|
An apparatus of semiconductor process including a chuck and a vacuum source is provided. The chuck has a plurality of holes for holding a semiconductor substrate, and the vacuum source is used for providing vacuum suction through the holes to make the semiconductor substrate be subjected to varied suction intensities according to a warpage level thereof..
| Exposure apparatus, exposure method, and method of manufacturing semiconductor device|
An exposure apparatus according to an embodiment controls the positioning between layers using an alignment correction value calculated on the basis of lower layer position information of a lower-layer-side pattern and upper layer position information of an upper-layer-side pattern. The lower layer position information includes alignment data, a focus map, and a correction value which is set on the basis of the previous substrate.
| Photomask and method for forming pattern of semiconductor device using the same|
A semiconductor device includes a cell mask pattern disposed in a cell region of a mask substrate and a vernier mask pattern disposed in a vernier region of the mask substrate. The vernier mask pattern includes a variable mask pattern portion to transfer a different shape of pattern depending on the magnitude of exposure energy..
| Base film and pressure-sensitive adhesive sheet provided therewith|
The base film of the invention is a base film of a pressure-sensitive adhesive sheet for laminating onto a semiconductor wafer composed of: (a) a layer of a cured product in which a composition including a polyether polyol urethan(meth)acrylate oligomer and an energy ray curable monomer is cured by energy ray irradiation, and (b) a thermoplastic resin layer. The present invention, by using a surface protection sheet, protects a circuit side of a wafer with bumps, prevents collapse of bumps on the circuit side when grinding the back surface, and prevents generation of dimples or cracks on the grinding surface..