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Semiconductor patents

      

This page is updated frequently with new Semiconductor-related patent applications.




 Image sensor having different substrate bias voltages patent thumbnailnew patent Image sensor having different substrate bias voltages
An image sensor having different bias voltages is provided. The image sensor may include a plurality of pixels configured to output pixel signals based on a received optical signal, and logic circuits configured to output the pixels signals as image data.

 Photoelectric conversion device and image pick-up device patent thumbnailnew patent Photoelectric conversion device and image pick-up device
A photoelectric conversion device includes a semiconductor substrate, an insulating layer provided on the semiconductor substrate, an electrode provided on the insulating layer, a photoelectric conversion film provided on the electrode for converting received light to charges, a line connected between the electrode and the semiconductor substrate, a first planar electrode provided in the insulating layer and connected to the electrode, and a second planar electrode provided in the insulating layer between the first planar electrode and the semiconductor substrate.. .
Rohm Co., Ltd.


 Semiconductor device patent thumbnailnew patent Semiconductor device
The present invention is directed to solve a problem that, in an imaging element, complicated control is necessary for reading data for focus detection. A scanning circuit makes a first signal output from a pixel by setting first and second switches to “off” in a period before a first timing, makes a second signal output from the pixel by setting only the first switch to “on” for a predetermined period from the first timing, and makes a third signal output from the pixel by setting the first and second switches to “on” for a predetermined period from a second timing after the first timing.
Renesas Electronics Corporation


 Solid-state imaging device,  manufacturing solid-state imaging device, and electronic apparatus patent thumbnailnew patent Solid-state imaging device, manufacturing solid-state imaging device, and electronic apparatus
The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of rts noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device (1-1) includes: a photodiode (pd) as a photoelectric conversion unit; a transfer gate (tg) that reads out charges from the photodiode (pd); a floating diffusion (fd) from which the charges of the photodiode (pd) are read by an operation of the transfer gate (tg); and an amplifying transistor (tr3) connected to the floating diffusion (fd).
Sony Corporation


 Semiconductor device, correction method in semiconductor device, and correction  camera module patent thumbnailnew patent Semiconductor device, correction method in semiconductor device, and correction camera module
Provided is a semiconductor device which is coupled to a device that outputs positional information representing a position and includes a first external terminal to which the positional information is supplied, and a second external terminal. Sensitivity deviation information representing the deviation of the sensitivity of the device is received through the second external terminal, and a gain to amplify the positional information from the first external terminal is set on the basis of the sensitivity deviation information.

 Semiconductor device and radio communication device patent thumbnailnew patent Semiconductor device and radio communication device
A semiconductor device (10) includes a transmitting circuit (12) that converts transmission data into a transmission signal with a specified frequency, an amplifier (13) that amplifies a power of the transmission signal, a matching circuit (14) that converts the transmission signal from a balanced signal to an unbalanced signal, and a filter circuit (14) that restricts a frequency band of the transmission signal. The matching circuit includes a primary inductor and a secondary indictor, the filter circuit includes an inductor for a filter, and the primary inductor, the secondary indictor and the inductor for a filter are wound substantially concentrically on one plane..
Renesas Electronics Corporation


 Floating-point adder, semiconductor device, and control  floating-point adder patent thumbnailnew patent Floating-point adder, semiconductor device, and control floating-point adder
An object of the invention is to speed up processing of adding floating-point numbers. A floating-point adder includes: a first register configured to store a first fixed-point number having a predetermined number of digits corresponding to a result of accumulation of a plurality of floating-point numbers; a first conversion unit configured to convert an input first floating-point number into a second fixed-point number having the predetermined number of digits; a second register configured to store the second fixed-point number; an adder configured to add the second fixed-point number stored in the second register and the first fixed-point number stored in the first register, and store a result of the addition in the first register as the first fixed-point number; and a second conversion unit configured to convert the first fixed-point number into a second floating-point number, and output the second floating-point number..
Renesas Electronics Corporation


 A/d converter circuit and semiconductor integrated circuit patent thumbnailnew patent A/d converter circuit and semiconductor integrated circuit
An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit.
Renesas Electronics Corporation


 Method for driving semiconductor device patent thumbnailnew patent Method for driving semiconductor device
A method for driving a semiconductor device capable of reducing an area of a multiplexer and reducing its power consumption is provided. In a method for operating a semiconductor device including a memory and a multiplexer, a first transistor is connected to a first capacitor, and a second transistor is connected to a second capacitor.
Semiconductor Energy Laboratory Co., Ltd.


 Switching circuit, semiconductor switching arrangement and method patent thumbnailnew patent Switching circuit, semiconductor switching arrangement and method
In an embodiment, a switching circuit includes a high voltage depletion mode transistor having a first leakage current and operatively connected in a cascode arrangement to a low voltage enhancement mode transistor having a second leakage current. The second leakage current is larger than the first leakage current..
Infineon Technologies Austria Ag


new patent

Semiconductor device and electronic device


To reduce power consumption, a semiconductor device includes a power source circuit for generating a power source potential, and a power supply control switch for controlling supply of the power source potential from the power source circuit to a back gate of a transistor, and the power supply control switch includes a control transistor for controlling conduction between the power source circuit and the back gate of the transistor by being turned on or off in accordance with a pulse signal that is input into a control terminal of the control transistor. The power source potential is intermittently supplied from the power source circuit to the back gate of the transistor, using the power supply control switch..
Semiconductor Energy Laboratory Co., Ltd.


new patent

Drive device


A drive device that drives a semiconductor switching device includes a capacitor and an output selection unit that selects whether or not to supply charge of the capacitor to a conduction control terminal of the semiconductor switching device, in which the output selection unit includes a first switching device and a second switching device, the charge of the capacitor is supplied to the conduction control terminal of the semiconductor switching device by the first switching device going to a conducting state, the charge is extracted from the conduction control terminal of the semiconductor switching device by the second switching device going to the conducting state, and a gate width of the second switching device is smaller than the gate width of the first switching device.. .
Panasonic Corporation


new patent

Semiconductor device


A semiconductor device according to an embodiment includes a differential circuit including a first current-path receiving a first voltage and a second current-path receiving a second voltage. A first mirror circuit can cause a current obtained by multiplying a current flowing through the first current-path by a first mirror ratio to flow through a third current-path.
Kabushiki Kaisha Toshiba


new patent

Gate-drive-on-array circuit for use with oxide semiconductor thin-film transistors


A gate-drive-on-array circuit for use with oxide semiconductor thin-film transistors of the present invention uses two constant-voltage negative potential sources (vss1, vss2) that are reduced step by step and low potentials of a high-frequency clock signal (ck(n)) and a low-frequency clock signal (lc1, lc2) to ensure an up-pull circuit portion (200) is maintained in a well closed condition during a non-operating period without being affected by the high-frequency clock signal (ck(n)) so as to ensure the circuit operates normally. Further, the first down-pull circuit portion (400) is re-designed to prevent influence thereof imposed on the outputs of the first node (q(n)) and the output terminal (g(n)) so as to ensure the first node (q(n)) and the output terminal (g(n)) can supply the outputs normally without generating signal distortion..
Shenzhen China Star Optoelectronics Technology Co., Ltd.


new patent

Semiconductor device with guard ring coupled resonant circuit


A semiconductor device comprises a guarded circuit. The semiconductor device also comprises a guard ring surrounding the guarded circuit.
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Electric motor control device


The electric motor control device includes: an inverter circuit 20 which converts dc power of a dc power supply 90 into ac power; and a switching control section 60 which performs on/off control of a semiconductor switching element composing the inverter circuit. The switching control section 60 includes: a power-supply-side abnormality determination section 62 which determines whether a power-supply-side abnormal state is established in which regenerative energy from an electric motor 10 cannot be regenerated to the dc power supply; and a switching frequency changeable section 63 which changes, when the power-supply-side abnormality determination section has determined that the power-supply-side abnormal state has been established, a switching frequency of the semiconductor switching element such that an overall loss, which is a total of loss in the inverter and loss in the electric motor, is increased..
Mitsubishi Electric Corporation


new patent

Semiconductor device


A semiconductor device includes a plurality of transistors, each having a gate electrode including extending portions having a length obtained by dividing the gate electrode causing interruption to switching at a desired frequency, wherein current inflow terminals of the plurality of transistors are connected to each other and current outflow terminals of the plurality of transistors are connected to each other.. .
Rohm Co., Ltd.


new patent

Semiconductor device and control method thereof


According to one embodiment, a dc-dc converter 1 includes a power supply unit 12 that includes an inductor l1 and a switching unit and generates an output voltage vout corresponding to a duty of a pulse signal p1, a pid controller 111 that outputs a control signal s corresponding to a difference between a divided voltage of vout and a target voltage vcnst, a pi controller 112 that outputs a control signal d corresponding to a difference between the control signal s and an average current flowing through the inductor l1, a pwm generation unit 113 that generates the pulse signal p1 with a duty ratio corresponding to the control signal d, and in step-down mode, the pi controller 112 performs proportional control of the differential signal ei by using a product of the control signal d and a reference proportionality constant kp as a proportionality constant.. .
Renesas Electronics Corporation


new patent

Resonant type high frequency power supply device and switching circuit for resonant type high frequency power supply device


A resonant type high frequency power supply device provided with a power semiconductor element that performs a switching operation, the resonant type high frequency power supply device including a high frequency pulse drive circuit that transmits a pulse-shaped voltage signal having a high frequency exceeding 2 mhz to the power semiconductor element to drive the above-mentioned power semiconductor element, a variable pulse signal generating circuit that transmits a pulse-shaped voltage signal having a high frequency exceeding 2 mhz to the high frequency pulse drive circuit to drive the above-mentioned high frequency pulse drive circuit, and a bias power supply circuit that supplies driving power to both the variable pulse signal generating circuit and the high frequency pulse drive circuit.. .
Mitsubishi Electric Engineering Company, Limited


new patent

Surface-emitting semiconductor laser, surface-emitting semiconductor laser array, surface-emitting semiconductor laser device, optical transmission device, and information processing device


A surface-emitting semiconductor laser includes a substrate; a first semiconductor multilayer film reflector stacked on the substrate; an active region stacked on or above the first semiconductor multilayer film reflector; a second semiconductor multilayer film reflector stacked on or above the active layer; a cavity extension region interposed between the first semiconductor multilayer film reflector and the active region or between the second semiconductor multilayer film reflector and the active region; and a carrier block layer interposed between the cavity extension region and the active region. The carrier block layer includes a first carrier block layer and a second carrier block layer.
Fuji Xerox Co., Ltd.


new patent

Vertical-cavity surface-emitting laser diode and optical transmission apparatus


A vertical-cavity surface-emitting laser diode includes: a first resonator that has a plurality of semiconductor layers comprising a first current narrowing structure having a first conductive region and a first non-conductor region; a first electrode that supplies electric power to drive the first resonator; a second resonator that has a plurality of semiconductor layers comprising a second current narrowing structure having a second conductive region and a second non-conductive region and that is formed side by side with the first resonator, the second current narrowing structure being formed in same current narrowing layer as the layer where the first current narrowing structure is formed; and a coupling portion as defined herein; and an equivalent refractive index of the coupling portion is smaller than an equivalent refractive index of each of the first resonator and the second resonator.. .
Fuji Xerox Co., Ltd.


new patent

Method of fabricating and operating an optical modulator


A semiconductor device comprising a substrate; a monolithic gain region disposed on the substrate and operable to produce optical gain in response to current injection, including a first electrode over a first portion of the gain region having a first length l1, with a first current i1 being applied; and a second electrode over a second portion of the gain region having a second length l2, with a second current i2 being applied; wherein i1/l1 is greater than i2/l2.. .
Emcore Corporation


new patent

Resonant unit, voltage controlled oscillator (vco) implementing the same, and push-push oscillator implementing a pair of vcos


A resonant circuit to be connected to a negative resistance unit is disclosed. The resonant circuit includes a pair of resonant transmission lines electrically coupled to each other and a coupling transmission line connecting the resonant transmission lines.
Sumitomo Electric Industries, Ltd.


new patent

System and converting chemical energy into electrical energy using nano-engineered porous network materials


An energy conversion device for conversion of chemical energy into electricity. The energy conversion device has a first and second electrode.
Quswami, Inc.


new patent

Peeling method and manufacturing semiconductor device


There is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high yield.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Electronic device


An electronic device includes a semiconductor unit. The semiconductor unit includes a first electrode and a second electrode spaced apart from each other in a first direction; and a first material layer interposed between the first electrode and the second electrode and having a variable resistance characteristic or a threshold switching characteristic, wherein the first electrode, or the second electrode, or both includes a plurality of sub-electrodes and a plurality of second material layers that are alternately arranged in the first direction, and wherein each of the second material layers has a thickness that is sufficiently small to enable the second material layers to exhibit an ohmic-like behavior for a current flowing therein at an operating current of the semiconductor unit..
Sk Hynix Inc.


new patent

Electrode structure for resistive memory device


A semiconductor device includes an interconnect layer and a bottom electrode of a resistive memory device. The bottom electrode is coupled to the interconnect layer, and the bottom electrode is comprised of cobalt tungsten phosphorus (cowp)..
Qualcomm Incorporated


new patent

Self-limited crack etch to prevent device shorting


A semiconductor device includes a piezoelectric layer interposed between a first metal layer and a hardmask layer. A first trench extends through the hardmask layer, the piezoelectric layer and the first metal layer.
International Business Machines Corporation


new patent

Semiconductor light emitting diode chip


A semiconductor light emitting diode chip relates to the field of production technologies of a light emitting diode. In the present invention, corresponding graphical current extension layers are respectively disposed below an n pad and a p pad, and in all light emitting compound areas, there is electronic compound light emitting.
Yangzhou Zhongke Semiconductor Lighting Co., Ltd.


new patent

Semiconductor element, semiconductor device including the same, and manufacturing semiconductor element


To provide a semiconductor element that can have the high adhesion between a substrate made of an oxide or the like and a metal film, a semiconductor element includes a substrate made of an oxide, a semiconductor element structure provided on an upper surface of the substrate, and a metal film provided on a lower surface of the substrate, in which the metal film contains nanoparticles made of an oxide.. .
Nichia Corporation


new patent

Semiconductor light-emitting device


A semiconductor light-emitting device can include a wavelength converting layer including a surrounding portion, which covers at least one semiconductor light-emitting chip in order to emit various colored lights including white light. The semiconductor light-emitting device can include a substrate, a frame located on the substrate, the chip mounted on the substrate, a transparent material layer located on the wavelength converting layer so as to reduce from the wavelength converting layer toward a light-emitting surface thereof, and a reflective material layer disposed at least between the frame and both side surfaces of the wavelength converting layer and the transparent material layer.
Stanley Electric Co., Ltd.


new patent

Semiconductor component and producing a semiconductor component


A method of producing a semiconductor component includes providing an optoelectronic semiconductor chip; applying a molding compound for an optical element, wherein the molding compound is based on a highly refractive polymer material; precuring the molding compound at a temperature of at most 50° c.; and curing the molding compound.. .
Osram Opto Semiconductors Gmbh


new patent

Light emitting device and the manufacturing method thereof


A light emitting device includes a semiconductor light emitting unit and a light-transmitting substrate. The light-transmitting substrate includes an upper surface having two long sides and two short sides and a side surface, and the semiconductor light emitting unit is disposed on the upper surface.
Genesis Photonics Inc.


new patent

Light emitting diode


A light emitting diode including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, and a bragg reflector structure. The emitting layer is configured to emit a light beam and is located between the first-type semiconductor layer and the second-type semiconductor layer.
Genesis Photonics Inc.


new patent

Light-emitting diode chip


A light-emitting diode chip including a semiconductor device layer, a first electrode, a current-blocking layer, a current-spreading layer, and a second electrode is provided. The semiconductor device layer includes a first-type doped semiconductor layer, a second-type doped semiconductor layer, and a light-emitting layer located between the first-type and second-type doped semiconductor layers.
Genesis Photonics Inc.


new patent

Light emitting diode


A light emitting diode includes a light emitting structure including first and second conductive type semiconductor layers and an active layer disposed therebetween, a second hole formed through the active layer and the second conductive type semiconductor layer, and exposing the first conductive type semiconductor layer, a reflective metal layer contacting a portion of the light emitting structure, a cover metal layer contacting at least a portion of the reflective metal layer, a first insulation layer covering the reflective metal layer and the cover metal layer, an electrode layer disposed on the first insulation layer, the electrode layer covering the first insulation layer and filling the second hole, an electrode pad disposed on the light emitting structure, and a first hole formed through the first conductive type semiconductor layer and corresponding to the cover metal layer, in which the electrode pad overlaps the cover metal layer.. .
Seoul Viosys Co., Ltd.


new patent

Method of bonding a semiconductor device to a support substrate


A method according to embodiments of the invention includes providing a wafer of semiconductor devices grown on a growth substrate. The wafer of semiconductor devices has a first surface and a second surface opposite the first surface.
Koninklijke Philips N.v.


new patent

Nitride semiconductor wafer, nitride semiconductor element, and manufacturing nitride semiconductor wafer


A nitride semiconductor wafer includes a silicon substrate, a first layer, a second layer, a third layer, a fourth layer, a fifth layer, and a sixth layer. The first layer is provided on the silicon substrate.
Kabushiki Kaisha Toshiba


new patent

Gallium nitride on 3c-sic composite wafer


We disclose a semiconductor structure comprising a monocrystalline silicon wafer; spaced apart monocrystalline silicon carbide layers disposed directly on the silicon wafer; amorphous and/or polycrystalline silicon carbide layers disposed directly on the silicon wafer between the monocrystalline silicon carbide layers; first gallium nitride layers disposed on the monocrystalline silicon carbide layers; and second gallium nitride layers disposed on the amorphous and/or polycrystalline silicon carbide layers.. .
Anvil Semiconductors Limited


new patent

Producing a light-emitting semiconductor component by connecting first and second semiconductor bodies


The invention relates to a light-emitting semiconductor component, comprising—a first semiconductor body (1), which comprises an active zone (11) in which during the operation of the light-emitting semiconductor component electromagnetic radiation is generated, at least some of which leaves the first semiconductor body (1) through a radiation exit surface (1a), and—a second semiconductor body (2), which is suitable for converting the electromagnetic radiation into converted electromagnetic radiation having a longer wavelength, wherein—the first semiconductor body (1) and the second semiconductor body (2) are produced separately from each other,—the second semiconductor body (2) is electrically inactive, and—the second semiconductor body (2) is in direct contact with the radiation exit surface (1a) and is attached there to the first semiconductor body (1) without connecting means.. .
Osram Opto Semiconductors Gmbh


new patent

Method for producing substrate for semiconductor light emitting elements, manufacturing semiconductor light emitting element, substrate for semiconductor light emitting elements, and semiconductor light emitting element


An upper surface of a substrate is etched using a first single-particle film as a mask. The first single-particle film is constituted of first particles having a first particle diameter.
Oji Holdings Corporation


new patent

Method for producing group iii nitride semiconductor light-emitting device


There is provided a method for producing a group iii nitride semiconductor light-emitting device having a low driving voltage, which is realized by steeply increasing the concentration of mg within a p-type semiconductor layer. This production method includes the steps of forming an n-type contact layer, forming an n-side high electrostatic breakdown voltage layer, forming an n-side superlattice layer, forming a light-emitting layer, forming a p-type cladding layer, forming a p-type intermediate layer, and forming a p-type contact layer.
Toyoda Gosei Co., Ltd.


new patent

Layer transfer of films utilizing controlled shear region


A film of material may be formed by providing a semiconductor substrate having a surface region and a cleave region located at a predetermined depth beneath the surface region. During a process of cleaving the film from the substrate, shear in the cleave region is carefully controlled.
Silicon Genesis Corporation


new patent

Transistor barrier-controlled internal photoemission detector


A three-terminal transistor-based radiation detector is presented which uses internal photoemission over a bias-controlled potential barrier which may be of a bipolar or field-effect transistor nature. The proposed invention allows bias-tunable control of the radiation wavelength under detection while enabling integration with conventional silicon or other semiconductor fabrication processes.

new patent

Solar cell


A solar cell is provided with: a crystal substrate having n-type conductivity type as one conductivity type; an n-type semiconductor layer-that is continuously laminated from a light receiving surface, i.e., one main surface of the crystal substrate, and a side surface of the crystal substrate; a p-type semiconductor layer, which is continuously laminated from a rear surface, i.e., the other main surface of the crystal substrate, and the side surface of the crystal substrate, and which has at least one part thereof overlapping, on the side surface of the crystal substrate, the n-type semiconductor layer; a light receiving surface-side transparent conductive film, which is, on the light receiving surface of the crystal substrate, laminated to the n-type semiconductor layer, and which has a smaller area than a planar shape of the crystal substrate; and a rear surface-side transparent conductive film laminated to the p-type semiconductor layer.. .
Panasonic Intellectual Property Management Co., Ltd.


new patent

Epitaxial wafer and manufacturing same


An epitaxial wafer which allows manufacture of a photodiode having suppressed dark current and ensured sensitivity, and a method for manufacturing the epitaxial wafer, are provided. The epitaxial wafer of the present invention includes: a iii-v semiconductor substrate; and a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a first layer and a second layer.
Sumitomo Electric Industries, Ltd.


new patent

Solar cell element and manufacturing solar cell element


In a solar cell element including a silicon substrate that includes a p-type semiconductor region in a surface thereof and an electrode that is located on the p-type semiconductor region and based on aluminum, the electrode includes a glass component containing vanadium oxide, tellurium oxide, and boron oxide, the glass component having a vanadium oxide content smaller than the sum of a tellurium oxide and a boron oxide content. Alternatively, the electrode includes a glass component containing vanadium oxide, tellurium oxide, and boron oxide, the glass component containing 5 to 33 parts by mass of vanadium oxide, 4 to 30 parts by mass of tellurium oxide, and 4 to 18 parts by mass of boron oxide based on 100 parts by mass of the glass component..
Kyocera Corporation


new patent

Photoelectric conversion element, photoelectric conversion module, and solar photovoltaic power generation system


There is provided a photoelectric conversion element which can prevent the contact resistance between a non-crystalline semiconductor layer containing impurities and an electrode formed on the non-crystalline semiconductor layer from increasing, and can improve the element characteristics. A photoelectric conversion element (10) includes a semiconductor substrate (12), a first semiconductor layer (20n), a second semiconductor layer (20p), a first electrode (22n), and a second electrode (22p).
Sharp Kabushiki Kaisha


new patent

Damage buffer for solar cell metallization


A solar cell structure includes a semiconductor region disposed in or above a substrate. A damage buffer can be disposed above the semiconductor region.

new patent

Photovoltaic solar cell and producing a metallic contact-connection of a photovoltaic solar cell


The invention relates to a method for producing a metallic contact-connection of a photovoltaic solar cell, including the following method steps: a providing a semiconductor substrate, and b applying an aluminum-containing contact-connection layer indirectly or directly to a side of the semiconductor substrate. The invention is characterized in that in a method step c, a diffusion barrier layer, which acts as a diffusion barrier at least with respect to aluminum, is applied indirectly or directly to the contact-connection layer, and in a method step d, a solderable layer comprised of a solderable material is applied indirectly or directly to the diffusion barrier layer, and in that the diffusion barrier layer and the contact-connection layer are applied by a pvd method..
Fraunhofer-gesellschaft Zur Forderung Der Angewand Ten Forschung E.v.


new patent

Silicon photonics integration method and structure


Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device.
International Business Machines Corporation


new patent

Method of intercalating insulating layer between metal and graphene layer and fabricating semiconductor device using the intercalation method


A method includes growing a graphene layer on a metal layer, intercalating a first material between the metal layer and the graphene layer by heating the first material at a first pressure and a first temperature, and intercalating a second material between the metal layer and the graphene layer by heating the second material at a second pressure different from the first pressure and a second temperature different from the first temperature. Accordingly, the first material and the second material are chemically bonded to each other to form an insulating layer, and the insulating layer may be between the metal layer and the graphene layer..
Samsung Electronics Co., Ltd.


new patent

Manufacturing method and structure of oxide semiconductor tft substrate


The present invention provides a manufacturing method and a structure of an oxide semiconductor tft substrate, in which an oxide conductor layer is used to define a channel of an oxide semiconductor tft substrate. Since the oxide conductor layer is relatively thin and compared to the known techniques, the width of the channel can be made smaller and the width of the channel can be controlled precisely, the difficult of the manufacturing process of the oxide semiconductor tft substrate can be reduced and the performance of the oxide semiconductor tft substrate can be enhanced and the yield rate of manufacture can be increased.
Shenzhen China Star Optoelectronics Technology Co., Ltd.


new patent

Semiconductor device and manufacturing the same


A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Method for producing semiconductor device and semiconductor device


An sgt production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.. .
Unisantis Electronics Singapore Pte. Ltd.


new patent

Method for manufacturing polysilicon thin film transistor


A method for manufacturing polysilicon thin film transistor is disclosed, and the method comprises the following steps: forming a semiconductor material layer on a prefabricated substrate; forming an intermediate layer on the semiconductor material layer; forming a photoresist layer on the intermediate layer, and exposing the photoresist layer with a photomask for a first time; moving the prefabricated substrate in a predetermined direction relative to the photomask, and exposing the photoresist layer with the photomask for a second time; forming a photoresist region which comprises a central part and a wing part and a hollowed-out region which contains no photoresist material in the photoresist layer; and forming an ion lightly doped region corresponding to the wing part and an ion heavily doped region corresponding to the hollowed-out region in the semiconductor material layer.. .
Shenzhen China Star Optoelectronics Technology Co., Ltd.


new patent

Semiconductor device


To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor device, an oxide semiconductor layer filling a groove is surrounded by insulating layers including an aluminum oxide film containing excess oxygen.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Semiconductor device and manufacturing method thereof


To provide a semiconductor device having a structure with which the device can be easily manufactured even if the size is decreased and which can suppress a decrease in electrical characteristics caused by the decrease in the size, and a manufacturing method thereof. A source electrode layer and a drain electrode layer are formed on an upper surface of an oxide semiconductor layer.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Ferroelectric device and meethod for manufacturing same


A ferroelectric device and a manufacturing method are provided. While holding a nonvolatile memory retention capability and a multiple rewriting endurance as the distinctive features of a ferroelectric device, the disclosed ferroelectric device is wider in memory window and more adaptively made microfiner than a conventional ferroelectric device that has used a ferroelectric mainly constituted of sr—bi—ta—o as an oxide of strontium, bismuth and tantalum.
Wacom R&d Corporation


new patent

Method of manufacturing semiconductor device


An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, a silicon film, for the memory gate electrode of a memory cell in a nonvolatile memory is formed via an insulating film so as to cover the control gate electrode of the memory cell.
Renesas Electronics Corporation


new patent

Semiconductor device and manufacturing the same


An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Semiconductor device


To provide a transistor with favorable electrical characteristics. A semiconductor device includes a first insulator over a substrate; a first metal oxide over the first insulator; a second metal oxide over the first metal oxide; a first conductor and a second conductor over the second metal oxide; a third metal oxide over the second metal oxide, the first conductor, and the second conductor; a second insulator over the third metal oxide; and a third conductor over the second insulator.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Semiconductor device and fabrication method thereof


A transistor with high and stable electrical characteristics whose parasitic capacitance is suppressed is provided even when miniaturized. A semiconductor device including it also achieves higher performance and reliability.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Manufacturing method and structure of oxide semiconductor tft substrate


The present invention provides a manufacturing method and a structure of an oxide semiconductor tft substrate, in which an oxide conductor layer is used to define a channel and a source terminal of an oxide semiconductor tft substrate. Since the oxide conductor layer is relatively thin and compared to the known techniques, the width of the channel can be made smaller and the width of the channel can be controlled precisely, the difficult of the manufacturing process of the oxide semiconductor tft substrate can be reduced and the performance of the oxide semiconductor tft substrate can be enhanced and the yield rate of manufacture can be increased.
Shenzhen China Star Optoelectronics Technology Co., Ltd.


new patent

Semiconductor device and fabricating the same


semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess.
Samsung Electronics Co., Ltd.


new patent

Semiconductor devices


A method of manufacturing a semiconductor device includes partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, which includes providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (seg) process using a top surface of the active fin exposed by the trench as a seed so that a silicon-germanium layer is grown; and purging the chamber by providing the carrier gas into the chamber to etch the silicon-germanium layer.. .
Samsung Electronics Co., Ltd.


new patent

Semiconductor structure with template for transition metal dichalcogenides channel material growth


A semiconductor structure includes a substrate, a buffer layer, and a two-dimensional layered material. The buffer layer is above the substrate and is formed from one of sic and a nitride-based material.
National Chiao-tung University


new patent

Semiconductor devices and fabrication method thereof


A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate; and forming a first gate structure on the semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


new patent

Field-effect transistor with aggressively strained fins


In a method for fabricating a field-effect transistor (fet) structure, forming a shallow trench isolation (sti) structure on a semiconductor substrate, wherein the sti structure includes dielectric structures that form one or more dielectric walled aspect ratio trapping (art) trenches. The method further includes epitaxially growing a first semiconductor material on the semiconductor substrate and substantially filling at least one of the one or more art trenches, and recessing the first semiconductor material down into the art trenches selective to the dielectric structures, such that the upper surface of the first semiconductor material is below the upper surface of the dielectric structures.
International Business Machines Corporation


new patent

Finfets and the methods for forming the same


A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched.
Taiwan Semiconductor Manuufacturing, Ltd.


new patent

Channel last replacement flow for bulk finfets


There is set forth herein a method including patterning a fin on a substrate of a semiconductor structure, forming dielectric material over the substrate, performing a process for removing material from a fin to define a cavity at a channel region of the fin, and forming a replacement semiconductor material formation at the channel region.. .
Globalfoundries Inc.


new patent

Semiconductor device


A semiconductor device according to an embodiment includes a semiconductor layer. A gate dielectric film is provided on a surface of the semiconductor layer.
Kabushiki Kaisha Toshiba


new patent

Method of manufacturing semiconductor device and semiconductor device


A semiconductor device includes a supporting substrate, an insulating film formed in a first region over the supporting substrate, a first semiconductor layer formed over the insulating film, a first epitaxial layer formed in an opening of the insulating film in a second region over the supporting substrate, an element isolation region formed between the first semiconductor layer and the first epitaxial layer, and a semiconductor element formed over each of the first semiconductor layer in the first region and the first epitaxial layer in the second region. The first semiconductor layer and the first epitaxial layer is spaced apart from each other by 5 μm or more..
Renesas Electronics Corporation


new patent

Power mosfets and methods for forming the same


Power metal-oxide-semiconductor field-effect transistors (mosfets) and methods of forming the same are provided. A power mosfet may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape.
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes: an n-type first source region and first drain region formed in a surface of a p-type epitaxial layer; an n-type first source drift region and first drain drift region formed so as to individually surround the first source region and the first drain region; and a p-type first diffusion region formed in a first channel region and having a higher concentration than the epitaxial layer, the semiconductor device having p-type first withstand voltage maintaining regions formed between the first diffusion region, and the first source drift region and first drain drift region respectively, the first withstand voltage maintaining regions having a lower concentration than the first diffusion region.. .
Rohm Co., Ltd.


new patent

Silicon carbide semiconductor device and manufacturing the same


A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer having a main surface, the main surface being provided with a trench which has a bottom portion and a sidewall inclined with respect to the main surface; a gate insulating film covering each of the bottom portion and the sidewall; a gate electrode provided at least on the gate insulating film; and an upper insulating film provided on the main surface and having a part which protrudes into the trench.. .
Sumitomo Electric Industries, Ltd.


new patent

Silicon carbide semiconductor device


A silicon carbide semiconductor device includes: a substrate; a drift layer; a current dispersion layer; a base region; a source region; trenches; a gate insulation film; a gate electrode; a source electrode; a drain electrode; and a bottom layer. The current dispersion layer is arranged on the drift layer, and has a first conductive type with an impurity concentration higher than the drift layer.
Toyota Jidosha Kabushiki Kaisha


new patent

Semiconductor device and manufacturing the same


In one embodiment, a semiconductor device includes a substrate, and a gate conductor provided on the substrate. The device further includes a first insulator provided on the gate conductor, a second insulator provided on the first insulator and including an opening, and a third insulator provided on the second insulator and provided in the opening.
Kabushiki Kaisha Toshiba


new patent

Nonvolatile semiconductor memory device


According to an embodiment, a nonvolatile semiconductor memory device comprises: a semiconductor layer; a charge accumulation layer facing the semiconductor layer via a gate insulating layer; and a control gate electrode facing the charge accumulation layer via an inter-gate insulating layer. The charge accumulation layer comprises: a first semiconductor layer facing the semiconductor layer via the gate insulating layer; a second semiconductor layer contacting the first semiconductor layer and including carbon; and a third semiconductor layer contacting the second semiconductor layer and including carbon and boron.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device and manufacturing the same


A semiconductor device of an embodiment includes a sic layer having a surface, the surface inclined at an angle of 0° to 10° with respect to a {000-1} face or the surface having a normal line direction inclined at an angle of 80° to 90° with respect to a <000-1> direction, a gate electrode, a gate insulating layer provided between the surface and the gate electrode, and a region provided between the surface and the gate insulating layer, a maximum concentration of deuterium (d) in the region being 1×1020 cm−3 or more and a maximum concentration of hydrogen (h) in the region being 1×1019 cm−3 or less.. .
Kabushiki Kaisha Toshiba


new patent

Semiconductor devices and methods of manufacturing the same


Provided are semiconductor devices and methods of manufacturing the same. A semiconductor device may include a source, a drain, a semiconductor element between the source and the drain, and a graphene layer that is provided on the source and the semiconductor element and is spaced apart from the drain.
Samsung Electronics Co., Ltd.


new patent

Vertical power component


A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.. .
Universite Francois Rabelais


new patent

Semiconductor device and manufacturing semiconductor device


In a semiconductor device including an oxide semiconductor, the amount of oxygen vacancies is reduced. Moreover, electrical characteristics of a semiconductor device including an oxide semiconductor are improved.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Semiconductor device having a strained region


The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure.
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Finfets and methods for forming the same


A finfet and methods for forming a finfet are disclosed. A method includes forming trenches in a semiconductor substrate to form a fin, depositing an insulating material within the trenches, and removing a portion of the insulating material to expose sidewalls of the fin.
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Power mosfet device structure for high frequency applications


This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current.

new patent

High-voltage field-effect transistor and making the same


The high-voltage transistor device comprises a semiconductor substrate (1) with a source region (2) of a first type of electrical conductivity, a body region (3) including a channel region (4) of a second type of electrical conductivity opposite to the first type of conductivity, a drift region (5) of the first type of conductivity, and a drain region (6) of the first type of conductivity extending longitudinally in striplike fashion from the channel region (4) to the drain region (6) and laterally confined by isolation regions (9). The drift region (5) comprises a doping of the first type of conductivity and includes an additional region (8) with a net doping of the second type of conductivity to adjust the electrical properties of the drift region (5).
Ams Ag


new patent

Drain extended mos transistors with split channel


A method of making a semiconductor device is provided. The method includes forming a deep well (dwell) and a well (well) in a first region of a substrate, the well adjacent a surface of the substrate so that an interface between the well and dwell is exposed on the surface of the substrate.
Cypress Semiconductor Corporation


new patent

Method of forming mosfet structure


A method includes providing a semiconductor structure that includes an epitaxial layer and a cap layer above the epitaxial layer, filling a trench above the cap layer with a sacrificial layer, and removing the sacrificial layer. As such, the cap layer is protected by the sacrificial layer during an etching process and the epitaxial layer is protected by the cap layer during another etching process..
Taiwan Semiconductor Manufacturing Company Limited


new patent

Lateral pnp bipolar transistor with narrow trench emitter


A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector.
Alpha And Omega Semiconductor Incorporated


new patent

Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device capable of reducing an on resistance. In the present invention, a drift layer is formed on a substrate.
Mitsubishi Electric Corporation


new patent

Method for producing semiconductor device and semiconductor device


An sgt production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask formed from a third insulating film; a third step of forming a second hard mask on a side wall of the first hard mask, and forming a second dummy gate; a fourth step of forming a sidewall and forming a second diffusion layer; a fifth step of depositing an interlayer insulating film, exposing upper portions of the second dummy gate and the first dummy gate, removing the second dummy gate and the first dummy gate, forming a first gate insulating film, and forming a gate electrode and a gate line; and a sixth step of forming a first contact and a second contact.. .
Unisantis Electronics Singapore Pte. Ltd.


new patent

Semiconductor structure including at least one electrically conductive pillar, semiconductor structure including a contact contacting an outer layer of an electrically conductive structure and the formation thereof


A semiconductor structure includes a substrate, at least one electrically conductive pillar provided over the substrate and an electrically conductive structure provided over the substrate. The electrically conductive pillar includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion.
Globalfoundries Inc.


new patent

Metal contacts to group iv semiconductors by inserting interfacial atomic monolayers


Techniques for reducing the specific contact resistance of metal-semiconductor (group iv) junctions by interposing a monolayer of group v or group iii atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group iv semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (fet).
Acorn Technologies, Inc.


new patent

Semiconductor device


A semiconductor device includes first and second fin-shaped silicon layers on a substrate, each corresponding to the dimensions of a sidewall pattern around a dummy pattern. First and second pillar-shaped silicon layers reside on the first and second fin-shaped silicon layers, respectively.
Unisantis Electronics Singapore Pte. Ltd.


new patent

Semiconductor template and manufacturing method thereof


The present invention provides a semiconductor template, comprising: a substrate; a buffer layer, disposed on a surface of the substrate and comprises a first sub-buffer layer and a second sub-buffer layer sequentially stacked, wherein the buffer layer has irregular cracks such that the top surface of the buffer layer is discontinuous, and the depth of the cracks are greater than or equal to the thickness of the second sub-buffer layer and less than or equal to sum of the thickness of the first sub-buffer and the second sub-buffer layer; and an epitaxial layer, which is a continuous layer and disposed on the buffer layer.. .
Hermes-epitek Corp.


new patent

Stress relieving semiconductor layer


A semiconductor structure, such as a group iii nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer.
Sensor Electronic Technology, Inc.


new patent

Semiconductor device and manufacturing the same


A semiconductor device of an embodiment includes a sic layer, a gate electrode, a gate insulating layer provided between the sic layer and the gate electrode, and a first region provided between the sic layer and the gate insulating layer and having a peak of nitrogen (n) concentration distribution and a peak of fluorine (f) concentration distribution.. .
Kabushiki Kaisha Toshiba


new patent

Epitaxial silicon germanium fin formation using sacrificial silicon fin templates


A method of forming semiconductor fins includes forming a plurality of sacrificial template fins from a first semiconductor material; epitaxially growing fins of a second semiconductor material on exposed sidewall surfaces of the sacrificial template fins; and removing the plurality of sacrificial template fins.. .
International Business Machines Corporation


new patent

Planar heterogeneous device


In an embodiment a second semiconductor layer is transferred (e.g., using layer transfer techniques) on top of a first semiconductor layer. The second layer is patterned into desired wells.
Intel Corporation


new patent

Mos-based power semiconductor device having increased current carrying area and fabricating same


A semiconductor device includes a substrate, a drift region, a source region, a gate region, a drain contact and a base region. The substrate is doped with a first dopant type.
Purdue Research Foundation


new patent

Semiconductor device comprising a switch


A semiconductor device comprising a switch and a method of making the same. The device has a layout that includes one or more rectangular unit cells.
Nxp B.v.


new patent

Trench semiconductor device layout configurations


A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material..
Sanken Electric Co., Ltd.


new patent

Preventing buried oxide gouging during planar and finfet processing on soi


A method for preventing damage to the insulator layer of a semiconductor device during creation of fin field effect transistor (finfet) includes obtaining a material stack having an active semiconductor layer, an insulator layer, and an etch stop layer between the active semiconductor layer and the insulator layer; forming a fin-array from the active semiconductor layer; patterning the fin-array; and fabricating a finfet device from the patterned fin-array; where the etch stop layer is resistant to processes the etch stop layer is exposed to during the forming, patterning, and fabricating operations, such that the etch stop layer and the insulator layer are not damaged during the forming, patterning, and fabricating operations.. .
International Business Machines Corporation


new patent

Organic light emitting display device


An organic light emitting display device comprises a driving transistor for driving an organic light emitting diode; a first transistor controlled by a scan signal and connected between a reference voltage line and a first node of the driving transistor; a second transistor controlled by the scan signal and connected between a data line and a second node of the driving transistor; a first plate with an improved conductive characteristic and connected to the semiconductor layer of the driving transistor and the semiconductor layer of the first transistor; a second plate positioned on the first plate, and connected to the semiconductor layer of the second transistor and a gate electrode of the driving transistor; and a pixel electrode of the organic light emitting diode, positioned on the second plate and connected to the first plate through a contact hole.. .
Lg Display Co., Ltd.


new patent

Area sensor and display apparatus provided with an area sensor


An area sensor of the present invention has a function of displaying an image in a sensor portion by using light-emitting elements and a reading function using photoelectric conversion devices. Therefore, an image read in the sensor portion can be displayed thereon without separately providing an electronic display on the area sensor.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Pixel structure having high aperture ratio and circuit


The present invention provides a pixel structure having high aperture ratio and circuit. The first gate (21), the first source/the first drain (61), and the etching stopper layer (5), the first semiconductor layer (41), the gate isolation layer (3) sandwiched in-between of the pixel structure having high aperture ratio construct a first thin film transistor (tft1); the second gate (22), the second source/the second drain (62), and the etching stopper layer (5), the second semiconductor layer (42), the gate isolation layer (3) sandwiched in between construct a second thin film transistor (tft2); the transparent electrode (8), the pixel electrode (10) and the flat isolation layer (9)sandwiched in-between construct a transparent capacitor (c), and the transparent capacitor (c) constructs an activation area part of the pixel structure which is capable of increasing the activation area of the pixel and raising the aperture ratio to increase the display brightness and reduce the power consumption..
Shenzhen China Star Optoelectronics Technology Co., Ltd.


new patent

Flexible display


A flexible display includes a driving circuit to drive a light emitting device. The driving circuit includes a thin film transistor which includes a column-shaped gate electrode extending in a first direction, a gate insulating layer enclosing an outer surface of the gate electrode, a semiconductor layer on an outer surface of the gate insulating layer, and first and second conductive layers enclosing first and second areas of the semiconductor layer, respectively..
Samsung Display Co., Ltd.


new patent

Organic light emitting display device and manufacturing organic light emitting display device


An organic light emitting display device, including a substrate, a first conductive layer pattern on the substrate, a first insulation layer pattern on the first conductive layer pattern, a first semiconductor layer pattern on the first insulation layer pattern, a gate insulation layer pattern on the gate insulation layer pattern, a gate electrode on the gate insulation layer pattern, a planarization layer on the gate electrode, the planarization layer including a first protruding potion protruded in a first direction perpendicular to an upper surface of the substrate, a lower electrode on the first protruding portion, a pixel defining layer exposing at least a portion of the lower electrode, the pixel defining layer covering opposite side portions of the first protruding portion, a light emitting layer on the lower electrode, and an upper electrode on the light emitting layer.. .
Samsung Display Co., Ltd.


new patent

Solid-state image sensing device


According to one embodiment, a solid-state image sensing device includes an organic photoelectric conversion layer. The organic photoelectric conversion layer includes an organic semiconductor material and an organic dye.
Kabushiki Kaisha Toshiba


new patent

Floating staircase word lines and process in a 3d non-volatile memory having vertical bit lines


A 3d nonvolatile memory has memory elements arranged in a three-dimensional pattern with a plurality of memory layers stacked over a semiconductor substrate. It has a 2d array of vertical bit lines and a plurality of staircase word lines.
Sandisk 3d Llc


new patent

Electronic device


An electronic device includes a semiconductor unit. The semiconductor unit includes a first electrode and a second electrode spaced apart from each other in a first direction; and a first material layer interposed between the first electrode and the second electrode and having a variable resistance characteristic or a threshold switching characteristic, wherein the first electrode, or the second electrode, or both comprises: a first sub-electrode and a second sub-electrode spaced apart from each other in the first direction; and a second material layer interposed between the first sub-electrode and the second sub-electrode and having a thickness sufficiently small to enable the second material layer to exhibit an ohmic-like behavior for a current flowing therein at an operating current of the semiconductor unit.
Sk Hynix Inc.


new patent

Electronic device having buried gate and fabricating the same


Electronic devices having semiconductor elements and methods for fabricating such devices including, a method for fabricating an electronic device including a semiconductor memory, which includes: forming a sacrificial layer on a substrate including a first region and a second region; selectively etching the sacrificial layer and the substrate of the first region to form a trench; forming a first gate that fills a part of the trench in the first region; forming a gate protection layer on the first gate to fill the remaining part of the trench; removing the sacrificial layer of the first region to form a grooved portion surrounded by the gate protection layer; forming a conductive plug to cover the grooved portion; removing the sacrificial layer of the second region; and forming a second gate on the substrate of the second region.. .
Sk Hynix Inc.


new patent

Display device and producing a display device


A display device with a semiconductor layer sequence includes an active region provided for generating radiation and a plurality of pixels. The display device also includes a carrier.
Osram Opto Semiconductors Gmbh


new patent

Method for manufacturing semiconductor device


An inorganic film is dry-etched using plasma with a photoresist pattern serving as a mask, and an organic film is dry-etched using plasma with the photoresist pattern serving as a mask without exposing a pad electrode. The photoresist pattern is removed using a stripping solution.
Canon Kabushiki Kaisha


new patent

Image sensor and electronic device including the same


An image sensor includes a semiconductor substrate integrated with at least one first photo-sensing device configured to sense light in a blue wavelength region and at least one second photo-sensing device configured to sense light in a red wavelength region, a color filter layer on the semiconductor substrate and including a blue color filter configured to selectively absorb light in a blue wavelength region and a red color filter configured to selectively absorb light in a red wavelength region, and a third photo-sensing device on the color filter layer and including a pair of electrodes facing each other, and a photoactive layer between the pair of electrodes and configured to selectively absorb light in a green wavelength region.. .
Samsung Electronics Co., Ltd.


new patent

Semiconductor device and electronic appliance


The semiconductor device includes a first semiconductor substrate, a second semiconductor substrate providing a function different from a function provided by the first semiconductor substrate, and a diffusion prevention film that prevents diffusion of a dangling bond terminating atom used for reducing the interface state of the first semiconductor substrate and the second semiconductor substrate, wherein at least two semiconductor substrates are stacked and the semiconductor substrates are electrically connected to each other, and the first semiconductor substrate and the second semiconductor substrate are stacked with the diffusion prevention film inserted between an interface of the first semiconductor substrate and an interface of the second semiconductor substrate.. .

new patent

Solid-state image pickup device, manufacturing solid-state image pickup device, and electronic apparatus


There is provided a solid-state image pickup device including: a semiconductor substrate (21); a photodiode (11a, 11b) formed in the semiconductor substrate; a transistor (10) having a gate electrode (14) part or all of which is embedded in the semiconductor substrate, the transistor being configured to read a signal electric charge from the photodiode via the gate electrode; and an electric charge transfer layer (13) provided between the gate electrode and the photodiode.. .
Sony Corporation


new patent

Semiconductor device, imaging apparatus, and manufacturing semiconductor device


A semiconductor device includes a semiconductor layer, an electrode embedded from a surface of the semiconductor layer to an inside of the semiconductor layer and insulated by an insulation layer, and a structure in which a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of the first conductivity type are formed in this order from the surface of the semiconductor layer along the electrode via the insulation layer. The electrode is arranged at a position where no inversion layer is formed by a voltage supplied to the electrode in at least one of an interface of the first semiconductor region and the second semiconductor region and an interface of the second semiconductor region and the third semiconductor region..
Ricoh Company, Ltd.


new patent

Photoelectric conversion apparatus


Provided is a photoelectric conversion apparatus including a photoelectric conversion element. The photoelectric conversion element includes a first semiconductor region, a second semiconductor region, and a third semiconductor region.
Canon Kabushiki Kaisha


new patent

Method for manufacturing tft substrate having storage capacitors and tft substrate


The present invention provides a method for manufacturing a tft substrate having storage capacitors and the tft substrate. The method includes: (1) forming a gate terminal (21) and a first metal electrode (23); (2) forming a gate insulation layer (3) and a gate insulation layer through-hole (31); (3) forming an oxide semiconductor layer (4); (4) subjecting a portion of the oxide semiconductor layer (4) to n-type heavy doping to form a first conductor electrode (5) thereby constituting a first storage capacitor c1; (5) forming an etch stop layer (6) and a first etch stop layer through-hole (61); (6) forming source/drain terminals (71) and a second metal electrode (73), thereby constituting a second storage capacitor c2 with c2 being connected in parallel to c1; (7) forming a protection layer (8), a protection layer through-hole (81), and a second etch stop layer through-hole (63); and (8) forming a pixel electrode (91) and a second conductor electrode (93), thereby constituting a third storage capacitor c3 with c3 being connected in parallel to c2..
Shenzhen China Star Optoelectronics Technology Co., Ltd.


new patent

Tft backplate structure and manufacture method thereof


The present invention provides a tft backplate structure and a manufacture method thereof. The tft backplate structure comprises a switch tft (t1) and a drive tft (t2).
Shenzhen China Star Optoelectronics Technology Co., Ltd.


new patent

Semiconductor device and manufacturing the same


A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a first insulating layer; a first oxide layer over the first insulating layer; a semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer over the semiconductor layer; a second insulating layer over the first insulating layer; a third insulating layer over the second insulating layer, the source electrode layer, and the drain electrode layer; a second oxide layer over the semiconductor layer; a gate insulating layer over the second oxide layer; a gate electrode layer over the gate insulating layer; and a fourth insulating layer over the third insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer..
Semiconductor Energy Laboratory Co., Ltd.


new patent

Semiconductor device and manufacturing same


A semiconductor device (100) includes: a substrate (11); a first thin film transistor (10a) supported on the substrate (11), the first thin film transistor (10a) having a first active region (13c) which mainly contains a crystalline silicon; and a second thin film transistor (10b) being supported on the substrate (11), the second thin film transistor (10b) having a second active region (17c) which mainly contains an oxide semiconductor having a crystalline portion.. .
Sharp Kabushiki Kaisha


new patent

Display device and manufacturing the same


An object of the present invention is to decrease substantial resistance of an electrode such as a transparent electrode or a wiring, and furthermore, to provide a display device for which is possible to apply same voltage to light-emitting elements. In the invention, a auxiliary wiring that is formed in one layer in which a conductive film of a semiconductor element such as an electrode, wiring, a signal line, a scanning line, or a power supply line is connected to an electrode typified by a second electrode, and a wiring.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Semiconductor device


A well potential supply region is provided in an n-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch.
Socionext Inc.


new patent

Memory devices including vertical pillars and methods of manufacturing and operating the same


A semiconductor device includes a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate.
Samsung Electronics Co., Ltd.


new patent

Vertical type memory device


A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections.

new patent

Three-dimensional semiconductor memory devices


Three-dimensional (3d) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., p-type) therein and a common source region of first conductivity type (e.g., n-type) on the well region. A recess extends partially (or completely) through the common source region.
Samsung Electronics Co., Ltd.


new patent

Semiconductor device and manufacturing semiconductor device


According to one embodiment, a semiconductor device includes a semiconductor layer, memory cell component layers, a dividing part, and a complementary film. The memory cell component layers are provided on the semiconductor layer such that memory cells are arranged in a three-dimensional state.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device and manufacturing semiconductor device


According to one embodiment, it includes a stacked body formed such that a first layer and a second layer, which are made of materials different from each other, are alternately stacked, and one of layers of the first layer or one of layers of the second layer is replaced with a third layer that does not transmit light of a wavelength λ, and an opening that penetrates the stacked body in a stack direction and has a diameter or width smaller than the wavelength λ.. .
Kabushiki Kaisha Toshiba


new patent

Semiconductor device and manufacturing method thereof


A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps.
Macronix International Co., Ltd.


new patent

Semiconductor device and manufacturing method thereof


A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps.
Macronix International Co., Ltd.


new patent

Pattern layout to prevent split gate flash memory cell failure


A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region.
Taiwan Semiconductor Manufacturing Co., Ltd.


new patent

Semiconductor structure including a split gate nonvolatile memory cell and a high voltage transistor, and the formation thereof


A semiconductor structure includes a split gate nonvolatile memory cell and a high voltage transistor. The nonvolatile memory cell includes an active region, a nonvolatile memory stack provided above the active region, a control gate electrode provided above the memory stack, a select gate electrode at least partially provided above the active region adjacent to the memory stack and a select gate insulation layer.
Globalfoundries Inc.


new patent

Semiconductor storage device and manufacturing the semiconductor storage device


A semiconductor storage device includes an insulating layer. A ferroelectric capacitor is on the insulating layer and includes a lower electrode, a ferroelectric film, and an upper electrode.
Rohm Co., Ltd.


new patent

Semiconductor memory device


The memory capacity of a dram is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Semiconductor device


Provided is a technology for further reducing a loss in a semiconductor device including a semiconductor substrate in which an igbt region and a diode region are provided. This semiconductor device includes a semiconductor substrate in which at least one igbt region and at least one diode region are provided.
Toyota Jidosha Kabushiki Kaisha


new patent

Fin field effect transistor


Various embodiments provide semiconductor devices and methods for forming the same. A first fin and a second fin are formed on a semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


new patent

Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin structures


A method of forming a semiconductor device that includes forming an at least partially relaxed semiconductor material, and forming a plurality of fin trenches in the partially relaxed semiconductor material. At least a portion of the plurality of fin trenches is filled with a first strained semiconductor material that is formed using epitaxial deposition.
International Business Machines Corporation


new patent

Method of forming a complementary metal oxide semiconductor structure with n-type and p-type field effect transistors having symmetric source/drain junctions and optional dual silicides


In a method of forming a semiconductor structure, different sections of a dielectric layer are etched at different stages during processing to form a first gate sidewall spacer for a first fet (e.g., a nfet) and a second gate sidewall spacer for a second fet (e.g., a pfet) such that the first and second gate sidewall spacers are symmetric. Raised source/drain regions for the first fet are formed immediately following first gate sidewall spacer formation and raised source/drain regions for the second fet are formed immediately following second gate sidewall spacer formation.
Globalfoundries Inc.


new patent

Semiconductor integrated circuit device and manufacturing the same


Provided is a semiconductor integrated circuit device including a first n-channel type high withstanding-voltage mos transistor and a second n-channel type high withstanding-voltage mos transistor formed on an n-type semiconductor substrate, the first n-channel type high withstanding-voltage transistor including a third n-type low-concentration impurity region containing arsenic having a depth smaller than a p-type well region in a drain region within the p-type well region, and the second n-channel type high withstanding-voltage mos transistor including a fourth n-type low-concentration impurity region that is adjacent to the p-type well region and has a bottom surface being in contact with the n-type semiconductor substrate. In this manner, the high withstanding-voltage nmos transistors capable of operating at 30 v or higher are integrated on the n-type semiconductor substrate..
Sii Semiconductor Corporation


new patent

Semiconductor device


A semiconductor device includes a semiconductor substrate having an active layer in which an element region and a contact region are formed, a support substrate supporting the active layer, and a buried insulation layer interposed between the active layer and the support substrate. A transistor element is formed in the element region, the transistor element having a transistor buried impurity layer formed within the active layer.
Rohm Co., Ltd.


new patent

Electrode structure, fabricating the same, and semiconductor device including the electrode structure


An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer..
Samsung Electronics Co., Ltd.


new patent

Method for forming deep trench isolation for rf devices on soi


A semiconductor device includes a silicon-on-insulator (soi) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a soi substrate having shallow trench isolations (stis) and transistors formed within and on the second semiconductor substrate, respectively.
Semiconductor Manufacturing International (shanghai) Corporation


new patent

Dual-series varactor epi


A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode.
Triquint Semiconductor, Inc.


new patent

Semiconductor device


A semiconductor device includes a package, an input terminal fixed to the package, an input pre-matched substrate provided in the package, a semiconductor element provided in the package and formed on a substrate different from the input pre-matched substrate, a matching circuit including a circuit element formed on the input pre-matched substrate, a first wire for connecting the input terminal and the circuit element, and a second wire for connecting the circuit element and the semiconductor element, a first mim capacitor formed as part of the circuit element, and a first stabilization circuit formed as part of the circuit element to reduce oscillation, wherein a lower electrode of the first mim capacitor is connected to the package through a via provided in the input pre-matched substrate.. .
Mitsubishi Electric Corporation


new patent

Semiconductor integrated circuit device


In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of i/o cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding i/o cell.
Socionext Inc.


new patent

Avalanche energy handling capable iii-nitride transistors


A semiconductor device includes a gan fet with an overvoltage clamping component electrically coupled to a drain node of the gan fet and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the gan fet.
Texas Instruments Incorporated


new patent

Compound semiconductor transistor with gate overvoltage protection


A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region.
Infineon Technologies Austria Ag


new patent

Semiconductor module, semiconductor device, and manufacturing semiconductor devices


A semiconductor module includes: first semiconductor devices; second semiconductor devices; a first and second wires. Each first semiconductor device comprises: first sealing resin; first-third terminals; a first semiconductor chip connected to the first and third terminals.
Toyota Jidosha Kabushiki Kaisha


new patent

Semiconductor chip stacking assemblies


Embodiments of the invention provide semiconductor chip stacking assemblies that provide direct attachment of a first semiconductor device with a second semiconductor device. An assembly comprises a first semiconductor chip that has a first and a second set of electrical interconnect regions disposed on its surface and a second semiconductor chip.
Intel Corporation


new patent

High-voltage light emitting diode and manufacturing method thereof


The disclosure relates to a high-voltage light-emitting diode (hv led) and a manufacturing method thereof. A plurality of led dies connected in series, in parallel, or in series and parallel are formed on a substrate.
Genesis Photonics Inc.


new patent

Method and interconnecting stacked dies using metal posts


Embodiments include a semiconductor package comprising a first die having (i) a first side and (ii) a second side, wherein the first die comprises a first plurality of bond pads formed on the first side of the first die; a second die having (i) a first side and (ii) a second side, wherein the second die comprises a second plurality of bond pads formed on the first side of the second die, wherein the second die is stacked on the first die; a first plurality of metal posts formed on the first plurality of bond pads; a second plurality of metal posts formed on the second plurality of bond pads; and a redistribution layer configured to electrically couple (i) a first metal post of the first plurality of metal posts and (ii) a second metal post of the second plurality of metal posts.. .
Marvell World Trade Ltd.


new patent

Semiconductor device


A semiconductor device includes a semiconductor layer and a first insulating film provided on the semiconductor layer. The first insulating film has a surface opposite to the semiconductor layer, the surface including a first portion, a second portion and a third portion between the first portion and the second portion.
Kabushiki Kaisha Toshiba


new patent

Semiconductor packages


semiconductor packages are provided. A semiconductor package may include an embedding substrate including a cavity therein and a connection window in a bottom portion of the cavity.
Sk Hynix Inc.


new patent

Method of manufacturing a semiconductor package having an integrated microwave component


A method of manufacturing an array of semiconductor device packages includes placing a plurality of semiconductor chips on a temporary carrier, covering the plurality of semiconductor chips with an encapsulation material to form an encapsulation body, providing a plurality of microwave components each including at least one electrically conducting wall structure integrated in the encapsulation body, forming a plurality of electrical interconnects each configured to electrically couple a semiconductor chip and a microwave component, and separating the encapsulation body into single semiconductor device packages each including a semiconductor chip, a microwave component and an electrical interconnect.. .
Infineon Technologies Ag


new patent

Integrated wluf and sod process


This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.. .
Intel Corporation


new patent

Manufacturing semiconductor devices


A manufacturing method for semiconductor devices includes the steps of forming an ni/au film that includes an ni film and an au film formed over the ni film over a wiring that is coupled to each of a plurality of electrode pads formed over a principal surface of a semiconductor wafer and arranges each of the electrode pads at a different position, grinding a back surface of the semiconductor wafer, performing reduction treatment on a surface of the ni/au film, and forming a solder bump over the ni/au film. In the reduction treatment, respective processes of flux application, reflow soldering and cleaning are performed and the solder bump is bonded to the ni/au film after the reduction treatment has been completed.
Renesas Electronics Corporation


new patent

Semiconductor device


A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region.
Panasonic Corporation


new patent

On-chip semiconductor device having enhanced variability


A physical unclonable function (puf) semiconductor device includes a semiconductor substrate extending along a first direction to define a length and a second direction opposite the first direction to define a thickness. At least one pair of semiconductor structures is formed on the semiconductor substrate.
International Business Machines Corporation


new patent

Apparatus and generating identification key


Provided is an apparatus for generating an identification key by using process variation in a conductive layer manufacturing process. The apparatus may include a first contact connected to a first conductive layer included in a semiconductor chip, wherein a first node is formed by an electrical connection between the first conductive layer and the first contact, a second contact connected to a second conductive layer included in the semiconductor chip, wherein a second node is formed by an electrical connection between the second conductive layer and the second contact, and wherein a value of a spacing between the first contact and the second contact is smaller than a minimum spacing value that guarantees that the first node and the second node are not shorted on a patterning layout, and a reader configured to determine whether the first node and the second node are electrically shorted and to provide the identification key..
Ictk Co., Ltd.


new patent

Apparatus and generating identification key


An apparatus for generating an identification key is provided. The apparatus may include a first conductive layer formed on a semiconductor chip, a second conductive layer formed on the semiconductor chip, wherein a spacing between the first conductive layer and the second conductive layer is equal to or greater than a first threshold and equal to or less than a second threshold, and a reader configured to determine whether a first node associated with the first conductive layer and a second node associated with the second conductive layer are shorted, and to provide an identification key..
Ictk Co., Ltd.


new patent

Semiconductor package and manufacturing method thereof


A semiconductor package and a method of manufacturing a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor packages, and methods of making thereof, that comprise a cover layer that enhances reliability of the semiconductor packages..
Amkor Technology, Inc.


new patent

Registration mark formation during sidewall image transfer process


Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto.
International Business Machines Corporation


new patent

Semiconductor device, plating method, plating system and recording medium


Adhesivity between a catalyst adsorption layer on a substrate and a barrier metal plating layer can be improved. The catalyst adsorption layer 22 containing a catalyst metal is formed on the substrate 2 by supplying a catalyst solution onto the substrate 2, and a bonding metal layer 22a containing a bonding metal different from the catalyst metal is formed on the catalyst adsorption layer 22 by performing a plating process with the catalyst metal as a catalyst.
Tokyo Electron Limited


new patent

Semiconductor device and manufacturing the same


In one embodiment, a semiconductor device includes a substrate. The device further includes a first interconnect which includes a first layer provided on the substrate and formed of a first interconnect material, and a second layer provided on the first layer, formed of a second interconnect material different from the first interconnect material, and having a first lower face, and has a first width.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device with air gap and fabricating the same


A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening; a second conductive pattern covering a top surface and sidewalls of the first conductive pattern; an air gap defined between sidewalls of the opening and the second conductive pattern; and a third conductive pattern capping the second conductive pattern and the air gap.. .
Sk Hynix Inc.


new patent

Semiconductor devices having staggered air gaps


A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween.
Samsung Electronics Co., Ltd.


new patent

Semiconductor device and manufacturing the same


In one embodiment, a method of manufacturing a semiconductor device includes forming a plug in a first insulator, forming a first film on the first insulator and the plug, and forming an opening in the first film. The method further includes forming a second insulator in the opening to form an air gap in the opening, removing the first film after forming the second insulator, to expose the plug, and forming an interconnect on the exposed plug..
Kabushiki Kaisha Toshiba


new patent

Semiconductor dies with recesses, associated leadframes, and associated systems and methods


semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess.
Micron Technology, Inc.


new patent

Electronic packages for flip chip devices


Electronic packages are formed from a generally planar leadframe having a plurality of leads coupled to a gan-based semiconductor device, and are encased in an encapsulant. The plurality of leads are interdigitated and are at different voltage potentials..
Navitas Semiconductor Inc.


new patent

Semiconductor device, manufacturing semiconductor device, and electronic device


There is provided a method for manufacturing a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first surface side of the first semiconductor base substrate, a through electrode that is formed to penetrate from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate, and an insulation layer that surrounds a circumference of the through electrode formed inside the first semiconductor base substrate.. .
Sony Corporation


new patent

Semiconductor structure including a thermally conductive, electrically insulating layer


A thermally conductive and electrically insulating layer is provided over a semiconductor structure.. .
Avago Technologies General Ip (singapore) Pte. Ltd


new patent

Heat spreader and forming


The present disclosure provides embodiments for a semiconductor structure including a heat spreader that includes a graphene grid having a first major surface and a second major surface opposite the first major surface. The graphene grid has a plurality of holes, each hole having a first opening in the first major surface and a second opening in the second major surface.
Freescale Semiconductor, Inc.


new patent

Semiconductor module


A semiconductor module has a structure in which a semiconductor device, an insulating sheet, and a cooler are stacked on each other. The semiconductor device includes a semiconductor element, a heat transfer plate that is connected to the semiconductor element, and a resin molding that seals the semiconductor element and the heat transfer plate.
Toyota Jidosha Kabushiki Kaisha


new patent

Apparatuses and methods for semiconductor die heat dissipation


Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader.
Micron Technology, Inc.


new patent

Systems and methods to enhance passivation integrity


A semiconductor device is disclosed in some embodiments. The device includes a substrate, and a layer disposed over the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


new patent

Compound semiconductor device and manufacturing the same


A compound semiconductor device includes a first protection film which covers a surface of a compound semiconductor layer, where the first protection film is an insulating film whose major constituent is si and at least one element between n and o, and a hydrophobic layer containing si—cxhy is formed at a surface thereof.. .
Fujitsu Limited


new patent

Integrated circuit carrier coating


A device includes an integrated circuit (ic) carrier for a semiconductor device, and a coating on the ic carrier. In the presence of an electrical field or a magnetic field, the coating includes a first functional group that attracts anions and a second functional group that attracts cations..
Freescale Semiconductor, Inc.


new patent

Semiconductor device and semiconductor module


A semiconductor device includes a housing with a fragile portion. The fragile unit or portion has a resistance to a pressure or a melting point temperature that is lower than other portions of the housing.
Kabushiki Kaisha Toshiba


new patent

Semiconductor package with elastic coupler and related methods


A semiconductor package includes: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die. The pin includes a reversibly elastically deformable lower portion, which in implementations includes a spring, configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.
Semiconductor Components Industries, Llc


new patent

Method of manufacturing semiconductor device, and probe card


Reliability of an electrical test of a semiconductor wafer is improved. A method of manufacturing a semiconductor device includes a step of performing an electrical test of a semiconductor element by allowing contact portions (tips) of a force terminal (contact terminal) and a sense terminal (contact terminal) held by a probe card (first card) to come into contact with an electrode terminal of a semiconductor wafer.
Renesas Electronics Corporation


new patent

Multiple threshold voltage trigate devices using 3d condensation


A method of forming a multiple threshold voltage p-channel silicon germanium trigate device using (3d) condensation. The method may include forming a first and second fin in a single semiconductor layer, where the first and second fin have similar initial widths; thinning the second fin; performing a (3d) condensation process to condense the germanium within the first and second fin; and thinning the first fin to a similar width as the second fin..
International Business Machines Corporation


new patent

Methods of fabricating semiconductor devices including hard mask patterning


Methods of fabricating semiconductor devices may include forming an isolation region that defines a plurality of fin active regions on a semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate, forming a first hard mask line that crosses first and second fin active regions and an edge bard mask line that crosses an edge fin active region, and forming a gate cut mask having a plurality of gate cut openings. The plurality of gate cut openings may include first and second gate cut openings that have a first width and are adjacent to the first and second fin active regions, respectively, and an edge gate cut opening that is adjacent to the edge fin active region and has a second width that is greater than the first width but smaller than twice a size of the first width..

new patent

Semiconductor device and manufacturing the same


A semiconductor device includes: a first silicon section g1 which contains a p-type impurity and is a gate electrode g of a p-channel type misfet 1p; a second silicon section g2 which contains an n-type impurity and is a gate electrode g of an n-channel type misfet 2n; and an insulation film if1 which is interposed between the first silicon section g1 and the second silicon section g2. Then, a silicide film is formed continuously on surfaces of the first silicon section g1, the insulation film if1 and the second silicon section g2, and the first silicon section g1 and the second silicon section g2 are electrically connected to each other by the silicide film sil.
Renesas Electonics Corporation


new patent

Method of fabricating semiconductor device


A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line..

new patent

Method for fabricating a quasi-soi source-drain multi-gate device


The present invention discloses a method for fabricating a quasi soi source-drain multi-gate device, belonging to a field of manufacturing ultra large scale integrated circuit, the method comprises in sequence the following steps of: forming a fin strip-shaped active region on a first semiconductor substrate; forming a sti isolation layer; depositing a gate dielectric layer and a gate material layer, forming a gate stack structure; forming a doped structure of a source-drain extension region; forming a recessed source-drain structure; forming a quasi soi source-drain isolation layer; in-situ doping an epitaxial source and drain of a second semiconductor material and performing annealing for activating; removing a dummy gate and performing a deposition of a high k metal gate again; and forming a contact and a metal interconnection.. .
Perking University


new patent

Fine patterning methods and methods of fabricating semiconductor devices using the same


A fine-patterning method includes forming a mask layer with lower and upper mask layers on an underlying layer, forming a pair of sacrificial patterns on the mask layer, forming a connection spacer between the sacrificial patterns and first spacers that are spaced apart from each other with the pair of sacrificial patterns interposed therebetween and covering side surfaces of the sacrificial patterns, etching the upper mask layer using the first spacers and the connection spacer as an etch mask to form upper mask patterns, forming second spacers to cover side surfaces of the upper mask patterns, etching the lower mask layer using the second spacers as an etch mask to form lower mask patterns, and etching the underlying layer using the lower mask patterns as an etch mask.. .
Samsung Electronics Co., Ltd.


new patent

Method, apparatus and system for advanced channel cmos integration


At least one method, apparatus and system disclosed involves a semiconductor substrate on which nmos and pmos devices with enhanced current drives may be formed. A first substrate having an enhanced electron mobility is formed.
Globalfoundries Inc.


new patent

Semiconductor device and manufacturing the same


A method for manufacturing a semiconductor device is provided. The method includes the following operations: (i) forming a transistor having a source, a drain and a gate on a semiconductor substrate; (ii) forming a conductive contact located on and in contact with at least one of the source and the drain; and (iii) forming a capacitor having a first electrode and a second electrode on the semiconductor substrate, in which at least one of the first and second electrodes is formed using front-end-of line (feol) processes or middle-end-of line (meol) processes..
Taiwan Semiconductor Manufacturing Co., Ltd.


new patent

Top metal pads as local interconnectors of vertical transistors


An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first semiconductor channel, a first top source/drain region over the first semiconductor channel, and a first top source/drain pad overlapping the first top source/drain region.
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Semiconductor devices and fabrication methods with improved word line resistance and reduced salicide bridge formation


Provided are improved semiconductor memory devices and method for manufacturing such semiconductor memory devices. A method may incorporate the formation of silicide regions in a semiconductor.
Macronix International Co., Ltd.


new patent

Method of enabling seamless cobalt gap-fill


Methods for depositing a contact metal layer in contact structures of a semiconductor device are provided. In one embodiment, a method for depositing a contact metal layer for forming a contact structure in a semiconductor device is provided.
Applied Materials, Inc.


new patent

Electron-beam (e-beam) based semiconductor device features


Electron-beam (e-beam) based semiconductor device features are disclosed. In a particular aspect, a method includes performing a first lithography process to fabricate a first set of cut pattern features on a semiconductor device.
Qualcomm Incorporated


new patent

Composite substrate and producing same


A composite substrate 1 according to the present invention comprises: a supporting substrate 10 that is formed of an insulating material; a semiconductor part 20 that is disposed over the supporting substrate 10; and interfacial inclusions 30 that are present at the interface between the supporting substrate 10 and the semiconductor part 20 and contains ni and fe so that the ratio of ni to fe is 0.4 or more. Consequently, the present invention is able to provide a highly reliable composite substrate wherein the interfacial inclusions 30 are prevented from diffusing into the semiconductor part 20..
Kyocera Corporation


new patent

Semiconductor device including air gaps and fabricating the same


A semiconductor device including air gaps and a method of fabricating the same. The semiconductor device in accordance with an embodiment may include a bit line structure having a bit line formed over a first contact plug, a second contact plug formed adjacent to the first contact plug and the bit line structure, an air gap structure comprising two or more air gaps to surround the second contact plug and have an outer sidewall in contact with the bit line structure, and one or more capping support layers separating the air gaps, a third contact plug capping a part of the air gap structure and being formed over the second contact plug, and a capping layer for capping a remainder of the air gap structure..
Sk Hynix Inc.


new patent

Semiconductor device and manufacturing the same


In one embodiment, a method of manufacturing a semiconductor device includes forming plugs in a first insulator, and forming a first film on the first insulator and the plugs. The method further includes forming openings in the first film to expose the plugs in the openings, and forming a second insulator on side faces of the openings.
Kabushiki Kaisha Toshiba


new patent

Support ring with masked edge


A support ring for semiconductor processing is provided. The support ring includes a ring shaped body defined by an inner edge and an outer edge.
Applied Materials, Inc.


new patent

Vacuum tweezer and manufacturing semiconductor device


A vacuum tweezer includes: a tweezer body including a suction distal end portion that performs vacuum suction of an object to be suctioned; and a light source causing a beam to be condensed at a position on an extension of the suction distal end portion on which a vacuum suction force acts.. .
Mitsubishi Electric Corporation


new patent

Led die dispersal in displays and light panels with preserving neighboring relationship


A method of dispersing semiconductor chips from a wafer of semiconductor chips onto a substrate while preserving the neighboring relationship of each chip to each adjacent chip is disclosed. The method includes dispersing the wafer into sequential columns of semiconductor chips with a first pitch between columns while preserving the neighboring relationship and sequentially dispersing the columns of semiconductor chips into rows of individual chips with a second pitch between rows onto a substrate while preserving the neighboring relationship..

new patent

Semiconductor substrate arrangements and a forming a semiconductor substrate arrangement


A semiconductor substrate arrangement includes a carrier wafer and a plurality of semiconductor substrate pieces fixed to the carrier wafer and distributed laterally over the carrier wafer. The semiconductor substrate pieces of the plurality of semiconductor substrate pieces comprise a hexagonal shape..
Infineon Technologies Ag


new patent

Container storage add-on for bare workpiece stocker


The present invention relates to apparatuses and methods to store and transfer objects, and more particularly to workpiece stocker configurations such as stocker for semiconductor wafers, reticles or carrier boxes.. .
Brooks Ccs Gmbh


new patent

Substrate processing apparatus, manufacturing semiconductor device, and non-transitory computer-readable recording medium


An apparatus and method capable of reducing the footprint of substrate processing system. An apparatus includes a housing chamber including a housing cabinet which houses housing containers for housing substrates, and a housing container carrying mechanism provided on the ceiling of the housing chamber and configured to carry the housing containers..
Hitachit Kokusai Electric Inc.


new patent

Metal film polishing slurry composition, and reducing scratches generated when polishing metal film by using same


The present invention relates to a slurry composition for reducing scratches generated when polishing the metal film in a manufacturing process of a semiconductor integrated circuit, by lowering frictional force so that a temperature of the composition which may rise during the polishing is lowered, the thermal stability of the slurry is improved and the size increase of particles in the slurry is suppressed, and a method for reducing scratches using the same. The method comprises the steps of applying a slurry composition for polishing a metal film to a substrate on which the metal film is formed, the slurry composition containing an organic solvent including a nitrogen atom and a glycol-based organic solvent; and making a polishing pad to be contacted to the substrate and moving the polishing pad with respect to the substrate, thereby removing at least part of the metal film from the substrate..
Dongjin Semichem Co., Ltd.


new patent

Heat treatment method and heat treatment heating substrate by irradiating substrate with light


First irradiation which causes an emission output from a flash lamp to reach its maximum value over a time period in the range of 1 to 20 milliseconds is performed to increase the temperature of a front surface of a semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 1 to 20 milliseconds. This achieves the activation of the impurities.
Screen Holdings Co., Ltd.


new patent

Method for achieving ultra-high selectivity while etching silicon nitride


Methods of selectively etching silicon nitride on a semiconductor substrate by providing silicon to the plasma to achieve high etch selectivity of silicon nitride to silicon-containing materials are provided. Methods involve providing silicon from a solid or fluidic silicon source or both.
Lam Research Corporation


new patent

Pattern forming method and manufacturing semiconductor device


According to one embodiment, a mask material is formed on a processing layer, a mask pattern with a top surface and a bottom surface is formed on the mask material, a protective film is formed on the top surface of the mask pattern, and after the formation of the protective film, the bottom surface of the mask pattern is etched in a depth direction.. .
Kabushiki Kaisha Toshiba


new patent

Dual fin integration for electron and hole mobility enhancement


A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer.
International Business Machines Corporation


new patent

Semiconductor device manufacturing method


To improve the manufacturing yield of a semiconductor device, there is to provide a method of manufacturing a semiconductor device using a multilayer resist, in which before performing water repelling processing for immersion exposure on a wafer, an anti-reflection film, an underlayer film, and an intermediate film applied to a wafer edge portion are eliminated through rinse processing.. .
Renesas Electronics Corporation


new patent

Method for manufacturing semiconductor device, and semiconductor device


With a method for manufacturing a semiconductor device, a semiconductor layer having a protrusion on a main face is formed. The protrusion includes an upper face and side faces.
Nichia Corporation


new patent

Method for doping impurities, manufacturing semiconductor device, and semiconductor device


Impurity elements are doped at a high concentration exceeding a thermodynamic equilibrium concentration into a solid material having an extremely small diffusion coefficient of the impurity element. A method for doping impurities includes steps for depositing source film made of material containing impurity elements with a film thickness on a surface of a solid target object (semiconductor substrate) made from the solid material.
Fuji Electric Co., Ltd.


new patent

Manufacturing a semiconductor device, pattern generating method and nontransitory computer readable medium storing a pattern generating program


According to one embodiment, stepped structure is formed on a semiconductor substrate, a processing film is formed to cover the stepped structure, a resist film is formed on the processing film in such a manner as to be thinner at a higher portion of the stepped structure than at a lower portion of the same, and the resist film and the processing film are etched to flatten the processing film.. .
Kabushiki Kaisha Toshiba


new patent

Method of forming a semiconductor structure


A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided.
United Microelectronics Corp.


new patent

Epitaxial silicon germanium fin formation using sacrificial silicon fin templates


A method of forming semiconductor fins includes forming a plurality of sacrificial template fins from a first semiconductor material; epitaxially growing fins of a second semiconductor material on exposed sidewall surfaces of the sacrificial template fins; and removing the plurality of sacrificial template fins.. .
International Business Machines Corporation


new patent

Method and composition for removing resist, etch residue, and copper oxide from substrates having copper, metal hardmask and low-k dielectric material


A semiconductor processing composition and method for removing photoresist, polymeric materials, etching residues and copper oxide from a substrate comprising copper, low-k dielectric material and tin, tinxoy or w wherein the composition includes water, at least one halide anion selected from cl− or br−, and, where the metal hard mask comprises only tin or tinxoy, optionally at least one hydroxide source.. .
Ekc Technology


new patent

Semiconductor device


A memory cell (101) includes a memory transistor (10a) having channel length l1 and channel width w1, and a plurality of select transistors (10b) each electrically being connected in series with the memory transistor and independently having channel length l2 and channel width w2, wherein each of the memory transistor and the plurality of select transistors includes an active layer (7a) formed from a common oxide semiconductor film, the memory transistor is a transistor which is capable of being irreversibly changed from a semiconductor state where drain current ids depends on gate voltage vg to a resistor state where drain current ids does not depend on gate voltage vg, and channel length l2 is greater than channel length l1.. .
Sharp Kabushiki Kaisha


new patent

Memory controller and operating method thereof


An operating method of a memory controller includes: performing a first hard decision read operation based on a read retry table including an index representing a read environment of a semiconductor memory device, wherein the read retry table defines hard read voltage values for a plurality of hard read voltage levels of a multi-level cell; and performing a second hard decision read operation by independently changing each of the hard read voltage levels based on the hard read voltage values of the read retry table when the first hard decision read operation fails.. .
Sk Hynix Inc.


new patent

Semiconductor memory device


A semiconductor memory device includes a first memory block having a first memory cell transistor and a first select transistor, a second memory block having a second memory cell transistor and a second select transistor, a first select gate line that is electrically connected to a gate of the first select transistor, and a second select gate line that is electrically connected to a gate of the second select transistor. During writing of data to a memory cell transistor in the first block, a first voltage is applied to the first select gate line during a first time period, a second voltage is applied to the second select gate line during a second time period after the first time period, and a third voltage lower than the first voltage is applied to the first select gate line during a third time period after the second time period..
Kabushiki Kaisha Toshiba


new patent

Semiconductor memory device and production method thereof


A semiconductor memory device according to an embodiment comprises a memory cell array including first and second wiring line layers disposed sequentially above memory cells, the first wiring line layer including a first wiring line and a first dummy wiring line, and the second wiring line layer including a second wiring line and a second dummy wiring line, the second wiring line being disposed at the same position in the first direction as the first dummy wiring line, the second dummy wiring line being disposed at the same position in the first direction as the first wiring line, and during an access operation by a control circuit, the first and second wiring lines being electrically connected to at least one of the memory cells, and the first and second dummy wiring lines being fixed at a certain first potential.. .
Kabushiki Kaisha Toshiba


new patent

Semiconductor memory device


A semiconductor memory device capable of a high-accuracy data search is provided. Each of the memory cells can hold two bits of information and includes a first cell and a second cell.
Renesas Electronics Corporation


new patent

Semiconductor storage device and processor system


A semiconductor storage device has a non-volatile memory, a memory controller to carry out write processing to the non-volatile memory using a write pulse, and a write pulse controller to select one of a first write mode for writing to the non-volatile memory and a second write mode for writing to the non-volatile memory with higher electric power consumption than the first write mode at higher speed than the first write mode and, when the first write mode is selected, set a pulse width of the write pulse such that the pulse width is shorter than one cycle of a clock signal used to control access to the non-volatile memory,. .
Kabushiki Kaisha Toshiba


new patent

Electronic device


An electronic device comprising a semiconductor memory unit that may include a cell array including a plurality of storage cells; a first line connected to one ends of the plurality of storage cells; a second line connected to the other ends of the plurality of storage cells; a first driver connected to one end of the first line at a first contact location on one side of the cell array, and configured to apply a first electrical signal to the one end of the first line; and a second driver connected to one end of the second line at a second contact location on a side of the cell array opposing the side of the cell array where the first contact location is located, and configured to apply a second electrical signal to the one end of the second line.. .
Sk Hynix Inc.


new patent

Resistive switching memory with cell access by analog signal controlled transmission gate


In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) a word line pair configured to control access to the programmable impedance element, where the word line pair comprises first and second word lines; (iii) a pmos transistor having a source coupled to the cathode, a drain coupled to a bit line, and a gate coupled to the first word line; and (iv) an nmos transistor having a source coupled to the bit line, a drain coupled to the cathode, and a gate coupled to the second word line.. .
Adesto Technologies Corporation


new patent

Memory controller, nonvolatile semiconductor memory device and memory system


According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command.
Kabushiki Kaisha Toshiba


new patent

Semiconductor memory devices including redundancy memory cells


A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells.
Samsung Electronics Co., Ltd.


new patent

Semiconductor memory device


A semiconductor memory device includes a plurality of memory cells, a data bus connected to a first column of the memory cells, by which data is transferred to and from the memory cells of the first column, a data latch storing data indicating whether the first column is defective or not, and a transistor having a first terminal connected to the data bus, a second terminal connected to a voltage source, and a gate connected to an output of the data latch.. .
Kabushiki Kaisha Toshiba


new patent

Memory device


To provide a memory device where multiple pieces of multilevel data can be written and read. The memory device includes first to fifth transistors, first to fourth capacitors, first to fourth nodes, and first and second wirings.
Semiconductor Energy Laboratory Co., Ltd.


new patent

A gate driver circuit basing on igzo process


The present invention provides a gate driver basing on igzo process, comprising: goas in cascade connection comprising a nth-stage goa, wherein the nth-stage goa further comprising: a pull-up control part 100, a pull-up part 200, a transfer part 300, a pull-down part 400, a pull-down holding part 500, a boost part 600, a first negative supply vss1, a second negative supply vss2, a third negative supply vss3, which are three gradually decreasing negative supplies and pull down an output terminal g(n), a first node q(n), a second node p(n), and a driving single st(n) to prevent the electrical leakage of tfts effectively. And channels of the tft switches of the gate driver basing on the igzo process are oxide semiconductor channels..
Shenzhen China Star Optoelectronics Technology Co., Ltd.


new patent

Method for driving semiconductor device


The resolution of a low-resolution image is made high and a stereoscopic image is displayed. Resolution is made high by super-resolution processing.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Semiconductor fingerprint identification sensor and manufacturing method thereof


Disclosed are a semiconductor fingerprint identification sensor and a method for manufacturing the same. The semiconductor fingerprint identification sensor includes: a sensing area, a control area and an interface area; the sensing area, the control area and the interface area are communicated with one another; a fingerprint information sensed in the sensing area is sent to the control area, and is output through the interface area after being processed in the control area; the sensing area includes an insulation layer, an wiring layer, a substrate layer and a protective layer which are stacked in a sequence, the wiring layer is embedded between the insulation layer and the substrate layer, a sensor array is disposed on a side of the substrate layer being in contact with the protective layer, a via hole corresponding to the sensor array is disposed on the substrate layer, the sensor array is electrically connected with a sensing lead circuit of the wiring layer through the via hole.
Boe Technology Group Co., Ltd.




Semiconductor topics:
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  • Semiconductor Material
  • Electric Conversion
  • Conductive Layer
  • Molybdenum
  • Camera Module
  • Semiconductor Devices
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  • Integrated Circuit
  • Surfactant
  • Photoelectric Conversion
  • Electronic Device
  • Transparent Conductive Oxide


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