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Semiconductor patents



      

This page is updated frequently with new Semiconductor-related patent applications.




Date/App# patent app List of recent Semiconductor-related patents
04/07/16
20160100489 
 Method for manufacturing an integrated circuit package patent thumbnailMethod for manufacturing an integrated circuit package
This disclosure relates to integrated circuit (ic) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die.
Rf Micro Devices, Inc.


04/07/16
20160099715 
 Level shift circuit and semiconductor device patent thumbnailLevel shift circuit and semiconductor device
A level shift circuit includes: a latch circuit (q5, q6, q7, q8) including first (q5, q7) and second (q6, q8) inverter circuits; a first input mos transistor (q1) operating in accordance with an input signal; a second input mos transistor (q2) operating in accordance with an inversion signal of the input signal; and a current-voltage control mos transistor (q9). The latch circuit (q5, q6, q7, q8) outputs a voltage having been converted from the input voltage in level.
Renesas Electronics Corporation


04/07/16
20160099711 
 Semiconductor device, and on-vehicle electronic device and automobile each including semiconductor device patent thumbnailSemiconductor device, and on-vehicle electronic device and automobile each including semiconductor device
A load driving device 10 includes a temperature detector td1 that sets a temperature difference detection signal dt_ot to active when a temperature difference tdif between a temperature ttr of an output transistor t1 and an ambient temperature becomes more than a reference temperature difference tdref1, and sets an over temperature detection signal at_ot to active when the temperature ttr of the output transistor t1 becomes higher than a reference temperature tref1, a current limiter il1 that limits a gs current of the output transistor t1 when any one of the detection signals becomes active, and the output transistor t1 that turns off regardless of an external input signal in when any one of the detection signals becomes active. The temperature detector td1 sets the temperature difference detection signal dt_ot to inactive when the temperature difference tdif between the output transistor temperature ttr and the ambient temperature becomes equal to or less than a reference temperature difference tdref2, and sets the over temperature detection signal at_ot to inactive when the output transistor temperature ttr becomes equal to or lower than a reference temperature tref2..
Renesas Electronics Corporation


04/07/16
20160099704 
 Temperature compensated plate resonator patent thumbnailTemperature compensated plate resonator
The invention relates to a microelectromechanical resonator device comprising a support structure and a semiconductor resonator plate doped to a doping concentration with an n-type doping agent and being capable of resonating in a width-extensional resonance mode. In addition, there is at least one anchor suspending the resonator plate to the support structure and an actuator for exciting the width-extensional resonance mode into the resonator plate.
Teknologian Tutkimuskeskus Vtt Oy


04/07/16
20160099703 
 Temperature compensated beam resonator patent thumbnailTemperature compensated beam resonator
The invention provides a microelectromechanical resonator device comprising a support structure and a resonator manufactured on a (100) or (110) semiconductor wafer, wherein the resonator is suspended to the support structure and comprises at least one beam being doped to a doping concentration of 1.1*1020 cm−3 or more with an n-type doping agent and is being capable of resonating in a length-extensional, flexural resonance or torsional mode upon suitable actuation. In particular, the doping concentration and angle of the beam are chosen so as to simultaneously produce zero or close to zero second order tcf, and even more preferably zero or close to zero first and second order tcfs, for the resonator in said resonance mode, thus providing a temperature stable resonator..
Teknologian Tutkimuskeskus Vtt Oy


04/07/16
20160099702 
 Temperature compensated compound resonator patent thumbnailTemperature compensated compound resonator
The invention concerns microelectromechanical resonators. In particular, the invention provides a resonator comprising a support structure, a doped semiconductor resonator suspended to the support structure by at least one anchor, and actuator for exciting resonance into the resonator.
Teknologian Tutkimuskeskus Vtt Oy


04/07/16
20160099695 
 Semiconductor integrated circuit, variable gain amplifier, and sensing system patent thumbnailSemiconductor integrated circuit, variable gain amplifier, and sensing system
Provided is a semiconductor integrated circuit including a pad pd1 provided on one end side of a resistive element r1 externally provided, a pad pd5 provided on a different end side of the resistive element r1; an operation amplifier a1, a signal line l11 wired between an output terminal of the operation amplifier a1 and the pad pd1, a signal line l21 wired between an inverting input terminal of the operation amplifier a1 and the pad pd5, a esd protection element r11 provided to the signal line l11, and a signal line l31, through which a voltage signal of the pad pd1 is transmitted. The signal line l31 is connected to the pad pd1..
Renesas Electronics Corporation


04/07/16
20160099655 
 Power conversion apparatus patent thumbnailPower conversion apparatus
A power conversion apparatus includes a semiconductor module that includes a main body containing at least one semiconductor element, power terminals projecting from the main body to be connected to a high-voltage dc power supply and high-voltage signal terminals projecting from the main body, and is configured to convert a dc power supplied from the high-voltage dc power supply to an ac power by switching operation of the semiconductor element. The power conversion apparatus further includes a low-voltage component connected to a low-voltage dc power supply and a control circuit board on which a control circuit for controlling the switching operation of the semiconductor element is formed.
Denso Corporation


04/07/16
20160099654 
 Three-level converter and  controlling three-level converter patent thumbnailThree-level converter and controlling three-level converter
A three-level converter and a method for controlling a three-level converter, wherein the third (s31, s32, s33), the fourth (s41, s42, s43) and the fifth (s51, s52, s53) controllable semiconductor switch of a switching branch having, out of all the switching branches, the most positive voltage in its alternating current pole (ac1, ac2, ac3) is controlled to be non-conductive for the whole period of time when the switching branch in question has the most positive voltage in its alternating current pole, and the first (s11, s12, s13), the second (s21, s22, s23) and the sixth (s61, s62, s63) controllable semiconductor switch of a switching branch having, out of all the switching branches, the most negative voltage in its alternating current pole is controlled to be non-conductive for the whole period of time when the switching branch in question has the most negative voltage in its alternating current pole. (fig.
Abb Technology Oy


04/07/16
20160099650 
 Gate-power-supply device and semiconductor circuit breaker using same patent thumbnailGate-power-supply device and semiconductor circuit breaker using same
A gate-power-supply device is provided with an inverter circuit, a transformer, and rectifier circuits. The device includes secondary-side parallel capacitors, connected in parallel to secondary-side coils of the transformer, for cancelling inductance components of the secondary-side coils at the drive frequency of the inverter circuit.
Mitsubishi Electric Corporation


04/07/16
20160099573 

Circuit arrangement for inline voltage supply, use of such a circuit arrangement and device having such a circuit arrangement


In a circuit arrangement for in-line supply of voltage to an electrical or electronic apparatus located in the region of a dc line, a parallel circuit of two diodes oriented in anti-parallel is arranged in the line. When a direct current is flowing between terminals of the circuit arrangement, the anti-parallel diodes permit a small voltage drop between the terminals, irrespective of the direction of flow of the current, which voltage drop is limited to the forward voltage of the diode that is currently forward biased.
Sma Solar Technology Ag


04/07/16
20160099561 

Power dissipating arrangement in a wind turbine


A power dissipating arrangement for dissipating power from a generator in a wind turbine is provided. The generator comprises a plurality of output terminals corresponding to a multi-phase output.
Vestas Wind Systems A/s


04/07/16
20160099550 

Laser apparatus and information acquisition apparatus using the same


A laser apparatus includes an active medium, a first reflection portion, a second reflection portion, a first laser array including a plurality of semiconductor lasers, a third reflection portion configured to reflect at least part of light emitted from the first laser array and transmitted through the active medium, and a fourth reflection portion configured to transmit at least part of light emitted from the first laser array, and to reflect at least part of light reflected by the third reflection portion and transmitted through the active medium. The fourth reflection portion is disposed across the plurality of semiconductor lasers including respective light-emitting regions of the plurality of semiconductor lasers of the first laser array..
Canon Kabushiki Kaisha


04/07/16
20160099549 

Surface-emitting semiconductor laser device and producing the same


A surface-emitting semiconductor laser device includes a substrate and a semiconductor layer disposed on the substrate. The semiconductor layer includes a first semiconductor multilayer film of a first conductivity type, a first spacer layer, an active layer, a second spacer layer, and a second semiconductor multilayer film of a second conductivity type.
Fuji Xerox Co., Ltd.


04/07/16
20160099548 

External cavity with a pair of two fiber bragg gratings at the front and back facet of a laser diode


The first fbg is placed at the front facet of the laser chip, while the second fbg is placed on the back facet of the chip. The two fbgs are used to form an external cavity.

04/07/16
20160099547 

Semiconductor laser light source having an edge-emitting semiconductor body


A semiconductor laser light source comprising an edge-emitting semiconductor body (10) is provided. The semiconductor body (10) contains a semiconductor layer stack (110) having an n-type layer (111), an active layer (112) and a p-type layer (113) which is formed for generating electromagnetic radiation which comprises a coherent portion (21).
Osram Opto Semiconductors Gmbh


04/07/16
20160099543 

Semiconductor laser device


X>½·t·(kx/ky). .

04/07/16
20160099413 

Organic polymer semiconductors with increased interdomain connectivity and mobility


An electronic device, including an organic semiconductor, the organic semiconductor having a first polymer having a first molecular weight and a first length, and a second polymer having a second molecular weight and a second length, wherein the second length is longer than the first length.. .
Palo Alto Research Center Incorporated


04/07/16
20160099412 

N-type organic semiconductor formulations and devices


The present invention discloses an organic semiconductor formulation comprising an organic semiconductor (osc) and an organic phosphorous-containing additive (opa) capable of enhancing the n-type performance of the organic semiconductor. The semiconductor formulation disclosed herein is suitable for producing n-type semiconductor thin films for use in a variety of electronic, optical, or optoelectronic devices such as organic thin film transistors, organic photovoltaics, and organic light emitting devices..

04/07/16
20160099399 

Method for manufacturing a thermoelectric module based on a polymer film


A method of manufacturing a thermoelectric module including a substrate and at least one conductive or semiconductor polymer film deposited on a surface of the substrate, the method including a step of manufacturing the conductive polymer film independently from the surface of the substrate and transferring the conductive polymer film onto the surface of the substrate. The transfer comprises: immersing the conductive polymer film in a transfer bath to obtain a conductive polymer film which is solvated, self-supporting, and capable of matching the shape of the substrate surface; applying the conductive polymer film in its solvated state on the substrate to match the shape of the surface thereof; and drying the solvated conductive polymer film..
Commissariat A L'energie Atomique Et Aux Energies Alternatives


04/07/16
20160099395 

Led leadframe or led substrate, semiconductor device, and manufacturing led leadframe or led substrate


An led leadframe or led substrate includes a main body portion having a mounting surface for mounting an led element thereover. A reflection metal layer serving as a reflection layer for reflecting light from the led element is disposed over the mounting surface of the main body portion.
Dai Nippon Printing Co., Ltd.


04/07/16
20160099390 

Optoelectronic semiconductor component


An optoelectronic semiconductor component includes a luminescent diode chip including a radiation passage face through which primary electromagnetic radiation leaves the luminescent diode chip when in operation, and a filter element that covers the radiation passage face of the luminescent diode chip at least in places, wherein the filter element prevents passage of some of the primary electromagnetic radiation in the uv range, and the filter element consists of a ii-vi compound semiconductor material.. .
Osram Opto Semiconductors Gmbh


04/07/16
20160099389 

Light-emitting dies incorporating wavelength-conversion materials and related methods


In accordance with certain embodiments, semiconductor dies are embedded within polymeric binder to form, e.g., freestanding white light-emitting dies and/or composite wafers containing multiple light-emitting dies embedded in a single volume of binder.. .

04/07/16
20160099387 

Semiconductor light emitting device


A semiconductor light emitting device includes a package body having first and second surfaces being opposed to each other, first and second external terminal blocks disposed in opposite end portions of the package body, respectively, and having portions exposed to surfaces of the package body, respectively. A wavelength converting material layer is disposed between the first and second external terminal blocks and has a first surface substantially coplanar with the first surface of the package body, and a second surface opposing the first surface of the wavelength converting material layer.
Samsung Electronics Co., Ltd.


04/07/16
20160099386 

Light emitting diode and manufacturing method thereof


A light emitting diode includes: a substrate; an n-type semiconductor layer disposed on the substrate; an active layer disposed on the n-type semiconductor layer; a p-type semiconductor layer disposed on the active layer; a first electrode disposed on the p-type semiconductor layer and made of a metal oxide; a second electrode disposed on the first electrode and made of graphene; a p-type electrode disposed on the second electrode; and an n-type electrode disposed on the n-type semiconductor layer, wherein a work function of the first electrode is less than a work function of the p-type semiconductor layer, but is greater than a to work function of the second electrode.. .
Electronics And Telecommunications Research Institute


04/07/16
20160099385 

Method for manufacturing vertical type light emitting diode, vertical type light emitting diode, manufacturing ultraviolet ray light emitting diode, and ultraviolet ray light emitting diode


A vertical type light emitting diode includes a nitride semiconductor having a p-n conjunction structure with a transparent material layer formed on a p type clad layer, the transparent material layer having a refractive index different from that of the p type clad layer and having a pattern structure of mesh, punched plate, or one-dimensional grid form, etc. A reflective metal electrode layer is formed on the transparent material layer as a p-electrode.
Korea Polytechnic University Industry Academic Cooperation Foundation


04/07/16
20160099384 

Light emitting device


A light emitting device includes a light emitting structure having a plurality of light emitting regions including a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode in one of the light emitting regions, a second electrode in another of the light emitting regions, and at least one connection electrode to sequentially connect the light emitting regions in series. The light emitting regions connected in series are divided into 1st to ith light emitting region groups.
Lg Innotek Co., Ltd.


04/07/16
20160099383 

Semiconductor device and manufacturing the same


A semiconductor device including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer which are sequentially stacked; a first conductivity type upper electrode portion and a first conductivity type lower electrode portion disposed to correspond to each other with the first conductivity type semiconductor layer interposed therebetween; a second conductivity type upper electrode portion and a second conductivity type lower electrode portion disposed to correspond to each other with the first and second conductivity type semiconductor layers interposed therebetween; and a second conductivity type electrode connection portion electrically connecting the second conductivity type upper electrode portion and the second conductivity type lower electrode portion.. .
Lg Electronics Inc.


04/07/16
20160099381 

Epitaxy base, semiconductor light emitting device and manufacturing methods thereof


An epitaxy base including a substrate and a nucleating layer disposed on the substrate. The nucleating layer is an aln layer with a single crystal structure.
Playnitride Inc.


04/07/16
20160099378 

Method of fabricating semiconductor light emitting device


A method of fabricating a semiconductor light emitting device includes forming a first conductivity type semiconductor layer, forming an active layer by alternately forming a plurality of quantum well layers and a plurality of quantum barrier layers on the first conductivity type semiconductor layer, and forming a second conductivity type semiconductor layer on the active layer. The plurality of quantum barrier layers include at least one first quantum barrier layer adjacent to the first conductivity type semiconductor layer and at least one second quantum barrier layer adjacent to the second conductivity type semiconductor layer.

04/07/16
20160099376 

Method of manufacturing nanostructure semiconductor light-emitting device


According to an example embodiment, a method of manufacturing a nanostructure semiconductor light-emitting device includes forming nanocores of a first-conductivity type nitride semiconductor material on abase layer to be spaced apart from each other, and forming a multilayer shell including an active layer and a second-conductivity type nitride semiconductor layers on surfaces of each of the nanocores. At least a portion the multilayer shell is formed by controlling at least one process parameter of a flux of source gas, a flow rate of source gas, a chamber pressure, a growth temperature, and a growth rate so as to have a higher film thickness uniformity..
Samsung Electronics Co., Ltd.


04/07/16
20160099374 

Semiconductor device


A semiconductor device used for a semiconductor relay includes: a first diode; a second diode; an electric field shield film for covering the second semiconductor island region, where the second diode is formed; and a wiring for electrically connecting the first diode to the second diode. The wiring is arranged so as to cross above a silicon oxide film surrounding the second semiconductor island region.
Renesas Electronics Corporation


04/07/16
20160099372 

Gate-controlled charge modulated device for cmos image sensors


A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region.
Stratio Inc.


04/07/16
20160099371 

Back side illuminated image sensor with guard ring region reflecting structure


A photon detector includes a single photon avalanche diode (spad) disposed proximate to a front side of a semiconductor layer. The spad includes a multiplication junction that is reversed biased above a breakdown voltage such that light directed into the spad through a backside of the semiconductor layer triggers an avalanche multiplication process.
Omnivision Technologies, Inc.


04/07/16
20160099368 

Nanostructured units formed inside a silicon material and the manufacturing process to perform them therein


The invention bears on elementary nanoscale units nanostructured-formed inside a silicon material and the manufacturing process to implement them. Each elementary nanoscale unit is created by means of a limited displacement of two si atoms outside a crystal elementary unit.
Segton Advanced Technology Sas


04/07/16
20160099361 

Element and photovoltaic cell


The invention provides an element including a semiconductor substrate and an electrode disposed on the semiconductor substrate, the electrode being a sintered product of a composition for an electrode that includes phosphorus-containing copper alloy particles, glass particles and a dispersing medium, and the electrode includes a line-shaped electrode having an aspect ratio, which is defined as electrode short length : electrode height, of from 2:1 to 250:1.. .
Hitachi Chemical Company, Ltd.


04/07/16
20160099360 

Wafer for solar cell, producing wafer for solar cell, producing solar cell, and producing solar cell module


In a wafer for solar cell before acid texturing of the present invention, produced from a polycrystalline semiconductor wafer cut out using a bonded abrasive wire, an amorphous layer does not exist, and irregularities caused due to the cutting using the bonded abrasive wire are left in at least one surface of the wafer for solar cell.. .

04/07/16
20160099358 

Method of manufacturing semiconductor device


A semiconductor device including a nonvolatile memory cell and a field effect transistor together is improved in performance. In a method of manufacturing a semiconductor device, a hydrogen-containing insulating film is formed before heat treatment of a semiconductor wafer, the hydrogen-containing insulating film covering a gate electrode and agate insulating film in a region that will have a memory cell therein, and exposing a region that will have therein a misfet configuring a peripheral circuit.
Renesas Electronics Corporation


04/07/16
20160099356 

Semiconductor device, manufacturing method thereof, and display device


A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a tft which is in an on state is reduced to increase an on current.
Semiconductor Energy Laboratory Co., Ltd.


04/07/16
20160099353 

Semiconductor device


A semiconductor device in which release of oxygen from side surfaces of an oxide semiconductor film including c-axis aligned crystal parts can be prevented is provided. The semiconductor device includes a first oxide semiconductor film, a second oxide semiconductor film including c-axis aligned crystal parts, and an oxide film including c-axis aligned crystal parts.
Semiconductor Energy Laboratory Co., Ltd.


04/07/16
20160099351 

Self-aligned slotted accumulation-mode field effect transistor (accufet) structure and method


This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers.

04/07/16
20160099350 

Semiconductor device


A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and extends in a first direction with a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped semiconductor layer resides on the fin-shaped semiconductor layer.
Unisantis Electronics Singapore Pte. Ltd.


04/07/16
20160099349 

Semiconductor device with non-isolated power transistor with integrated diode protection


A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.. .
Freescale Semiconductor, Inc.


04/07/16
20160099347 

Laterally diffused metal oxide semiconductor device and manufacturing method therefor


Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (s210); coating a photoresist on the surface of the wafer (s220); performing photoetching by using a first photoetching mask, and exposing a first implantation window after development (s230); performing ion implantation via the first implantation window to form a drift region in the substrate (s240); coating one layer of photoresist on the surface of the wafer again after removing the photoresist (s250); performing photoetching by using the photoetching mask of the oxide layer of the drift region (s260); and etching the oxide layer to form the oxide layer of the drift region (s270). Further provided is a laterally diffused metal oxide semiconductor device..
Csmc Technologies Fab1 Co., Ltd.


04/07/16
20160099346 

Semiconductor device


A semiconductor device including a gate structure, a source region, a drain region, a first conductive type epitaxial layer, a high voltage second conductive type well, a linear graded high voltage first conductive type well and a first conductive type buried layer is provided. The first conductive type buried layer is located within the first conductive type epitaxial layer and below the high voltage second conductive type well, and a length of the first conductive type buried layer is smaller than a length of the high voltage second conductive type well..
Nuvoton Technology Corporation


04/07/16
20160099344 

Facilitating fabricating gate-all-around nanowire field-effect transistors


Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s).
Globalfoundries Inc.


04/07/16
20160099343 

Tunneling field effect transistor and methods of making such a transistor


One illustrative method of forming a tfet device includes forming a first semiconductor material that extends for a full length of a drain region, a gate region and a source region of the device, masking the drain region while exposing at least a portion of the gate region and exposing the source region, forming a second semiconductor material above the gate region and above the source region, forming a third semiconductor material above the second semiconductor material and above the gate region and above the source region, the third semiconductor material being doped with an opposite type of dopant material than in the first semiconductor material, masking the drain region, and forming a gate structure above at least a portion of the exposed gate region.. .
Globalfoundries Inc.


04/07/16
20160099342 

Structure and method to increase contact area in unmerged epi integration for cmos finfets


Source/drain contact structures with increased contact areas for a multiple fin-based complementary metal oxide semiconductor field effect transistor (cmosfet) having unmerged epitaxial source/drain regions and methods for forming such source/drain contact structures are provided by forming wrap-around source/drain contact structures for both n-type finfets and p-type finfets. Each of first source/drain contact structures for the n-type finfets includes at least one first conductive plug encapsulating epitaxial first source/drain regions on one side of a gate structure, while each of second source/drain contact structures for the p-type finfets includes at least a contact metal layer portion encapsulating epitaxial second source/drain regions on one side of the gate structure, and a second conductive plug located over a top surface of the contact metal layer portion..
International Business Machines Corporation


04/07/16
20160099341 

High breakdown voltage ldmos device


A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (ldmos) device (40) has a semiconductor-on-insulator (soi) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first ldmos region (81) and a substantially asymmetric, laterally edge-proximate, second ldmos region (83). A deep trench isolation (dti) wall (60) substantially laterally terminates the laterally edge-proximate second ldmos region (83).
Freescale Semiconductor, Inc.


04/07/16
20160099340 

High voltage metal-oxide-semiconductor transistor device and forming the same


A hvmos transistor device is provided. The hvmos has a substrate, a gate structure, a drain region and a source region, a base region and a gate dielectric layer.
United Microelectronics Corp.


04/07/16
20160099337 

Gate structure having designed profile and forming the same


A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a metal gate structure having curved sidewalls formed over a substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


04/07/16
20160099335 

Semiconductor device and manufacturing the same


A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.. .
Fujitsu Limited


04/07/16
20160099334 

Bipolar transistor manufacturing method


A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.. .
Stmicroelectronics Sa


04/07/16
20160099332 

Partial sacrificial dummy gate with cmos device with high-k metal gate


A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.. .
International Business Machines Corporation


04/07/16
20160099331 

Self-aligned dual-metal silicide and germanide formation


A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet.
Taiwan Semiconductor Manufacturing Company, Ltd.


04/07/16
20160099330 

Semiconductor device with nanowires in different regions at different heights


A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels.

04/07/16
20160099329 

Suspended body field effect transistor


A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed.
Globalfoundries Inc.


04/07/16
20160099328 

Method of forming nanowires


According to another embodiment, a semiconductor structure is provided. The structure includes: a substrate; a first nanowire over the substrate; and a second nanowire over the substrate and substantially symmetric with the first nanowire..
Taiwan Semiconductor Manufacturing Company Limited


04/07/16
20160099325 

Dual oxide trench gate power mosfet using oxide filled trench


A power mosfet device including a semiconductor layer, an active trench formed in the semiconductor layer and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the active trench by a liner oxide layer having a first thickness, and a termination trench formed in the semiconductor layer apart from the active trench and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the termination trench by the liner oxide layer having a second thickness greater than the first thickness.. .
Alpha And Omega Semiconductor Incorporated


04/07/16
20160099324 

Structure and formation semiconductor device with gate stack


A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


04/07/16
20160099323 

Semiconductor structures and methods of fabrication of same


Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening.
Micron Technology, Inc.


04/07/16
20160099322 

Semiconductor devices with sidewall spacers of equal thickness


semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack.
International Business Machines Corporation


04/07/16
20160099321 

Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers


A semiconductor device includes a silicide contact region positioned at least partially in a semiconductor layer, an etch stop layer positioned above the semiconductor layer, and a dielectric layer positioned above the etch stop layer. A contact structure that includes a conductive contact material extends through at least a portion of the dielectric layer and through an entirety of the etch stop layer to the silicide contact region, and a silicide protection layer is positioned between sidewalls of the etch stop layer and sidewalls of the contact structure..
Globalfoundries Inc.


04/07/16
20160099320 

Semiconductor composite film with heterojunction and manufacturing method thereof


The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface.
Richtek Technology Corporation


04/07/16
20160099319 

Semiconductor wafer including a monocrystalline semiconductor layer spaced apart from a poly template layer


A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline.
Semiconductor Components Industries, Llc


04/07/16
20160099318 

Structure and transient voltage suppression devices with a two-region base


A transient voltage suppression (tvs) device and a method of forming the device are provided. The tvs device includes a first layer of wide band-gap semiconductor material formed of a first conductivity type material, a second layer of wide band-gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, the second layer including a first concentration of dopant.
General Electric Company


04/07/16
20160099317 

Vertical semiconductor devices including superlattice punch through stop layer and related methods


A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion.
Mears Technologies, Inc.


04/07/16
20160099316 

Semiconductor device and manufacturing method thereof


In a silicon carbide semiconductor device having a trench type mos gate structure, the present invention makes it possible to inhibit the operating characteristic from varying. A p-type channel layer having an impurity concentration distribution homogeneous in the depth direction at the sidewall part of a trench is formed by applying angled ion implantation of p-type impurities to a p-type body layer formed by implanting ions having implantation energies different from each other two or more times after the trench is formed.
Renesas Electronics Corporation


04/07/16
20160099315 

Nanotube semiconductor devices


semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer.
Alpha And Omega Semiconductor Incorporated


04/07/16
20160099314 

Method of forming a semiconductor device and structure therefor


In one embodiment, a method of forming an mos transistor includes forming a threshold voltage (vth) of the mos transistor to have a first value at interior portions of the mos transistor and a second value at other locations within the mos transistor that are distal from the interior portion wherein the second value is less than the first value.. .
Semiconductor Components Industries, Llc


04/07/16
20160099313 

Semiconductor structure for a transistor and fabricating the same


A semiconductor structure includes a substrate and a fin. The fin extends from the substrate and is formed with a hole therethrough.
Taiwan Semiconductor Manufacturing Company Limited


04/07/16
20160099312 

Nanowire fabrication method and structure thereof


A method of providing an out-of-plane semiconductor structure and a structure fabricated thereby is disclosed. The method comprises acts of: providing a substrate defining a major surface; providing a template layer having a predetermined template thickness on the major surface of the substrate; forming a recess in the template layer having a recess pattern and a recess depth smaller than the template thickness; and epitaxilally growing a semiconductor structure from the recess.
Taiwan Semiconductor Manufacturing Company Limited


04/07/16
20160099311 

Semiconductor structure and a processing a carrier


According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage.. .
Infineon Technologies Ag


04/07/16
20160099310 

Semiconductor device integrating high and low voltage devices


The present invention is directed to a method for forming multiple active components, such as bipolar transistors. Mosfets, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components.
Alpha & Omega Semiconductor Incorporated


04/07/16
20160099309 

Method for growing iii-v epitaxial layers


Disclosed are methods of growing iii-v epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer.
Epigan Nv


04/07/16
20160099308 

Oxide terminated trench mosfet with three or four masks


An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region.
Alpha And Omega Semiconductor Incorporated


04/07/16
20160099307 

Termination design by metal strapping guard ring trenches shorted to a body region to shrink termination area


This invention discloses a semiconductor power device formed in a semiconductor substrate of a first conductivity type comprises an active cell area and a termination area surrounding the active cell area and disposed near edges of the semiconductor substrate. The termination area includes a plurality of trenches filled with a conductivity material forming a shield electrode and insulated by a dielectric layer along trench sidewalls and trench bottom surface wherein the trenches extending vertically through a body region of a second conductivity type near a top surface of the semiconductor substrate and further extending through a surface shield region of the first conductivity type.
Alpha And Omega Semiconductor Incorporated


04/07/16
20160099302 

Embedded metal-insulator-metal capacitor


A method of manufacturing a semiconductor device comprising a capacitor structure is provided, including the steps of forming a first metallization layer comprising a first dielectric layer and a first conductive layer functioning as a lower electrode for the capacitor structure over a semiconductor substrate, forming a barrier layer functioning as a capacitor insulator for the capacitor structure on the first metallization layer, forming a metal layer on the barrier layer and etching the metal layer to form an upper electrode of the capacitor structure.. .
Globalfoundries Inc.


04/07/16
20160099301 

Structure of integrated inductor


This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure.
Realtek Semiconductor Corporation


04/07/16
20160099297 

Flexible active matrix display


High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate.
Globalfoundries Inc.


04/07/16
20160099292 

Resistance-change semiconductor memory


According to one embodiment, a memory includes first to fourth memory cells aligned in a first direction. Each of the first to fourth memory cells comprises a cell transistor having a gate connected to a word line extending in a second direction crossing the first direction and a resistive memory element having one end connected to a first source/drain region of the cell transistor.
Kabushiki Kaisha Toshiba


04/07/16
20160099291 

Metal line connection for improved rram reliability, semiconductor arrangement comprising the same, and manufacture thereof


Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array.
Taiwan Semiconductor Manufacturing Co., Ltd.


04/07/16
20160099289 

Semiconductor memory device


A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells.
Kabushiki Kaisha Toshiba


04/07/16
20160099286 

Semiconductor device including image pick up device


The performance of a semiconductor device is improved by preventing 1/f noise from being generated in a peripheral transistor, in the case where the occupation area of photodiodes, which are included in each of a plurality of pixels that form an image pickup device, is expanded. In the semiconductor device, the gate electrode of an amplification transistor is formed by both a gate electrode part over an active region and a large width part that covers the boundary between the active region and an element isolation region and the active region near the boundary and that has a gate length larger than that of the gate electrode part..
Renesas Electronics Corporation


04/07/16
20160099283 

Photosensor with channel region having center contact


A pixel cell includes a charge accumulation region having a second doping polarity buried completely in a semiconductor substrate having a first doping polarity beneath a first surface. The charge accumulation region accumulates image charge in response to light directed through a second surface.
Omnivision Technologies, Inc.


04/07/16
20160099278 

Back-illuminated integrated imaging device with simplified interconnect routing


A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels.
Stmicroelectronics (crolles 2) Sas


04/07/16
20160099267 

Cmos image sensor for reducing dead zone


An image sensor such as a complementary metal-oxide-semiconductor (cmos) image sensor and a method of manufacturing the same are provided. The cmos image sensor includes: a semiconductor substrate including a first surface and a third surface formed by removing a part of the semiconductor substrate from a second surface opposite to the first surface; a plurality of active regions which are formed between the first surface and the third surface and each of which includes a photoelectric conversion element generating charges in response to light input through the third surface; and an isolation region vertically formed from either of the first and third surfaces to isolate the active regions from one another.
Samsung Electronics Co., Ltd.


04/07/16
20160099266 

Self-aligned isolation structures and light filters


An image sensor includes a semiconductor layer with a plurality of photodiodes. A plurality of isolation structures is disposed in the back side of the semiconductor layer between individual photodiodes in the plurality of photodiodes.
Omnivision Technologies, Inc.


04/07/16
20160099262 

Hybrid pixel control circuits for light-emitting diode display


An electronic device may include a display. The display may be formed by an array of light-emitting diodes mounted to the surface of a substrate.
Apple Inc.


04/07/16
20160099259 

Wiring layer and manufacturing method therefor


To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator.
Semiconductor Energy Laboratory Co., Ltd.


04/07/16
20160099258 

Semiconductor device and electronic device


To provide a novel semiconductor device or a semiconductor device capable of operating at high speed. The semiconductor device includes a plurality of circuits each having a function of storing data and a wiring el.
Semiconductor Energy Laboratory Co., Ltd.


04/07/16
20160099256 

Semiconductor memory device and manufacturing same


According to one embodiment, a semiconductor memory device includes a substrate; a memory cell array including a plurality of memory cells and stacked on the substrate; a first transistor; an interlayer insulating layer covering the first transistor; and a first contact portion. The first transistor includes a first gate insulating film which is disposed on the substrate, a first gate electrode which is disposed on the first gate insulating film, and a first semiconductor layer which includes an upper surface at a higher position than an interface between the substrate and the first gate insulating film and a bottom surface at a deeper position than the interface between the substrate and the first gate insulating film.
Kabushiki Kaisha Toshiba


04/07/16
20160099255 

Three dimensional stacked semiconductor structure and manufacturing the same


A 3d stacked semiconductor structure is provided, comprising a plurality of multi-layered pillars formed on a substrate and spaced apart from each other, a plurality of first conductors formed between the adjacent multi-layered pillars, a plurality of charging-trapping layers formed on the substrate and on the sidewalls of the multi-layered pillars for separating the first conductor and the multi-layered pillars, and a second conductor formed on the first conductors and on the charging-trapping layers. One of the multi-layered pillars comprises a plurality of insulating layers and a plurality of conductive layers arranged alternately.
Macronix International Co., Ltd.


04/07/16
20160099251 

Semiconductor device


An insulating film, which is sandwiched between a gate electrode formed on an soi layer constituting an soi substrate and an epitaxial layer formed on the soi layer and including a high-concentration diffusion region and is formed in contact with a side wall of the gate electrode, is set as a target of dielectric breakdown in a write operation in an anti-fuse element.. .
Renesas Electronics Corporation


04/07/16
20160099250 

Three dimensional nand device with silicon germanium heterostructure channel


A method of making a monolithic three dimensional nand string including forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one opening in the stack, forming at least a portion of a memory film in the at least one opening and forming a first portion of a semiconductor channel followed by forming a second portion of the semiconductor channel in the at least one opening. The second portion of the semiconductor channel comprises silicon and germanium and contains more germanium than a first portion of the semiconductor channel which is located closer to the memory film than the second portion..
Sandisk Technologies Inc.


04/07/16
20160099249 

Integrated fin and strap structure for an access transistor of a trench capacitor


At least one dielectric pad layer is formed on a semiconductor-on-insulator (soi) substrate. A deep trench is formed in the soi substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the soi substrate.
International Business Machines Corporation


04/07/16
20160099248 

Semiconductor memory device with improved active area/word line layout


One semiconductor device includes a bit line extending in a straight line in an x direction, a first and a second horizontal active region extending in the x direction, and a sloped active region arranged between the first and the second horizontal regions and inclined with respect to the x direction, an active region arranged at the center of a bit line impurity diffusion region, a first word line arranged in the first horizontal active region segment, a second word line arranged in the second horizontal active region segment, and a third and a fourth word line arranged in the sloped active region segment next to each other with the bit line impurity diffusion region interposed therebetween.. .
Ps5 Luxco S.a.r.l.


04/07/16
20160099247 

Semiconductor devices with capacitors


A semiconductor device includes bottom electrodes two-dimensionally arranged on a substrate and transistors connected to the bottom electrodes, respectively. Each of the bottom electrodes may include first side surfaces facing each other in a first direction and second side surfaces facing each other in a second direction crossing the first direction.

04/07/16
20160099246 

Structure and method to increase contact area in unmerged epi integration for cmos finfets


Source/drain contact structures with increased contact areas for a multiple fin-based complementary metal oxide semiconductor field effect transistor (cmosfet) having unmerged epitaxial source/drain regions and methods for forming such source/drain contact structures are provided by forming wrap-around source/drain contact structures for both n-type finfets and p-type finfets. Each of first source/drain contact structures for the n-type finfets includes at least one first conductive plug encapsulating epitaxial first source/drain regions on one side of a gate structure, while each of second source/drain contact structures for the p-type finfets includes at least a contact metal layer portion encapsulating epitaxial second source/drain regions on one side of the gate structure, and a second conductive plug located over a top surface of the contact metal layer portion..
International Business Machines Corporation


04/07/16
20160099245 

Semiconductor devices with sidewall spacers of equal thickness


semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack.
International Business Machines Corporation


04/07/16
20160099244 

Methods of forming semiconductor devices and structures thereof


Methods of forming semiconductor devices and structures thereof are disclosed. In some embodiments, a semiconductor device includes a substrate that includes fins.
Taiwan Semiconductor Manufacturing Company, Ltd.


04/07/16
20160099243 

Semiconductor device and manufacturing the same


A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction.
Samsung Electronics Co., Ltd.


04/07/16
20160099242 

Semiconductor device employing trenches for active gate and isolation


A semiconductor device includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer including a first trench gate; a second trench formed in the semiconductor layer and extending into the substrate and including a second trench gate; a first transistor device formed in the semiconductor layer adjacent the first trench. The second trench encircles active area of the first transistor device to provide electrical isolation of the first transistor device..
Alpha And Omega Semiconductor Incorporated


04/07/16
20160099241 

N-type metal oxide semiconductor (nmos) transistor for electrostatic discharge (esd)


One or more techniques or systems for forming an n-type metal oxide semiconductor (nmos) transistor for electrostatic discharge (esd) are provided herein. In some embodiments, the nmos transistor includes a first region, a first n-type plus (np) region, a first p-type plus (pp) region, a second np region, a second pp region, a shallow trench isolation (sti) region, and a gate stack.
Taiwan Semiconductor Manufacturing Company Limited


04/07/16
20160099240 

Integrated electrostatic discharge (esd) clamping


A method of fabricating a laterally diffused metal-oxide-semiconductor (ldmos) transistor device having a bipolar transistor for electrostatic discharge (esd) protection includes doping a substrate to form a body region of the ldmos transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the ldmos transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the ldmos transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the ldmos transistor device in the substrate, and to form an emitter region of the bipolar transistor within the body region.. .
Freescale Seminconductor, Inc.


04/07/16
20160099239 

Methods, apparatus and system for reduction of power consumption in a semiconductor device


At least one method, apparatus and system disclosed herein involves performing power reduction process on a finfet device. A first design is provided.
Globalfoundries Inc.


04/07/16
20160099236 

Light emitting lamp


Disclosed is a light emitting lamp including a light source module including at least one light source and a light guide layer disposed on a substrate burying the at least one light source, and a housing accommodating the light source module, and the at least one light source includes a body having a cavity, a first lead frame including one end exposed to the cavity and the other end passing through the body and exposed to one surface of the body, a second lead frame including one end exposed to one portion of the surface of the body, the other end exposed to the another portion of the surface of the body, and an intermediate part exposed to the cavity, and at least one light emitting chip including a first semiconductor layer, an active layer and a second semiconductor layer, and disposed on the first lead frame.. .
Lg Innotek Co., Ltd.


04/07/16
20160099232 

Fingerprint recognition semiconductor device and semiconductor device


A fingerprint recognition semiconductor device includes an insulation layer, a wiring pattern formed on a lower surface of the insulation layer, and a sensor element flip-chip-connected to the wiring pattern. The sensor element includes an active surface, including a sensor portion that recognizes a fingerprint, and a rear surface, located at a side opposite to the active surface.
Shinko Electric Industries Co., Ltd.


04/07/16
20160099231 

Semiconductor package assembly


The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package stacked on the first semiconductor package.
Mediatek Inc.


04/07/16
20160099230 

Multi-chip package, test system and operating the same


A multi-chip package includes: a plurality of semiconductor chips that are coupled with each other through normal through silicon vias and repair through silicon vias; a state detection device suitable for detecting connection states of the normal through silicon vias and the repair through silicon vias; and a repair control device suitable for comparing the connection state of the normal through silicon vias with the connection state of the repair through silicon vias, and controlling whether to perform a repair operation.. .
Sk Hynix Inc.


04/07/16
20160099229 

Semiconductor devices having through electrodes, semiconductor packages including the same, methods of manufacturing the same, electronic systems including the same, and memory cards including the same


A semiconductor device includes a substrate having a first surface and a second surface that are opposite to each other, a plurality of through electrodes penetrating the substrate and extending from the first surface to the second surface, front-side bumps disposed on the first surface and connected to odd-numbered through electrodes among the plurality of through electrodes, and backside bumps disposed on the second surface and connected to even-numbered through electrodes among the plurality of through electrodes. Related semiconductor packages, fabrication methods, electronic systems and memory cards are also provided..
Sk Hynix Inc.


04/07/16
20160099228 

Method and die-to-die pad contact


A semiconductor device includes at least a first semiconductor die and a second semiconductor die. The first semiconductor dies comprises a first and second side, and includes at least a first contact pad located on the first side of the first semiconductor die.
Hgst Netherlands B.v.


04/07/16
20160099224 

Semiconductor device and manufacturing the same


A semiconductor device according to the present invention includes an insulating substrate having a circuit pattern, semiconductor elements bonded on the circuit pattern with a brazing material, and a wiring terminal bonded with a brazing material on an electrode provided on each of the semiconductor elements on an opposite side of the circuit pattern, in which a part of the wiring terminal is in contact with the insulating substrate, and insulated from the circuit pattern.. .
Mitsubishi Electric Corporation


04/07/16
20160099223 

Semiconductor device and manufacturing method thereof


A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (ppi) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the ppi by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the ppi and around the metallic paste and the conductive bump.. .
Taiwan Semiconductor Manufacturing Company Ltd.


04/07/16
20160099221 

Semiconductor structure and manufacturing method thereof


A semiconductor structure includes a semiconductive substrate, a post passivation interconnect (ppi) and a polymer layer. The ppi is disposed above the semiconductive substrate and includes a landing area for receiving a conductor.
Taiwan Semiconductor Manufacturing Company Ltd.


04/07/16
20160099219 

Semiconductor device having features to prevent reverse engineering


It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques.
Secure Silicon Layer, Inc.


04/07/16
20160099218 

Semiconductor package and manufacturing the same


Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the substrate, wherein the mold is formed to cover the semiconductor device such that at least one inner side surface of the mold has a slope; providing a molding material into the mold to encapsulate the semiconductor device; removing the mold from the substrate; and forming an electromagnetic shielding (ems) layer to cover a top surface and side surfaces of the molding material..
Samsung Electronics Co., Ltd.


04/07/16
20160099216 

Semiconductor device structure and forming the same


A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


04/07/16
20160099214 

Flexible electronic circuits with embedded integrated circuit die and methods of making and using the same


Flexible integrated circuit (ic) modules, flexible ic devices, and methods of making and using flexible ic modules are presented herein. A flexible integrated circuit module is disclosed which includes a flexible substrate and a semiconductor die attached to the flexible substrate.
Mc10, Inc.


04/07/16
20160099213 

Semiconductor package


A semiconductor package includes a package substrate with a cavity, a plurality of semiconductor chips vertically stacked in the cavity, a first insulating layer on a first surface of the package substrate, a first interconnection layer on the first insulating layer, a second insulating layer on a second surface of the package substrate opposite the first surface, and a second interconnection layer on the second insulating layer.. .
Samsung Electronics Co., Ltd.


04/07/16
20160099210 

Semiconductor package and manufacturing the same


Disclosed herein are a semiconductor package and a method of manufacturing the same, which allows a conductive path to be provided to connect upper and lower portions of the semiconductor package. A semiconductor package according to the present invention includes a semiconductor chip, a substrate including an accommodating portion to accommodate the semiconductor chip, a sealing material configured to mold the semiconductor chip and the substrate to be integrated, a through wiring configured to vertically pass through the substrate, a wiring portion configured to electrically connect the semiconductor chip and one side of the through wiring, and an external connection portion to electrically connected to the other side of the through wiring and configured to be able to be electrically connected to an outside, wherein a wiring layer of the wiring portion is provided to be connected to the through wiring..
Nepes Co., Ltd.


04/07/16
20160099207 

Electronic module comprising a plurality of encapsulation layers and a producing it


An electronic module includes a first insulation layer, at least one carrier having a first main surface, a second main surface situated opposite the first main surface, and side surfaces connecting the first and second main surfaces to one another, at least one semiconductor chip arranged on the second main surface of the carrier, wherein the semiconductor chip has contact elements, and a second insulation layer, which is arranged on the carrier and the semiconductor chip.. .
Infineon Technologies Austria Ag


04/07/16
20160099206 

Wafer level packaging of electronic device


Wafer level packaged semiconductor device with enhanced heat dissipation properties. The semiconductor device includes a top and a bottom face and at least one metal pad is positioned on the top and the bottom faces.
Viagan Ltd.


04/07/16
20160099205 

Package on package and computing device including the same


A semiconductor package includes a printed circuit board (pcb), a chip bonded to the pcb, a mold protecting the chip and exposing a backside surface of the chip, via openings extending in the mold to expose first contacts bonded to the pcb, and at least one first marking inscribed in a marking region of the mold between the backside surface of the chip and the vias. The mold has an exposed molded underfill (emuf) structure covering the sides of the chip while exposing the backside surface of the chip.

04/07/16
20160099203 

Semiconductor stack packages


A semiconductor stack package includes a printed circuit board (pcb), a first semiconductor chip, and a second semiconductor chip. The first and second semiconductor chips are disposed side-by-side on a first surface of the pcb to be spaced apart from each other.
Sk Hynix Inc.


04/07/16
20160099202 

Semiconductor packaging structure


A semiconductor packaging structure including a circuit board, a chip, and a paste is provided. The circuit board includes a base layer, a first circuit layer, and a second circuit layer.
Powertech Technology Inc.


04/07/16
20160099201 

Integrated circuit devices having through-silicon vias and methods of manufacturing such devices


An integrated circuit device includes a semiconductor structure, a through-silicon-via (tsv) structure that penetrates through the semiconductor structure and a connection terminal connected to the tsv structure. A metal capping layer includes a flat capping portion that covers the bottom surface of the connection terminal and a wedge-shaped capping portion that is integrally connected to the flat capping portion and that partially covers a side wall of the connection terminal.

04/07/16
20160099200 

Aluminum alloy lead frame for a semiconductor device and corresponding manufacturing process


Described herein is a semiconductor device provided with: a die of semiconductor material; a lead frame, defining a support plate, which is designed to carry the die, and leads, which are designed to be electrically coupled to the die; and a package, of encapsulating material, which is designed to encapsulate the die and partially coming out of which are the leads. The lead frame has as constituent material an aluminum alloy comprising a percentage of silicon ranging between 1% and 1.5%..
Stmicroelectronics S.r.l.


04/07/16
20160099199 

Electronic devices with solderable die structures and methods of formation of such devices


An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.. .
Freescale Semiconductor, Inc.


04/07/16
20160099198 

Semiconductor package apparatus


A semiconductor package apparatus includes a lead frame, a first semiconductor chip, a second semiconductor chip, a first connecting element, and a second connecting element. The lead frame includes a power input plate, a ground plate, a phase plate, and a phase detection plate.
Ubiq Semiconductor Corp.


04/07/16
20160099197 

Semiconductor package and circuit substrate for the semiconductor package


Provided is a circuit substrate for a semiconductor package used for mounting a plurality of semiconductor devices. The circuit substrate including: a first circuit substrate unit; and a second circuit substrate unit that is formed on the first circuit substrate unit, wherein young's modulus of a first dielectric material composing the dielectric layer of the first circuit substrate unit is higher than young's modulus of a second dielectric material composing the dielectric layer of the second circuit substrate unit, and a coefficient of thermal expansion of the first dielectric material composing the dielectric layer of the first circuit substrate unit is smaller than a coefficient of thermal expansion of the second dielectric material composing the dielectric layer of the second circuit substrate unit..
Hitachi Metals, Ltd.


04/07/16
20160099194 

Semiconductor module and electrically-driven vehicle


A semiconductor module includes a first semiconductor element, a second semiconductor element, a first heat spreader electrically and thermally connected to the first semiconductor element, a second heat spreader electrically and thermally connected to the second semiconductor element, a dcb substrate including a first metal foil on a top surface of a ceramic insulating substrate and including a second metal foil on a bottom surface, the first metal foil being electrically and thermally joined to the first heat spreader and the second heat spreader, and a cooler thermally connected to the second metal foil of the dcb substrate. The first semiconductor element is disposed on an upstream side, and the second semiconductor element is disposed on a downstream side with respect to a flowing direction of a refrigerant of the cooler.
Fuji Electric Co., Ltd.


04/07/16
20160099193 

Semiconductor device


A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor substrate; an electrode pad provided on the main plane of the semiconductor substrate and connected to the semiconductor element; a guard ring surrounding the semiconductor element and the electrode pad, and provided on the main plane of the semiconductor substrate; and an insulating film covering all region of a semiconductor of the main plane of the semiconductor substrate exposed inside the guard ring, wherein the insulating film is made of a water impermeable material.. .
Mitsubishi Electric Corporation


04/07/16
20160099189 

Semiconductor packages and modules with integrated ferrite material


A semiconductor package includes a lead frame having a die paddle and a plurality of leads including a gate lead spaced apart from the die paddle. The semiconductor package further includes a semiconductor die attached to the die paddle and having a plurality of pads including a gate pad, a plurality of electrical conductors connecting the pads to the leads, an encapsulant encasing the semiconductor die and a portion of the leads such that part of the leads are not covered by the encapsulant, and a ferrite material embedded in the encapsulant and surrounding a portion of the electrical conductor that connects the gate pad to the gate lead.
Infineon Technologies Ag


04/07/16
20160099188 

Semiconductor device with sensor potential in the active region


A semiconductor device includes semiconductor body region and a surface region, the semiconductor body region including a first conductivity type first semiconductor region type and a second conductivity type second semiconductor region. The semiconductor device further includes: a first load contact structure included in the surface region and arranged for feeding a load current into the semiconductor body region; a first trench extending into the semiconductor body region and having a sensor electrode and a first dielectric, the first dielectric electrically insulating the sensor electrode from the second semiconductor region; an electrically conductive path electrically connecting the sensor electrode to the first semiconductor region; a first semiconductor path, wherein the first semiconductor region is electrically coupled to the first load contact structure by at least the first semiconductor path; a sensor contact structure included in the surface region and arranged for receiving an electrical potential of the sensor electrode..
Infineon Technologies Ag


04/07/16
20160099187 

3d nand staircase cd control by using interferometric endpoint detection


Embodiments of the present disclosure provide methods for forming stair-like structures in manufacturing three dimensional (3d) stacking of semiconductor chips. In one example, a method includes performing a trimming process on a substrate to trim a patterned photoresist layer disposed on a film stack from a first width to a second width in a processing chamber, performing an etching process to etch a portion of the film stack exposed by the trimmed patterned photoresist layer, directing an optical signal to a surface of the trimmed patterned photoresist layer continuously during the trimming and the etching process, collecting a return reflected optical signal reflected from the trimmed patterned photoresist layer, determining a change of reflected intensify of the return reflected optical signal as collected; and calculating a photoresist thickness loss based on the change of the reflected intensity..
Applied Materials, Inc.


04/07/16
20160099186 

Method for postdoping a semiconductor wafer


A method for treating a semiconductor wafer having a basic doping is disclosed. The method includes determining a doping concentration of the basic doping, and adapting the basic doping of the semiconductor wafer by postdoping.
Infineon Technologies Ag


04/07/16
20160099185 

Method of controlling an etching process for forming fine patterns of a semiconductor device


A method of controlling an etching process for forming fine patterns of a semiconductor device includes forming a lower pattern having a plurality of openings on a substrate, obtaining a width value of the lower pattern, and controlling a process recipe of an etching process for forming the lower pattern by using the width value.. .
Samsung Electronics Co., Ltd.


04/07/16
20160099184 

Semiconductor chip and estimating capability of semiconductor manufacturing system


A method of estimating the capability of a semiconductor manufacturing system is provided. Plural first transistors are formed and a first vtmm value and a first scale value are obtained.
United Microelectronics Corp.


04/07/16
20160099182 

Backside contacts for integrated circuit devices


A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor substrate. A source/drain region of the transistor is disposed in the well region.
Taiwan Semiconductor Manufacturing Co., Ltd.


04/07/16
20160099181 

Semiconductor device and fabricating the same


A semiconductor device comprises a substrate, a semiconductor fin, a first isolation structure and a first dummy structure. The semiconductor fin comprises a first sub-fin and a second sub-fin protruding from a surface of the substrate.
United Microelectronics Corp.


04/07/16
20160099180 

Method for manufacturing a semiconductor switching device with different local cell geometry


A method for manufacturing a semiconductor device includes providing a semiconductor substrate having an outer rim, an active area, and an edge termination region arranged between the active area and the outer rim, and forming a plurality of switchable cells in the active area. Each of the switchable cells includes a body region, a gate electrode structure, and a source region.
Infineon Technologies Austria Ag


04/07/16
20160099179 

Method of forming semiconductor device


A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided.
United Microelectronics Corp.


04/07/16
20160099177 

Methods of manufacturing a semiconductor device


In a method, an isolation layer pattern is formed on a substrate to define first and second active fins. An arc layer is formed on the isolation layer pattern to at least partially cover sidewalls of the first and second active fins.

04/07/16
20160099176 

Method for manufacturing semiconductor chip


A method for manufacturing a semiconductor chip includes forming a front-side groove in a front surface of a substrate; forming a back-side groove wider than the front-side groove by a rotating cutting member from the back surface of the substrate toward the front-side groove; attaching a holding member having an adhesive layer to the back surface of the substrate after forming the back-side groove; dry-washing the back surface before attaching the holding member to the back surface; extending the distance between adjacent semiconductor chips by expanding the holding member attached to the back surface; and separating the semiconductor chips at the extended distance therebetween from the holding member.. .
Fuji Xerox Co., Ltd.


04/07/16
20160099175 

Semiconductor structure including a through electrode, and forming the same


A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.. .
International Business Machines Corporation


04/07/16
20160099174 

Method of forming an interconnect structure for a semiconductor device


Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate. A via pattern including a plurality of openings may be defined above the substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


04/07/16
20160099173 

Methods for etching a barrier layer for an interconnection structure for semiconductor applications


Embodiments of the present disclosure provide methods for etching a barrier layer disposed under a metal layer, such as a copper layer, when the metal layer is etched open exposing the barrier layer, to form an interconnection structure in semiconductor devices. In one embodiment, a method of etching a barrier layer disposed under a metal layer formed on a substrate includes supplying a first etching gas mixture comprising a hydrogen containing gas and an inert gas into a processing chamber to clean a surface of a barrier layer disposed on a substrate for a first period of time, supplying a second etching gas mixture comprising fluorine containing gas into the processing chamber to etch the barrier layer, and switching to supply the first etching gas in the processing chamber to clean the etched barrier layer for a second period of time..
Applied Materials, Inc.


04/07/16
20160099170 

Methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby


Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure.

04/07/16
20160099168 

Method for defining an isolation region(s) of a semiconductor structure


Methods for defining an isolation region of a semiconductor structure are provided. The method includes, for instance: providing a semiconductor structure with a recess therein; disposing an insulator layer conformally within the recess in the semiconductor structure to partially fill the recess; modifying at least one material property of the insulator layer to obtain a densified insulator layer within the recess, where the modifying reduces a thickness of the densified insulator layer compared to that of the insulator layer; and depositing at least one additional insulator layer within the recess over the densified insulator layer, where the densified insulator layer within the recess defines, at least in part, an isolation region of the semiconductor structure..
Globalfoundries Inc.


04/07/16
20160099166 

Spring-loaded pins for susceptor assembly and processing methods using same


Apparatus and methods for processing a semiconductor wafer including a susceptor assembly with recesses comprising at least three lift pins. The lift pins include a sleeve with a spring and pin positioned therein.
Applied Materials, Inc.


04/07/16
20160099165 

Semiconductor wafer device and manufacturing method thereof


A method of manufacturing a semiconductor device comprises providing a carrier, disposing a plurality of dies over the carrier along a first direction and a second direction orthogonal to the first direction to arrange the plurality of dies in a plurality of rows, and shifting one of the plurality of rows along the first direction or the second direction in a predetermined distance.. .
Taiwan Semiconductor Manufacturing Company Ltd.


04/07/16
20160099164 

Structure for joining ceramic plate to metal cylindrical member


A member for semiconductor manufacturing device includes a susceptor 10 which is a ceramic plate formed of aln and a gas introduction pipe 20 which is joined to the susceptor 10. An annular pipe joining bank 14 is provided at a position of the susceptor 10 facing a flange 22 of the gas introduction pipe 20.
Ngk Insulators, Ltd.


04/07/16
20160099163 

Semiconductor manufacturing equipment component and making the same


A method of making a semiconductor manufacturing equipment component, such as an electrostatic chuck, includes an application step of applying a photosensitive metal paste onto a ceramic green sheet, which is to become the body substrate, the photosensitive metal paste being a heating element material; an exposure-and-development step of exposing the photosensitive metal paste, which has been applied onto the ceramic green sheet, to light and developing the photosensitive metal paste to form an intermediate heating element, which is to become the heating element, on the ceramic green sheet; and a firing step of co-firing the ceramic green sheet and the intermediate heating element to form the body substrate and the heating element.. .
Ngk Spark Plug Co., Ltd.


04/07/16
20160099158 

Method for removing metal oxide


The present invention relates to a method of selectively removing metal oxide, particularly tungsten oxide without etching the un-oxidized metal. The method removes metal oxide with little or no loss of the clean metal to improve the contact resistance for contact metal in semiconductor device fabrication.
International Business Machines Corporation


04/07/16
20160099157 

Barc-assisted process for planar recessing or removing of variable-height layers


The present disclosure provides a method of manufacturing an integrated circuit device in some embodiments. In the method, a semiconductor substrate is processed through a series of operations to form a topographically variable surface over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


04/07/16
20160099155 

Methods of forming a hard mask layer and of fabricating a semiconductor device using the same


A method of forming a hard mask layer on a substrate includes forming an amorphous carbon layer using nitrous oxide (n2o). A source of carbon and the nitrous oxide (n2o) are introduced to the substrate under a plasma ambient of an inert gas.
Samsung Electronics Co., Ltd.


04/07/16
20160099153 

Split-gate non-volatile memory (nvm) cell and method therefor


A split gate memory device includes a semiconductor substrate and a select gate over the substrate. The select gate has a bottom portion and a top portion over the bottom portion, wherein the top portion has a top sidewall and the bottom portion has a bottom sidewall, and wherein the bottom sidewall extends beyond the top sidewall.
Freescale Semiconductor, Inc.


04/07/16
20160099152 

Semiconductor device and fabricating the same


A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region.. .
Sk Hynix Inc.


04/07/16
20160099151 

Etching process


A method includes providing a semiconductor substrate; forming a doping oxide layer on the semiconductor substrate; forming a patterning layer on the doping oxide layer, the patterning layer leaving exposed regions of the doping oxide layer; performing a sputtering process to the substrate; and after the sputtering process, performing a wet etching process to the semiconductor substrate to remove the doping oxide layer from the exposed regions.. .
Taiwan Semiconductor Manufacturing Compnay, Ltd.


04/07/16
20160099149 

Method for manufacturing semiconductor substrate


A method for manufacturing a semiconductor substrate. An impurity diffusion ingredient can be diffused well and uniformly from a coating film into a semiconductor substrate by forming a coating film having a thickness of not more than 30 nm on a surface of a semiconductor substrate with a diffusion agent composition containing an impurity diffusion ingredient and a silicon compound that can be hydrolyzed to produce a silanol group..
Tokyo Ohka Kogyo Co., Ltd.


04/07/16
20160099079 

Repair circuit and semiconductor apparatus using the same


A repair circuit includes a fuse set latch array including a plurality of fuse set latches, and configured to store fuse informations in target fuse latches selected among the plurality of fuse set latches in response to fuse latch select signals; a fuse information control unit configured to generate the fuse latch select signals by using boot-up source signals generated by differently combining boot-up mode region select informations according to a region determination signal; and a repair processing unit configured to compare an address inputted from an exterior and the fuse informations, and access a normal memory cell corresponding to the external address or a redundant memory cell.. .
Sk Hynix Inc.


04/07/16
20160099077 

Test system simultaneously testing semiconductor devices


Individual memory chips are simultaneously tested by a tester using selectively enabled stress modules that apply a corresponding stress test to memory cells, wherein each stress test is associated with a corresponding failure attribute for the memory cells. Built-in self-test (bist)/built-in self-stress (biss) circuitry is provided in each stress module and may configured to selectively apply one or more stress test(s) during the simultaneous testing of a plurality of memory chips..

04/07/16
20160099076 

Semiconductor memory device


A semiconductor memory device includes a memory bank divided into a plurality of test areas which provide test data for a data compression test operation, a data compressing unit suitable for generating compressed data based on the test data, a data converting unit suitable for converting the compressed data into analog data to generate a final compressed data, and an output unit suitable for outputting the final compressed data during a read operation for the data compression test operation.. .
Sk Hynix Inc.


04/07/16
20160099075 

Fuse array circuit and semiconductor system including the same


A fuse array circuit includes a power generation block suitable for generating a driving power to be level-shifted at least once in a read operation period, a word line driving block suitable for driving a word line by using the driving power, and a fuse array suitable for outputting information programmed in a fuse that is activated by the driven word line through a bit line.. .
Sk Hynix Inc.


04/07/16
20160099074 

Fuse circuit and semiconductor apparatus including the same


A fuse circuit includes an e-fuse array including a plurality of e-fuse elements configured to store fuse data; a latch block including a plurality of latch groups configured to latch the fuse data read from the e-fuse array; and a control block configured to output latch reset signals corresponding to the plurality of latch groups in response to an apparatus reset signal and a clock signal, wherein the control block sequentially enables the latch reset signals.. .
Sk Hynix Inc.


04/07/16
20160099072 

Non-volatile semiconductor memory having multiple external power supplies


A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory.
Conversant Intellectual Property Management Inc.


04/07/16
20160099067 

Non-volatile split gate memory device and a operating same


A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns.
Silicon Storage Technology, Inc.


04/07/16
20160099064 

Non-volatile semiconductor memory with high reliability and data erasing method thereof


A non-volatile semiconductor memory apparatus and a data erasing method thereof are provided to suppress deterioration in reliability due to data rewriting. An erasing method of a flash memory is provided, which includes the following steps.
Winbond Electronics Corp.


04/07/16
20160099063 

Semiconductor device


A semiconductor device includes memory strings each including a drain select transistor, memory cells and a source select transistor, which are connected between a bit line and a common source line and suitable for operating based on voltages applied to a drain select line, word lines and a source select line, respectively, and an operation circuit suitable for performing a pre-program operation, an erase operation and a post-program operation on the memory strings. The operation circuit sequentially performs erase operations on the drain select transistors included in the memory strings..
Sk Hynix Inc.


04/07/16
20160099060 

Semiconductor memory device including a dummy memory cell and programming the same


A semiconductor memory and a method of programming the same are provided. A semiconductor memory device may include a memory cell array including a plurality of normal memory cells, a select transistor, and a dummy memory cell.
Sk Hynix Inc.


04/07/16
20160099057 

Block refresh to adapt to new die trim settings


Systems, apparatuses, and methods may be provided that adapt to trim set advancement. Trim set advancement may be a change in trim sets over time.
Sandisk Technologies Inc.


04/07/16
20160099041 

Semiconductor device


Disclosed herein is a device that includes a memory cell array including plurality of word lines, a plurality of bit lines each intersecting the word lines and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines, and the device further includes a driver configured to drive a selected one of the word lines from an inactive level to an active and to drive the selected one of the word lines from the active level to an intermediate level at a first rate and from the intermediated level to the inactive level at a second rate. The intermediate level is between the active and inactive levels, and the first rate is greater than the second rate..
Ps4 Luxco S.a.r.l.




Semiconductor topics: Semiconductor, Semiconductor Substrate, Semiconductor Device, Semiconductor Material, Electric Conversion, Conductive Layer, Molybdenum, Camera Module, Semiconductor Devices, Semiconductors, Integrated Circuit, Surfactant, Photoelectric Conversion, Electronic Device, Transparent Conductive Oxide

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