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Semiconductor patents



      
           
This page is updated frequently with new Semiconductor-related patents. Subscribe to the Semiconductor RSS feed to automatically get the update: related Semiconductor RSS feeds.

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Date/App# patent app List of recent Semiconductor-related patents
04/17/14
20140108808
 Host device, semiconductor memory device, and authentication method patent thumbnailHost device, semiconductor memory device, and authentication method
According to one embodiment, encrypted secret identification information (e-secretid) and the key management information (fkb) are read from a memory device. Encrypted management key (e-fkey) is obtained using the key management information (fkb) and index information (k).
04/17/14
20140108725
 Semiconductor memory device patent thumbnailSemiconductor memory device
A semiconductor memory device includes a memory cell array configured to include sub memory blocks and a redundancy memory block, data line groups configured to deliver data to be programmed into the sub memory blocks and data read from the sub memory blocks, a redundancy data line group configured to deliver data to be programmed into the redundancy memory block and data read from the redundancy memory block, and switching circuits configured to couple selectively the data line groups to the redundancy data line group.. .
04/17/14
20140108714
 Apparatus and method for generating descriptors to transfer data to and from non-volatile semiconductor memory of a storage drive patent thumbnailApparatus and method for generating descriptors to transfer data to and from non-volatile semiconductor memory of a storage drive
A storage drive including first, second, third, fourth and fifth modules. The first module is configured to control transfer of blocks of data between a host device and the storage drive.
04/17/14
20140108712
 Programming mode for multi-layer storage flash memory array and switching control method thereof patent thumbnailProgramming mode for multi-layer storage flash memory array and switching control method thereof
The present invention relates to a programming mode for improving the reliability of a multi-layer storage flash memory device in a semiconductor storage field. The present invention provides several programming modes for improving the reliability of a multi-layer storage flash memory device and switching control methods thereof, based on the technical conception of skipping some specific logic pages in the programming process to reduce the impact of the floating gate coupling effect on the operation of the flash memory.
04/17/14
20140108702
 Storage system which includes non-volatile semiconductor storage medium, and storage control method of storage system patent thumbnailStorage system which includes non-volatile semiconductor storage medium, and storage control method of storage system
Each block selected at (a 1) process is a block whose next write destination page is the first kind page. Each block consists of multiple pages.
04/17/14
20140107998
 System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking patent thumbnailSystem and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking
Systems and methods for prediction of in-plane distortions (ipd) due to wafer shape in semiconductor wafer chucking process is disclosed. A process to emulate the non-linear finite element (fe) contact mechanics model based ipd prediction is utilized in accordance with one embodiment of the present disclosure.
04/17/14
20140107961
 Testing method and testing system for semiconductor element patent thumbnailTesting method and testing system for semiconductor element
A testing method and testing system for a semiconductor element are provided. The method includes following steps.
04/17/14
20140107845
 Method of fabricating semiconductor cleaners patent thumbnailMethod of fabricating semiconductor cleaners
A method of manufacturing cleaning solvents is provided. The method includes selecting a small plurality of test solvents from a large plurality of perspective solvents.
04/17/14
20140107828
 Method and system for wafer quality predictive modeling based on multi-source information with heterogeneous relatedness patent thumbnailMethod and system for wafer quality predictive modeling based on multi-source information with heterogeneous relatedness
The present invention generally relates to the monitoring and controlling of a semiconductor manufacturing environment and, more particularly, to methods and systems for virtual meteorology (vm) applications based on data from multiple tools having heterogeneous relatedness. The methods and systems leverage the natural relationship of the multiple tools and take advantage of the relationship embedded in process variables to improve the prediction performance of the vm predictive wafer quality modeling.
04/17/14
20140107824
 Method and system for wafer quality predictive modeling based on multi-source information with heterogeneous relatedness patent thumbnailMethod and system for wafer quality predictive modeling based on multi-source information with heterogeneous relatedness
The present invention generally relates to the monitoring and controlling of a semiconductor manufacturing environment and, more particularly, to methods and systems for virtual meteorology (vm) applications based on data from multiple tools having heterogeneous relatedness. The methods and systems leverage the natural relationship of the multiple tools and take advantage of the relationship embedded in process variables to improve the prediction performance of the vm predictive wafer quality modeling.
04/17/14
20140107295
Epoxy resin composition, cured object and optical semiconductor sealing material
An epoxy resin composition, a cured object thereof, and an optical semiconductor sealing material using the cured object are described. The epoxy resin composition includes an alicyclic epoxy resin (a) and a vinyl polymer particle (b).
04/17/14
20140106652
Polishing pad and manufacturing method therefor
Provided are a polishing pad which remedies the problem of scratches occurring when a conventional hard (dry) polishing pad is used, which is excellent in polishing rate and polishing uniformity, and which can be used for not only primary polishing but also finish polishing, and a manufacturing method therefor. The polishing pad is a polishing pad for polishing a semiconductor device, comprising a polishing layer having a polyurethane-polyurea resin foam containing substantially spherical cells, wherein the polyurethane-polyurea resin foam has a young's modulus e in a range from 450 to 30000 kpa, and a density d in a range from 0.30 to 0.60 g/cm3..
04/17/14
20140106576
Inorganic polysilazane, silica film-forming coating liquid containing same, and method for forming silica film
Disclosed is an inorganic polysilazane that undergoes less shrinkage during a calcination step in an oxidizing agent such as water vapor and is less prone to allow a silica film to suffer from the formation of cracks or peel off from a semiconductor substrate, and a silica film-forming coating liquid containing the inorganic polysilazane, and also provides an inorganic polysilazane and a silica film-forming coating liquid containing the same. The value of a/(b+c) is 0.9-1.5 and the value of (a+b)/c is 4.2-50.
04/17/14
20140106574
Gapfill of variable aspect ratio features with a composite peald and pecvd method
Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features.
04/17/14
20140106573
Substrate processing apparatus and method of manufacturing semiconductor device
A substrate processing apparatus includes a substrate processing chamber including a plasma generation space where a plasma is generated and a substrate processing space where a substrate is placed during a substrate process; an inductive coupling structure outside the plasma generation space wherein a sum of electrical lengths of a coil of the inductive coupling structure and a waveform adjustment circuit connected to the coil is an integer multiple of a wavelength of an applied power; a substrate mounting table in the substrate processing space and supporting the substrate including grooves having high aspect ratios with a silicon-containing layer disposed thereon; a substrate transfer port at a wall of the substrate processing chamber; a substrate mounting table elevator moving the substrate mounting table upward/downward; an oxygen gas supply system to supply an oxygen-containing gas into the plasma generation space; and an exhaust unit exhausting gas from the substrate processing chamber.. .
04/17/14
20140106569
Method of fabricating three-dimensional semiconductor device and three-dimensional semiconductor device fabricated using the same
According to example embodiments of inventive concepts, a method of fabricating a 3d semiconductor device may include: forming a stack structure including a plurality of horizontal layers sequentially stacked on a substrate including a cell array region and a contact region; forming a first mask pattern covering the cell array region and defining openings extending in one direction over the contact region; performing a first etching process with a first etch-depth using the first mask pattern as an etch mask on the stack structure; forming a second mask pattern covering the cell array region and exposing a part of the contact region; and performing a second etching process with a second etch-depth using the second mask pattern as an etch mask structure on the stack structure. The second etch-depth may be greater than the first etch-depth..
04/17/14
20140106568
Method of forming opening on semiconductor substrate
The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided.
04/17/14
20140106567
Methods of forming fine patterns in semiconductor devices
Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer.
04/17/14
20140106559
System and method for forming an aluminum fuse for compatibility with copper beol interconnect scheme
A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.. .
04/17/14
20140106558
Semiconductor device having metal gate and manufacturing method thereof
A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (stis) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.. .
04/17/14
20140106557
Manufacturing method for semiconductor device having metal gate
A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.. .
04/17/14
20140106556
Method for manufacturing a dual work function semiconductor device
A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types.
04/17/14
20140106555
Method for forming a semiconductor device
A method for forming a semiconductor device. One embodiment provides a semiconductor substrate having a trench with a sidewall isolation.
04/17/14
20140106554
Methods of forming gated devices
Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction.
04/17/14
20140106553
Process for manufacturing a semiconductor device and an intermediate product for the manufacture of a semiconductor device
According to one aspect of the inventive concept there is provided a process for manufacturing a semiconductor device, comprising: providing a channel layer (104), providing a mask (106) on the channel layer, epitaxially growing a contact layer (108) in contact with the channel layer, epitaxially growing a support layer (110) on the contact layer, wherein the support layer is arranged to be etched at a higher rate than the contact layer, forming a trench extending through the support layer by removing the mask, and providing a conductor (118) in the trench. There is also provided an intermediate product for the manufacture of a semiconductor device..
04/17/14
20140106551
Back contact solar cells with effective and efficient designs and corresponding patterning processes
Laser based processes are used alone or in combination to effectively process doped domains for semiconductors and/or current harvesting structures. For example, dopants can be driven into a silicon/germanium semiconductor layer from a bare silicon/germanium surface using a laser beam.
04/17/14
20140106548
Fabrication of iii-nitride semiconductor device and related structures
A method of fabricating a iii-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.. .
04/17/14
20140106547
Epitaxy of high tensile silicon alloy for tensile strain applications
Embodiments of the present invention generally relate to methods for forming silicon epitaxial layers on semiconductor devices. The methods include forming a silicon epitaxial layer on a substrate at increased pressure and reduced temperature.
04/17/14
20140106546
Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.. .
04/17/14
20140106544
Semiconductor wafer with assisting dicing structure and dicing method thereof
A semiconductor wafer with an assisting dicing structure. The wafer comprises a substrate having a front surface and a rear surface.
04/17/14
20140106542
Laser and plasma etch wafer dicing with partial pre-curing of uv release dicing tape for film frame wafer application
Methods and systems of laser and plasma etch wafer dicing using uv-curable adhesive films. A method includes forming a mask covering ics formed on the wafer.
04/17/14
20140106539
Semiconductor isolation structure and method of manufacture
A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.. .
04/17/14
20140106538
Dummy pattern design for thermal annealing
The present disclosure provides a semiconductor structure including a semiconductor substrate having a device region and a dummy region adjacent the device region; a plurality of active regions in the device region; and a plurality of dummy active regions in the dummy region, where each of the active regions has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, and the first dimension is substantially greater than the second dimension; and each of the dummy active regions has a third dimension in the first direction and a fourth dimension in the second direction, and the third dimension is substantially greater than the fourth dimension. The plurality of dummy active regions are configured such that thermal annealing effect in the dummy region is substantially equal to that of the device region..
04/17/14
20140106537
Methods of manufacturing a semiconductor device
Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively..
04/17/14
20140106535
Methods of manufacturing semiconductor devices
A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.. .
04/17/14
20140106532
Semiconductor structure and manufacturing method for the same and esd circuit
A semiconductor structure and manufacturing method for the same, and an esd circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor.
04/17/14
20140106531
Field effect transistor device having a hybrid metal gate stack
A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer.
04/17/14
20140106530
Semiconductor device and method of manufacturing the same
In a power feeding region of a memory cell (mc) in which a sidewall-shaped memory gate electrode (mg) of a memory nmis (qnm) is provided by self alignment on a side surface of a selection gate electrode (cg) of a selection nmis (qnc) via an insulating film, a plug (pm) which supplies a voltage to the memory gate electrode (mg) is embedded in a contact hole (cm) formed in an interlayer insulating film (9) formed on the memory gate electrode (mg) and is electrically connected to the memory gate electrode (mg). Since a cap insulating film (cap) is formed on an upper surface of the selection gate electrode (cg), the electrical conduction between the plug (pm) and the selection gate electrode (cg) can be prevented..
04/17/14
20140106529
Finfet device with silicided source-drain regions and method of making same using a two step anneal
A thermal annealing flow process includes the steps of: depositing a metal or metal alloy on a silicon semiconductor structure, performing a first annealing of a rapid thermal anneal (rta) type to produce a metal rich phase in a portion of the silicon semiconductor structure, removing unreacted metal or metal alloy and performing a second annealing as a millisecond annealing at a temperature that is below a melt temperature of the silicon material present in the silicon semiconductor structure.. .
04/17/14
20140106527
Method of producing semiconductor device
A method of producing a semiconductor device, includes: forming a semiconductor layer on a substrate; forming an a recess in the semiconductor layer by dry etching with a gas containing fluorine components, the recess having an opening portion on the surface of the semiconductor layer; forming a fluorine-containing region by heating the semiconductor layer and thus diffusing, into the semiconductor layer, the fluorine components attached to side surfaces and a bottom surface of the recess; forming an insulating film on an inner surface of the recess and on the semiconductor layer; and forming an electrode on the insulating film in a region in which the recess is formed.. .
04/17/14
20140106525
Method of forming pn floating gate non-volatile storage elements and transistor having n+ gate
Non-volatile storage elements having a pn floating gate are disclosed herein. The floating gate may have a p− region near the tunnel oxide, and may have an n+ region near the control gate.
04/17/14
20140106523
Vertical super-thin body semiconductor on dielectric wall devices and methods of their fabrication
The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (vstb) formed on dielectric body wall (such as sti-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to sti side surface. The body is made self-aligned to sti hard mask edge allowing tight control of body thickness.
04/17/14
20140106521
Method for manufacturing semiconductor device
Provided is a method for manufacturing a semiconductor device which includes, on a wafer which has a notch, a plurality of transistors parallel with and perpendicular to a notch direction extending between the center of the wafer and the notch, the method including: preparing the wafer having the front surface which has off angle of at least 2 degrees and at most 2.8 degrees from plane in a direction in which twist angle relative to the notch direction is at least 12.5 degrees and at most 32.5 degrees; and doping impurities into the front surface of the wafer in a direction perpendicular to the front surface.. .
04/17/14
20140106520
Semiconductor device manufacturing method
A semiconductor device manufacturing method with high productivity is disclosed with improved trade-off relationship between auto-doping and breakdown in alignment mark form. First to sixth epitaxial layers are grown sequentially on si {100} main surface of an arsenic doped substrate using multilayer epitaxial technology.
04/17/14
20140106519
Semiconductor structure and manufacturing process thereof
A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region.
04/17/14
20140106517
Semiconductor devices with minimized current flow differences and methods of same
A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device..
04/17/14
20140106516
Self-doped ohmic contacts for compound semiconductor devices
A compound semiconductor device is manufactured by forming an iii-nitride compound semiconductor device structure on a silicon-containing semiconductor substrate, the iii-nitride compound semiconductor device structure including a gan alloy on gan and a channel region arising near an interface between the gan alloy and the gan. One or more silicon-containing insulating layers are formed on a surface of the iii-nitride compound semiconductor device structure adjacent the gan alloy, and a contact opening is formed which extends through the one or more silicon-containing insulating layers to at least the gan alloy.
04/17/14
20140106514
Method for manufacturing semiconductor device and method for growing graphene
A catalyst film (2) is formed over a substrate (1). A graphene (3) is grown on the catalyst film (2).
04/17/14
20140106509
Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion..
04/17/14
20140106507
System and process for fabricating semiconductor packages
A method of processing semiconductor chips includes measuring locations of semiconductor dies placed on a carrier with a scanner to generate die location information. The method includes applying a dielectric layer over the semiconductor dies and communicating the die location information to a laser assembly.
04/17/14
20140106506
Semiconductor device and manufacturing method thereof
A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer..
04/17/14
20140106505
Method for manufacturing semiconductor device
Disclosed is a method to manufacture a thin film transistor having an oxide semiconductor as a channel formation region. The method includes; forming an oxide semiconductor layer over a gate insulating layer; forming a source and drain electrode layers over and in contact with the oxide semiconductor layer so that at least portion of the oxide semiconductor layer is exposed; and forming an oxide insulating film over and in contact with the oxide semiconductor layer.
04/17/14
20140106504
Method for manufacturing semiconductor device
To provide a semiconductor device in which an increase in oxygen vacancies is suppressed. To provide a semiconductor device with favorable electrical characteristics.
04/17/14
20140106503
Method for manufacturing semiconductor device and manufacturing apparatus of semiconductor device
A semiconductor device including an oxide semiconductor and an organic resin film is manufactured in the following manner. Heat treatment is performed on a first substrate provided with an organic resin film over a transistor including an oxide semiconductor in a reduced pressure atmosphere; handling of the first substrate is performed in an atmosphere containing moisture as little as possible in an inert gas (e.g., nitrogen) atmosphere with a dew point of lower than or equal to −60° c., preferably with a dew point of lower than or equal to −75° c.
04/17/14
20140106502
Semiconductor device and method for manufacturing the same
Stable electrical characteristics and high reliability are provided for a miniaturized semiconductor device including an oxide semiconductor, and the semiconductor device is manufactured. The semiconductor device includes a base insulating layer; an oxide stack which is over the base insulating layer and includes an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide stack; a gate insulating layer over the oxide stack, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer; and an interlayer insulating layer over the gate electrode layer.
04/17/14
20140106496
Solid state image pickup device and manufacturing method therefor
A method of manufacturing an active pixel sensor having a plurality of pixels, each of the pixels having a photodiode formed by a part of a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type, and a transfer transistor for transferring a charge carrier from the photodiode, includes the steps of preparing a substrate on which the first semiconductor region of the first conductive type is formed, forming a mask to form the second semiconductor region on the substrate, forming the second semiconductor region using the mask, and forming a gate of the transferring transistor after forming the second semiconductor region. The gate of the transferring transistor overlaps the second semiconductor region in a planar view..
04/17/14
20140106494
Dual-gate bio/chem sensor
A dual gate extremely thin semiconductor-on-insulator transistor with asymmetric gate dielectrics is provided. This structure can improve the sensor detection limit and also relieve the drift effects.
04/17/14
20140106493
P-type doping layers for use with light emitting devices
A light emitting diode (led) comprises an n-type group iii-v semiconductor layer, an active layer adjacent to the n-type group iii-v semiconductor layer, and a p-type group iii-v semiconductor layer adjacent to the active layer. The active layer includes one or more v-pits.
04/17/14
20140106487
Optical-semiconductor encapsulating material
The present invention relates to a sheet-shaped, optical-semiconductor encapsulating material including: a first resin layer containing inorganic particles; and a second resin layer containing a phosphor and being superposed directly or indirectly on the first resin layer, and relates to a kit for optical-semiconductor encapsulation including: a sheet-shaped molded body including a first resin layer containing inorganic particles; and a sheet-shaped molded body including a second resin layer containing a phosphor.. .
04/17/14
20140106483

Provided is a vertical nitride-based led including a first electrode; a first nitride semiconductor layer that is disposed on the first electrode; an active layer that is disposed on the first nitride semiconductor layer; a second nitride semiconductor layer that is disposed on the active layer; an ohmic contact pattern that is disposed on the second nitride semiconductor layer; a second electrode that is disposed on the ohmic contact pattern; and a bonding pad that is electrically connected to the second electrode and disposed on the second nitride semiconductor layer.. .
04/17/14
20140106481
Method for wafer level reliability
A method for ensuring wafer level reliability is provided. The method involves: forming a gate oxide layer having a thickness of less than 50 Å on a semiconductor substrate; forming a pmos element having a channel length of less than 0.13 μm on the semiconductor substrate; and assessing hot carrier injection (hci) for the pmos element..
04/17/14
20140106480
Method and apparatus for depositing phosphor on semiconductor-light emitting device
A method and apparatus for depositing a phosphor using transfer molding. The method includes: forming a plurality of light-emitting devices on a wafer and rearranging the light-emitting devices on a carrier substrate according to luminance characteristics of the plurality of light-emitting devices by examining the luminance characteristics of the plurality of light-emitting devices; depositing the phosphor on the rearranged light-emitting devices using transfer molding; and separating the light-emitting devices on the carrier substrate..
04/17/14
20140106479
End-cut first approach for critical dimension control
A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer..
04/17/14
20140106474
Systems and methods of automatically detecting failure patterns for semiconductor wafer fabrication processes
A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process..
04/17/14
20140106473
Advanced handler wafer bonding and debonding
A method for processing a semiconductor wafer includes applying a release layer to a transparent handler. An adhesive layer, that is distinct from the release layer, is applied between a semiconductor wafer and the transparent handler having the release layer applied thereon.
04/17/14
20140106106
Dicing film with protecting film
The present invention provides a dicing film with a protecting film that enables to paste a dicing film to a semiconductor wafer without a shift in position while reducing a downtime. There is provided a dicing film with a protecting film in which a dicing film and a protecting film are laminated, wherein the difference between the transmittance of the protecting film and the transmittance of the dicing film with a protecting film at a portion of the dicing film where light for detecting a film transmits first is 20% or more in a wavelength of 600 to 700 nm..
04/17/14
20140106064
Method for fabricating a planar micro-tube discharger structure
A method for fabricating a semiconductor-based planar micro-tube discharger structure is provided, including the steps of forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap, forming an insulating layer over the patterned electrodes and the separating block., and filling the insulating layer into the gap. At least two discharge paths are formed.


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Semiconductor topics: Semiconductor, Semiconductor Substrate, Semiconductor Device, Semiconductor Material, Electric Conversion, Conductive Layer, Molybdenum, Camera Module, Semiconductor Devices, Semiconductors, Integrated Circuit, Surfactant, Photoelectric Conversion, Electronic Device, Transparent Conductive Oxide

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