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Semiconductor patents

      

This page is updated frequently with new Semiconductor-related patent applications.




 Electronics assembly with interference-suppression capacitors patent thumbnailElectronics assembly with interference-suppression capacitors
An electronics assembly includes a plurality of first semiconductor chips each having a first load terminal and a second load terminal, a conductor structure having a first conductor strip, a second conductor strip and a third conductor strip, a plurality of first interference-suppression capacitors arranged on the conductor structure and each having a first capacitor terminal and a second capacitor terminal, and a heat sink. The first load terminal of each first semiconductor chip is electrically connected to the first conductor strip, the second load terminal of each first semiconductor chip is electrically connected to the third conductor strip, the first capacitor terminal of each first interference-suppression capacitor is electrically connected to the first conductor strip, the second capacitor terminal of each first interference-suppression capacitor is electrically connected to the second conductor strip, and the heat sink is electrically connected to the second conductor strip..
Infineon Technologies Ag


 Projection system, semiconductor integrated circuit, and image correction method patent thumbnailProjection system, semiconductor integrated circuit, and image correction method
A projection apparatus projects pattern light onto an object, the pattern light including pattern images corresponding to information that indicates coded projection coordinates in a projection coordinate system. Each of the pattern images includes two or more continuous areas.
Panasonic Intellectual Property Corporation Of America


 High efficiency image sensor pixels with deep trench isolation structures and embedded reflectors patent thumbnailHigh efficiency image sensor pixels with deep trench isolation structures and embedded reflectors
An image sensor with an array of pixels is provided. To minimize optical and electrical and crosstalk, the array of pixels may include deep trench isolation structures interposed between adjacent pairs of photodiodes.
Semiconductor Components Industries, Llc


 Social network service for semiconductor manufacturing equipment and users patent thumbnailSocial network service for semiconductor manufacturing equipment and users
Methods and systems for sharing information related to operational metrics of a plurality of equipment used in manufacturing of semiconductor wafer includes interfacing a server with the equipment to allow the server to receive a plurality of parameters including operational metrics associated with operation of each of the plurality of equipment. The plurality of parameters are processed to identify event-related data, message-related data and to generate human-readable interpretation for the identified event-related data and the message related data.
Lam Research Corporation


 Semiconductor device patent thumbnailSemiconductor device
According to embodiments, a semiconductor device includes a field-effect transistor; a switch; and a controller. The field-effect transistor includes a substrate; a nitride semiconductor layer on the substrate; a drain electrode and a source electrode on the nitride semiconductor layer; and a gate electrode between the drain electrode and the source electrode.
Kabushiki Kaisha Toshiba


 Semiconductor device and driving  the same patent thumbnailSemiconductor device and driving the same
The semiconductor device includes a switching arm unit in which first and second wide bandgap semiconductor elements, each having a body diode, are connected in series between a positive line and a negative line; a current detecting unit that detects a current in at least a wide bandgap semiconductor element in which a flyback current flows; and a semiconductor element driving unit that drives the first and second wide bandgap semiconductor elements. When driving one of the wide bandgap semiconductor elements, the semiconductor element driving unit determines, by referring to a fault inhibiting characteristic curve, whether a flyback current detection value of the other wide bandgap semiconductor elements falls within a fault growth region or a fault inhibiting region, and when a result of the determination indicates that the flyback current detection value is within the fault growth region, inhibits a current flowing in the one wide bandgap semiconductor element..
Fuji Electric Co., Ltd.


 Device patent thumbnailDevice
As one example, the voltage boosting circuit boosts a voltage of the first control signal which turns the first semiconductor switch on to a higher voltage than a high voltage.. .

 Semiconductor device and  outputting temperature alarm patent thumbnailSemiconductor device and outputting temperature alarm
A semiconductor device including a semiconductor switch circuit and a drive circuit. The semiconductor switch circuit includes a semiconductor switch and a temperature sensor for detecting a temperature in a periphery of the semiconductor switch.
Fuji Electric Co., Ltd.


 Semiconductor device patent thumbnailSemiconductor device
According to one embodiment, there is provided a semiconductor device including an input terminal, an output terminal, an oscillation circuit, an adjuster circuit, a driver circuit, and a detector circuit. The input terminal receives a first clock.
Kabushiki Kaisha Toshiba


 Semiconductor integrated circuits patent thumbnailSemiconductor integrated circuits
A semiconductor integrated circuit includes a scan enable (se) inverter and a clock (ck) inverter on a substrate, a first multiplex part, and a second multiplex part. The se inverter and the ck inverter are aligned in a first direction.

Semiconductor integrated circuit

According to one embodiment, a semiconductor integrated circuit comprises: a first flip-flop including a first input circuit, a first latch, a second latch, and a first output circuit; a second flip-flop including a second input circuit, a third latch, a fourth latch, and a second output circuit; and a clock buffer configured to output a common clock signal to the first flip-flop and the second flip-flop. A first output terminal of the second latch is coupled to an input terminal of the first output circuit, and a second output terminal of the second latch is directly coupled to an input terminal of the second input circuit..
Kabushiki Kaisha Toshiba

Power tool and motor drive circuit thereof

A power tool and a motor drive circuit thereof are provided. The motor drive circuit includes an inverter, a controller and a current sensor.
Johnson Electric S.a.

Three-phase inverter system

A three-phase inverter system, in one configuration, includes an inverter main circuit and a control circuit. The inverter system includes current sensors which detect output currents in, for example, u- and w-phases, respectively, the inverter main circuit includes a semiconductor switching device with a current sense which is provided in, for example, the v-phase.
Fuji Electric Co., Ltd

Semiconductor device, manufacturing the same and power converter

There is provided a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device comprises a process of forming a semiconductor layer that is mainly made of a group iii nitride and has n-type characteristics, by crystal growth; a film formation process of forming a through film that is mainly made of an element different from an element serving as an n-type impurity relative to the group iii nitride, by growth on the semiconductor layer continuous with crystal growth of the semiconductor layer; an ion implantation process of implanting a p-type impurity into the semiconductor layer across the through film by ion implantation; a heating process of heating the semiconductor layer and the through film after completion of the ion implantation process, so as to activate a region of the semiconductor layer in which the p-type impurity is ion-implanted, to a p-type semiconductor region; and a removal process of removing the through film from the semiconductor layer, after completion of the heating process.
Toyoda Gosei Co., Ltd.

Power supply system having two dc power supplies

A power supply system includes first and second dc power supplies and a power converter having first to fifth semiconductor elements and first and second reactors. The first and fourth semiconductor elements are electrically connected between a first node and a second node, and a first power line, respectively.
Toyota Jidosha Kabushiki Kaisha

Startup circuit for reference circuits

A start-up circuit for a reference circuit such as a bandgap reference circuit. The start-up circuit includes a diode-connected metal-oxide-semiconductor (mos) transistor connected between a power supply node and a start-up node that is connected in turn to the gate of a current control mos transistor in the reference circuit.
Texas Instruments Deutschland Gmbh

Semiconductor device and power receiving device

An object is to provide a semiconductor device that is capable of wireless communication, such as an rfid tag, which can transmit and receive individual information without checking remaining capacity of a battery or changing batteries due to deterioration with time in the battery for a drive power supply voltage, and maintain a favorable a transmission/reception state even when electric power of an electromagnetic wave from a reader/writer is not sufficient. The semiconductor device includes a signal processing circuit, a first antenna circuit connected to the signal processing circuit, an antenna circuit group, a rectifier circuit-group and a battery connected to the signal processing circuit.
Semiconductor Energy Laboratory Co., Ltd.

Discharge of back-up capacitor by constant current

An electrical arrangement includes a high-voltage battery and a number of electrical utility arrangements connected to the battery via a main switch and a downstream back-up capacitor. A discharge circuit is connected to the capacitor and has a discharge path with an ohmic discharge resistor.
Siemens Aktiengesellschaft

External resonator type laser device

An external resonator type laser device has an optical element that forms an external resonator with a semiconductor device by selecting and reflecting light of a specific wavelength range from light outputted from the semiconductor device; a supporting member formed of a material having a larger coefficient of linear expansion than the optical element; and a first mount interposed between the optical element and the supporting member, formed of a material having a coefficient of linear expansion closer to that of the optical element compared with that of the supporting member. The optical element is adhered to the first mount.
Ushio Denki Kabushiki Kaisha

Thermal emission source and two-dimensional photonic crystal for use in the same emission source

A thermal emission source capable of switching the intensity of light at a high response speed similarly to a photoelectric conversion element. A thermal emission source includes: a two-dimensional photonic crystal including a slab in which an n-layer made of an n-type semiconductor, a quantum well structure layer having a quantum well structure, and a p-layer made of a p-type semiconductor are stacked in the mentioned order in the thickness direction, wherein modified refractive index areas (air holes) whose refractive index differs from the refractive indices of the n-layer, the p-layer and the quantum well structure layer are cyclically arranged in the slab so as to resonate with a specific wavelength of light corresponding to a transition energy between the subbands in a quantum well in the quantum well structure layer; and a p-type electrode and an n-type electrode for applying, to the slab, a voltage which is negative on the side of the p-layer and positive on the side of the n-layer..
Japan Science And Technology Agency

Semiconductor laser element and making semiconductor laser device

A semiconductor laser element includes an inclined substrate, a semiconductor layer formed on one surface of the substrate, a first electrode (n-type electrode) formed on an opposite surface of the substrate, a second electrode (p-type electrode) formed on the semiconductor layer, and a current constriction part formed in the semiconductor layer. The semiconductor layer has a multi-layer structure including at least an active layer.
Ushio Denki Kabushiki Kaisha

Method for producing semiconductor laser element

A method for producing a semiconductor laser element includes providing a semiconductor wafer comprising: a nitride semiconductor substrate, and a semiconductor stack located on the substrate, the semiconductor stack including a plurality of nitride semiconductor layers; forming in the substrate a fissure starting point and a fissure extending from the fissure starting point; forming a cleavage reference portion extending parallel to a cleavage plane of the semiconductor wafer as estimated from a plan view shape of the fissure; and cleaving the semiconductor wafer parallel to the cleavage reference portion to thereby obtain resonator end faces.. .
Nichia Corporation

Flip-chip employing integrated cavity filter, and related components, systems, and methods

A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (ic) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip.
Qualcomm Incorporated

Hybrid system for storing solar energy as heat and electricity

A photoelectrochemical system and method utilizing the photons having energies above the bandgaps of a p-type semiconductor photocathode and an n-type semiconductor photoanode with redox couples having fast electron transfer kinetics to keep overpotentials under 0.15 volts, and redox potentials energetically located within the band gaps, for storing energy in photodriven oxidation and reduction reactions separated by less than 1.6 volts using a redox flow battery configuration, are described. The photoelectrochemical system can also store heat in the flow battery generated from the inefficiencies of the photoredox reactions and from impinging photons having energies below the band gaps.
University Of Wyoming

Method and manufacturing semiconductor elements

The embodiment provides a method and an apparatus for manufacturing a semiconductor element showing high conversion efficiency and having a perovskite structure. The embodiment is a method for manufacturing a semiconductor element comprising an active layer having a perovskite structure.
Kabushiki Kaisha Toshiba

Light emitting diode

A light emitting diode includes an insulating substrate, a first mgo layer, a semiconductor carbon nanotube layer, a second mgo layer, a functional dielectric layer, a first electrode, and a second electrode. The semiconductor carbon nanotube layer has a first surface and a second surface.
Hon Hai Precision Industry Co., Ltd.

Semiconductor memory device and manufacturing the same

According to one embodiment, a semiconductor memory device includes first and second interconnect parts, and a second interconnect connection part. The first interconnect part includes a first core part, and a first interconnect layer.
Kabushiki Kaisha Toshiba

Semiconductor device, related manufacturing method, and related electronic device

A method for manufacturing a semiconductor device may include the following steps: preparing a substrate; preparing a first insulating layer on the substrate; preparing an electrode in the first insulating layer; preparing a second insulating layer on the first insulating layer; removing (e.g., using a dry etching process or a wet etching process) a portion of the second insulating layer to form a hole that at least partially exposes the electrode; providing a phase change material layer that may cover the electrode; and removing (e.g., using a sputtering process such as an argon sputtering process), a portion of the phase change material layer positioned inside the hole to form a phase change member that may expose a first portion of (a top side of) the electrode and may directly contact a second portion of (the top side of) the electrode.. .
Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor device manufacturing method

There is provided a semiconductor device manufacturing method which includes: loading a substrate with a magnetic substance film formed thereon into a process container; regulating an internal pressure of the process container to a first pressure lower than an atmospheric pressure; regulating the internal pressure of the process container from the first pressure to a second pressure higher than the first pressure; and magnetizing the magnetic substance film by applying a magnetic field to the magnetic substance film under the second pressure.. .
Tokyo Electron Limited

Semiconductor devices and methods of manufacturing the same

A semiconductor device includes a magnetic tunnel junction structure including a first magnetic pattern, a tunnel barrier pattern, and a second magnetic pattern that are disposed on a substrate. A material layer including oxidation-facilitation dopants is formed on a surface of the magnetic tunnel junction structure.

Semiconductor device with a magnetic shield

A semiconductor device includes a substrate, a magnetoresistive memory chip disposed on the substrate, and a sealing resin layer that seals the magnetoresistive memory chip. The magnetoresistive memory chip includes a magnetoresistive memory element layer and an organic resin layer that covers at least a portion of the magnetoresistive memory element layer and contains magnetic particles..
Kabushiki Kaisha Toshiba

Thermoelectric module

A thermoelectric module mounted on a non-flat surface of a heating source component to reduce thermal resistance to enhance thermoelectric generation efficiency is provided. The thermoelectric module includes at least one electrode component having a first electrode plate and a second electrode plate connected to be pivoted with respect to each other.
Hyundai Motor Company

Method for manufacturing light emitting device

A method for manufacturing a light emitting device includes preparing a light emitting element that includes a light transmissive substrate comprising a first main surface, a second main surface, and a side surface having a light transmitting part and a light absorbing part whose optical transmissivity is lower than that of the light transmitting part, and a semiconductor laminate that is provided to the first main surface of the light transmissive substrate, joining the light emitting element to an upper surface of a base body such that the base body is opposite to the side where the semiconductor laminate is provided, providing a support member that covers the side surface of the light emitting element and part of the base body, and removing the light absorbing part by thinning the light transmissive substrate from the second main surface side.. .
Nichia Corporation

Optoelectronic semiconductor device

An optoelectronic semiconductor device comprising: a semiconductor system comprises an upper surface, an interfacial layer comprises a upper interfacial layer on the upper surface of the semiconductor system, and the upper interfacial layer comprises a first wavelength converting material; and a void region in the upper interfacial layer, and a material different from that of the upper interfacial layer fills in the void region.. .
Epistar Corporation

Semiconductor light emitting device and manufacturing same

According to one embodiment, a semiconductor light-emitting device includes a semiconductor layer including a first semiconductor layer, a second semiconductor layer, a light emitting layer, a first surface, and a second surface; a p-side electrode; an n-side electrode; a first p-side pillar; a first n-side pillar; a first insulating layer; a fluorescer layer; a second insulating layer; a p-side interconnect; and an n-side interconnect. The second insulating layer is provided as one body in at least a portion of an outer side of a side surface of the first insulating layer and at least a portion of an outer side of a side surface of the fluorescer layer..
Kabushiki Kaisha Toshiba

Semiconductor light emitting device

A semiconductor light emitting device includes first and second light emitting bodies, a first electrode, a second electrode and a first interconnection. The first and second light emitting bodies are disposed on a conductive substrate, and each includes first and second semiconductor layers and a light emitting layer therebetween.
Kabushiki Kaisha Toshiba

Production of optoelectronic components

A method of producing optoelectronic components includes providing a carrier; arranging optoelectronic semiconductor chips on the carrier; forming a conversion layer for radiation conversion on the carrier, wherein the optoelectronic semiconductor chips are surrounded by the conversion layer; and carrying out a singulation process to form separate optoelectronic components, wherein at least the conversion layer is severed.. .
Osram Opto Semiconductors Gmbh

Multistep deposition of zinc oxide on gallium nitride

A method for fabricating a zinc oxide (zno) conductive film on a semiconductor material, including depositing a doped zno seed layer on a diode, wherein the zno seed layer forms an electrical contact to the diode; and depositing a zno layer on the zno seed layer, wherein the zno seed layer and the zno layer each have a thickness, a crystal quality, and a doping level such that (1) the diode comprising iii-nitride material is turned on with a turn on voltage of 2.75 volts or less applied across the zno layers and the diode, and (2) a contact resistance, of a structure comprising the zno layers and the diode, is lower as compared to a contact resistance of a structure comprising the zno layer directly on the diode without the zno seed layer.. .
The Regents Of The University Of California

Light-emitting diode with improved light extraction efficiency

According to the present invention, a light-emitting diode with improved light extraction efficiency comprises: a semiconductor laminated structure including an n-layer, a light-emitting layer, and a p-layer formed on a substrate; an n-type electrode formed on the n-layer; and a p-type electrode formed on the p-layer, wherein the n-type electrode and the p-type electrode include a pad electrode and a dispersion electrode, and the n-type electrode and/or the p-type electrode includes a reflective electrode layer for reflecting light onto the dispersion electrode. Thus, the light-emitting diode has a reflective electrode layer on the electrode so as to improve light extraction efficiency.
Seoul Viosys Co., Ltd.

Light emitting device

One embodiment provides a light emitting device comprising: a substrate; a first electrode arranged on the substrate; a light emitting structure arranged on the first electrode and including a first semiconductor layer, a second semiconductor layer, and an active layer between the first and second semiconductor layers; and a second electrode arranged on the second semiconductor layer, wherein the second electrode includes: a pad electrode; and a branch electrode extending from the pad electrode and having a hexagonal structure for enabling an upper surface of the second semiconductor layer to be exposed in a hexagonal shape.. .
Lg Innotek Co., Ltd.

Semiconductor light emitting device

A semiconductor light emitting device includes a semiconductor stack including a first conductive semiconductor layer including a first surface, a second conductive semiconductor layer including a second surface opposite to the first surface, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and a through hole disposed through the semiconductor stack. The semiconductor light emitting device further includes a contact layer connected to the first conductive semiconductor layer, disposed in the through hole, and disposed through the semiconductor stack, a first electrode layer connected to the contact layer, and a second electrode layer disposed on the second surface, and including a pad forming portion on which the semiconductor stack is not disposed.
Samsung Electronics Co., Ltd.

Nitride semiconductor light emitting element

A nitride semiconductor light emitting element comprises a sapphire substrate, and a light emitting element structure portion that has a plurality of nitride semiconductor layers formed on the sapphire substrate. The nitride semiconductor light emitting element is a back-surface-emitting type nitride semiconductor light emitting element that outputs light from the light emitting element structure portion to an outside of the element through the sapphire substrate.
Soko Kagaku Co., Ltd.

Polycrystalline gallium-nitride self-supporting substrate and light-emitting element using same

Provided is a self-supporting polycrystalline gan substrate composed of gan-based single crystal grains having a specific crystal orientation in a direction approximately normal to the substrate. The crystal orientations of individual gan-based single crystal grains as determined from inverse pole figure mapping by ebsd analysis on the substrate surface are distributed with tilt angles from the specific crystal orientation, the average tilt angle being 1 to 10°.
Ngk Insulators, Ltd.

Semiconductor light-emitting device

A semiconductor light-emitting device includes a light-emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, and a magnetic layer on the light-emitting structure. The magnetic layer may have at least one magnetization direction that is parallel to an upper surface of the active layer.
Samsung Electronics Co., Ltd.

Method of fabricating semiconductor light emitting device

A method of fabricating a semiconductor light emitting device includes forming a first conductivity type semiconductor layer, forming an active layer by alternately forming a plurality of quantum well layers and a plurality of quantum barrier layers on the first conductivity type semiconductor layer, and forming a second conductivity type semiconductor layer on the active layer. The plurality of quantum barrier layers include at least one first quantum barrier layer adjacent to the first conductivity type semiconductor layer and at least one second quantum barrier layer adjacent to the second conductivity type semiconductor layer.
Samsung Electronics Co., Ltd.

Photovoltaic devices including controlled copper uptake

A photovoltaic cell can include a substrate having a copper-doped semiconductor layer. The doping can be mediated with a salt..
First Solar, Inc.

Compound-semiconductor photovoltaic cell and manufacturing compound-semiconductor photovoltaic cell

A compound-semiconductor photovoltaic cell includes a first photoelectric conversion cell made of a first compound-semiconductor material which lattice matches with gaas or ge; a first tunnel junction layer arranged on a deep side farther than the first photoelectric conversion cell in a light incident direction, and including a first p-type (alx1ga1-x1)y1in1-y1as (0≦x1<1, 0<y1≦1) layer and a first n-type (alx2ga1-x2)y2in1-y2p (0≦x2<1, 0<y2<1) layer; and a second photoelectric conversion cell arranged on a deep side farther than the first tunnel junction layer in the light incident direction, and made of a second compound-semiconductor material which is a gaas-based semiconductor material. The first photoelectric conversion cell and the second photoelectric conversion cell are joined via the first tunnel junction layer, and a lattice constant of the first n-type (alx2ga1-x2)y2in1-y2p layer is greater than a lattice constant of the first photoelectric conversion cell..
Rich Company, Ltd.

Solar cell module

A solar cell module includes first and second solar cells each including a semiconductor substrate, and first electrodes and second electrodes that have different polarities on the semiconductor substrate and extend in a first direction, and a plurality of conductive lines extended in the second direction, disposed on the semiconductor substrate of each of the first and second solar cells, and connected to the first electrodes or the second electrodes of each of the first and second solar cells, thereby connecting in series the first and second solar cells in the second direction. Each conductive line includes an uneven portion, in a thickness direction of the semiconductor substrate, a remaining portion except a portion of the conductive line connected to the first electrodes or the second electrodes..
Lg Electronics Inc.

Optical cladding layer design

Embodiments of the invention describe apparatuses, optical systems, and methods related to utilizing optical cladding layers. According to one embodiment, a hybrid optical device includes a silicon semiconductor layer and a iii-v semiconductor layer having an overlapping region, wherein a majority of a field of an optical mode in the overlapping region is to be contained in the iii-v semiconductor layer.

Solar cell element, manufacturing solar cell element and solar cell module

A solar cell element comprises a semiconductor substrate, a passivation layer and a protective layer. The semiconductor substrate includes a p-type semiconductor region on one main surface thereof.
Kyocera Corporation

Semiconductor device and semiconductor device manufacturing method

This semiconductor device includes: a semiconductor layer (6) that is formed of first conductivity-type sic; a plurality of trenches (8) that are formed in the semiconductor layer; second conductivity-type column regions (12) that are formed along the inner surfaces of the trenches; a first conductivity-type column region (13) that is disposed between the adjacent second conductivity-type column regions; and insulating films (14) that are embedded in the trenches. The semiconductor device is capable of improving a withstand voltage by means of a super junction structure.
Rohm Co., Ltd.

Semiconductor device

A semiconductor device according to an embodiment includes a first metal layer, a second metal layer, an n-type first sic region provided between the first metal layer and the second metal layer and having an n-type impurity concentration of 1×1018 cm−3 or less, and a conductive layer provided between the first sic region and the first metal layer and containing titanium (ti), oxygen (o), and at least one element selected from the group consisting of vanadium (v), niobium (nb), and tantalum (ta).. .
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing the same

A semiconductor device is provided. The semiconductor device includes a substrate; a well region disposed in the substrate; an isolation structure surrounding an active region in the well region; a source region disposed in the well region; a drain region disposed in the well region; a second conductive type first doped region disposed in the well region and disposed along a periphery of the active region; a second conductive type second doped region disposed in the well region and under the source region, the drain region and the second conductive type first doped region, wherein the second conductive type second doped region is in direct contact with the second conductive type first doped region; a source electrode; a drain electrode and a gate electrode.
Vanguard International Semiconductor Corporation

Semiconductor device

A semiconductor device includes a first pillar-shaped semiconductor layer, a first selection gate insulating film, a first selection gate, a first gate insulating film, a first contact electrode, a first bit line connected to an upper portion of the first pillar-shaped semiconductor layer and an upper portion of the first contact electrode, a second pillar-shaped semiconductor layer, a layer including a first charge storage layer, a first control gate, a layer including a second charge storage layer and formed above the first control gate, a second control gate, a second gate insulating film, a second contact electrode having an upper portion connected to an upper portion of the second pillar-shaped semiconductor layer, and a first lower internal line that connects a lower portion of the first pillar-shaped semiconductor layer and a lower portion of the second pillar-shaped semiconductor layer.. .
Unisantis Electronics Singapore Pte. Ltd.

Wafer with soi structure having a buried insulating multilayer structure and semiconductor device structure

The present disclosure provides, in a first aspect, a semiconductor device structure, including an soi substrate comprising a semiconductor base substrate, a buried insulating structure formed on the semiconductor base substrate and a semiconductor film formed on the buried insulating structure, wherein the buried insulating structure comprises a multilayer stack having a nitride layer interposed between two oxide layers. The semiconductor device structure further includes a semiconductor device formed in and above an active region of the soi substrate, and a back bias contact which is electrically connected to the semiconductor base substrate below the semiconductor device..
Globalfoundries Inc.

Semiconductor device

A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack.
Semiconductor Energy Laboratory Co., Ltd.

Display device

According to one embodiment, a display device includes a first light shielding layer, a second light shielding layer, a first semiconductor layer, a second semiconductor layer, a gate line, a first source line, a second source line, a switching element, and a pixel electrode, wherein an area in which the first light shielding layer and the pixel electrode are opposed to each other and an area in which the second light shielding layer and the pixel electrode are opposed to each other are equal in size.. .
Japan Display Inc.

Semiconductor device

According to one embodiment, a semiconductor device includes first to third semiconductor regions and first to third conductors. The second semiconductor region is separated from the first semiconductor region in a first direction.
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing the same

Provided is a semiconductor device, which prevents unnecessary voltage drop in a mos transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the on/off ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film..
Sii Semiconductor Corporation

Field-effect transistor, and memory and semiconductor circuit including the same

Provided is a field-effect transistor (fet) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface, a gate insulating film formed to cover the oxide semiconductor, and a gate electrode which is formed to cover the gate insulating film.
Semiconductor Energy Laboratory Co., Ltd.

Oxide semiconductor thin film, thin film transistor, manufacturing

This disclosure discloses an oxide semiconductor thin film, a thin film transistor, a manufacturing method and a device, belonging to the field of flat panel display. The oxide semiconductor thin film is made of an oxide containing zirconium and indium.
South China University Of Technology

Vertical slit transistor with optimized ac performance

A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent respective sidewalls of the semiconductor substrate.
International Business Machines Corporation

Semiconductor device and forming the same

A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

According to one embodiment, a semiconductor device includes a first element isolating area, a first element area surrounding the first element isolating area, a second element isolating area surrounding the first element area a first gate electrode provided on and across the first element isolating area, the first element area, and the second element isolating area, and a second gate electrode isolated from the first gate electrode and provided on and across the first element isolating area, the first element area, and the second element isolating area.. .
Kabushiki Kaisha Toshiba

Enhanced volume control by recess profile control

The present disclosure relates to a semiconductor device that controls a strain on a channel region by forming a dielectric material in recesses, adjacent to a channel region, in order to provide control over a volume and shape of a strain inducing material of epitaxial source/drain regions formed within the recesses. In some embodiments, the semiconductor device has epitaxial source/drain regions arranged in recesses within an upper surface of a semiconductor body on opposing sides of a channel region.
Taiwan Semiconductor Manufacturing Co., Ltd.

Methods of making source/drain regions positioned inside u-shaped semiconductor material using source/drain placeholder structures

One illustrative method disclosed herein includes, among other things, forming a liner semiconductor material within a trench, the liner material defining a transistor cavity, and forming spaced-apart source/drain placeholder structures that are at least partially positioned within the transistor cavity, the spaced-apart source/drain placeholder structures defining a gate cavity therebetween where a portion of the liner semiconductor material is exposed within the gate cavity. The method further includes forming a gate structure within the gate cavity and, after forming the gate structure, removing at least a portion of the source/drain placeholder structures to define a plurality of source/drain cavities within the transistor cavity on opposite sides of the gate structure, and forming a source/drain structure in each of the source drain cavities..
Globalfoundries Inc.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, at least one first isolation structure, at least two second isolation structures, and a plurality of epitaxy structures. The substrate has a plurality of semiconductor fins therein.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

A semiconductor device of an embodiment includes an sic layer having a first and a second plane, an n-type first sic region in the sic layer, p-type second sic regions between the first sic region and the first plane, n-type third sic regions between the second sic regions and the first plane, a gate electrode provided between two p-type second sic regions, a gate insulating film provided between the gate electrode and the second sic regions, a metal layer provided between two p-type second sic regions, and having a work function of 6.5 ev or more, and a first electrode electrically connected to the metal layer, and a second electrode, the sic layer provided between the first electrode and the second electrode, and a part of the first sic region is disposed between the gate insulating film and the metal layer.. .
Kabushiki Kaisha Toshiba

Semiconductor device

A semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type that is between the first electrode and the second electrode. A second semiconductor region is adjacent to the first semiconductor region along a first direction and includes a second conductivity type material.
Kabushiki Kaisha Toshiba

Semiconductor device with gate inside u-shaped channel and methods of making such a device

One illustrative method disclosed herein includes, among other things, forming a trench in a semiconductor substrate, forming a liner semiconductor material above the entire interior surface of the trench, the liner semiconductor material defining a transistor cavity, forming a gate structure that is at least partially positioned within the transistor cavity, and performing at least one epitaxial deposition process to form a source region structure and a drain region structure on opposite sides of the gate structure, wherein at least a portion of each of the source region structure and the drain region structure is positioned within the transistor cavity.. .
Globalfoundries Inc.

Partially biased isolation in semiconductor device

Embodiments of a device are provided, including a semiconductor substrate including an active device area; a body region disposed in the semiconductor substrate within the active device area, wherein a channel is formed within the body region during operation; a doped isolation layer disposed in the semiconductor substrate underneath the active device area, the doped isolation layer including an opening positioned under the active device area; and a lightly-doped isolation layer disposed in the semiconductor substrate underneath the active device area, the lightly-doped isolation layer positioned at least within the opening and in electrical contact with the doped isolation layer, wherein the doped isolation layer and the lightly-doped isolation layer form a doped isolation barrier that extends across an entire lateral extent of the active device area.. .
Nxp Usa, Inc.

Partially biased isolation in semiconductor devices

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region..
Freescale Semiconductor, Inc.

Semiconductor device having gate structures and manufacturing method thereof

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a high-voltage doped region having the first conductivity type and disposed in the high-voltage well, a drain region disposed in the high-voltage well and spaced apart from the high-voltage doped region, a source region disposed in the high-voltage doped region, a first gate structure disposed above a first side portion of the high-voltage doped region between the source region and the drain region, and a second gate structure disposed above a second and opposite side portion of the high-voltage doped region.. .
Macronix International Co., Ltd.

Trench-gate semiconductor device and manufacturing method thereof

A trench gate semiconductor device includes a high concentration first conductivity type semiconductor layer, a low concentration first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and a trench. The second conductivity type semiconductor is provided at a position corresponding to the bottom-side portion of the trench.
Kabushiki Kaisha Toyota Jidoshokki

Semiconductor device and a making a semiconductor device

A semiconductor device and a method of making a semiconductor device. The device includes a semiconductor substrate having a first conductivity type, a layer of doped silicon located on the substrate, a trench extending into the layer of silicon, and a gate electrode and gate dielectric located in the trench.
Nxp B.v.

Method for manufacturing semiconductor device and semiconductor device

A method for manufacturing a semiconductor device according to an embodiment includes implanting impurity ions into a sic layer in a direction of <10-11>±1 degrees, <10-1-1>±1 degrees, <10-12>±1 degrees, or <10-1-2>±1 degrees.. .
Kabushiki Kaisha Toshiba

Semiconductor device

A semiconductor device according to an embodiment includes a sic layer having a first plane and a second plane, a first sic region of a first conductivity type which is provided in the sic layer, first and second pillar regions of a second conductivity type, third and fourth pillar regions of a second conductivity type which are provided between the first and second pillar regions and the first plane, a gate electrode provided between the third pillar region and the fourth pillar region, first and second body regions of the second conductivity type, a gate insulating film, fifth and sixth pillar regions provided between the third and fourth pillar regions and the gate electrode, first and second source regions of the first conductivity type.. .
Kabushiki Kaisha Toshiba

Semiconductor device

A semiconductor device according to an embodiment includes a conductive region including titanium (ti), oxygen (o), at least one first element from zirconium (zr) and hafnium (hf), and at least one second element from vanadium (v), niobium (nb), and tantalum (ta), an n-type first sic region, a p-type second sic region provided between the conductive region and the n-type first sic region, a gate electrode, and a gate insulating layer provided between the conductive region, the p-type second sic region, the n-type first sic region, and the gate electrode.. .
Kabushiki Kaisha Toshiba

Semiconductor device including fin fet and manufacturing method thereof

A semiconductor device includes a fin structure for a fin field effect transistor (fet). The fin structure includes a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer.
Taiwan Semiconductor Manufacturing Company

Semiconductor device

A semiconductor device includes a sic layer having a first surface, a gate insulating film on the first surface, a gate electrode on the gate insulating film, a first sic region of a first conductivity type in the sic layer, a second sic region of a second conductivity type in the first sic region, a third sic region of the first conductivity type in the second sic region, wherein a boundary between the second sic region and the third sic region, and the first surface forms a first angle, and a fourth sic region of the first conductivity type in the third sic region, having an impurity concentration of the first conductivity type higher than that of the third sic region, wherein a boundary between the third sic region and the fourth sic region, and the first surface forms a second angle that is smaller than the first angle.. .
Kabushiki Kaisha Toshiba

Semiconductor device

A semiconductor device includes a first nitride semiconductor layer, a source electrode on the first nitride semiconductor layer, a drain electrode on the first nitride semiconductor layer, a gate electrode on the first nitride semiconductor layer and between the source electrode and the drain electrode, a gate field plate electrode that is separated from the first nitride semiconductor layer, and includes one end in direct contact with the gate electrode, and the other end positioned between the gate electrode and the drain electrode, a first interlayer insulating film that is separated from the gate electrode and is between the gate field plate electrode and the first nitride semiconductor layer, and a second interlayer insulating film that is between the gate electrode and the first interlayer insulating film and has a dielectric constant higher than a dielectric constant of the first interlayer insulating film.. .
Kabushiki Kaisha Toshiba

High electron mobility transistor and forming the same using atomic layer deposition technique

A hemt made of nitride semiconductor materials is disclosed. The hemt includes the gan channel layer, the inaln barrier layer, and the n-type gan regions formed beneath the source electrode and the drain electrode at a temperature such that the inaln barrier layer in the crystal quality thereof is not degraded, lower than 800° c.
Sumitomo Electric Industries, Ltd.

Electronical device

Provided is an electronic device. The electronic device includes a first semiconductor layer and a second semiconductor layer sequentially stacked on a substrate and a source electrode, a gate electrode, and a drain electrode arranged on the second semiconductor layer.
Electronics And Telecommunications Research Institute

High electron mobility transistor fabrication process on reverse polarized substrate by layer transfer

A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier substrate to form a composite structure wherein the barrier layer is disposed between the polar compound semiconductor layer and the carrier substrate; separating the sacrificial substrate from the composite structure to expose the polar compound semiconductor layer; and forming at least one circuit device. An apparatus including a barrier layer on a substrate; a transistor device on the barrier layer; and a polar compound semiconductor layer disposed between the barrier layer and the transistor device, the polar compound semiconductor layer including a two-dimensional electron gas therein..
Intel Corporation

Semiconductor device and manufacturing a semiconductor device

A semiconductor device includes a substrate, a first layer above the substrate and including a nitride semiconductor layer of a first conductivity type, a second layer on the first layer and including a nitride semiconductor layer of the first conductivity type containing al, an insulating film on the upper surface of the second layer in a first region of the upper surface of the second layer, a third layer on the upper surface of the second layer in a second region of the upper surface of the second layer, the third layer including a nitride semiconductor layer of a second conductivity type, the third layer including a first portion in contact with the second layer and a second portion on the first portion, and an electrode on the second portion. A width of the first portion is larger than that of the second region and that of the first portion..
Kabushiki Kaisha Toshiba

Semiconductor device

A semiconductor device includes a semiconductor substrate which includes a first surface, a second surface, and an end portion, the semiconductor substrate including a first region of a p-type and a second region of an n-type provided in a corner portion of the semiconductor substrate between the first surface and the end surface, a nitride semiconductor layer on the first surface, and an electrode on the nitride semiconductor layer.. .
Kabushiki Kaisha Toshiba

Device with channel having varying carrier concentration

A semiconductor device including a device channel with a gate-drain region having a carrier concentration that varies laterally along a direction from the gate contact to the drain contact is provided. Lateral variation of the carrier concentration can be implemented by laterally varying one or more attributes of one or more layers located in the gate-drain region of the device..
Sensor Electronic Technology, Inc.

Semiconductor device

A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a source electrode provided on the first nitride semiconductor layer; a drain electrode provided on the first nitride semiconductor layer; a gate electrode provided between the source electrode and the drain electrode; a first film provided between the source electrode and the gate electrode and between the gate electrode and the drain electrode; and a second film provided on the first film. The first film is provided on the first nitride semiconductor layer.
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing the same

A semiconductor device includes: a substrate; a nitride semiconductor film on the substrate; a schottky electrode on the nitride semiconductor film; a first insulating film on the nitride semiconductor film, contacting at least part of a side surface of the schottky electrode, forming an interface with the nitride semiconductor film and formed of sin; and a second insulating film covering the schottky electrode and the first insulating film and formed of alo whose atomic layers are alternately disposed.. .
Mitsubishi Electric Corporation

Semiconductor device and manufacturing method

A semiconductor device including a semiconductor substrate; a trench formed in a front surface of the semiconductor substrate; a gate conducting portion formed within the gate trench; and a first region formed adjacent to the trench in the front surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. A shoulder portion is provided on a side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the gate trench at a position opposite the top end of the gate conducting portion, and a portion of the first region that contacts the gate trench is formed as a deepest portion thereof..
Fuji Electric Co., Ltd.

Semiconductor device and driving same

A semiconductor device according to an embodiment includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, a first electrode connected to the second semiconductor layer and the fourth semiconductor layer, a second electrode facing the second semiconductor layer with an insulating film interposed, a fifth semiconductor layer of the second conductivity type, a sixth semiconductor layer of the first conductivity type, a seventh semiconductor layer of the second conductivity type, a third electrode connected to the fifth semiconductor layer and the seventh semiconductor layer, and a fourth electrode facing the fifth semiconductor layer with an insulating film interposed.. .
Kabushiki Kaisha Toshiba

Semiconductor device and inverter including the semiconductor device

A semiconductor device includes a conductivity type drain layer, a conductivity type drift layer, conductivity type base regions located in an upper surface of the drift layer, a conductivity type source region which is disposed inside each of the base regions and is spaced apart from the periphery of the base region, and a channel region is formed between the source region and the periphery of the base region. The semiconductor device further includes a gate insulating layer covering the channel region, a gate electrode which is located on the gate insulating layer and faces the channel region, a plurality of conductivity type column regions, each extends from the plurality of base regions to the drain layer in the drift layer, a trap level forming region in the drift layer, a drain electrode electrically connected to the drain layer, and a source electrode electrically connected to the source region..
Rohm Co., Ltd.

Array substrate for liquid crystal display device and manufacturing the same

An array substrate for a liquid crystal display device includes a substrate; a semiconductor layer on the substrate; a gate electrode on the semiconductor layer; source and drain electrodes that are on and contact the semiconductor layer; and an oxide layer that corresponds to the semiconductor layer and is on the gate electrode.. .
Lg Display Co., Ltd.

Vertical junction finfet device and manufacture

A vertical junction field effect transistor (jfet) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends.
Stmicroelectronics, Inc.

Punch through stopper in bulk finfet device

A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure.
International Business Machines Corporation

Method for producing semiconductor device

A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; and a second step following the first step and including forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to conduct planarization, forming a second resist for forming a gate line and a pillar-shaped semiconductor layer so that the second resist extends in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer and a first dummy gate formed of the first polysilicon.. .
Unisantis Electronics Singapore Pte.ltd:

Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins

A method of making a semiconductor device includes forming a fin in a substrate; depositing a first spacer material to form a first spacer around the fin; depositing a second spacer material to form a second spacer over the first spacer; recessing the first spacer and the second spacer; removing the first spacer; and performing an epitaxial growth process to form epitaxial growth on an end of the fin, along a sidewall of the fin, and adjacent to the fin.. .
Globalfoundries, Inc.

Semiconductor device

A semiconductor device includes a fin-shaped semiconductor layer and a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A metal gate line is connected to a metal gate electrode and extends in a direction perpendicular to a direction that of the fin-shaped semiconductor layer.
Unisantis Electronics Singapore Pte. Ltd.

Method of manufacturing semiconductor device

A manufacturing method includes an implantation of impurities and laser irradiation. In the implantation, impurities are implanted to first and second areas so as to obtain a relationship that a total amount of the first impurities is larger than a total amount of the second impurities in a first depth range and a total amount of the second impurities is larger than a total amount of the first impurities in a second depth range (deeper range).
Toyota Jidosha Kabushiki Kaisha

Semiconductor device

A semiconductor device according to an embodiment includes a semiconductor region, a gate electrode, and a first gate insulating film provided between the semiconductor region and the gate electrode and containing a material having a chemical composition expressed by (sio2)n(si3n4)m (where n and m are positive integers), in the material, at least one silicon atom being bonded with at least one oxygen atom and at least one nitrogen atom.. .
Kabushiki Kaisha Toshiba

Spacer chamfering gate stack scheme

A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width..
Globalfoundries Inc.

Preventing leakage inside air-gap spacer during contact formation

Techniques for preventing leakage of contact material into air-gap spacers during contact formation. For example, a method comprises forming a contact trench on a semiconductor structure over an air-gap spacer and depositing a liner in the contact trench.
Globalfoundries Inc.

Semiconductor structure

A semiconductor structure is disclosed. The semiconductor structure includes a substrate, and an interlayer dielectric disposed on the substrate which has agate structure therein.
United Microelectronics Corp.

Ohmic contact structure for group iii nitride semiconductor device having improved surface morphology and well-defined edge features

Embodiments of an ohmic contact structure for a group iii nitride semiconductor device and methods of fabrication thereof are disclosed. In general, the ohmic contact structure has a root-mean-squared (rms) surface roughness of less than 10 nanometers, and more preferably less than or equal to 7.5 nanometers, and more preferably less than or equal to 5 nanometers, and more preferably less than or equal to 2 nanometers, and even more preferably less than or equal to 1.5 nanometers..
Cree, Inc.

Contacts for highly scaled transistors

A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain(s/d) regions, a channel between the first and second s/d regions, a gate engaging the channel, and a contact feature connecting to the first s/d region.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

A semiconductor device includes a silicon carbide layer having first and second surfaces, a first insulating film on the first surface, a first electrode on the first insulating film, a first silicon carbide region of a first conductivity type in the silicon carbide layer, a second silicon carbide region of a second conductivity type in the first silicon carbide region, a third silicon carbide region of the first conductivity type in the second silicon carbide region, a second electrode on the second surface, which contains metal, silicon, and carbon, and a third electrode in contact with the third silicon carbide region, which contains metal, silicon, and carbon, and has a carbon concentration higher than a carbon concentration of the second electrode.. .
Kabushiki Kaisha Toshiba

Semiconductor device with stripe-shaped trench gate structures and gate connector structure

A semiconductor device includes a transistor cell with a stripe-shaped trench gate structure that extends from a first surface into a semiconductor body. A gate connector structure at a distance to the first surface is electrically connected to a gate electrode in the trench gate structure.
Infineon Technologies Ag

High-voltage metal-oxide-semiconductor transistor device and manufacturing method thereof

The present invention provides a high-voltage metal-oxide-semiconductor transistor device and a manufacturing method thereof. First, a semiconductor substrate is provided and a dielectric layer and a conductive layer sequentially stacked on the semiconductor substrate.
United Microelectronics Corp.

Finfet device with vertical silicide on recessed source/drain epitaxy regions

A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure.
International Business Machines Corporation

Semiconductor device including contact plug and manufacturing the same

A semiconductor device includes an active fin partially protruding from an isolation pattern on a substrate, a gate structure on the active fin, a source/drain layer on a portion of the active fin adjacent to the gate structure, a source/drain layer on a portion of the active fin adjacent to the gate structure, a metal silicide pattern on the source/drain layer, and a plug on the metal silicide pattern. The plug includes a second metal pattern, a metal nitride pattern contacting an upper surface of the metal silicide pattern and covering a bottom and a sidewall of the second metal pattern, and a first metal pattern on the metal silicide pattern, the first metal pattern covering an outer sidewall of the metal nitride pattern.
Samsung Electronics Co., Ltd.

Methods of forming semiconductor device with self-aligned contact elements and the resulting device

One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A transistor device disclosed herein includes a final gate structure that has an upper surface positioned at a first height level above a surface of a substrate, sidewall spacers positioned adjacent the final gate structure, the sidewall spacers having an upper surface that is positioned at a second, greater height level above the substrate, an etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure, and a conductive contact that is conductively coupled to a contact region of the transistor..
Globalfoundries Inc.

Thin film transistor panel having an etch stopper on semiconductor

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.. .
Samsung Display Co., Ltd.

Semiconductor device and forming the same

A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Sintered oxide, sputtering target, and oxide semiconductor thin film obtained using sputtering target

An oxide sintered body which, when made into an oxide semiconductor thin film by sputtering, can achieve low carrier density and high carrier mobility, and a sputtering target using said oxide sintered body are provided. This oxide sintered body contains indium and gallium as oxides, contains nitrogen, and does not contain zinc.
Sumitomo Metal Mining Co., Ltd.

Semiconductor device

According to embodiments, a semiconductor device includes a first laminated nitride semiconductor layer in which first nitride semiconductor layers and second nitride semiconductor layers are alternately laminated; a third nitride semiconductor layer; a fourth nitride semiconductor layer; a drain electrode; a source electrode; and a gate electrode. The first nitride semiconductor layer is carbon-containing gallium nitride.
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing the same

A semiconductor device according to embodiments includes a p-type sic region, a gate insulating film disposed on the p-type sic region, and a gate electrode disposed on the gate insulating film and including a p-type impurity and 3c-sic.. .
Kabushiki Kaisha Toshiba

Semiconductor device

A semiconductor device of an embodiment includes an n-type sic region, a metal layer, and a conductive layer provided between the n-type sic region and the metal layer, the conductive layer including titanium (ti), oxygen (o), at least one first element from zirconium (zr) and hafnium (hf), and at least one second element from vanadium (v), niobium (nb), and tantalum (ta).. .
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing the same

Provided is a semiconductor device according to an embodiment including: a first electrode; a second electrode; a third electrode provided between the first electrode and the second electrode; a first insulating film provided between the third electrode and the second electrode; a silicon carbide layer provided between the first insulating film and the second electrode; a first silicon carbide region provided between the third electrode and the second electrode, the first silicon carbide region being provided in the silicon carbide layer; a second silicon carbide region provided between the third electrode and the first silicon carbide region, the second silicon carbide region being provided in the silicon carbide layer; a third silicon carbide region provided between the third electrode and the second silicon carbide region, the third. Silicon carbide region being provided in the silicon carbide layer; a fourth silicon carbide region provided between the third silicon carbide region and the second silicon carbide region, the fourth silicon carbide region being provided in the silicon carbide layer; and a fourth electrode provided between the first electrode and the fourth silicon carbide region, the fourth electrode being provided laterally adjacent to the third silicon carbide region, the fourth electrode containing a metal silicide, a first distance between the first electrode and a first interface between the fourth electrode and the fourth silicon carbide region being longer than a second distance between the first electrode and a second interface between the third silicon carbide region and the fourth silicon carbide region, and a third distance between a third interface between the fourth electrode and the first electrode and a fourth interface between the third silicon carbide region and the fourth silicon carbide region being shorter than a fourth distance between the fourth interface and a fifth interface between the third silicon carbide region and the first electrode..
Kabushiki Kaisha Toshiba

Semiconductor device

A semiconductor device according to an embodiment includes a sic layer having a first plane and a second plane, a gate insulating film provided on the first plane, a gate electrode provided on the gate insulating film, a first sic region of a first conductivity type provided in the sic layer, a second sic region of a second conductivity type provided in the first sic region, a third sic region of the first conductivity type provided in the second sic region, and a fourth sic region of the first conductivity type provided between the second sic region and the gate insulating film, the fourth sic region interposed between the second sic regions, and the fourth sic region provided between the first sic region and the third sic region.. .
Kabushiki Kaisha Toshiba

Semiconductor device

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a first electrode on the first surface, a second electrode on the second surface, a first semiconductor region of a first conductivity type in the semiconductor layer, a second semiconductor region of a second conductivity type in an element region of the semiconductor layer between the first semiconductor region and the first electrode, a third semiconductor region of the second conductivity type between the second semiconductor region and the first electrode, and a fourth semiconductor region of the second conductivity type in a termination region of the semiconductor layer inwardly of the first surface. A distance between the fourth semiconductor region and the second surface is greater than a distance between the second semiconductor region and the second surface..
Kabushiki Kaisha Toshiba

Devices and methods of creating elastic relaxation of epitaxially grown lattice mismatched films

Devices and methods of creating elastic relaxation of epitaxially grown lattice mismatched films for semiconductor devices are provided. One method includes, for instance: obtaining a wafer including a substrate; epitaxially growing at least one first silicon germanium (sige) layer over the wafer; and epitaxially growing at least one second sige layer over the at least one first sige layer.
Globalfoundries Inc.

Multi-gate semiconductor devices with improved hot-carrier injection immunity

A semiconductor device includes a substrate having a first dopant type, a first gate electrode and second gate electrode formed over the substrate and spatially separated from each other, a first region of a second dopant type, having a pocket of the first dopant type, formed in the substrate between the first and second gate electrodes, the pocket being spaced apart from the first and second gate electrodes, a silicide block over the first region, a source region formed in the substrate on an opposing side of the first gate electrode from the first region and having the second dopant type, a drain region formed in the substrate on an opposing side of the second gate electrode from the first region, the drain region having the second dopant type, and a second pocket of the first dopant type formed in the drain region adjacent to the second gate electrode.. .
Freescale Semiconductor Inc.

Strained stacked nanowire field-effect transistors (fets)

A method for manufacturing a semiconductor device comprises epitaxially growing a plurality of silicon layers and compressively strained silicon germanium (sige) layers on a substrate in a stacked configuration, wherein the silicon layers and compressively strained sige layers are alternately stacked on each other starting with a silicon layer on a bottom of the stacked configuration, patterning the stacked configuration to a first width, selectively removing a portion of each of the silicon layers in the stacked configuration to reduce the silicon layers to a second width less than the first width, forming an oxide layer on the compressively strained sige layers of the stacked configuration, wherein forming the oxide layer comprises fully oxidizing the silicon layers so that portions of the oxide layer are formed in place of each fully oxidized silicon layer, and removing part of the oxide layer while maintaining at least part of the portions of the oxide layer formed in place of each fully oxidized silicon layer, wherein the compressively strained sige layers are anchored to one another and a compressive strain is maintained in each of the compressively strained sige layers.. .
International Business Machines Corporation

Semiconductor device

This semiconductor device comprises a plurality of first conductive layers arranged above a substrate in a first direction intersecting an upper surface of the substrate. The conductive layers includes a portion in which positions of ends of the first conductive layers made different from each other in a second direction intersecting the first direction.
Kabushiki Kaisha Toshiba

Semiconductor structure having epitaxial layers

The present invention provides a semiconductor structure, including a substrate having a first conductivity region and a second conductivity region defined thereon, a plurality of first fin structures and at least one first gate structure disposed on the substrate and within the first conductivity region, a plurality of second fin structures and at least one second gate structure disposed on the substrate and within the second conductivity region, at least two first crown epitaxial layers disposed within the first conductivity region, a plurality of second epitaxial layers disposed within the second conductivity region, where the shape of the first crown epitaxial layer is different from that of the second epitaxial layer.. .
United Microelectronics Corp.

Finfet device and fabricating the same

A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins and a source/drain structure. The semiconductor fins and the source/drain structure are located on the semiconductor substrate, and the source/drain structure is connected to the semiconductor fins.
Taiwan Semiconductor Manufacturing Co., Ltd.

Needle field plate mosfet with mesa contacts and conductive posts

There are disclosed herein various implementations of a vertical metal-oxide-semiconductor field-effect transistor (mosfet). Such a vertical mosfet includes a semiconductor substrate having a drift region situated over a drain, a gate trench and needle field plates extending into the drift region, and source regions situated in respective mesas.
Infineon Technologies Austria Ag

Method of forming nanostructure, manufacturing semiconductor device using the same, and semiconductor device including nanostructure

Provided are methods of forming nanostructures, methods of manufacturing semiconductor devices using the same, and semiconductor devices including nanostructures. A method of forming a nanostructure may include forming an insulating layer and forming a nanostructure on the insulating layer.
Samsung Electronics Co., Ltd.

Semiconductor structure, integrated circuit device, and forming semiconductor structure

A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region..
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor devices

A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a gate structure; and forming offset sidewall spacers around the gate structure.
Semiconductor Manufacturing International Shanghai) Corporation

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, at least one first isolation structure, at least two second isolation structure, and an epitaxy structure. The substrate has a plurality of semiconductor fins therein.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

A semiconductor device includes a sic layer that has a first surface and a second surface, a first electrode in contact with the first surface, a first sic region of a first conductivity type in the sic layer, a second sic region of a second conductivity type in the sic layer and surrounding a portion of the first sic region, a third sic region of the second conductivity type in the sic layer and surrounding the second sic region, the third sic region having an impurity concentration of the second conductivity type lower than that of the second sic region, and a fourth sic region of the second conductivity type in the sic layer between the second sic region and the third sic region, the fourth sic region having an impurity concentration of the second conductivity type higher than that of the second sic region.. .
Kabushiki Kaisha Toshiba

Partially biased isolation in semiconductor devices

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area, and a body region disposed in the semiconductor substrate within the core device area, and in which a channel is formed during operation. The body region is electrically tied to the isolation contact region.
Freescale Semiconductor, Inc.

Semiconductor device

Provided is a semiconductor device including a first electrode, a second electrode, a semiconductor substrate having a first plane, a second plane, a first conductivity-type first region, and a plurality of second conductivity-type second regions provided around the first electrode, the second regions being in contact with the first plane, at least a portion of the semiconductor substrate being provided between the first electrode and the second electrode, a first insulating film provided on or above the second regions, the first insulating film including positive charges, and a second insulating film provided on or above the second regions, second insulating film including negative charges.. .
Kabushiki Kaisha Toshiba

Semiconductor device

To improve withstand capability of a semiconductor device during reverse recovery, provided is a semiconductor device including a semiconductor substrate having a first conduction type; a first region having a second conduction type that is formed in a front surface of the semiconductor substrate; a second region having a second conduction type that is formed adjacent to the first region in the front surface of the semiconductor substrate and has a higher concentration than the first region; a third region having a second conduction type that is formed adjacent to the second region in the front surface of the semiconductor substrate and has a higher concentration than the second region; an insulating film that covers a portion of the second region and the third region; and an electrode connected to the second region and the first region that are not covered by the insulating film.. .
Fuji Electric Co., Ltd.

Semiconductor device

A semiconductor device includes a semiconductor substrate with: a drift layer; a base layer; and a collector layer and a cathode layer. In the semiconductor substrate, when a region operating as an igbt device is an igbt region and a region operating as a diode device is a diode region, the igbt and diode regions are arranged alternately in a repetitive manner; a damaged region is arranged on a surface portion of the diode region in the semiconductor substrate.
Denso Corporation

Electronic device and manufacturing electronic device

According to one embodiment, an electronic device includes a first element provided on a semiconductor substrate and used for actual operation, and a second element unit constituted by at least one second element for evaluation provided on the semiconductor substrate, wherein the first element includes a first plate-like portion and a first thin-film portion covering the first plate-like portion and forming a cavity therein, and the second element unit includes a plurality of second plate-like portions having different lengths, and at least one second thin-film portion covering the second plate-like portions and forming a cavity therein.. .
Kabushiki Kaisha Toshiba

Display apparatus and manufacturing the same

A display apparatus includes a substrate having a plurality of pixel areas, and a pixel circuit including a storage capacitor and a plurality of thin film transistors (tfts) which are disposed in each pixel area. At least one of the plurality of tfts includes a semiconductor layer disposed on the substrate and including a first ion impurity, a source area and a drain area, which are spaced apart from each other, have a first depth from a surface of the semiconductor layer, and include a second ion impurity, a gate electrode disposed on the semiconductor layer between the source area and the drain area, and a bias wiring electrically connected to the semiconductor layer and disposed adjacent to at least one of the source area and the drain area..
Samsung Display Co., Ltd.

Semiconductor memory device and manufacturing the same

The embodiments provide a semiconductor memory device including: a plurality of first wiring lines extending in a first direction, the first wiring lines being provided in a second direction intersecting the first direction; a plurality of second wiring lines extending in the second direction, the second wiring lines being provided in the first direction; a plurality of memory cells provided in the intersections between the first wiring lines and the second wiring lines, each memory cell having a first stack structure comprising at least a variable resistor film; a contact extending in a third direction intersecting the first and second directions, the contact having a first end connected to one of the first wiring lines or one of the second wiring lines, the contact having a second stack structure having a stack of a plurality of films; and a wiring layer connected to a second end of the contact. At least some of the films of the second stack structure have generally the same third direction position and film thickness as at least some of layers of the first stack structure.
Kabushiki Kaisha Toshiba

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device includes a memory cell array. The memory cell array includes conducting layers, semiconductor layers, variable resistance films, and first wirings.
Kabushiki Kaisha Toshiba

Nonvolatile storage device, semiconductor element, and capacitor

A nonvolatile storage device of an embodiment includes a first wiring layer extending in a first direction, a second wiring layer extending in a second direction intersecting with the first direction, a conductive layer between the first wiring layer and the second wiring layer at an intersection of the first wiring layer and the second wiring layer, and a resistance change region including at least one of an oxide, a nitride, and an oxynitride in the first wiring layer. The resistance change region exists in the first wiring layer including an interface between the first wiring layer and the conductive layer..
Kabushiki Kaisha Toshiba

Magnetic memory device

According to one embodiment, a magnetic memory device includes a stack structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, wherein the second magnetic layer includes a first layer containing iron (fe) and boron (b), a second layer containing iron (fe) and boron (b), and a third layer provided between the first layer and the second layer and containing a semiconductor.. .
Kabushiki Kaisha Toshiba

Variable resistance memory

According to one embodiment, a variable resistance memory includes first and second semiconductor regions in a layer; a memory cell on the first semiconductor region, the memory cell including a first transistor having a first gate connected to a word line and a memory element, the word line extending in a first direction parallel to a surface of the layer; and a second transistor on the second semiconductor region and connected to the memory cell via a bit line, the bit line extending a second direction parallel to the surface of the layer, and the second direction intersecting the first direction. The second semiconductor region extends in a third direction parallel to the surface of the substrate and the third direction intersects the first and second directions..
Kabushiki Kaisha Toshiba

Magnetic memory and manufacturing same

According to one embodiment, a magnetic memory includes a structure body including a first magnetic layer and a conductive layer, a second magnetic layer, a first electrode, a second electrode, a third magnetic layer, an intermediate layer, a third electrode, a fourth magnetic layer, and a circuit element. The first magnetic layer is disposed between the second magnetic layer and the conductive layer.
Kabushiki Kaisha Toshiba

Light-emitting unit

To provide a light-emitting unit having a semiconductor light-emitting device with a good responsiveness and a sufficient light emission quantity. The light-emitting unit comprises a plurality of semiconductor light-emitting devices, an n-wiring electrode and a p-wiring electrode respectively connecting the semiconductor light-emitting devices in parallel, an n-pad electrode connected to the n-wiring electrode, and a p-pad electrode connected to the p-wiring electrode.
Toyoda Gosei Co., Ltd.

Method of producing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and producing solid-state image sensing device

A method of producing a semiconductor epitaxial wafer 100 according to the present invention includes a first step of irradiating a semiconductor wafer 10 with cluster ions 16 to form a modifying layer 18 formed from a constituent element of the cluster ions 16 in a surface portion 10a of the semiconductor wafer; and a second step of forming an epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer 10.. .

Semiconductor device and manufacturing method thereof

A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region.
United Microelectronics Corp.

Stacked semiconductor chip rgbz sensor

An apparatus is described that includes a first semiconductor chip having a first pixel array. The first pixel array has visible light sensitive pixels.
Google Inc.

Image sensor device

Image sensor devices of related art have a problem that an auto-focus accuracy deteriorates due to crosstalk of electrons between a plurality of photodiodes formed below one microlens. According to one embodiment, at least some of a plurality of pixels in an image sensor device include: first and second photoelectric conversion elements (pd_l, pd_r) that are formed on a semiconductor substrate below one microlens (45); and a potential barrier (34) that inhibits transfer of electric charges between at least a part of a lower region of the first photoelectric conversion element (pd_l) and at least a part of a lower region of the second photoelectric conversion element (pd_r) in a depth direction of the semiconductor substrate..
Renesas Electronics Corporation

Method of manufacturing semiconductor unit and the semiconductor unit

In a solid-state imaging device including a plurality of pixels each pixel including a plurality of photodiodes, it is prevented that an incidence angle of incident light on the solid-state imaging device becomes large in a pixel in an end of the solid-state imaging device, causing a difference in output between the two photodiodes in the pixel, and thus autofocus detection accuracy is deteriorated. Photodiodes extending in a longitudinal direction of a pixel allay section are provided in each pixel.
Renesas Electronics Corporation

Microlens for a phase detection auto focus (phaf) pixel of a composite grid structure

An image sensor for high angular response discrimination is provided. A plurality of pixels comprises a phase detection autofocus (pdaf) pixel and an image capture pixel.
Taiwan Semiconductor Manufactuing Co., Ltd.

Cmos image sensor structure with crosstalk improvement

A semiconductor device includes a substrate, a device layer, an anti-reflective coating layer, reflective structures, a composite grid structure, a passivation layer and color filters. The device layer is disposed on the substrate, in which trenches are formed in the device layer and the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Solid state imaging element and manufacturing method thereof, and electronic apparatus

A solid state imaging element according to the invention includes: a semiconductor layer of a first conductivity type; a gate insulation film on the semiconductor layer; a gate electrode on the gate insulation film; a first impurity region of a second conductivity type in the semiconductor layer and in a region outside the gate electrode on a first end portion side; a second impurity region of the second conductivity type in the semiconductor layer and in a region outside the gate electrode on a second end portion side that is opposite to the first end portion of the gate electrode; and a third impurity region of the first conductivity type over the second impurity region in the semiconductor layer at a position separate from the second end portion of the gate electrode as viewed in plan view, and is in contact with the second impurity region.. .
Seiko Epson Corporation

Manufacturing semiconductor device and semiconductor device

In the divided exposure performed when the solid state image sensor is manufactured, a dividing line that divides an exposure region is defined to be located between a first photodiode and a second photodiode aligned in a first direction in an active region in a pixel and is defined to be along a second direction perpendicular to the first direction.. .

Image sensor and a method to manufacture thereof

The disclosed embodiments include an image sensor and a method to manufacture thereof. In one embodiment, the method includes forming a plurality of semiconductor slices having a uniform width, at least two of the semiconductor slices having different lengths, and each of the semiconductor slices having a slice edge defining a side of the semiconductor slice.
Teledyne Dalsa, Inc.

Semiconductor device and manufacturing the same

A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer.
Semiconductor Energy Laboratory Co., Ltd.

Display device and the manufacturing the same

Provided are a reliable high performance thin film transistor and a reliable high performance display device. The display device has: a gate electrode which is formed on a substrate; a gate insulating film which is formed to cover the substrate and the gate electrode; an oxide semiconductor layer which is formed on the gate electrode through the gate insulating film; a channel protective layer which is in contact with the oxide semiconductor layer and formed on the oxide semiconductor layer; and source/drain electrodes which are electrically connected to the oxide semiconductor layer and formed to cover the oxide semiconductor layer.
Japan Display Inc.

Semiconductor device, electro-optical device, manufacturing semiconductor device, manufacturing electro-optical device, and electronic apparatus

A first insulation layer includes a concave portion. A semiconductor layer includes a source area and a drain area, and a channel area disposed at the concave portion of the first insulation layer.
Seiko Epson Corporation

Dual-material mandrel for epitaxial crystal growth on silicon

In one example, a method for fabricating a semiconductor device includes etching a layer of silicon to form a plurality of fins and growing layers of a semiconductor material directly on sidewalls of the plurality of fins, wherein the semiconductor material and surfaces of the sidewalls have different crystalline properties.. .
International Business Machines Corporation

Display panel

A display panel is provided. The display panel includes a substrate including a non-display region containing a thin film transistor, which includes a semiconductor layer; a first insulating layer; a first metal layer; a second insulating layer; a first and second via hole series disposed adjacent to the respective opposite sides of the first metal layer.
Innolux Corporation

Thin film transistor array substrate and manufacturing method thereof

A substrate including gate wirings including gate line and a gate electrode disposed on the substrate, a storage line disposed on the same layer as the gate wirings, a gate insulating layer disposed on the gate wirings and the storage line, an oxide semiconductor layer pattern disposed on the gate insulating layer, data wirings including a data line crossing the gate line, a source electrode disposed on one side of the oxide semiconductor layer pattern, and a drain electrode disposed on another side of the oxide semiconductor layer, and an etch stopper including a first etch stopper portion disposed between the storage line and the data line and partially overlapping both the data line and the storage line.. .
Samsung Display Co., Ltd.

Semiconductor memory device and manufacturing same

According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers.
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing method thereof

A semiconductor memory device according to an embodiment includes a memory cell array that includes memory cells and a plurality of first conducting layers. The memory cells are arrayed in a three-dimensional manner.
Kabushiki Kaisha Toshiba

Method for manufacturing semiconductor device

Embodiments of the inventive concepts provide a method for manufacturing a three-dimensional semiconductor memory device. The method includes forming a stack structure including insulating layers and sacrificial layers which are alternately and repeatedly stacked on a substrate.
Samsung Electronics Co., Ltd.

Semiconductor device

A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations..

Method for manufacturing semiconductor device

Embodiments of the inventive concept provide a method for a semiconductor device. The method includes forming a stack structure by alternately and repeatedly stacking insulating layers and sacrificial layers on a substrate, sequentially forming a first lower layer and a first photoresist pattern on the stack structure, etching the first lower layer using the first photoresist pattern as an etch mask to form a first lower pattern.

Semiconductor memory device and manufacturing method thereof

A semiconductor memory device according to an embodiment includes a laminated body. The laminated body is disposed above a semiconductor substrate.
Kabushiki Kaisha Toshiba

Semiconductor device

According to one embodiment, a semiconductor device includes a substrate; a first structure; a second structure; a step; an insulating layer; a first pillar; a second pillar; a first contact portion; and a second contact. The first structure includes a first electrode layer and a first insulator.
Kabushiki Kaisha Toshiba

Non-volatile memory device and manufacturing same

A non-volatile memory device comprises a first electrode, a second electrode stacked on the first electrode, a semiconductor layer extending in a first direction through the first electrode and the second electrode, charge storage parts respectively provided between the first electrode and the semiconductor layer and between the second electrode and the semiconductor layer, and a barrier body arranged with the first electrode and the second electrode in a second direction orthogonal to the first direction and extending in the first direction. A distance between the second electrode and the barrier body is wider in the second direction than a distance between the first electrode and the barrier body..
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing the same

According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film and a conductive member. The stacked body includes a plurality of electrode layers arranged in a first direction.
Kabushiki Kaisha Toshiba

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; a charge storage layer; a first conductor; a second conductor; and a third conductor. The stacked body includes a plurality of electrode layers stacked with an insulator interposed.
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing the same

According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film and a first contact portion. The stacked body includes a first electrode film, a second electrode film and an inter-electrode insulating film.
Kabushiki Kaisha Toshiba

Semiconductor memory device

According to one embodiment, a semiconductor memory device comprises a first semiconductor region of n-type conductivity, a second semiconductor region of p-type conductivity, a third semiconductor region of n-type conductivity, a stacked body, a semiconductor pillar, a first insulating layer, a charge storage layer, a second insulating layer, a first conductive portion, and a second conductive portion. The semiconductor pillar extends in the stacked body in a direction in which the conductive layers and the insulating layers are stacked.
Kabushiki Kaisha Toshiba

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and at least one columnar member. The stacked body is provided on the substrate.
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing the same

According to one embodiment, a semiconductor device includes a substrate, a first electrode layer, a second electrode layer, a third electrode layer, a fourth electrode layer, a first gate electrode layer, a second gate electrode layer, a gate insulating film, a first interlayer insulating film, a second interlayer insulating film. The first electrode layer is separated from the substrate in a first direction.
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing same

According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of insulating layers and including a first insulating layer and a plurality of conductive layers including a first conductive layer; a first semiconductor film extending in a stacking direction of the stacked body; a second semiconductor film, the second semiconductor film having a maximum thickness thicker than a maximum thickness of the first semiconductor film in a first direction crossing the stacking direction; and a first insulating film. The second semiconductor film has an upper face, and a height of the upper face is lower than a height of the first conductive layer.
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing the same

According to one embodiment, a semiconductor memory device includes a structural body, first to fourth pillars, a first interconnection, a second interconnection, a third interconnection, and a fourth interconnection. The first to fourth pillars provides within the structural body extending along the first direction.
Kabushiki Kaisha Toshiba

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a plurality of memory cells arranged on a substrate. The semiconductor memory device includes an interconnect layer including a first interconnect and a second interconnect, the first interconnect extending in a first direction, the second interconnect extending in a second direction, the first direction being tilted with respect to an arrangement direction of the memory cells, the second direction being different from the first direction and tilted with respect to the arrangement direction of the memory cells..
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing the same

A semiconductor memory device according to an embodiment includes a first semiconductor layer containing an acceptor and a memory cell array including an interlayer insulating layer and a conductive layer arranged in a first direction above the first semiconductor layer and a memory columnar body extending in the first direction and having a lower end positioned lower than a position of a top surface of the first semiconductor layer, the memory columnar body containing a second semiconductor layer in a columnar shape having a side face opposite to a side face of the conductive layer, wherein a first portion of the first semiconductor layer in contact with the side face of the memory columnar body contains a donor in a higher concentration than a second portion different from the first portion of the first semiconductor substrate.. .
Kabushiki Kaisha Toshiba

Semiconductor memory device and production method thereof

A semiconductor memory device according to an embodiment includes a memory cell array which has: a first conductive layer which is arranged in a first direction on a first semiconductor layer; a second conductive layer which is arranged in the first direction above the first conductive layer; a columnar second semiconductor layer which extends in the first direction; and a contact unit which electrically connects the first semiconductor layer and the second conductive layer. The contact unit has a first film which contains silicide as a first metal, and is in contact with the first semiconductor layer; and a second film which contains the first metal, is in contact with the first film, and is in contact with the first semiconductor layer with the first film interposed therebetween..
Kabushiki Kaisha Toshiba

Semiconductor memory device

A semiconductor memory device according to an embodiment includes: an insulating layer; a conductive layer stacked above the insulating layer in a first direction, the conductive layer having a second direction as a longitudinal direction and a third direction as a short direction; and a channel semiconductor layer extending in the first direction, and the conductive layer including a recessed portion narrowed in the third direction.. .
Kabushiki Kaisha Toshiba

Semiconductor integrated circuit device and a manufacturing the same

A semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.. .
Renesas Electronics Corporation

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell, the memory cell comprising: a semiconductor layer; a control gate electrode; a charge accumulation layer disposed between the semiconductor layer and the control gate electrode; a first insulating layer disposed between the semiconductor layer and the charge accumulation layer; and a second insulating layer disposed between the charge accumulation layer and the control gate electrode, the charge accumulation layer including an insulator that includes silicon and nitrogen, and the insulator further including: a first element or a second element, the second element being different from the first element; and a third element different from the first element and the second element.. .
Kabushiki Kaisha Toshiba

Semiconductor memory device

A semiconductor memory device includes a first word line that is provided above a semiconductor substrate, a second word line that is provided above the first word line, a plurality of semiconductor pillars that are provided on the semiconductor substrate, and pass through the first and second word lines, and first and second plugs that are provided so that the plurality of semiconductor pillars are interposed therebetween. The semiconductor substrate includes an insulating region that is provided deeper than a bottom of the first plug relative to a surface of the semiconductor substrate, between the first plug and one of the semiconductor pillars..
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing the same

An embodiment includes: a semiconductor substrate, a memory cell array region including a plurality of conductive layers connected to memory cells arranged in a stacking direction on the semiconductor substrate; a peripheral region including a transistor on the substrate ; a plurality of first layers and second layers stacked alternately in the stacking direction, above the transistor; and a plurality of first contacts penetrating the plurality of first and second layers and connected to the transistor. The plurality of first layers and second layers are stacked alternately in the stacking direction, above the transistor disposed in the peripheral region.
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing the same

According to one embodiment, the first separation film separates the control electrode, the first insulating layer, the charge storage layer, the intermediate insulating layer, the floating electrode layer, and the second insulating layer in a first direction. The second separation film separates a first stacked unit in a second direction.
Kabushiki Kaisha Toshiba

Nonvolatile semiconductor memory device and manufacturing the same

A semiconductor memory device according to an embodiment includes a plurality of channel layers, a gate-insulating film disposed on the channel layer, a floating gate electrode disposed on the gate-insulating film, a block insulating film disposed over the floating gate electrode, the block insulating film including at least a first insulating film and a second insulating film, the second insulating film including lanthanum and aluminum, and a control gate electrode disposed on the block insulating film. The second insulating film includes an upwardly convex curved portion in a region between the channel layers..
Kabushiki Kaisha Toshiba

Semiconductor device and forming the same

Provided is a semiconductor device including a memory gate structure and a select gate structure. The memory gate structure is closely adjacent to the select gate structure.
United Microelectronics Corp.

Semiconductor memory device and manufacturing the same

According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction.
Kabushiki Kaisha Toshiba

Semiconductor device, non-volatile semiconductor memory device and manufacturing semiconductor device

According to one embodiment, it includes a stacked body including n-number of layers (n is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing m-number of layers (m is an integer of 1 or more and (n−2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.. .
Kabushiki Kaisha Toshiba

Method for manufacturing semiconductor memory device, semiconductor wafer and semiconductor memory device

A method for manufacturing includes forming a first insulating film on a substrate, forming first to third portions in the first insulating film, forming a second insulating film on the first insulating film, removing a part of the second portion, a portion including a region directly above the part of the second portion of the second insulating film, and at least a part of a portion including a region directly above the other part of the second portion of the second insulating film, and forming a first stacked body, forming a stacked film by alternately stacking third and fourth insulating films, and forming a stacked structure by processing a remaining part of the stacked film into a stepped pattern forming steps at each of the third insulating films. A depression is formed on the region directly above the third portion in an upper surface of the second insulating film..
Kabushiki Kaisha Toshiba

Semiconductor device

According to an embodiment, a semiconductor device, includes: a first region of an n-type conductive layer; a second region of a p-type conductive layer on the first region; a first tfet having an n-type drain region formed in the second region; a second tfet provided adjacent to the first tfet and of a tfet having an n-type drain region formed in the second region; and an insulating film formed between the drain region of the first tfet and the drain region of the second tfet, and reaching the first region.. .
Kabushiki Kaisha Toshiba

Semiconductor arrangement with capacitor

A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device.
Taiwan Semiconductor Manufacturing Company Limited

Semiconductor device and manufacturing the same

A method of manufacturing a semiconductor device includes: preparing a wafer in which a first cell area and a second cell area are defined; forming a bottom electrode structure in the first cell area and a dummy structure located in the second cell area; and sequentially forming a dielectric layer and a top electrode on the bottom electrode structure and the dummy structure, wherein the bottom electrode structure includes a plurality of bottom electrodes extending in a first direction in the first cell area and first and second supporters to support the plurality of bottom electrodes, wherein the dummy structure includes a first mold film, a first supporter film, a second mold film, and a second supporter film that are sequentially formed to cover the second cell area, and the second supporter and the second supporter film are at a same level relative to the wafer.. .
Samsung Electronics Co., Ltd.

Semiconductor device having supporters and manufacturing the same

A semiconductor device includes storage electrodes on a substrate and one or more supporters configured to couple one or more portions of the storage electrodes. The semiconductor device may include multiple non-intersecting supporters extending in parallel to a surface of the substrate.
Samsung Electronics Co., Ltd.

Semiconductor device and driving method thereof

A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node.
Semiconductor Energy Laboratory Co., Ltd.

Spacer chamfering gate stack scheme

A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width..
Globalfoundries Inc.

Semiconductor device having first and second gate electrodes and manufacturing the same

Provided is a semiconductor device having first and second gate electrodes. The semiconductor device includes a substrate, an active region extending in a first direction on the substrate, a first gate electrode crossing the active region and extending in a second direction, and a second gate electrode extending in the second direction on the first gate electrode, wherein the first gate electrode has a first width in the first direction, and wherein the second gate electrode has a second width in the first direction, the second width being less than the first width..

Multi-gate fets and methods for forming the same

A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor integrated circuit

A semiconductor integrated circuit includes a substrate, a multi-gate transistor device positioned on the substrate, and an ldmos device positioned on the substrate. The substrate includes a plurality of first isolation structures and a plurality of second isolation structures.
United Microelectronics Corp.

Integrated circuit composed of tunnel field-effect transistors and manufacturing same

The present invention provides an integrated circuit formed of tunneling field-effect transistors that includes a first tunneling field-effect transistor in which one of a first p-type region and a first n-type region operates as a source region and the other one operates as a drain region; and a second tunneling field-effect transistor in which one of a second p-type region and a second n-type region operates as a source region and the other one operates as a drain region, the first and second tunneling field-effect transistors being formed in one active region to have the same polarity, the first p-type region and the second n-type region being formed adjacently, the adjacent first p-type region and second n-type region being electrically connected through metal semiconductor alloy film.. .
National Institute Of Advanced Industrial Science And Technology

Semiconductor structure and manufacturing the same

A semiconductor structure includes a first high-voltage mos device region having a first light doping region in a substrate. The conductive type of the substrate is similar to that of the first light doping region.
Vanguard International Semiconductor Corporation

Semiconductor device

According to one embodiment, in a semiconductor device, the first semiconductor region is provided between the first and the second electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode.
Kabushiki Kaisha Toshiba

Device and device manufacturing method

A device includes a vertical semiconductor switch including (i) a gate terminal and a first terminal provided on a substrate and (ii) a second terminal provided on the substrate, where the vertical semiconductor switch is configured to electrically connect or disconnect the first terminal and the second terminal, a first insulative film provided on the substrate, a second insulative film provided on the substrate, where the second insulative film is in contact with the first insulative film and thinner than the first insulative film, and a zener diode formed on the first insulative film and the second insulative film, where the zener diode includes a first portion that is formed on the first insulative film and connected to the first surface of the substrate and a second portion that is formed on the second insulative film and connected to the gate terminal.. .
Fuji Electric Co., Ltd.

Silicon carbide semiconductor device

A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer.
Panasonic Intellectual Property Management Co., Ltd.

Solid-state lighting structure with integrated short-circuit protection

A solid-state light source (ssls) with an integrated short-circuit protection approach is described. A device can include a ssls having an n-type semiconductor layer, a p-type semiconductor layer and a light generating structure formed there between.
Sensor Electronic Technology, Inc.

Semiconductor device

A semiconductor device for driving a load includes: a protection circuit configured to be connected to the load, the protection circuit including a protection diode, a diode-connected unipolar protection element, and a diode-connected bipolar protection element, all of which are connected in parallel so that when connected to the load, the protection diode, the diode-connected unipolar protection element, and the diode-connected bipolar protection element are connected in parallel to the load; and a switching circuit that is connected in series to the protection circuit and that performs a switching operation so as to drive the load. The protection diode, the diode-connected unipolar protection element, and the diode-connected bipolar protection element are connected in such a polarity that each is reverse-biased when the switching circuit is turned on, and consume a discharge current resulting from a counter-electromotive force from the load when the switching circuit is turned off..
Fuji Electric Co., Ltd.

Electrostatic discharge (esd) robust transistors and related methods

An electrostatic discharge robust semiconductor transistor (transistor) includes a semiconductor substrate of a first conductivity type, a substrate contact region of the first conductivity type coupled with the semiconductor substrate, a source region of a second conductivity type, a channel region of the second conductivity type, a gate region of the first conductivity type, a drain region having a first drain region of the first conductivity type and a second drain region of the second conductivity type, and an electrical conductor coupled over the second drain region and a portion of the first drain region. A portion of the first drain region not covered by the electrical conductor forms a resistive electrical ballast region configured to protect the transistor from electrostatic discharge (esd) induced voltage pulses.
Semiconductor Components Industries, Llc

Fast scr structure for esd protection

An ultra-low capacitance esd protection device with an ultra-fast response time and a low turn-on voltage, and a high holding current. The device may include: a heavily-doped p-type substrate; a lightly-doped n-type epitaxial layer with a heavily-doped n-type buried layer; and a semiconductor-controlled rectifier (scr) structure within the epitaxial layer.
Semiconductor Components Industries, Llc

Semiconductor device and manufacturing semiconductor device

A diffusion diode including a p+ diffusion region, a p-type diffusion region, and an n+ diffusion region is formed in the front surface of a semiconductor substrate. A polysilicon diode including a p+ layer and an n+ layer is formed on top of a local insulating film formed on the front surface of the semiconductor substrate and faces the diffusion diode in the depth direction.
Fuji Electric Co., Ltd.

Lighting device including a thermally conductive body and a semiconductor light emitting device

A lighting device including a body (10). The body (10) includes a mounting area (11) with a plurality of conductive pads (50, 52) and an elongate member (16) extending from the mounting area (11).
Koninklijke Philips N.v.

Making electrical components in handle wafers of integrated circuit packages

A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region.
Invensas Corporation

Method for manufacturing semiconductor package

A method for manufacturing a semiconductor package including providing a first semiconductor package including a first package substrate and a first solder ball, the first package substrate having a first surface and a second surface opposite to the first surface, the first solder ball on the first surface, providing a second semiconductor package including a second package substrate and a second solder ball, the second package substrate having a third surface and a fourth surface opposite to the third surface, the second solder ball on the third surface, forming a depression in the first solder ball, applying flux to the first solder ball to fill the depression, aligning the first semiconductor package and the second semiconductor package with each other such that the second solder ball is inserted into the depression, and performing a reflow process to combine the first solder ball with the second solder ball may be provided.. .

Fan-out package structure having embedded package substrate

A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor package that includes a first semiconductor die having a first surface and a second surface opposite thereto.
Mediatek Inc.

System-in-packages containing preassembled surface mount device modules and methods for the production thereof

Methods for producing system-in-packages (sips) containing embedded surface mount device (smd) modules are provided, as sips containing smd modules. In one embodiment, the fabrication method includes positioning a semiconductor die and first preassembled smd module, which contains a plurality of smds soldered to an interposer substrate, in predetermined spatial relationship.
Freescale Semiconductor Inc.

Optoelectronic component

An optoelectronic component for mixing electromagnetic radiation having different wavelengths, for example, for the far field is disclosed. In an embodiment the optoelectronic component includes a carrier, at least one first semiconductor chip arranged on the carrier and having a first radiation exit surface for emitting electromagnetic radiation in a first spectral range and at least one second semiconductor chip arranged on the carrier and having a second radiation exit surface for emitting electromagnetic radiation in a second spectral range, wherein a diffusing layer is arranged on the first and second radiation exit surfaces of the semiconductor chips that face away from the carrier and wherein a reflecting layer is arranged between the first semiconductor chip and the second semiconductor chip, the first and second radiation exit surfaces being free from the reflecting layer at least in regions..
Osram Opto Semiconductors Gmbh

Semiconductor component, lighting device and producing a semiconductor component

The invention relates to a semiconductor component (1) comprising: a plurality of semiconductor chips (2), each having a semiconductor layer sequence (200) with an active region (20) for generating radiation; a radiation output side (10) that runs parallel to the active regions (20); a mounting side surface (11) which is provided for securing the semiconductor component, and which runs in a transverse or perpendicular direction to the radiation output side; a moulded body (4) which is shaped in places on the semiconductor chips, and which at least partially forms the mounting side surface; and a contact structure (50) which is arranged on the moulded body, and which connects at least two semiconductor chips of the plurality of semiconductor chips in an electrically conductive manner. The invention also relates to a lighting device (9) and to a method for producing a semiconductor component..
Osram Opto Semiconductors Gmbh

Semiconductor device and electronic device

An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted.
Renesas Electronics Corporation

Semiconductor device

A semiconductor device includes an insulating substrate having an insulating plate and a circuit plate; a semiconductor chip having a front surface provided with a gate electrode and a source electrode, and a rear surface fixed to the circuit plate; a printed circuit board facing the insulating substrate, and including a first metal layer and a second metal layer; a first conductive post having two ends electrically and mechanically connected to the gate electrode and the first metal layer; a second conductive post having two ends electrically and mechanically connected to the source electrode and the second metal layer; and a circuit impedance reducing element electrically connected between the gate electrode and the source electrode through the first conductive post and the second conductive post.. .
Fuji Electric Co., Ltd.

Semiconductor substrates with unitary vias and via terminals, and associated systems and methods

semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative system in accordance with a particular embodiment includes a semiconductor substrate having an opening that includes a generally cylindrical portion with a generally smooth, uniform surface.
Micron Technology, Inc.

Semiconductor device and control the same

A semiconductor device includes: a first semiconductor chip including a first terminal at a first face side, a first load whose one end is connected to the first terminal, another end of the first load being to be connected to a power source potential, a second terminal at a second face side, a second load whose one end is connected to the second terminal, another end of the second load being to be connected to a ground potential, a first detection circuit that detects generation of potential difference at the first load, and a second detection circuit that detects generation of potential difference at the second load; and a second semiconductor chip including a connection terminal disposed at a face facing the first semiconductor chip; wherein the power source potential or the ground potential is to be connected through the connection terminal to the first or second terminal.. .
Fujitsu Limited

Semiconductor storage device and manufacturing method thereof

A semiconductor storage device of the present embodiments includes a substrate, a first semiconductor chip and a sealer. The substrate has wirings.
Kabushiki Kaisha Toshiba

Semiconductor device, semiconductor chip, and manufacturing semiconductor device

A semiconductor device includes a semiconductor chip including first to fourth pads, and first and second switches. The first switch includes first and second nodes coupled to the first and second pads and sends from the second node a current larger than a threshold flowing in from the first node.
Kabushiki Kaisha Toshiba

Semiconductor device including a buffer layer structure for reducing stress

A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer..
Seiko Epson Corporation

Semiconductor device

A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other..
Murata Manufacturing Co., Ltd.

Semiconductor package interconnect

A semiconductor package interconnect system may include a conductive pillar having a core, a first layer surrounding the core, and a second layer surrounding the first layer. The core may be composed of a drawn copper wire, the first layer may be composed of nickel, and the second layer may be composed of a solder.
Qualcomm Incorporated

Collars for under-bump metal structures and associated systems and methods

The present technology is directed to manufacturing collars for under-bump metal (ubm) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material.
Micron Technology, Inc.

Monolithic microwave integrated circuits

Low q associated with passive components of monolithic integrated circuits (ics) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 ohm-cm) semiconductor substrates and lower resistance inductors for the ic. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate.
Freescale Semiconductor, Inc.

Semiconductor device, inverter circuit, and drive device

A semiconductor device of an embodiment includes a first electrode, a second electrode facing the first electrode, an alternating-current electrode, a first switching element provided between the first electrode and the alternating-current electrode, and a second switching element provided between the second electrode and the alternating-current electrode. The first switching element and the second switching element are electrically connected in series between the first electrode and the second electrode, and the alternating-current electrode is electrically connected between the first switching element and the second switching element..
Kabushiki Kaisha Toshiba

Semiconductor structure

A semiconductor structure includes an insulating layer, a plurality of stepped conductive vias and a patterned circuit layer. The insulating layer includes a top surface and a bottom surface opposite to the top surface.
Ibis Innotech Inc.

Semiconductor device

A semiconductor device includes a plurality of main terminals extending from one end of a base plate toward the other end thereof, a group of semiconductor chips on a side of higher electric potential disposed on one side of the main terminal and mounted on the base plate, and a group of semiconductor chips on a side of lower electric potential disposed on the other side of the main terminal and mounted on the base plate. The one main terminal has an extending portion extending, in a direction perpendicular to the extending direction of the main terminal, toward one of both sides of the main terminal, and two adjacent semiconductor chips in one of the group of semiconductor chips on the side of higher electric potential and the group of semiconductor chips on the side of lower electric potential are axisymmetrically disposed with respect to the extending portion..
Fuji Electric Co., Ltd.

Semiconductor apparatus, stacked semiconductor apparatus, encapsulated stacked-semiconductor apparatus, and manufacturing the same

A semiconductor apparatus including a semiconductor device, an on-semiconductor-device metal pad and a metal interconnect each electrically connected to the semiconductor device, a through electrode and a solder bump each electrically connected to the metal interconnect, a first insulating layer on which the semiconductor device is placed, a second insulating layer formed on the semiconductor device, a third insulating layer formed on the second insulating layer, wherein the metal interconnect is electrically connected to the semiconductor device via the on-semiconductor-device metal pad at an upper surface of the second insulating layer, and the metal interconnect penetrates the second insulating layer from its upper surface and is electrically connected to the through electrode at an lower surface of the second insulating layer. This semiconductor apparatus can be easily placed on a circuit board and stacked, and can reduce its warpage even with dense metal interconnects..
Shin-etsu Chemical Co., Ltd.

Method for manufacturing semiconductor device and semiconductor device

According to one embodiment, in a method for manufacturing a semiconductor device, a semiconductor chip is provided on a first surface of a substrate having the first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface. A resin that seals the first surface of the semiconductor chip is formed on the semiconductor chip.
Kabushiki Kaisha Toshiba

Semiconductor package device and manufacturing the same

The present disclosure provides a semiconductor package device and a method for manufacturing the same. In embodiments of the present disclosure, a semiconductor package device includes a carrier, a first antenna, a second antenna, a package body and a first shield.
Advanced Semiconductor Engineering, Inc.

Semiconductor device

A semiconductor device includes a first identification mark that is identifiable by a photoluminescence method, and a second identification mark that is identifiable using visible light.. .
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing the same

A semiconductor device includes a first gate electrode provided in a jumper region of a substrate and extending in a first direction, first source/drain regions provided at both sides of the first gate electrode, and a connecting contact electrically connecting the first gate electrode and the first source/drain regions to each other. The connecting contact includes first sub-contacts disposed at both sides of the first gate electrode and connected to the first source/drain regions, and a second sub-contact extending in a second direction intersecting the first direction.
Samsung Electronics Co., Ltd.

Interconnection structure, fabricating method thereof, and semiconductor device using the same

A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions are present between the silicide and the contact region.
Taiwan Semiconductor Manufacturing Co., Ltd.

Interconnection structure, fabricating method thereof, and semiconductor device using the same

A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a si concentration of the silicide is varied along a height of the silicide.. .
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device and manufacturing method thereof

A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate.
United Microelectronics Corp.

Backside semiconductor die trimming

A semiconductor die including a substrate, a device layer over the substrate, and an adjustable component in the device layer is provided, where a surface of the device layer opposite the substrate is the frontside of the semiconductor die. At least a portion of the substrate is removed to expose a backside of the semiconductor die opposite the frontside.
Qorvo Us, Inc.

Semiconductor device

A semiconductor device includes: a semiconductor substrate, a first portion and a second portion of an upper layer portion of the semiconductor substrate being conductive; an insulating member electrically isolating the first portion from the second portion; a first stacked body provided in a region directly above the second portion, the first stacked body including first insulating films and electrode films stacked alternately; a semiconductor pillar provided inside the first stacked body and extending in a stacking direction; a charge storage film provided between the semiconductor pillar and the electrode films; a second stacked body provided in a region directly above the first portion, the second stacked body including second insulating films and third insulating films stacked alternately; and two first conductive pillars provided inside the second stacked body extending in the stacking direction, lower ends thereof being connected to the first portion.. .
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing method thereof

According to an embodiment, a semiconductor memory device includes a plurality of first conductive layers disposed above a substrate in a laminating direction. A stepped wiring area includes a second conductive layer electrically connected to the first conductive layer.
Kabushiki Kaisha Toshiba

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, and a first interconnect. When an imaginary first straight line extending in a second direction crossing a first direction is set, the plurality of columnar portions are divided into first sets of n (n is an integer number not less than 3 and not more than 32) columnar portions with center axes alternately disposed on both sides of the first straight line along the second direction and second sets of n columnar portions having position relationships of inversion of the first sets with respect to the first straight line, and the first sets and the second sets are alternately arranged..
Kabushiki Kaisha Toshiba

Semiconductor substrate, semiconductor module and manufacturing the same

A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer..
Advanced Semiconductor Engineering, Inc.

Fully molded miniaturized semiconductor module

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion.
Deca Technologies Inc.

Semiconductor device

According to one embodiment, there is provided a semiconductor device including a package. The package includes a first terminal, a second terminal, a semiconductor chip, and a sealing member.
Kabushiki Kaisha Toshiba

Semiconductor device, embedded capacitor unit, semiconductor package, and manufacturing embedded capacitor unit

Jitter that becomes a problem in a semiconductor part which performs high-speed signal processing is reduced. A semiconductor device includes a heat-resistant metal plate, a capacitor part having a lower electrode, a sintered dielectric part, and an upper electrode that are formed on one or more surfaces of the heat-resistant metal plate, a semiconductor chip fixed on the capacitor part, a wire for electrically connecting a lead frame to the semiconductor chip and the upper electrode, and a mold part in which at least the capacitor part and the semiconductor chip are buried.
Panasonic Intellectual Property Management Co., Ltd.

Semiconductor device having terminals directly attachable to circuit board

Disclosed embodiments relate to a semiconductor device. A semiconductor device is fabricated by attachment of a first chip to a first surface of a pad of a leadframe.
Texas Instruments Incorporated

Cascode semiconductor package and related methods

A semiconductor package includes an electrically conductive base (base) having a source connector. A drain connector and a gate connector are electrically coupled with the base.
Semiconductor Components Industries, Llc

Power overlay structure and making same

A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim.
General Electric Company

Semiconductor device

Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction, each of which has a plurality of transistors.
Renesas Electronics Corporation

Lead frame, manufacturing lead frame, semiconductor device, and manufacturing semiconductor device

A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside.
Dai Nippon Printing Co., Ltd.

Semiconductor device

A semiconductor device includes a radiation base having a plurality of dents formed and overlapped with each other in the rear surface thereof. The dents in the rear surface of the radiation base are formed by performing a shot peening process on the rear surface of the radiation base.
Fuji Electric Co., Ltd.

Semiconductor packages and methods of packaging semiconductor devices

semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces.
Utac Headquarters Pte. Ltd.

Semiconductor device and manufacturing the same

An object is to realize a hermetically sealed package which ensures long-term airtightness inside the package by sealing using a substrate, or a sealing structure for reducing destruction caused by pressure from the outside. A frame of a semiconductor material is provided over a first substrate, which is bonded to a second substrate having a semiconductor element so that the semiconductor element is located inside the frame between the first substrate and the second substrate.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device

For a purpose of raising the breakdown voltage of a semiconductor device, the creepage distance and clearance between an electrode terminal and another metallic portion are preferably increased. A semiconductor device is provided, the semiconductor device including: a semiconductor element; a case portion that houses the semiconductor element; and an external terminal provided to a front surface of the case portion, wherein the front surface of the case portion has, formed thereon: a wall portion that protrudes from the front surface; and a hollow portion that is provided to a region surrounded by the wall portion and is depressed relative to the front surface, and the external terminal is arranged on a floor surface of the hollow portion..
Fuji Electric Co., Ltd.

Semiconductor device

Provided is a semiconductor device including a semiconductor substrate; a dummy trench that is formed on a front surface side of the semiconductor substrate; an emitter electrode that is formed above a front surface of the semiconductor substrate and includes a recessed portion that is a recess in an outer periphery thereof, as seen in a planar view; a dummy pad that is electrically connected to the dummy trench and has at least a portion thereof formed within the recessed portion, as seen in the planar view; and a dummy wire that electrically connects the emitter electrode and the dummy pad.. .
Fuji Electric Co., Ltd.

System to detect wafer arcing in semiconductor manufacturing equipment

Methods and systems for accurate arc detection in semiconductor manufacturing tools are disclosed. Such methods and systems provide real-time arc detection and near real-time notification for corrective actions during a semiconductor manufacturing process.
Applied Materials, Inc.



Semiconductor topics:
  • Semiconductor
  • Semiconductor Substrate
  • Semiconductor Device
  • Semiconductor Material
  • Electric Conversion
  • Conductive Layer
  • Molybdenum
  • Camera Module
  • Semiconductor Devices
  • Semiconductors
  • Integrated Circuit
  • Surfactant
  • Photoelectric Conversion
  • Electronic Device
  • Transparent Conductive Oxide


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