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Semiconductor patents



      
           
This page is updated frequently with new Semiconductor-related patent applications. Subscribe to the Semiconductor RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor RSS RSS


Biologically based chamber matching

Biologically based chamber matching

Photoinduced carrier lifetime measurement device and photoinduced carrier lifetime measurement method

Photoinduced carrier lifetime measurement device and photoinduced carrier lifetime measurement method

Photoinduced carrier lifetime measurement device and photoinduced carrier lifetime measurement method

Apparatus and method for detecting position drift in a machine operation using a robot arm

Date/App# patent app List of recent Semiconductor-related patents
10/09/14
20140304567
 Method of controlling a semiconductor storage device patent thumbnailMethod of controlling a semiconductor storage device
A method of controlling a nonvolatile semiconductor memory includes checking a first group at a first interval period, the first group including a plurality of blocks, and when a first block in the first group satisfies a first condition, assigning the first block to a second group. The method includes checking, at a second interval period, an error count of data stored in the second group, and when a second block in the second group satisfies a second condition, moving data stored in the second block to an erased block in which stored data is erased among the plurality of blocks..
10/09/14
20140304196
 Biologically based chamber matching patent thumbnailBiologically based chamber matching
The subject disclosure relates to automatically learning relationships among a plurality of manufacturing tool parameters as applied to arbitrary semiconductor manufacturing tools and a graphical user interface that is supported, at least in part, by an autonomous learning system. The graphical user interface can create one or more matrixes based on received data and can further generate additional matrices by transforming the one or more matrixes.
10/09/14
20140303919
 Photoinduced carrier lifetime measurement device and photoinduced carrier lifetime measurement method patent thumbnailPhotoinduced carrier lifetime measurement device and photoinduced carrier lifetime measurement method
A photoinduced carrier lifetime measurement device includes light sources that respectively apply light that differs in wavelength and generates photoinduced carriers to a semiconductor substrate, a microwave generation section that generates microwaves that are applied to the semiconductor substrate, a detection section that detects the intensity of the microwaves that have passed through the semiconductor substrate, and a calculation section that calculates the effective carrier lifetime corresponding to the wavelength of each light based on the intensity of the microwaves detected when applying each light, and calculates the bulk carrier lifetime and a surface recombination velocity of the semiconductor substrate based on the effective carrier lifetime calculated corresponding to the wavelength of each light.. .
10/09/14
20140303776
 Apparatus and method for detecting position drift in a machine operation using a robot arm patent thumbnailApparatus and method for detecting position drift in a machine operation using a robot arm
In an example embodiment, apparatus for detecting position drift in a machine operation using a robot arm, the robot arm being for operation on a semiconductor substrate, the robot arm and the semiconductor substrate being configured for relative movement therebetween, the apparatus includes an input for receiving an input signal from a sensor mounted on the robot arm; a detector for detecting, from the input signal, a detection of there being a predefined distance between the robot arm and the semiconductor substrate; wherein the apparatus is configured to determine, from the detection, whether there has been position drift.. .
10/09/14
20140303765
 Semiconductor processing dispatch control patent thumbnailSemiconductor processing dispatch control
An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage.
10/09/14
20140303335
 Diketopyrrolopyrrole polymers for use in organic semiconductor devices patent thumbnailDiketopyrrolopyrrole polymers for use in organic semiconductor devices
The present invention relates to polymers comprising one or more (repeating) unit(s) of the formula (i) which are characterized in that ar1 and ar1′ are independently of each other are an annulated (aromatic) heterocyclic ring system, containing at least one thiophene ring, which may be optionally substituted by one, or more groups, and their use as organic semiconductor in organic devices, especially in organic photovoltaics (solar cells) and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties.
10/09/14
20140303043
 Reversible reaction sensors and assemblies patent thumbnailReversible reaction sensors and assemblies
A reversible reaction sensor provides for detecting medical, biologic or explosive airborne compounds. The sensor may be formed in semiconductor material and is activated by radiation from sources to provide sensing of particular airborne compounds optically detectable by detectors, and reversed by other radiation from a source (or removal of activating radiation) to take away such airborne compounds from the sensor.
10/09/14
20140302754
 Polishing apparatus patent thumbnailPolishing apparatus
A polishing apparatus has a polishing pad, a top ring for holding a semiconductor wafer, and a vertical movement mechanism operable to move the top ring in a vertical direction. The polishing apparatus also has a distance measuring sensor operable to detect a position of the top ring when a lower surface of the top ring is brought into contact with the polishing pad, and a controller operable to calculate an optimal position of the top ring to polish the semiconductor wafer based on the position detected by the distance measuring sensor.
10/09/14
20140302688
 Flowable silicon-carbon-oxygen layers for semiconductor processing patent thumbnailFlowable silicon-carbon-oxygen layers for semiconductor processing
Methods are described for forming a dielectric layer on a patterned substrate. The methods may include combining a silicon-and-carbon-containing precursor and a radical oxygen precursor in a plasma free substrate processing region within a chemical vapor deposition chamber.
10/09/14
20140302687
 Substrate processing device, method for manufacturing semiconductor device, and vaporizer patent thumbnailSubstrate processing device, method for manufacturing semiconductor device, and vaporizer
A substrate processing apparatus includes: a reaction chamber configured to process a substrate; a vaporizer including a vaporization container into which a processing liquid including hydrogen peroxide or hydrogen peroxide and water is supplied, a processing liquid supply unit configured to supply the processing liquid to the vaporization container, and a heating unit configured to heat the vaporization container; a gas supply unit configured to supply a processing gas generated by the vaporizer into the reaction chamber; an exhaust unit configured to exhaust an atmosphere in the reaction chamber; and a control unit configured to control the heating unit and the processing liquid supply unit such that the processing liquid supply unit supplies the processing liquid to the vaporization container while the heating unit heats the vaporization container.. .
10/09/14
20140302681
Internal plasma grid for semiconductor fabrication
The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers.
10/09/14
20140302680
Internal plasma grid for semiconductor fabrication
The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers.
10/09/14
20140302679
Phase shift mask, method of forming asymmetric pattern, method of manufacturing diffraction grating, and method of manufacturing semiconductor device
A technique of forming an asymmetric pattern by using a phase shift mask, and further, techniques of manufacturing a diffraction grating and a semiconductor device, capable of improving accuracy of a product and capable of shortening manufacturing time. In a method of manufacturing a diffraction grating by using a phase shift mask (in which a light shield part and a light transmission part are periodically arranged), light emitted from an illumination light source is transmitted through the phase shift mask, and a photoresist on a surface of a si wafer is exposed by providing interference between zero diffraction order light and positive first diffraction order light which are generated by the transmission through this phase shift mask onto the surface of the si wafer, and a diffraction grating which has a blazed cross-sectional shape is formed on the si wafer..
10/09/14
20140302678
Internal plasma grid applications for semiconductor fabrication
The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers.
10/09/14
20140302677
Method for manufacturing semiconductor structures
A method for manufacturing semiconductor structures includes providing a substrate having a plurality of mandrel patterns and a plurality of dummy patterns, simultaneously forming a plurality of first spacers on sidewalls of the mandrel patterns and a plurality of second spacers on sidewalls of the dummy patterns, and removing the second spacers and the mandrel patterns to form a plurality of spacer patterns on the substrate.. .
10/09/14
20140302674
Method for strain-relieved through substrate vias
A semiconductor die including strain relief for through substrate vias (tsvs). A method for strain relief of tsvs includes defining a through substrate via cavity in a substrate.
10/09/14
20140302670
Method for manufacturing semiconductor device
The number of masks and photolithography processes used in a manufacturing process of a semiconductor device are reduced. A first conductive film is formed over a substrate; a first insulating film is formed over the first conductive film; a semiconductor film is formed over the first insulating film; a semiconductor film including a channel region is formed by etching part of the semiconductor film; a second insulating film is formed over the semiconductor film; a mask is formed over the second insulating film; a first portion of the second insulating film that overlaps the semiconductor film and second portions of the first insulating film and the second insulating film that do not overlap the semiconductor film are removed with the use of the mask; the mask is removed; and a second conductive film electrically connected to the semiconductor film is formed over at least part of the second insulating film..
10/09/14
20140302669
Pillar structure having a non-planar surface for semiconductor devices
A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar.
10/09/14
20140302668
Semiconductor device and manufacturing method thereof
An improvement is achieved in the performance of semiconductor device including a nonvolatile memory. In a split-gate nonvolatile memory, between a memory gate electrode and a p-type well and between a control gate electrode and the memory gate electrode, an insulating film is formed.
10/09/14
20140302667
Method of manufacturing a semiconductor device including an edge area
A method of manufacturing a semiconductor device includes providing a doped layer containing a first dopant of a first conductivity type and forming a counter-doped zone in the doped layer in an edge area surrounding an element area of the semiconductor device. The counter-doped zone contains at least the first dopant and a second dopant of a second conductivity type which is the opposite of the first conductivity type.
10/09/14
20140302665
Method for producing an optoelectronic nitride compound semiconductor component
A method of producing a nitride compound semiconductor component includes providing a growth substrate having a silicon surface, growing a buffer layer containing an aluminium-containing nitride compound semiconductor onto the silicon surface, growing a stress layer structure that produces a compressive stress, and growing a functional semiconductor layer sequence onto the stress layer structure, wherein the stress layer structure includes a first gan semiconductor layer and a second gan semiconductor layer, a masking layer is embedded in the first gan semiconductor layer, an al(ga)n-intermediate layer that produces a compressive stress is disposed between the first gan semiconductor layer and the second gan semiconductor layer, and the stress layer structure does not contain further al(ga)n-intermediate layers.. .
10/09/14
20140302664
Synthesis, capping and dispersion of nanocrystals
Preparation of semiconductor nanocrystals and their dispersions in solvents and other media is described. The nanocrystals described herein have small (1-10 nm) particle size with minimal aggregation and can be synthesized with high yield.
10/09/14
20140302663
Semiconductor device with isolation layer, electronic device having the same, and method for fabricating the same
A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench..
10/09/14
20140302662
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device is disclosed, which can completely remove hard mask residues left along boundaries between a high-voltage device region and sti structures after a dry etch process, by partially reducing a thickness of each of the exposed portion of the respective sti structures adjacent to the high-voltage device region so as to sufficiently expose the residues. As a result, after a portion of an underlying pad oxide corresponding to the high-voltage device region is removed in a subsequent process, the exposed surface of the substrate is uniform with a smooth and clear border.
10/09/14
20140302661
Contact isolation scheme for thin buried oxide substrate devices
A method of forming a semiconductor-on-insulator (soi) device includes defining a shallow trench isolation (sti) structure in an soi substrate, the soi substrate including a bulk layer, a buried insulator (box) layer over the bulk layer, and an soi layer over the box layer; forming a doped region in a portion of the bulk layer corresponding to a lower location of the sti structure, the doped region extending laterally into the bulk layer beneath the box layer; selectively etching the doped region of the bulk layer with respect to undoped regions of the bulk layer such that the lower location of the sti structure undercuts the box layer; and filling the sti structure with an insulator fill material.. .
10/09/14
20140302658
Transistor with improved sigma-shaped embedded stressor and method of formation
A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers.
10/09/14
20140302657
Method for fabricating power semiconductor device
A substrate having thereon an epitaxial layer is provided. A hard mask having an opening is formed on the epitaxial layer.
10/09/14
20140302656
Method of forming ultra shallow junction
The present invention discloses a method of forming ultra shallow junction, wherein the method includes the following steps: (1) providing a grid side wall etched semiconductor structure; (2) after the implantation of the nitrogen source ion into the said semiconductor structures, implanting the boron ions into the said structure of semiconductor by lightly doped drain (ldd) process; (3) forming an ultra shallow junction on the semiconductor structure by continuous processes of the heavily doped ions implantation and the anneal. The new source of n28 was introduced into this invention.
10/09/14
20140302655
Non-volatile memory device with vertical memory cells and method for fabricating the same
A non-volatile memory device includes a plurality of gate electrodes stacked over a semiconductor substrate and stretched in a first direction along the semiconductor substrate and a plurality of junction layers having a first region protruding from the semiconductor substrate and crossing the gate electrodes and a second region formed between the gate electrodes.. .
10/09/14
20140302654
Mos device and method of manufacturing the same
A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving ron-sp and bvd characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate.
10/09/14
20140302653
Finlike structures and methods of making same
Semiconductor materials, particularly iii-v materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material.
10/09/14
20140302652
Semiconductor device and method of fabricating the same
A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor.
10/09/14
20140302651
Method for manufacturing semiconductor device with first and second gates over buried bit line
A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device.
10/09/14
20140302650
Charge storage apparatus and methods
Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric.
10/09/14
20140302649
Semiconductor field-effect transistor, memory cell and memory device
Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion..
10/09/14
20140302646
Method of manufacturing semiconductor device
A performance and reliability of a semiconductor device are improved. On a semiconductor substrate, a gate electrode for a first misfet and a dummy gate electrode for a second misfet are formed, and then, an insulating film is partially formed on the gate electrode.
10/09/14
20140302644
Method for manufacturing semiconductor device
The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the nickel-based metal layer to form a ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the ni-rich phase of metal silicide; performing a second annealing so that the ni-rich phase of metal to silicide is transformed into a nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the nickel-based metal silicide source/drain and the substrate. The method for manufacturing the semiconductor device according to the present invention performs the annealing after implanting the doping ions into the ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the sbh between the nickel-based metal silicide and the silicon channel is effectively reduced, and the driving capability of the device is improved..
10/09/14
20140302641
Stiffened semiconductor die package
A stiffened semiconductor die package has a semiconductor die including an integrated circuit. The die has an active side with die bonding pads and an opposite inactive side.
10/09/14
20140302639
Semiconductor device, display device, and electronic appliance
To reduce adverse effects on actual operation and to reduce adverse effects of noise. A structure including an electrode, a wiring electrically connected to the electrode, an oxide semiconductor layer overlapping with the electrode in a plane view, an insulating layer provided between the electrode and the oxide semiconductor layer in a cross-sectional view, and a functional circuit to which a signal is inputted from the electrode through the wiring and in which operation is controlled in accordance with the signal inputted.
10/09/14
20140302638
Semiconductor device and manufacturing method thereof
A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer.
10/09/14
20140302637
Polymers based on benzodiones
The present invention relates to polymers comprising one or more (repeating) unit(s) of the formula (i), and compounds of formula (iii), wherein y, y15, y16 and y17 are independently of each other a group of formula (a), (b) or (c) and their use as ir absorber, organic semiconductor in organic devices, especially in organic photovoltaics and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers and compounds according to the invention can have excellent solubility in organic solvents and excellent film-forming properties.
10/09/14
20140302635
N-doping of organic semiconductors by bis-metallosandwich compounds
The various inventions disclosed, described, and/or claimed herein relate to the field of methods for n-doping organic semiconductors with certain bis-metallosandwich compounds, the doped compositions produced, and the uses of the doped compositions in organic electronic devices. Metals can be manganese, rhenium, iron, ruthenium, osmium, rhodium, or iridium.
10/09/14
20140302628
Optical semiconductor device and method of manufacturing optical semiconductor device
A method of manufacturing an optical semiconductor device including: forming a mesa structure including a first conductivity type cladding layer, an active layer and a second conductivity type cladding layer in this order on a first conductivity type semiconductor substrate, an upper most surface of the mesa structure being constituted of an upper face of the second conductivity type cladding layer; growing a first burying layer burying both sides of the mesa structure at higher position than the active layer; forming an depressed face by etching both edges of the upper face of the second conductivity type cladding layer; and growing a second burying layer of the first conductivity type on the depressed face of the second conductivity type cladding layer and the first burying layer.. .
10/09/14
20140302625
Semiconductor light emitting device and method for manufacturing the same
According to one embodiment, a semiconductor light emitting device includes: a semiconductor layer including a first face, a second face, a side face, and a light emitting layer; a p-side electrode provided on the second face; an n-side electrode provided on the side face; a first p-side metal layer provided on the p-side electrode; a first n-side metal layer provided on the periphery of the n-side electrode; a first insulating layer provided on a face on the second face side in the first n-side metal layer; a second p-side metal layer connected with the first p-side metal layer on the first p-side metal layer, and provided, extending from on the first p-side metal layer to on the first insulating layer; and a second n-side metal layer provided on a face on the second face side in the first n-side metal layer in a peripheral region of the semiconductor layer.. .
10/09/14
20140302622
Semiconductor device and method for manufacturing the same
A semiconductor device includes a pixel portion having a first thin film transistor and a driver circuit having a second thin film transistor. Each of the first thin film transistor and the second thin film transistor includes a gate electrode layer, a gate insulating layer, a semiconductor layer, a source electrode layer, and a drain electrode layer.
10/09/14
20140302621
Semiconductor device and manufacturing method therefor
A semiconductor device manufacturing method is disclosed by which electron beam irradiation is accomplished at a low cost while exhibiting uniform characteristics. A wafer stack consisting of multiple stacked wafers is irradiated with an electron beam from both the front surface and reverse surface.
10/09/14
20140302620
Method for manufacturing solar cell
A method for manufacturing a solar cell capable of significantly reducing the amount of wastewater generated during a wet-etching process and improving the efficiency of the solar cell. A method comprising: texturing to form an uneven structure on one semiconductor substrate surface by etching the semiconductor substrate surface with a texturing device; forming a temporary layer at an upper portion of the semiconductor substrate surface to surround a first byproduct layer formed at a predetermined region of the semiconductor substrate surface during the texturing; and doping the semiconductor substrate surface with a predetermined dopant using a doping device to form a first semiconductor layer and a second semiconductor layer disposed above the first semiconductor layer and having a different polarity than the first semiconductor layer.
10/09/14
20140302428
Mask for fabricating semiconductor device and method of fabricating the mask
A photo-mask for fabricating a semiconductor device may include a transparent substrate including a main region, a supplementary region adjacent to the main region, a main pattern for developing circuits in a semiconductor device provided on the main region of the transparent substrate, and a supplementary pattern for optical proximity correction provided on the supplementary region of the transparent substrate. The main pattern has a sidewall perpendicular to a surface of the transparent substrate, and the supplementary pattern has a sidewall inclined to the surface of the transparent substrate and an upward tapered structure..


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Semiconductor topics: Semiconductor, Semiconductor Substrate, Semiconductor Device, Semiconductor Material, Electric Conversion, Conductive Layer, Molybdenum, Camera Module, Semiconductor Devices, Semiconductors, Integrated Circuit, Surfactant, Photoelectric Conversion, Electronic Device, Transparent Conductive Oxide

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