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Semiconductor patents



      
           
This page is updated frequently with new Semiconductor-related patent applications. Subscribe to the Semiconductor RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor RSS RSS


Dual layer hardmask for embedded epi growth

Dual layer hardmask for embedded epi growth

Methods of fabricating three-dimensional semiconductor devices

Methods of fabricating three-dimensional semiconductor devices

Methods of fabricating three-dimensional semiconductor devices

Memory device with multiple voltage generators

Date/App# patent app List of recent Semiconductor-related patents
07/02/15
20150189790
 Electric power convertor patent thumbnailnew patent Electric power convertor
An electric power converter includes a stacked semiconductor unit formed by stacking semiconductor modules and cooling tubes, and a case. The case has a rear wall portion, a front wall portion, and a pair of side wall portions.
07/02/15
20150189772
 Semiconductor package and method therefor patent thumbnailnew patent Semiconductor package and method therefor
In one embodiment, a semiconductor package may be formed having a first side and a second side that is substantially opposite to the first side. An embodiment may include forming an attachment clip extending substantially laterally between the first and second sides wherein the attachment clip is positioned near a distal end of the first and second sides.
07/02/15
20150189764
 Preparation  a thin power device patent thumbnailnew patent Preparation a thin power device
A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back surface of the substrate, a through opening opened from the front surface and through the substrate exposing a third contact pad at the back surface of the substrate, a semiconductor chip embedded into the through opening with a back metal layer at a back surface of the semiconductor chip attached on the third contact pad, and a plurality of conductive structures electrically connecting electrodes at a front surface of the semiconductor chip with the corresponding first contact pads in the first sets of first contact pads.. .
07/02/15
20150189761
 Method for depositing and curing nanoparticle-based ink patent thumbnailnew patent Method for depositing and curing nanoparticle-based ink
A method for forming a conductive pattern on a substrate deposits, onto a surface of the substrate, a nanoparticle ink that comprises nanoparticles of a conductive or semiconductor material, at least one low boiling point solvent, and from 0.1 weight % to 50 weight % of a high boiling point solvent. The method forms a partially wet patterned substrate by drying the deposited nanoparticle ink to a wetness range between about 3 weight % and 8 weight % solvent.
07/02/15
20150189726
 Wall-mountable wireless remote control device patent thumbnailnew patent Wall-mountable wireless remote control device
A wall-mountable remote control device may be installed in place of an existing light switch and may be configured to transmit wireless signals to an electrical load device, such as a screw-in light-emitting diode (led) lamp, to provide control of the electrical load device. The remote control device may comprise an air-gap switch adapted to be electrically coupled in series between a power source and the controllable light source, but may not comprise a bidirectional semiconductor switch for controlling the amount of power delivered to the electrical load device using a phase-control dimming technique.
07/02/15
20150189694
 Moisture reduction in an electric assembly patent thumbnailnew patent Moisture reduction in an electric assembly
The present invention relates to an electric assembly (1) comprising at least one semi-conductor component (2, 3, 4, 5; 6, 7, 8, 9; 10, 11, 12). The electric assembly (1) is arranged to be switched between a first mode and a second mode, where the electric assembly is arranged to be run in a stand-by condition during the first mode and in an operational condition during the second mode.
07/02/15
20150189214
 Electronic device patent thumbnailnew patent Electronic device
An electronic device comprising a laminated structure including a first semiconductor chip and a second semiconductor chip is disclosed. In one example, the first semiconductor chip includes a sensor portion in which sensors are arranged, and the second semiconductor chip includes a signal processing portion in which signals obtained by the sensors are processed.
07/02/15
20150189207
 Protection layer in cmos image sensor array region patent thumbnailnew patent Protection layer in cmos image sensor array region
A semiconductor image sensor device having a conformal protective layer includes a semiconductor substrate a pixel-array region and a peripheral region. The conformal protective layer is disposed over a plurality of pixels having a photodiode and a plurality of transistors in the pixel-array region.
07/02/15
20150189204
 Semiconductor device on cover substrate and  making same patent thumbnailnew patent Semiconductor device on cover substrate and making same
A sensor device comprising a sensor die, a second substrate and a conductor assembly. The sensor die includes a first substrate having front and back surfaces, a sensor disposed in or at the front surface, bond pads disposed in or at the front surface and electrically coupled to the sensor, and a plurality of openings each extending from the back surface to one of the bond pads.
07/02/15
20150189200
 Cmos image sensor based on thin-film on asic and operating method thereof patent thumbnailnew patent Cmos image sensor based on thin-film on asic and operating method thereof
Provided are a complementary metal-oxide semiconductor (cmos) image sensor based on a thin-film-on-application specific integrated circuit (tfa), and a method of operating the same. The cmos image sensor may include at least one floating diffusion region formed in a semiconductor substrate, and a thin film type light sensor disposed to correspond to a plurality of pixels.
07/02/15
20150189196
new patent

Dispersion material, photoelectric conversion device, and imaging unit


A dispersion material includes: a plurality of semiconductor nanoparticles; and an adsorption molecule configured to selectively absorb light having a predetermined wavelength and adsorbed to each of the plurality of semiconductor nanoparticles, the adsorption molecule having a plane aligned to be non-parallel to a direction from a center portion of each of the plurality of semiconductor nanoparticles toward an adsorption portion of each of the plurality of semiconductor nanoparticles.. .
07/02/15
20150188577
new patent

Controller of nonvolatile semiconductor memory


According to one embodiment, a controller includes a decoder, calculation section, table creation, and control section. The decoder converts ecc frames into likelihood information based on a set table, generates decoded ecc frames by decoding using the likelihood information and switches the set table when there is an ecc frame in which the decoding is unsuccessful.
07/02/15
20150188557
new patent

Semiconductor device


To determine the accuracy of an ad converter more simply than in the related art, a semiconductor device includes a successive approximation ad converter. The ad converter includes one or a plurality of testing capacitors used in a test mode, separately from a c-dac used for ad conversion in a normal mode.
07/02/15
20150188555
new patent

A/d converter circuit and semiconductor integrated circuit


An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit.
07/02/15
20150188544
new patent

Semiconductor apparatus cross-references to related application


A semiconductor apparatus including an inverter chain including a plurality of inverters, wherein the plurality of inverters are electrically coupled in series, and at least one of the plurality of inverters includes at least two output nodes.. .
07/02/15
20150188536
new patent

Method and system for reliable bootstrapping switches


Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (mos) transistor having a pull-down path coupled to a gate terminal of the switching mos transistor. The pull-down path includes a diode-connected mos transistor coupled in parallel with a second mos transistor that couples the gate terminal of the switching mos transistor to ground via third and fourth mos transistors when the switching mos transistor is in an off state.
07/02/15
20150188534
new patent

Semiconductor device


A semiconductor device includes: a first field-effect transistor configured to have a source connected to a reference potential node; a second field-effect transistor configured to have a source connected to a drain of the first field-effect transistor, and a gate connected to the source of the first field-effect transistor; a gate signal node configured to input a gate signal therein; a first resistor configured to be connected between the gate signal node and a gate of the first field-effect transistor; and a first capacitor and a switch circuit configured to be connected between a drain of the second field-effect transistor and the gate of the first field-effect transistor, in which the switch circuit is connected in series with the first capacitor.. .
07/02/15
20150188529
new patent

Semiconductor device


A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal.. .
07/02/15
20150188526
new patent

Semiconductor apparatus


A delay circuit of a semiconductor apparatus includes a control signal generation block configured to output a control signal having an analog voltage level in response to an input signal, and an input/output block configured to delay the input signal by a delay amount based on the analog voltage level of the control signal, and output a resultant signal.. .
07/02/15
20150188520
new patent

Semiconductor device


A semiconductor device that can operate normally with lower power consumption is provided. The semiconductor device includes a pair of first circuits which each include a first transistor and a second transistor capable of controlling the supply of a first signal to a gate of the first transistor, and a second circuit which is capable of generating a second signal which is to be supplied to a gate of the second transistor and which has a larger amplitude than the first signal.
07/02/15
20150188518
new patent

Semicondutor controlling back bias


A semiconductor apparatus includes a back bias control block, a first back bias switching block and second back bias switching block. The back bias control block is configured to generate a first p channel control signal and a second n channel control signal.
07/02/15
20150188501
new patent

Power amplifying apparatus


A power amplifying apparatus may include a first amplifying unit receiving power and amplifying a high frequency signal, a second amplifying unit receiving the power and amplifying the high frequency signal from the first amplifying unit, and a control unit controlling an operation of the first amplifying unit or the second amplifying unit. The first amplifying unit and the control unit are disposed on a complementary metal oxide semiconductor (cmos) substrate, and the second amplifying unit is disposed on a gaas substrate..
07/02/15
20150188479
new patent

Vehicular ac electric generator


To provide a vehicular ac electric generator provided with a highly reliable electric power conversion unit. A stator of a rotary electric machine is configured to have a plurality of sets of three-phase windings, an electric power conversion unit is configured to have a plurality of sets of three-phase bridge circuits corresponding to the plurality of sets of three-phase windings, each of the three-phase windings of the stator is connected to a dc power supply via the corresponding three-phase bridge circuits of the electric power conversion unit, the plurality of sets of three-phase bridge circuits are controlled to be at different switching timings from each other, and semiconductor switches constituting respective arms in the plurality of sets of three-phase bridge circuits are configured to be one-chip mosfets..
07/02/15
20150188452
new patent

Actuating circuit for three-level inverter


An actuating circuit having a primary-side circuit part with an actuating logic circuit and a primary-side reference potential, and four secondary-side circuit parts each having one driver stage designed for actuating a phase of a three-level inverter and a first to fourth semiconductor switch, wherein each semiconductor switch and the secondary-side circuit part assigned thereto has a respective first to fourth secondary-side reference potential, and wherein in each case a level shifter connects the primary-side circuit part to the respective secondary-side circuit part and thus is assigned in each case to both circuit parts. In this connection, the primary-side reference potential corresponds to the first secondary-side reference potential.
07/02/15
20150188447
new patent

Electrical power converter


An electrical power converter includes: ac voltage terminals u, v, and w; dc voltage terminals p and n; a converter cell series unit composed of one or more converter cells connected in series between the ac voltage terminals u, v, and w and the dc voltage terminals p and n, each converter cell including a semiconductor element and a capacitor; and a first inductance connected in series to the converter cell series unit, between, of the dc voltage terminals p and n, a dc voltage terminal at the lowest potential with respect to the ground, and the ac voltage terminals u, v, and w.. .
07/02/15
20150188436
new patent

Semiconductor device


The present invention is directed to prevent occurrence of a problem on a withstand voltage in a circuit group which receives supply of an internal power supply voltage. An error amplifier outputs a control voltage obtained by amplifying a difference voltage between a reference voltage and a divided voltage obtained by dividing an internal power supply voltage to an output node.
07/02/15
20150188422
new patent

Dc-dc converter and semiconductor integrated circuit


The dc-dc converter includes a reference voltage generating circuit that generates a reference voltage. The dc-dc converter includes a modulation clock signal generating circuit that generates a modulation clock signal.
07/02/15
20150188410
new patent

Power conversion device


A power conversion device, including first and second semiconductor switching elements, first and second free wheeling diodes respectively connected in reverse parallel to the first and second semiconductor switching elements, and first and second drive circuits configured to respectively on/off drive the first and second semiconductor switching elements. The first and second semiconductor switching elements are connected in series to form a half bridge circuit and are respectively disposed on upper and lower arms of the half bridge circuit.
07/02/15
20150188311
new patent

Semiconductor device


Of a wireless communication system, an rf tag which can operate normally even when a communication distance is extremely short, like the case where the rf tag is in contact with a reader/writer, whereby the reliability is improved. The rf tag which communicates data by wireless communication includes a comparison circuit which compares electric power supplied from outside with reference electric power and a protection circuit portion which is operated when the electric power supplied from outside is higher than the reference electric power in the comparison circuit..
07/02/15
20150188280
new patent

Metal-insulator-metal waveguide for nano-lasers and optical amplifiers


A metal-insulator-metal (mim) waveguide structure for nano-lasers or optical amplifiers is described. The structure comprises a substrate on which are supported first and second metal layers which form electrical contacts for the waveguide.
07/02/15
20150188065
new patent

Semiconductor device, manufacturing semiconductor device, solid-state image pickup unit, and electronic apparatus


There are provided a semiconductor device capable of adjusting a work function without reducing light transmittance of an electrode, a method of manufacturing this semiconductor device, a solid-state image pickup unit including this semiconductor device, and an electronic apparatus including this solid-state image pickup action. The semiconductor device includes a functional layer between a first electrode and a second electrode, the functional layer including an organic film, in which the first electrode and the second electrode are made of a same transparent conductive material, and an oxygen amount at an interface on the functional layer side of the first electrode is smaller than an oxygen amount at an interface on the functional layer side of the second electrode..
07/02/15
20150188063
new patent

Organic thin film transistor and producing same


An organic thin film transistor includes an insulating substrate (1), gate electrodes (2, 4), a gate insulating film (3), an organic semiconductor film (5), and a source electrode (6) and a drain electrode (7). The gate electrodes include a main gate electrode (2) that is disposed in a region opposed to a channel region between the source electrode and the drain electrode in the organic semiconductor film, and a pair of auxiliary gate electrodes (4) that are disposed in respective regions opposed to the source electrode and the drain electrode on the two sides of the main gate electrode.
07/02/15
20150188053
new patent

Method for preparing a semiconducting layer


A method for preparing a semiconducting layer of an organic electronic device comprising: (i) depositing said semiconducting layer from a solution comprising a polymeric semiconductor, a non-polymeric semiconductor, a first aromatic solvent and a second aromatic solvent, wherein said second aromatic solvent has a boiling point that is at least 15° c. Higher than the boiling point of said first aromatic solvent; and (ii) heating said deposited layer to evaporate said solvent, wherein said first aromatic solvent is of formula (i): wherein r1 is selected from c1-6 alkyl and oc1-6 alkyl; and r2 and r3 are each independently selected from h and cc1-6 alkyl..
07/02/15
20150188038
new patent

Phase change memories


A method is provided for fabricating a phase change memory. The method includes providing a semiconductor substrate having a bottom electrode connecting with one or more semiconductor devices, and forming a first dielectric layer on the semiconductor substrate.
07/02/15
20150188012
new patent

Light-emitting diode elements


A light-emitting diode element is provided. N light-emitting diode chips are arranged on a substrate.
07/02/15
20150188011
new patent

Side-emitting type nitride semiconductor light emitting chip and nitride semiconductor light emitting device having the same


Disclosed are a side-emitting type nitride semiconductor light-emitting chip and a light-emitting device comprising the same, which emit light from the sides so that the beam angle of the light can be increased and the need for a lead frame mold cup and a lens can be eliminated.. .
07/02/15
20150188009
new patent

Method of manufacturing semiconductor device


The present disclosure provides a method of manufacturing a semiconductor device, including providing a semiconductor structure including a sequential stack of an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. A first metal layer and a second metal layer on the first metal layer are formed on the semiconductor structure.
07/02/15
20150188008
new patent

Curable resin composition, curable resin composition tablet, molded body, semiconductor package, semiconductor component and light emitting diode


The present invention aims to provide a curable resin composition which gives a cured product having a low linear expansion coefficient. The curable resin composition of the present invention contains, as essential components, (a) an organic compound having at least two carbon-carbon double bonds reactive with sih groups per molecule, (b) a compound containing at least two sih groups per molecule, (c) a hydrosilylation catalyst, (d) a silicone compound having at least one carbon-carbon double bond reactive with a sih group per molecule, and (e) an inorganic filler..
07/02/15
20150188004
new patent

Semiconductor light emitting device


A light emitting device includes a substrate, a light emitting element mounted on the substrate, a light transmissive member placed on an upper surface of the light emitting element, and a sealing member which seals the light emitting element and the light transmissive member. The light transmissive member is a plate-shaped member not containing a phosphor and is larger than the light emitting element when viewed from above.
07/02/15
20150187997
new patent

Light-emitting diode chip


A light-emitting diode (led) chip is disclosed. The led chip includes a substrate and a led stack on the substrate.
07/02/15
20150187996
new patent

Light emitting diode having electrode pads


A substrate, a first conductive type semiconductor layer arranged on the substrate, a second conductive type semiconductor layer arranged on the first conductive type semiconductor layer, an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer, a first electrode pad electrically connected to the first conductive type semiconductor layer, a second electrode pad arranged on the second conductive type semiconductor layer, an insulation layer disposed between the second conductive type semiconductor layer and the second electrode pad, and at least one upper extension electrically connected to the second electrode pad, the at least one upper extension being electrically connected to the second conductive type semiconductor layer.. .
07/02/15
20150187995
new patent

Light emitting device


A light emitting device is constituted with a semiconductor light emitting element on which a support member is disposed on one surface provided with a p-side electrode and an n-side electrode and a fluorescent material layer is disposed on the other surface which is an opposite side of the one surface. The support member includes a resin layer, an electrode for p-side external connection and an electrode for n-side external connection disposed exposed at a surface opposite side of a surface where the resin layer is in touch with a light emitting element, and internal wirings disposed in the resin layer and electrically connecting between a p-side electrode and the electrode for p-side external connection respectively.
07/02/15
20150187994
new patent

Light emitting device


Disclosed is a light emitting device. A light emitting device comprises a plurality of n-type semiconductor layers including a first n-type semiconductor layer and a second n-type semiconductor layer on the first n-type semiconductor layer, an active layer on the second n-type semiconductor layer, and a p-type semiconductor layer on the active layer, wherein the first n-type semiconductor layer comprises a si doped nitride layer and the second n-type semiconductor layer comprises a si doped nitride layer, and wherein the first and second n-type semiconductor layers have a si impurity concentration different from each other..
07/02/15
20150187993
new patent

Semiconductor light-emitting device and manufacturing the same


The disclosed invention relates to a semiconductor light-emitting element comprising: a plurality of semiconductor layers which are provided with a growth substrate eliminating surface on the side where a first semiconductor layer is located; a support substrate which is provided with a first electrical pathway and a second electrical pathway; a joining layer which joins a first surface side of the support substrate with a second semiconductor layer side of the plurality of semiconductor layers, and is electrically linked with the first electrical pathway; a joining layer eliminating surface which is formed on the first surface, and in which the second electrical pathway is exposed, and which is open towards the plurality of semiconductor layers; and an electrical link for electrically linking the plurality of semiconductor layers with the second electrical pathway exposed in the joining layer eliminating surface.. .
07/02/15
20150187990
new patent

Light-emitting diode and fabrication method thereof


A light-emitting diode includes a substrate; a light-emitting epitaxial layer, laminated by semiconductor material layers and formed over the substrate; a first current spreading layer over the light-emitting epitaxial layer; an adhesive layer with alternating second current spreading layers and first metal barrier layers over the first current spreading layer, including three structure layers; a second metal barrier layer over the adhesive layer with alternating second current spreading layers and metal barrier layers; and a metal electrode layer over the second metal barrier layer.. .
07/02/15
20150187988
new patent

Light-emitting device, light-emitting device package, and light unit


A light-emitting device, according to one embodiment, comprises: a light-emitting structure comprising a first conductive semiconductor layer, an active layer which is underneath the first conductive semiconductor layer, and a second conductive semiconductor layer which is underneath the active layer; a first electrode which is arranged under the light-emitting structure and is electrically connected to the second conductive semiconductor layer; a reflection layer which is arranged inside the second conductive semiconductor layer and arranged apart from the first electrode and the active layer; and a second electrode which is electrically connected to the first conductive semiconductor layer.. .
07/02/15
20150187985
new patent

Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip


In at least one embodiment, the method is designed to produce an optoelectronic semiconductor chip. The method includes at least the following steps in the stated sequence: a) providing a growth substrate with a growth side, b) depositing at least one nucleation layer based on alxga1-xoyn1-y on the growth side, c) depositing and structuring a masking layer, d) optionally growing a gan-based seed layer in regions on the nucleation layer not covered by the masking layer, e) partially removing the nucleation layer and/or the seed layer in regions not covered by the masking layer or applying a second masking layer on the nucleation layer or on the seed layer in the regions not covered by the masking layer, and f) growing an alingan-based semiconductor layer sequence with at least one active layer..
07/02/15
20150187973
new patent

Solar cell and manufacturing method thereof


A solar cell includes a semiconductor substrate of a first conductivity; a pillar-shaped structure constituted by a semiconductor of the first conductivity, the pillar-shaped structure being formed on the semiconductor substrate; a superlattice layer including a barrier layer and a quantum structure layer that are alternately deposited on a side wall of the pillar-shaped structure, the quantum structure layer being constituted by a material having a smaller energy bandgap than that of the barrier layer, the quantum structure layer including a wurtzite type crystal part and a zinc blende type crystal part that are alternately arranged along an axial direction of the pillar-shaped structure; and a semiconductor layer of a second conductivity that is formed so as to surround the superlattice layer, the second conductivity being an opposite conductivity to that of the first conductivity.. .
07/02/15
20150187972
new patent

Semiconductor photodetector element and method


A semiconductor photodetector element includes a semiconductor substrate having a first conductivity type; a columnar structure formed on a first surface of the semiconductor substrate, the columnar structure being composed of a semiconductor of the first conductivity type; a light absorption layer formed so as to surround the columnar structure; and a semiconductor layer formed so as to surround the light absorption layer.. .
07/02/15
20150187969
new patent

Systems and methods for monolithically isled solar photovoltaic cells


The monolithically isled solar cell comprises a semiconductor layer having a light receiving frontside and a passivated backside opposite the frontside. A first metal layer on the semiconductor layer passivated backside comprises base and emitter metallization islands corresponding to monolithic isled semiconductor regions.
07/02/15
20150187961
new patent

Piezoresistive sensor


The present disclosure relates to a piezoresistive sensor that improves measurement precision by using a piezoresistive pattern that increases a piezoresistive deformation rate. An embodiment of the present disclosure provides a piezoresistive sensor that may include: a semiconductor substrate, four beams formed as a cross-shape with reference to a central body of the semiconductor substrate, and sixteen piezoresistive patterns formed on a top of the four beams, wherein sixteen piezoresistive patterns are formed as an “x” shape and are disposed on the four beams so as to form four piezoresistive pattern groups..
07/02/15
20150187959
new patent

Array substrate


An array substrate having a thin film transistor with an oxide semiconductor layer, comprising: gate and data lines formed on the array substrate and defining a pixel region, wherein the thin film transistor is located in a device area of the pixel region; a light-shielding pattern arranged on the array substrate in the device area; an auxiliary line connected to the light-shielding pattern and supplying a constant voltage to the light-shielding pattern, wherein the auxiliary line is parallel to and spaced apart from one of the gate and data lines; a buffer layer of an inorganic material and located on the light-shielding pattern and a surface of the array substrate, wherein the oxide semiconductor layer is located on the buffer layer and the light-shielding pattern; an inter-insulating layer on the buffer layer, wherein the oxide semiconductor layer includes an active portion located entirely on the light-blocking pattern and having a channel formed thereon, and conductive portions located on sides of the active portion.. .
07/02/15
20150187955
new patent

Semiconductor device and manufacturing the same


It is an object to manufacture a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. An insulating layer which covers an oxide semiconductor layer of the thin film transistor contains a boron element or an aluminum element.
07/02/15
20150187954
new patent

Semiconductor device


A semiconductor device includes a first conductive layer, a first insulating layer over the first conductive layer, first and second oxide semiconductor layers over the first insulating layer, a second conductive layer over the first oxide semiconductor layer, a third conductive layer over the second oxide semiconductor layer, a fourth conductive layer over the first oxide semiconductor layer and the second oxide semiconductor layer, a second insulating layer over the second conductive layer, the third conductive layer, and the fourth conductive layer, a fifth conductive layer electrically connected to the first conductive layer over the second insulating layer, and a sixth conductive layer over the second insulating layer. Each of the first and fifth conductive layers includes an area overlapping with the first oxide semiconductor layer.
07/02/15
20150187953
new patent

Semiconductor device and display device including the semiconductor device


A novel semiconductor device including an oxide semiconductor is provided. In particular, a planar semiconductor device including an oxide semiconductor is provided.
07/02/15
20150187952
new patent

Semiconductor device


To provide a transistor with stable electrical characteristics, a transistor with a low off-state current, a transistor with a high on-state current, a semiconductor device including the transistor, or a durable semiconductor device. The semiconductor device includes a first transistor using silicon, an aluminum oxide film over the first transistor, and a second transistor using an oxide semiconductor over the aluminum oxide film.
07/02/15
20150187951
new patent

Semiconductor device


To provide a transistor with stable electric characteristics, provide a transistor having a small current in a non-conductive state, provide a transistor having a large current in a conductive state, provide a semiconductor device including the transistor, or provide a durable semiconductor device, a semiconductor device includes a first insulator containing excess oxygen, a semiconductor over the first insulator, a second insulator over the semiconductor, and a conductor having a region overlapping with the semiconductor with the second insulator provided therebetween. A region containing boron or phosphorus is located between the first insulator and the semiconductor..
07/02/15
20150187950
new patent

Semiconductor device


A transistor with stable electric characteristics is provided. An aluminum oxide film containing boron is formed in order to prevent hydrogen from diffusing into an oxide semiconductor film..
07/02/15
20150187949
new patent

Semiconductor device


High field-effect mobility is provided for a transistor including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided.
07/02/15
20150187948
new patent

Semiconductor device and producing same


This semiconductor device (100) includes: a gate electrode (12) formed on a substrate (10); a gate insulating layer (20) formed over the gate electrode; an oxide semiconductor layer (18) formed on the gate insulating layer; source and drain electrodes (14, 16) connected to the oxide semiconductor layer; and an insulating layer (22) formed over the source and drain electrodes. The insulating layer includes a silicon nitride layer (22a) which contacts with at least a part of the upper surface of the source and drain electrodes and of which the thickness is greater than 0 nm and equal to or smaller than 30 nm, and a silicon oxide layer (22b) which has been formed on the silicon nitride layer and which has a thickness of more than 30 nm..
07/02/15
20150187947
new patent

Finfet with active region shaped structures and channel separation


A semiconductor structure in fabrication includes a n-finfet and p-finfet. Stress inducing materials such as silicon and silicon germanium are epitaxially grown into naturally diamond-shaped structures atop the silicon fins of the n-finfet and p-finfet areas.
07/02/15
20150187946
new patent

Semiconductor devices including trench walls having multiple slopes


A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate.
07/02/15
20150187945
new patent

Salicide protection during contact metallization and resulting semiconductor structures


A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A gate is provided above the channel region.
07/02/15
20150187944
new patent

Semiconductor liner of semiconductor device


The disclosure relates to a fin field effect transistor (finfet). An exemplary finfet comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion, an upper portion, and a middle portion between the lower portion and upper portion, wherein the fin structure comprises a first semiconductor material having a first lattice constant; a pair of notches extending into opposite sides of the middle portion; and a semiconductor liner adjoining the lower portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant..
07/02/15
20150187943
new patent

Source/drain structure of semiconductor device


The disclosure relates to a semiconductor device having an isolation structure with a top surface over a substrate major surface; a cavity having a convex bottom surface below the top surface; and a strained material in the cavity and extending above the top surface. The strained material has an upper portion having a rhombus shape and a lower portion having substantially vertical sidewalls; and a pair of tapered spacers adjoining a portion of the substantially vertical sidewalls above the top surface..
07/02/15
20150187942
new patent

Semiconductor structure and manufacturing the same


The present invention discloses a semiconductor structure and a method for manufacturing the same, which comprises providing a substrate, and forming a stress layer, a buried oxide layer, and an soi layer on the substrate; forming a doped region of the stress layer arranged in a specific position in the stress layer; forming an oxide layer and a nitride layer on the soi layer, and forming a first trench that etches the nitride layer, the oxide layer, the soi layer, and the buried oxide layer, and stops on the upper surface of the stress layer, and exposes at least part of the doped region of the stress layer; forming a cavity by wet etching through the first trench to remove the doped region of the stress layer; forming a polycrystalline silicon region of the stress layer and a second trench by filling the cavity with polycrystalline silicon and etching back; forming an isolation region by filling the second trench. The semiconductor structure and the method for manufacturing the same disclosed in the present invention provide a favorable stress for the channel of the semiconductor device by introducing a stress layer and a stress induced zone set at specific positions depending on device type to help improving the performance of the semiconductor device..
07/02/15
20150187940
new patent

Semiconductor device structure and manufacturing the same


Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate.
07/02/15
20150187939
new patent

Metal gate transistor and tuning metal gate profile


A semiconductor device having arrays of metal gate transistors is fabricated by forming a number of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer, depositing a tensile ild layer between the dummy gate structures, stressing the tensile ild layer, removing at least the dummy gate material to form a number of trenches, and depositing a metal gate material in the trenches, which have a tapered profile.. .
07/02/15
20150187936
new patent

Quasi-vertical structure having a sidewall implantation for high voltage mos device


A semiconductor device includes a buried layer in a substrate, the buried layer having a first dopant type. The semiconductor device further includes a first layer over the buried layer, the first layer having the first dopant type.
07/02/15
20150187935
new patent

Semiconductor device including pillar transistors


A first pillar transistor and a second pillar transistor are arranged with no other pillar transistor therebetween, a distance between a first silicon pillar in the first pillar transistor and a second silicon pillar in the second pillar transistor is smaller than a distance between a third silicon pillar in a third pillar transistor and the first silicon pillar.. .
07/02/15
20150187932
new patent

Power semiconductor device and fabricating the same


A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a substrate and an active layer on the substrate.
07/02/15
20150187930
new patent

Semiconductor element


A drain drift portion is a first parallel p-n structure, largely corresponding to a portion directly below a p-type base region forming an active region, formed by first n-type regions and first p-type regions being alternately and repeatedly joined. The periphery of the drain drift portion is an edge termination region formed of a second parallel p-n structure aligned contiguously to the first parallel p-n structure and formed by second n-type regions and second p-type regions being alternately and repeatedly joined.
07/02/15
20150187929
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes: a first n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate including a current carrying region and termination regions positioned at both sides of the current carrying region; a p type epitaxial layer disposed on the first n− type epitaxial layer; a second n− type epitaxial layer disposed on the p type epitaxial layer; a first trench disposed in the current carrying region; a second trench disposed in each termination region; a gate insulating layer disposed in the first trench; a gate electrode disposed on the gate insulating layer; and a termination insulating layer disposed in the second trench, in which a side of the termination insulating layer contacts the p type epitaxial layer and the second n− type epitaxial layer.. .
07/02/15
20150187928
new patent

Semiconductor device, related manufacturing method, and related electronic device


A semiconductor device may include a first-type substrate. The semiconductor device may further include a second-type well configured to form a pn junction with the first-type substrate.
07/02/15
20150187927
new patent

Method to reduce etch variation using ion implantation


The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate.
07/02/15
20150187926
new patent

Group 13 nitride composite substrate semiconductor device, and manufacturing group 13 nitride composite substrate


Provided are a group 13 nitride composite substrate allowing for the production of a semiconductor device suitable for high-frequency applications while including a conductive gan substrate, and a semiconductor device produced using this substrate. The group 13 nitride composite substrate includes a base material of an n-conductivity type formed of gan, a base layer located on the base material, being a group 13 nitride layer having a resistivity of 1×106 Ω·cm or more, a channel layer located on the base layer, being a gan layer having a total impurity density of 1×1017/cm3 or less, and a barrier layer that is located on the channel layer and is formed of a group 13 nitride having a composition alxinyga1-x-yn (0≦x≦1, 0≦y≦1)..
07/02/15
20150187923
new patent

Semiconductor element and solid-state imaging device


A semiconductor element encompasses a charge-transfer path defined in a semiconductor region (34.35), configured to transfer signal charges, (b) a pair of first field-control electrodes (42a, 42b) laminated via an insulating film on the semiconductor region so as to sandwich the charge-transfer path in between, and a pair of second field-control electrodes (43a, 43b) arranged separately from and adjacently to the first field-control electrodes (42a, 42b). By applying field-control voltages differing from each other, to the first and second field-control electrodes (43a, 43b), a depleted potential in the charge-transfer path is changed, and a movement of the signal charges transferring in the semiconductor region is controlled.
07/02/15
20150187922
new patent

Power semiconductor device


A power semiconductor device may include: a first conductivity-type drift region in which a plurality of trench gates each including a gate insulating layer disposed on a surface thereof and a conductive material filling the interior thereof are disposed; a second conductivity-type body region disposed on an inner side of an upper portion of the drift region and disposed to be in contact with the trench gate; a first conductivity-type emitter region disposed on an inner side of an upper portion of the body region and disposed to be in contact with the trench gate; and a hole accumulation region disposed in the drift region, disposed below the body region, and disposed between the trench gates.. .
07/02/15
20150187921
new patent

Power semiconductor device


A power semiconductor device may include a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type and formed in an upper portion of the first semiconductor region; a third semiconductor region having a first conductivity type and formed in an upper portion of the second semiconductor region; and a trench gate formed by penetrating from the third semiconductor region to the first semiconductor region. A portion of at least one of the first semiconductor region, the second semiconductor region, and the third semiconductor region may include a device protection material of which a conduction band has a main state and a satellite state in an e-k diagram, and a curvature of the device protection material in the satellite state may be lower than a curvature thereof in the main state in the e-k diagram..
07/02/15
20150187920
new patent

Power semiconductor device


A power semiconductor device may include: a first conductivity-type first semiconductor region; a second conductivity-type second semiconductor region disposed above the first semiconductor region; a trench gate penetrating through the second semiconductor region and a portion of the first semiconductor region; a third semiconductor region disposed on both sides of the trench gate and disposed on an inner side of an upper portion of the second semiconductor region; and a device protective region disposed in the third semiconductor region.. .
07/02/15
20150187919
new patent

Power semiconductor device


A provided a power semiconductor device may include: a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type formed on the first semiconductor region; a plurality of trench gates formed to penetrate through the second semiconductor region and lengthily formed in one direction; and a third semiconductor region of the first conductive type formed on the second semiconductor region, formed at least partially in a length direction between the plurality of trench gates, and formed to contact one side of an adjacent trench gate in a width direction.. .
07/02/15
20150187918
new patent

Power semiconductor device


A power semiconductor device may include: a semiconductor laminate formed by stacking a plurality of semiconductor layers each having an emitter metal layer formed on a top thereof and a collector metal layer formed on a bottom thereof; an insulating layer interposed between the semiconductor layers; and a first external electrode and a second external electrode formed on sides of the semiconductor laminate. The first external electrode is electrically connected to the emitter metal layer, and the second external electrode is electrically connected to the collector metal layer..
07/02/15
20150187917
new patent

Semiconductor device and manufacturing semiconductor device


To provide a miniaturized transistor having high electric characteristics. A conductive film to be a source electrode layer and a drain electrode layer is formed to cover an oxide semiconductor layer and a channel protection layer, and then a region of the conductive film, which overlaps with the oxide semiconductor layer and the channel protection layer, is removed by chemical mechanical polishing treatment.
07/02/15
20150187914
new patent

Finfet including improved epitaxial topology


A semiconductor device includes a semiconductor substrate having a plurality of semiconductor fins formed on an upper surface thereof. An epitaxial material is formed on the upper surface of the semiconductor substrate and on an outer surface of the semiconductor fins.
07/02/15
20150187913
new patent

Trench-gate resurf semiconductor device and manufacturing method


A trench-gate device with lateral resurf pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the resurf pillars, and this provides additional gate shielding which improves the electrical characteristics of the device..
07/02/15
20150187912
new patent

Integrated electronic device with edge-termination structure and manufacturing method thereof


An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.. .
07/02/15
20150187911
new patent

Semiconductor device and fabrication method thereof


A semiconductor device includes a gate electrode formed on a sidewall of a structure extending from a semiconductor substrate. A junction region is form in the structure to a first depth from a top of the structure and formed to overlap the gate electrode.
07/02/15
20150187910
new patent

Methods of manufacturing semiconductor devices and electronic devices


In a method of manufacturing a semiconductor device, an isolation layer pattern is formed on a substrate to define a field region covered by the isolation layer pattern and first and second active regions that is not covered by the isolation layer pattern and protrudes from the isolation layer pattern. A first anti-reflective layer is formed on the isolation layer pattern.
07/02/15
20150187909
new patent

Methods for fabricating multiple-gate integrated circuits


A method for fabricating an integrated circuit includes providing a silicon semiconductor substrate including a single-crystal crystallography, removing a portion of the semiconductor substrate to form a fin structure, the fin structure being defined by adjacent trenches formed within the semiconductor substrate, and forming an insulating material in the trenches, the insulating material covering a first portion of the fin and leaving a second portion of the fin exposed. The method further includes applying a wet etchant to the second portion of the fin, the wet etchant including an etching chemistry that selectively etches the fin against a <111> crystallographic orientation of the single-crystal silicon..
07/02/15
20150187908
new patent

Method for fabricating semiconductor device


Methods for fabricating semiconductor devices are provided. Gate structures are formed on a top surface of a substrate to form semiconductor devices.
07/02/15
20150187907
new patent

Semiconductor device including gate electrode provided over active region in p-type nitride semiconductor layer and manufacturing the same, and power supply apparatus


A semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and including an active region and an inactive region; an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and a gate electrode provided over the active region in the p-type nitride semiconductor layer.. .
07/02/15
20150187906
new patent

Semiconductor device and manufacturing method


A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.. .
07/02/15
20150187905
new patent

Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices


One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.. .
07/02/15
20150187904
new patent

Semiconductor device structure and manufacturing the same


Embodiments of a method for forming a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a sealing structure over a sidewall of the gate stack.
07/02/15
20150187902
new patent

Semiconductor structure having interfacial layer and high-k dielectric layer


A semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an interfacial layer over the semiconductor substrate, the interfacial layer having a capacitive effective thickness of less than 1.37 nanometers (nm).
07/02/15
20150187900
new patent

Composite materials for use in semiconductor components


An integrated circuit including a transistor, wherein the transistor includes a substrate including a surface, a gate oxide deposited on the substrate surface and a gate deposited on the gate oxide. The gate oxide includes one or more dielectric domains and a band gap matrix.
07/02/15
20150187899
new patent

Semiconductor device and forming the same


A semiconductor device includes a junction region on both sides of a trench in a semiconductor substrate, a first gate electrode with a first workfunction buried in the trench, and a second gate electrode formed of a polycide layer having a second workfunction overlapping with the junction region at an upper part of the first gate electrode.. .
07/02/15
20150187898
new patent

Semiconductor device and manufacturing the same


A novel semiconductor device with a transistor using an oxide semiconductor film, in which a conductive film including cu is used as a wiring or the like, is provided. The semiconductor device includes a first insulating film, an oxide semiconductor over the first insulating film, a gate electrode overlapping the oxide semiconductor with a gate insulating film positioned therebetween, a second insulating film in contact with a side surface of the gate electrode, and a third insulating film in contact with a top surface of the gate electrode.
07/02/15
20150187897
new patent

Partial sacrificial dummy gate with cmos device with high-k metal gate


A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.. .
07/02/15
20150187896
new patent

Silicide protection during contact metallization and resulting semiconductor structures


A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region.
07/02/15
20150187895
new patent

Thin film transistor structure


A thin film transistor structure includes a substrate, a gate structure, a semiconductor active layer, a drain structure and a source structure. The gate structure and the semiconductor active layer are disposed above the substrate.
07/02/15
20150187893
new patent

Semiconductor devices with field plates


A iii-n device is described with a iii-n material layer, an insulator layer on a surface of the iii-n material layer, an etch stop layer on an opposite side of the insulator layer from the iii-n material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer.
07/02/15
20150187892
new patent

Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device is disclosed, comprising: forming a contact sacrificial layer on the substrate, etching the contact sacrificial layer to form a contact sacrificial pattern, wherein the contact sacrificial pattern covers the source region and the drain region and has a gate trench that exposes the substrate; forming a gate spacer and a gate stack structure in the gate trench; partially or completely etching off the contact sacrificial pattern that covers the source region and the drain region so as to form a source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of the double-layer contact sacrificial layer, the method for manufacturing a semiconductor device in accordance with the present invention effectively reduces the spacing between the gate spacer and the contact region and increases the area of contact region, thus effectively reducing the parasitic resistance of the device..
07/02/15
20150187891
new patent

Formation of gate sidewall structure


A semiconductor device having a gate stack on a substrate is disclosed. The gate stack may include a mask layer disposed over a first gate conductor layer.
07/02/15
20150187889
new patent

Surface-controlled semiconductor nano-devices, methods and applications


semiconductor structures and semiconductor devices may include: (1) an n-type compound semiconductor material having a surface fermi level pinned to a conduction band of the n-type compound semiconductor material; (2) a p-type compound semiconductor material having a surface fermi level pinned to a valence band of the p-type compound semiconductor material; and/or (3) an i-type compound semiconductor materials having a surface fermi level pinned within a band gap of the i-type compound semiconductor material. Semiconductor structures and semiconductor devices in accordance with the foregoing n-type, p-type and i-type compound semiconductor materials provide the semiconductor structures and semiconductor devices with enhanced performance..
07/02/15
20150187887
new patent

Iii nitride semiconductor device and manufacturing the same


Provided is a iii nitride semiconductor device higher heat dissipation performance, and a method of manufacturing a iii nitride semiconductor device which makes it possible to fabricate such a iii nitride semiconductor device at higher yield. In a method of a iii nitride semiconductor device, a semiconductor structure obtained by sequentially stacking an n-layer, an active layer, and a p-layer is formed on a growth substrate; a support body including a first support electrically connected to an n-layer to serve as an n-side electrode, a second support electrically connected to a p-layer to serve as a p-side electrode, and structures made of an insulator for insulation between first and second supports is formed on the p-layer side of the semiconductor structure; and the growth substrate is separated using a lift-off process.
07/02/15
20150187886
new patent

Nitride semiconductor device


Provided is a nitride semiconductor device including: a substrate having through via holes; first and second nitride semiconductor layers sequentially stacked on the substrate; drain electrodes and source electrodes provided on the second nitride semiconductor layer; and an insulating pattern provided on the second nitride semiconductor layer, the insulating pattern having upper via holes provided on the drain electrodes, wherein the through via holes are extended into the first and second nitride semiconductor layers and expose a bottom of each of the source electrodes.. .
07/02/15
20150187885
new patent

Semiconductor epitaxial structure and forming the same


A semiconductor epitaxial structure is provided, which includes: a nitride nucleation layer, formed on a substrate including silicon, sapphire, patterned sapphire substrate (pss) or silicon carbide, a nitride layer on the nitride nucleation layer and an multi-layer structure in the nitride layer. The multi-layer structure includes a first intermediate layer and a second intermediate layer formed on the first intermediate layer.
07/02/15
20150187884
new patent

Method and system for transient voltage suppression


A transient voltage suppression (tvs) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (μm) and 22.0 μm thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.. .
07/02/15
20150187883
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes: a first n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a p type epitaxial layer disposed on the first n− type epitaxial layer; a second n− type epitaxial layer disposed on the p type epitaxial layer; an n+ region disposed on the second n− type epitaxial layer; a trench passing through the second n− type epitaxial layer, the p type epitaxial layer, and the n+ region, and disposed on the first n− type epitaxial layer; a p+ region disposed on the p type epitaxial layer and separated from the trench; and a gate insulating layer positioned in the trench, in which channels are disposed in the second n− type epitaxial layer of both sides of the trench and the p type epitaxial layer of both sides of the trench.. .
07/02/15
20150187882
new patent

Semiconductor device, manufacturing the same and power semiconductor device including the same


A method of manufacturing a semiconductor device may include: preparing a substrate formed of sic; depositing crystalline or amorphous silicon (si) on one surface of the substrate to form a first semiconductor layer; and performing a heat treatment under a nitrogen atmosphere to form a second semiconductor layer formed of sicn between the substrate and the first semiconductor layer.. .
07/02/15
20150187881
new patent

Contact resistance reduction in finfets


A semiconductor device having fin transistors includes a plurality of substantially parallel semiconductor fins formed over a substrate and a gate structure formed over the fins transversely to a longitudinal axis of the fins. Source and drain regions are formed on opposite sides of the gate structure and are merged with the fins by an epitaxially grown crystalline material between the fins in merged regions.
07/02/15
20150187880
new patent

Semiconductor structure with compositionally-graded transition layer


The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer.
07/02/15
20150187879
new patent

Lateral mos power transistor having backside terminal


A semiconductor component may include a semiconductor layer which has a front side and a back side, a first terminal electrode on the front side, a second terminal electrode on the back side, a first dopant region of a first conduction type on the front side, which is electrically connected to one of the terminal electrodes, a second dopant region of a second conduction type in the semiconductor layer, which is electrically connected to the other terminal electrode, a pn junction being formed between the first and second dopant regions, a dielectric layer on the back side between the semiconductor layer and the second terminal electrode, and the dielectric layer having an opening through which an electrical connection between the second terminal electrode and the first or second dopant region is passed.. .
07/02/15
20150187878
new patent

Semiconductor device


To provide a semiconductor device including a transistor in which an oxide semiconductor is used and on-state current is high. In a semiconductor device including a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion, the first transistor and the second transistor have different structures.
07/02/15
20150187877
new patent

Power semiconductor device


A power semiconductor device may include: an active region having a channel formed therein when the power semiconductor device is turned on, the channel allowing a current to flow therethrough; a termination region formed around the active region; first trenches formed in the active region, each first trench having an insulating layer formed on a surface thereof and filled with a conductive material; and second trenches formed in the termination region, each second trench having an insulating layer formed on a surface thereof and filled with a conductive material.. .
07/02/15
20150187876
new patent

Nitride semiconductor structure


A nitride semiconductor structure including a silicon substrate, a nucleation layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate.
07/02/15
20150187875
new patent

Semiconductor body with a buried material layer and method


One aspect includes a method for forming a buried material layer in a semiconductor body, including providing a semiconductor body having a first side and having a plurality of first trenches extending from the first surface into the semiconductor body. Each of the plurality of first trenches has a bottom and has at least one sidewall and the plurality of first trenches is separated from one another by semiconductor mesa regions.
07/02/15
20150187874
new patent

Field-effect semiconductor device and manufacturing therefor


A power semiconductor device includes a semiconductor body having a first surface and including an active area including n-type semiconductor regions and p-type semiconductor regions, the n-type semiconductor regions alternating, in a direction substantially parallel to the first surface, with the p-type semiconductor regions. The semiconductor body further includes a peripheral area surrounding the active area and including a low-doped semiconductor region having a first concentration of n-dopants lower than a doping concentration of n-dopants of the n-type semiconductor regions, and at least one auxiliary semiconductor region having a concentration of n-dopants higher than the first concentration and a concentration of p-dopants higher than the first concentration..
07/02/15
20150187870
new patent

Semiconductor device


In a semiconductor device, an edge termination region which surrounds an active region includes an electric field reduction mechanism including guard rings, first field plates which come into contact with the guard rings, and second field plates which are provided on the first field plates, with an interlayer insulating film interposed therebetween. The second field plate is thicker than the first field plate.
07/02/15
20150187869
new patent

Power semiconductor device


A power semiconductor device may include: a first conductivity-type first semiconductor region; a resurf region disposed in the first semiconductor region and including first conductivity-type second semiconductor regions and second conductivity-type third semiconductor regions alternately disposed in a width direction; a first conductivity-type first cover region disposed in the first semiconductor region, disposed to be contiguous with an upper surface of the resurf region, and having an impurity concentration higher than that of the first semiconductor region; a second conductivity-type fourth semiconductor region disposed above the first semiconductor region; a first conductivity-type fifth semiconductor region disposed on an inner side of an upper portion of the fourth semiconductor region; and a trench gate disposed to penetrate from the fifth semiconductor region to a portion of an upper portion of the first semiconductor region and including a gate insulating layer and a conductive material.. .
07/02/15
20150187868
new patent

Power semiconductor device


A power semiconductor device may include: an active region in which a current flows through a channel formed when the device being turned on; a termination region disposed around the active region; a first semiconductor region of a first conductive type disposed in the termination region in a direction from the active region to the termination region; and a second semiconductor region of a second conductive type disposed in the termination region in the direction from the active region to the termination region, the first semiconductor region and the second semiconductor region being disposed alternately.. .
07/02/15
20150187867
new patent

Independent gate vertical finfet structure


A semiconductor device includes a substrate extending in a first direction to define a substrate length and a second direction perpendicular to the first direction to define a substrate width. A first semiconductor fin is formed on an upper surface of the substrate.
07/02/15
20150187863
new patent

Integrated circuits including a resistance element and gate-last techniques for forming the integrated circuits


Integrated circuits with a resistance element and gate-last techniques for forming the integrated circuits are provided. An exemplary technique includes providing a semiconductor substrate that includes a shallow trench isolation (sti) structure disposed therein.
07/02/15
20150187855
new patent

Semiconductor device


A display device that includes a first flexible substrate, a first bonding layer over the first flexible substrate, a first insulating film over the first bonding layer, a first element layer over the first insulating film, a second element layer over the first element layer, a second insulating film over the second element layer, a second bonding layer over the second insulating film, and a second flexible substrate over the second bonding layer is provided. The first element layer includes a pixel portion and a circuit portion.
07/02/15
20150187853
new patent

Display device and manufacturing method thereof


A display device includes an organic light emitting element and a capacitor connected to the a thin film transistor. The transistor includes a semiconductor layer uniformly disposed on an entire area of a substrate.
07/02/15
20150187831
new patent

Solid state imaging device


According to one embodiment, a solid state imaging device includes a semiconductor substrate, a photodiode formed in the semiconductor substrate, a first insulating film having a first refractive index, and disposed on a surface of the semiconductor substrate, a second insulating film having a second refractive index higher than the first refractive index, and formed on the first insulating film above the photodiode, a third insulating film having a third refractive index higher than the second refractive index, and formed on the second insulating film above the photodiode, and a micro lens provided above the photodiode.. .
07/02/15
20150187827
new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes an epitaxial layer including a first surface and a silicon layer disposed on the first surface and including a second surface opposite to the first surface, wherein the silicon layer includes a plurality of pillars on the second surface, a portion of the plurality of pillars on a predetermined portion of the second surface are in substantially same dimension, each of the plurality of pillars on the predetermined portion of the second surface stands substantially orthogonal to the second surface, the plurality of pillars are configured for absorbing an electromagnetic radiation of a predetermined wavelength projected from the epitaxial layer and generating an electrical energy in response to the absorption of the electromagnetic radiation.. .
07/02/15
20150187824
new patent

Semiconductor device


Disclosed is a semiconductor device having a first transistor and a second transistor over the first transistor. The first transistor includes a first semiconductor, and the second transistor includes an oxide semiconductor that is different from the first semiconductor.
07/02/15
20150187823
new patent

Semiconductor device


A semiconductor device that is suitable for miniaturization is provided. Alternatively, a highly reliable semiconductor device is provided.
07/02/15
20150187819
new patent

Semiconductor device


A semiconductor device having a high aperture ratio and including a capacitor capable of increasing the charge capacity is provided. A semiconductor device includes a transistor over a substrate, a first light-transmitting conductive film over the substrate, an oxide insulating film covering the transistor and having an opening over the first light-transmitting conductive film, a nitride insulating film over the oxide insulating film and in contact with the first light-transmitting conductive film in the opening, a second light-transmitting conductive film connected to the transistor and having a depressed portion in the opening, and an organic resin film with which the depressed portion of the second light-transmitting conductive film is filled..
07/02/15
20150187818
new patent

Light-emitting device


A light-emitting device capable of suppressing variation in luminance among pixels is provided. A light-emitting device includes a pixel and first and second circuits.
07/02/15
20150187816
new patent

Finfet with reduced capacitance


An finfet structure including a plurality of fins etched from a semiconductor substrate, a plurality of gates above and perpendicular to the plurality of fins, each comprising a pair of spacers on opposing sides of the gates, and a gap fill material above the semiconductor substrate, below the gate, and between the plurality of fins, wherein the gate separates the gap fill material from each of the plurality of fins.. .
07/02/15
20150187815
new patent

Multi-fin finfets with merged-fin source/drains and replacement gates


A semiconductor structure including semiconductor fins, a gate over a middle portion of the semiconductor fins, and faceted semiconductor regions outside of the gate separated from gaps may be formed. The semiconductor structure may be formed by forming fins on a semiconductor substrate where each fin has a pair of sidewalls aligned parallel to the length of the fin, growing dummy semiconductor regions on the sidewalls of the fins, forming a sacrificial gate that covers a center portion of the fins and the dummy semiconductor regions, removing portions of the dummy semiconductor regions not covered by the sacrificial gate, and growing faceted semiconductor regions on the sidewalls of the portions of the fins not covered by the sacrificial gate.
07/02/15
20150187814
new patent

Semiconductor device


A semiconductor device that is suitable for miniaturization is provided. A semiconductor device including a first element, a first insulator over the first element, a first barrier film over the first insulator, a first conductor over the first barrier film, a second barrier film over the first conductor, a second insulator over the second barrier film, and a semiconductor over the second insulator is provided.
07/02/15
20150187813
new patent

Thin film transistor array panel and manufacturing the same


A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer.
07/02/15
20150187812
new patent

Semiconductor device, display device, and electronic appliance


In case the size of the transistor is enlarged, power consumption of the transistor is increased. Thus, the present invention provides a display device capable of preventing a current from flowing to a display element in signal writing operation without varying potentials of power source lines for supplying a current to the display element per row.
07/02/15
20150187805
new patent

Thin film transistor substrate and liquid crystal display device using the same


A thin film transistor substrate and a liquid crystal display device are disclosed. The thin film transistor substrate comprises gate lines arranged on a substrate in a first direction and sub gate lines connected with the gate lines; data lines arranged on the substrate in a second direction to define a pixel including a first pixel and a second pixel, together with the gate lines; a semiconductor layer formed overlapping with each of the gate lines, the sub gate lines and the data lines and connected with the date lines; and a pixel electrode connected with the semiconductor layer.
07/02/15
20150187798
new patent

Display device and repair method thereof


A display device includes: a substrate; a gate electrode on the substrate; a first electrode separated from the gate electrode; a gate insulating layer on the gate electrode and the first electrode; a semiconductor on the gate electrode; a source electrode and a drain electrode on the semiconductor and separated from each other; a passivation layer on the source electrode and the drain electrode; a first contact hole defined in the passivation layer and exposing the drain electrode; a second contact hole defined in the passivation layer and exposing the first electrode; a pixel electrode on the passivation layer and connected to the drain electrode through the first contact hole; and a second electrode on the passivation layer and connected to the first electrode through the second contact hole. The first electrode overlaps the drain electrode..
07/02/15
20150187796
new patent

Polysilicon tft device and manufacturing method thereof


The present invention discloses a polysilicon tft device and the manufacturing method thereof. The polysilicon tft device comprises: a scanning line and a data line arranged alternately; a semiconductor layer electrically connected with the scanning line and the data line; and a pixel electrode electrically connected with the semiconductor layer.
07/02/15
20150187795
new patent

Semiconductor device and manufacturing semiconductor device


An insulated gate type switching element which can control a gate potential appropriately in accordance with a potential of a rear surface electrode is provided. A semiconductor device has a semiconductor substrate, a front surface electrode on a front surface of the semiconductor substrate, and a rear surface electrode on a rear surface thereof.
07/02/15
20150187794
new patent

Method for forming deep trench isolation for rf devices on soi


A semiconductor device includes a silicon-on-insulator (soi) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a soi substrate having shallow trench isolations (stis) and transistors formed within and on the second semiconductor substrate, respectively.
07/02/15
20150187793
new patent

Semiconductor device, related manufacturing method, and related electronic device


A semiconductor device may include a first dielectric layer. The semiconductor device may further include a second dielectric layer overlapping the first dielectric layer and having a closed cavity structure.
07/02/15
20150187792
new patent

Nonvolatile semiconductor memory element, nonvolatile semiconductor memory, and operating nonvolatile semiconductor memory element


According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.. .
07/02/15
20150187791
new patent

Methods of fabricating three-dimensional semiconductor devices


A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.. .
07/02/15
20150187790
new patent

Methods of forming vertical type semiconductor devices including oxidation target layers


A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps.
07/02/15
20150187789
new patent

Semiconductor device and manufacturing the same


A semiconductor device that includes a plurality of first conductive patterns stacked over a substrate, dummy patterns formed in the first conductive patterns, respectively, first barrier patterns each surrounding the respective first conductive patterns and partially interposed between the respective first conductive patterns and the respective dummy patterns, second barrier patterns each surrounding the respective first barrier patterns and the respective dummy patterns, a second conductive pattern located over or under the first conductive patterns, and a third barrier pattern surrounding the second conductive pattern, wherein the second conductive pattern has a greater thickness than the first conductive patterns.. .
07/02/15
20150187783
new patent

Semiconductor device and fabricating method thereof


A semiconductor device and a method for fabricating the semiconductor device are provided in the present disclosure. The semiconductor device includes a substrate including a first active region and a second active region divided by a shallow trench isolation (sti) region, a protective structure located on the sti region, a first semiconductor structure on the first active region, and a second semiconductor structure on the second active region of the substrate including a high-k dielectric layer and a metal gate layer over the high-k dielectric layer.
07/02/15
20150187782
new patent

Semiconductor device


Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory.
07/02/15
20150187779
new patent

Semiconductor device and manufacturing method thereof


An object is to provide an antifuse with little power consumption at the time of writing. The antifuse is used for a memory element in a read-only memory device.
07/02/15
20150187778
new patent

Semiconductor device


A semiconductor storage device capable of performing low-voltage operation, reducing standby current, and decreasing memory size is provided. The semiconductor storage device is a semiconductor device including first to fourth transistors and a capacitor.
07/02/15
20150187777
new patent

Semiconductor arrangement with capacitor and fabricating the same


A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor.
07/02/15
20150187776
new patent

Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making


An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link..
07/02/15
20150187775
new patent

Semiconductor device and driving the same


A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line.
07/02/15
20150187774
new patent

Fin-type semiconductor device


An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin-type semiconductor device comprises means for providing a first fin-type conduction channel having first and second regions, means for providing a second fin-type conduction channel having a fourth region above a third region, and means for shielding current leakage coupled to at least one of the first region and the third region.
07/02/15
20150187773
new patent

High mobility transistors


An integrated circuit containing an n-channel finfet and a p-channel finfet has a dielectric layer over a silicon substrate. The fins of the finfets have semiconductor materials with higher mobilities than silicon.
07/02/15
20150187769
new patent

Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods


A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type.
07/02/15
20150187767
new patent

Semiconductor structures providing electrical isolation


Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins.
07/02/15
20150187766
new patent

Multi-gate finfet semiconductor device with flexible design width


A semiconductor device includes a substrate extending in a first direction to define a substrate length and a second direction perpendicular to the first direction to define a substrate width. A first semiconductor fin is formed on an upper surface of the substrate.
07/02/15
20150187765
new patent

Semiconductor device having high-k gate dielectric above an sti region


By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances.
07/02/15
20150187763
new patent

Semiconductor devices and methods of fabricating semiconductor devices


semiconductor devices are provided. A semiconductor device includes a substrate including first through fourth areas.
07/02/15
20150187762
new patent

Semiconductor device with a multiple nanowire channel structure and methods of variably connecting such nanowires for current density modulation


A nanowire device is disclosed that includes first and second nanowires, a gate structure positioned around a portion of the first and second nanowires and a phase change material surrounding at least a portion of the first nanowire in the source/drain regions of the device but not surrounding the second nanowire in the source/drain regions.. .
07/02/15
20150187761
new patent

Method for manufacturing a semiconductor device and a semiconductor device


A semiconductor device is formed by forming: a transistor in a semiconductor substrate having a main surface; a source region and a drain region; and a channel region and a drift zone between the source region and the drain region. The source and drain regions are arranged along a first direction parallel to the main surface.
07/02/15
20150187756
new patent

Semiconductor device with metal silicide blocking region and manufacturing the same


Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a gate stack on a semiconductor substrate.
07/02/15
20150187754
new patent

Ballast resistor for super-high-voltage devices


An integrated circuit including a well region, a plurality of semiconductor regions implanted in the well region, and a plurality of polysilicon regions arranged on each of the plurality of semiconductor regions. The well region has a first doping level.
07/02/15
20150187751
new patent

Amplifier voltage limiting using punch-through effect


Disclosed herein are systems and method for voltage clamping in semiconductor circuits using through-silicon via (tsv) positioning. A semiconductor die is disclosed that includes a silicon substrate, a bipolar transistor having collector, emitter, base and sub-collector regions disposed on the substrate, and a through-silicon via (tsv) positioned within 35 μm of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level..
07/02/15
20150187749
new patent

Silicon-controlled rectifier electrostatic discharge protection device and forming the same


Various embodiments provide scr esd protection devices and methods for forming the same. An exemplary device includes a semiconductor substrate having a p-type well region, an n-type well region adjacent to the p-type well region, a first p-type doped region and a first n-type doped region in the p-type well region, and a second n-type doped region and a second p-type doped region in the n-type well region.
07/02/15
20150187748
new patent

Electrostatic discharge shunt for semiconductor devices


A semiconductor device or an integrated circuit formed on a substrate with shunt disposed on the substrate in parallel with the device or circuit and designed to form a closed circuit or discharge path when the device is subjected to an electrostatic discharge pulse.. .
07/02/15
20150187746
new patent

Package on package devices and methods of packaging semiconductor dies


A method of packaging semiconductor dies may include: coupling a first die to a first substrate; forming a plurality of first portions of a plurality of metal pillars on a surface of the first substrate; forming a second portion of the plurality of metal pillars over each of the plurality of first portions of the plurality of metal pillars; forming a protection layer over sidewalls of each of the plurality of first portions and second portions of the plurality of metal pillars; coupling a second die to a second substrate; and coupling the plurality of metal pillars to the second substrate.. .
07/02/15
20150187745
new patent

Solder pillars for embedding semiconductor die


A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate.
07/02/15
20150187744
new patent

3d semiconductor initializing channels


A semiconductor apparatus includes a plurality of stack dies which are formed with a predetermined number of channels. The semiconductor apparatus also includes a base die configured to initialize a channel not electrically coupled with the stack dies..
07/02/15
20150187742
new patent

Semiconductor package, fabrication method therefor, and package-on package


Provided is a method of manufacturing a semiconductor package including a through wiring having precision and a low process defect. The semiconductor package includes an insulating substrate including a first through portion and a second through portion; a through wiring which fills the first through portion, and is located to penetrate the insulating substrate; a semiconductor chip which is located in the second through portion, and is electrically connected to the through wiring; a molding member molding the semiconductor chip and the insulating substrate; and a re-wiring pattern layer which is located at a lower side of the insulating substrate, and electrically connects the through wiring and the semiconductor chip..
07/02/15
20150187738
new patent

Package assembly and manufacturing the same


A package assembly and a method for manufacturing the same are disclosed. The package assembly includes semiconductor chips, encapsulant layers, and a chip carrier.
07/02/15
20150187737
new patent

Molding package assembly and molding material


A molding package assembly is provided, which includes a substrate and first and second molding packages stacked on the substrate. Each of the first and second molding packages has a semiconductor element, an anti-warping structure disposed around a periphery of the semiconductor element, a molding material encapsulating the semiconductor element and the anti-warping structure, and a protection layer formed on the semiconductor element, the molding material and the anti-warping structure.
07/02/15
20150187736
new patent

Semiconductor device and related manufacturing method


A method for manufacturing a semiconductor device may include providing a first dielectric layer and a first set of conductive pads on a first substrate. Each conductive pad of the first set of conductive pads may be positioned between portions of the first dielectric layer.
07/02/15
20150187734
new patent

Packages with die stack including exposed molding underfill


A method includes bonding a first device die onto a top surface of a package substrate, and performing an expose molding on the first device die and the package substrate. At least a lower portion of the first device die is molded in a molding material.
07/02/15
20150187733
new patent

Combination of tsv and back side wiring in 3d integration


The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3d integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (tsvs) to electrically connect the front side of a first integrated circuit (ic) chip to large back side wiring on the back side of the first ic chip and inter-wafer tsvs to electrically connect the first ic chip to a second ic chip.. .
07/02/15
20150187732
new patent

Electronic control device


In an electronic control device, semiconductor modules are disposed in a power region of a substrate, and on a surface of a substrate adjacent to a housing to radiate heat from rear surfaces to the housing through a heat radiation layer. Therefore, a heat radiation performance improves.
07/02/15
20150187729
new patent

Wire stitch bond having strengthened heel


A semiconductor chip (1100) assembled on a substrate (1110), the chip having bond pads (1102) and the substrate having contact pads (1111). Wires (1101) form arches to connect electrically the chip and the substrate, the wires forming first bonds (1103, e.g.
07/02/15
20150187728
new patent

Emiconductor device with die top power connections


In a packaged semiconductor device, a die is mounted on a substrate having power connection pads. An exterior (e.g., top) surface of the die has power bond pads and distributed power feed pads.
07/02/15
20150187726
new patent

Semiconductor package and manufacturing the same


There are provided a semiconductor package and a method for manufacturing the same. The semiconductor package according to an exemplary embodiment of the present disclosure includes: a board on which an insulating layer and a plurality of circuit patterns are formed; first bonding parts formed on portions of an upper portion of the circuit pattern; second bonding parts formed on portions of the upper portion of the circuit pattern; a first semiconductor device mounted on the board; a first connecting member of electrically connecting the first bonding part and the first semiconductor device to each other; a second connecting member having one surface bonded to the second bonding part and the other end exposed to the outside; and an oxide film formed on the remaining portions except for the first bonding part and the second bonding part..
07/02/15
20150187722
new patent

Semiconductor package and fabrication method thereof


A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.. .
07/02/15
20150187720
new patent

Method of manufacturing semiconductor device and semiconductor device


To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step.
07/02/15
20150187717
new patent

Semiconductor device


In one embodiment, a semiconductor package includes a first semiconductor die having a first surface facing upwardly to expose a bond pad, a second semiconductor die having a first surface facing downwardly to expose a bond pad and disposed to be offset with the first surface of the first semiconductor die, and an encapsulant encapsulating the first semiconductor die and the second semiconductor die together. Throughholes are disposed in the encapsulant adjacent the bond pad of the first semiconductor die and adjacent the bond pad of the second semiconductor die..
07/02/15
20150187716
new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a first substrate including a plurality of first pads disposed on a first surface of the first substrate, a second substrate including a plurality of second pads disposed on a second surface of the substrate, a plurality of conductive bumps bonded the plurality of first pads with the plurality of second pads correspondingly, a solder bracing material disposed on the first surface and surrounded the plurality of conductive bumps, an underfill material surrounded the plurality of conductive bumps and disposed between the solder bracing material and the second surface, and a rough interface between the solder bracing material and the underfill material; wherein the rough interface includes a plurality of protruded portions and a plurality of recessed portions.. .
07/02/15
20150187715
new patent

Semiconductor device having bucket-shaped under-bump metallizaton and forming same


A semiconductor device includes a first under-bump metallization (ubm) layer disposed over a bond pad, a dielectric layer above an interconnect layer having a via exposing at least a portion of the first ubm layer. A second ubm layer is disposed above the first ubm layer and forms a ubm bucket over the via.
07/02/15
20150187714
new patent

Integrated circuits including copper pillar structures and methods for fabricating the same


Integrated circuits including copper pillar structures and methods for fabricating the same are disclosed. In one exemplary embodiment, an integrated circuit includes a last metal layer and a passivation layer disposed over the last metal layer, both the last metal and passivation layers being disposed over an integrated circuit active device on a semiconductor substrate.
07/02/15
20150187710
new patent

Semiconductor device and method comprising thickened redistribution layers


A method of making a semiconductor package can comprise forming a plurality of thick redistribution layer (rdl) traces over active surfaces of a plurality of semiconductor die that are electrically connected to contact pads on the plurality of semiconductor die, singulating the plurality of semiconductor die comprising the plurality of thick rdl traces, mounting the singulated plurality of semiconductor die over a temporary carrier with the active surfaces of the plurality of semiconductor die oriented away from the temporary carrier, disposing encapsulant material over the active surfaces and at least four side surfaces of each of the plurality of semiconductor die, over the plurality of thick rdl traces, and over the temporary carrier, forming a via through the encapsulant material to expose at least one of the plurality of thickened rdl traces with respect to the encapsulant material, removing the temporary carrier, and singulating the plurality of semiconductor die.. .
07/02/15
20150187706
new patent

Semiconductor device having metal lines with slits


A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit..
07/02/15
20150187705
new patent

Semiconductor package having emi shielding and fabricating the same


A semiconductor package includes a dielectric layer in which a chip is embedded, interconnection parts disposed on a first surface of the dielectric layer, through connectors each of which penetrates a portion of the dielectric layer over the chip to electrically couple the chip to a corresponding one of the interconnection parts, a shielding plate covering a second surface of the dielectric layer that is opposite to the first surface, and a shielding encapsulation part connected to one of the interconnection parts and covering sidewalls of the dielectric layer. The shielding encapsulation part includes a portion contacting the shielding plate..
07/02/15
20150187704
new patent

Method of joining semiconductor substrate


A method of joining semiconductor substrates, which may include: forming an alignment key on a first semiconductor substrate; forming an insulating layer on the first semiconductor substrate and the alignment key; forming a first metal layer pattern and a second metal layer pattern on the insulating layer; forming a first protrusion and a second protrusion, and an alignment recess positioned between the first protrusion and the second protrusion on a second semiconductor substrate; forming a third metal layer pattern and a fourth metal layer pattern on the first protrusion and the second protrusion, respectively; and joining the first semiconductor substrate and the second semiconductor substrate, in which the alignment key is positioned at the alignment recess when the first semiconductor substrate and the second semiconductor substrate are joined, is provided.. .
07/02/15
20150187701
new patent

Semiconductor devices and methods of manufacture thereof


semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first semiconductor chip including a first substrate and a first conductive feature formed over the first substrate, and a second semiconductor chip bonded to the first semiconductor chip.
07/02/15
20150187700
new patent

Reliable interconnects


semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate prepared with intermediate dielectric layer having interconnect levels.
07/02/15
20150187699
new patent

Semiconductor devices and methods of fabricating the same


semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns.
07/02/15
20150187698
new patent

Semiconductor apparatus and an improved structure for power lines


A semiconductor apparatus includes a first power supply pad configured to supply a first power; a second power supply pad configured to supply a second power; a first power line configured to be directly electrically coupled to the first power supply pad; and a second power line configured to be directly electrically coupled to the second power supply pad.. .
07/02/15
20150187697
new patent

Interconnect structure for semiconductor devices


An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer.
07/02/15
20150187694
new patent

Semiconductor structure and forming the same


A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a stacked structure, a dielectric layer, a conductive structure, a dielectric structure and a conductive plug.
07/02/15
20150187693
new patent

Semiconductor device


An embodiment of the invention relates to a semiconductor device comprising: first and second electrodes comprising first and second busbars respectively that decrease in cross section in opposite directions; and a plurality of interleaving first and second conducting fingers that extend from the first and second busbars respectively.. .
07/02/15
20150187689
new patent

Semiconductor device


The semiconductor device includes an insulating substrate on which is mounted a main circuit part including a semiconductor chip, a printed substrate wherein a conductive connection member connected to the semiconductor chip is disposed on the surface opposing the insulating substrate, a first sealing member that seals so as to enclose the semiconductor chip between the opposing surfaces of the insulating substrate and printed substrate, and a second sealing member that covers the whole excepting a bottom portion of the insulating substrate, the semiconductor device having sealing region regulation rod portions disposed in an outer peripheral portion of a sealing region of the first sealing member and connected between the insulating substrate and printed substrate, wherein the heat resistance temperature of the first sealing member is set to be higher than the heat resistance temperature of the second sealing member.. .
07/02/15
20150187687
new patent

Semiconductor device


A trench portion (trench or groove) is formed at each of four corner portions of a chip bonding region having a quadrangular planar shape smaller than an outer-shape size of a die pad included in a semiconductor device. Each trench is formed along a direction of intersecting with a diagonal line which connects between the corner portions where the trench portions are arranged, and both ends of each trench portion are extended to an outside of the chip bonding region.
07/02/15
20150187686
new patent

Semiconductor device


There is provided a semiconductor device that includes a circuit board, a semiconductor element mounted to the circuit board, a control signal terminal disposed on the opposite side of the semiconductor element from the circuit board, and a bonding wire connecting the semiconductor element and the control signal terminal.. .
07/02/15
20150187684
new patent

Semiconductor package


There is provided a semiconductor package capable of preventing a lead frame from being separated from a molded portion during a manufacturing process. The semiconductor package according to an exemplary embodiment in the present disclosure includes: at least one electronic device; a lead frame including a plurality of leads electrically connected to the electronic device; a lead connecting member coupled to at least one of the leads; and a molded portion sealing the electronic device and the lead connecting member..
07/02/15
20150187683
new patent

Qfn package and forming qfn package


The present invention relates to a semiconductor package and a method for forming a semiconductor package. A lead frame adapted to a semiconductor package includes a first carrier, an adjacent second carrier, a first array of leads, and a second array of leads.
07/02/15
20150187682
new patent

Semiconductor device


A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source ic chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires.
07/02/15
20150187680
new patent

Semiconductor apparatus, manufacturing method thereof and testing method thereof


A semiconductor apparatus includes one or more semiconductor chips. Each semiconductor chip includes a semiconductor substrate formed with a through-silicon via, and a bottom wiring layer with a first dielectric layer formed on a bottom of the semiconductor substrate.
07/02/15
20150187678
new patent

Power semiconductor device


A power semiconductor device may include: a first conductivity-type first semiconductor layer; a second conductivity-type second semiconductor layer disposed above the first semiconductor layer; and a heat dissipation trench disposed to penetrate from an upper surface of the second semiconductor layer into a portion of the second semiconductor layer and having an insulating layer disposed on a surface thereof.. .
07/02/15
20150187674
new patent

Semiconductor device


A surface of a power semiconductor chip, mounted within a power semiconductor module and not being opposed to a wiring thin film, and a surface of a bonding wire are sealed with a resin that does not contain a thermally-conductive filler, and the resin that does not contain a thermally-conductive filler is sealed with a resin that contains a thermally-conductive filler.. .
07/02/15
20150187673
new patent

Reduced stress tsv and interposer structures


A microelectronic component with circuitry includes a substrate (possibly semiconductor) having an opening in a top surface. The circuitry includes a conductive via (possibly metal) in the opening.
07/02/15
20150187672
new patent

Metal oxide semiconductor structure


A metal oxide semiconductor structure, the structure including: a substrate; a gate electrode, deposited on the substrate; a gate insulation layer, deposited over the gate electrode and the substrate; an igzo layer, deposited on the gate insulation layer and functioning as a channel; a source electrode, deposited on the gate insulation layer and being at one side of the igzo layer; a drain electrode, deposited on the gate insulation layer and being at another side of the igzo layer; a first passivation layer, deposited over the source electrode, the igzo layer, and the drain electrode; a second passivation layer, deposited over the first passivation layer; and an opaque resin layer, deposited over the source electrode, the second passivation layer, and the drain electrode.. .
07/02/15
20150187671
new patent

Semiconductor device


A semiconductor device according to the invention includes an insulating substrate including an insulating plate, a circuit pattern that is formed on a front surface of the insulating plate, and a radiator plate that is fixed to a rear surface of the insulating plate, a semiconductor chip that is fixed to the circuit pattern, an external lead terminal that is connected to a surface electrode of the semiconductor chip through a wiring line, a molding resin that covers the insulating substrate, the semiconductor chip, the wiring line, and the external lead terminal such that a rear surface of the radiator plate and a portion of the external lead terminal are exposed, and an anchor layer including a stripe-shaped concave portion which is formed in the circuit pattern by laser beam irradiation.. .
07/02/15
20150187670
new patent

Semiconductor device, manufacturing the same, and rinsing liquid


A method for manufacturing a semiconductor device including: a process of applying a sealing composition for a semiconductor to a semiconductor substrate, to form a sealing layer for a semiconductor on at least the bottom face and the side face of a recess portion of an interlayer insulating layer, the sealing composition including a polymer having a cationic functional group and a weight average molecular weight of from 2,000 to 1,000,000, each of the content of sodium and the content of potassium in the sealing composition being 10 ppb by mass or less on an elemental basis; and a process of subjecting a surface of the semiconductor substrate at a side at which the sealing layer has been formed to heat treatment of from 200° c. To 425° c., to remove at least a part of the sealing layer..
07/02/15
20150187669
new patent

Semiconductor device


A miniaturized semiconductor device includes a frame body having an opening region formed in a central portion, an insulating substrate which is provided in the opening region of the frame body and on which semiconductor chips are mounted, lead portions, each including an inclined portion that is at least partially exposed to the opening region formed in the frame body and extends so as to be inclined with respect to an end surface forming the opening region, and a bonding wire that is bonded between the lead portion and the semiconductor chip by ultrasonic bonding.. .
07/02/15
20150187668
new patent

Semiconductor device


A semiconductor device includes an insulating substrate on which semiconductor elements are mounted and a surrounding case in which the insulating substrate is housed. Two terminal conductors, both ends of each of which are fixed in sidewalls of the surrounding case, are provided between the sidewalls, and connection terminals protruding toward the insulating substrate side are provided on the respective terminal conductors.
07/02/15
20150187667
new patent

Inline measurement of through-silicon via depth


A through-silicon via (tsv) capacitive test structure and method of determining tsv depth based on capacitance is disclosed. The tsv capacitive test structure is formed from a plurality of tsv bars that are evenly spaced.
07/02/15
20150187664
new patent

High productivity combinatorial testing of multiple work function materials on the same semiconductor substrate


Provided are methods of high productivity combinatorial (hpc) screening of work function materials. Multiple test materials may be deposited as separate blanket layers on the same substrate while still forming individual interfaces with a common base layer.
07/02/15
20150187663
new patent

Systems and methods of local focus error compensation for semiconductor processes


A system and method of compensating for local focus errors in a semiconductor process. The method includes providing a reticle and applying, at a first portion of the reticle, a step height based on an estimated local focus error for a first portion of a wafer corresponding to the first portion of the reticle.
07/02/15
20150187661
new patent

Dual layer hardmask for embedded epi growth


A process for forming an integrated circuit with an embedded epitaxially grown semiconductor using an epi blocking bilayer. The epi blocking bilayer comprised of a two different materials that may be etched selectively with respect to each other such as silicon nitride and silicon dioxide..
07/02/15
20150187660
new patent

Balancing asymmetric spacers


An issue arises when manufacturing semiconductor circuits including pfets with an sige alloy embedded in their source/drain regions and nfets without any embedded sige alloy. In this case, the thickness of the nfet spacers is considerably greater than that of the pfet spacers.
07/02/15
20150187657
new patent

Method of manufacturing a semiconductor device


In an n-channel hk/mg transistor including: a gate insulating film made of a first high dielectric film containing la and hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains hf but whose la content is smaller than a la content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film.. .
07/02/15
20150187654
new patent

Method of manufacturing a semiconductor device with buried channel/body zone and semiconductor device


A semiconductor device includes a source zone of a first conductivity type formed in a first electrode fin that extends from a first surface into a semiconductor portion. A drain region of the first conductivity type is formed in a second electrode fin that extends from the first surface into the semiconductor portion.
07/02/15
20150187652
new patent

Method for producing a composite wafer and a producing a semiconductor crystal layer forming wafer


The (a) to the (c) are repeated by using the forming wafer separated in the (c).. .
07/02/15
20150187651
new patent

Semiconductor device and manufacturing the same


A method of manufacturing a semiconductor device includes: a step of forming an inorganic insulating film and an organic insulating film on one surface of a first substrate; a step of forming an opening portion by dry-etching a laminated film of them; a step of forming a bump electrode inside the opening portion; and a step (bonding step) of bonding the one surface of the first substrate having a bump electrode formed thereon and one surface of a second substrate having a bump electrode formed thereon to each other. A surface treatment on the inorganic insulating film is performed subsequent to the step of forming the opening portion but prior to the bonding step.
07/02/15
20150187648
new patent

Semiconductor device and fabricating the same


A semiconductor device and a method for fabricating the same are disclosed, which can prevent migration of copper (cu) ion when forming a through silicon via (tsv). The semiconductor device includes a through silicon via (tsv) formed to pass through a semiconductor substrate; an oxide film located at a lower sidewall of the tsv; and a first prevention film formed to cover an upper portion of the tsv, an upper sidewall of the tsv, and an upper surface of the oxide film..
07/02/15
20150187646
new patent

Manufacturing semiconductor device and semiconductor device


According to one embodiment, a first core pattern is formed in a wiring portion on a process target film and a second core pattern, which is led out from the first core pattern and includes an opening, is formed in a leading portion on the process target film, a sidewall pattern is formed along an outer periphery of the first core pattern and the second core pattern and a sidewall dummy pattern is formed along an inner periphery of the opening of the second core pattern, the first core pattern and the second core pattern are removed, and the process target film is processed to transfer the sidewall pattern and the sidewall dummy pattern.. .
07/02/15
20150187645
new patent

Semiconductor device having non-planar interface between a plug layer and a contact layer


A semiconductor device is provided, in which it becomes easy to reliably couple a plug conductive layer and a wiring layer located over the plug conductive layer to each other and falling of the wiring can be suppressed. The plug conductive layer contacts a source/drain region formed over a major surface of the semiconductor substrate.
07/02/15
20150187644
new patent

Semiconductor device with air gap and fabricating the same


A method of fabricating a semiconductor device and a semiconductor device formed by the method. The method includes form a stack conductive structure by stacking a first conductive pattern and an insulation pattern over a substrate; forming a sacrificial pattern over sidewalls of the stack conductive structure; forming a second conductive pattern having a recessed surface lower than a top surface of the stack conductive structure; forming a sacrificial spacer to expose sidewalls of the insulation pattern by removing an upper portion of the sacrificial pattern; reducing a width of the exposed portion of the insulation patters; forming a capping spacer to cap the sidewalls of the insulation pattern having the reduced width over the sacrificial spacer; and forming an air gap between the first conductive pattern and the second conductive pattern by converting the sacrificial spacer to volatile byproducts.
07/02/15
20150187643
new patent

Depression filling method and processing apparatus


A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor substrate includes: forming an impurity-doped first semiconductor layer along a wall surface which defines the depression; forming, on the first semiconductor layer, a second semiconductor layer which is lower in impurity concentration than the first semiconductor layer and which is smaller in thickness than the first semiconductor layer; annealing the workpiece to form an epitaxial region at the bottom of the depression corresponding to crystals of the semiconductor substrate from the first semiconductor layer and the second semiconductor layer; and etching the first amorphous semiconductor region and the second amorphous semiconductor region.. .
07/02/15
20150187642
new patent

Double-sided segmented line architecture in 3d integration


Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3d) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (tsvs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an ic chip and connected to a second word line architecture formed on a back side of the ic chip through intra-wafer, tsvs, thereby relocating required wiring to the back side of the ic chip..
07/02/15
20150187641
new patent

Integrated circuits with improved gap fill dielectric and methods for fabricating same


Integrated circuits with reduced shorting and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a gap fill dielectric overlying a semiconductor substrate.
07/02/15
20150187639
new patent

Silicon-on-insulator substrate and manufacturing thereof


A method of manufacturing a silicon-on-insulator (soi) substrate is provided. The method includes forming an island-shaped insulating layer on a first surface of a first semiconductor substrate in a first region, forming a silicon epitaxial layer on the first surface of the first semiconductor substrate so as to cover the island-shaped insulating layer, forming a trench by etching the silicon epitaxial layer so as to expose the island-shaped insulating layer, and forming a first insulating adhesive layer on the silicon epitaxial layer and the island-shaped insulating layer so as to fill the trench..
07/02/15
20150187636
new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a first semiconductor chip comprising a first metallic structure, a top surface, and a bottom surface, a second semiconductor chip comprising a second metallic structure, wherein the second semiconductor chip is bonded with the first semiconductor chip on the bottom surface, a conductive material connecting the first metallic structure and the second metallic structure, wherein a portion of the conductive material is inside the first semiconductor chip and the second semiconductor chip, and a dielectric layer disposed surrounding the portion of the conductive material.. .
07/02/15
20150187634
new patent

Mechanisms for forming finfets with different fin heights


Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a first fin partially surrounded by a first isolation structure and protruding through a top surface thereof.
07/02/15
20150187633
new patent

Semiconductor device and fabrication method


semiconductor devices and fabrication methods are provided. First metal layers are provided in a substrate including a first region and a second region.
07/02/15
20150187630
new patent

Support ring with masked edge


A support ring for semiconductor processing is provided. The support ring includes a ring shaped body defined by an inner edge and an outer edge.
07/02/15
20150187620
new patent

Water carrier having thermal cover for chemical vapor deposition systems


The invention relates generally to semiconductor fabrication technology and, more particularly, to chemical vapor deposition (cvd) processing and associated apparatus for addressing temperature non-uniformities on semiconductor wafer surfaces. Embodiments include a wafer carrier for use in a system for growing epitaxial layers on one or more wafers by cvd, the wafer carrier comprising a top plate and base plate which function coordinately to reduce temperature variability caused during cvd processing..
07/02/15
20150187615
new patent

Component of a plasma processing apparatus including an electrically conductive and nonmagnetic cold sprayed coating


A semiconductor plasma processing apparatus used to process semiconductor components comprises a plasma processing chamber, a process gas source in fluid communication with the plasma processing chamber for supplying a process gas into the plasma processing chamber, a rf energy source adapted to energize the process gas into the plasma state in the plasma processing chamber, and a vacuum port for exhausting process gas from the plasma processing chamber. The semiconductor plasma processing apparatus further comprises at least one component wherein the component has a body which has a relative magnetic permeability of about 70,000 or greater and a cold sprayed electrically conductive and nonmagnetic coating on a surface of the body wherein the coating has a thickness greater than the skin depth of a rf current configured to flow therethrough during plasma processing..
07/02/15
20150187614
new patent

Edge seal for lower electrode assembly


A lower electrode assembly useful for supporting a semiconductor substrate in a plasma processing chamber includes a temperature controlled lower base plate, an upper plate, a mounting groove surrounding a bond layer and an edge seal comprising a ring compressed in the groove. A gas source supplies inert gas to the groove and maintains the inert gas at a pressure of 100 mtorr to 100 torr in the groove..
07/02/15
20150187611
new patent

Substrate processing system, manufacturing semiconductor device and non-transitory computer-readable recording medium


A substrate processing system includes a plurality of processing chambers accommodating substrates, a processing gas supply system configured to supply a processing gas sequentially into the plurality of processing chambers, a reactive gas supply system configured to supply an activated reactive gas sequentially into the plurality of processing chambers, a buffer tank installed at the processing gas supply system, and a control unit configured to control the processing gas supply system and the reactive gas supply system such that a time period of supplying the reactive gas into one of the plurality of processing chambers is equal to a sum of a time period of supplying the processing gas into the one of the plurality of processing chambers and a time period of supplying the processing gas into the buffer tank, and the processing gas and the reactive gas are alternately supplied into the plurality of processing chambers.. .
07/02/15
20150187610
new patent

Substrate processing apparatus, manufacturing semiconductor device, and non-transitory computer-readable recording medium


A substrate processing apparatus includes a common pipe connected to a process container wherethrough a first and second process gases flow; a buffer unit connected to an upstream side of the common pipe and having a width greater than a diameter of the common pipe; a first supply pipe wherethrough the first process gas flows, connected to a first surface of the buffer unit where the common pipe is connected or a second surface of the buffer unit opposite to the first surface; and a second supply pipe wherethrough the second process gas flows, connected to the first or second surface. Each of the first and second supply pipes is installed outer than the common pipe, and a distance between the first and second surfaces is shorter than a distance between a center axis of the common pipe and that of the first or second supply pipe..
07/02/15
20150187609
new patent

Semiconductor wafer cleaning system


A semiconductor wafer cleaning apparatus comprising a first supporting unit, a movable unit having a first chamber, a second supporting unit having a second chamber, and a third supporting unit is provided. A micro processing chamber in which the semiconductor wafer is being processed is formed when the first chamber is brought in contact with the second chamber.
07/02/15
20150187607
new patent

Two step molding grinding for packaging applications


Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including mounting a die to a top surface of a substrate to form a device, encapsulating the die and top surface of the substrate in a mold compound, the mold compound having a first thickness over the die, and removing a portion, but not all, of the thickness of the mold compound over the die.
07/02/15
20150187606
new patent

Semiconductor device and a manufacturing method thereof


There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead.
07/02/15
20150187605
new patent

Method of packaging a semiconductor device


A method of packaging a semiconductor device includes forming an insulating layer over a semiconductor device, wherein the semiconductor device has a contact pad, and a thickness of the contact pad is greater than a thickness of the insulating layer. The method further includes forming a molding compound to cover the semiconductor device and a space between the semiconductor device and a neighboring semiconductor device, wherein both semiconductor devices are on a carrier wafer.
07/02/15
20150187604
new patent

Method of joining semiconductor substrate


A method of joining semiconductor substrates includes: forming an alignment key on a first semiconductor substrate; forming a first protrusion and a second protrusion, and an alignment recess positioned between the first protrusion and the second protrusion on a second semiconductor substrate; forming a first metal layer and a second metal layer on the first protrusion and the second protrusion, respectively; and joining the first semiconductor substrate and the second semiconductor substrate, in which the alignment key is positioned at the alignment recess when the first semiconductor substrate and the second semiconductor substrate are joined.. .
07/02/15
20150187602
new patent

Nanoscale patterning method and integrated device for electronic apparatus manufactured therefrom


Provided is a nanoscale patterning method using self-assembly, wherein nanoscale patterns having desirable shapes such as a lamella shape, a cylinder shape, and the like, may be formed by using a self-assembly property of a block copolymer, and low segment interaction caused in a structure of 10 nm or less which is a disadvantage of the block copolymer may be prevented. In addition, even though single photolithography is used, pattern density may double as that of the existing nano patterns, and pitch and cycle of the patterns may be controlled to thereby be largely utilized for electronic apparatuses requiring high integration of circuits such as a semiconductor device, and the like..
07/02/15
20150187601
new patent

Interconnect structure and forming the same


Various embodiments provide semiconductor devices and methods for forming the same. A base including a substrate and an interlayer dielectric layer is provided.
07/02/15
20150187599
new patent

Methods of manufacturing nitride semiconductor devices


Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer..
07/02/15
20150187596
new patent

Wet etching of silicon containing antireflective coatings


Provided are methods for processing semiconductor substrates or, more specifically, etching silicon containing antireflective coatings (siarcs) from the substrates while preserving silicon oxides layers disposed on the same substrates. An etching solution including sulfuric acid and hydrofluoric acid may be used for these purposes.
07/02/15
20150187595
new patent

A semiconductor device comprising a surface portion implanted with nitrogen and fluorine


A method of fabricating a semiconductor device is provided. A substrate is provided.
07/02/15
20150187594
new patent

Composite structure for gate level inter-layer dielectric


A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer.
07/02/15
20150187591
new patent

Method of forming pattern for semiconductor device


The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements.
07/02/15
20150187588
new patent

Plasma etching method and semiconductor device manufacturing method


A plasma etching method for etching a substrate includes an adjustment step adjusting a concentration distribution of active species contained in plasma. The adjustment step adjusts a supply rate of an etching gas according to whether a supply region on a substrate to which the etching gas is supplied corresponds to a region where an effect of diffusion of the supplied etching gas is greater than an effect of flow of the supplied etching gas or a region where the effect of flow of the supplied etching gas is greater than the effect of diffusion of the supplied etching gas..
07/02/15
20150187582
new patent

Doping method, doping apparatus and manufacturing semiconductor device


Disclosed is a plasma doping apparatus and a plasma doping method for performing a doping on a processing target substrate by implanting dopant ions into the processing target substrate. The plasma doping method includes a plasma doping processing performed on the processing target substrate held on a holding unit within a processing container by generating plasma using a microwave.
07/02/15
20150187580
new patent

Method for overcoming broken line and photoresist scum issues in tri-layer photoresist patterning


A method of patterning a semiconductor device using a tri-layer photoresist is disclosed. A material layer is formed over a substrate.
07/02/15
20150187579
new patent

Stress-controlled formation of tin hard mask


A method to form a titanium nitride (tin) hard mask in the damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the tin hard mask is controlled. The tin hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising tin and chlorine pecvd deposition, and n2/h2 plasma gas treatment.
07/02/15
20150187577
new patent

Method and structure for multigate finfet device epi-extension junction control by hydrogen treatment


Embodiments are directed to forming a structure comprising at least one fin, a gate, and a spacer, applying an annealing process to the structure to create a gap between the at least one fin and the spacer, and growing an epitaxial semiconductor layer in the gap between the spacer and the at least one fin.. .
07/02/15
20150187575
new patent

Manufacturing oxide semiconductor


A method of forming an oxide semiconductor includes a step of depositing an oxide semiconductor layer over a substrate by using a sputtering apparatus in which in a target containing indium, an element m (aluminum, gallium, yttrium, or tin), zinc, and oxygen, the substrate which faces a surface of the target, and a magnet unit comprising a first magnet and a second magnet on a rear surface side of the target are provided. In the method, deposition is performed under a condition that a maximum intensity of a horizontal magnetic field is greater than or equal to 350 g and less than or equal to 2000 g in a plane where a vertical distance toward the substrate from a surface of the magnet unit is 10 mm..
07/02/15
20150187573
new patent

P-type metal oxide semiconductor material and fabricating the same


In(1−3)ga(1−b)zn(1+a+b)o4, wherein 0≦a≦0.1, 0≦b≦0.1, and 0<a+b≦0.16. In particular, the p-type metal oxide semiconductor material has a hole carrier concentration of between 1×1011 cm−3 and 5×1018 cm−3..
07/02/15
20150187572
new patent

Interlayer design for epitaxial growth of semiconductor layers


An interlayer structure that, in one implementation, includes a combination of an amorphous or nano-crystalline seed-layer, and one or more metallic layers, deposited on the seed layer, with the fcc, hcp or bcc crystal structure is used to epitaxially orient a semiconductor layer on top of non-single-crystal substrates. In some implementations, this interlayer structure is used to establish epitaxial growth of multiple semiconductor layers, combinations of semiconductor and oxide layers, combinations of semiconductor and metal layers and combination of semiconductor, oxide and metal layers.
07/02/15
20150187571
new patent

Germanium-containing finfet and methods for forming the same


A method includes forming isolation regions in a semiconductor substrate, forming a first semiconductor strip between opposite portions of isolation regions, forming a second semiconductor strip overlying and contacting the first semiconductor strip, and performing a first recessing to recess the isolation regions. A portion of the second semiconductor strip over top surfaces of remaining portions of the isolation regions forms a semiconductor fin.
07/02/15
20150187568
new patent

Process feed management for semiconductor substrate processing


Embodiments related to managing the process feed conditions for a semiconductor process module are provided. In one example, a gas channel plate for a semiconductor process module is provided.
07/02/15
20150187567
new patent

Substrate processing apparatus, manufacturing semiconductor device, and non-transitory computer-readable recording medium


A substrate processing apparatus processes a substrate by supplying a gas into a processing space. The apparatus includes a buffer space wherein the gas is dispersed, the buffer space disposed at an upstream side of the processing space; a transfer space where the substrate passes when transferred to the processing space; a first, a second and a third exhaust pipe connected to the transfer space, the buffer space and the processing space, respectively; a fourth exhaust pipe connected to downstream sides of the first exhaust pipe, the second exhaust pipe and the third exhaust pipe; a first vacuum pump disposed at the first exhaust pipe; a second vacuum pump disposed at the fourth exhaust pipe; a first valve disposed at the first exhaust pipe at a downstream side of the first vacuum pump; and a second and a third valve disposed at the second and the third exhaust pipe, respectively..
07/02/15
20150187566
new patent

Hardmask composition, forming patterns using the hardmask composition and semiconductor integrated circuit device including the patterns


R1a, r1b, r4a, r4b, r2a, r2b, r5a, r5b and r3 are the same as defined in the specification.. .
07/02/15
20150187564
new patent

Method of using a vaporizing spray system to perform a trimming process


A method of semiconductor device fabrication including placing a substrate having a first and second features disposed thereon in a vaporizing spray deposition system. An atomizing spray head of the vaporizing spray deposition system is used to deposit a conformal polymer layer on the first and second features.
07/02/15
20150187560
new patent

Cyclic deposition thin film formation, semiconductor manufacturing method, and semiconductor device


A cyclic deposition method for thin film formation includes forming a silicon thin film on an object by injecting a silicon precursor into a chamber in which the object is loaded, depositing silicon on the object, and performing a first purge, removing an unreacted portion of the silicon precursor and reaction by-products from the interior of the chamber, pre-processing a surface of the silicon thin film by forming a plasma atmosphere in the chamber and supplying a first reaction source having a hydrogen atom, and forming the silicon thin film as an insulating film including silicon, by forming the plasma atmosphere in the chamber and supplying a second reaction source having one or more oxygen atoms, one or more nitrogen atoms, or a mixture thereof.. .
07/02/15
20150187559
new patent

Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium


A method of manufacturing a semiconductor device includes forming a laminated film on a substrate by performing a cycle a predetermined number of times. The cycle includes forming a first film which contains a predetermined element, boron, and nitrogen and which does not contain a borazine ring skeleton, and forming a second film which contains the predetermined element and a borazine ring skeleton.
07/02/15
20150187511
new patent

Dye-sensitized solar cell


Provided is a dye-sensitized solar cell which exhibits excellent heat resistance and high photoelectric conversion efficiency. This dye-sensitized solar cell is provided with: a negative electrode having a semiconductor layer with a pigment as a photosensitizer, an electrolyte layer located on the semiconductor layer of the negative electrode having a paired oxidized species and reduced species, and a positive electrode located on the electrolyte layer having a conductive polymer layer that acts as a catalyst to convert the oxidized species into the reduced species.
07/02/15
20150187505
new patent

Method for manufacturing solid electrolytic capacitor element


The present invention provides a method for manufacturing a solid electrolytic capacitor element, wherein a dielectric layer, a semiconductor layer, a carbon layer and a silver layer are sequentially formed on a tungsten base material. This method is characterized in that: the formation of the carbon layer is carried out by laminating a carbon paste on the semiconductor layer; the carbon paste is an aqueous resin solution containing carbon particles; and a repair formation treatment is carried out after the formation of the carbon layer but before the formation of the silver layer.
07/02/15
20150187470
new patent

Multi-sided optical waveguide-fed photoconductive switches


A photoconductive switch and optical transconductance varistor having a photoconductive region e.g. A wide bandgap semiconductor material substrate between opposing electrodes.
07/02/15
20150187438
new patent

Semiconductor memory apparatus and test method using the same


A semiconductor memory apparatus includes first data outputted from a first data storage region; second data outputted from a second data storage region; a data comparison block configured to perform a comparison to determine whether the first data and the second data are the same, and generate a comparison result signal; a timing control block configured to latch the comparison result signal in response to a clock and a latency signal, and output a comparison signal; and a data output block configured to receive a test signal and invert the first data in response to the comparison signal and output data.. .
07/02/15
20150187434
new patent

Test circuit of semiconductor apparatus


A test circuit of a semiconductor apparatus includes a plurality of memory blocks, and a comparison block configured to compare data of two memory blocks, wherein the two of the plurality of memory blocks do not share word lines.. .
07/02/15
20150187428
new patent

Nonvolatile semiconductor storage device


According to one embodiment, a nonvolatile semiconductor storage device includes a word line transfer unit which transfers voltage applied to a memory cell selected on the basis of an address to a word line. The word line transfer unit includes a word line transfer transistor which is arranged in a first layout area of the word line transfer unit and transfers voltage applied to the memory cell to the word line and a dummy word line transfer transistor which is arranged in a second layout area provided outside an end of the first layout area and does not transfer voltage applied to the memory cell to the word line..
07/02/15
20150187426
new patent

Memory operating the same


A memory system and a method for operating the same are provided. The memory system includes a semiconductor memory device suitable for performing an erase operation in response to a control signal, and if an erase command is input from a host, a controller suitable for temporarily storing erase block information according the erase command, and when a program command is input after the erase command is input, transmitting the control signal according to the erase command to the semiconductor memory device..
07/02/15
20150187424
new patent

Nonvolatile semiconductor memory device


A non-volatile semiconductor memory device according to one embodiment includes: a cell array; and a data writing unit that repeatedly executes a write loop including a programming operation of applying a program voltage to a selected word line and a passage voltage to non-selected word lines during writing of data, in which, when a difference between the passage voltage used in an n-th write loop and the passage voltage used in an n+1-th write loop is expressed as Δvn and when a condition of l<m (l and m are integers) is satisfied, the data writing unit executes the write loop using the passage voltage where Δv (l−1)<Δvl, Δvl≦Δv (m−1), and Δv (m−1)<Δvm.. .
07/02/15
20150187423
new patent

Input buffer for semiconductor memory device and flash memory device including the same


An input buffer includes an amplifier circuit configured to amplify an input signal and output an amplified signal to a first output node. The input signal is amplified according to a first bias voltage set, at a bias node, to a first level based on a power supply voltage and a reference voltage.
07/02/15
20150187422
new patent

Semiconductor device


A semiconductor device includes first memory strings coupled between a first common source line formed on a substrate and bit lines formed over the first common source line, and second memory strings coupled between the bit lines and a second common source line formed over the bit lines, wherein each of the bit lines includes a stacked structure of a conductive layer and a silicon layer formed on the conductive layer.. .
07/02/15
20150187421
new patent

Spacer layer for embedding semiconductor die


A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate.
07/02/15
20150187420
new patent

Semiconductor memory device, memory system including the same, and operating method thereof


The memory system includes a semiconductor memory device including a cam data block for storing cam data, and a controller configured to control an operation of the semiconductor memory device in response to a cam data program command received from a host, wherein the semiconductor memory device is configured to perform a pre-program operation and an erase operation of the cam data block prior to the performance of a cam data program operation associated with the cam data block.. .
07/02/15
20150187418
new patent

Metal line connection for improved rram reliability, semiconductor arrangement comprising the same, and manufacture thereof


An integrated circuit device includes an array of rram cells, an array of bit lines for the array of rram cells, and an array of source lines for the array of rram cells. Both the source lines and the bit lines are in metal interconnect layers above the rram cells.
07/02/15
20150187415
new patent

Electronic device and fabricating the same


An electronic device comprising a semiconductor memory unit that includes a cell structure having two memory cells, which share one selector, wherein the cell structure includes first electrodes, variable resistance patterns and second electrodes which are symmetrically disposed on both sides of the selector.. .
07/02/15
20150187411
new patent

Semiconductor device having data terminal supplied with plural write data in serial


Disclosed herein is a semiconductor device that includes: a frequency dividing circuit dividing a frequency of a first clock signal to generate second clock signals that are different in phase from one another; a multiplier circuit multiplying the second clock signals to generate a third clock signal; a data input/output terminal; data buses; and a data input/output circuit coupled between the data input/output terminal and the data buses. The data input/output circuit includes a data output circuit and a data input circuit.
07/02/15
20150187409
new patent

Semiconductor device having pda function


A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.. .
07/02/15
20150187406
new patent

Active control device, semiconductor device and system including the same


Disclosed herein are an active control device, a semiconductor device and system including the same. The active control device may include a refresh control unit configured for outputting a refresh signal by controlling a delay time for a refresh start time when a refresh operation is performed and a precharge signal generation unit configured for generating a bank precharge signal for precharging a bank in response to the refresh signal.
07/02/15
20150187405
new patent

Stacked semiconductor generating refresh signal


A stacked semiconductor apparatus includes a plurality of chips which are stacked one upon the other. One chip of the plurality of chips may be configured to generate a plurality of refresh period signals for performing refresh operations within the plurality of chips, and may be configured to transmit the plurality of refresh period signals to the plurality of chips excluding the one chip.
07/02/15
20150187402
new patent

Memory device with multiple voltage generators


A semiconductor memory device includes multiple voltage generators. The memory device includes a first voltage generator for generating a first internal voltage based on a first power supply voltage, and a second voltage generator for generating a second internal voltage based on a second power supply voltage that is lower than the first power supply voltage.
07/02/15
20150187401
new patent

Semiconductor memory apparatus


A semiconductor memory apparatus may include a clock buffer configured to receive an external clock signal, buffer the external clock signal in response to an activation control signal, and the clock buffer configured to output an internal clock signal in response to an activation control signal. The semiconductor memory apparatus may also include a delay-locked loop block configured to receive the internal clock signal outputted from the clock buffer and compare phases of the internal clock signal and a feedback clock signal, and responsively generate a delay-locked clock signal.
07/02/15
20150187400
new patent

Data sensing circuit of semiconductor apparatus


A data sensing circuit of a semiconductor apparatus includes a sensing unit configured to drive a pair of output lines based on a voltage level difference between a pair of input/output lines in response to a pair of enable signals, a timing control unit configured to perform an equalizing operation between the pair of output lines while the pair of enable signals are in a deactivated state in response to a control signal, and to interrupt the equalizing operation between the pair of output lines when a predetermined period of time has passed following the activation of the pair of enable signals, and a control signal generation unit configured to generate the control signal in response to the enable signal.. .
07/02/15
20150187396
new patent

Buffer control circuit of semiconductor memory apparatus


A buffer control circuit of a semiconductor memory apparatus includes a delay unit configured to determine delay amounts for a command in response to a plurality of command latency signals, delay the command according to a clock, and generate a plurality of delayed signals; and a buffer control signal generation unit configured to receive the plurality of command latency signals and the plurality of delayed signals, and generate a buffer control signal.. .
07/02/15
20150187393
new patent

Nonvolatile semiconductor memory device


A memory array includes a resistive memory cell array having a first cell transistor and a resistance change element connected in series and a reference cell array having a second cell transistor and a resistance element connected in series. The second cell transistor of the reference cell array is connected to a reference source line, and the resistance element is connected to a reference bit line.
07/02/15
20150187276
new patent

Organic light emitting display device and driving the same


An organic light emitting display device includes a display panel having a plurality of pixels, each pixel connected to a data line, a gate line group and a reference line, each pixel further including: an organic light emitting device; a driving transistor controlling a current flowing in the organic light emitting device and including first and second gate electrodes overlapped with each other, with a semiconductor layer provided therebetween; a first switching transistor selectively supplying a data voltage supplied to the data line to a first node connected to the first gate electrode; a second switching transistor selectively supplying a sensing voltage to the second gate electrode; a third switching transistor selectively connecting a second node connected to a source electrode of the driving transistor to the first node; a fourth switching transistor selectively connecting the reference line to the second node; a first capacitor connected between the second gate electrode and the second node, the first capacitor storing a threshold voltage of the driving transistor; and a second capacitor connected between the first and second nodes, the second capacitor storing a difference voltage of the first and second nodes.. .
07/02/15
20150187255
new patent

Driving circuit of amoled and driving the amoled


A driving circuit of an active matrix/organic light emitting diode (amoled) includes a first semiconductor controllable switch, a second semiconductor controllable switch, an energy-storage. Capacitor, an organic light emitting diode, and a sequential control unit that divides a driving time of one frame of the organic light emitting diode into driving times of n subframes.
07/02/15
20150187059
new patent

Image processing method, image processing system, and storage medium storing image processing program


An image processing method includes a step of acquiring a measured image g1b measured from a semiconductor device s and a first pattern image g2b showing a pattern of the semiconductor device s, a step of acquiring a reference measured image g3b measured from a reference semiconductor device sr being the semiconductor device s or a semiconductor device different from the semiconductor device s and a second pattern image g4b showing a pattern of the reference semiconductor device sr, a step of acquiring matching information indicating a correlation of the first pattern image g2b and the second pattern image g4b, and a step of determining a difference of the measured image g1b and the reference measured image g3b based on the matching information to acquire a comparative image g5b.. .
07/02/15
20150187058
new patent

Image processing method, image processing system, and storage medium storing image processing program


An image processing method in an observation system 1a includes a step of acquiring a measured image g1 measured from a semiconductor device s and a first pattern image g2 showing a pattern of the semiconductor device s corresponding to the measured image g1, a step of acquiring a second pattern image g3 showing a pattern of the semiconductor device s, a step of acquiring matching information indicating a correlation of the first pattern image g2 and the second pattern image g3 based on the first pattern image g2 and the second pattern image g3, and a step of superimposing the second pattern image g3 and the measured image g1 based on the matching information to acquire a superimposed image g4.. .


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Semiconductor topics: Semiconductor, Semiconductor Substrate, Semiconductor Device, Semiconductor Material, Electric Conversion, Conductive Layer, Molybdenum, Camera Module, Semiconductor Devices, Semiconductors, Integrated Circuit, Surfactant, Photoelectric Conversion, Electronic Device, Transparent Conductive Oxide

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