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Semiconductor patents



      

This page is updated frequently with new Semiconductor-related patent applications.




Date/App# patent app List of recent Semiconductor-related patents
07/21/16
20160212854 
 Printed wiring board patent thumbnailPrinted wiring board
A printed wiring board for mounting a semiconductor element includes an insulating substrate, a first conductor structure on first side of the substrate, and a second conductor structure on second side of the substrate. The substrate has a first area and a second area outside the first area such that when a semiconductor element is mounted on the first side, the first area is directly below the element, the first structure has a first area conductor structure in the first area and a second area conductor structure in the second area, and the first structure is formed such that first ratio is set greater than second ratio, where the first ratio is obtained by dividing volume of the first area structure by area of the first area structure, and the second ratio is obtained by dividing volume of the second area structure by area of the second area structure..
Ibiden Co., Ltd.


07/21/16
20160212834 
 Cyclic accelerator for accelerating charge carriers and  manufacturing a cyclic accelerator patent thumbnailCyclic accelerator for accelerating charge carriers and manufacturing a cyclic accelerator
What is shown is a cyclic accelerator for accelerating charge carriers. The cyclic accelerator includes a charge carrier source configured to generate free charge carriers, a vacuum chamber configured to receive the free charge carriers, wherein the vacuum chamber is produced by means of mems technology, and wherein at least a main surface region of the vacuum chamber has a semiconductor material.
Fraunhofer-gesellschaft Zur Foerderung Der Angewandten Forschung E.v.


07/21/16
20160212551 
 Microelectromechanical system microphone patent thumbnailMicroelectromechanical system microphone
A microelectromechanical system microphone includes a semiconductor-on-insulator structure, a plurality of resistors, a plurality of first openings, and a vent hole. The semiconductor-on-insulator structure includes a substrate, an insulating layer and a semiconductor layer.
United Microelectronics Corp.


07/21/16
20160211860 
 D/a conversion circuit, oscillator, electronic apparatus, and moving object patent thumbnailD/a conversion circuit, oscillator, electronic apparatus, and moving object
A d/a conversion circuit includes a plurality of resistors that are connected to each other in series, and a plurality of mos transistors that are connected to terminals of the plurality of resistors, respectively. The plurality of resistors and the plurality of mos transistors are formed on a semiconductor substrate.
Seiko Epson Corporation


07/21/16
20160211859 
 D/a conversion circuit, oscillator, electronic apparatus, and moving object patent thumbnailD/a conversion circuit, oscillator, electronic apparatus, and moving object
A d/a conversion circuit includes a plurality of resistors connected to each other in series, a plurality of mos transistors connected to each other so as to correspond to a plurality of contacts, and a plurality of dummy electrodes respectively disposed on sides opposite to the plurality of mos transistors with a resistive element interposed therebetween when seen in a plan view of a semiconductor substrate. Each of the dummy electrodes is set to be in a second potential state when a gate electrode of the mos transistor disposed on a side opposite thereto with the resistive element interposed therebetween is in a first potential state, and is set to be in a first potential state when the gate electrode of the mos transistor is in a second potential state..
Seiko Epson Corporation


07/21/16
20160211839 
 Semiconductor integrated circuit and semiconductor integrated circuit device patent thumbnailSemiconductor integrated circuit and semiconductor integrated circuit device
Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node..
Socionext Inc.


07/21/16
20160211838 
 Hybrid tfet-mosfet circuit design patent thumbnailHybrid tfet-mosfet circuit design
A circuit includes a hybrid switch, which includes a tunnel field-effect transistor (tfet) having a first source, a first drain, and a first gate. The hybrid switch further includes a metal-oxide-semiconductor field-effect transistor (mosfet) connected to the tfet in parallel, with the mosfet including a second source connected to the first source, a second drain connected to the first drain, and a second gate connected to the first gate..
National Chiao Tung University


07/21/16
20160211826 
 Passive wireless sensor including piezoelectric mems resonator patent thumbnailPassive wireless sensor including piezoelectric mems resonator
A passive wireless sensor includes a substrate having at least one microelectromechanical system (mems) piezoelectric resonator thereon. The mems piezoelectric resonator includes a piezoelectric layer between a top metal or semiconductor layer (top electrode layer) and a bottom metal or semiconductor layer (bottom electrode layer).
University Of Central Florida Research Foundation, Inc.


07/21/16
20160211806 
 Semiconductor integrated circuit and wireless transmitter patent thumbnailSemiconductor integrated circuit and wireless transmitter
A semiconductor integrated circuit includes a first transmission power mode configured to transmit by a first power, and a second transmission power mode configured to transmit by a second power smaller than the first power, the semiconductor integrated circuit. The semiconductor integrated circuit includes a first transistor configured to receive and amplify a transmission signal in the second transmission power mode, and an attenuator including a resistor element and a switching element, provided between an output of the first transistor and an output terminal, configured to control attenuation of an output signal of the first transistor..
Fujitsu Limited


07/21/16
20160211748 
 Self-powered bjt driver for power supplies patent thumbnailSelf-powered bjt driver for power supplies
An apparatus for providing auxiliary power to an off-line switcher. The apparatus includes a high voltage semiconductor switch and a driver for the high voltage semiconductor switch.
Dialog Semiconductor Inc.


07/21/16
20160211660 

Semiconductor device with surge current protection


A power device includes an active area having at least two switchable regions with different threshold voltages.. .
Infineon Technologies Ag


07/21/16
20160211657 

Semiconductor device


A semiconductor device includes a semiconductor switching element, a correction current voltage generation circuit, a voltage dividing circuit, an overcurrent protection circuit, and a drive circuit. The switching element is capable of outputting a sense current from its sense terminal.
Mitsubishi Electric Corporation


07/21/16
20160211651 

Semiconductor laser device


A semiconductor laser device capable of high output is provided. A semiconductor laser diode includes: a substrate; and a semiconductor stacked structure, which is formed on the substrate through crystal growth.
Rohm Co., Ltd.


07/21/16
20160211650 

Optical semiconductor device


An upper cladding layer includes a first low carrier concentration layer having a lower carrier concentration than the p-type cladding layer and a first fe-doped semiconductor layer formed on the first low carrier concentration layer. The leakage current suppression layer includes a second fe-doped semiconductor layer disposed on a side of the p-type semiconductor layer.
Mitsubishi Electric Corporation


07/21/16
20160211649 

Tensile strained semiconductor photon emission and detection devices and integrated photonics system


Tensile strained germanium is provided that can be sufficiently strained to provide a nearly direct band gap material or a direct band gap material. Compressively stressed or tensile stressed stressor materials in contact with germanium regions induce uniaxial or biaxial tensile strain in the germanium regions.
Acorn Technologies, Inc.


07/21/16
20160211646 

Semiconductor stripe laser


A semiconductor stripe laser has a first semiconductor region having a first conductivity type and a second semiconductor region having a different, second conductivity type. An active zone for generating laser radiation is located between the semiconductor regions.
Osram Opto Semiconductors Gmbh


07/21/16
20160211645 

Semiconductor laser apparatus and manufactruing method thereof


A semiconductor laser apparatus includes a silicon-on-insulator assembly and an edge-emitting semiconductor laser assembly integrated on the silicon-on-insulator assembly. The silicon-on-insulator assembly includes an optical waveguide at the top which is bonded to the edge-emitting semiconductor laser assembly and configured to couple a laser light emitted from the edge-emitting semiconductor laser assembly, and the optical waveguide includes a core portion located in the middle of the optical waveguide; and at least one vertical rib configured on two sides of the core portion respectively, with a width narrower than that of the core portion.
Sae Magnetics (h.k.) Ltd.


07/21/16
20160211637 

Slab laser and amplifier and use


A slab laser and its method of use for high power applications including the manufacture of semiconductors and deposition of diamond and/or diamond-like-carbon layers, among other materials. A lamp driven slab design with a face-to-face beam propagation scheme and an end reflection that redirects the amplified radiation back out the same input surface is utilized.

07/21/16
20160211474 

Thin film transistor array and manufacturing the same


A thin film transistor array includes thin film transistors positioned in a matrix, each of the thin film transistors including a substrate, a gate electrode formed on the substrate, a gate insulation layer formed on the gate electrode, a source electrode formed on the gate insulation layer, a drain electrode formed on the gate insulation layer, a pixel electrode formed on the gate insulation layer and connected to the source electrode and the drain electrode, a semiconductor layer formed between the source electrode and the drain electrode, an interlayer insulation film covering the source electrode, the drain electrode, the semiconductor layer and a portion of the pixel electrode, and an upper pixel electrode formed on the interlayer insulation film and connected to the pixel electrode. The interlayer insulation film has one or more concave portions and one or more via hole portions..
Toppan Printing Co., Ltd.


07/21/16
20160211472 

Flexible display device


A flexible display device includes a display panel having a driving circuit unit including at least two capacitors and at least two thin film transistors on a flexible substrate, each of the at least two thin film transistors including a semiconductor layer with a gate region, a drain region, and a source region on the flexible substrate, and a gate electrode on the semiconductor layer, and a display unit on the flexible substrate and connected to the driving circuit unit, wherein the display panel is partitioned into a bending area and a non-bending area, the bending area being bendable by a tensile force and a compression force, and the driving circuit unit being asymmetrically designed in the bending area and the non-bending area.. .
Samsung Display Co., Ltd.


07/21/16
20160211440 

Semiconductor devices, magnetic tunnel junctions, and methods of fabrication thereof


A semiconductor device comprises an array of magnetic cell structures each comprising a magnetic tunnel junction over an electrode on a substrate. Each of the magnetic tunnel junctions includes a magnetic material over the substrate, a first tunnel barrier material over the magnetic material, a second tunnel barrier material over the annealed first tunnel barrier material, and another magnetic material over the second tunnel barrier material.
Micron Technology, Inc.


07/21/16
20160211427 

Light emitting device


The present invention relates to a light emitting device. The light emitting device according to an embodiment of the present invention comprises: a light emitting structure comprising a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer; a channel layer arranged around the lower portion of the light emitting structure; a first electrode arranged on the channel layer; a second electrode arranged under the light emitting structure; and a connection wiring for electrically connecting the first electrode and the first conductive semiconductor layer..
Lg Innotek Co., Ltd.


07/21/16
20160211425 

Semiconductor light emitting device and optical film


A semiconductor light emitting device, which can endure a dicing step for singulation, is superior in resistance to a high/low thermal cycle, and exhibits a high light extraction efficiency, and an optical film, which can be used favorably for producing the semiconductor light emitting device, are to be provided. The invention provides a semiconductor light emitting device comprising a semiconductor layer, an a layer, and a b layer, in which the semiconductor light emitting device is configured such that at least a part of emitted light from the semiconductor layer is emitted outward from the b layer through the a layer, the thickness of the a layer is from 1 nm to 200 nm, the b layer has a first major surface and a second major surface, while the first major surface faces the a layer and the second major surface has a concave-convex microstructure, the b layer contains an inorganic substance at 60 mass-% or more on the basis of the total mass of the b layer, and the content of an inorganic substance present in the a layer is lower than the content of the inorganic substance present in the b layer..
Asahi Kasei E-materials Corporation


07/21/16
20160211423 

Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting devices, and associated systems and methods


Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting devices, and associated systems and methods are disclosed. A solid state radiative semiconductor structure in accordance with a particular embodiment includes a first region having a first value of a material characteristic and being positioned to receive radiation at a first wavelength.
Micron Technology, Inc.


07/21/16
20160211422 

Semiconductor light emitting device


A semiconductor light emitting device comprises a supporting substrate that has light reflecting characteristics; a wavelength conversion layer that is disposed on the supporting substrate, and contains semiconductor nanoparticles developing a quantum size effect; an optical semiconductor laminate that is disposed on the wavelength conversion layer and has light emitting characteristics; and a photonic crystal layer that is disposed on the optical semiconductor laminate, and that has first portions having a first refractive index and second portions having a second refractive index different from the first refractive index, the first portions and the second portions being arranged in a two-dimensional cyclic pattern.. .
Stanley Electric Co., Ltd.


07/21/16
20160211419 

Semiconductor light emitting element and manufacturing the same


A light emitting device includes a first semiconductor layer of a first conductivity type having an upper and lower surface sides. A first portion of the first semiconductor layer is adjacent to a second portion of the first semiconductor layer.
Kabushiki Kaisha Toshiba


07/21/16
20160211418 

Method for producing a semiconductor device


The present invention provides a method for producing a semiconductor device exhibiting the improved emission efficiency by reducing a strain between a p-contact layer and a transparent electrode. A transparent electrode made of izo (zinc-doped indium oxide) was formed on a p-type contact layer by vapor deposition or sputtering.
Toyoda Gosei Co., Ltd.


07/21/16
20160211417 

Semiconductor light-emitting element, light emitting device, and manufacturing semiconductor light-emitting element


A semiconductor light-emitting element includes a stacked body having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer between the first and second semiconductor layers. A first metal layer is on the second semiconductor layer.
Kabushiki Kaisha Toshiba


07/21/16
20160211416 

Led die


An led die includes a base, and an n-typed semiconductor layer, an active layer and a p-typed semiconductor layer formed on the base that order. The led die also includes an n-electrode and a p-electrode.
Advanced Optoelectronic Technology, Inc.


07/21/16
20160211415 

Semiconductor light emitting device and fabricating method thereof


A semiconductor light emitting device including a substrate, a plurality of semiconductor light emitting units and a plurality of non-conductive walls is provided. The semiconductor light emitting device is disposed on the substrate in an array.
Industrial Technology Research Institute


07/21/16
20160211414 

Light-emitting element having a reflective structure with high efficiency


An optoelectronic element comprises a semiconductor stack comprising an active layer, wherein the semiconductor stack has a first surface and a second surface opposite to the first surface; a first transparent layer on the second surface; a plurality of cavities in the first transparent layer; and a layer on the first transparent layer, wherein the first transparent layer comprises oxide or diamond-like carbon.. .
Epistar Corporation


07/21/16
20160211412 

Semiconductor light-emitting device


A semiconductor light-emitting device comprises an epitaxial structure comprising a first semiconductor stack, a second semiconductor stack, and an active layer between the first semiconductor stack and second semiconductor stack for emitting a light; and a main light-extraction surface on the first semiconductor stack, wherein the light passes through the main light-extraction surface. The main light-extraction surface comprises a first light-extraction region, a second light-extraction region, and a maximum near-field luminous intensity.
Epistar Corporation


07/21/16
20160211411 

High efficiency ultraviolet light emitting diode with band structure potential fluctuations


A method of growing an algan semiconductor material utilizes an excess of ga above the stoichiometric amount typically used. The excess ga results in the formation of band structure potential fluctuations that improve the efficiency of radiative recombination and increase light generation of optoelectronic devices, in particular ultraviolet light emitting diodes, made using the method.
Trustees Of Boston University


07/21/16
20160211410 

Wafer level light-emitting diode array


A light emitting diode array is provide to include: a substrate; light emitting diodes positioned over the substrate, each including a first semiconductor layer, an active layer, and a second semiconductor layer, wherein each light emitting diode is disposed to form a first via hole structure exposing a portion of the corresponding first semiconductor layer; lower electrodes disposed over the second semiconductor layer; a first interlayer insulating layer disposed over the lower electrodes and configured to expose the portion of the first semiconductor layer of corresponding light emitting diodes; upper electrodes electrically connected to the first semiconductor layer through the first via hole structure, wherein the first via hole structure is disposed in parallel with one side of the corresponding second semiconductor layer and the first interlayer insulating layer is disposed to form a second via hole structure exposing a portion of the lower electrodes.. .
Seoul Viosys Co., Ltd.


07/21/16
20160211408 

Semiconductor light emitting device


According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, an electrode pad, a first electrode, a second electrode and a layer. The semiconductor layer includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer.
Kabushiki Kaisha Toshiba


07/21/16
20160211406 

Nanowire led structure and manufacturing the same


A method for ablating a first area of a light emitting diode (led) device which includes an array of nanowires on a support with a laser is provided. The laser ablation exposes a conductive layer of the support that is electrically connected to a first conductivity type semiconductor nanowire core in the nanowires, to form a first electrode for the led device.
Glo Ab


07/21/16
20160211405 

Method of manufacturing semiconductor device


A method includes the steps of: forming a plurality of recessed portions in an insulating film formed above a wafer including a first region and a second region outside the first region such that the recessed portions are formed above both the first region and the second region; forming a conductive film on the insulating film such that the plurality of recessed portions are filled with the conductive film; removing the conductive film above the second region while leaving the conductive film above the first region; and removing part of the conductive film remaining above the first region outside the plurality of recessed portions, wherein an area proportion of the recessed portions each having a projected area of 10 μm2 or smaller on the wafer among the plurality of recessed portions is higher in the second region than in the first region.. .
Canon Kabushiki Kaisha


07/21/16
20160211403 

Method for manufacturing solar cell


A method for manufacturing a solar cell is disclosed. The disclosed method includes conductive region formation of forming a first-conduction-type region at one surface of a semiconductor substrate and a second-conduction-type region at another surface of the semiconductor substrate, and electrode formation of forming a first electrode connected to the first-conduction-type region and a second electrode connected to the second-conduction-type region.
Lg Electronics Inc.


07/21/16
20160211401 

Monolithic multiple solar cells


A monolithic multiple solar cell includes at least three partial cells, with a semiconductor mirror placed between two partial cells. The aim of the invention is to improve the radiation stability of said solar cell.
Azur Space Solar Power Gmbh


07/21/16
20160211400 

Monolithic multiple solar cells


A monolithic multiple solar cell includes at least three partial cells, with a semiconductor mirror placed between two partial cells. The aim of the invention is to improve the radiation stability of said solar cell.
Azur Space Solar Power Gmbh


07/21/16
20160211393 

Tunnel diode with broken-gap quantum well


A broken-gap tunnel junction device comprising a thin quantum well (qw) layer situated at the interface between adjacent highly doped n-type and p-type semiconductor layers, wherein the qw layer has a type-iii broken-gap energy band alignment with respect to one or more of the surrounding semiconductor layers such that a conduction band of the qw layer is below the valence band of one or more of the n-type and p-type bulk semiconductor layers.. .
The Government Of The United States Of America, As Represented By The Secretary Of The Navy


07/21/16
20160211392 

Air stable infrared photodetectors from solution-processed inorganic semiconductors


A photodetector has a photoactive layer of semiconducting inorganic nanoparticles positioned between a hole transport electron blocking layer of a first metal oxide and an electron transport hole blocking layer of a second metal oxide. The nanoparticles are responsive to electromagnetic radiation in at least the infrared region of the spectrum.
University Of Florida Research Foundation, Inc.


07/21/16
20160211389 

Composition for forming passivation layer, semiconductor substrate having passivation layer, producing semiconductor substrate having passivation layer, photov oltaic cell element, producing photovoltaic cell element, and photovoltaic cell


A composition for forming a passivation layer, including a resin and a compound represented by formula (i): m(or1)m. In formula (i), m includes at least one metal element selected from the group consisting of nb, ta, v, y and hf, each r1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5..
Hitachi Chemical Company, Ltd.


07/21/16
20160211386 

Oxide semiconductor substrate and schottky barrier diode


A schottky barrier diode element includes an n-type or p-type silicon (si) substrate, an oxide semiconductor layer, and a schottky electrode layer, the oxide semiconductor layer including either or both of a polycrystalline oxide that includes gallium (ga) as the main component and an amorphous oxide that includes gallium (ga) as the main component.. .
Idemitsu Kosan Co., Ltd.


07/21/16
20160211385 

Semiconductor device and semiconductor device manufacturing method


A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma treatment damages the surface of an oxide film formed on a n− type drift layer deposited on an n+ type semiconductor substrate.
Fuji Electric Co., Ltd.


07/21/16
20160211384 

Oxide for semiconductor layer of thin film transistor, thin film transistor and display device


In an oxide for a semiconductor layer of a thin film transistor according to the present invention, wherein metal elements constituting the oxide are in, zn, and sn, an oxygen partial pressure is 15% by volume or more when depositing the oxide in the semiconductor layer of the thin film transistor, and a defect density of the oxide satisfies 7.5×1015cm−3 or less, and a mobility satisfies 15 cm2/vs or more.. .
Samsung Display Co., Ltd


07/21/16
20160211383 

Planarisation layers


A device, comprising: an unplanarised plastic substrate; an electrically and/or optically functional layer formed on the unplanarised substrate; a planarisation layer formed over the functional layer; at least a first conductor layer and a semiconductor layer formed over the planarization layer, wherein the first conductor layer defines at least source and drain electrode circuitry for one or more transistor devices, and the semiconductor layer defines semiconductor channels for said one or more transistor devices.. .
Flexenable Limited


07/21/16
20160211382 

Semiconductor device and manufacturing method thereof


A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer..
Semiconductor Energy Laboratory Co., Ltd.


07/21/16
20160211381 

Switch circuit, semiconductor device, and system


A switch circuit that can control an electrical connection state without additionally providing a control circuit is provided. The switch circuit includes a transistor, a first switch which control an electrical connection state between a gate of the transistor and a wiring, a second switch, a first diode including an anode and a cathode, a third switch, and a second diode including an anode and a cathode.
Semiconductor Energy Laboratory Co., Ltd.


07/21/16
20160211380 

Semiconductor device and manufacturing method thereof


A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer.
Semiconductor Energy Laboratory Co., Ltd.


07/21/16
20160211379 

Semiconductor device having asymmetric fin-shaped pattern


semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern.

07/21/16
20160211378 

Semiconductor device, fabricating the same, and memory system including the semiconductor device


semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an l shape, a second gate spacer formed on the first gate spacer to have an l shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer..

07/21/16
20160211377 

Finfet with dielectric isolated channel


Embodiments of the present invention provide a fin type field effect transistor (finfet) and methods of fabrication. A punchthrough stopper region is formed on a semiconductor substrate.
International Business Machines Corporation


07/21/16
20160211374 

Semiconductor device and manufacturing same


A semiconductor device includes: a sidewall insulating film; a gate electrode; source and drain regions; a first stress film; and a second stress film.. .
Sony Corporation


07/21/16
20160211372 

Semiconductor device and manufacturing method thereof


A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. An isolation insulating layer is formed so that an upper part of the fin structure protrudes from the isolation insulating layer.
Taiwan Semiconductor Manufacturing Co., Ltd


07/21/16
20160211371 

Semiconductor device including fin structures and manufacturing method thereof


A semiconductor fin fet device includes a fin structure disposed over a substrate. The fin structure includes a channel layer.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/21/16
20160211370 

Semiconductor device and forming vertical structure


A semiconductor device includes a source/drain region, a barrier layer, and an interlayer dielectric. The barrier layer surrounds the source/drain region.
Taiwan Semiconductor Manufacturing Company Limited


07/21/16
20160211369 

Vertical non-planar semiconductor device for system-on-chip (soc) applications


Vertical non-planar semiconductor devices for system-on-chip (soc) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion.
Intel Corporation


07/21/16
20160211368 

Semiconductor device and fabricating the same


A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first dielectric layer and a second dielectric layer thereon; forming a drain layer in the first dielectric layer and the second dielectric layer; forming a gate layer on the second dielectric layer; forming a channel layer in the gate layer; forming a third dielectric layer and a fourth dielectric layer on the gate layer and the channel layer; and forming a source layer in the third dielectric layer and the fourth dielectric layer..
United Microelectronics Corp.


07/21/16
20160211367 

Metal oxide semiconductor devices and fabrication methods


A semiconductor device includes a first well that is disposed in a semiconductor substrate. The semiconductor device further includes a second well that is disposed in the semiconductor substrate.
Broadcom Corporation


07/21/16
20160211365 

Superjunction with surrounding lightly doped drain region


A semiconductor device has a substrate and a lightly doped drain (ldd) region formed in the substrate. A superjunction is formed in the ldd region..
Great Wall Semiconductor Corporation


07/21/16
20160211362 

Mosfets with multiple dislocation planes


A method includes forming a metal-oxide-semiconductor field-effect transistor (mosfet). The method includes performing an implantation to form a pre-amorphization implantation (pai) region adjacent to a gate electrode of the mosfet, forming a strained capping layer over the pai region, and performing an annealing on the strained capping layer and the pai region to form a dislocation plane.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/21/16
20160211361 

Semiconductor device


A semiconductor device in which current sensing accuracy is maintained while ruggedness of a current sensing region is improved. The semiconductor device includes a semiconductor substrate; a main element provided on the semiconductor substrate and having a first trench gate structure including a first trench disposed on a first main surface side of the semiconductor substrate; a gate insulating film disposed along an inner wall of the first trench; and a gate electrode disposed inside the first trench; and a current detecting element for detecting a current flowing into the semiconductor substrate when the main element is operating provided on the semiconductor substrate and having a second trench gate structure including a second trench disposed on the first main surface side of the semiconductor substrate; the gate insulating film disposed along an inner wall of the second trench; and the gate electrode disposed inside the second trench..
Fuji Electric Co., Ltd.


07/21/16
20160211360 

Vertical power transistor device


A power metal-oxide-semiconductor field-effect transistor (mosfet) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (jfet) region.
Cree, Inc.


07/21/16
20160211359 

Integrated power device


A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die.. .
Infineon Technologies Americas Corp.


07/21/16
20160211358 

Semiconductor device


A semiconductor device includes a first semiconductor layer on a substrate, a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including a nitride semiconductor doped with carbon, a third semiconductor layer on the second semiconductor layer, the third semiconductor layer including a nitride semiconductor doped with indium, and a fourth semiconductor layer on the third semiconductor layer, the fourth semiconductor layer including a nitride semiconductor having a band gap larger than a band gap of the third semiconductor layer. The concentration of indium in the third semiconductor layer is higher than 1×1018 cm−3 and lower than 1×1019 cm−3..
Kabushiki Kaisha Toshiba


07/21/16
20160211357 

Semiconductor device


A semiconductor device includes a first semiconductor layer on a substrate, a second semiconductor layer comprising a nitride semiconductor doped with p-type dopants on the first semiconductor layer, a third semiconductor layer comprising an undoped nitride semiconductor on the second semiconductor layer, a fourth semiconductor layer comprising an undoped nitride semiconductor on the third semiconductor layer, and a fifth semiconductor layer on the fourth semiconductor layer, the fifth semiconductor layer comprising a nitride semiconductor having a band gap greater than a band gap of the fourth semiconductor layer.. .
Kabushiki Kaisha Toshiba


07/21/16
20160211356 

Semiconductor device and semiconductor device manufacturing method


In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n− type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p+ type collector layer toward a p-type base layer, and the diffusion depth is 20 μm or more.
Fuji Electric Co., Ltd.


07/21/16
20160211355 

Semiconductor device


A semiconductor device of the present invention includes a semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode filled via a gate insulating film in the plurality of gate trenches, an n+-type emitter region, a p-type base region, and an n−-type drift region disposed, lateral to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, a p+-type collector region disposed on a back surface side of the semiconductor layer with respect to the n−-type drift region, an emitter trench formed between the plurality of gate trenches adjacent to each other, and a buried electrode filled via an insulating film in the emitter trench, and electrically connected with the n+-type emitter region, and the emitter trench is disposed at an interval of 2 μm or less via an n−-type drift region with the gate trench.. .
Rohm Co., Ltd.


07/21/16
20160211354 

Semiconductor device


A shield electrode is formed above a floating p region in a semiconductor layer and connected to a gate electrode in a trench. The shield electrode is composed of a material having an electrical resistivity lower than that of the gate electrode..
Fuji Electric Co., Ltd.


07/21/16
20160211353 

Method of manufacturing oxide thin film transistor


There is provided a method of manufacturing an oxide thin film transistor (tft). The method includes forming a gate electrode on a substrate, forming a gale insulating layer on the gate electrode, forming an oxide semiconductor layer including a channel layer on the gate insulating layer, forming a source electrode and a drain electrode separated from each other on the oxide semiconductor layer, first plasma processing the substrate on which the source electrode and the drain electrode are formed at a carbon (c) atmosphere, secondly plasma processing the substrate al a nitrogen oxide atmosphere, and sequentially forming a first protective layer and a second protective layer on the substrate..
Samsung Display Co., Ltd.


07/21/16
20160211349 

Semiconductor device and a manufacturing a semiconductor device


A semiconductor device includes a semiconductor substrate, a trench extending from a front surface toward a rear surface side of the semiconductor substrate, and an insulator filled in the trench. The semiconductor substrate is provided with in this order from the rear surface side toward the front surface, an n-type drift region, a p-type base region provided on a front surface side of the drift region, a p-type diffusion region provided on a front surface side of the base region and having a higher impurity concentration than that of the base region.
Toyota Jidosha Kabushiki Kaisha


07/21/16
20160211348 

Trench lateral diffusion metal oxide semiconductor device and manufacturing the same


A trench lateral diffusion metal oxide semiconductor (ldmos) device, disposed on a substrate, comprising: a transistor and an ldmos transistor. The transistor has a gate.
Maxchip Electronics Corp.


07/21/16
20160211347 

Method for semiconductor device fabrication


Provided is a method of forming a semiconductor device. The method includes providing a substrate; depositing a flowable dielectric material layer over the substrate; performing a wet annealing process and a dry annealing process to the flowable dielectric material layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/21/16
20160211346 

Epitaxial channel transistors and die with diffusion doped channels


semiconductor structures can be fabricated by implanting a screen layer into a substrate, with the screen layer formed at least in part from a low diffusion dopant species. An epitaxial channel of silicon or silicon germanium is formed above the screen layer, and the same or different dopant species is diffused from the screen layer into the epitaxial channel layer to form a slightly depleted channel (sdc) transistor.
Mie Fujitsu Semiconductor Limited


07/21/16
20160211345 

Bipolar junction transistor with multiple emitter fingers


Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed on the first semiconductor layer.
Globalfoundries Inc.


07/21/16
20160211344 

Modified self-aligned contact process and semiconductor device


A semiconductor device includes a transistor and a contact pad over a substrate. The transistor includes a high-k dielectric layer, a work function metal layer, a metal gate, two spacers, a metal compound, an insulator and a doped region.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/21/16
20160211343 

Implantation formed metal-insulator-semiconductor (mis) contacts


A method of forming a metal-insulator-semiconductor (mis) contact, a transistor including the mis contact, and the mis contact are described. The method includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region.
International Business Machines Corporation


07/21/16
20160211342 

Implantation formed metal-insulator-semiconductor (mis) contacts


A method of forming a metal-insulator-semiconductor (mis) contact, a transistor including the mis contact, and the mis contact are described. The method includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region.
International Business Machines Corporation


07/21/16
20160211340 

Implantation formed metal-insulator-semiconductor (mis) contacts


A method of forming a metal-insulator-semiconductor (mis) contact, a transistor including the mis contact, and the mis contact are described. The method includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region.
International Business Machines Corporation


07/21/16
20160211339 

Metal gate and manufacutring method thereof


The present disclosure provides a semiconductor structure, including an active region with a first surface; an isolated region having a second surface, surrounding the active region, the first surface being higher than the second surface; and a metal gate having a plurality of metal layers disposed over the first surface and the second surface. A ratio of a thinnest portion and a thickest portion of at least one of the plurality of metal layers is greater than about 40%..
Taiwan Semiconductor Manufacturing Company Ltd.


07/21/16
20160211338 

Semiconductor devices, finfet devices, and manufacturing methods thereof


semiconductor devices, fin field effect transistor (finfet) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/21/16
20160211336 

Semiconductor device with a semiconductor body containing hydrogen-related donors


A semiconductor device includes a semiconductor body with parallel first and second surfaces and containing hydrogen-related donors. A concentration profile of the hydrogen-related donors vertical to the first surface includes a maximum value of at least 1e15 cm−3 at a first distance to the first surface and does not fall below 1e14 cm−3 over at least 60% of an interval between the first surface and the first distance..
Infineon Technologies Ag


07/21/16
20160211335 

Semiconductor device


A semiconductor device includes a first semiconductor layer on a substrate, a second semiconductor layer containing an n-type dopant, on the first semiconductor layer, a third semiconductor layer having a resistance greater than a resistance of the second semiconductor layer, on the second semiconductor layer, a fourth semiconductor layer containing a nitride semiconductor, on the third semiconductor layer, and a fifth semiconductor layer containing a nitride semiconductor having a band gap greater than a band gap of the fourth semiconductor layer, on the fourth semiconductor layer.. .
Kabushiki Kaisha Toshiba


07/21/16
20160211334 

Silicon carbide semiconductor device and manufacturing same


A silicon carbide semiconductor device capable of decreasing an on-state resistance and improving a breakdown voltage. The silicon carbide semiconductor device includes: a drift layer of a first conductivity type made of a silicon carbide semiconductor; a depletion suppression layer of the first conductivity type formed on the drift layer and having a first conductivity type impurity concentration higher than that of the drift layer; a body region of a second conductivity type formed on the depletion suppression layer; a trench extending through the body region and the depletion suppression layer to reach the drift layer; and a gate insulation film formed along bottom and side surfaces of the trench.
Mitsubishi Electric Corporation


07/21/16
20160211333 

Silicon carbide semiconductor device and manufacturing the same


A sic semiconductor device includes a sic substrate, a gate insulating film formed on a surface of the sic substrate and made of sio2, and a gate electrode formed on the gate insulating film. A maximum value of a nitrogen concentration in a region within 10 nm from an interface between the sic substrate and the gate insulating film is greater than or equal to 3×1019 cm−3.
Sumitomo Electric Industries, Ltd.


07/21/16
20160211332 

Silicon carbide semiconductor device and manufacturing the same


A silicon carbide semiconductor device capable of achieving a high current gain with a simplified construction is provided. A silicon carbide layer includes a collector region, a base region, and an emitter region.
Sumitomo Electric Industries, Ltd.


07/21/16
20160211331 

Stress relieving semiconductor layer


A semiconductor structure, such as a group iii nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer.
Sensor Electronic Technology, Inc.


07/21/16
20160211325 

Semiconductor element, manufacturing same, and semiconductor integrated circuit


The present invention provides a semiconductor element that can be manufactured easily at a low cost, can obtain a high tunneling current, and has an excellent operating characteristic, a method for manufacturing the same, and a semiconductor integrated circuit including the semiconductor element. The semiconductor element of the present invention is characterized in that the whole or a part of a tunnel junction is constituted by a semiconductor region made of an indirect-transition semiconductor containing isoelectronic-trap-forming impurities..
National Institute Of Advanced Industrial Science And Technology


07/21/16
20160211324 

Semiconductor devices, and methods of forming semiconductor devices


Some embodiments include a device having an n-type diffusion region, and having a boron-doped region within the n-type diffusion region. The boron-doped region extends no deeper than about 10 nanometers from an upper surface of the n-type diffusion region.
Micron Technology, Inc.


07/21/16
20160211323 

Semiconductor device, manufacturing the same, and power module


A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.. .
Rohm Co., Ltd.


07/21/16
20160211320 

Semiconductor device, related manufacturing method, and related electronic device


A semiconductor device may include the following elements: a first doped portion; a second doped portion; an enclosing member, which encloses both the first doped portion and the second doped portion; a first barrier, which directly contacts the first doped portion; a second barrier, which directly contacts the second doped portion; a dielectric member, which is positioned between the first barrier and the second barrier and directly contacts each of the first barrier and the second barrier; a third barrier, which directly contacts the first doped portion; and a device component, wherein a portion of the device component is positioned between the dielectric member and the third barrier.. .
Semiconductor Manufacturing International (shanghai) Corporation


07/21/16
20160211319 

Semiconductor device


A semiconductor device includes a semiconductor substrate. The element region of the semiconductor substrate includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and a plurality of first floating regions, each the first floating regions having the first conductivity type.
Denso Corporation


07/21/16
20160211315 

Electro-optical device, driving electro-optical device, and electronic apparatus


A pixel circuit includes a driving transistor, a switching transistor, and a light emitting element, and the light emitting elements are formed on a semiconductor substrate. A first substrate potential is supplied to the switching transistor, and a second substrate potential, different from the first substrate potential, is supplied to the driving transistor..
Seiko Epson Corporation


07/21/16
20160211304 

Solid-state imaging device and electronic apparatus


A solid-state imaging device includes a semiconductor layer on which a plurality of pixels are arranged along a light-receiving surface being a main surface of the semiconductor layer, photoelectric conversion units provided for the respective pixels in the semiconductor layer, and a trench element isolation area formed by providing an insulating layer in a trench pattern formed on a light-receiving surface side of the semiconductor layer, the trench element isolation area being provided at a position displaced from a pixel boundary between the pixels.. .
Sony Corporation


07/21/16
20160211303 

Solid-state imaging device, manufacturing method thereof, and electronic apparatus


A solid-state imaging device includes a plurality of photoelectric conversion portions each provided in a semiconductor substrate and receives incident light through a light sensing surface, and a pixel separation portion provided to electrically separate a plurality of pixels. At least a pinning layer and a light shielding layer are provided in an inner portion of a trench provided on a side portion of each of the photoelectric conversion portions in an incident surface side, the trench includes a first trench and a second trench formed to be wider than the first trench in a portion shallower than the first trench, the pinning layer is formed in an inner portion of the first trench to cover an inside surface of the second trench, and the light shielding layer is formed to bury an inner portion of the second trench at least via the pinning layer..
Sony Corporation


07/21/16
20160211301 

Solid-state imaging device, manufacturing the same, and electronic equipment


A solid state imaging device including a semiconductor layer comprising a plurality of photodiodes, a first antireflection film located over a first surface of the semiconductor layer, a second antireflection film located over the first antireflection film, a light shielding layer having side surfaces which are adjacent to at least one of first and the second antireflection film.. .
Sony Corporation


07/21/16
20160211300 

Semiconductor integrated circuit, electronic device, solid-state imaging apparatus, and imaging apparatus


A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate..
Sony Corporation


07/21/16
20160211298 

Semiconductor device, manufacturing method thereof, solid-state imaging device, and electronic apparatus


A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.. .
Sony Corporation


07/21/16
20160211296 

Semiconductor device, solid state imaging element, and electronic apparatus


The present disclosure relates to a semiconductor device, a solid state imaging element, and an electronic apparatus in which the adverse effect due to hot carrier luminescence can be suppressed. In them, an element formation unit in which a plurality of elements are formed and an interconnection unit in which interconnections connecting elements are formed are stacked.
Sony Corporation


07/21/16
20160211295 

Blue enhanced image sensor


A back side illuminated image sensor includes a semiconductor material having a front side and a back side. The semiconductor material is disposed between image sensor circuitry and a light filter array.
Omnivision Technologies, Inc.


07/21/16
20160211294 

Solid-state imaging devices


A solid-state imaging device is provided. The solid-state imaging device includes a semiconductor substrate containing a plurality of photoelectric conversion elements.
Visera Technologies Company Limited


07/21/16
20160211292 

Method for manufacturing image pickup apparatus, and image pickup apparatus


A method for manufacturing an image pickup apparatus in which a second semiconductor region of first conductive type which becomes a well contact region is disposed adjacent to a first semiconductor region via an element isolation region in a pixel which has a well contact region among a plurality of pixels. A first mask which has openings in a region which becomes a first semiconductor region, an element isolation region disposed between the region which becomes the first semiconductor region and a region which becomes a second semiconductor region, and a region which becomes the second semiconductor region is disposed, and the first semiconductor region is formed in the region which becomes the first semiconductor region by conducting ion implantation of second conductive type at an oblique angle to a normal line of a principal surface using the first mask..
Canon Kabushiki Kaisha


07/21/16
20160211289 

Solid-state imaging device and manufacturing the same, and electronic apparatus


A trench is formed between pds so as to be opened to a light receiving surface side of a semiconductor substrate on which a plurality of the pds, each of which receives light to generate charges, are formed, an insulating film is embedded in the trench and the insulating film is laminated on a back surface side of the semiconductor substrate. Then, a light shielding portion is formed so as to be laminated on the insulating film and to have a convex shape protruding to the semiconductor substrate at a location corresponding to the trench.

07/21/16
20160211286 

Detection apparatus, detection system, and producing detection apparatus


A detection apparatus includes a plurality of conversion elements, an interlayer insulating layer, and a covering layer. Each of the plurality of conversion elements includes an electrode electrically connected to a corresponding one of a plurality of switching elements and a semiconductor layer disposed on the electrode.
Canon Kabushiki Kaisha


07/21/16
20160211284 

Method for fabricating array substrate


Embodiments of the invention provides a method for fabricating an array substrate comprising: forming, on a substrate, at least two semiconductor active islands, first patterns positioned on both sides of each of the semiconductor active islands, second patterns positioned at outer side of a part of the first patterns, and third patterns positioned at outer side of the rest of the first patterns, through a single patterning process; doping a semiconductor at the second patterns for once to form a semiconductor of a first conductivity type; and doping a semiconductor at the third patterns for once to form a semiconductor of a second conductivity type.. .
Boe Technology Group Co., Ltd.


07/21/16
20160211280 

Thin-film transistor array, fabrication method therefor, image display device and display method


A thin-film transistor array includes thin-film transistors each including an insulating substrate which is formed with a gate electrode, a gate wiring, a capacitor electrode and a capacitor wiring. A source electrode and a drain electrode having a gap therebetween and including a semiconductor pattern are formed, in a region overlapping with the gate electrode on the substrate via a gate insulator, with the semiconductor pattern being covered with a protective layer.
Toppan Printing Co., Ltd.


07/21/16
20160211278 

Semiconductor device, manufacturing method thereof, and display device


A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a tft which is in an on state is reduced to increase an on current.
Semicondudor Energy Laboratory Co., Ltd.


07/21/16
20160211276 

Semiconductor devices and manufacturing methods thereof


semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first fin field effect transistor (finfet) disposed over a substrate, and a second finfet device disposed over the first finfet.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/21/16
20160211275 

Display apparatus


Provided is a display apparatus capable of stably repairing a bright spot defect to be a black spot without decreasing an aperture ratio of an array substrate. The display device includes: a substrate having a plurality of semiconductor switching elements disposed thereon; a repair island pattern formed on the substrate; a pixel electrode formed to overlap with the repair island pattern in a plan view and not to come into contact with the repair island pattern; and a common electrode overlapping with the repair island pattern in a plan view and having a connection part for connecting the common electrode to the repair island pattern..
Mitsubishi Electric Corporation


07/21/16
20160211272 

Semiconductor structure with concave blocking dielectric sidewall and making thereof by isotropically etching the blocking dielectric layer


A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A spacer with a bottom opening is formed over the first blocking dielectric layer by deposition of a conformal material layer and an anisotropic etch.
Sandisk Technologies Inc.


07/21/16
20160211270 

Convex shaped thin-film transistor device having elongated channel over insulating layer


The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines and in a groove in the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed..
Cypress Semiconductor Corporation


07/21/16
20160211269 

Semiconductor device and manufacturing the same


A method of manufacturing a semiconductor device includes: forming an insulating film above a semiconductor substrate; forming a conductive film on the insulating film; forming a dielectric film on the conductive film; forming a plurality of upper electrodes at intervals on the dielectric film; forming a first protective insulating film on the upper electrodes and the dielectric film by a sputtering method; forming a second protective insulating film on the first protective insulating film by an atomic layer deposition method, thereby filling gaps of a grain boundary of the dielectric film with the second protective insulating film; and patterning the conductive film after the second protective insulating film is formed to provide a lower electrode.. .
Fujitsu Semiconductor Limited


07/21/16
20160211268 

Semiconductor integrated circuit device and a manufacturing the same


A semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.. .
Renesas Electronics Corporation


07/21/16
20160211267 

Semiconductor storage device


Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked.
Semiconductor Energy Laboratory Co., Ltd.


07/21/16
20160211266 

Memory device and electronic device


A memory device with excellent writing performance and excellent storing performance is provided. In the memory device, a first layer overlaps with a second layer.
Semiconductor Energy Laboratory Co., Ltd.


07/21/16
20160211265 

Single source/drain epitaxy for co-integrating nfet semiconductor fins and pfet semiconductor fins


A plurality of gate structures are formed straddling nfet semiconductor fins and pfet semiconductor fins which extend upwards from a surface of a semiconductor substrate. A boron-doped silicon germanium alloy material is epitaxially grown from exposed surfaces of both the nfet semiconductor fins and the pfet semiconductor fins not protected by the gate structures.
International Business Machines Corporation


07/21/16
20160211262 

Isolation well doping with solid-state diffusion sources for finfet architectures


An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin.

07/21/16
20160211261 

Method and structure for finfet devices


A semiconductor device and a method of forming the same are disclosed. The device comprises a semiconductor substrate comprised of a first semiconductor material and having a plurality of isolation features, thereby defining a first active region and a second active region; a first fin semiconductor feature comprised of a second semiconductor material and formed in the first active region; and a second fin semiconductor feature comprised of a second semiconductor material and formed in the second active region.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/21/16
20160211260 

Devices formed from a non-polar plane of a crystalline material and making the same


Materials, methods, structures and device including the same can provide a semiconductor device such as an led using an active region corresponding to a non-polar face or surface of iii-v semiconductor crystalline material. In some embodiments, an active diode region contains more non-polar iii-v material oriented to a non-polar plane than iii-v material oriented to a polar plane.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/21/16
20160211259 

Stacked device and associated layout structure


Stacked devices and circuits formed by stacked devices are described. In accordance with some embodiments, a semiconductor post extends vertically from a substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/21/16
20160211258 

Reverse-conducting gated-base bipolar-conduction devices and methods with reduced risk of warping


Reverse-conducting igbts where the collector side includes diode terminal regions, and the semiconductor material is much thicker through the diode terminal regions than it is through the collector regions. This exploits the area fraction which is taken up by the diode terminal regions to provide increased rigidity for the wafer, and thus avoid warping..
Maxpower Semiconductor Inc.


07/21/16
20160211257 

Semiconductor device


In an igbt portion, a first gate electrode is provided in a first trench via a first gate insulating film. A thickness of a first gate insulating film lower portion is thicker than a thickness of a first gate insulating film upper portion, whereby a width of a mesa portion between adjacent first trenches is narrower at a portion of a collector side than at an emitter side.
Fuji Electric Co., Ltd.


07/21/16
20160211256 

Semiconductor device


A power element and a temperature sensing element are formed on the same semiconductor substrate, and one end of a pn junction of the temperature sensing element is connected to a ground potential (vss) or a power supply potential (vdd) through an intermediation of a resistor. A sum of a potential difference between both ends of the pn junction and a potential difference between both ends of the resistor is used as a temperature detection signal.
Seiko Instruments Inc.


07/21/16
20160211255 

Semiconductor device and manufacturing same


A method of manufacturing a semiconductor device, comprising: providing a substrate; forming a first trough structure, which comprises at least a first sidewall, on the substrate; forming a first doping layer on the first sidewall; covering the first doping layer and a part of a surface of the substrate by a photoresist; forming a second trough structure, which comprises at least a second sidewall, on a part of the substrate which is not covered by the photoresist; removing the photoresist; forming an insulation layer on the substrate, the first trough structure, and the second trough structure; forming a conductive layer on the substrate, the first trough structure, and the second trough structure; and removing parts of the insulation layer and the conductive layer outside the first trough structure and the second trough structure to expose a surface of the first doping layer at the opening of the first trough structure.. .
Realtek Semiconductor Corporation


07/21/16
20160211252 

Semiconductor device


A semiconductor device includes a semiconductor layer having an element formation region in which a semiconductor element is formed. An element isolation well is formed in a surface portion of the semiconductor layer to isolate the element formation region.
Rohm Co., Ltd.


07/21/16
20160211251 

Semiconductor device layout, memory device layout, and manufacturing semiconductor device


A layout of a semiconductor device includes active area regions, gate electrodes crossing the plurality of active area regions, spacers along sides of the corresponding plurality of gate electrodes, a first contact patterning region, a second contact patterning region, and a contact area. The first contact patterning region overlaps at least one active area region among the plurality of active area regions, at least one gate electrode among the plurality of gate electrodes, and at least one spacer among the plurality of spacers, the at least one spacer corresponding to the at least one gate electrode.
Taiwan Semiconductor Manufacturing Company., Ltd.


07/21/16
20160211250 

Semiconductor substrate arrangement, a semiconductor device, and a processing a semiconductor substrate


According to various embodiments, a semiconductor substrate arrangement may be provided, wherein the semiconductor substrate arrangement may include: a semiconductor substrate defining a first area at a first level and a second area next to the first area at a second level, wherein the first level is lower than the second level; a plurality of planar non-volatile memory structures disposed over the semiconductor substrate in the first area; and a plurality of planar transistor structures disposed over the semiconductor substrate in the second area.. .
Infineon Technologies Ag


07/21/16
20160211248 

Hybrid bonding with uniform pattern density


A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/21/16
20160211246 

Semiconductor device and electronic apparatus


The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction fets using as a material, a substance larger in bandgap than silicon, and a normally-off mosfet using silicon as a material.
Renesas Electronics Corporation


07/21/16
20160211240 

Manufacturing ultra-thin semiconductor device package assembly


A manufacturing method of ultra-thin semiconductor device package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided, and one of the semiconductor devices has an active surface having an active region and an outer region and a back surface.
Niko Semiconductor Co., Ltd.


07/21/16
20160211236 

Semiconductor package and forming the same


semiconductor packages and methods of forming the same may be provided. According to the semiconductor package of the present inventive concepts, a bump attached to and protruded from a bonding pad on a surface of a semiconductor chip is inserted into a through-hole defined in a package substrate.

07/21/16
20160211235 

Bump structures, semiconductor device and semiconductor device package having the same


The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar.
Advanced Semiconductor Engineering, Inc.


07/21/16
20160211231 

Device and generating identification key


Provided is a device for generating an identification key using a process variation during a manufacturing process of a conductive layer. The device for generating an identification key may include a conductive layer, which is disposed between a first node and a second node in a semiconductor chip, and which has a width that is at least a first threshold value but not more than a second threshold value, the first threshold value and the second threshold value being less than the minimum width according to the design rules that can ensure that the conductive layer is patterned such that the first node and the second node are electrically short-circuited, and a reader which provides an identification key by identifying if there is a short circuit between the first node and the second node..
Ictk Co., Ltd.


07/21/16
20160211228 

Thermally curable resin sheet for sealing semiconductor chip, and manufacturing semiconductor package


10,000≦α×e′≦300,000 [pa/k]  (2).. .

07/21/16
20160211227 

Semiconductor device including a protection structure


A device includes a semiconductor chip including a dicing edge. The device further includes an active structure arranged in a semiconductor material of the semiconductor chip, and a protection structure arranged between the dicing edge and the active structure..
Infineon Technologies Ag


07/21/16
20160211226 

Integrated circuit and manufacturing an integrated circuit


In various embodiments, an integrated circuit is provided. The integrated circuit may include a semiconductor chip and an electrically conductive composite material fixed to the semiconductor chip, wherein the electrically conductive composite material may include a metal, and wherein a coefficient of thermal expansion (cte) value of the electrically conductive composite material may be lower than the cte value of the metal..
Infineon Technologies Ag


07/21/16
20160211225 

Semiconductor device and manufacturing method thereof


A semiconductor device includes a substrate, and a nitride semiconductor layer provided on the substrate. An opening is provided through the nitride semiconductor layer, and a portion of the opening extends inwardly of a side surface of the substrate and beneath the nitride semiconductor layer..
Kabushiki Kaisha Toshiba


07/21/16
20160211224 

System, method and apparatus to relieve stresses in a semiconductor wafer caused by uneven internal metallization layers


Systems and methods for forming semiconductor wafers with wafer support structures includes: multiple semiconductor devices formed in multiple semiconductor dies. An electrical interconnect structure is formed over the semiconductor devices and providing electrical connections to the semiconductor devices.
Sandisk Technologies Inc.


07/21/16
20160211223 

System, method and apparatus to relieve stresses in a semiconductor die caused by uneven internal metallization layers


A system, method and apparatus for making a semiconductor die includes forming multiple semiconductor devices in a respective portion of a semiconductor wafer. An electrical interconnect structure is formed over the semiconductor devices and provide electrical connections to the semiconductor devices.
Sandisk Technologies Inc.


07/21/16
20160211222 

Semiconductor packages having wire bond wall to reduce coupling


A device (e.g., a doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals..
Freescale Semiconductor, Inc.


07/21/16
20160211221 

Semiconductor device and manufacturing method thereof


A selectively shielded and/or three-dimensional semiconductor device and a method of manufacturing thereof. For example and without limitation, various aspects of this disclosure provide a semiconductor device that comprises a composite plate for selective shielding and/or a three-dimensional embedded component configuration..
Amkor Technology, Inc.


07/21/16
20160211219 

Semiconductor device with at least one truncated corner and/or side cut-out


A method of producing a substantially rectangular semiconductor device having at least one corner truncation or corner cut-out or side cut-out, comprises: a) providing a semiconductor substrate; b) making at least one opening through the substrate by means of etching; and c) cutting the substrate along a first pair of parallel lines, and along a second pair of parallel lines perpendicular to the first pair. At least one line of the first/second pair passes through said opening.
Melexis Technologies Nv


07/21/16
20160211217 

Sheet for sealing and manufacturing semiconductor device using said sheet for sealing


Provided is a thermosetting sheet for sealing which is used to seal an electronic device. One surface of the sheet has a surface roughness (ra) of 3 μm or less before the sheet is cured..
Nitto Denko Corporation


07/21/16
20160211215 

Semiconductor devices


semiconductor devices are provided. The semiconductor devices may include a first interconnection structure and a second interconnection structure which are disposed on a semiconductor substrate.
Samsung Electronics Co., Ltd.


07/21/16
20160211214 

Power amplifier package and method thereof


A device is provided, which includes a wiring structure including a first surface and a second surface opposite the first surface. The device also includes a first semiconductor die on the first surface of the wiring structure where the first semiconductor die includes first power amplifier unit.
Taiwan Semiconductor Manufacturing Company Ltd.


07/21/16
20160211211 

Semiconductor device and manufacturing the same


A semiconductor device is provided. The semiconductor device includes a first porous interlayer insulating film having a low dielectric constant and including a first region and a second region, a second interlayer insulating film formed on the first interlayer insulating film in the first region, a plurality of first conductive patterns formed in the second interlayer insulating film such that the plurality of first conductive patterns are spaced apart from each other, at least one second conductive pattern formed in the first interlayer insulating film in the second region and air gaps disposed at lateral sides of the plurality of first conductive patterns..
Samsung Electronics Co., Ltd.


07/21/16
20160211209 

Semiconductor structure and fabricating the same


A semiconductor structure and a method for fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate, a plurality of composite layers, and at least one composite pillar.
Powerchip Technology Corporation


07/21/16
20160211207 

Semiconductor assembly having wiring board with electrical isolator and moisture inhibiting cap incorporated therein and making wiring board


A method of making a wiring board is characterized by the provision of moisture inhibiting caps covering interfaces between an electrical isolator/optional metal posts and a surrounding plastic material. In a preferred embodiment, the electrical isolator and metal posts are bonded to the resin core by an adhesive substantially coplanar with the metal layers on two opposite sides of the resin core, the metal posts and a thermally conductive slug that includes the electrical isolator at smoothed lapped top and bottom surfaces, so that a metal bridge can be deposited on the adhesive at the smoothed lapped bottom surface to completely cover interfaces between the electrical isolator/metal posts and the surrounding plastic material.
Bridge Semiconductor Corporation


07/21/16
20160211206 

Multilayer structure for a semiconductor device and a forming a multilayer structure for a semiconductor device


A multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device. The multilayer structure comprises: a substrate having an electrically conductive portion thereon; a dielectric layer formed over the substrate; the dielectric layer comprising an opening over at least part of the electrically conductive portion; and a conductive pillar formed on the at least part of the electrically conductive portion; wherein the conductive pillar comprises walls defined by at least the opening of the dielectric layer and an opening of a patterned layer..
Institute Of Technical Education


07/21/16
20160211203 

Isolation a stand alone high voltage laterally-diffused metal-oxide semiconductor (ldmos) transistor


A semiconductor package having a lead frame over which a first device and a second device are spaced is provided. The lead frame includes a die pad upon which a first chip and a second chip are spaced and bonded.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/21/16
20160211202 

Semiconductor device


A miniaturized semiconductor device includes a frame body having an opening region formed in a central portion, an insulating substrate which is provided in the opening region of the frame body and on which semiconductor chips are mounted, lead portions, each including an inclined portion that is at least partially exposed to the opening region formed in the frame body and extends so as to be inclined with respect to an end surface forming the opening region, and a bonding wire that is bonded between the lead portion and the semiconductor chip by ultrasonic bonding.. .
Fuji Electric Co., Ltd.


07/21/16
20160211201 

Manufacturing and evaluation a semiconductor device


Provided is a method of manufacturing a semiconductor device which includes a semiconductor chip, an insulating board mounted with the semiconductor chip and having a wiring pattern, and a leadframe connected to the wiring pattern, the semiconductor chip, the wiring pattern and the leadframe being partially sealed with a sealing resin, wherein: an epoxy resin composition formed by adding 0.3 to 0.7 mass % of epoxysilane as a silane coupling agent to an epoxy resin is used as the sealing resin; and a copper member made of copper or a copper alloy and having an oxide film formed in the surface with a film thickness in a color indicated by an l* value in the range of 48 to 51, an a* value in the range of 40 to 49 and a b* value in the range of 24 to 40 is used as the leadframe and the wiring pattern.. .
Fuji Electric Co., Ltd.


07/21/16
20160211200 

Semiconductor device


One embodiment provides a semiconductor device having a first chip for lowering an input voltage and a second chip for performing signal processing, mounted on a die pad. Lead terminals are divided into a first lead row and a second lead row.
New Japan Radio Co., Ltd.


07/21/16
20160211198 

Manufacturing semiconductor device and semiconductor device


The present invention provides a semiconductor device and a method for manufacturing a semiconductor device. The method comprises: preparing a semiconductor chip 6 with a first electrode layer 21 formed on an element-forming surface 7.
Rohm Co., Ltd.


07/21/16
20160211196 

Method of producing a semiconductor package


A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer.
United Test And Assembly Center Ltd.


07/21/16
20160211194 

Semiconductor package structure and forming the same


A semiconductor package structure and method for forming the same are provided. The semiconductor package structure includes a substrate and the substrate has a front side and a back side.
Mediatek Inc.


07/21/16
20160211188 

Semiconductor packages, methods of manufacturing the same, electronic systems including the same, and memory cards including the same


A semiconductor package includes an adhesive member disposed on a package substrate to have a trapezoid cross-section view, and a semiconductor chip disposed on the adhesive member and attached to the package substrate by the adhesive member. The semiconductor chip has a first surface and a second surface facing the first surface, and the second surface of the semiconductor chip contacts the adhesive member.
Sk Hynix Inc.


07/21/16
20160211187 

Monitoring semiconductor device, performing deep n-typed well-correlated (dnw-correlated) antenna rule check of integrated circuit and semiconductor structure complying with dnw-correlated antenna rule


A semiconductor monitoring device includes a substrate, a die seal ring formed on the substrate, a deep n-typed well formed in the substrate under the die seal ring, and a monitoring device electrically connected to the die seal ring. The monitoring device is formed in a scribe line region defined on the substrate.
United Microelectronics Corp.


07/21/16
20160211186 

Plasma processing apparatus


A processing apparatus and a processing method for a semiconductor wafer, which allow stable end point detection, are provided. In the plasma processing apparatus or method in which a processing-target film layer of a film structure including a plurality of film layers formed in advance on a surface of a wafer mounted on a sample stage deployed within a processing chamber inside a vacuum vessel, by using plasma formed with the processing chamber, intensities of lights of a plurality of wavelengths are detected using data composed of results of reception of lights during a plurality of different time-intervals by an optical receiver which receives lights of the plurality of wavelengths from an inside of the processing chamber while processing is going..
Hitachi High-technologies Corporation


07/21/16
20160211183 

Semiconductor device with metal gate and high-k dielectric layer, cmos integrated circuit, and fabricating the same


A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.. .
Sk Hynix Inc.


07/21/16
20160211182 

Semiconductor device and manufacturing semiconductor device


A semiconductor device including: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes agate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.. .
Sony Corporation


07/21/16
20160211180 

Semiconductor piece manufacturing method


A semiconductor piece manufacturing method includes: a process of forming a fine groove on a front surface side including a first groove portion having a width that is gradually narrowed from a front surface of a semiconductor substrate w toward a rear surface thereof; a process of attaching a dicing tape having an adhesive layer on the front surface after the fine groove on the front surface side is formed; a process of forming a groove on a rear surface side having a width greater than the width of the fine groove on the front surface side along the fine groove on the front surface side from a rear surface side of the substrate by a rotating dicing blade; and a process of separating the dicing tape from the front surface after the groove on the rear surface side is formed.. .
Fuji Xerox Co., Ltd.


07/21/16
20160211179 

Method of processing a semiconductor substrate and semiconductor chip


A method of processing a semiconductor substrate is provided. The method may include forming a film over a first side of a semiconductor substrate, forming at least one separation region in the semiconductor substrate between a first region and a second region of the semiconductor substrate, arranging the semiconductor substrate on a breaking device, wherein the breaking device comprises a breaking edge, and wherein the semiconductor substrate is arranged with the film facing the breaking device and in at least one alignment position with the at least one separation region aligned with the breaking edge, and forcing the semiconductor substrate to bend the first region with respect to the second region over the breaking edge until the film separates between the breaking edge and the at least one separation region..
Infineon Technologies Ag


07/21/16
20160211178 

Method of dicing a wafer and semiconductor chip


A method of dicing a wafer may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the active regions extending from a first surface of the wafer into the wafer by a height and being separated by separation regions, the separation regions being free from metal, forming at least one trench in the wafer by plasma etching in at least one separation region from the first surface of the wafer. The at least one trench is extending into the wafer farther than the plurality of active regions.
Infineon Technologies Ag


07/21/16
20160211177 

Method of manufacturing thin-film transistor


According to one embodiment, a method of manufacturing a thin-film transistor includes forming a semiconductor layer on a gate electrode with an insulating layer 12 being interposed, forming interconnect formation layers on the semiconductor layer, forming a plurality of interconnects and electrodes by patterning the interconnect formation layers through etching, patterning the semiconductor layer in an island shape through etching after forming the electrodes, exposing a channel region of the semiconductor layer by etching a part of the electrodes on the semiconductor layer, and forming a protective layer so as to overlap the interconnects, the electrodes and the semiconductor layer having the island shape.. .
Japan Display Inc.


07/21/16
20160211175 

Method for fabricating semiconductor structure


A method for fabricating semiconductor structure is provided. A substrate having a plurality of blocks is provided.
Powerchip Technology Corporation


07/21/16
20160211174 

Etch damage and esl free dual damascene metal interconnect


A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/21/16
20160211173 

Semiconductor device and manufacturing semiconductor device


The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by cu or cu alloy, respectively..
Renesas Electronics Corporations


07/21/16
20160211170 

Fabrication of iii-v-on-insulator platforms for semiconductor devices


Embodiments of the present invention provide iii-v-on-insulator (iiivoi) platforms for semiconductor devices and methods for fabricating the same. According to one embodiment, compositionally-graded buffer layers of iii-v alloy are grown on a silicon substrate, and a smart cut technique is used to cut and transfer one or more layers of iii-v alloy to a silicon wafer having an insulator layer such as an oxide.
International Business Machines Corporation


07/21/16
20160211168 

Semiconductor devices including active patterns having different pitches and methods of fabricating the same


Methods for fabricating semiconductor devices are provided including sequentially stacking hardmask layers, a first sacrificial layer, and a second sacrificial layer on a substrate, forming first mandrels on the first sacrificial layer by etching the second sacrificial layer, forming first spacers on side walls of the first mandrels, forming a photoresist pattern disposed outside a region from which the first mandrels have been removed, forming second and third mandrels by etching the first sacrificial layer using the first spacers and the photoresist pattern as respective etching masks, forming second and third spacers on side walls of the second and third mandrels, forming first and second active patterns respectively having first and second pitches by etching the hardmask layer and at least a portion of the substrate, and forming a device isolation layer so that upper portions of the first and second active patterns protrude therefrom.. .

07/21/16
20160211167 

Semiconductor structure with airgap


A field effect transistor (fet) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate.
International Business Machines Corporation


07/21/16
20160211166 

Moveable edge coupling ring for edge process control during semiconductor wafer processing


A substrate processing system includes a processing chamber and a pedestal arranged in the processing chamber. An edge coupling ring is arranged adjacent to a radially outer edge of the pedestal.
Lam Research Corporation


07/21/16
20160211165 

Moveable edge coupling ring for edge process control during semiconductor wafer processing


A substrate processing system includes a processing chamber. A pedestal is arranged in the processing chamber.
Lam Research Corporation


07/21/16
20160211163 

Sheet for semiconductor processing


A semiconductor processing sheet, the sheet comprising a base material and a pressure sensitive adhesive layer laminated on at least one surface of the base material, the pressure sensitive adhesive layer being formed of a pressure sensitive adhesive composition, the pressure sensitive adhesive composition containing a polymer having a salt and an energy ray curable group and an energy ray curable pressure sensitive adhesive component (excluding the above polymer). The semiconductor processing sheet can suppress contamination of an adherent at the time of peeling after energy ray irradiation while exhibiting a sufficient antistatic property..
Lintec Corporation


07/21/16
20160211158 

Tank switch and monitoring a fluid rate


A tank switch for a semiconductor test system is provided, wherein the tank switch comprises a manifold comprising a first input pipe, a second input pipe, an output pipe and an flow sensor, wherein each of the input pipes is configured to be connected to a respective fluid tank and the output pipe comprises an output terminal which is configured to be connected to a testing handler, wherein each of the input pipes comprises a respective control valve; wherein the flow sensor is built into the manifold before the output terminal and is configured to provide a measurement signal indicative of the flow rate of a fluid through output terminal and to send the signal to a control unit; and wherein each of the control valves is configured to receive a control signal and to be opened or closed responsive to the received control signal.. .
Infineon Technologies Ag


07/21/16
20160211157 

Maintenance substrate processing apparatus, manufacturing semiconductor device, substrate processing apparatus, and storage medium capable of reading maintenance program of substrate processing apparatus


A maintenance method of a substrate processing apparatus includes a first processing step of carrying a first substrate holder holding a substrate into a process chamber and processing the substrate held by the first substrate holder within the process chamber, a second processing step of carrying a second substrate holder holding a substrate into the process chamber and processing the substrate held by the second substrate holder within the process chamber, a determination step of determining a replacement timing of the first substrate holder and the second substrate holder, and a maintenance step of, at the replacement timing determined at the determination step, replacing the first substrate holder and the second substrate holder respectively with a third substrate holder and a fourth substrate holder, if at least one of the first substrate holder and the second substrate holder reaches the replacement timing.. .
Hitachi Kokusai Electric Inc.


07/21/16
20160211156 

Ion beam etching system


The disclosed embodiments relate to methods and apparatus for removing material from a substrate. In various implementations, conductive material is removed from a sidewall of a previously etched feature such as a trench, hole or pillar on a semiconductor substrate.
Lam Research Corporation


07/21/16
20160211152 

Manufacturing semiconductor device


An object of the present invention is to improve the reliability and productivity of a semiconductor device by suppressing generation of a resin burr in a molding process. In a mold die, a tip-end surface of each push-up pin provided on the rear surface side of a lower die cavity block and a part of the rear surface of the lower die cavity block with which the tip-end surface of each push-up pin is contacted are inclined in such a manner that a distance to a top surface of the lower die cavity block becomes longer towards the pot side where mold resin is supplied.
Renesas Electronics Corporation


07/21/16
20160211151 

Substrate processing apparatus and manufacturing semiconductor device


Etching having high selectivity is performed within a plane of a substrate. To this end, a substrate processing apparatus includes a substrate support where a substrate including a first film containing at least silicon and a second film having a silicon content ratio lower than that of the first film is placed; a process chamber wherein the substrate support is disposed; a gas supply system configured to supply an etching gas to the substrate; a coolant channel disposed in the substrate support and having a coolant flowing therein; a coolant flow rate controller configured to control a flow rate of the coolant supplied to the coolant channel; a control unit configured to control at least the coolant flow rate controller such that a temperature of the substrate is maintained whereat an etch rate of the first film is higher than that of the second film while the etching gas is in contact with the substrate; and an exhaust system configured to exhaust an inner atmosphere of the process chamber..
Hitachi Kokusai Electric Inc.


07/21/16
20160211146 

Semiconductor manufacturing device, management method thereof, and manufacturing semiconductor device


Manufacturing yield of semiconductor device is improved by suppressing generation of foreign objects in a high-density plasma processing device. A high-density plasma cvd device includes an electrode, a guard ring surrounding an outer circumference of the electrode, an insulating member which is arranged over the guard ring and which surrounds the outer circumference of the electrode, and a plurality of spacers arranged between the guard ring and the insulating member.
Renesas Electronics Corporation


07/21/16
20160211145 

Method for etching group iii-v semiconductor and etching the same


Disclosed is a method for etching a group iii-v semiconductor, including irradiating, under an atmosphere of an organic gas, neutral particles to a group iii-v semiconductor layer formed on a substrate to cause a complex reaction, thereby etching the group iii-v semiconductor layer.. .
Tohoku Techno Arch Co., Ltd.


07/21/16
20160211143 

Curable composition for optical imprinting and pattern forming method


A curable composition for optical imprinting which is excellent in ink jet adequacy and releasability, a pattern forming method, a fine pattern, and a method for manufacturing a semiconductor device are provided. The curable composition for optical imprinting contains a polymerizable compound (a), a photopolymerization initiator (b), and a compound (c) expressed by general formula (i); in general formula (i), a represents a dihydric to hexahydric polyhydric alcohol residue.
Fujifilm Corporation


07/21/16
20160211140 

Method for processing a semiconductor surface


A method for processing a semiconductor includes irradiating a surface of a semiconductor with ions of a first gas type for cleaning the surface and implanting of ions of a second gas type in a region below the surface of the semiconductor for creating defects in the region below the surface. The irradiating and the implanting are performed within the same chamber..
Infineon Technologies Ag


07/21/16
20160211139 

Contact process and contact structure for semiconductor device


A contact process for a semiconductor device is described. A substrate having a doped region and a dielectric layer over the doped region is provided.
Macronix International Co., Ltd.


07/21/16
20160211135 

Method of manufacturing semiconductor device, substrate processing apparatus, substrate processing system and recording medium


There is provided a technique including: (a) forming a thin film containing a predetermined element, oxygen and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a source gas containing the predetermined element, carbon and a halogen element having a chemical bond between the predetermined element and carbon to the substrate; (a-2) supplying an oxidizing gas to the substrate; and (a-3) supplying a catalytic gas to the substrate; (b) removing a first impurity from the thin film by thermally processing the thin film at a first temperature higher than a temperature of the substrate in (a); and (c) removing a second impurity different from the first impurity from the thin film by thermally processing the thin film at a second temperature equal to or higher than the first temperature after performing (b).. .
Hitachi Kokusai Electric Inc.


07/21/16
20160211134 

Method of manufacturing semiconductor device


Provided is a technique of forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes: forming a first layer by supplying a gas containing a first element to the substrate, wherein the first layer is a discontinuous layer, a continuous layer, or a layer in which at least one of the discontinuous layer or the continuous layer is overlapped; forming a second layer including the first layer and a discontinuous layer including a second element stacked on the first layer; and forming a third layer by supplying a gas containing a third element to the substrate to modify the second layer under a condition where a modifying reaction of the second layer by the gas containing the third element is not saturated..
Hitachi-kokusai Electric Inc.


07/21/16
20160211133 

Method of manufacturing semiconductor device


Provided is a technique of forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes: forming a first layer by supplying a gas containing a first element to the substrate, wherein the first layer is a discontinuous layer, a continuous layer, or a layer in which at least one of the discontinuous layer or the continuous layer is overlapped; forming a second layer including the first layer and a discontinuous layer including a second element stacked on the first layer; and forming a third layer by supplying a gas containing a third element to the substrate to modify the second layer under a condition where a modifying reaction of the second layer by the gas containing the third element is not saturated..
Hitachi-kokusai Electric Inc.


07/21/16
20160211132 

Method of manufacturing semiconductor device


Provided is a technique of forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes: forming a first layer by supplying a gas containing a first element to the substrate, wherein the first layer is a discontinuous layer, a continuous layer, or a layer in which at least one of the discontinuous layer or the continuous layer is overlapped; forming a second layer including the first layer and a discontinuous layer including a second element stacked on the first layer; and forming a third layer by supplying a gas containing a third element to the substrate to modify the second layer under a condition where a modifying reaction of the second layer by the gas containing the third element is not saturated..
Hitachi-kokusai Electric Inc.


07/21/16
20160211043 

Systems and methods for regulating electrical power generated from a decay of radiation-emitting isotopes


Systems and methods are presented for regulating electrical power generated from a decay of radiation-emitting isotopes. The systems include a diode formed of a semiconductor material capable of mitigating radiation damage by operating at temperatures greater than 300° c.
Idaho State University


07/21/16
20160211042 

Devices and methods for converting energy from radiation into electrical power


Devices and methods are presented for converting energy from radiation into electrical power. In one illustrative embodiment, a device for converting energy from radiation into electrical power includes a diode formed of a semiconductor material capable of mitigating radiation damage by operating at temperatures greater than 300° c.
Idaho State University


07/21/16
20160211026 

Memory with output control


An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device.
Conversant Intellectual Property Management Inc.


07/21/16
20160211025 

Semiconductor memory device and operating method thereof


The invention relates to a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a first plane and a second plane each including a plurality of memory blocks, a first read and write circuit and a second read and write circuit suitable for sensing and temporarily storing data programmed into the first and second planes, respectively, and a control logic suitable for controlling the first and second read and write circuits to perform a read operation on the first and second planes, respectively, wherein the control logic controls the first and second read and write circuits to set the temporarily stored data as setting data, performs a new read operation to store new data, or maintains the temporarily stored data, depending on whether the first and second planes are in an lsb program state or an msb program state..
Sk Hynix Inc.


07/21/16
20160211021 

Irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus


An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus are provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region.
The United States Of America As Represented By The Secretary Of The Navy


07/21/16
20160211010 

Three-dimensional wordline sharing memory


A semiconductor memory includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be above or below the wordline and be coupled to different bit lines..
Taiwan Semiconductor Manufacturing Co., Ltd.


07/21/16
20160211007 

Semiconductor memory device


According to one embodiment, a semiconductor memory device includes first, second, third and fourth mos transistors, and first and second precharge circuits. A memory cell includes the first, second, third and fourth mos transistors.
Kabushiki Kaisha Toshiba




Semiconductor topics: Semiconductor, Semiconductor Substrate, Semiconductor Device, Semiconductor Material, Electric Conversion, Conductive Layer, Molybdenum, Camera Module, Semiconductor Devices, Semiconductors, Integrated Circuit, Surfactant, Photoelectric Conversion, Electronic Device, Transparent Conductive Oxide

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