Popular terms

[SEARCH]

Semiconductor topics
Semiconductor
Semiconductor Substrate
Semiconductor Device
Semiconductor Material
Electric Conversion
Conductive Layer
Molybdenum
Camera Module
Semiconductor Devices
Semiconductors
Integrated Circuit
Surfactant
Photoelectric Conversion
Electronic Device
Transparent Conductive Oxide

Follow us on Twitter
twitter icon@FreshPatents

Web & Computing
Cloud Computing
Ecommerce
Search patents
Smartphone patents
Social Media patents
Video patents
Website patents
Web Server
Android patents
Copyright patents
Database patents
Programming patents
Wearable Computing
Webcam patents

Web Companies
Apple patents
Google patents
Adobe patents
Ebay patents
Oracle patents
Yahoo patents

[SEARCH]

Semiconductor patents



      
           
This page is updated frequently with new Semiconductor-related patent applications. Subscribe to the Semiconductor RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor RSS RSS


Method for making contact between a semiconductor material and a contact layer

Toshiba

Memory device and method of manufacturing memory device


Date/App# patent app List of recent Semiconductor-related patents
07/23/15
20150208524 
 Semiconductor device patent thumbnailnew patent Semiconductor device
A connecting terminal includes an external terminal connecting portion, having an end surface to connect an external terminal thereto and located at a second principal surface side of a second circuit board faces, and a substrate-fixed portion which is securely connected to a first circuit board. A seal attachment portion is provided on a portion of the external terminal connecting portion including the end surface to attach thereto a seal member to seal a gap between the portion and the case.
Kabushiki Kaisha Toyota Jidoshokki


07/23/15
20150208507 
 Device including interposer between semiconductor and substrate patent thumbnailnew patent Device including interposer between semiconductor and substrate
A device including a semiconductor, a substrate, and an interposer. The interposer is attached between the semiconductor and the substrate to absorb stresses between the semiconductor and the substrate..
Hewlett-packard Development Company, L.p.


07/23/15
20150208501 
 Wiring board and  manufacturing same patent thumbnailnew patent Wiring board and manufacturing same
To provide a wiring board excellent in connection reliability with a semiconductor chip. A first buildup layer 31 where resin insulating layers 21 and 22 and a conductor layer 24 are laminated is formed at a substrate main surface 11 side of an organic wiring board 10.
Ngk Spark Plug Co., Ltd.


07/23/15
20150208500 
 Semiconductor device patent thumbnailnew patent Semiconductor device
A semiconductor device includes a terminal electrode and a terminal electrode placement member. The terminal electrode includes a substrate-fixed portion secured to the circuit substrate through a fastening member, and an external wiring connection portion to which an external wiring is connected.
Kabushiki Kaishi Toyota Jidoshokki


07/23/15
20150208476 
 Light source control device patent thumbnailnew patent Light source control device
A semiconductor light source control device includes a driver circuit, which generates a drive current iout flowing through a plurality of leds connected in series and which performs control such that the amount of the drive current is brought close to a target value, and bypass switches, which are on-off controlled by a control signal, the bypass switches being connected in parallel with the corresponding leds. The semiconductor light source control device is configured such that when the control signal indicates the off-state of the bypass switches, a voltage across the corresponding leds is clamped at an upper limit by using the bypass switches..
Koito Manufacturing Co., Ltd.


07/23/15
20150208467 
 Induction heating generator and an induction cooking hob patent thumbnailnew patent Induction heating generator and an induction cooking hob
The present invention relates to an induction heating generator. The induction heating generator comprises or corresponds with a rectifier circuit (10).
Electrolux Home Products Corporation N. V.


07/23/15
20150208011 
 Photodetector comprising a pinned photodiode that is formed by an optically sensitive layer and a silicon diode patent thumbnailnew patent Photodetector comprising a pinned photodiode that is formed by an optically sensitive layer and a silicon diode
In various embodiments, a photodetector includes a semiconductor substrate and a plurality of pixel regions. Each of the plurality of pixel regions comprises an optically sensitive layer over the semiconductor substrate.
Invisage Technologies, Inc.


07/23/15
20150207629 
 Semiconductor device and  writing data to semiconductor device patent thumbnailnew patent Semiconductor device and writing data to semiconductor device
A semiconductor device in related art has a problem that security at the time of writing data cannot be sufficiently assured. A semiconductor device of the present invention has: a unique code generating unit generating an initial unique code which is a value unique to a device and includes an error in a random bit; a first error correcting unit correcting an error in the initial unique code to generate an intermediate unique code; a second error correcting unit correcting an error in the intermediate unique code to generate a first determinate unique code; and a decrypting unit decrypting, with the first determinate unique code, transmission data obtained by encrypting confidential information with key information generated on the basis of the intermediate unique code by an external device to generate confidential information..
Renesas Electronics Corporation


07/23/15
20150207627 
 Semiconductor integrated circuit, authentication system, and authentication method patent thumbnailnew patent Semiconductor integrated circuit, authentication system, and authentication method
A semiconductor integrated circuit includes a first circuit configured to provide a predetermined function and a second circuit configured to have a physically unclonable function, wherein the second circuit is incorporated into the first circuit such that a signal value of at least one node in the first circuit varies in response to an output of the second circuit, and the output of the second circuit is set such that the first circuit provides the predetermined function.. .
Fujitsu Limited


07/23/15
20150207565 
 Interface circuit for transmitting and receiving signals between electronic devices, and semiconductor memory chip and operation processing device including the same patent thumbnailnew patent Interface circuit for transmitting and receiving signals between electronic devices, and semiconductor memory chip and operation processing device including the same
An interface circuit configured to transmit and receive signals between electronic devices is provided. The interface circuit includes an optical connection protocol manager configured to serialize a parallel transmission packet electrical signal generated based on output data to generate a serialized transmission packet electrical signal, parallelize a serial reception packet electrical signal to generate a parallelized reception packet electrical signal, and parse the parallelized reception packet electrical signal according to whether there is an error in the parallelized reception packet electrical signal to generate input data; and an electro-optical converter configured to convert the serialized transmission packet electrical signal into a transmission packet optical signal to output the transmission packet optical signal, receive a reception packet optical signal, and convert the reception packet optical signal into the serial reception packet electrical signal to provide the serial reception packet electrical signal to the optical connection protocol manager..
Electronics And Telecommunications Research Institute


07/23/15
20150207505 
new patent

Semiconductor device including enhanced variability


A physical unclonable function (puf) semiconductor device includes a semiconductor substrate, and a well formed in the semiconductor substrate. The well includes a first region having a first concentration of ions, and at least one second region having a second concentration that is less than the first concentration.
International Business Machines Corporation


07/23/15
20150207494 
new patent

Semiconductor circuit and operating the circuit


Provided is a semiconductor circuit which includes a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch input node, and a voltage level of a clock signal, a second circuit configured to pre-charge the latch input node based on the voltage level of the clock signal, a third circuit configured to pull down the latch input node based on the voltage level of the feedback node and the voltage level of the clock signal, a latch configured to output output data based on the voltage level of the clock signal and the voltage level of the latch input node, and a control circuit included in at least one of the first to third circuits and the latch and configured to receive the control signal.. .

07/23/15
20150207445 
new patent

Semiconductor device and driving apparatus


In a drive system using a single synchronous motor which is not paired with a synchronous generator, even if a failure occurs in an analog angle data converter for detecting the rotation angle of the synchronous motor, the driving of the synchronous motor can be continued in a temporal emergency manner. In addition to an analog angle data converter for converting an analog sense signal which is output from a rotation angle sensor of a synchronous motor to digital angle data, a digital angle data converter for converting digital data generated by an analog-to-digital converter to digital angle data is provided.
Renesas Electronics Corporation


07/23/15
20150207407 
new patent

Semiconductor device, semiconductor module, and electronic circuit


According to one embodiment, in semiconductor device, first semiconductor region is provided between first electrode and second electrode. Second semiconductor region is provided between first semiconductor region and second electrode.
Kabushiki Kaisha Toshiba


07/23/15
20150207364 
new patent

Microwave energy converter


A microwave energy converter, including at least one semiconductor and ohmic contact electrodes. The semiconductor acts as both a microwave receiving unit and a microwave rectifying unit of the microwave energy converter.
Sichuan University


07/23/15
20150207310 
new patent

Direct current voltage switch for switching a direct current in a branch of a direct current voltage network node


A device switches a direct current in a branch of a direct current voltage network node. The device contains a constant current path extending between two connection terminals, in which a mechanical switch is disposed.
Siemens Aktiengesellschaft


07/23/15
20150207298 
new patent

Method for producing semiconductor optical device


A method for producing a semiconductor optical device includes the steps of forming a first semiconductor substrate having a stacked semiconductor layer; adjusting a proportion of h2o molecules in a process chamber, the process chamber having an inner surface on which an alumite film is formed by anodizing; and, after the step of adjusting the proportion of h2o molecules, forming a substrate product by arranging the first semiconductor substrate in the process chamber and etching the stacked semiconductor layer using a dry etching method in which a halogen-based gas is used as an etching gas. In addition, the step of adjusting the proportion of h2o molecules in the process chamber includes a first substep of evacuating the process chamber; a second substep of dry-cleaning the inner surface of the process chamber; and a third substep of generating a plasma in the process chamber using a halogen-based gas..
Sumitomo Electric Industries, Ltd.


07/23/15
20150207296 
new patent

Tunable soi laser


A wavelength tunable silicon-on-insulator (soi) laser comprising: a laser cavity including: a semiconductor gain medium having a front end and a back end; and a phase-tunable waveguide platform coupled to the front end of the semiconductor gain medium; wherein the phase-tunable waveguide platform includes a first distributed bragg reflector (dbr) and a second distributed bragg reflector (dbr); at least one of the distributed bragg reflectors having a comb reflectance spectrum; and wherein a mirror of the laser cavity is located at the back end of the semiconductor gain medium.. .
Rockley Photonics Limited


07/23/15
20150207293 
new patent

Method of producing a semiconductor laser element, and semiconductor laser element


A method of producing a semiconductor laser element includes a) providing at least one carrier assemblage having a multiplicity of carriers for the semiconductor laser elements, c) providing at least one laser bar having a multiplicity of semiconductor laser diodes which include a common growth substrate and a semiconductor layer sequence grown thereon, d) fitting the laser bar on a top side of the carrier assemblage, and e) singulating to form the semiconductor laser elements after d).. .
Osram Opto Semiconductors Gmbh


07/23/15
20150207291 
new patent

Tunable soi laser


A wavelength tunable silicon-on-insulator (soi) laser comprising: a laser cavity including: a semiconductor gain medium having a front end and a back end, wherein a mirror of the laser cavity is located at the back end of the semiconductor gain medium; and a phase-tunable waveguide platform coupled to the front end of the semiconductor gain medium, the phase-tunable waveguide platform comprising: a first resonator and a second resonator; at least one resonator being a phase-tunable resonator; wherein the first resonator is any one of: an mmi device including a pair of reflective surfaces defining a resonator cavity therebetween such that the device is configured to act as a fabry-perot filter; a ring resonator; or a waveguide fabry-perot filter; and wherein the second resonator is any one of: an mmi device including a pair of reflective surfaces defining a resonator cavity therebetween such that the device is configured to act as a fabry-perot filter; a ring resonator; or a waveguide fabry-perot filter.. .
Rockley Photonics Limited


07/23/15
20150207106 
new patent

High efficiency organic light emitting devices


A method for producing high efficiency organic light emitting devices, that have an organic semiconductor active layer sandwiched between electrodes where at least one of the electrodes is a film of conductive nanowires, carbon nanoparticles, light scattering nanoparticles and a polymer support. The light scattering nanoparticles can be incorporated in the conductive nanowires, carbon nanoparticle or polymer support elements of the electrode.
The Regents Of The University Of California


07/23/15
20150207103 
new patent

Light-emitting device


Organic semiconductor layers comprise between a first electrode and a photoelectric converting layer a light extraction improving layer that contains at least silver or gold in part as a component, partially reflects light, and has transparency. The light extraction improving layer is in contact with or is inserted into a functional layer containing, for example, an organic semiconductor material, an oxide, a fluoride, or an inorganic compound having strong acceptor properties or strong donor properties with an ionization potential of 5.5 ev or higher, within the organic semiconductor layers..
Pioneer Corporation


07/23/15
20150207094 
new patent

Display panel and display device


A display panel and a display device, such as an organic light emitting panel that includes a spacer. The display panel and the display device include a semiconductor element including a first electrode; a passivation layer arranged on the semiconductor element and including a via hole exposing the first electrode; a second electrode arranged on the passivation layer and connected to the first electrode through the via hole; and a spacer arranged on the second electrode and adjacent to the via hole, wherein the spacer exposes at least a portion of a region where the via hole is formed..
Samsung Display Co., Ltd.


07/23/15
20150207087 
new patent

Photoelectric conversion element, imaging device, and optical sensor


The photoelectric conversion element is formed by providing an organic photoelectric conversion portion including two or more types of organic semiconductor materials having different spectral sensitivities between the first and the second electrodes. Wavelength sensitivity characteristics of the photoelectric conversion element change according to a voltage (bias voltage) applied between the first and the second electrodes.

07/23/15
20150207076 
new patent

Polymers of benzodithiophene and their use as organic semiconductors


The invention relates to novel polymers of benzodithiophene, methods and materials for their preparation, their use as semiconductors in organic electronic (oe) devices, and to oe devices comprising these polymers.. .
Merck Patent Gmbh


07/23/15
20150207074 
new patent

Deposition method and a deposition apparatus of fine particles, a forming method and a forming apparatus of carbon nanotubes, and a semiconductor device and a manufacturing the same


A deposition method of fine particles, includes the steps of irradiating a fine particle beam formed by size-classified fine particles to an irradiated subject under a vacuum state, and depositing the fine particles on a bottom part of a groove structure formed at the irradiated subject.. .
Fujitsu Limited


07/23/15
20150207073 
new patent

Semiconductor memory apparatus and fabrication method thereof


semiconductor memory apparatus and a method of fabricating the same are provided. The semiconductor memory apparatus includes a semiconductor substrate in which a cell area and a peripheral area are defined, a plurality of pillars formed in the a cell area of the semiconductor substrate to a first depth, a stepped part formed in the peripheral area to a height corresponding to the first depth, a recessed part formed in the stepped part to a second depth, and a core switching device formed in the recessed part..
Sk Hynix Inc.


07/23/15
20150207072 
new patent

Memory device and manufacturing memory device


According to one embodiment, a memory device includes a first conductive line extending in a first direction, second conductive lines each extending in a second direction intersect with the first direction, a third conductive line extending in a third direction intersect with the first and second directions, an insulating layer disposed between the second conductive lines and the third conductive line, resistance change elements each disposed on one of first and second surfaces of each of the second conductive lines in the third direction, and each connected to the third conductive line, a semiconductor layer connected between the first conductive line and one end of the third conductive line, and a select fet having a select gate electrode, and using the semiconductor layer as a channel.. .
Kabushiki Kaisha Toshiba


07/23/15
20150207063 
new patent

Semiconductor device


The present invention provides a magnetoresistive effect element which performs writing by a novel method. In a state in which a current does not flow in a magnetization free layer mfr, the magnetization free layer mfr has a magnetic wall mw1 on the side of a magnetization fixed layer mfx1.
Renesas Electronics Corporation


07/23/15
20150207053 
new patent

Apparatus and harvesting energy in an electronic device


An apparatus, a method, and a computer program product are provided. The apparatus may be an electronic component.
Qualcomm Incorporated


07/23/15
20150207051 
new patent

Semiconductor light emitting device


A semiconductor light emitting device includes a stacked semiconductor structure including a first conductivity-type semiconductor layer having a top surface divided into a first region and a second region, and an active layer and a second conductivity-type semiconductor layer disposed sequentially on the second region of the first conductivity-type semiconductor layer. First and second contact electrodes are disposed in the first region of the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, respectively.

07/23/15
20150207050 
new patent

Semiconductor package and manufacturing method thereof


For a semiconductor package mounted on a mounting member with wiring which connects an electrode on the upper surface of an led device (semiconductor device) and an electrode at the mounting member side formed by a droplet discharge method or printing method, a stress relaxation film to reduce stresses applied to the wiring due to the difference in expansion/contraction between a land at the level difference sections and the wiring is formed at least at the level difference sections in the land which forms wiring, and the wiring is formed by a droplet discharge method or printing method on the stress relaxation film. The stress relaxation film may be formed of an insulating material for which the difference of the linear expansion coefficient from wiring is as small as possible and for which the young's modulus is as large as possible..
Fuji Machine Mfg Co., Ltd.


07/23/15
20150207046 
new patent

Light emitting device and manufacturing light emitting device


Provided is a light emitting device having a phosphor layer on a surface of a semiconductor light emitting element and reducing unevenness in light distribution color, and a method of manufacturing the same. A light emitting device 100 includes a light emitting element 20 with a supporting body which is composed of a semiconductor light emitting element 1 and a supporting body 10, and a phosphor layer 7 which continuously covers an upper surface and side surfaces of the semiconductor light emitting element 1, and side surfaces of the supporting body 10.
Nichia Corporation


07/23/15
20150207044 
new patent

Method for producing an optoelectronic component


A method for producing a plurality of optoelectronic components (100) comprises the steps: providing a semiconductor body (101) that is arranged on a carrier (114); and applying a converter material (105) to the semiconductor body (101) by means of a photoconductive transfer element (120).. .
Osram Opto Semiconductors Gmbh


07/23/15
20150207042 
new patent

Light emitting device and manufacturing light emitting device


A method of manufacturing a light emitting device includes preparing wafer with a plurality of light emitting elements arrayed on a growth substrate, on a first side of a semiconductor stacked layer body, forming a resin layer which includes metal wires respectively connected to a p-side electrode and an n-side electrode, forming a groove by removing at least portion of the resin layer from an upper surface side in a boundary region between the light emitting elements and exposing end surfaces of metal wires which are internal conductive members on an inner side surface defining a groove, forming electrodes for external connection respectively connecting to exposed end surfaces of metal wires, and singulating the wafer into a plurality of singulated light emitting elements.. .
Nichia Corporation


07/23/15
20150207041 
new patent

Phosphor separated from led by transparent spacer


To reduce absorption by an led die (12) of light emitted by a phosphor layer (48), the absorbing semiconductor layers of the led die (12) are separated from the phosphor layer by a relatively thick glass plate (44) affixed to the led die or by the led die transparent growth substrate. Therefore, phosphor light emitted at a sufficient angle towards the led die will pass through the transparent spacer (44) and exit the sidewalls of the spacer, preventing the light from being absorbed by the led die.
Koninklijke Philips N.v.


07/23/15
20150207039 
new patent

Light emitting diode chip having distributed bragg reflector and fabricating the same


A light-emitting diode chip configured to emit light of a first wavelength range and light of a second wavelength range, including a substrate, a light-emitting structure disposed on a first surface of the substrate, the light-emitting structure including an active layer disposed between a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer, and configured to emit light of the first wavelength range, and first and second distributed bragg reflectors (dbrs) disposed on a second surface of the substrate. The first dbr is disposed closer to the substrate than the second dbr, the first wavelength range comprises a blue wavelength range, the first dbr comprises a higher reflectivity for light of the second wavelength range than for light of the first wavelength range, and the second dbr comprises a higher reflectivity for light of the first wavelength range than for light of the second wavelength range..
Seoul Viosys Co., Ltd.


07/23/15
20150207038 
new patent

Semiconductor light-emitting device


A semiconductor light-emitting device includes a first conductive type semiconductor layer having a main surface, a plurality of vertical type light-emitting structures protruding upward from the first conductive type semiconductor layer; a transparent electrode layer covering the plurality of vertical type light-emitting structures; and an insulation-filling layer disposed on the transparent electrode layer. The insulation-filling layer extends parallel to the first conductive type semiconductor layer so as to cover the plurality of vertical type light-emitting structures.
Samsung Electronics Co., Ltd.


07/23/15
20150207037 
new patent

Nanowire sized opto-electronic structure and manufacturing the same


An opto-electric structure includes a plurality of nano elements arranged side by side on a support layer, where each nano element includes at least a first conductivity type semiconductor nano sized core, and where the core and a second conductivity type semiconductor form a pn or pin junction. A first electrode layer that extends over the plurality of nano elements and is in electrical contact with at least a portion of the second conductivity type semiconductor, and a mirror provided on a second conductivity type semiconductor side of the structure..
Glo Ab


07/23/15
20150207035 
new patent

Light-emitting element having a tunneling structure


A light-emitting element includes a first light-emitting stacked structure including a first active layer; and a tunneling structure on the light-emitting stacked structure including a first doped semiconductor layer; a first undoped semiconductor layer on the first doped semiconductor layer; a second undoped semiconductor layer on the first undoped semiconductor layer; a third undoped semiconductor layer between the first undoped semiconductor layer and the second undoped semiconductor layer, wherein the third undoped semiconductor layer includes a material different from that of the first undoped semiconductor layer; and a second doped semiconductor layer on the second undoped semiconductor layer, having a different conductivity from that of the first doped semiconductor layer; wherein the tunneling structure has a polarization field enhanced by the third undoped semiconductor layer.. .
Epistar Corporation


07/23/15
20150207034 
new patent

Semiconductor light emitting device


A semiconductor light emitting device may include a base semiconductor layer formed on a substrate and having defect regions therein; cavities disposed in regions corresponding to the defect regions on the base semiconductor layer; a capping layer disposed to cover at least one region of the base semiconductor layer and the cavities; and a light emitting structure disposed on the capping layer and including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. Lattice defects formed in the light emitting structure may be reduced to enhance luminous efficiency..
Samsung Electronics Co., Ltd.


07/23/15
20150207033 
new patent

Nanopyramid sized opto-electronic structure and manufacturing of same


Aspects of the invention provide methods and devices. In one embodiment, the invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, leds and transistors.
Glo Ab


07/23/15
20150207031 
new patent

Semiconductor light emitting structure


A semiconductor light emitting structure is provided. The semiconductor light emitting structure comprises a substrate, a first semiconductor layer, an active layer and a second semiconductor layer.
Lextar Electronics Corporation


07/23/15
20150207030 
new patent

Semiconductor light emitting structure


A semiconductor light emitting structure comprising a substrate, a patterned structure, a first semiconductor layer, an active layer and a second semiconductor layer is provided. The substrate has a first surface and a second surface opposite to the first surface.
Lextar Electronics Corporation


07/23/15
20150207028 
new patent

Iii-nitride nanowire led with strain modified surface active region and making thereof


A light emitting diode (led) device includes a semiconductor nanowire core, and an in(al)gan active region quantum well shell located radially around the semiconductor nanowire core. The active quantum well shell contains indium rich regions having at least 5 atomic percent higher indium content than indium poor regions in the same shell.
Glo Ab


07/23/15
20150207027 
new patent

Semiconductor component and process for fabricating a semiconductor component


A semi-conducting component including a semi-conducting layer of a first conductivity type including a plurality of semi-conducting zones of a second conductivity type opposite that of the semi-conducting layer, and an insulating layer. The component further includes a first bias mechanism configured to bias the semi-conducting layer and a second bias mechanism configured to bias a semi-conducting zone.
Commissariat A L'energie Atomique Et Aux Ene Alt


07/23/15
20150207026 
new patent

Method of manufacturing semiconductor light emitting device


A method of manufacturing a semiconductor light emitting device includes forming a light emitting structure layer including an active layer on a first substrate. A second substrate is bonded to the light emitting structure layer at a first temperature higher than room temperature.
Samsung Electronics Co., Ltd.


07/23/15
20150207025 
new patent

Method of manufacturing semiconductor light emitting device and manufacturing semiconductor light emitting device package


A method of manufacturing a semiconductor light emitting device includes forming, on a substrate, a first region of a light emitting structure and the light emitting structure includes a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. A protective layer is formed on the first region in a first chamber.

07/23/15
20150207023 
new patent

A fabricating pixelated silicon device cells


A method, apparatus and system for flexible, ultra-thin, and high efficiency pixelated silicon or other semiconductor photovoltaic solar cell array fabrication is disclosed. A structure and method of creation for a pixelated silicon or other semiconductor photovoltaic solar cell array with interconnects is described using a manufacturing method that is simplified compared to previous versions of pixelated silicon photovoltaic cells that require more microfabrication steps..
Sandia Corporation


07/23/15
20150207022 
new patent

System for the production of single crystal semiconductors and solar panels using the single crystal semiconductors


A process and the required technical arrangement has been developed to produce single crystal solar panels or otherwise used semiconductors, which starts with the raw material to produce single crystal copper ribbons, extruded directly from the melt, with unharmed and optical surfaces onto which in the next unit a silicon or germanium film will be deposited. In the next unit the copper ribbon will be removed from the silicon film, whilst a hard plastic support or ceramic support is mounted, leaving copper contours on the silicon film to be used as electrical conductors or contacts.
Grain Free Products, Inc.


07/23/15
20150207015 
new patent

Apparatus and optically initiating collapse of a reverse biased p-type-n-type junction


An optical method of collapsing the electric field of an innovatively fabricated, reverse-biased pn junction causes a semiconductor switch to transition from a current blocking mode to a current conduction mode in a planar electron avalanche. This switch structure and the method of optically initiating the switch closure is applicable to conventional semiconductor switch configurations that employ a reverse-biased pn junction, including, but not limited to, thyristors, bipolar transistors, and insulated gate bipolar transistors..
Applied Physical Electronics, L.c.


07/23/15
20150207013 
new patent

Inverted metamorphic multijunction solar cells having a permanent supporting substrate


The present disclosure provides a method of manufacturing a solar cell that includes providing a semiconductor growth substrate; depositing on said growth substrate a sequence of layers of semiconductor material forming a solar cell; applying a metal contact layer over said sequence of layers; affixing the adhesive polyimide surface of a permanent supporting substrate directly over said metal contact layer and permanently bonding it thereto by a thermocompressive technique; and removing the semiconductor growth substrate.. .
Solaero Technologies Corp.


07/23/15
20150206998 
new patent

Passivated contacts for back contact back junction solar cells


Passivated contact structures and fabrication methods for back contact back junction solar cells are provided. According to one example embodiment, a back contact back junction photovoltaic solar cell is described that has a semiconductor light absorbing layer having a front side and a backside having base regions and emitter regions.
Solexel, Inc.


07/23/15
20150206990 
new patent

Solar cell production method, and solar cell produced by same production method


This solar cell production method involves productively forming an antireflection film comprising silicon nitride, said antireflection film having an excellent passivation effect. In an embodiment, a remote plasma cvd is used to form a first silicon nitride film on a semiconductor substrate (102) using the plasma flow from a first plasma chamber (111), then to form a second silicon nitride film, which has a different composition than the first silicon nitride film, using the plasma flow from a second plasma chamber (112), into which ammonia gas and silane gas have been introduced at a different flow ratio than that of the first plasma chamber (111).
Shin-etsu Chemical Co., Ltd.


07/23/15
20150206989 
new patent

Semiconductor component with a passivation layer made of hydrated aluminium nitride and also surface passivation of semiconductor components


The invention relates to a semiconductor component with base emitter and electrical contacts and also at least one passivation layer which consists of hydrated aluminium nitride or essentially comprises this. The invention relates likewise to a corresponding method for surface passivation of semiconductor components..
Fraunhofer-gesellschaft Zur Forderung Der Angewandten Forschung E.v.


07/23/15
20150206985 
new patent

Semiconductor diode assembly


Tsv devices with p-n junctions that are planar have superior performance in breakdown and current handling. Junction diode assembly formed in enclosed trenches occupies less chip area compared with junction-isolation diode assembly in the known art.
Diodes Incorporated


07/23/15
20150206983 
new patent

Semiconductor diode and manufacturing a semiconductor diode


A semiconductor diode includes a semiconductor body having opposite first and second sides. A first and a second semiconductor region are consecutively arranged along a lateral direction at the second side.
Infineon Technologies Ag


07/23/15
20150206982 
new patent

Thin film transistor for a display device, display device and manufacturing a display device


A thin film transistor for a display device is disclosed. In one aspect, the thin film transistor includes a gate electrode formed over a substrate and including a first conductive pattern and a plurality of second conductive patterns.
Samsung Display Co., Ltd.


07/23/15
20150206981 
new patent

Semiconductor device, display device, and manufacturing semiconductor device


There is provided a semiconductor device including a first region which, in an oxide semiconductor layer, has a higher carrier concentration than a channel region immediately below a gate electrode formed over the oxide semiconductor layer and is formed at least in a partial region other than the channel region, and a second region which, in the oxide semiconductor layer, has a higher carrier concentration than the first region and is formed farther from the channel region than the first region. The first region is formed through a first reduction reaction by stacking a first reduction reaction film over the oxide semiconductor layer and reducing the oxide semiconductor layer by the first reduction reaction film.
Sony Corporation


07/23/15
20150206979 
new patent

Semiconductor device and manufacturing same


This semiconductor device (101) includes: a substrate (1); a thin-film transistor (10) which includes an oxide semiconductor layer (6) as its active layer; a protective layer (11) covering the thin-film transistor; a metal layer (9d, 9t) interposed between the protective layer (11) and the substrate (1); a transparent conductive layer (13, 13t) formed on the protective layer (11); and a connecting portion (20, 30) to electrically connect the metal layer (9d, 9t) and the transparent conductive layer (13, 13t) together. The connecting portion (20, 30) includes an oxide connecting layer (6a, 6t) which is formed out of a same oxide film as a oxide semiconductor layer (6) and which has a lower electrical resistance than the oxide semiconductor layer (6).
Sharp Kabushiki Kaisha


07/23/15
20150206978 
new patent

Thin film transistor and display device


Provided is a thin film transistor comprising an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with: a gate electrode; two or more oxide semiconductor layers that are used as a channel layer; an etch stopper layer for protecting the surfaces of the oxide semiconductor layers; a source-drain electrode; and a gate insulator film interposed between the gate electrode and the channel layer.
Kabushiki Kaisha Kobe Seiko Sho (kobe Steel, Ltd.)


07/23/15
20150206977 
new patent

Metal oxide transistor


Provided is a transistor element in which the state thereof is changed into that of a resistor with a small power consumption without migration and melting of the resistor due to a large current, and physical changes, such as breakdown of an insulating film due to high electric field application, and the state change can be used as a memory element. This metal oxide transistor is provided with: a semiconductor thin film formed of a metal oxide semiconductor; a source electrode and a drain electrode, which are in contact with the semiconductor thin film; and a gate electrode, which faces the semiconductor thin film with a gate insulating film therebetween.
Sharp Kabushiki Kaisha


07/23/15
20150206976 
new patent

Thin film transistor and manufacturing the same


A thin film transistor includes a gate electrode disposed on a substrate, a gate insulating layer disposed on the gate electrode and the substrate, an oxide semiconductor pattern disposed on the gate insulating layer, wherein a part of the oxide semiconductor overlaps the gate electrode, a source electrode disposed on a part of the oxide semiconductor pattern, and a drain electrode disposed on a part of the oxide semiconductor pattern spaced apart from the source electrode, wherein a thickness of the gate insulating layer in a channel region, the channel region overlapping the gate electrode, is thinner than a thickness of the gate insulating layer in a remaining region, the remaining region other than the channel region.. .
Samsung Display Co., Ltd.


07/23/15
20150206975 
new patent

Fin-type semiconductor device and manufacturing method


One embodiment of a semiconductor device includes a fin at a first side of a semiconductor body, a body region of a second conductivity type in at least a part of the fin, a drain extension region of a first conductivity type, a source region and a drain region of the first conductivity type, a source contact in contact with the source region, the source contact extending along a vertical direction along the source region, and a gate structure adjoining opposing walls of the fin. The body region and the drain extension region are arranged one after another between the source region and the drain region.
Infineon Technologies Austria Ag


07/23/15
20150206974 
new patent

Semiconductor device and fabricating the same


A semiconductor device includes a semiconductor substrate comprising a group iii element and a group v element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region.

07/23/15
20150206973 
new patent

Semiconductor device and manufacturing same


[solution] a method according to the present invention comprises: a step of forming dopant-diffused layers 5a, 5b on the main surface of a semiconductor substrate 1; a step of forming a trench 11 on a bottom surface of which is erected at least one semiconductor beam 4, each connected at one end to the dopant-diffused layer 5a and connected at the other end to the dopant-diffused layer 5b; a step of forming a gate insulating film 6 on an inner surface of the trench 11, including the side surfaces of each at least one semiconductor beam 4, and on an upper surface of each at least one semiconductor beam 4; a step of depositing a gate electrode material having a film thickness that fills the trench 11, after the gate insulating film 6 has been formed; and a step of removing the gate electrode material that is located outside the trench 11 as seen in a plan view, while leaving the gate electrode material that is located inside the trench 11 as seen in a plan view.. .

07/23/15
20150206972 
new patent

Method of making a cmos semiconductor device using a stressed silicon-on-insulator (soi) wafer


A method for forming a complementary metal oxide semiconductor (cmos) semiconductor device includes providing a stressed silicon-on-insulator (ssoi) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region.
Stmicroelectronics, Inc.


07/23/15
20150206971 
new patent

Hybrid fin field-effect transistor structures and related methods


semiconductor-on-insulator structures facilitate the fabrication of devices, including mosfets that are at least partially depleted during operation and finfets including bilayer fins and/or crystalline oxide.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206970 
new patent

Body-tied, strained-channel multi-gate device and methods of manufacturing same


A fin-fet or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206969 
new patent

Semiconductor device, related manufacturing method, and related electronic device


A semiconductor device may include a semiconductor substrate. The semiconductor device may further include a gate electrode that overlaps the semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/23/15
20150206968 
new patent

Power ldmos semiconductor device with reduced on-resistance and manufacturing method thereof


An electronic semiconductor device including a semiconductor body having a first structural region and a second structural region, which extends on the first structural region and houses a drain region; a body region, which extends into the second structural region; a source region, which extends into the body region; and a gate electrode, which extends over the semiconductor body for generating a conductive channel between the source region and the drain region. The device includes a first conductive trench extending through, and electrically insulated from, the second structural region on one side of the gate electrode; and a second conductive trench extending through the source region, the body region, and right through the second structural region on an opposite side of the gate electrode, electrically insulated from the second structural region and electrically coupled to the body region and to the source region..
Stmicroelectronics S.r.l.


07/23/15
20150206967 
new patent

Semiconductor device


A semiconductor device includes a silicon carbide semiconductor substrate, a silicon carbide layer, a switching element section, and an overvoltage detection element section whose area is smaller than that of the switching element section. The switching element section includes a first electrode pad, a first terminal section surrounding the first electrode pad and provided in the silicon carbide layer, and a first insulating film covering the first terminal section.
Panasonic Intellectual Property Management Co., Ltd.


07/23/15
20150206966 
new patent

Semiconductor device and fabricating the same


The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region.. .
Vanguard International Semiconductor Corporation


07/23/15
20150206964 
new patent

Semiconductor device structure with metal ring on silicon-on-insulator (soi) substrate


In accordance with some embodiments, a semiconductor device is provided. The semiconductor device structure includes a substrate, and the substrate has a device region and an edge region.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/23/15
20150206963 
new patent

Metal gate structure and manufacturing method thereof


The present disclosure provides a semiconductor structure includes a semiconductor layer having a first surface, and an interlayer dielectric (ild) defining a metal gate over the first surface of the semiconductor layer. The metal gate includes a high-k dielectric layer, a barrier layer, and a work function metal layer.
Taiwan Semiconductor Manufacturing Company Ltd.


07/23/15
20150206962 
new patent

Semiconductor device, transistor having doped seed layer and manufacturing the same


A semiconductor device includes a substrate, and a seed layer over the substrate, wherein the seed layer comprises carbon dopants. The semiconductor device further includes a channel layer over the seed layer, and an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206960 
new patent

Semiconductor device


A semiconductor device 1 in which an igbt region 2 and a diode region 3 adjoining each other are formed on a same substrate 4 is presented. The semiconductor device 1 is provided with a plurality of first gate trenches 11 extending abreast in a first direction in the igbt region 2 and a plurality of second gate trenches 12 extending abreast in a second direction intersecting the first direction.
Toyota Jidosha Kabushiki Kaisha


07/23/15
20150206959 
new patent

Formation of a high aspect ratio trench in a semiconductor substrate and a bipolar semiconductor device having a high aspect ratio trench isolation region


Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening.
International Business Machines Corporation


07/23/15
20150206958 
new patent

Tunnel field-effect transistor


A tunnel field-effect transistor (tfet) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure comprises a channel region and a source region disposed on the channel region.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206957 
new patent

Low-temperature fabrication of nanomaterial-derived metal composite thin films


Disclosed are new methods of fabricating nanomaterial-derived metal composite thin films via solution processes at low temperatures (<400° c.). The present thin films are useful as thin film semiconductors, thin film dielectrics, or thin film conductors, and can be implemented into semiconductor devices such as thin film transistors and thin film photovoltaic devices..
Polyera Corporation


07/23/15
20150206956 
new patent

Semiconductor device and manufacturing the same


A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (seg) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate..
Samsung Electronics Co., Ltd.


07/23/15
20150206955 
new patent

Methods of selectively growing source/drain regions of fin field effect transistor and manufacturing semiconductor device including a fin field effect transistor


The inventive concepts provide methods of manufacturing a semiconductor device. The method includes patterning a substrate to form an active pattern, forming a gate pattern intersecting the active pattern, forming a gate spacer on a sidewall of the gate pattern, forming a growth-inhibiting layer covering an upper region of the gate pattern, and forming source/drain electrodes at opposite first and second sides of the gate pattern..
Samsung Electronics Co., Ltd.


07/23/15
20150206951 
new patent

Semiconductor structure and manufacuturing the same


Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a substrate, a high k dielectric layer disposed over the substrate, and a gate layer over the high k dielectric layer.
Taiwan Semiconductor Manufacturing Company Ltd.


07/23/15
20150206950 
new patent

Semiconductor structure


A semiconductor structure includes a top gate, an oxide semiconductor channel layer, a first dielectric layer, a second dielectric layer, a source and a drain. The oxide semiconductor channel layer is disposed between the top gate and a substrate.
E Ink Holdings Inc.


07/23/15
20150206946 
new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; and an interconnect plug on the doped region. The raised source/drain region includes a top surface being elevated from a surface of the substrate; and a doped region exposed on the top surface.
Taiwan Semiconductor Manufacturing Company Ltd.


07/23/15
20150206945 
new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a metal oxide semiconductor device disposed over a substrate and an interconnect plug. The metal oxide semiconductor device includes a gate structure located on the substrate and a raised source/drain region disposed adjacent to the gate structure.
Taiwan Semiconductor Manufacturing Company Ltd.


07/23/15
20150206943 
new patent

Edge termination configurations for high voltage semiconductor power devices


This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench..

07/23/15
20150206941 
new patent

Silicon carbide semiconductor device having junction barrier schottky diode


A silicon carbide semiconductor device includes a junction barrier schottky diode including a substrate, a drift layer, an insulating film, a schottky barrier diode, and a plurality of second conductivity type layers. The schottky barrier diode includes a schottky electrode and an ohmic electrode.
Denso Corporation


07/23/15
20150206940 
new patent

Semiconductor device and producing same


The aim of the present invention is to provide a semiconductor device containing a graphene p-n vertical tunneling-junction diode by assessing the optical and electrical characteristics of a graphene p-n junction produced by varying the doping concentration. The semiconductor device includes first graphene of a first doping type, and second graphene of a second doping type different from the first doping type, which is arranged on the first graphene and is in contact therewith..
University-industry Cooperation Group Of Kyung Hee University


07/23/15
20150206939 
new patent

Epitaxy in semiconductor structure and menufacuting the same


The present disclosure provides a semiconductor structure having an insulating layer positioning on a substrate; a semiconductor fin partially located in the insulating layer; and a metal gate over the semiconductor fin and the insulating layer. The semiconductor fin includes a first region including a first lattice constant and a second region in proximity to the metal gate, including a second lattice constant.
Taiwan Semiconductor Manufacturing Company Ltd.


07/23/15
20150206937 
new patent

Trench-based power semiconductor devices with increased breakdown voltage characteristics


Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.. .
Fairchild Semiconductor Corporation


07/23/15
20150206936 
new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a base dielectric layer, a semiconductor substrate layer disposed on the base dielectric layer, and a transistor disposed in the semiconductor substrate layer. The transistor includes a gate dielectric layer disposed on the semiconductor substrate layer, a gate electrode disposed on the gate dielectric layer, source and drain electrodes disposed within the semiconductor substrate layer on opposite sides of the gate electrode, an undoped channel region, a base dopant region, and a threshold voltage setting region.
Semiconductor Manufacturing International (shanghai) Corporation


07/23/15
20150206935 
new patent

Compound semiconductor device and manufacturing the same


An embodiment of a compound semiconductor device includes: a substrate; a compound semiconductor stacked structure formed over the substrate; and an amorphous insulating film formed between the substrate and the compound semiconductor stacked structure.. .
Fujitsu Limited


07/23/15
20150206934 
new patent

Method of manufacturing semiconductor device


Provided is a semiconductor device having improved reliability. Over a semiconductor substrate, a first coil is formed via a first insulating film.
Renesas Electronics Corporation


07/23/15
20150206932 
new patent

Thin film transistor, manufacturing thin film transistor and flat panel display having the thin film transistor


A thin film transistor (tft), method of manufacturing the tft and a flat panel display having the tft are disclosed. In one aspect, the tft comprises a substrate and an active layer formed over the substrate, wherein the active layer is formed of oxide semiconductor, and wherein the active layer includes two opposing sides.
Samsung Display Co., Ltd.


07/23/15
20150206930 
new patent

Light-emitting device wtih oxide thin film transistors and manufacturing method thereof


The present disclosure disclosed a light-emitting device with thin film transistors, comprising: a substrate and a substrate insulating layer formed thereon; a gate electrode, a source electrode, and a drain electrode. The gate electrode is arranged on the substrate insulating layer, and a gate insulating layer is formed between the gate electrode and the electrodes of the source and the drain.
Shenzhen China Star Optoelectronics Technology Co., Ltd.


07/23/15
20150206925 
new patent

Solid state imaging element, production method thereof and electronic device


There is provided a solid state imaging element including: an insulation film laminated on a semiconductor substrate; a lower transparent electrode film formed and separated by the insulation film per pixel; a hydrophobic treatment layer laminated on a flat surface of the insulation film and the lower transparent electrode film; an organic photoelectric conversion layer laminated on the hydrophobic treatment layer; and an upper transparent electrode film laminated on the organic photoelectric conversion layer. Also, there is provided a production method thereof and an electronic device..
Sony Corporation


07/23/15
20150206923 
new patent

Semiconductor device and manufacturing semiconductor device


A semiconductor device includes a first fin-shaped semiconductor layer on a semiconductor substrate, a first insulating film around the first fin-shaped semiconductor layer, a first pillar-shaped semiconductor layer on the first fin-shaped semiconductor layer, a first gate insulating film around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film and extending in a direction perpendicular to the first fin-shaped semiconductor layer, a second diffusion layer disposed in a lower portion of the first pillar-shaped semiconductor layer, a third gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer, a first contact electrode surrounding the third gate insulating film, a second contact electrode that connects an upper portion of the first contact electrode to an upper portion of the first pillar-shaped semiconductor layer, and a first magnetic tunnel junction memory element on the second contact electrode.. .
Unisantis Electronics Singapore Pte. Ltd.


07/23/15
20150206922 
new patent

Semiconductor light-emitting device


A semiconductor light-emitting device comprises: a mounting substrate; a plurality of semiconductor light-emitting elements that are arranged on the mounting substrate; a light absorber that is formed so as to cover an entire region between the plurality of semiconductor light-emitting elements adjacent to each other on the mounting substrate; and a wiring group including a plurality of wirings wired to each of the plurality of semiconductor light-emitting elements.. .
Stanley Electric Co., Ltd.


07/23/15
20150206920 
new patent

Semiconductor device


The performance of a semiconductor device is improved by preventing 1/f noise from being generated in a peripheral transistor, in the case where the occupation area of photodiodes, which are included in each of a plurality of pixels that form an image pickup device, is expanded. In the semiconductor device, the gate electrode of an amplification transistor is formed by both a gate electrode part over an active region and a large width part that covers the boundary between the active region and an element isolation region and the active region near the boundary and that.
Renesas Electronics Corporation


07/23/15
20150206919 
new patent

Cmos integrated fabrication of thermopile pixel on semiconductor substrate with buried insulation regions


A method for manufacturing an imaging device in a semiconductor substrate is disclosed. The substrate includes a first surface, a second surface substantially opposite the first surface, and a thickness defined by a distance between the first surface and the second surface.
Excelitas Technologies Singapore Pte. Ltd.


07/23/15
20150206918 
new patent

Image sensor with oblique pick up plug and semiconductor structure comprising the same


An image sensor includes a substrate, multiple pixel regions separately disposed in the substrate, and a pickup region including a doping region and a pick up plug obliquely disposed on the doping region and directly contacting the doping region.. .
Himax Imaging, Inc.


07/23/15
20150206917 
new patent

Image-sensor device structure and manufacturing


Embodiments of an image-sensor device structure and a method of manufacturing thereof are provided. The image-sensor device structure includes a semiconductor substrate and a light-sensing region in the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/23/15
20150206916 
new patent

Semiconductor device and manufacturing method thereof


A manufacturing method of a semiconductor device includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer.
Xintec Inc.


07/23/15
20150206915 
new patent

Image-sensor device and manufacturing the same


An image-sensor device includes a first semiconductor substrate. The image-sensor device further includes a second semiconductor substrate under the first semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


07/23/15
20150206911 
new patent

Solid-state imaging device and manufacturing the same


According to one embodiment, there is a solid-state imaging device including an imaging region. In the imaging region, a plurality of pixels are arranged two-dimensionally.
Kabushiki Kaisha Toshiba


07/23/15
20150206902 
new patent

Semiconductor device and forming the same


Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/23/15
20150206901 
new patent

Non-volatile memory device having a vertical structure and fabricating the same


A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.. .
Samsung Electronics Co., Ltd.


07/23/15
20150206897 
new patent

Semiconductor device and manufacturing method thereof


A semiconductor device according to the embodiment includes a first stack structure. The first stack structure includes at least one first insulating film and a plurality of first conducting films above a surface of a substrate.
Kabushiki Kaisha Toshiba


07/23/15
20150206896 
new patent

Three-dimensional semiconductor device


A 3d semiconductor device is provided, comprising plural memory layers vertically stacked on a substrate and parallel to each other; plural selection lines disposed on the memory layers and parallel to each other; plural bit lines disposed on the selection lines, and the bit lines arranged in parallel to each other and in perpendicular to the selection lines; plural strings formed vertically to the memory layers and the selection lines, and the strings electrically connected to the corresponding selection lines; a plurality of cells respectively defined by the strings, the selection lines and the bit lines correspondingly, and the cells arranged in a plurality of rows and columns, wherein a column direction is parallel to the bit lines while a row direction is parallel to the selection lines. The adjacent cells in the same column are electrically connected to the different bit lines..
Macronix International Co., Ltd.


07/23/15
20150206895 
new patent

Semiconductor device and manufacturing the same


A semiconductor device may include interlayer insulating patterns and local word lines which are alternately stacked to form a stepped structure, and a first insulating layer formed on a surface of the stepped structure. The semiconductor device may also include a word line selection gate formed along a surface of the first insulating layer, and active patterns passing through the word line selection gate and the first insulating layer, and connected to the local word lines, respectively..
Sk Hynix Inc.


07/23/15
20150206894 
new patent

Semiconductor structure and layout structure for memory devices


A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns.
United Microelectronics Corp.


07/23/15
20150206891 
new patent

Semiconductor device and manufacturing the same


The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/23/15
20150206889 
new patent

Semiconductor device


A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an sram memory cell. In the sram memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor.
Renesas Electronics Corporation


07/23/15
20150206888 
new patent

Static random access memory and fabrication methods thereof


A method for fabricating a static random access memory is provided. The method includes providing a semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/23/15
20150206887 
new patent

Semiconductor device structure and manufacturing the same


In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate, and the substrate has a cell region and a logic region.
Taiwan Semiconductor Manufacturing Co., Ltd


07/23/15
20150206886 
new patent

Methods of forming memory arrays and semiconductor constructions


Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material.
Micron Technology, Inc.


07/23/15
20150206885 
new patent

Dummy gate structure for electrical isolation of a fin dram


Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy.
International Business Machines Corporation


07/23/15
20150206884 
new patent

Dynamic random access memory cell with self-aligned strap


After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures.
International Business Machines Corporation


07/23/15
20150206883 
new patent

Manufacturing capacitor structure and semiconductor device using the same


The instant disclosure relates to a semiconductor device which includes a semiconductor substrate, at least one patterned reinforcing layer, a plurality of lower electrodes, and a supporting layer. The at least one patterned reinforcing layer is arranged above the semiconductor substrate, wherein the at least one patterned reinforcing layer has a plurality of reinforcing structures configured to define a plurality of alignment apertures.
Inotera Memories, Inc.


07/23/15
20150206881 
new patent

Formation of silicide contacts in semiconductor devices


Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nfet) region and a p-type field effect transistor (pfet) region; performing a pre-amorphized implantation (pai) process to an n-type doped silicon (si) feature in on the nfet region and a p-type doped silicon germanium (sige) feature in the pfet region, thereby forming an n-type amorphous silicon (a-si) feature and a p-type amorphous silicon germanium (a-sige) feature; depositing a metal layer over each of the a-si and a-sige features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-si and the p-type a-sige features.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206880 
new patent

High voltage lateral double-diffused metal oxide semiconductor field effect transistor (ldmosfet) having a deep fully depleted drain drift region


Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (ldmosfet) on the substrate.
International Business Machines Corporation


07/23/15
20150206878 
new patent

Implementing buried fet below and beside finfet on bulk substrate


A method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with added device drive strength with buried field effect transistors (fets) below and beside a traditional finfet on a bulk substrate, and a design structure on which the subject circuit resides are provided. Buried field effect transistors (fets) are formed on either side and under the traditional finfet.
International Business Machines Corporation


07/23/15
20150206877 
new patent

Non-merged epitaxially grown mosfet devices


semiconductor devices having non-merged fin extensions. A semiconductor device includes fins formed in trenches in an insulator layer, each of the fins having a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench.
Renesas Electronics Corporation


07/23/15
20150206876 
new patent

Fin field effect transistors having heteroepitaxial channels


Disposable gate structures are formed over semiconductor material portions, and source and drain regions can be formed in the semiconductor material portions. After formation of a planarization dielectric layer, one type of disposable gate structure can be removed selective to at least another type of disposable gate structure employing a patterned hard dielectric mask layer.
International Business Machines Corporation


07/23/15
20150206875 
new patent

Finfet semiconductor device with germanium diffusion over silicon fins


A method for manufacturing a semiconductor device is described that comprises providing a substrate, forming a plurality of fins having a first semiconductor material, replacing a first portion of at least one of the fins with a second semiconductor material, and distributing the second semiconductor material from the first portion to a second portion of the at least one of the fins.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206874 
new patent

Semiconductor device and fabricating the same


Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a gate structure formed on a substrate, a source/drain extension formed at one side of the gate structure while not being formed at the other side of the gate structure, and doped with a first type impurity, a halo region formed at one side of the gate structure while not being formed at the other side of the gate structure, and doped with a second type impurity different from the first type impurity, a first source/drain region formed at one side of the gate structure and doped with the first type impurity, and a second source/drain region formed at the other side of the gate structure and doped with the first type impurity..
Samsung Electronics Co., Ltd.


07/23/15
20150206873 
new patent

Alignment marks in non-sti isolation formation and methods of forming the same


A method includes forming a photo resist over a semiconductor substrate of a wafer, patterning the photo resist to form a first opening in the photo resist, and implanting the semiconductor substrate using the photo resist as an implantation mask. An implanted region is formed in the semiconductor substrate, wherein the implanted region is overlapped by the first opening.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206870 
new patent

Semiconductor integrated circuit


The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer.
Win Semiconductors Corp.


07/23/15
20150206869 
new patent

Package-on-package devices and methods of manufacturing the same


Package-on-package (pop) devices and methods of manufacturing the pop devices are provided. In the pop devices, a thermal interface material layer disposed between lower and upper semiconductor packages may contact about 70% or greater of an area of a top surface of a lower semiconductor chip.

07/23/15
20150206868 
new patent

Flip chip semiconductor device


A semiconductor device package comprises a lead frame having a die paddle comprising a first chip installation area and a second chip installation area, a recess area formed in the first chip installation area, and multiple metal pillars formed in the recess area, a notch divides the first chip installation area into a transverse base extending transversely and a longitudinal base extending longitudinally, and separates the recess area into a transverse recess part formed in the transverse base and a longitudinal recess part formed in longitudinal base; a portion of a transverse extending part connecting to an external pin extends into a portion inside of the notch.. .

07/23/15
20150206867 
new patent

Semiconductor apparatus having pad and bump


A semiconductor apparatus may include a semiconductor chip, and the semiconductor chip may include a first pad, a second pad, and a bump. The first pad may be configured to receive a signal from an external device, and the second pad may include first and second metal layers electrically isolated from each other.
Sk Hynix Inc.


07/23/15
20150206866 
new patent

Semiconductor package and methods of forming same


An embodiment package-on-package (pop) device includes a fan-out structure, one or more memory chips, and a plurality of connectors bonding the one or more memory chips to the fan-out structure. The fan-out structure includes a logic chip, a molding compound encircling the logic chip, and a plurality of conductive pillars extending through the molding compound..
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206864 
new patent

Semiconductor device


The semiconductor device 10 is provided with a switching element (fet 14) provided on a substrate 18, a first electrode (electrode 13) provided on an opposite side of the substrate 18 interposing the switching element, a diode 12 provided on an opposite side of the switching element interposing the first electrode, and a second electrode (electrode 11) provided on an opposite side of the first electrode interposing the diode 12.. .

07/23/15
20150206863 
new patent

Semiconductor tsv device package to which other semiconductor device package can be later attached


A first package includes a laminate layer, an overmold layer above and in direct contact with the laminate layer, and a logic circuit-through-silicon via (tsv) layer including a first logic die and tsvs. The logic circuit-tsv layer is within the overmold layer, and the tsvs are electrically exposed at a top surface of the overmold layer.
International Business Machines Corporation


07/23/15
20150206862 
new patent

Package on package arrangement and method


A method of forming a package on package, semiconductor package arrangement is described. In one aspect, solder bumps on a lower surface of a first grid array package substrate are fused to corresponding unencapsulated solder bumps on an upper surface of a second grid array package substrate.
Nvidia Corporartion


07/23/15
20150206860 
new patent

Semiconductor device


A plurality of arm elements is arrayed along a first direction of a substrate. Each arm element includes a plurality of semiconductor elements connected in parallel.
Kabushiki Kaishi Toyota Jidoshokki


07/23/15
20150206855 
new patent

Semiconductor package


The invention provides a semiconductor package. The semiconductor package includes a first semiconductor die having pads thereon.
Mediatek Inc.


07/23/15
20150206845 
new patent

Interconnect arrangement with stress-reducing structure and fabricating the same


Embodiments of a semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a substrate and a first layer formed over the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


07/23/15
20150206843 
new patent

Semiconductor device having a nanotube layer and forming


A method of forming a semiconductor device includes forming a first conductive layer over the substrate. A dielectric layer, having a first opening, is formed over the first conductive layer.
Freescale Semiconductor, Inc.


07/23/15
20150206842 
new patent

Semiconductor device and manufacturing the same


According to one embodiment, there is provided a semiconductor device using graphene, includes a catalyst layer formed on or in a substrate along with an interconnect pattern and a graphene layer formed on the catalyst layer. The graphene layer is arranged parallel to a narrower linewidth than the width of the interconnect pattern..
Kabushiki Kaisha Toshiba


07/23/15
20150206841 
new patent

Semiconductor device and manufacturing method thereof


A semiconductor device according to the present embodiment includes a first wiring made of copper. A metal film is provided on the first wiring and is made of cobalt, a cobalt alloy, nickel, or a nickel alloy.
Kabushiki Kaisha Toshiba


07/23/15
20150206840 
new patent

Semiconductor device structure and manufacturing the same


Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


07/23/15
20150206839 
new patent

Method to reduce metal fuse thickness without extra mask


Methods of fabricating a multi-layer semiconductor structure are provided. In one embodiment, a method includes depositing a first dielectric layer over a semiconductor structure, depositing a first metal layer over the first dielectric layer, patterning the first metal layer to form a plurality of first metal lines, and depositing a second dielectric layer over the first metal lines and the first dielectric layer.
Stmicroelectronics, Inc.


07/23/15
20150206835 
new patent

Method, structures and designing reduced delamination integrated circuits


An integrated circuit wire structure. The structure includes a set of interconnect levels over a semiconductor substrate, each interconnect level of the set of interconnect levels comprising operational wires embedded in an interlevel dielectric layer; a dielectric barrier layer on an uppermost interconnect level of the set of interconnect levels and a bonding pad on the passivation layer; a stress reduction zone surrounding a perimeter of the bonding pad and extending into the set of interconnect levels; elongated fill wires in each of the interconnect levels in the stress reduction zone, the elongated fill wires not connected to any of the non-ground operational wires; and the elongated fill wires of each interconnect level of each set of interconnect levels physically connected to elongated fill wires of immediately upper and lower interconnect levels of the set of fill levels..
International Business Machines Corporation


07/23/15
20150206834 
new patent

Semiconductor device with combined power and ground ring structure


A semiconductor device includes a lead frame, and an integrated circuit die. The lead frame has a flag for supporting the die and leads that surround that flag and die.

07/23/15
20150206832 
new patent

Printed circuit board and stacked semiconductor device


A semiconductor package includes an interposer and a semiconductor element mounted on one surface of the interposer. A plurality of lands are formed on another surface of the interposer.
Canon Kabushiki Kaisha


07/23/15
20150206831 
new patent

Semiconductor device with webbing between leads


A quad flat package integrated circuit (ic) device has alternating inner and outer leads that protrude from a package body. The inner leads are j-shaped leads and the outer leads are gull-wing shaped leads.
Freescale Seminconductor, Inc.


07/23/15
20150206830 
new patent

Method of manufacturing semiconductor device and the semiconductor device


A lead frame having a first chip-mounting part on which a first semiconductor chip is mounted and having a second chip-mounting part on which a second semiconductor chip is mounted is prepared. Moreover, a process is provided, the process connecting a first electrode pad, which is formed on a top surface of the first semiconductor chip, with a first end of a first metal ribbon and connecting a ribbon-connecting surface on the second chip-mounting part with a second end of the first metal ribbon on the opposite side of the first end.
Renesas Electronics Corporation


07/23/15
20150206829 
new patent

Semiconductor package with interior leads


A packaged semiconductor device has a lead frame, a semiconductor die, and bond wires. The lead frame has a two-dimensional array of leads with a subset of interior leads located in the interior of the array that do not extend to the perimeter of the array.

07/23/15
20150206828 
new patent

Semiconductor device having barrier metal layer


According to one embodiment, a semiconductor device having an interlayer insulating film, a molybdenum containing layer, a barrier metal layer and a plug material layer is provided. The interlayer insulating film is formed on a substrate or on a conductive layer formed on a substrate.
Kabushiki Kaisha Toshiba


07/23/15
20150206827 
new patent

Semiconductor device with through silicon via and alignment mark


A semiconductor device with a semiconductor substrate having a first surface and an opposite-facing second surface, a through electrode electrically connected to the semiconductor element and penetrating the semiconductor substrate from the first surface to the second surface, and a conductor, not electrically connected to the semiconductor element, penetrating the semiconductor substrate from the first surface to the second surface, where the through electrode and the conductor have different shapes in plan view.. .
Ps4 Luxco S.a.r.l.


07/23/15
20150206826 
new patent

Semiconductor device and manufacturing semiconductor device


A semiconductor device including: a base material portion that includes a semiconductor substrate and an insulating film that is formed on one face of the semiconductor substrate and on which a vertical hole is formed along the thickness direction of the semiconductor substrate; a vertical hole wiring portion that includes a vertical hole electrode formed on a side wall of the base material portion that forms the vertical hole; a metallic film that is formed within the insulating film and that is electrically connected to the vertical hole wiring portion; and a conductive protective film that is formed to be in contact with the metallic film within the insulating film and that is formed in a region that includes a contact region of a probe during a probe test that is performed in the middle of manufacture on a film face of the metallic film.. .
Sony Corporation


07/23/15
20150206825 
new patent

Semiconductor device having through-silicon via


A semiconductor device includes a through electrode vertically passing through the semiconductor device; a metal pad electrically coupling the through electrode and an exterior; a data input block suitable for transferring a data signal to the metal pad in response to a write command; a through electrode storage block suitable for storing the data signal transferred through the metal pad; and a data output block suitable for outputting the data signal, which is stored in the through electrode storage block, to the exterior in response to a read command.. .
Sk Hynix Inc.


07/23/15
20150206822 
new patent

Carbon nanotube sheet, semiconductor device, manufacturing carbon nanotube sheet, and manufacturing semiconductor device


A carbon nanotube sheet includes a carbon nanotube aggregate in which a plurality of carbon nanotubes are arrayed, a thermoplastic resin portion formed in a center area of the carbon nanotube aggregate, and an uncured thermosetting resin portion formed in an outer periphery area of the carbon nanotube aggregate so as to surround the thermoplastic resin portion.. .
Shinko Electric Industries Co., Ltd.


07/23/15
20150206820 
new patent

Electronic component


An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, means for a spreading heat in directions substantially parallel to a major surface of the one or more semiconductor dice embedded in a second dielectric layer and means for dissipating heat in directions substantially perpendicular to the major surface of the one or more semiconductor dice.. .
Infineon Technologies Austria Ag


07/23/15
20150206818 
new patent

Liquid crystal display and fabricating the same


A liquid crystal display and a method of fabricating a liquid crystal display (lcd), the lcd including a substrate; gate wiring including a gate pad, a gate electrode, and a gate line, which are formed on the substrate; a gate insulating layer disposed on the gate wiring; an electrode pattern including a connecting electrode, which is disposed on the gate insulating layer and is electrically connected to the gate pad, a source electrode and a drain electrode, which partially overlap the gate electrode; a pixel electrode, which is electrically connected to the drain electrode; a data line, which intersects the gate line; a semiconductor layer disposed on the gate electrode; first auxiliary wiring overlapping the data line and spaced from the semiconductor layer; and second auxiliary wiring overlapping the gate line.. .
Samsung Display Co., Ltd.


07/23/15
20150206817 
new patent

Chip package and manufacturing the same


A package comprises a semiconductor device. The semiconductor device comprises an active surface and side surfaces.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206814 
new patent

Layer structure for mounting semiconductor device and fabrication method thereof


A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.. .
Siliconware Precision Industries Co., Ltd.


07/23/15
20150206813 
new patent

Methods and structures for processing semiconductor devices


Methods of processing a semiconductor device include attaching a semiconductor substrate to a carrier substrate, forming a silane material over an exposed portion of the carrier substrate, and curing the silane material to form a hydrophobic coating over the carrier substrate. The hydrophobic coating may reduce or prevent undercut of the semiconductor substrate due to wicking of adhesive from between the semiconductor substrate and the carrier substrate during processing.
Micron Technology, Inc.


07/23/15
20150206812 
new patent

Substrate and forming the same


Methods and apparatus for cavity formation in a semiconductor package substrate are provided. In one embodiment, a method for producing at least one cavity within a semiconductor package substrate includes etching the semiconductor package substrate from a surface of the semiconductor package substrate at least one intended cavity location in order to obtain at least one cavity.
Qualcomm Incorporated


07/23/15
20150206811 
new patent

Semiconductor device


According to one embodiment, a semiconductor device includes a semiconductor chip including a first terminal surface and a second terminal surface located on a side opposite to the first terminal surface. An insulation unit surrounds an outer circumference of a side surface of the semiconductor chip.
Kabushiki Kaisha Toshiba


07/23/15
20150206810 
new patent

Stacked semiconductor structure and manufacturing the same


A stacked semiconductor structure and a manufacturing method for the same are provided. The stacked semiconductor structure is provided, which comprises a first semiconductor substrate, a second semiconductor substrate, a dielectric layer, a trench, a via, and a conductive structure.
United Microelectronics Corp.


07/23/15
20150206808 
new patent

Systems and methods for microwave-radiation annealing


Systems and methods are provided for annealing a semiconductor structure using microwave radiation. A semiconductor structure is provided.
Taiwan Semiconductor Manufacturing Company Limited


07/23/15
20150206807 
new patent

Semiconductor device and manufacturing method thereof


A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise connection verification for a first one or more mounted components prior to additional assembly..
Amkor Technology, Inc.


07/23/15
20150206806 
new patent

Method and system of measuring semiconductor device and fabricating semiconductor device using the same


The measurement method may include obtaining first measurement data from a recess region formed in a semiconductor substrate, obtaining second measurement data from a conductive pattern filling a portion of the recess region, calculating a first volume of the recess region from the first measurement data, calculating a second volume of the conductive pattern from the second measurement data, and calculating a measurement target parameter using a difference between the first and second volumes.. .

07/23/15
20150206805 
new patent

Semiconductor device with metal gate and high-k materials and fabricating the same


A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust species is formed over the first region and a second gate stack structure containing a second effective work function adjust species is formed over the second region.
Sk Hynix Inc.


07/23/15
20150206804 
new patent

Method of semiconductor integrated circuit fabrication


A method of fabricating a semiconductor integrated circuit (ic) is disclosed. A high-k/metal gate (hk/mg) and a conductive feature are disposed over a substrate, separated by a first dielectric layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206802 
new patent

Singulation of semiconductor dies with contact metallization by electrical discharge machining


A method of separating individual dies of a semiconductor wafer includes forming a metal layer on a first surface of a semiconductor wafer, the semiconductor wafer including a plurality of dies, separating the plurality of dies from one another, and electrical discharge machining the metal layer into individual segments each of which remains attached to one of the dies. A corresponding semiconductor die produced by such a method is also provided..
Infineon Technologies Ag


07/23/15
20150206801 
new patent

Devices, systems, and methods related to planarizing semiconductor devices after forming openings


Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stop layer and a dielectric liner including dielectric material along sidewalls of openings, e.g., through-substrate openings, of the semiconductor device and excess dielectric material outside the openings.
Micron Technology, Inc.


07/23/15
20150206800 
new patent

Semiconductor device with air gap and fabricating the same


A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening; a second conductive pattern covering a top surface and sidewalls of the first conductive pattern; an air gap defined between sidewalls of the opening and the second conductive pattern; and a third conductive pattern capping the second conductive pattern and the air gap.. .
Sk Hynix Inc.


07/23/15
20150206797 
new patent

Semiconductor device and making same


One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.. .
Infineon Technologies Ag


07/23/15
20150206794 
new patent

Method for removing micro scratches in chemical mechanical polishing processes


A chemical mechanical polishing process for manufacturing a semiconductor device includes forming a conductive layer over a first dielectric layer formed over a semiconductor substrate. The conductive layer is patterned to form a patterned conductive layer with a plurality of openings.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206791 
new patent

Method for forming semiconductor device structure


In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer on a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/23/15
20150206788 
new patent

Double patterning forming semiconductor active areas and isolation regions


A method of forming active areas and isolation regions in a semiconductor substrate using a double patterning process. The method include forming a first material on the substrate surface, forming a second material on the first material, forming a plurality of first trenches into the second material wherein the plurality of first trenches are parallel to each other, forming a second trench into the second material wherein the second trench is perpendicular to and crosses the plurality of first trenches in a central region of the substrate, filling the first and second trenches with a third material, removing the second material to form third trenches in the third material that are parallel to each other and do not extend through the central region of the substrate, and extending the third trenches through the first material and into the substrate..
Silicon Storage Technology, Inc.


07/23/15
20150206787 
new patent

Method of manufacturing semiconductor device


An object of the invention is to provide a semiconductor device having improved performance. A method of manufacturing a semiconductor device includes: forming a trench and then forming a first insulating film made of a silicon oxide film through cvd using a gas containing an o3 gas and a teos gas to cover the side surface of the trench with the insulating film; forming a second insulating film made of a silicon oxide film through pecvd to cover the side surface of the trench with the second insulating film via the first insulating film; and forming a third insulating film made of a silicon oxide film through cvd using a gas containing an o3 gas and a teos gas to close the trench with the third insulating film while leaving a space in the trench..
Renesas Electronics Corporation


07/23/15
20150206780 
new patent

Wafer storage apparatus having gas charging portions and semiconductor manufacturing apparatus using the same


A wafer storage apparatus includes a wafer stacking portion that encloses an internal space with an open front side for receiving a plurality of wafers; a rear cover portion disposed on the back side of the wafer stacking portion; and a gas charging portion that includes a plurality of gas supply blocks disposed on the inner side of the rear cover portion, a plurality of gas supply pipes connected to the gas supply blocks via through holes in the rear cover portion, and a gas supply unit connected to the gas supply pipes.. .
Samsung Electronics Co., Ltd.


07/23/15
20150206779 
new patent

Semiconductor processing boat design with pressure sensor


Presented herein is a device comprising a device processing boat comprising a base at least one unit retainer disposed in the base. The device further comprises a cover having at least one recess configured to accept and retain at least one unit, the at least one recess aligned over, and configured to hold the at least one unit over, at least a portion of the at least one unit retainer.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206776 
new patent

Temperature controller for semiconductor manufacturing equipment, calculating pid constants in semiconductor manfacturing, and operating temperature controller for semiconductor manufacturing equipment


A temperature adjustment system configured to adjust the temperature of a fluid used in a semiconductor manufacturing apparatus includes: a heat exchanger including therein a temperature adjuster for heating and cooling the fluid, the heat exchanger being configured to perform heat exchange between the fluid therein and the temperature adjuster; a temperature sensor configured to measure the temperature of the fluid; a pid-constant calculator configured to calculate pid constants for pid control based on the physical properties of the fluid and a time constant of the temperature sensor; and a pid-control calculator configured to perform the pid control on the temperature adjuster with the pid constants calculated by the pid-constant calculator.. .
Kelk Ltd.


07/23/15
20150206769 
new patent

Lead frame based semiconductor device with power bars


A semiconductor device includes a semiconductor die having first and second opposing main surfaces and a die bonding pads on the first main surface, and a conductive member having first and second opposing main surfaces that surrounds the die. The die and the conductive member are encapsulated with a first encapsulant and form an expanded die.

07/23/15
20150206767 
new patent

Method of manufacturing semiconductor device


A false report on appearance inspection of a semiconductor device is prevented by suppressing variation in surface state of an electrodeposited gold electrode. In formation of an electrodeposited gold electrode, an electrodeposited gold electrode comprised of a plurality of electrodeposited gold layers in the stack is formed by alternately repeating a step of performing energization between an anode electrode and a cathode electrode provided in a treatment cup of a plating apparatus to cause crystal growth of an electrodeposited gold layer (energization on), and a step of performing no energization between the anode electrode and the cathode electrode (energization off).
Renesas Electronics Corporation


07/23/15
20150206765 
new patent

Mechanical compression-based the reduction of defects in semiconductors


A high pressure-directed engineering method enables reduced defect semiconductor materials that are unattainable by other chemical and physical methods. Experimental results show that hydraulic pressures as low as 0.5 gpa can eliminate stacking faults and significantly reduce point defects, leading to improved materials quality in semiconductors, such as gan..
Sandia Corporation


07/23/15
20150206759 
new patent

Semiconductor structure and manufacturing method thereof


The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (sti) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.. .
United Microelectronics Corp.


07/23/15
20150206758 
new patent

Method for manufacturing semiconductor device


A method includes: forming a front surface structure of a semiconductor element on a front surface side of a semiconductor substrate; forming crystal defects in the semiconductor substrate by implanting charged particles into the semiconductor substrate; subjecting the semiconductor substrate to a heat treatment after having formed the crystal defects; attaching a supporting plate on the front surface side of the semiconductor substrate after the heat treatment; thinning the semiconductor substrate by grinding a back surface side of the semiconductor substrate to which the supporting plate has been attached; and forming a back surface structure of the semiconductor element on a back surface of the thinned semiconductor substrate.. .
Toyota Jidosha Kabushiki Kaisha


07/23/15
20150206756 
new patent

Lowering tungsten resistivity by replacing titanium nitride with titanium silicon nitride


semiconductor devices, methods and apparatus for forming the same are provided. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions.
Applied Materials, Inc.


07/23/15
20150206755 
new patent

Method of patterning a metal gate of semiconductor device


Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206754 
new patent

Gate contact with vertical isolation from source-drain


A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ild) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed.
International Business Machines Corporation


07/23/15
20150206750 
new patent

Method for making contact between a semiconductor material and a contact layer


A method for making contact between (i) a semiconductor material having silicon carbide and (ii) a contact layer having nickel oxide includes applying the contact layer to the semiconductor material, and treating at least an interface between the contact layer and the semiconductor material at an elevated temperature. An ohmic contact between the contact layer and the semiconductor material has an improved long-term stability due to an improved adhesion of the nickel to the silicon carbide.
Robert Bosch Gmbh


07/23/15
20150206749 
new patent

Diamond semiconductor system and method


Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer..

07/23/15
20150206746 
new patent

Semiconductor fins on a trench isolation region in a bulk semiconductor substrate and a forming the semiconductor fins


Disclosed are semiconductor structures with monocrystalline semiconductor fins, which are above a trench isolation region in a semiconductor substrate and which can be incorporated into semiconductor device(s). Also disclosed are methods of forming such structures by forming sidewall spacers on opposing sides of mandrels on a dielectric cap layer.
International Business Machines Corporation


07/23/15
20150206742 
new patent

Method of manufacturing semiconductor device and substrate processing apparatus


Provided is a technique of forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes: forming a first layer including a first element, wherein the first layer is a discontinuous layer, a continuous layer, or a layer in which at least one of the discontinuous layer or the continuous layer is overlapped; forming a second layer including the first layer and a discontinuous layer including a second element stacked on the first layer; forming a third layer by supplying a gas containing a third element to the substrate to modify the second layer; and forming a fourth layer including the first element, the second element, the third element and a fourth element by supplying a gas containing the fourth element to the substrate to modify the third layer..
Hitachi-kokusai Electric Inc.


07/23/15
20150206740 
new patent

Electrical charge regulation for a semiconductor substrate during charged particle beam processing


A method for preparing a semiconductor target (10), the method comprising providing a semiconductor substrate (12) including a main substrate surface (14) which defines a substrate periphery (20) along an outer edge. The semiconductor substrate (12) further has an structure layer (30) arranged on the main substrate surface, and comprising a structure layer periphery (32) that is located inwards with respect to the substrate periphery, so as to leave exposed a peripheral substrate region (22) along the substrate periphery.
Mapper Lithography Ip B.v


07/23/15
20150206737 
new patent

Method of manufacturing semiconductor device and substrate processing apparatus


Provided is a technique of forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes: forming a first layer by supplying a gas containing a first element to the substrate, wherein the first layer is a discontinuous layer, a continuous layer, or a layer in which at least one of the discontinuous layer or the continuous layer is overlapped; forming a second layer including the first layer and a discontinuous layer including a second element stacked on the first layer; and forming a third layer by supplying a gas containing a third element to the substrate to modify the second layer under a condition where a modifying reaction of the second layer by the gas containing the third element is not saturated..
Hitachi-kokusai Electric Inc.


07/23/15
20150206736 
new patent

Method of manufacturing semiconductor device, substrate processing apparatus and non-transitory computer-readable recording medium


The uniformity of the thickness of the film of a film to be formed on a substrate within a plane of the substrate can be improved. A method of manufacturing a semiconductor includes performing a cycle, a predetermined number of times, to form a film on a substrate, the cycle including non-simultaneously performing: (a) supplying a source gas to the substrate in a process chamber; (b) removing the source gas from the process chamber; (c) supplying a reactive gas having a chemical structure different from that of the source gas to the substrate in the process chamber; and (d) removing the reactive gas from the process chamber, wherein the (d) includes alternately repeating: (d-1) exhausting an inside of the process chamber to depressurize the inside of the process chamber; and (d-2) purging the inside of the process chamber using an inert gas..
Hitachi Kokusai Electric Inc.


07/23/15
20150206722 
new patent

Lower electrode and plasma processing apparatus


A lower electrode 2 includes a conductive base member 2a to which a high frequency power is applied; an electrostatic chuck 6, having an insulating layer 6b formed on a top surface of the base member 2a to cover an electrode 6a, configured to electrostatically attract a semiconductor wafer w as a target of a plasma process onto the insulating layer 6b; a focus ring 5 provided on a top surface of the insulating layer 6b of the electrostatic chuck 6 to surround the semiconductor wafer w; and a thermally sprayed film 100, which is conductive and formed on a portion of the insulating layer 6b of the electrostatic chuck 6 positioned between the focus ring 5 and the base member 2a by using a composite material in which titania is added to an insulating material for the insulating layer at a preset weight ratio.. .
Tokyo Electron Limited


07/23/15
20150206707 
new patent

Method for s/tem sample analysis


An improved method and apparatus for s/tem sample preparation and analysis. Preferred embodiments of the present invention provide improved methods for tem sample creation, especially for small geometry (<100 nm thick) tem lamellae.
Fei Company


07/23/15
20150206701 
new patent

Two-dimensional mass resolving slit mechanism for semiconductor processing systems


An adjustable mass-resolving slit assembly includes an aperture portion and an actuation portion. The aperture portion includes first and second shield members that define an aperture therebetween for receiving an ion beam during semiconductor processing operations.
Varian Semiconductor Equipment Associates, Inc.


07/23/15
20150206699 
new patent

Electron emission device and electron emission display


An electron emission device includes a number of electron emission units spaced from each other, wherein each of the number of electron emission units includes a first electrode, a semiconductor layer, an insulating layer, and a second electrode stacked with each other, the first electrode includes a carbon nanotube layer, a number of holes defines in the semiconductor layer, and a portion of the carbon nanotube layer suspended on the number of holes.. .
Hon Hai Precision Industry Co., Ltd.


07/23/15
20150206697 
new patent

Electron emission device and electron emission display


An electron emission device includes a number of electron emission units spaced from each other, wherein each of the number of electron emission units includes a first electrode, a semiconductor layer, an electron collection layer, an insulating layer, and a second electrode stacked with each other, the electron collection layer is in contact with the semiconductor layer and the insulating layer, and the electron collection layer is a conductive layer.. .
Hon Hai Precision Industry Co., Ltd.


07/23/15
20150206696 
new patent

Electron emission device and electron emission display


An electron emission device includes a number of second electrodes intersected with a number of first electrodes to define a number of intersections. An electron emission unit is sandwiched between the first electrode and the second electrode at each of the number of intersections, wherein the electron emission unit includes a semiconductor layer, an electron collection layer, and an insulating layer stacked together, and the electron collection layer is a conductive layer..
Hon Hai Precision Industry Co., Ltd.


07/23/15
20150206695 
new patent

Electron emission source and making the same


An electron emission source includes a first electrode, an insulating layer, and a second electrode stacked in that sequence, wherein the first electrode is a carbon nanotube composite structure comprising a carbon nanotube layer and a semiconductor layer stacked together, and the semiconductor layer is sandwiched between the carbon nanotube layer and the insulating layer. A method for making the electron emission source is also related..
Hon Hai Precision Industry Co., Ltd.


07/23/15
20150206694 
new patent

Electron emission device and electron emission display


An electron emission device includes a number of electron emission units, wherein each of the number of electron emission units includes a first electrode, an insulating layer, and a second electrode stacked in that sequence, wherein the first electrode is a carbon nanotube composite structure having a carbon nanotube layer and a semiconductor layer stacked together, and the semiconductor layer is sandwiched between the carbon nanotube layer and the insulating layer, the first electrodes in the number of electron emission units are spaced apart from each other, and the second electrodes in the number of electron emission units are spaced apart from each other.. .
Hon Hai Precision Industry Co., Ltd.


07/23/15
20150206693 
new patent

Electron emission source


An electron emission source includes a first electrode, a semiconductor layer, an insulating layer, and a second electrode stacked in that sequence, wherein the semiconductor layer defines a number of holes, the first electrode comprises a carbon nanotube layer, and a portion of the carbon nanotube layer corresponding to the number of holes is suspended on the number of holes.. .
Hon Hai Precision Industry Co., Ltd.


07/23/15
20150206692 
new patent

Electron emission device and electron emission display


An electron emission device includes a number of first electrodes and a number of second electrodes intersected with each other to define a number of intersections. An electron emission unit is sandwiched between the first electrode and the second electrode at each of the number of intersections, wherein the electron emission unit includes a semiconductor layer and an insulating layer stacked together, the semiconductor layer defines a number of holes, the carbon nanotube layer covers the number of holes, and a portion of the carbon nanotube layer is suspended on the number of holes..
Hon Hai Precision Industry Co., Ltd.


07/23/15
20150206691 
new patent

Electron emission device and electron emission display


An electron emission device includes a number of second electrodes intersected with a number of first electrodes to define a number of intersections. The first electrode includes a carbon nanotube layer and a semiconductor layer coated on the carbon nanotube layer.
Hon Hai Precision Industry Co., Ltd.


07/23/15
20150206689 
new patent

Electron emission source


An electron emission source includes a first electrode, a semiconductor layer, an insulating layer, and a second electrode stacked in that sequence, wherein an electron collection layer is sandwiched between the semiconductor layer and the insulating layer, the electron collection layer is in contact with the semiconductor layer and the insulating layer, and the electron collection layer is a conductive layer to collect electrons.. .
Hon Hai Precision Industry Co., Ltd.


07/23/15
20150206619 
new patent

Conductive fiber-coated particle, curable composition and cured article derived from curable composition


The conductive fiber-coated particle includes a particulate substance and a fibrous conductive substance. The particulate substance is coated with the fibrous conductive substance.

07/23/15
20150206603 
new patent

E-fuse structure of semiconductor device


Provided is an e-fuse structure of a semiconductor device having improved fusing performance so as to enable a program operation at a low voltage. The e-fuse structure includes a first metal pattern formed at a first vertical level, the first metal pattern including a first part extending in a first direction and a second part extending in the first direction and positioned to be adjacent to the first part, and a third part adjacent to the second part, the second part being positioned between the first part and the third part, the first part and the second part being electrically connected to each other, and the third part being electrically disconnected from the second part; and a second metal pattern electrically connected to the first metal pattern and formed at a second vertical level different from the first vertical level..

07/23/15
20150206601 
new patent

Semiconductor memory device, test control system, and operating test control system


A semiconductor memory device includes a plurality of memory cells electrically coupled to a plurality of word lines and a word line failure detection unit suitable for supplying a test voltage to a test target word line selected from among the plurality of word lines, and for detecting the test voltage transferred from at least one of the plurality of word lines, wherein the at least one of the plurality of word lines does not include the test target word line.. .
Sk Hynix Inc.


07/23/15
20150206595 
new patent

Antifuse array architecture


An anti-fuse including a program transistor which can be short-circuited depending on whether the program transistor is programmed, and also including a read transistor which is coupled with the program transistor and a bit line, and outputs information to the bit line based on whether the program transistor is short-circuited, comprising: an active region formed in a first direction in a semiconductor substrate; a bit line contact formed over the active region and coupled with the bit line; a program gate electrode the entire or part of which is buried in the active region over the program transistor; and a read gate electrode disposed over the read transistor and formed between the program gate electrode and the bit line contact.. .
Sk Hynix Inc.


07/23/15
20150206592 
new patent

Methods of operating a memory device having a buried boosting plate


Memory devices are disclosed, such as those that include a semiconductor-on-insulator (soi) nand memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the soi substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array.
Micron Technology, Inc.


07/23/15
20150206591 
new patent

Nonvolatile memory device and operating method thereof


A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with p-type impurities.. .
Sk Hynix Inc.


07/23/15
20150206590 
new patent

Memory system


According to one embodiment, a memory system includes a nonvolatile semiconductor memory device and a controller. The system includes the nonvolatile semiconductor memory device including a plurality of memory cells; and the controller configured to control one of read operation, write operation, and a use frequency of the read operation or the write operation on the nonvolatile semiconductor memory device, and configured to change controlling for a memory cell belonging to a first group of the memory cells and to change controlling for a memory cell belonging to a second group located on an upper side or a lower side of the memory cell belonging to the first group..
Kabushiki Kaisha Toshiba


07/23/15
20150206588 
new patent

Semiconductor device


A semiconductor device has a smaller area. That is, in a row selection decoder including mos transistors, which selectively connect a plurality of selection signal lines to row selection lines of nand flash memories having an sgt structure, the mos transistors are formed on a planar silicon layer that is formed on a substrate, and each have a structure such that a drain, a gate, and a source are disposed in the vertical direction and the gate surrounds a silicon pillar.
Unisantis Electronics Singapore Pte. Ltd.


07/23/15
20150206585 
new patent

Electronic device and fabricating the same


An electronic device including a semiconductor memory is provided. The semiconductor memory includes a first electrode, a second electrode crossing the first electrode, and a variable resistance pattern positioned in an intersection region of the first electrode and the second electrode and buried in the first electrode..
Sk Hynix Inc.


07/23/15
20150206580 
new patent

Semiconductor memory device


A semiconductor memory device according to an embodiment comprises: a plurality of first lines extending in a first direction perpendicular to a substrate surface and arranged with a certain pitch in a second direction parallel to the substrate surface; a plurality of second lines extending in the second direction and arranged with a certain pitch in the first direction; a memory cell provided at an intersection of the first line and the second line and including a variable resistance element; a third line provided extending in the second direction between the plurality of second lines; and a control circuit capable of executing a first operation that changes a resistance value of the variable resistance element by applying a voltage to the memory cell via the first line and the second line, and a second operation that supplies heat to the memory cell using the third line.. .
Kabushiki Kaisha Toshiba


07/23/15
20150206571 
new patent

Semiconductor device


A semiconductor device including an operation initiation block suitable for sequentially generating a plurality of operation initiation signals at a predetermined time interval in response to an operation initiation source signal, a clock-based signal generation block suitable for generating an operation termination source signal in response to one of the multiple operation initiation signals and a clock, an operation termination block suitable for sequentially generating a plurality of operation termination signals at the predetermined time interval in response to the operation termination source signal, and an operation control block suitable for sequentially generating a plurality of first operation control signals in response to the multiple operation initiation signals and the multiple operation termination signals.. .
Sk Hynix Inc.


07/23/15
20150206565 
new patent

Semiconductor memory device and controlling semiconductor memory device


A semiconductor memory device includes a memory cell, a reference cell, a first current source configured to cause a first current to flow through the memory cell, a second current source configured to cause a second current having an amount thereof being variable to flow through the reference cell, a sense amplifier configured to compare a voltage responsive to a voltage drop across the memory cell with a voltage responsive to a voltage drop across the reference cell, and a current-amount setting circuit configured to determine the amount of the second current, wherein the current-amount setting circuit determines the amount of the second current such that the voltage drop across the reference cell is equal to a midpoint between the voltage drop across the memory cell having a data value of “0” stored therein and the voltage drop across the memory cell having a data value of “1” stored therein.. .
Fujitsu Limited


07/23/15
20150206563 
new patent

Semiconductor system


A semiconductor system includes a first clock channel and a second clock channel. The first clock channel transmits a first clock signal from a controller to a memory.
Sk Hynix Inc.




Popular terms: [SEARCH]

Semiconductor topics: Semiconductor, Semiconductor Substrate, Semiconductor Device, Semiconductor Material, Electric Conversion, Conductive Layer, Molybdenum, Camera Module, Semiconductor Devices, Semiconductors, Integrated Circuit, Surfactant, Photoelectric Conversion, Electronic Device, Transparent Conductive Oxide

Follow us on Twitter
twitter icon@FreshPatents

###

This listing is a sample listing of patent applications related to Semiconductor for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Semiconductor with additional patents listed. Browse our RSS directory or Search for other possible listings.


0.9867

21669

1 - 1 - 406