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This page is updated frequently with new Semiconductor-related patent applications. Subscribe to the Semiconductor RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor RSS RSS


Electronic device

Method for bonding semiconductor devices

Polishing pad and method for producing same

Date/App# patent app List of recent Semiconductor-related patents
08/28/14
20140245248
 Cell and macro placement on fin grid patent thumbnailnew patent Cell and macro placement on fin grid
A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction.
08/28/14
20140245239
 Detection and removal of self-aligned double patterning artifacts patent thumbnailnew patent Detection and removal of self-aligned double patterning artifacts
Mask design techniques for detection and removal of undesirable artifacts in sadp processes using multiple patterns are disclosed. Artifacts or spurs result from lithographic and chemical processing of semiconducting wafers.
08/28/14
20140245105
 Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices patent thumbnailnew patent Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices
A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit.
08/28/14
20140245101
 Semiconductor memory patent thumbnailnew patent Semiconductor memory
According to one embodiment, a semiconductor memory includes a memory cell unit, an encoding circuit that generates a first parity and a second parity for data, and a decoding circuit that performs error correction by using the data, the first parity, and the second parity, the first parity is generated by using a first generation polynomial for the data, the second parity is generated by using a second generation polynomial for the input data and the first parity, the second generation polynomial is selected based on the first generation polynomial, the data and the first parity is output to the outside, and the second parity is not output to the outside.. .
08/28/14
20140245100
 Semiconductor memory device patent thumbnailnew patent Semiconductor memory device
A crc code is generated from an original data, a bch code is generated with respect to the original data and the crc code, and the original data, the crc code, and the bch code are recorded in pages selected from different planes of a plurality of memory chips. An rs code is generated from the original data across pages, a crc code is generated with respect to the rs code, a bch code is generated with respect to the rs code and the crc code, and the rs code, the crc code, the bch code are recorded in a memory chip different from a memory chip including the original data.
08/28/14
20140245089
 Semiconductor memory device patent thumbnailnew patent Semiconductor memory device
According to one embodiment, a semiconductor memory device includes memory cells each given one of threshold voltages to store data, and a controller configured to use read voltages to determine threshold voltages of the memory cells. The controller is configured to use voltages over a window to read data from the memory cells to determine distribution of the threshold voltages of the memory cells to estimate a read voltage.
08/28/14
20140245088
 Semiconductor test device and semiconductor test method patent thumbnailnew patent Semiconductor test device and semiconductor test method
There is provided a semiconductor test device, including: a test information acquisition unit acquiring test information; a test information conversion unit converting the acquired test information into test vector information including a plurality of test vectors; and a test signal generation unit generating a test input signal based on the test vector information.. .
08/28/14
20140245087
 Semiconductor integrated circuit with bist circuit patent thumbnailnew patent Semiconductor integrated circuit with bist circuit
According to an embodiment, a semiconductor integrated circuit includes a memory, a bypass circuit, a first selection unit, a compression unit, and a comparison unit. The bypass circuit bypasses the test signal to output a bypass signal.
08/28/14
20140244945
 Electronic device and method for operating electronic device patent thumbnailnew patent Electronic device and method for operating electronic device
An electronic device comprising a semiconductor memory unit that may a variable resistance element configured to be changed in its resistance value in response to current flowing through both ends thereof; an information storage unit configured to store switching frequency information corresponding to a switching frequency which minimizes an amplitude of a voltage to be applied to both ends of the variable resistance element to change the resistance value of the variable resistance element and switching amplitude information corresponding to a minimum amplitude; and a driving unit configured to generate a driving voltage with the switching frequency and the minimum amplitude in response to the switching frequency information and the switching amplitude information and apply the driving voltage to both ends of the variable resistance element.. .
08/28/14
20140244931
 Electronic device patent thumbnailnew patent Electronic device
An electronic device comprising a semiconductor memory unit that may include a cell array including a plurality of storage cells; a first line connected to one ends of the plurality of storage cells; a second line connected to the other ends of the plurality of storage cells; a first driver connected to one end of the first line at a first contact location on one side of the cell array, and configured to apply a first electrical signal to the one end of the first line; and a second driver connected to one end of the second line at a second contact location on a side of the cell array opposing the side of the cell array where the first contact location is located, and configured to apply a second electrical signal to the one end of the second line.. .
08/28/14
20140244930
new patent Electronic devices having semiconductor magnetic memory units
An electronic device comprising a semiconductor memory unit that includes a resistance variable element configured to be changed in a resistance value according to a value of data stored therein; a first reference resistance element having a first resistance value; a second reference resistance element having a second resistance value larger than the first resistance value; and a comparison unit configured to receive a voltage corresponding to the resistance value of the resistance variable element through a first input terminal and a second input terminal thereof, a voltage corresponding to the first resistance value of the first reference resistance element through a third input terminal, and a voltage corresponding to the second resistance value of the second reference resistance element through a fourth input terminal, the comparison unit configured to output a result of comparing inputs to the first input terminal and the second input terminal and inputs to the third input terminal and fourth input terminal.. .
08/28/14
20140244909
new patent Semiconductor memory device
According to one embodiment, a semiconductor memory device includes: string units including a plurality of memory cells stacked above a semiconductor substrate; and a control circuit configured to perform an erase operation per a block, the block including the string units, the control circuit being configured to perform an erase verify operation per string unit.. .
08/28/14
20140244903
new patent Controller, semiconductor storage device and method of controlling data writing
According to one embodiment, a memory controller includes a mode selection part that selects one of a mlc-mode and a slc-mode, after a write command is decoded by a command decode part, and a write part that executes a data writing to a storage memory by using one of the mlc-mode and the slc-mode selected by the mode selection part. The mode selection part is configured to check whether a first data wrote from a host to a buffer memory is a time-continuous data that is wrote continuously during a predetermined period, execute the data writing of a second data from the buffer memory to the storage memory in the mlc-mode, when the first data is the time-continuous data, and execute the data writing of the second data from the buffer memory to the storage memory in the slc-mode, when the first data is not the time-continuous data..
08/28/14
20140244864
new patent Semiconductor memory device capable of testing signal integrity
According to one embodiment, a semiconductor memory device includes a memory cell array, a first buffer, a second buffer, an interface unit and a controller. Data is transferred between the interface unit and the first buffer.
08/28/14
20140244255
new patent Speech recognition device and method, and semiconductor integrated circuit device
A semiconductor integrated circuit device for speech recognition includes a conversion candidate setting unit that receives text data indicating words or sentences together with a command and sets the text data in a conversion list in accordance with the command; a standard pattern extracting unit that extracts, from a speech recognition database, a standard pattern corresponding to at least a part of the words or sentences indicated by the text data that is set in the conversion list; a signal processing unit that extracts frequency components of an input speech signal and generates a feature pattern indicating distribution of the frequency components; and a match detecting unit that detects a match between the feature pattern generated from at least a part of the speech signal and the standard pattern and outputs a speech recognition result.. .
08/28/14
20140244226
new patent Compact opc model generation using virtual data
A method, system or computer usable program product for building a fast lithography opc model that predicts semiconductor manufacturing process outputs on silicon wafers including providing a first principles model of the semiconductor manufacturing process, providing a set of empirical data for storage in memory, utilizing a processor to develop a rigorous model for a process condition from the first principles model and the set of empirical data, and utilizing the processor running the rigorous model to generate emulated data for the process condition to develop a virtual model for predicting the semiconductor manufacturing process outputs.. .
08/28/14
20140244020
new patent Anomaly detection method, computer-readable non-transitory storage medium, and anomaly detection apparatus
In accordance with an embodiment, an anomaly detection method includes acquiring coordinate data of defects or particles generated on a wafer during a semiconductor manufacturing process, calculating an eberhardt's index from the acquired data, calculating a first probability point, comparing the calculated eberhardt's index with the first probability point, and judging presence/absence in state of a spatial point distribution relative to the defects or the particles. The first probability point is calculated based on a sample distribution of the eberhardt's index..
08/28/14
20140243242
new patent Compositions and methods for co-amplifying subsequences of a nucleic acid fragment sequence
The present invention is related to genomic nucleotide sequencing. In particular, the invention describes a single reaction method to co-amplify multiple subsequences of a nucleic acid fragment sequence (i.e., for example, at least two read pairs from a single library insert sequence).
08/28/14
20140242894
new patent Polishing pad and method for producing same
Provided are: a polishing pad which is capable of alleviating a scratch problem that occurs when a conventional hard (dry) polishing pad is used, and which is excellent in polishing rate and polishing uniformity and is usable not only for primary polishing but also for finish polishing; and a method for producing the polishing pad. The polishing pad is for polishing a semiconductor device and includes a polishing layer having a polyurethane-polyurea resin molded body containing cells of a substantially spherical shape.
08/28/14
20140242815
new patent Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device according to the present invention includes the steps of (b) forming, on a back face of a dummy substrate and back faces of a plurality of semiconductor substrates, inorganic films having such thicknesses as to be resistant to a temperature of a thermal oxidizing treatment or a heat treatment and to sufficiently decrease an amount of oxidation or reducing gaseous species to reach the back faces of the dummy substrate and the plurality of semiconductor substrates, (c) disposing the dummy substrate and the plurality of semiconductor substrates in a lamination with surfaces turned in the same direction at an interval from each other, and (d) carrying out a thermal oxidizing treatment or post annealing over the surfaces of the semiconductor substrates in an oxidation gas atmosphere or a reducing gas atmosphere after the steps (b) and (c).. .
08/28/14
20140242812
new patent Method of forming dielectric films, new precursors and their use in semiconductor manufacturing
Method of deposition on a substrate of a dielectric film by introducing into a reaction chamber a vapor of a precursor selected from the group consisting of zr(mecp)(nme2)3, zr(etcp)(nme2)3, zrcp(nme2)3, zr(mecp)(netme)3, zr(etcp)(netme)3, zrcp(netme)3, zr(mecp)(net2)3, zr(etcp)(net2)3, zrcp(net2)3, zr(ipr2cp)(nme2)3, zr(tbu2cp)(nme2)3, hf(mecp)(nme2)3, hf(etcp)(nme2)3, hfcp(nme2)3, hf(mecp)(netme)3, hf(etcp)(netme)3, hfcp(netme)3, hf(mecp)(net2)3, hf(etcp)(net2)3, hfcp(net2)3, hf(ipr2cp)(nme2)3, hf(tbu2cp)(nme2)3, and mixtures thereof; and depositing the dielectric film on the substrate.. .
08/28/14
20140242809
new patent Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
A method of manufacturing a semiconductor device is disclosed. The method includes forming a film containing a predetermined element and carbon on a substrate by performing a cycle a predetermined number of times.
08/28/14
20140242808
new patent Semiconductor device manufacturing method and substrate processing system
A semiconductor device manufacturing method includes forming a first high-k insulating film on a processing target object; performing a crystallization heat-treatment process on the first high-k insulating film at a temperature equal to or higher than about 650° c. For a time less than about 60 seconds; and forming, on the first high-k insulating film, a second high-k insulating film containing a metal element having an ionic radius smaller than that of a metal element of the first high-k insulating film and having a relative permittivity higher than that of the first high-k insulating film..
08/28/14
20140242804
new patent Integrated platform for improved wafer manufacturing quality
The present disclosure relates to a method and apparatus for performing a dry plasma procedure, while mitigating internal contamination of a semiconductor substrate. In some embodiments, the apparatus includes a semiconductor processing tool having a dry process stage with one or more dry process elements that perform a dry plasma procedure on a semiconductor substrate received from an input port.
08/28/14
20140242802
new patent Semiconductor process
A semiconductor process includes the following steps. A wafer on a pedestal is provided.
08/28/14
20140242800
new patent Methods of forming layer patterns of a semiconductor device
A method of manufacturing a layer pattern of a semiconductor device, the method including forming an anti-reflective coating (arc) layer on an etching object layer such that the arc layer includes a polymer having an imide group; forming a photoresist pattern on the arc layer; wet etching portions of the arc layer exposed by the photoresist pattern to form an arc layer pattern; and etching the etching object layer using the photoresist pattern as an etch mask to form the layer pattern.. .
08/28/14
20140242799
new patent Pattern formation method and method for manufacturing semiconductor device
According to one embodiment, a pattern formation method includes forming a first mask layer including a first and a second concave pattern on a first surface of a substrate. The method can include providing a protection film in the first concave pattern.
08/28/14
20140242797
new patent Semiconductor fabrication method using stop layer
A method of making a semiconductor assembly including the steps of: (i) providing an initial-state assembly including: (a) a fin layer, and (b) a hard mask layer located on top of at least a portion of the fin layer; (ii) performing a first material removal on the initial-state assembly, by cmp, to yield a second-state assembly; and (iii) performing a second material removal on the second-state assembly to yield a third-state assembly. In the first material-removal step: (i) any remaining portion of the soft sacrificial layer is removed, (ii) a portion of the fin layer is removed, and (iii) the lower portion of the hard mask layer is used as a stop layer for the second material removal..
08/28/14
20140242796
new patent Method of manufacturing semiconductor device
To improve a semiconductor device having a nonvolatile memory. A first misfet, a second misfet, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover.
08/28/14
20140242793
new patent Pattern forming method and method of manufacturing semiconductor device
According to one embodiment, a core material is ejected onto an object using an inkjet method to form a core pattern on the object, a mask pattern is formed on the object so as to embed the core pattern, and the core pattern which is embedded in the mask pattern is removed.. .
08/28/14
20140242792
new patent Method for forming semiconductor device
A method for forming a semiconductor device is provided, which may include: providing an interlayer dielectric layer, a metal layer formed on the interlayer dielectric layer, an etch stop layer formed on the metal layer, and a first opening extending through the etch stop layer and the metal layer, wherein the interlayer dielectric layer is exposed from the first opening; forming a protecting layer on the sidewall of the first opening to cover the metal layer; after forming the protecting layer, forming a second opening by etching a portion of the interlayer dielectric layer; and forming an isolating layer by filling up the second opening, wherein the isolating layer includes an air gap. The semiconductor device is more stable in performance..
08/28/14
20140242790
new patent Method of manufacturing semiconductor device
A metal-containing film capable of adjusting a work function is formed. A first source containing a first metal element and a halogen element and a second source containing a second metal element different from the first metal element and an amino group are alternately supplied onto a substrate having a high-k dielectric film to form a composite metal nitride film on the high-k dielectric film..
08/28/14
20140242789
new patent Semiconductor device manufacturing method
A semiconductor device manufacturing method includes forming a dielectric film on a semiconductor substrate; performing a heat treatment on the dielectric film; forming an electrode on a first region of the dielectric film; irradiating an ionized gas cluster to a second region of the dielectric film where the electrode is not formed; and removing the second region of the dielectric film where the ionized gas cluster is irradiated by a wet etching after the irradiating of the ionized gas cluster.. .
08/28/14
20140242788
new patent Method of forming a high quality interfacial layer for a semiconductor device by performing a low temperature ald process
One illustrative method disclosed herein includes performing an atomic layer deposition (ald) process at a temperature of less than 400° c. To deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide..
08/28/14
20140242787
new patent Photosensitive resin composition and method for producing semiconductor device
Disclosed is a photosensitive resin composition which exhibits positive or negative photosensitivity and is used as a mask in an ion implantation step, the photosensitive resin composition including, as a resin, (a) a polysiloxane. The photosensitive resin composition of the present invention has high heat resistance and is capable of controlling a pattern shape, and also has excellent ion implantation mask performance, thus enabling application to a low-cost high-temperature ion implantation process..
08/28/14
20140242786
new patent Method of manufacturing nonvolatile semiconductor memory device
According to one embodiment, a method includes forming first and second gate patterns each including a structure stacked in order of a first insulating layer, a floating gate layer, a charge trap layer, a second insulating layer and a dummy layer on a semiconductor layer, implanting impurities in the semiconductor layer by an ion implantation using the first and second gate patterns as a mask, forming a third insulating layer on the semiconductor layer, the third insulating layer covering side surfaces of the first and second gate patterns, and forming first and second concave portions, the first concave portion formed by removing the dummy layer of the first gate pattern, the second concave portion formed by removing the dummy layer, the second insulating layer, the charge trap layer and the floating gate layer of the second gate pattern.. .
08/28/14
20140242785
new patent Semiconductor films on sapphire glass
A method is disclosed for growing large grain to single crystalline semiconductor films on inexpensive glass substrates. The method comprises deposition of semiconductor films from a eutectic melt on sapphire glass.
08/28/14
20140242782
new patent Methods of transferring semiconductor elements and manufacturing semiconductor devices
The present disclosure relates to a method of transferring semiconductor elements from a non-flexible substrate to a flexible substrate. The present disclosure also relates to a method of manufacturing a flexible semiconductor device based on the method of transferring semiconductor elements.
08/28/14
20140242781
new patent Coating adhesives onto dicing before grinding and micro-fabricated wafers
A method for preparing a semiconductor wafer into individual semiconductor dies uses both a dicing before grinding step and/or via hole micro-fabrication step, and an adhesive coating step.. .
08/28/14
20140242779
new patent Semiconductor device manufacturing method and manufacturing apparatus
According to one embodiment, a semiconductor device manufacturing method includes: bonding a first wafer and a second wafer to each other, to form a stack; rubbing a film attached with a fill material in a thin-film shape into a gap located between a bevel of the first wafer and a bevel of the second wafer, to fill the gap with the fill material; and thinning the first wafer.. .
08/28/14
20140242778
new patent Methods of forming strained-semiconductor-on-insulator device structures
The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.. .
08/28/14
20140242777
new patent Method for bonding semiconductor devices
A method of attaching first and second semiconductor devices to one another includes applying plating gel over a surface of a first semiconductor device, positioning bonding regions of a second semiconductor device in contact with the plating gel on corresponding bonding regions on the first semiconductor device, and reacting at least some the plating gel to bond the second semiconductor device to the first semiconductor device.. .
08/28/14
20140242776
new patent Strained isolation regions
A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material.
08/28/14
20140242775
new patent Method of fabricating finfets
The disclosure relates to a method of fabricating a semiconductor device including forming a patterned hardmask layer over a substrate comprising a major surface. The method further includes forming a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (esc) temperature between about 90° c.
08/28/14
20140242773
new patent Phase change memory device having self-aligned bottom electrode and fabrication method thereof
A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer..
08/28/14
20140242772
new patent Method for fabricating semiconductor device
A semiconductor device includes a dielectric layer in which zirconium, hafnium, and a iv group element are mixed. A method for fabricating a capacitor includes forming a bottom electrode, forming the dielectric layer and forming a top electrode over the dielectric layer..
08/28/14
20140242771
new patent Method for manufacturing a semiconductor device
A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer.
08/28/14
20140242770
new patent Semiconductor process
A semiconductor process includes the following step. A stacked structure is formed on a substrate.
08/28/14
20140242769
new patent Method of manufacturing a super-junciton semiconductor device
A method of manufacturing a super-junction semiconductor device is disclosed that allows forming a high concentration layer with high precision and improves the trade-off relationship between the eoff and the dv/dt using a trench embedding method. The method comprises a step of forming a parallel pn layer using a trench embedding method and a step of forming a proton irradiated layer in the upper region of the pn layer.
08/28/14
20140242768
new patent Reducing wafer distortion through a high cte layer
Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides.
08/28/14
20140242767
new patent Method of manufacturing a semiconductor device
After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed.
08/28/14
20140242766
new patent Method for manufacturing semiconductor device and semiconductor device
A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact.. .
08/28/14
20140242764
new patent Three dimensional non-volatile storage with asymmetrical vertical select devices
A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate.
08/28/14
20140242763
new patent Method for fabricating nonvolatile memory structure
A nonvolatile memory structure includes a semiconductor substrate having thereon a first oxide define (od) region, a second od region and a third od region arranged in a row. The first, second, and third od regions are separated from one another by an isolation region.
08/28/14
20140242762
new patent Tunable schottky diode with depleted conduction path
A method of fabricating a schottky diode having an integrated junction field-effect transistor (jfet) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the schottky diode. The conduction path region has a first conductivity type.
08/28/14
20140242761
new patent High electron mobility transistor and method of forming the same
A method of forming a semiconductor structure, the method includes epitaxially growing a second iii-v compound layer on a first iii-v compound layer. A carrier channel is located between the first iii-v compound layer and the second iii-v compound layer.
08/28/14
20140242760
new patent Semiconductor radio frequency switch with body contact
The present disclosure relates to a radio frequency (rf) switch that includes multiple body-contacted field effect transistor (fet) elements coupled in series. The fet elements may be formed using a thin-film semiconductor device layer, which is part of a thin-film semiconductor die.
08/28/14
20140242759
new patent Reducing wafer distortion through a high cte layer
Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides.
08/28/14
20140242756
new patent Method for preparing semiconductor devices applied in flip chip technology
A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices.. .
08/28/14
20140242754
new patent Multi-chip package and method of manufacturing the same
A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate.
08/28/14
20140242752
new patent Method of fabricating semiconductor package
A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (tsvs) and a lower area not having the tsvs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the tsvs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer.. .
08/28/14
20140242749
new patent Method for manufacturing semiconductor device
Electrical characteristics of transistors using an oxide semiconductor are greatly varied in a substrate, between substrates, and between lots, and the electrical characteristics are changed due to heat, bias, light, or the like in some cases. In view of the above, a semiconductor device using an oxide semiconductor with high reliability and small variation in electrical characteristics is manufactured.
08/28/14
20140242745
new patent Solid-state imaging device, method of manufacturing same, and electronic apparatus
A solid-state imaging device includes a plurality of photoelectric conversion units configured to receive light and generate signal charge, the plurality of photoelectric conversion units being provided in such a manner as to correspond to a plurality of pixels in a pixel area of a semiconductor substrate; and pixel transistors configured to output the signal charge generated by the photoelectric conversion units as electrical signals. Each of the pixel transistors includes at least a transfer transistor that transfers the signal charge generated in the photoelectric conversion unit to a floating diffusion corresponding to a drain.
08/28/14
20140242741
new patent Material for forming passivation film for semiconductor substrate, passivation film for semiconductor substrate and method of producing the same, and photovoltaic cell element and method of producing the same
The invention provides a material for forming a passivation film for a semiconductor substrate. The material includes a polymer compound having an anionic group or a cationic group..
08/28/14
20140242735
new patent Method for aligning a biochip
A method of aligning a semiconductor chip includes forming a semiconductor chip with a light-activated circuit including at least one photosite, positioning the semiconductor chip relative to a device, and illuminating the positioned semiconductor chip. The method further includes generating an rf signal with an rf circuit based upon illumination of the at least one photosite, and determining the position of the photosite with respect to the device based upon the generated rf signal..
08/28/14
20140242734
new patent Leadframe, semiconductor device, and method of manufacturing the same
A method of manufacturing a semiconductor device includes mounting at least one of a first semiconductor chip and a second semiconductor chip over a die pad of a leadframe, and inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, wherein the leadframe includes first mark formed to the die pad, for indicating a first mounting region for the first semiconductor chip, and second mark formed to the die pad, for indicating a second mounting region for the second semiconductor chip, the first mark is different from the second mark, in at least either one of size and geometry, wherein, in the inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, a mounting position of the first semiconductor chip is inspected when the first semiconductor chip is mounted.. .
08/28/14
20140242733
new patent Reflective mask, method of monitoring the same, and method of manufacturing semiconductor device
According to one embodiment, provided is a reflective mask having a substrate, a reflection layer that reflects euv light formed above the substrate, and an absorption layer that absorbs the euv light formed above the reflection layer. The reflective mask further includes a monitor pattern monitoring an attachment amount of contamination attached during exposure..
08/28/14
20140242538
new patent Radiation source and light guiding device
The invention relates to a radiation source, in particular a light curing device, for the polymerization of dental materials, comprising a light conductor and a light generation device which has at least two light sources, preferably semiconductor light sources, in particular light diodes, and the radiation of which is bundled by a reflector and fed into the light conductor. The light sources differ from one another with respect to their light color and/or their emission spectrum and are controllable separately for changing the light color and/or the emission spectrum and/or the spectral radiant power of the radiation emitted.
08/28/14
20140242526
new patent Positive tone organic solvent developed chemically amplified resist
Provided is a method for developing positive-tone chemically amplified resists with an organic developer solvent having at least one polyhydric alcohol, such as ethylene glycol and/or glycerol, alone or in combination with an additional organic solvent, such as isopropyl alcohol, and/or water. The organic solvent developed positive tone resists described herein are useful for lithography pattern forming processes; for producing semiconductor devices, such as integrated circuits (ic); and for applications where basic solvents are not suitable, such as the fabrication of chips patterned with arrays of biomolecules or deprotection applications that do not require the presence of acid moieties..
08/28/14
20140242503
new patent Method of manufacturing a color filter
A color filter is manufactured on each of a plurality of light-receiving elements of an rgb sensor using a plurality of kinds of light-transmitting films having different transmission colors. In such a case, the light-transmitting film that is to be coated next does not uniformly spread across the entire semiconductor wafer, and coating nonuniformities readily occur when a pattern of the light-transmitting film formed earlier on a certain optical element has a right angle portion.
08/28/14
20140242499
new patent Light-reflective photomask and mask blank for euv exposure, and manufacturing method of semiconductor device
According to one embodiment, a light-reflective photomask including a circuit pattern area, and an outside area positioned outside the circuit pattern area includes a substrate, a low-reflectivity layer provided in both the circuit pattern area, and the outside area, formed on the substrate, including at least a conductive layer, and comprising a first reflectivity for deep ultraviolet light, a multilayer reflection layer provided in the circuit pattern area, and formed on the low-reflectivity layer, and a light-absorber provided in the circuit pattern area, formed on the multilayer reflection layer, including a circuit pattern, and comprising a second reflectivity for deep ultraviolet light. The first reflectivity is lower than or equal to the second reflectivity..


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Semiconductor topics: Semiconductor, Semiconductor Substrate, Semiconductor Device, Semiconductor Material, Electric Conversion, Conductive Layer, Molybdenum, Camera Module, Semiconductor Devices, Semiconductors, Integrated Circuit, Surfactant, Photoelectric Conversion, Electronic Device, Transparent Conductive Oxide

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