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Semiconductor patents



      
           
This page is updated frequently with new Semiconductor-related patent applications. Subscribe to the Semiconductor RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor RSS RSS


Methods for forming a round bottom silicon trench recess for semiconductor applications

Applied Materials

Methods for forming a round bottom silicon trench recess for semiconductor applications

Mechanisms for cleaning substrate surface for hybrid bonding

Taiwan Semiconductor Manufacturing

Mechanisms for cleaning substrate surface for hybrid bonding

Mechanisms for cleaning substrate surface for hybrid bonding

Ye Xin Technology Consulting

Display panel and manufacturing method thereof

Date/App# patent app List of recent Semiconductor-related patents
01/29/15
20150033201
 Systems and methods for fabricating semiconductor device structures patent thumbnailnew patent Systems and methods for fabricating semiconductor device structures
Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining raw measurement data for a wafer of semiconductor material from a metrology tool and adjusting a measurement model utilized by a metrology tool based at least in part on the raw measurement data and a value for a design parameter.
Globalfoundries, Inc.
01/29/15
20150033089
 Semiconductor device patent thumbnailnew patent Semiconductor device
A semiconductor device includes a compression block configured to compare and compress data of a plurality of core array blocks, by a unit of a group; a combination block configured to combine outputs of the compression block and output compression data; and a control block configured to latch the compression data and output latched data, and drive the latched data and the compression data and output resultant data to a first data line and a second data line.. .
Sk Hynix Inc.
01/29/15
20150033050
 Semiconductor integrated circuit and computing device including the same patent thumbnailnew patent Semiconductor integrated circuit and computing device including the same
A semiconductor integrated circuit and a computing system including the same are provided. The semiconductor integrated circuit includes: an integrated clock gating cell including a clock output node; and clock-based cells each including a clock input node.
Samsung Electronics Co., Ltd
01/29/15
20150032960
 Electronic devices having semiconductor memory units and  fabricating the same patent thumbnailnew patent Electronic devices having semiconductor memory units and fabricating the same
Electronic devices have a semiconductor memory unit including a magnetization compensation layer in a contact plug. One implementation of the semiconductor memory unit includes a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer, and a contact plug arranged in at least one side of the variable resistance element and comprising a magnetization compensation layer.
Sk Hynix Inc.
01/29/15
20150032949
 Semiconductor device and  controlling non-volatile memory device patent thumbnailnew patent Semiconductor device and controlling non-volatile memory device
A control circuit of a semiconductor device (memory module) realizes long life and others by a mechanism that suppresses and smoothes variations in use of a memory by equalizing the sizes of data write and data erase with respect to a data write request and sequentially allocating and using addresses of the memory in data write to an overwritable non-volatile memory device without carrying out an overwriting operation even in the case of an overwrite request. The control circuit realizes data write by a set of two types of operations of (a) an operation of erasing data of a first address or an operation of setting a flag value to an invalid state and (b) an operation of writing data to a second address different from the first address or an operation of setting a flag value to a valid state..
Hitachi, Ltd.
01/29/15
20150032948
 Semiconductor storage device and  throttling performance of the same patent thumbnailnew patent Semiconductor storage device and throttling performance of the same
A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state; and a controller configured to control the non-volatile memory device.
01/29/15
20150032939
 Semiconductor memory garbage collection patent thumbnailnew patent Semiconductor memory garbage collection
For semiconductor memory garbage collection, an identification module identifies a garbage collection time window for at least one block of a flash memory array. A garbage collection module garbage collects a first block of the flash memory array with a highest garbage collection level and an open garbage collection time window..
International Business Machines Corporation
01/29/15
20150032404
 Method and device for determining the temperature calibration characteristic curve of a semiconductor component appertaining to power electronics patent thumbnailnew patent Method and device for determining the temperature calibration characteristic curve of a semiconductor component appertaining to power electronics
The invention relates to methods and devices for determining the temperature calibration characteristic curve of a semiconductor component (3) appertaining to power electronics. They are distinguished, in particular, by the fact that the temperature calibration characteristic curve can be determined in a simple and economically advantageous manner.
Siemens Aktiengesellschaft
01/29/15
20150032394
 Power management system patent thumbnailnew patent Power management system
A battery monitoring unit monitors at least one from among: (i) the attachment state of secondary battery pack; (ii) the low state of a battery voltage vbat; and (iii) the state of whether it is possible or impossible to use the secondary battery. A battery measurement unit measures the battery voltage vbat, a charge/discharge current ibat, and a temperature t of the secondary battery pack, and converts the measured values into digital data.
Rohm Co., Ltd.
01/29/15
20150032388
 Method of controlling transmission apparatus, transmission apparatus, and recording medium patent thumbnailnew patent Method of controlling transmission apparatus, transmission apparatus, and recording medium
A method of controlling a transmission apparatus, executed by a processor, the transmission apparatus including a plurality of ports capable of connection to an optical module, the method includes receiving operating time information of the optical module, and monitor information including at least one of information on temperature of the optical module, optical output power, and a bias current value of a semiconductor laser at predetermined time intervals, when the optical module is coupled to a first port; calculating a deterioration point based on the operating time information and the monitor information at the predetermined time intervals; calculating an accumulated deterioration point by adding the deterioration point at the predetermined time intervals; and determining a deterioration degree of the optical module based on the accumulated deterioration point, when the optical module is recoupled to the first port, or when the optical module is coupled to a second port.. .
Fujitsu Limited
01/29/15
20150031996
new patent

Semiconducting polymer nanoparticles as photoacoustic molecular imaging probes


Provided are nanoparticles comprising an organic photovoltaic semiconductor polymer and a phospholipid, the semiconductor polymer being near-infra red absorbing and generating a detectable photoacoustic signal and a fluorescent emission when irradiated by an incident activation energy. Also provided are methods of molecular imaging, comprising delivering to a subject a plurality of said nanoparticles, irradiating the subject with a first incident energy to generate a first photoacoustic signal, irradiating the subject with a second incident energy to generate a second photoacoustic signal, determining a ratio of the intensities of the two photoacoustic signals, comparing this first ratio with a second ratio determined from the nanoparticles before delivery to the subject, whereby a difference in said first and second ratios indicates ros degradation of the nanoparticles in the subject; and generating a ratiometric image indicating the difference in said first and second ratios relative to an image of the subject..
The Board Of Trustees Of The Leland Stanford Junior University
01/29/15
20150031216
new patent

Cleaning method, manufacturing semiconductor device, substrate processing apparatus, and recording medium


There is provided a method of cleaning an inside of a process chamber, which is formed by a reaction tube and a manifold configured to support the reaction tube and installed under a heater, after forming a stacked film of oxide and nitride films on a substrate in the process chamber by alternately performing forming the oxide film on the substrate and forming the nitride film thereon. The method includes supplying a hydrogen-free fluorine-based gas from a first nozzle, which is installed in the manifold to extend upward from the manifold to an inside of the reaction tube, to an inner wall of the reaction tube; and supplying a hydrogen fluoride gas from a second nozzle, which is installed in the manifold, to an inner wall of the manifold..
Hitachi Kokusai Electric, Inc.
01/29/15
20150031211
new patent

Intrench profile


A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density.
Applied Materials, Inc.
01/29/15
20150031209
new patent

Method for forming features with sub-lithographic pitch using directed self-assembly of polymer blend


There is provided a manufacturing method of a semiconductor device including forming a first pattern of first features, according to a lithography process, in a photoresist layer disposed on a substrate, the lithography process having a minimum printable dimension and a minimum printable pitch, applying an additional layer on the photoresist layer having the first pattern formed therein, forming a second pattern of second features in the additional layer, the second features concentric with the first features, and etching portions of the substrate exposed through the second pattern. Further, in the provided method, the first features include geometrical features separated by a distance less than the dimension of minimum printable feature, and the geometrical features are disposed at a pitch less than the minimum printable pitch..
Renesas Electronics Corporation
01/29/15
20150031208
new patent

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device, includes the steps of forming a top surface nitride film on a top surface of a substrate and a bottom surface nitride film on a bottom surface of the substrate, forming a protective film on the top surface nitride film, removing the bottom surface nitride film by wet etching while the top surface nitride film is being protected by the protective film, removing the protective film after the removing of the bottom surface nitride film, patterning the top surface nitride film so as to form an opening in the top surface nitride film, and forming a second oxide film on the bottom surface of the substrate while forming a first oxide film on a surface portion of the substrate which is exposed by the opening.. .
Mitsubishi Electric Corporation
01/29/15
20150031205
new patent

Polishing method


Provided is a polishing method including a step of preparing a substrate having (1) silicon nitride as a stopper, and to a direction of a surface subjected to polishing from the stopper, (2) at least a portion of a wiring metal, and (3) at least a portion of an insulating material; a step of supplying a cmp slurry, and thereby polishing the (2) wiring metal and (3) insulating material on the direction of the surface subjected to polishing; and a step of stopping polishing before the (1) silicon nitride is exposed and completely removed, in which method the cmp slurry contains (a) a copolymer of (a) a monomer that is anionic and does not contain a hydrophobic substituent and (b) a monomer containing a hydrophobic substituent; (b) an abrasive grain; (c) an acid; (d) an oxidizing agent; and (e) a liquid medium, the component (b) has a zeta potential of +10 mv or more in the cmp slurry, and the copolymerization ratio (a):(b) of the component (a) is 25:75 to 75:25 as a molar ratio, with the ph being 5.0 or less. Through this method, an interlayer insulating film and a stopper can be polished at a high selectivity while metal and the interlayer insulating film are removed at high polishing rates, and thus a semiconductor device having high dimensional accuracy can be produced..
Hitachi Chemical Company, Ltd.
01/29/15
20150031202
new patent

Method for manufacturing semiconductor wafers


The invention relates to a method for manufacturing a semiconductor wafer including a conductive via extending from a main surface of the wafer, said the via having a shape factor greater than five, the wafer including a dielectric layer, the method including: producing, by means of deep etching, at least one recess in the semiconductor wafer, the recess extending from the main surface of the wafer and having a shape factor greater than five, the recess including a side surface; forming at least one dielectric layer in the recess, including two treatments in a controlled-pressure reactor, one of said the treatments including the chemical vapor deposition, at sub-atmospheric pressure, of a dielectric onto the side surface of the recess, the chemical deposition being carried out at a temperature lower than 400° c. And at a pressure greater than 100 torr in the reactor, and another of the treatments including the plasma-enhanced chemical vapor deposition of a dielectric onto the side surface of the recess, the chemical deposition being carried out at a pressure of less than 20 torr in the reactor; and filling the recess with a conductive material, thus forming a via..
Altatech Semiconductor
01/29/15
20150031198
new patent

Pattern forming method and manufacturing semiconductor device


According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer.
Kabushiki Kaisha Toshiba
01/29/15
20150031197
new patent

Integrated circuits with non-volatile memory and methods for manufacture


Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region.
Spansion Llc
01/29/15
20150031195
new patent

Method of fabricating a semiconductor device


A method of fabricating a semiconductor device may include conformally forming a gate insulating layer on a substrate having a recess, conformally forming a barrier layer containing fluorine-free tungsten nitride on the substrate with the gate insulating layer using an atomic layer deposition process, and forming a gate electrode on the barrier layer to fill at least a portion of the recess.. .
Samsung Electronics Co., Ltd.
01/29/15
20150031194
new patent

Method for designing antenna cell that prevents plasma induced gate dielectric damage in semiconductor integrated circuits


An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor.
Taiwan Semiconductor Manufacturing Co., Ltd.
01/29/15
20150031193
new patent

Semiconductor substrate suitable for the realization of electronic and/or optoelectronic devices and relative manufacturing process


A semiconductive substrate (1) is described that is suitable for realising electronic and/or optoelectronic devices of the type comprising at least one substrate (3), in particular of single crystal silicon, and an overlying layer of single crystal silicon (5). Advantageously, according to the invention, the semiconductive substrate (1) comprises at least one functional coupling layer (10) suitable for reducing the defects linked to the differences in the materials used.
Consiglio Nazionale Delle Ricerche
01/29/15
20150031191
new patent

Method of manufacturing semiconductor device


To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension line of a dicing region provided between a first semiconductor device region and a second semiconductor device region but is provided between the extension line of the dicing region and a first imaginary extension line of a first outermost peripheral land row and between the extension line of the dicing region and a second imaginary extension line of a second outermost peripheral land row.
Renesas Electronics Corporation
01/29/15
20150031189
new patent

Mechanisms for cleaning substrate surface for hybrid bonding


Embodiments of mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer.
Taiwan Semiconductor Manufacturing Co., Ltd.
01/29/15
20150031187
new patent

Methods for forming a round bottom silicon trench recess for semiconductor applications


Embodiments of the present invention provide methods to etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a cl2 gas into the processing chamber, supplying a rf source power to form a plasma from the etching gas mixture, supplying a pulsed rf bias power in the etching gas mixture, and etching the portion of the silicon substrate exposed through the patterned photoresist layer in the presence of the plasma..
Applied Materials, Inc.
01/29/15
20150031186
new patent

Method of fabricating semiconductor device having dielectric layer with improved electrical characteristics


A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.. .
01/29/15
20150031185
new patent

Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby


The method includes forming an array of first separation walls on an underlying layer. A block co-polymer (bcp) layer is formed to fill inside regions of the first separation walls and gaps between the first separation walls.
Sk Hynix Inc.
01/29/15
20150031183
new patent

Semiconductor devices including silicide regions and methods of fabricating the same


A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween.
Samsung Electronics Co., Ltd.
01/29/15
20150031182
new patent

Method of manufacturing a fin-like field effect transistor (finfet) device


A finfet device and method for fabricating a finfet device is disclosed. An exemplary finfet device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed over a portion of the fin structure.
Taiwan Semiconductor Manufacturing Company, Ltd.
01/29/15
20150031181
new patent

Replacement source/drain finfet fabrication


A finfet is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer.
Advanced Ion Beam Technology, Inc.
01/29/15
20150031179
new patent

Method of forming a semiconductor structure including silicided and non-silicided circuit elements


A method includes providing a semiconductor structure including at least one first circuit element including a first semiconductor material and at least one second circuit element including a second semiconductor material. A dielectric layer having an intrinsic stress is formed that includes a first portion over the at least one first circuit element and a second portion over the at least one second circuit element.
Globalfoundries Inc.
01/29/15
20150031176
new patent

Semiconductor device containing hemt and misfet and forming the same


A semiconductor structure with a misfet and a hemt region includes a first iii-v compound layer. A second iii-v compound layer is disposed on the first iii-v compound layer and is different from the first iii-v compound layer in composition.
Taiwan Semiconductor Manufacturing Company, Ltd.
01/29/15
20150031175
new patent

Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device, includes providing a silicon semiconductor substrate which is manufactured by a floating zone method; and performing thermal diffusion at a heat treatment temperature that is equal to or higher than 1290° c. And that is lower than a melting temperature of a silicon crystal to form a diffusion layer with a depth of 50 μm or more in the silicon semiconductor substrate, the thermal diffusion including a first heat treatment performed in an oxygen atmosphere or a mixed gas atmosphere of oxygen and inert gas, and a second heat treatment performed in a nitrogen atmosphere or a mixed gas atmosphere of nitrogen and oxygen to form the diffusion layer.
Fuji Electric Co., Ltd.
01/29/15
20150031173
new patent

Copper post solder bumps on substrates


A method comprises forming semiconductor flip chip interconnects having electrical connecting pads and electrically conductive posts terminating in distal ends operatively associated with the pads. We solder bump the distal ends by injection molding, mask the posts on the pads with a mask having a plurality of through hole reservoirs and align the reservoirs in the mask to be substantially concentric with the distal ends.
International Bushiness Machines Corporation
01/29/15
20150031170
new patent

Method and stacked semiconductor chips


Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip..
Samsung Electronics Co., Ltd.
01/29/15
20150031169
new patent

Method for manufacturing semiconductor device


An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like.
Semiconductor Energy Laboratory Co., Ltd.
01/29/15
20150031168
new patent

Display panel and manufacturing method thereof


A display panel manufacturing method includes forming a gate electrode on a substrate and a gate insulator, a semiconductor layer, and an etch stop layer covering the gate electrode. A photoresist layer covering on the etch stop layer is pattern from two opposite side of the substrate by two photolithography processes to form a photoresist pattern.
Ye Xin Technology Consulting Co., Ltd.
01/29/15
20150031162
new patent

Photoelectric conversion device, image pickup system and manufacturing photoelectric conversion device


A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate.
Canon Kabushiki Kaisha
01/29/15
20150031150
new patent

Method for producing a radiation-emitting semiconductor component


A method for producing a radiation-emitting semiconductor component is provided, comprising the following steps:—providing a growth substrate (1)—depositing a nucleation layer (2) on the growth substrate (1),—applying a structured dielectric layer (3) to the nucleation layer (2),—applying an epitaxial layer (4) by means of a facelo process to the structured dielectric layer (3),—epitaxial growth of an epitaxial layer sequence (5) on the epitaxial layer (4), wherein the epitaxial layer sequence (5) comprises an active zone (6) that is suitable for producing electromagnetic radiation.. .
Osram Opto Semiconductors Gmbh
01/29/15
20150031149
new patent

Multi-chip package and manufacturing the same


A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad.
Samsung Electronics Co., Ltd.


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Semiconductor topics: Semiconductor, Semiconductor Substrate, Semiconductor Device, Semiconductor Material, Electric Conversion, Conductive Layer, Molybdenum, Camera Module, Semiconductor Devices, Semiconductors, Integrated Circuit, Surfactant, Photoelectric Conversion, Electronic Device, Transparent Conductive Oxide

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