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Semiconductor patents



      
           
This page is updated frequently with new Semiconductor-related patent applications. Subscribe to the Semiconductor RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor RSS RSS


Semiconductor system

Semiconductor system

Error correction in multiple semiconductor memory units

Error correction in multiple semiconductor memory units

Error correction in multiple semiconductor memory units

Semiconductor apparatus and memory system

Date/App# patent app List of recent Semiconductor-related patents
11/20/14
20140344771
 Optical semiconductor device, socket, and optical semiconductor unit patent thumbnailOptical semiconductor device, socket, and optical semiconductor unit
An optical semiconductor unit of the present invention has an led device provided with an led (light emitting diode) and a socket to which the led device is mounted, the led device has a main body to which the led is mounted, the main body has a first surface to which block-shaped electrode portions are connected.. .
11/20/14
20140344654
 Semiconductor system patent thumbnailSemiconductor system
A semiconductor system including a semiconductor circuit configured to compare a first error detection code generated by performing an operation on read data to a second error detection code and determine a data transmission error, and a controller configured to provide the second error detection code, generated by performing an operation on expect data based on the read data, to the semiconductor circuit.. .
11/20/14
20140344644
 Error correction in multiple semiconductor memory units patent thumbnailError correction in multiple semiconductor memory units
Various embodiments include apparatus and methods to store data in a first semiconductor memory unit and to store error correction information in a second semiconductor memory unit to recover the data. The error correction information has a value equal to at least the value of the data store in the first memory unit..
11/20/14
20140344613
 Semiconductor apparatus and memory system patent thumbnailSemiconductor apparatus and memory system
A semiconductor apparatus includes a chip id generation unit, a chip id transmission unit and a chip stack information generation unit. The chip id generation unit is configured to generate a chip id signal.
11/20/14
20140344612
 Semiconductor device, semiconductor device testing method, and data processing system patent thumbnailSemiconductor device, semiconductor device testing method, and data processing system
1. A semiconductor device includes an interface chip, a core chip, and a measurement-target signal line and a reference signal line, each including a through electrode penetrating through the core chip and each having a first end provided on the core chip and a second end provided on the interface chip.
11/20/14
20140344505
 Semiconductor device and method of operating the same patent thumbnailSemiconductor device and method of operating the same
A semiconductor device includes a memory block including memory cells coupled to bit lines, read/write circuits each including cache latch suitable for temporarily storing data to be stored in the memory cells, wherein the read/write circuits are divided into a plurality of groups and perform a program operation to store the data in the memory cells coupled to the bit lines, and an initialization control unit suitable for initializing the cache latches of the read/write circuits of a group corresponding to the address before the data is input to the cache latches, when a program command and an address are input.. .
11/20/14
20140343884
 Method and system for intelligent weak pattern diagnosis, and non-transitory computer-readable storage medium patent thumbnailMethod and system for intelligent weak pattern diagnosis, and non-transitory computer-readable storage medium
Disclosure herein is related to a method and a system for intelligent weak pattern diagnosis for semiconductor product, and a related non-transitory computer-readable storage medium. In the method, a weak pattern layout is firstly retrieved from a defect pattern library and a frequent failure defect pattern library; defect data is retrieved from fab defect inspection tool; a design layout is then received and weak defect pattern screen is performed to extract known and unknown weak defect patterns.
11/20/14
20140343870
 Determination of acceptor and donor dopant concentrations patent thumbnailDetermination of acceptor and donor dopant concentrations
The concentrations of three acceptor and donor dopants of a semiconductor sample are determined by solving a system of three equations. A first equation is obtained by measuring the free charge carrier concentration of the sample at low temperature, and in then confronting these measurements with a mathematical model suitable for these temperatures.
11/20/14
20140343223
 Process for the production of polyimide and polyamic ester polymers patent thumbnailProcess for the production of polyimide and polyamic ester polymers
This disclosure relates to a process of purifying a polymer. The process includes (a) providing an organic solution containing a polyimide or polyamic ester in at least one polar, aprotic polymerization solvent; (b) adding at least one purification solvent to the organic solution to form a diluted organic solution, the at least one purification solvent is less polar than the at least one polymerization solvent and has a lower water solubility than the at least one polymerization solvent at 25° c.; (c) washing the diluted organic solution with water or an aqueous solution to obtain a washed organic solution; and (d) removing at least a portion of the at least one purification solvent in the washed organic solution to obtain a solution containing a purified polyimide or polyamic ester.
11/20/14
20140342683
 Wireless communication system patent thumbnailWireless communication system
A wireless communication system includes: a filter; and a semiconductor chip including a signal processing integrated circuit having an amplifier, wherein a main surface of the semiconductor chip is provided with a plurality of electrode terminals along an edge portion thereof; wherein the amplifier has a transistor including a control electrode, a first electrode through which a signal is outputted, and a second electrode to which a voltage is applied; wherein the control electrode, the first electrode and the second electrode of the transistor are connected to the electrode terminals, respectively; and wherein none of wirings are arranged between the electrode terminals and placements of the control electrode, the first electrode and the second electrode, making space between the electrodes and the electrode terminals narrow.. .
11/20/14
20140342643
Chemical mechanical polishing fixture having lateral perforation structures
A chemical mechanical polishing fixture having lateral perforation structures includes: a holder and a retaining ring. The holder includes: an annular substrate, a plurality of third holes and a plurality of lateral perforation structures.
11/20/14
20140342575
Method for forming an interfacial layer on a semiconductor using hydrogen plasma
Techniques include a method of forming an interfacial passivation layer between a first semiconductor material (such as germanium) and a high-k gate dielectric. Such techniques include using a hydrogen-based plasma formed using a slotted-plane antenna plasma processing system.
11/20/14
20140342573
Method for manufacturing semiconductor device, method for processing substrate, substrate processing apparatus and recording medium
There is provided a method for manufacturing a semiconductor device, including forming a thin film containing a specific element and having a prescribed composition on a substrate by alternately performing the following steps prescribed number of times: forming a first layer containing the specific element, nitrogen, and carbon on the substrate by alternately performing prescribed number of times: supplying a first source gas containing the specific element and a halogen-group to the substrate, and supplying a second source gas containing the specific element and an amino-group to the substrate, and forming a second layer by modifying the first layer by supplying a reactive gas different from each of the source gases, to the substrate.. .
11/20/14
20140342567
Method of manufacturing semiconductor structure
A method of manufacturing a semiconductor structure. A patterned first hard mask is formed on a substrate.
11/20/14
20140342566
Manufacturing method of semiconductor device
To improve the manufacturing yield of semiconductor devices. Over a semiconductor wafer, a film to be processed is formed; over that film, an antireflection film is formed; and, over the antireflection film, a resist layer is formed.
11/20/14
20140342556
Reusing active area mask for trench transfer exposure
A method of silicide formation in a semiconductor fabrication process is disclosed. An active area (rx) mask is used to form an active silicon area, and is then reused to form a trench transfer (tt) area.
11/20/14
20140342555
Deposition chambers with uv treatment and methods of use
Described are apparatus and methods for processing semiconductor wafers so that a film can be deposited on the wafer and the film can be uv treated without the need to move the wafer to a separate location for treatment. The apparatus and methods include a window which is isolated from the reactive gases by a flow of an inert gas..
11/20/14
20140342553
Method for forming semiconductor structure having opening
According to one embodiment of the present invention, a method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region.
11/20/14
20140342552
Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via
A method for fabricating through-silicon vias (tsvs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill tsvs with plated-conductive material (e.g., copper) from an electroplating solution.
11/20/14
20140342551
Semiconductor devices and method of fabricating the same
In a method of fabricating a semiconductor device, a first sacrificial layer, a first insulating layer, and a second sacrificial layer are successively provided on a substrate. The second sacrificial layer, the first insulating layer, and the first sacrificial layer are patterened to define an opening exposing a portion of the substrate and successively forming second sacrificial patterns, capping patterns, and first sacrificial patterns on the substrate.
11/20/14
20140342550
Method for fabricating semiconductor device by damascene process
A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes.. .
11/20/14
20140342548
Integrated circuit devices including interconnections insulated by air gaps and methods of fabricating the same
Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection.
11/20/14
20140342546
Copper pillar bump with cobalt-containing sidewall protection layer
A method of forming an integrated circuit device comprises forming a metal pillar over a semiconductor substrate. The method also comprises forming a solder layer over the metal pillar.
11/20/14
20140342544
Method for manufacturing semiconductor device
A semiconductor wafer is subjected to a protection film formation step process as a process before evaluation of electrical characteristics. In this process, after an insulating film serving as a protection film is formed, a photolithography process and an etching process are performed so as to form a protection film having a plurality of openings exposing an emitter electrode.
11/20/14
20140342543
Method and apparatus for single step selective nitridation
Methods and apparatus for selective one-step nitridation of semiconductor substrates is provided. Nitrogen is selectively incorporated in silicon regions of a semiconductor substrate having silicon regions and silicon oxide regions by use of a selective nitridation process.
11/20/14
20140342540
Semiconductor device and method of manufacturing the same
A semiconductor device having a buried gate is provided. The semiconductor device is formed in a structure in which a plurality of contacts having small step differences are stacked without forming a metal contact applying an operation voltage to the buried gate in a single contact and a contact pad is formed between the contacts so that failure due to misalignment can be prevented without a separate additional process for forming the contacts..
11/20/14
20140342539
Semiconductor device having mixedly mounted components with common film layers and method of manufacturing the same
A metal gate electrode and a poly-silicon resistance element are mixedly mounted in the same semiconductor substrate. The metal gate electrode is formed on a first gate insulating film and includes a first gate metal film and a first gate silicon film.
11/20/14
20140342537
Mechanisms for forming ultra shallow junction
A method of making a semiconductor device includes forming a fin structure over a substrate. The method further includes performing a plasma doping process on the fin structure.
11/20/14
20140342535
Method for manufacturing semiconductor substrate
A semiconductor substrate preventing a void from being generated in an epitaxial film buried in a trench. An n-type first epitaxial film and first trenches are formed on an n+-type substrate body.
11/20/14
20140342533
Method of strain and defect control in thin semiconductor films
A method of managing strain and preventing defect formation in semiconductor materials is described. In structures featuring two or more semiconductor materials with different lattice constants, buffer layers may be used to form deposition surfaces that result in defect-free semiconductor devices.
11/20/14
20140342531
Adhesive sheet for semiconductor wafer processing, method for processing of semiconductor wafer using sheet
To provide an adhesive sheet for wafer processing that satisfies characteristics such as: (1) protecting an uneven circuit surface during grinding with an adhesive force that is not excessively weak; (2) being easy to remove after processing; and (3) leaving very little adhesive residue on the wafer, and that can preferably be used as a removable bg sheet or the like. This adhesive sheet for wafer processing is characterized in having a substrate and an adhesive layer formed on the substrate, the adhesive layer having an adhesive polymer (a) and a polyrotaxane (b) having a linear-chain molecule passing through the opening of the at least two cyclic molecules, and having a block group at both ends of the linear-chain molecule, the adhesive polymer (a) and the cyclic molecule of the polyrotaxane (b) being linked together to form a crosslinked structure..
11/20/14
20140342529
Semiconductor-on-insulator integrated circuit with back side gate
Methods for manufacturing semiconductor-on-insulator (soi) integrated circuits are disclosed. An soi wafer is provided having a first surface and a second surface.
11/20/14
20140342527
Integrated circuits separated by through-wafer trench isolation
An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material.. .
11/20/14
20140342526
Method for manufacturing semiconductor substrate
A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an n−-type layer formed on an n+-type substrate.
11/20/14
20140342525
Method for manufacturing semiconductor substrate
A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an n−-type layer formed on an n+-type substrate.
11/20/14
20140342524
Integrated circuit comprising an isolating trench and corresponding method
An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.. .
11/20/14
20140342522
Reducing variation by using combination epitaxy growth
A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (e/g) ratio of process gases used in the first growth stage; and performing a second growth stage with a second e/g ratio of process gases used in the second growth stage different from the first e/g ratio..
11/20/14
20140342521
Transistor performance using a two-step damage anneal
A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device.
11/20/14
20140342520
Vertical power mosfet and methods for forming the same
A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode.
11/20/14
20140342518
Power mosfet structure and method
A power mosfet includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness.
11/20/14
20140342517
Method for fabricating trench type power semiconductor device
A method of forming a trench type semiconductor power device is disclosed. An epitaxial layer is formed on a substrate.
11/20/14
20140342513
Semiconductor apparatus and method for manufacturing the semiconductor apparatus
A semiconductor apparatus includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a gate recess formed by removing at least a portion of the second semiconductor layer, an insulation film formed on the gate recess and the second semiconductor layer, a gate electrode formed on the gate recess via the insulation film, source and drain electrodes formed on one of the first and the second semiconductor layers, and a fluorine containing region formed in at least one of a part of the first semiconductor layer corresponding to a region in which the gate recess is formed and a part of the second semiconductor layer corresponding to the region in which the gate recess is formed.. .
11/20/14
20140342512
High voltage iii-nitride semiconductor devices
A iii-n device is described has a buffer layer, a first iii-n material layer on the buffer layer, a second iii-n material layer on the first iii-n material layer on an opposite side from the buffer layer and a dispersion blocking layer between the buffer layer and the channel layer. The first iii-n material layer is a channel layer and a compositional difference between the first iii-n material layer and the second iii-n material layer induces a 2deg channel in the first iii-n material layer.
11/20/14
20140342511
Semiconductor structure and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region.
11/20/14
20140342509
Module and assembly with dual dc-links for three-level npc applications
A power semiconductor module has four power terminals. An igbt has a collector connected to the first power terminal and an emitter coupled to the third power terminal.
11/20/14
20140342508
Hybrid substrates, semiconductor packages including the same and methods for fabricating semiconductor packages
Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer.
11/20/14
20140342507
Fabrication method of semiconductor package
A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost..
11/20/14
20140342506
Method for fabricating semiconductor package
Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place..
11/20/14
20140342505
Fabrication method of semiconductor package
A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an rdl structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant.. .
11/20/14
20140342501
Package stacks and methods of manufacturing the same
A package stack includes a first package, a second package, first solder balls and a molding member. The first package includes a first package substrate, a first semiconductor chip on the first package substrate and connecting pads.
11/20/14
20140342500
Method and system for template assisted wafer bonding
A method of fabricating a composite semiconductor structure includes providing a substrate including a plurality of devices and providing a compound semiconductor substrate including a plurality of photonic devices. The method also includes dicing the compound semiconductor substrate to provide a plurality of photonic dies.
11/20/14
20140342499
Semiconductor device and manufacturing method thereof
The contact resistance between an oxide semiconductor film and a metal film is reduced. A transistor that uses an oxide semiconductor film and has excellent on-state characteristics is provided.
11/20/14
20140342498
Semiconductor device and method for manufacturing the same
A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween.
11/20/14
20140342496
Preparation of cigs absorber layers using coated semiconductor nanoparticle and nanowire networks
We disclose a method of preparing cigs absorber layers using coated semiconductor nanoparticle and nanowire networks. The nanoparticles and nanowires containing one or more elements from group ib and/or iiia and/or via are prepared from metal salts such as metal chloride and acetate at room temperature without inert gas protection.
11/20/14
20140342495
Preparation of cigs absorber layers using coated semiconductor nanoparticle and nanowire networks
We disclose a method of preparing cigs absorber layers using coated semiconductor nanoparticle and nanowire networks. The nanoparticles and nanowires containing one or more elements from group ib and/or iiia and/or via are prepared from metal salts such as metal chloride and acetate at room temperature without inert gas protection.
11/20/14
20140342494
Ohmic n-contact formed at low temperature in inverted metamorphic multijunction solar cells
A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact composed of a sequence of layers over the first subcell at a temperature of 280° c. Or less and having a contact resistance of less than 5×10−4 ohms-cm2..
11/20/14
20140342493
Radiation detector having a bandgap engineered absorber
A radiation detector is provided that includes a photodiode having a radiation absorber with a graded multilayer structure. Each layer of the absorber is formed from a semiconductor material, such as hgcdte.
11/20/14
20140342491
Method for manufacturing waveguide-type semiconductor device
A method for manufacturing a waveguide-type semiconductor device includes the steps of forming an epitaxial structure including a waveguide mesa and a device mesa; forming a mask for selective growth on the epitaxial structure; growing a semiconductor region on an end surface of the device mesa by using the mask for selective growth, the semiconductor region including a side portion having a layer shape and a protruding wall portion; forming an ohmic electrode on a top surface of the device mesa; forming a resin layer on the device mesa and the semiconductor region; forming a resin mask having an opening on the ohmic electrode; forming an electric conductor connecting the ohmic electrode to an electrode pad, the electric conductor passing over the protruding wall portion while making contact with a surface of the resin mask; and removing the resin mask after forming the electric conductor.. .
11/20/14
20140342486
Elemental semiconductor material contact for gan-based light emitting diodes
A vertical stack including a p-doped gan portion, a multi-quantum-well, and an n-doped gan portion is formed on an insulator substrate. The p-doped gan portion may be formed above, or below, the multi-quantum-well.
11/20/14
20140342485
Elemental semiconductor material contact for high indium content ingan light emitting diodes
A vertical stack including a p-doped gan portion, a multi-quantum-well including indium gallium nitride layers, and an n-doped transparent conductive material portion is formed on an insulator substrate. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a surface of the p-doped gan portion.
11/20/14
20140342484
Method for producing an optoelectronic semiconductor chip and corresponding optoelectronic semiconductor chip
A method of producing a semiconductor chip includes providing a silicon growth substrate, producing a iii nitride buffer layer on the growth substrate by sputtering, and growing a iii nitride semiconductor layer sequence having an active layer above the buffer layer.. .
11/20/14
20140342479
Method and system for template assisted wafer bonding using pedestals
A method of fabricating a composite semiconductor structure includes providing a first substrate comprising a first material and having a first surface and forming a plurality of pedestals extending to a predetermined height in a direction normal to the first surface. The method also includes attaching a plurality of elements comprising a second material to each of the plurality of pedestals, providing a second substrate having one or more structures disposed thereon, and aligning the first substrate and the second substrate.
11/20/14
20140342477
Method of monitoring semiconductor fabrication process using xps
A method of monitoring a semiconductor fabrication process including forming a barrier pattern on a substrate, forming a sacrificial pattern on the barrier pattern, removing the sacrificial pattern to expose a surface of the barrier pattern, generating photoelectrons by irradiating x-rays to a surface of the substrate, and inferring at least one material existing on the surface of the substrate by collecting and analyzing the photoelectrons may be provided.. .
11/20/14
20140342476
Land grid array semiconductor device packages
A semiconductor device package includes a land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads on the same side of the interposer substrate as the at least one semiconductor die.
11/20/14
20140342475
Semiconductor test method and semiconductor test apparatus
A semiconductor test method includes attaching a sheet to a wafer on which a plurality of chips are formed, the sheet having a plurality of holes, each of which corresponds to a position of one of the chips, dicing the wafer to separate the plurality of chips into individual chips while the sheet remains attached to the individual chips, and after the dicing and while the sheet remains attached to the individual chips, measuring the electrical characteristics of the chips.. .
11/20/14
20140342474
Temperature detecting apparatus, substrate processing apparatus and method of manufacturing semiconductor device
A temperature detecting apparatus is provided which is capable of suppressing disconnection of a thermocouple wire or positional deviation of a thermocouple junction portion caused by change over time. The temperature detecting apparatus includes: an insulation rod installed to extend in a vertical direction and including a through-hole in vertical direction; a thermocouple wire inserted in the through-hole of the insulation rod, the thermocouple wire including a thermocouple junction portion at an upper end thereof and an angled portion at a lower end of the insulation rod; and a buffer area installed below the insulation rod and configured to suppress a restriction of a horizontal portion of the angled portion upon heat expansion, wherein an upper portion of the thermocouple wire or a middle portion in the vertical direction are supported by the insulation rod..
11/20/14
20140342473
Semiconductor processing method
A method for detecting metal contamination from a film-forming process causing interface traps is described. The film-forming process is performed to form a dielectric film on a wafer.
11/20/14
20140342254
Photo-catalytic systems for production of hydrogen
A system for splitting water and producing hydrogen for later use as an energy source may include the use of a photoactive material including pccn and plasmonic nanoparticles. A method for producing the pccn may include a semiconductor nanocrystal synthesis and an exchange of organic capping agents with inorganic capping agents.
11/20/14
20140342203
Apparatus for measuring a pressure, a method for manufacturing an apparatus for measuring a pressure and a battery
An apparatus for measuring a pressure includes a semiconductor die and a circuit board. The semiconductor die includes a micro-mechanical element generating a measurement signal indicating information on an external pressure applied to the micro-mechanical element.


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Semiconductor topics: Semiconductor, Semiconductor Substrate, Semiconductor Device, Semiconductor Material, Electric Conversion, Conductive Layer, Molybdenum, Camera Module, Semiconductor Devices, Semiconductors, Integrated Circuit, Surfactant, Photoelectric Conversion, Electronic Device, Transparent Conductive Oxide

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