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Semiconductor patents

      

This page is updated frequently with new Semiconductor-related patent applications.




new patent Semiconductor power converter
A semiconductor power converter includes a main circuit board installed in a housing of the semiconductor power converter. On the main circuit board, a main circuit converting power supplied from a power source to supply converted power to a load, and a first temperature sensor are disposed.
Mitsubishi Electric Corporation


new patent Structure containing conductor circuit, manufacturing same, and heat-curable resin composition
A method for manufacturing a structure containing a conductor circuit according to the present invention can provide openings in various shapes by patterning a first photosensitive resin layer in a first patterning process according to shapes of openings formed in a heat-curable resin layer. Further, in the method for manufacturing a structure containing a conductor circuit, a plurality of openings can be formed at the same time and a residue of the resin around the opening can be reduced, unlike a case in which openings are formed with a laser.
Hitachi Chemical Company, Ltd.


new patent Semiconductor substrate, semiconductor module and manufacturing the same
The present disclosure relates to a semiconductor substrate, a semiconductor module and a method for manufacturing the same. The semiconductor substrate includes a first dielectric structure, a second dielectric structure, a first patterned conductive layer and a second patterned conductive layer.
Advanced Semiconductor Engineering, Inc.


new patent Method, apparatus and system for providing multiple euv beams for semiconductor processing
At least one method, apparatus and system for providing a plurality of optical beams, such as euv beams. A first electron beam is received.
Globalfoundries Inc.


new patent Semiconductor device, lighting device, and vehicle
A novel semiconductor device is provided. The semiconductor device includes a first resistor and a second resistor.
Semiconductor Energy Laboratory Co., Ltd.


new patent Modular integrated lighting circuit
A light emitting diode (led) circuit board includes a power input configured to supply power, a driving circuit configured to convert power, and a light emitting circuit configured to generate light. The power input is configured to supply power to the driving circuit.
Cooper Technologies Company


new patent Protection of a telephone line against overvoltages
A structure protects a slic telephone line interface against overvoltages lower than a negative threshold or higher than a positive threshold. The structure includes at least one thyristor connected between each conductor of the telephone line and a reference potential.
Stmicroelectronics (tours) Sas


new patent Semiconductor device and system
An sci can perform transmission only or reception only, however, it is necessary to reset the sci when transmission and reception is switched to transmission only or to reception only. A semiconductor device includes an interface circuit which performs a sequential communication of transmit or receive according to a synchronous clock.
Renesas Electronics Corporation


new patent Method for driving semiconductor device
A novel pll is provided. An oscillator circuit includes first to n-th inverters, and first and second circuits.
Semiconductor Energy Laboratory Co., Ltd.


new patent Semiconductor device and controlling the semiconductor device
A semiconductor device includes: a clock synchronizing circuit that operates in synchronization with a clock; an enable signal generating circuit that generates an enable signal in an operation period during which the clock synchronizing circuit is operated; and a clock supplying circuit that supplies a clock to the clock synchronizing circuit or stop the supply of the clock according to the enable signal when a clock frequency is equal to or lower than a predetermined frequency, and supply a clock to the clock synchronizing circuit, irrespective of the enable signal, when the clock frequency is higher than the predetermined frequency.. .
Fujitsu Limited


new patent

Semiconductor apparatus

A semiconductor apparatus may include a transmission circuit, a reception circuit, and a pad commonly coupled to the transmission circuit and the reception circuit. When either the transmission circuit or the reception circuit is activated, parasitic capacitance of a line coupled to the transmission circuit, the reception circuit, and the pad is varied..
Sk Hynix Inc.

new patent

Driving device of gate driver

Disclosed embodiments relate to a driving device of a gate driver driving a semiconductor switching element, which may include a gate driver unit for outputting a control signal to the semiconductor switching element, and a control unit for controlling an operation of the semiconductor switching element by operating at least one gate driver configuring the gate driver unit, wherein the control unit operates at least one gate driver based on a preset operation range of the semiconductor switching element and a detected operation status thereof.. .
Lsis Co., Ltd.

new patent

Semiconductor switching device

Provided is a semiconductor switching device such that there is a reduction in surge or loss in multiple kinds of semiconductor switching element provided in parallel and of differing turn-on/turn-off operation characteristics. The semiconductor switching device includes a switching circuit unit that includes in parallel multiple kinds of semiconductor switching element having different turn-on/turn-off operation characteristics and turns a main current on and off, a driver circuit that includes a current source terminal and a current sink terminal and outputs drive signals that collectively turn the semiconductor switching elements on and off from the current source terminal and the current sink terminal, and an impedance element that is interposed between the current source terminal and the current sink terminal in the driver circuit and causes timings of operations by which the semiconductor switching elements are turned on and off to differ from each other..
Fuji Electric Co., Ltd.

new patent

System and a switching transistor

In accordance with an embodiment, a method of operating a semiconductor switch coupled to an inductor includes turning on the semiconductor switch by applying a turn-on voltage to between a gate of the semiconductor switch and a low current terminal connected to a reference node of the semiconductor switch, the low current terminal separate from a high current reference terminal connected to the reference node of the semiconductor switch, and the semiconductor switch comprises a first input capacitance to transconductance ratio. The method further includes turning off the semiconductor switch by applying a turn-off voltage to the gate of the semiconductor switch, wherein a ratio of a total capacitance at an output node of the semiconductor switch to a gate-drain capacitance is greater than a first ratio per watt of power being handled by a load coupled to the semiconductor switch..
Infineon Technologies Austria Ag

new patent

Semiconductor device and electric power control apparatus

A driver ic includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense mos that is arranged between a floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area.
Renesas Electronics Corporation

new patent

Semiconductor device

A signal indicating temperature of an igbt chip, after input into an overheat detection terminal, is simultaneously input into a first comparator for protection operation and a second comparator for precaution. At a normal time when the chip temperature is low, a first transistor connected to an alarm signal output terminal via a resistor and a second transistor connected to the alarm signal output terminal via a zener diode are turned off, and the alarm signal output terminal whose voltage is pulled up by an external pull-up circuit is set to high level voltage.
Fuji Electric Co., Ltd.

new patent

Signal generator adjusting a duty cycle and semiconductor apparatus using the same

A semiconductor apparatus may include a signal generator, and may operate by receiving two or more external power voltages. The signal generator may include a duty cycle circuit.
Sk Hynix Inc.

new patent

Semiconductor device, battery monitoring device, and voltage detection battery cell

The present disclosure provides a semiconductor device including: plural first switches, each provided so as to correspond to one of plural battery cells connected in series, each first switch including one end connected to a corresponding battery cell and another end connected to one electrode of a corresponding charge storage section of plural charge storage sections, each of the charge storage sections being provided so as to correspond to one of the plural battery cells, and another electrode of each charge storage section being connected to a fixed potential; plural second switches, each provided so as to correspond to one of the plural first switches, each second switch including one end connected to the other end of the corresponding first switch; and processing section connected to each other end of the plural second switches, that processes voltages supplied via the second switches.. .
Lapis Semiconductor Co., Ltd.

new patent

Power supply system

A power supply system includes first and second dc power supplies and a power converter. The power converter includes first and third semiconductor elements electrically connected between respective nodes of a first node and a second node and a power line, second and fourth semiconductor elements electrically connected between respective nodes of the first node and the second node and a second power line, a fifth semiconductor element electrically connected between the first and second nodes, and first and second reactors.
Toyota Jidosha Kabushiki Kaisha

new patent

Monolithic nanophotonic device on a semiconductor substrate

A photonic light generating device is provided on a portion of a first semiconductor material. The photonic light generating device includes a second semiconductor material that has a different lattice constant than the lattice constant of the first semiconductor material and that is capable of generating and emitting light.
International Business Machines Corporation

new patent

Monolithically integrated laser with led pump

A laser structure includes a substrate, a buffer layer formed on the substrate and a light emitting diode (led) formed on the buffer layer. A photonic crystal layer is formed on the led.
International Business Machines Corporation

new patent

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a conductor layer including a first terminal, and a first insulating layer including a first opening. The first opening includes a first edge and a second edge, a distance between the second edge and the first terminal being larger than a distance between the first edge and the first terminal..
Kabushiki Kaisha Toshiba

new patent

Insulating busbar and manufacturing method

To realize an insulating busbar that has both low inductance and high withstand voltage, provided is an insulating busbar that connects to a module on which is mounted a semiconductor chip, including a plurality of circuit conductors; a plurality of connection terminals that respectively electrically connect the circuit conductors to the module; and an insulating resin portion that is formed integrally between each of the circuit conductors and at least a portion of a region around each connection terminal and does not have any gaps between the circuit semiconductors.. .
Fuji Electric Co., Ltd.

new patent

Method of manufacturing a battery, battery and integrated circuit

A method of manufacturing a battery includes defining an active region and a bonding area in a first main surface of a first semiconductor substrate, forming a first ditch in the bonding area, forming an anode at the first semiconductor substrate in the active region, and forming a cathode at a carrier comprising an insulating material. The method further includes stacking the first semiconductor substrate and the carrier so that the first main surface of the first semiconductor substrate is disposed on a side adjacent to a first main surface of the carrier, a cavity being formed between the first semiconductor substrate and the carrier, and forming an electrolyte in the cavity..
Infineon Technologies Ag

new patent

Electronic device and manufacturing method thereof

A electronic device includes: a control electrode 11 formed on a base substrate 10; an insulation layer 21 adapted to cover the control electrode 11 and formed of an organic insulation material; an active layer 12 formed on the insulation layer 21, formed of an organic semiconductor material, and subjected to patterning; and a first electrode 13a and a second electrode 13b formed on the active layer 12, in which a chemical composition of a surface of a region a (21a) that is a region of the insulation layer 21 not formed with the active layer 12 differs from a chemical composition of a region b (21b) that is a region of the insulation layer 21 located under the active layer 12.. .
Sony Corporation

new patent

Organic transistor, compound, organic semiconductor material for non-light-emitting organic semiconductor device, material for organic transistor, coating solution for non-light-emitting organic semiconductor device, manufacturing organic transistor, manufacturing organic semiconductor film, organic semiconductor film for non-light-emitting organic semiconductor device, and synthesizing organic semiconductor material

(x represents an oxygen, sulfur, selenium, or tellurium atom or nr5; y and z each represents cr6, an oxygen, sulfur, selenium, or nitrogen atom, or nr7; a ring containing y and z is an aromatic heterocycle; any one of r1 and r2 and the aromatic heterocycle containing y and z or any one of r3 and r4 and a benzene ring may be bonded to each other through a specific divalent linking group; r1, r2, and r5 to r8 each represent a hydrogen atom, an alkyl group, an alkenyl group, an alkynyl group, an aryl group, or a heteroaryl group; r3 and r4 each represent an alkyl group, an alkenyl group, an alkynyl group, an aryl group, or heteroaryl group; and each of m and n is an integer of 0 to 2.). .

new patent

New cyclazines and their use as semiconductors

Wherein, if present, x3, x4 are o or c(cn)2 and m, r4a, r4b, r5a, r5b, r6a, r6b, r6c, r6d, r7a, r7a, r8a, r8b, r9, r10a, r10b, rm1, rm2, rm3 and rm4 are as defined in the claims and description. The present invention also relates to a method for their preparation and their use as semiconductors, in particular as semiconductors in organic electronics and organic photovoltaics..

new patent

Method for growing carbon nanotubes

A method of forming carbon nanotubes (cnts) is disclosed. The method includes dispersing a plurality of substantially semiconductor pure carbon nanotube (cnt) seeds on a substrate to provide a seeded substrate, ozonating the seeded substrate to remove defects on end faces of the plurality of substantially semiconductor pure cnt seeds, and growing carbon extensions on the end faces of the plurality of substantially semiconductor pure cnts seeds to form a plurality of substantially pure cnts..
Northrop Grumman Systems Corporation

new patent

Method for producing an optoelectronic device

A method for manufacturing an opto-electronic component (100) is given, comprising a provision of a carrier (1) with at least one mounting surface (11), a generation of at least two vias (4) in the carrier (1) with electrically conducting contacts (12, 13) running through the vias (4), a provision of at least one light-emitting semiconductor chip (2), wherein the semiconductor chip (2) comprises a growth substrate (10) and a layer sequence (7) epitaxially grown thereon, a mounting of the at least one semiconductor chip (2) onto the at least one mounting surface (11) of the carrier (1), wherein the semiconductor chip (2) is connected in an electrically conducting manner to the contacts (12, 13) in the same method step during the mounting onto the mounting surface (11), an isolation of the carrier (1) along isolation lines (v), wherein an isolation line (v) runs through at least one of the vias (4), so that, after the isolation, the contacts (12, 13) form contact surfaces (5) at at least one side surface (1a) of the carrier (1), wherein the side surface (1a) is perpendicular to the mounting surface (11) of the carrier (1), and a mounting of the carrier (1) with the contact surfaces (5) on a connection plate (8), wherein the mounting surface (11) is perpendicular to the connection plate (8).. .
Osram Opto Semiconductors Gmbh

new patent

Light emitting element and light emitting device

Provided are a light emitting element and a light emitting device with improved light emission intensity distribution. A light emitting element includes a light-transmissive substrate, an n-type semiconductor layer, a first p-type semiconductor layer, a first p-side electrode, a first n-side electrode, a second p-type semiconductor layer, a second p-side electrode, and a second n-side electrode.
Nichia Corporation

new patent

Heat-curable epoxy resin composition for optical semiconductor element encapsulation and optical semiconductor device using same

(b) a curing accelerator.. .

new patent

Method of manufacturing light-emitting diode

A method of manufacturing a light-emitting diode (led) includes preparing a substrate, forming a plurality of semiconductor light-emitting units on the substrate, each of the plurality of semiconductor light-emitting units protruding from the substrate and including a first conductive semiconductor layer, and an active layer and a second conductive semiconductor layer, the active layer and the second conductive semiconductor layer sequentially covering the first conductive semiconductor layer, dipping the semiconductor light-emitting units into an aqueous solution containing metal salt and an alkaline ligand compound, and forming an electrode layer on the plurality of semiconductor light-emitting units, wherein the forming the electrode layer includes maintaining a temperature of the aqueous solution between about 40° c. And about 200° c..
Samsung Electronics Co., Ltd.

new patent

Light-emitting element

A light-emitting element comprises a substrate; a light-emitting semiconductor stack on the substrate, the light-emitting semiconductor stack comprising a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer; a first electrode on the first semiconductor layer; a reflective layer formed on the light-emitting semiconductor stack; a protection layer formed on the light-emitting semiconductor stack; and a conductive contact layer formed on the light-emitting semiconductor stack, wherein each layer above the substrate comprises a side surface inclined to a top surface of the substrate.. .
Epistar Corporation

new patent

Porous-silicon light-emitting device and manufacturing method thereof

A light-emitting device may include a semiconductor body having a first conductivity type, with a front side and a back side. The light-emitting device may also include a porous-silicon region which extends in the semiconductor body at the front side, and a cathode region in direct lateral contact with the porous-silicon region.
Stmicroelectronics S.r.l.

new patent

Vertical topology light emitting device

A light emitting device includes a metal support structure comprising cu; an adhesion structure on the metal support structure and comprising au; a reflective conductive contact on the adhesion structure; a gan-based semiconductor structure on the reflective conductive contact, the gan-based semiconductor structure comprising a first-type gan layer, an active layer, and a second-type gan layer; a top interface layer on the gan-based semiconductor structure and comprising ti; and a contact pad on the top interface layer and comprising au, wherein the gan-based semiconductor structure is less than 1/20 thick of a thickness of the metal support structure.. .
Lg Innotek Co., Ltd.

new patent

P-type contact to semiconductor heterostructure

A contact to a semiconductor heterostructure is described. In one embodiment, there is an n-type semiconductor contact layer.
Sensor Electronic Technology, Inc.

new patent

Light emitting diode and data transmission and reception apparatus

A light emitting diode, including a semiconductor epitaxial structure, a first electrode and a second electrode is provided. The semiconductor epitaxial structure includes a plurality stacked light-emitting layers, and each of the light-emitting layers respectively emits different range of wavelength of light.
Southern Taiwan University Of Science And Technology

new patent

Method for manufacturing a photovoltaic cell with selective doping

A method for creating a photovoltaic cell, includes forming a first doped region in a semiconductor substrate having a first concentration of doping elements; forming, by ion implantation, alignment units, the largest size of which is smaller than one millimeter, and a second doped region, adjacent to the first region with a second concentration of doping elements; heat-treating the substrate to activate the doping elements and to form an oxide layer at the surface of the substrate, the second concentration and the heat treatment conditions being selected such that the oxide layer has a thickness above the alignment units that is larger, by at least 10 nm, than the thickness of the oxide layer above an area of the substrate adjacent to the alignment units; depositing an antireflection layer onto the oxide layer; and depositing an electrode onto the antireflection coating, through a screen, opposite the second region.. .
Commissariat A L'energie Atomique Et Aux Energies Alternatives

new patent

Method for producing solar cells having simultaneously etched-back doped regions

A method for producing a solar cell is described, in which a plurality of doped regions are to be etched-back selectively or over their entire surface. Once a semiconductor substrate (1) has been provided, various doped regions (3, 5) are formed in partial regions of a surface of the semiconductor substrate, the various doped regions (3, 5) differing as regards their doping concentration and/or their doping polarity.
UniversitÄt Konstanz

new patent

Semiconductor device for a system for measuring the temperature, and manufacturing method thereof

A semiconductor device for a system for measuring temperature, which includes a first uv detector and a second uv detector. The first and second uv detectors generate a first current and a second current, respectively, as a function of the irradiance in the ultraviolet band.
Stmicroelectronics S.r.l.

new patent

Solar cell and solar cell module

A solar cell and a solar cell module are disclosed. The solar cell includes a semiconductor substrate, an emitter region extending in a first direction, a back surface field region extending in the first direction in parallel with the emitter region, a first electrode connected to the emitter region and extending in the first direction, and a second electrode connected to the back surface field region and extending in the first direction.
Lg Electronics Inc.

new patent

Thick damage buffer for foil-based metallization of solar cells

Approaches for the foil-based metallization of solar cells and the resulting solar cells are described. A method involves patterning a first surface of a metal foil to provide a plurality of alternating grooves and ridges in the metal foil.

new patent

Formation of homojunction in kesterite-based semiconductors

Kesterite-based homojunction photovoltaic devices are provided. The photovoltaic devices include a p-type semiconductor layer including a copper-zinc-tin containing chalcogenide compound and an n-type semiconductor layer including a silver-zinc-tin containing chalcogenide compound having a crystalline structure the same as a crystalline structure the copper-zinc-tin containing chalcogenide compound..
International Business Machines Corporation

new patent

Photoactive semiconductor component and producing a photoactive semiconductor component

The invention relates to a photoactive semiconductor component, especially a photovoltaic solar cell, having a semiconductor substrate, a carbon-containing sic layer disposed indirectly upon a surface of the semiconductor substrate, and a passivating intermediate layer disposed indirectly or directly between the sic layer and semiconductor substrate, and a metallic contact connection disposed indirectly or directly upon a side of the sic layer facing away from the passivating intermediate layer and in electrically conductive connection with the sic layer, where the sic layer has p-type or n-type doping, which is characterized in that the sic layer partly has a partly amorphous structure and partly has a crystalline structure.. .
Fraunhofer-gesellschaft Zur Forderung Der Angewandten Forschung E.v.

new patent

Semiconductor device

For enhancing a reverse-recovery immunity of a diode element, a semiconductor device includes a first conductivity-type drift layer, a second conductivity-type anode region provided in an upper portion of the drift layer, an insulating film provided on the drift layer, an anode electrode having an ohmic contact portion ohmically contacted to the anode region through a contact hole penetrating the insulating film, and a schottky electrode schottky-contacted to a peripheral portion of the anode region.. .
Fuji Electric Co., Ltd.

new patent

Field effect transistor

An insulating film is provided over one surface of a first semiconductor layer including a first oxide semiconductor including indium as a main component, and a second semiconductor layer including an i-type second oxide semiconductor is provided in contact with the other surface. The energy difference between a vacuum level and a fermi level in the second oxide semiconductor is larger than that in the first oxide semiconductor.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor device

A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Thin-film transistor and manufacturing method thereof

A thin-film transistor and a manufacturing method thereof are characterized in that: the active layer is a group iv-vi compound semiconductor film; the group iv-vi compound is one of geranium sulfide (ges), germanium selenide (gese), germanium telluride (gete), tin selenide (snse), and tin telluride (snte) or a ternary, quaternary, or quinary compound thereof; the active layer is deposited by sputtering; and thermal annealing is performed after the active layer is deposited. The thin-film transistor has high carrier mobility and a high current on/off ratio and therefore meets the needs of high-resolution display development..
National Sun Yat-sen University

new patent

Tft substrate structure and manufacturing method thereof

The present invention provides a tft substrate structure and a manufacturing method thereof. A metal oxide semiconductor layer is formed on an amorphous silicon layer to replace an n-type heavily-doped layer.
Shenzhen China Star Optoelectronics Technology Co. Ltd.

new patent

Field-effect transistor, display element, image display device, and system

A field-effect transistor including: a substrate; a passivation layer; a gate insulating layer formed between the substrate and the passivation layer; a source electrode and a drain electrode, which are formed to be in contact with the gate insulating layer; a semiconductor layer, which is formed at least between the source electrode and the drain electrode and is in contact with the gate insulating layer, the source electrode, and the drain electrode; and a gate electrode, which is in contact with the gate insulating layer and faces the semiconductor layer via the gate insulating layer, wherein the passivation layer contains a first complex oxide containing an alkaline earth metal and a rare-earth element, and wherein the gate insulating layer contains a second complex oxide containing an alkaline earth metal and a rare-earth element.. .
Ricoh Company, Ltd.

new patent

Method for fabricating a flash memory

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a dielectric stack is formed on the substrate, in which the dielectric stack includes a first silicon oxide layer and a first silicon nitride layer.
United Microelectronics Corp.

new patent

Semiconductor device and manufacturing the same

The electrical characteristics of a transistor including an oxide semiconductor layer are varied by influence of an insulating film in contact with the oxide semiconductor layer, that is, by an interface state between the oxide semiconductor layer and the insulating film. A first oxide semiconductor layer s1, a second oxide semiconductor layer s2, and a third oxide semiconductor layer s3 are sequentially stacked, so that the oxide semiconductor layer through which carriers flow is separated from the gate insulating film containing silicon.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor device, manufacturing the same, and electronic device

A semiconductor device with reduced parasitic capacitance is provided. A stack is formed on an insulating layer, the stack comprising a first oxide insulating layer, an oxide semiconductor layer over the first oxide insulating layer, and a second oxide insulating layer on the oxide semiconductor layer; a gate electrode layer and a gate insulating layer are formed on the second oxide insulating layer; a first low-resistance region is formed by adding a first ion to the second oxide semiconductor layer using the gate electrode layer as a mask; a sidewall insulating layer is formed on an outer side of the gate electrode layer; a second conductive layer is formed over the gate electrode layer, the sidewall insulating layer, and the second insulating layer; and an alloyed region in the second oxide semiconductor layer is formed by performing heat treatment..
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor device and manufacturing same

A semiconductor device includes a thin film transistor (100), the thin film transistor (100) including: a substrate (1); a gate electrode (3) provided on the substrate (1); a gate dielectric layer (5) formed on the gate electrode (3); an island-shaped oxide semiconductor layer (7) formed on the gate dielectric layer (5); a protective layer (9) provided so as to cover an upper face (7u) and an entire side face (7e) of the oxide semiconductor layer (7), the protective layer (9) having a single opening (9p) through which the upper face (7u) of the oxide semiconductor layer (7) is only partially exposed; and a source electrode (11) and a drain electrode (13) which are in contact with the oxide semiconductor layer (7) within the single opening (9p).. .
Sharp Kabushiki Kaisha

new patent

Methods of fabricating semiconductor devices

Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer.
Samsung Electronics Co., Ltd.

new patent

Semiconductor device and fabricating the same

A semiconductor device is provided. A fin is disposed on a substrate.

new patent

Semiconductor device and manufacturing the semiconductor device

A semiconductor device provided herein includes: a fourth region of a p-type being in contact with a lower end of the gate trench; a termination trench provided in the front surface in a range outside the second region; a lower end p-type region of the p-type being in contact with a lower end of the termination trench; a lateral p-type region of the p-type being in contact with a lateral surface of the termination trench on an outer circumferential side, connected to the lower end p-type region, and exposed on the front surface; and a plurality of guard ring regions provided on the outer circumferential side with respect to the lateral p-type region and exposed on the front surface.. .
Denso Corporation

new patent

Semiconductor device

A semiconductor device includes a first conductivity type region provided to at least one of a second conductivity type column region and a second conductivity type layer located on the second conductivity type column region. The first conductivity type region has a non-depletion layer region when a voltage between a first electrode and a second electrode is 0v.
Denso Corporation

new patent

Semiconductor device with multiple carrier channels

A semiconductor device includes a layered structure forming multiple carrier channels including at least one n-type channel formed in a first layer made of a first material and at least one p-type channel formed in a second layer made of a second material and a set of electrodes for providing and controlling carrier charge in the carrier channels. The first material is different than the second material, and the first and the second materials are selected such that the n-type channel and the p-type channel have comparable switching frequency and current capability..
Mitsubishi Electric Research Laboratories, Inc.

new patent

Semiconductor device with multiple-functional barrier layer

A semiconductor device includes a semiconductor structure forming a carrier channel, a barrier layer arranged in proximity with the semiconductor structure, and a set of electrodes for providing and controlling carrier charge in the carrier channel. The barrier layer is at least partially doped by impurities having a conductivity type opposite to a conductivity type of the carrier channel.
Mitsubishi Electric Research Laboratories, Inc.

new patent

Semiconductor device and manufacturing the same

A semiconductor device includes: a drift layer of a first conductivity type, implementing a main semiconductor layer; a base region of a second conductivity type provided on an top surface side of the drift layer; a first main electrode region of the first conductivity type provided in an upper part of the base region, having an impurity concentration higher than the main semiconductor layer; a gate electrode buried in a trench penetrating the first main electrode region and the base region through a gate insulating film; a gate screening semiconductor layer of the second conductivity type, being buried under a bottom of the trench; an intermediate semiconductor layer of the first conductivity type sandwiched between the base region and the gate screening semiconductor layer; and a second main electrode region of the second conductivity type provided on a bottom surface side of the drift layer.. .
Fuji Electric Co., Ltd.

new patent

Semiconductor device

A semiconductor device is provided comprising a semiconductor substrate of a first conductivity type and a dummy trench portion having a main body portion and one or more branch portions, the main body portion formed in a front surface of the semiconductor substrate and extending in a predetermined extending direction, the branch portions extending from the main body portion in directions different from the extending direction. The semiconductor substrate has an emitter region of first conductivity type and a base region of a second conductivity type which are provided sequentially from the front surface side of the semiconductor substrate, and the dummy trench portion has a dummy trench which penetrates the emitter region and the base region from the front surface of the semiconductor substrate, and a dummy insulating portion which is provided within the dummy trench..
Fuji Electric Co., Ltd.

new patent

Semiconductor device

An improvement is achieved in the reliability of a semiconductor device having an igbt. In an active cell region, in a portion of a semiconductor substrate which is interposed between first and second trenches in which first and second trench gate electrodes are embedded, an n+-type emitter region, a p-type body region located thereunder, and a first n-type hole barrier region located thereunder are formed.
Renesas Electronics Corporation

new patent

3c-sic igbt

We disclose herein a method of manufacturing a silicon carbide (sic) based insulated gate bipolar transistor (igbt), the igbt comprising: a monocrystalline silicon substrate; a collector region of a first conductivity type disposed over the silicon substrate, wherein the collector region comprises a material comprising 3-step cubic silicon carbide (3c-sic); a semiconductor drift region of a second conductivity type, opposite the first conductivity type, disposed on the collector region; a body region of the first conductivity type located within the semiconductor drift region; an emitter region of the second conductivity type located within the body region; a gate region placed above and in contact to the emitter region. The method comprising: providing the silicon substrate having a principal surface, wherein the silicon substrate is of the second conductivity type; doping the principal surface of the silicon substrate using an aluminium ion implant; and driving the aluminium ion implant into the silicon substrate to a predetermined depth under a predetermined temperature so that a heavily doped silicon region of the first conductivity type is formed near the principal surface within the silicon substrate..
Anvil Semiconductors Limited

new patent

Desaturable semiconductor device with transistor cells and auxiliary cells

A semiconductor device includes transistor cells that connect a first load electrode with a drift structure forming first pn junctions with body zones when a gate voltage applied to a gate electrode exceeds a first threshold voltage. First auxiliary cells in a vertical projection of and electrically connected with the first load electrode are configured to inject charge carriers into the drift structure at least in a forward biased mode of the first pn junctions.
Infineon Technologies Ag

new patent

Semiconductor device, manufacturing semiconductor device, and forming oxide film

One embodiment of the present invention is a semiconductor device at least including an oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film therebetween. The oxide semiconductor film has a spin density lower than 9.3×1016 spins/cm3 and a carrier density lower than 1×1015/cm3.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor device

A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. The semiconductor device includes an oxide semiconductor film over an insulating surface, an antioxidant film over the insulating surface and the oxide semiconductor film, a pair of electrodes in contact with the antioxidant film, a gate insulating film over the pair of electrodes, and a gate electrode which is over the gate insulating film and overlaps with the oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Fin structure of semiconductor device

The disclosure relates to a fin field effect transistor (finfet). An exemplary finfet comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising an upper portion comprising a first semiconductor material having a first lattice constant, wherein the upper portion comprises a first substantially vertical portion having a first width and a second substantially vertical portion having a second width less than the first width over the first substantially vertical portion; and a lower portion comprising a second semiconductor material having a second lattice constant less than the first lattice constant, wherein a top surface of the lower portion has a third width less than the first width; and a gate structure covering the second substantially vertical portion..
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Semiconductor device and fabricating the same

The semiconductor device includes a first wire pattern formed on a substrate and spaced apart from the substrate, the first wire pattern extending in a first direction. A gate electrode surrounds a circumference of the first wire pattern and extends in a second direction.
Samsung Electronics Co., Ltd.

new patent

Spacer formation with straight sidewall

Disclosed herein is a semiconductor device comprising a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric.
Cypress Semiconductor Corporation

new patent

Field-plate structures for semiconductor devices

Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor structure includes a semiconductor substrate, a source ohmic contact, a drain ohmic contact, and a gate contact disposed over a gate region between the source ohmic contact and the drain ohmic contact, and a source field plate connected to the source ohmic contact.
Cambridge Electronics, Inc.

new patent

Semiconductor device and manufacturing semiconductor device

A semiconductor device includes an n-type silicon carbide substrate, an n-type silicon carbide layer formed on the n-type silicon carbide substrate, a p-type region selectively formed in a surface layer of the n-type silicon carbide layer, an n-type source region formed in the p-type region, a p contact region formed in the p-type region, a gate insulating film formed on a portion of a region from the n-type source region, through the p-type region, to the n-type silicon carbide layer, a gate electrode formed on the gate insulating film, an interlayer insulating film covering the gate electrode, and a first source electrode electrically connected to a surface of the p contact region and the n-type source region. An end of the interlayer insulating film covering the gate electrode has a slope of a predetermined angle..
Fuji Electric Co., Ltd.

new patent

Semiconductor device and a forming a semiconductor device

A method for forming a semiconductor device includes forming at least one graphene layer on a surface of a semiconductor substrate. The method further includes forming a silicon carbide layer on the at least one graphene layer..
Infineon Technologies Ag

new patent

Split-gate devices

A semiconductor device includes a substrate having a source region and a drain region implanted with a second dopant by a second ion implantation. The substrate includes a first well region implanted with a first dopant by a first ion implantation and a second well region blocked from the first ion implantation forming a native section.
Broadcom Corporation

new patent

Semiconductor device and manufacturing the same

A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the soi substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed.

new patent

Semiconductor device having a fin

Provided is a semiconductor device. The semiconductor device includes a fin disposed on a substrate along a first direction.
Samsung Electronics Co., Ltd.

new patent

Semiconductor device

A semiconductor device including a semiconductor substrate of a first conductivity type, a plurality of base regions of a second conductivity type formed on a first principal surface of the semiconductor substrate via a semiconductor layer of the first conductivity type, and a plurality of source regions of the first conductivity type formed in the base regions. Each base region, in a top-down view from an angle perpendicular to the first principle surface, is of a polygonal shape.
Fuji Electric Co., Ltd.

new patent

Semiconductor device

A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first jte region is set to 4.4×1017 cm−3 or higher and 6×1017 cm−3 or lower and an impurity concentration in a second jte region is set to 2×1017 cm−3 or lower in a case of a schottky diode, and an impurity concentration in the first jte region is set to 6×1017 cm−3 or higher and 8×107 cm−3 or lower and an impurity concentration in the second jte region is set to 2×1017 cm−3 or lower in a case of a junction barrier schottky diode..
Hitachi Power Semiconductor Device, Ltd.

new patent

Method for manufacturing semiconductor device

A method of manufacturing a semiconductor device includes forming a lower metal layer, forming an interfacial oxide film on the lower metal layer, providing a metal precursor on the interfacial oxide film at a first pressure to adsorb the metal precursor into the interfacial oxide film, performing a first purge process at a second pressure to remove the unadsorbed metal precursor, the second pressure lower than the first pressure, providing an oxidizing gas at the first pressure to react with the adsorbed metal precursor, performing a second purge process at the second pressure to remove the unreacted oxidizing gas and form a dielectric film, and forming an upper metal layer on the dielectric film.. .
Samsung Electronics Co., Ltd.

new patent

Waveguide and semiconductor packaging

A method and apparatus for integrating individual iii-v mmics into a micromachined waveguide package is disclosed. Mmics are screened prior to integration, allowing only known-good die to be integrated, leading to increased yield.
Northrop Grumman Systems Corporation

new patent

Semiconductor package, semiconductor device manufacturing method, and solid-state imaging device

A semiconductor package includes: a sheet-like thin plate on which a semiconductor chip is secured; and a substrate including a wiring layer, disposed on the thin plate to extend over a part of a region surrounding the region where the semiconductor chip is secured or over the entire surrounding region, wherein the semiconductor chip and the substrate are electrically connected.. .
Sony Corporation

new patent

Apparatus for radiation detection in a digital imaging system

The disclosure is directed at a method and apparatus for producing a detector element. The detector element includes first and second electrodes located on opposites sides of a semiconductor layer.

new patent

Cmos image sensor with pump gate and extremely high conversion gain

Some embodiments relate to an image sensor pixel comprising a transfer gate formed on a first surface of a semiconductor substrate, a floating diffusion formed in the first surface of the semiconductor substrate, and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially beneath the transfer gate. The transfer gate is spaced away from the floating diffusion such that an intervening semiconductor region provides a potential barrier to charge flow from beneath the transfer gate to the floating diffusion.
Dartmouth College

new patent

Isolated global shutter pixel storage structure

An imaging system includes a pixel array of pixel cells with each one of the pixel cells including a photodiode disposed in a semiconductor material, a global shutter gate transistor, disposed in the semiconductor material and coupled to the photodiode, a storage transistor disposed in the semiconductor material, an optical isolation structure disposed in the semiconductor material to isolate a sidewall of the storage transistor from stray light and stray charge. The optical isolation structure also includes a deep trench isolation structure that is filled with tungsten and a p+ passivation formed over an interior sidewall of the deep trench optical isolation structure.
Omnivision Technologies, Inc.

new patent

Semiconductor device

A semiconductor device including a capacitor having an increased charge capacity without decreasing an aperture ratio is provided. The semiconductor device includes a transistor including a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, and a pixel electrode electrically connected to the transistor.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor device

A semiconductor device that is suitable for miniaturization is provided. The semiconductor device has a plurality of different transistors, active layers of the plurality of transistors are each an oxide semiconductor, and in the plurality of transistors, field-effect mobility of a transistor whose channel length is maximum and field-effect mobility of a transistor whose channel length is minimum are substantially constant.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Display device and manufacturing the same

A display device capable of reducing the number of manufacturing processes and manufacturing costs and a method of manufacturing the display device are provided, the display device including: a first substrate; a gate transmission member and a pixel electrode on the first substrate; a gate insulating layer on the gate transmission member and the pixel electrode; a semiconductor layer on the gate insulating layer, the semiconductor layer overlapping a gate electrode of the gate transmission member; and a source electrode and a drain electrode on the semiconductor layer, wherein the gate transmission member includes a first conductive layer pattern and a second conductive layer pattern on the first conductive layer pattern, the first conductive layer pattern including a material the same as a material forming the pixel electrode.. .
Samsung Display Co., Ltd.

new patent

Soi-based semiconductor device with dynamic threshold voltage

A semiconductor device includes a semiconductor substrate, an insulating layer on a top surface of the substrate, and a first semiconductor transistor on the insulating layer, the transistor including an active region with a source region, a drain region, a channel region between the source and drain regions and a gate structure over the channel region, the gate structure extending beyond the transistor to an adjacent area. An outer well is included in the substrate, an inner well of an opposite type as the outer well situated within the outer well and under the active region and adjacent area, and a contact for the inner well in the adjacent area, the contact surrounding the gate structure.
Globalfoundries Inc.

new patent

Ultrahigh density vertical nand memory device and making thereof

Monolithic, three dimensional nand strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.. .
Sandisk Technologies Llc

new patent

Semiconductor memory device and manufacturing the same

According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate.
Kabushiki Kaisha Toshiba

new patent

Semiconductor memory device and manufacturing the same

According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate.
Kabushiki Kaisha Toshiba

new patent

Semiconductor memory device and manufacturing the same

Manufactured in a method of manufacturing according to an embodiment is a semiconductor memory device including: control gate electrodes; a semiconductor layer; and a charge accumulation layer. In this method of manufacturing, inter-layer insulating layers and sacrifice layers are stacked alternately, an opening that penetrates the inter-layer insulating layers and sacrifice layers is formed, a first insulating layer, the charge accumulation layer, and the semiconductor layer are formed in the opening, the sacrifice layer and part of the first insulating layer are removed, and the control gate electrodes are formed.
Kabushiki Kaisha Toshiba

new patent

Semiconductor memory device

According to one embodiment, a semiconductor memory device comprises a first stacked body, a column, a second stacked body, a through portion, and a first insulating portion. The first stacked body includes first conductive layers and first insulating layers.
Kabushiki Kaisha Toshiba

new patent

Semiconductor memory device and manufacturing the same

According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate.
Kabushiki Kaisha Toshiba

new patent

Semiconductor memory device and manufacturing same

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body provided on the substrate and including multiple electrode layers separately stacked with each other, a semiconductor film, a charge storage film provided between the semiconductor film and the multiple electrode layers, and a first insulating film provided between the semiconductor film and the charge storage film, extending in the stacking direction, and having a bottom surface contacting the substrate. The semiconductor film is provided integrally with the substrate in the stacked body, and extends in a stacking direction of the stacked body.
Kabushiki Kaisha Toshiba

new patent

Semiconductor memory device and manufacturing the same

According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode films and a plurality of insulating films, the plurality of electrode films and the plurality of insulating films being alternately stacked on each other, a semiconductor pillar extending in a stacking direction of the stacked body, and a charge storage film provided between the electrode films and the semiconductor pillar and extending linearly in the stacking direction of the stacked body. A stacking-direction width of an edge portion of the electrode films on side of the semiconductor pillar is shorter than a stacking-direction width of the electrode films other than the edge portion of the electrode films..
Kabushiki Kaisha Toshiba

new patent

Semiconductor device

An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Nonvolatile semiconductor memory device and manufacturing the same

A nonvolatile semiconductor memory device comprises: a substrate; a memory cell that is disposed on the substrate and accumulates a charge as data; and a cover layer covering the memory cell. The cover layer has a structure in which a first silicon nitride layer, an intermediate layer, and a second silicon nitride layer are stacked sequentially from a memory cell side..
Kabushiki Kaisha Toshiba

new patent

Semiconductor device

Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film.
Renesas Electronics Corporation

new patent

Semiconductor device and manufacturing semiconductor device

A semiconductor device having a high degree of freedom of layout has a first part ar1, in which a plurality of p-type wells pw and n-type wells nw are alternately arranged to be adjacent to each other along an x-axis direction. A common power feeding region (arp2) for the plurality of wells pw is arranged on one side so as to interpose the ar1 in a y-axis direction, and a common power feeding region (arn2) for the plurality of wells nw is arranged on the other side.
Renesas Electronics Corporation

new patent

Semiconductor device including capacitor and manufacturing the same

A method for manufacturing a semiconductor device may include forming contact pads spaced apart from each other in a first direction on a substrate and between first insulating patterns; forming first holes between the first insulating patterns and having bottom ends adjacent top surfaces of the contact pads; forming second holes between second insulating patterns and overlapping with partial portions of the first holes in a second direction perpendicular to the first direction; and forming a bottom electrode layer including first portions to cover the bottom ends of the first holes and sidewalls of the second holes. In forming the first and second holes, the first and second holes are formed simultaneously..
Samsung Electronics Co., Ltd.

new patent

Semiconductor devices including device isolation structures and methods of manufacturing the same

A method of manufacturing a semiconductor device includes forming a plurality of recess regions on an upper surface of a substrate, forming a first oxide layer in the recess regions, forming a polysilicon layer on the first oxide layer, forming a second oxide layer by oxidizing the polysilicon layer, and forming a gap-fill layer on the second oxide layer to fill the recess regions, wherein at least a portion of the polysilicon layer remains between the first oxide layer and the second oxide layer after forming the second oxide layer.. .
Samsung Electronics Co., Ltd.

new patent

Semiconductor device and manufacturing the same

A semiconductor device and a method for manufacturing the same is described. The semiconductor device includes a substrate, a first capacitor and a second capacitor.
Advanced Semiconductor Engineering, Inc.

new patent

Transistor

A transistor includes: a semiconductor substrate; a plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes on the semiconductor substrate; a drain pad on the semiconductor substrate and connected to the plurality of drain electrodes; a metal wiring on the semiconductor substrate and arranged spaced apart from, adjacent to and parallel to the drain pad; and a ground pad on the semiconductor substrate and connected to both ends of the metal wiring.. .
Mitsubishi Electric Corporation

new patent

Semiconductor device with a switchable and a non-switchable diode region

A semiconductor device includes at least one igbt cell region, at least one switchable free-wheeling diode region, and at least one non-switchable free-wheeling diode region integrated in the same semiconductor substrate as the at least one igbt cell region and the at least one switchable free-wheeling diode region.. .
Infineon Technologies Ag

new patent

Semiconductor device

In order to reduce electric field concentration in a semiconductor device including a main transistor section and a sense transistor section, the semiconductor device is provided, the semiconductor device including a semiconductor substrate of a first conductivity type, a main transistor section in an active region on the semiconductor substrate, and a sense transistor section outside the active region on the semiconductor substrate, wherein the active region is provided with a main well region of a second conductivity type, and wherein the sense transistor section has a sense gate trench section formed extending from the outside of the active region to the main well region on the front surface of the semiconductor substrate.. .
Fuji Electric Co., Ltd.

new patent

Dual-sided silicon integrated passive devices

In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface.
Apple Inc.

new patent

Silicon carbide semiconductor device and manufacturing the same

The first base regions have an impurity concentration of 4×1017 cm−3 or higher. The p-type region 33 is designed to have a lower impurity concentration than the first base regions 10 and higher than the p-type regions 31, 32.

new patent

Semiconductor device comprising a clamping structure

semiconductor device with a semiconductor body that includes a clamping structure including a pn junction diode and a schottky junction diode serially connected back to back between a first contact and a second contact. A breakdown voltage of the pn junction diode is greater than 100 v and a breakdown voltage of the schottky junction diode is greater than 10 v..
Infineon Technologies Austria Ag

new patent

Light emitting diode (led) package having short circuit (vled) die, lens support dam and same side electrodes and fabrication

A light emitting diode (led) package includes a main vled die; a short circuit vled die; a lens support dam; a transparent lens attached to the lens support dam; a first electrode in electrical communication with a first semiconductor layer of the main vled die and a second electrode in electrical communication with a second semiconductor layer of the main vled die.. .
Semileds Optoelectronics Co., Ltd.

new patent

Electronic circuit

A semiconductor device includes a mosfet including a pn junction diode. A unipolar device is connected in parallel to the mosfet and has two terminals.
Rohm Co., Ltd.

new patent

Semiconductor device and manufacture

An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the info-pop architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the info-pop architecture.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same

semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (msd) structure having a first substantially horizontal arrangement of semiconductor dies.

new patent

Flipped die stack

A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip terminal may extend from a contact at a front surface of each chip in a direction towards the edge surface of the respective chip.
Invensas Corporation

new patent

Semiconductor device

A semiconductor device includes a first circuit board having a first chip and a second chip mounted on a first base, the second chip having a greater height from the first base than that of the first chip; and a second circuit board having a third chip and a fourth chip mounted on a second base, the fourth chip having a greater height from the second base than that of the third chip, the second circuit board being disposed overlapping with the first base such that the second base faces the first chip, and the second base not contacting the second chip.. .
Fujitsu Limited

new patent

Semiconductor package having a plurality of semiconductor chips stacked therein

A semiconductor package may include a first semiconductor chip having a plurality of first bonding pads arranged at a first pitch on a first active surface. The semiconductor package may include one or more reconfigurable package units each including a second semiconductor chip having a plurality of second bonding pads arranged at a second pitch on a second active surface; a semiconductor chip connector arranged spaced apart from the second semiconductor chip and having a plurality of through vias arranged at the first pitch; a molding layer surrounding side surfaces of the second semiconductor chip and the semiconductor chip connector; and redistribution lines formed over the second semiconductor chip, the semiconductor chip connector, and the molding layer.
Sk Hynix Inc.

new patent

Semiconductor device and method

Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit.
Chip Solutions, Llc

new patent

Semiconductor device and semiconductor device fabrication method

A semiconductor device includes a plurality of semiconductor units each including a laminated substrate formed by laminating an insulating board and a circuit board and a semiconductor element joined to the circuit board using a joining material which irreversibly makes a phase transition into a solid-phase state. In addition, the semiconductor device may include a base plate to which each of the plurality of semiconductor units is joined using solder and a connection unit which electrically connects the plurality of semiconductor units in parallel..
Fuji Electric Co., Ltd.

new patent

Using an interconnect bump to traverse through a passivation layer of a semiconductor die

A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers.
Qorvo Us, Inc.

new patent

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a conductive bump, and a ferromagnetic member extended within the conductive bump, wherein a center of the conductive bump is disposed on a central axis of the ferromagnetic member.. .
Taiwan Semiconductor Manufacturing Company Ltd.

new patent

Method of producing a semiconductor device with through-substrate via covered by a solder ball

A semiconductor substrate is provided with a through-substrate via comprising a metallization and an opening. A solder ball is placed on the opening.
Ams Ag

new patent

Method for manufacturing semiconductor device, semiconductor manufacturing apparatus, and wafer lift pin-hole cleaning jig

To shorten a maintenance time of a semiconductor manufacturing apparatus and to improve productivity of a semiconductor manufacturing line. A semiconductor wafer is processed by the semiconductor manufacturing apparatus in which reaction product in the inside of a wafer lift pin hole was removed using a cleaning jig having a return on its tip part..
Renesas Electronics Corporation

new patent

Transmission line for 3d integrated circuit

A semiconductor transmission line substructure and methods of transmitting rf signals are described. The semiconductor transmission line substructure can include a substrate; a first signal line over the substrate; a first ground line over the substrate; and a second semiconductor substrate over the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Semiconductor package including an antenna formed in a groove within a sealing element

There are provided a semiconductor package including an antenna formed integrally therewith, and a method of manufacturing the same. The semiconductor package includes: a semiconductor chip; a sealing part sealing the semiconductor chip; a substrate part formed on at least one surface of the sealing part; and an antenna part formed on the sealing part or the substrate part and electrically connected to the semiconductor chip..
Samsung Electro-mechanics Co., Ltd.

new patent

Semiconductor device

The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Vias are formed in each layer on a dicing region side.
Renesas Electronics Corporation

new patent

Semiconductor device and semiconductor system

A semiconductor device is provided. The semiconductor device includes a seal ring and a noise-absorbing circuit.
Taiwan Semiconductor Manufacturing Co., Ltd

new patent

Through-body via liner deposition

Techniques are disclosed for through-body via liner structures and processes of forming such liner structures in an integrated circuit. In an embodiment, an integrated circuit includes a silicon semiconductor substrate having one or more through-silicon vias (tsvs), although other through-body vias can be used as will be appreciated in light of this disclosure.
Intel Corporation

new patent

Semiconductor device and forming emi shielding layer with conductive material around semiconductor die

A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier.
Stats Chippac Pte. Ltd.

new patent

Tungsten alloys in semiconductor devices

Conducting alloys comprising cobalt, tungsten, and boron and conducting alloys comprising nickel, tungsten, and boron are described. These alloys can, for example, be used to form metal interconnects, can be used as liner layers for traditional copper or copper alloy interconnects, and can act as capping layers.
Intel Corporation

new patent

Wiring board with embedded component and integrated stiffener and making the same

A wiring board with embedded component and integrated stiffener is characterized in that an embedded semiconductor device, a first routing circuitry, an encapsulant and an array of vertical connecting elements are integrated as an electronic component disposed within a through opening of a stiffener, and a second routing circuitry is disposed beyond the through opening of the stiffener and extends over the stiffener. The mechanical robustness of the stiffener can prevent the wiring board from warping.
Bridge Semiconductor Corporation

new patent

Semiconductor device having structure for improving voltage drop and device including the same

A semiconductor device includes a semiconductor substrate and a plurality of metal layers above the semiconductor substrate. A first of the metal layers includes a plurality of first power rails which extend in a first direction and provide a first voltage, a plurality of second power rails which extend in the first direction and provide a second voltage, and a first conductor which is integral with one end of each of the first power rails and extends in a second direction.
Samsung Electronics Co., Ltd.

new patent

Semiconductor die with a metal via

A semiconductor die that may include a substrate; an epitaxial layer; a metal layer; a first transistor; and a metal via that surrounds the first transistor, extends between the metal layer and the substrate, and penetrates the substrate.. .
Tower Semiconductor Ltd.

new patent

Method of manufacturing semiconductor device and semiconductor device

Pretreatment is carried out in a first chamber. Then, a mixed gas of titanium tetrachloride and hydrogen is supplied into a second chamber.
Renesas Electronics Corporation

new patent

Via structures for thermal dissipation

An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a substrate, pluralities of vias disposed in the substrate.
Avago Technologies General Ip (singapore) Pte. Ltd

new patent

Method of semiconductor integrated circuit fabrication

A method of fabricating a semiconductor integrated circuit (ic) is disclosed. A conductive feature over a substrate is provided.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Soc with integrated voltage regulator using preformed mim capacitor wafer

In some embodiments, a method and/or a system may include an integrated circuit. The integrated circuit may include a semiconductor die.
Apple Inc.

new patent

Interconnect structure for semiconductor devices

An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Semiconductor device for electric power

Herein provided are: a ceramic board; a semiconductor element for electric power, on one surface of which an electrode is formed, and the other surface of which is bonded to the ceramic board; a lead terminal, one end side of which is bonded to the electrode, and the other end side of which is to be electrically connected to an outside thereof; and a sealing member by which the semiconductor element for electric power is sealed together with a part, in the lead terminal, bonded to the electrode; wherein, near an end in said one end side of the lead terminal, an inclined surface is formed which becomes farther from the circuit board as it becomes closer to the end.. .
Mitsubishi Electric Corporation

new patent

Semiconductor package and manufacturing method thereof

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns..
Amkor Technology, Inc.

new patent

Interposers, semiconductor devices, manufacturing interposers, and manufacturing semiconductor devices

An interposer which can better prevent detachment of a conductive layer pattern due to thermal expansion and thermal contraction. The interposer includes a substrate having a through hole; an insulative resin layer formed on a surface of the substrate and including a conductive via; a wiring layer disposed on the substrate with the insulative resin layer interposed therebetween; an inorganic adhesive layer formed only on a side surface of the through hole; and a through electrode filled in a connection hole which is formed by the inorganic adhesive layer in the through hole so as to penetrate between both surfaces of the substrate, wherein the through electrode is electrically connected to the wiring layer via the conductive via, and a thermal expansion coefficient of the inorganic adhesive layer is larger than a thermal expansion coefficient of the substrate and smaller than a thermal expansion coefficient of the through electrode..
Toppan Printing Co., Ltd.

new patent

Semiconductor module

A semiconductor module can be realized, which is formed by mounting an electronic component and a bus bar by solder on a lead frame including a plurality of terminals, wherein a solder flow suppressing section capable of restricting a direction of flow of solder on the lead frame is formed in the vicinity of the solder portion of the component mounted by solder, and by this configuration, positional deviation, such as rotation or movement of the mounted component, is suppressed and the size of the module can be made compact.. .
Mitsubishi Electric Corporation

new patent

Flipped die stack assemblies with leadframe interconnects

A microelectronic assembly includes a stack of microelectronic elements, e.g., semiconductor chips, each having a front surface defining a respective plane of a plurality of planes. A leadframe interconnect joined to a contact at a front surface of each chip may extend to a position beyond the edge surface of the respective microelectronic element.
Invensas Corporation

new patent

Semiconductor device

The semiconductor device includes a semiconductor element, and an electro-conductive first plate-like part electrically connected to a top-face-side electrode of the semiconductor element and including a first joint part projecting from a side face, and an electro-conductive second plate-like part including a second joint part projecting from a side face. A bottom face of the first joint part and a top face of the second joint part face one another, and are electrically connected via an electro-conductive bonding material.
Denso Corporation

new patent

Recessed lead leadframe packages

Leadframes for semiconductor packages. Implementations may include a plurality of leads extending inwardly into an opening surrounded by the plurality of leads where the plurality of leads except for at least one are configured to mechanically couple at a surface of a semiconductor chip.
Semiconductor Components Industries, Llc

new patent

Semiconductor device

A control terminal 14 of a semiconductor device has a recessed portion 14c. A resin case 15 is provided with a fixing member 152 engaging with and fixing a recessed portion 14c of a control terminal 14.
Fuji Electric Co., Ltd.

new patent

Semiconductor device

A semiconductor device includes a substrate, a thermal conduction layer on the substrate, a first wire pattern on the thermal conduction layer, a first semiconductor pattern a second semiconductor pattern, and a gate electrode between the first semiconductor pattern and the second semiconductor pattern. The gate electrode surrounds a periphery of the first wire pattern.
Samsung Electronics Co., Ltd.

new patent

Via structures for thermal dissipation

An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a substrate, pluralities of vias disposed in the substrate.
Avago Technologies General Ip (singapore) Pte. Ltd.

new patent

Semiconductor device and method

Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate having a first surface and a second surface. The semiconductor die is attached to the second surface.
Chip Solutions, Llc

new patent

Phosphonium compound, epoxy resin composition including the same and semiconductor device prepared using the same

A phosphonium compound, an epoxy resin composition including the same, a semiconductor device encapsulated with the same, and a method of encapsulating a semiconductor device, the phosphonium compound being represented by formula 1:. .
Samsung Sdi Co., Ltd.

new patent

Underfill material, laminated sheet and producing semiconductor device

An underfill material having sufficient curing reactivity, and capable of achieving a small change in viscosity and good electrical connection even when loaded with thermal history, a laminated sheet including the underfill material, and a method for manufacturing a semiconductor device. The underfill material has a melt viscosity at 150° c.
Nitto Denko Corporation

new patent

Semiconductor device

A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad..
Renesas Electronics Corporation

new patent

X-ray inspection inspecting semiconductor wafers

An x-ray inspection system including an x-ray source, a sample support for supporting a sample to be inspected, an x-ray detector, a sample positioning assembly including a first positioning mechanism for moving the sample support along a first axis towards and away from the x-ray source, a proximity sensor fixed to the x-ray source configured to provide a measurement of distance between the x-ray source and a surface of a sample on the sample support, and a controller connected to the proximity sensor. Measurements from the proximity sensor can be used in image processing calculations and to prevent collision between a sample and the x-ray source..
Nordson Corporation

new patent

Silicon-germanium finfet device with controlled junction

Embodiments of the invention include a method for <something> and the resulting structure. A semiconductor device including a substrate, a silicon-germanium fin formed on the substrate, a dummy gate formed on the fin, and a first set of spacers formed on the exposed sidewalls of the dummy gate is provided.
International Business Machines Corporation

new patent

Semiconductor device and manufacturing the same

A semiconductor device includes a first fin-type pattern and a second fin-type pattern which protrude upwardly from an upper surface of a field insulating film and extend in a first direction. A gate structure intersects the first fin-type pattern and the second fin-type pattern.
Samsung Electronics Co., Ltd.

new patent

Dipole-based contact structure to reduce metal-semiconductor contact resistance in mosfets

A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.. .
The Research Foundation For The State University Of New York

new patent

Semiconductor device and fabricating method thereof

A semiconductor device is provided. A substrate includes a first region and a second region.

new patent

Semiconductor device including at least one lateral igfet and at least one vertical igfet and corresponding manufacturing method

A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface, first trenches and second trenches extending from the first surface into the semiconductor body, at least one lateral igfet including a first load terminal at the first surface, a second load terminal at the first surface and a gate electrode within the first trenches, and at least one vertical igfet including a first load terminal at the first surface, a second load terminal at the second surface and a gate electrode within the second trenches. The first trenches extend from the first surface into the semiconductor body deeper than a channel zone of the lateral igfet and confine the channel zone..
Infineon Technologies Ag

new patent

Semiconductor structure with self-aligned spacers and fabricating the same

A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate.
United Microelectronics Corp.

new patent

Interconnect structure including middle of line (mol) metal layer local interconnect on etch stop layer

An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer.
Globalfoundries, Inc.

new patent

Method for cleaning via of interconnect structure of semiconductor device structure

A method for forming the semiconductor device structure is provided. The method includes forming a metal layer in a first dielectric layer over a substrate and forming an etch stop layer over the metal layer.
Taiwan Semiconductor Manufacturing Co., Ltd

new patent

Semiconductor device comprising an oxygen diffusion barrier and manufacturing method

An embodiment of a method of manufacturing a semiconductor device includes forming an oxygen diffusion barrier on a first surface of a czochralski or magnetic czochralski silicon substrate. A silicon layer is formed on the oxygen diffusion barrier.
Infineon Technologies Ag

new patent

Method for preparing low-warpage semiconductor substrate

Disclosed is a method for preparing a low-warpage semiconductor substrate. The method includes: providing a first substrate and a second substrate, the first substrate including a first surface and a second surface which are opposite to each other, a first insulating layer is disposed on the first surface.
Shanghai Simgui Tehcnology Co., Ltd.

new patent

Methods of manufacturing semiconductor devices including isolation layers

A method of manufacturing a semiconductor device comprising the steps of: forming a trench at an upper portion of a semiconductor substrate forming a preliminary filling insulation layer by coating a siloxane composition on the semiconductor substrate to fill the trench performing a low temperature curing process at a temperature in a range from about 50° c. To about 150° c.
Samsung Electronics Co., Ltd.

new patent

Releasable carrier and method

Disclosed herein is a releasable carrier that includes a supporting carrier, a carrier conductive layer, and a releasable tape located between the supporting carrier and the carrier conductive layer. The releasable tape attaches the supporting carrier to the carrier conductive layer.
Chip Solutions, Llc

new patent

Semiconductor device and method

Disclosed herein is a semiconductor device that includes a substrate having a conductive circuit and a first mold material encapsulating the conductive circuit, the first mold material configured to function as an electrical insulator. The semiconductor device further includes a semiconductor die encapsulated with the first mold material or a second mold material.
Chip Solutions, Llc

new patent

Misalignment/alignment compensation method, semiconductor lithography system, and semiconductor patterning

A misalignment/alignment compensation method for a lithography process includes the steps of: obtaining misalignment data associated with an alignment mark disposed on a substrate; and obtaining a compensation parameter by performing asymmetry compensation calculation on at least one of a first directional component of the misalignment data, which is associated with a first direction, and a second directional component of the misalignment data, which is associated with a second direction.. .

new patent

3d ic bump height metrology apc

The present disclosure relates to a method of bump metrology that relies upon advanced process control (apc) to provide substrate warpage parameters describing a warpage of a substrate to a bump metrology module to improve focus of the bump metrology module. In some embodiments, the method measures one or more substrate warpage parameters of a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Cluster tool techniques with improved efficiency

Some embodiments relate to a cluster tool for semiconductor manufacturing. The cluster tool comprises a first transfer chamber having a first transfer robot.
Taiwan Semiconductor Manufactring Co., Ltd.

new patent

Semiconductor device and manufacture

A semiconductor device and method of manufacturing are presented in which features of reduced size are formed using an irradiated mask material. In an embodiment a mask material that has been irradiated with charged ions is utilized to focus a subsequent irradiation process.
National Taiwan University

new patent

Semiconductor device and semiconductor device manufacturing method

Protons are injected from a back surface side of a semiconductor substrate to repair both defects within the semiconductor substrate and also defects in a channel forming region on a front surface side of the semiconductor substrate. As a result, variation in gate threshold voltage is reduced and leak current when a reverse voltage is applied is reduced.
Fuji Electric Co., Ltd.

new patent

Manufacturing semiconductor structure

A manufacturing method of a semiconductor structure having an array area and a periphery area is provided. The manufacturing method includes the following steps.
United Microelectronics Corp.

new patent

Semiconductor manufacturing apparatus and manufacturing semiconductor device

A semiconductor manufacturing apparatus according to an embodiment includes a container that stores a processing liquid for plating processing of a substrate. A holder can hold the substrate.
Kabushiki Kaisha Toshiba

new patent

Semiconductor structure and manufacture method thereof

A method of making a semiconductor structure can include: (i) forming a plurality of oxide layers on a semiconductor substrate; (ii) forming a plurality of conductor layers on the plurality of oxide layers; (iii) forming plurality of thickening layers on the plurality of conductor layers; (iv) patterning the plurality of conductor layers and the plurality of thickening layers to form a hard mask; and (v) implanting ion using the hard mask to form a plurality of doped regions.. .
Silergy Semiconductor Technology (hangzhou) Ltd

new patent

Method for manufacturing semiconductor device

There are prepared a semiconductor substrate having a first main surface and a second main surface, and an adhesive tape having a third main surface and a fourth main surface, the first main surface having a maximum diameter of not less than 100 mm. The semiconductor substrate fixed to the third main surface of the adhesive tape is placed in an accommodation chamber.
Sumitomo Electric Industries, Ltd.

new patent

Semiconductor substrates and methods for processing semiconductor substrates

semiconductor substrates and methods for fabricating integrated circuits are provided. A method for fabricating an integrated circuit includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region.
Globalfoundries, Inc.

new patent

Method of manufacturing semiconductor device, substrate processing apparatus and recording medium

A method of manufacturing: a semiconductor device includes fanning an oxide film containing a metal element on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor containing a metal element and a halogen group to the substrate; and supplying an oxidant to the substrate. In the act of supplying the oxidant, a catalyst is supplied to the substrate together with the oxidant.
Hitachi Kokusai Electric Inc.

new patent

Semiconductor plasma antenna apparatus

Provided is a semiconductor plasma antenna apparatus. The apparatus includes: a cell array unit in which a plurality of pin diode cells are arranged, and in which a cell pattern is formed by using a predefined pin diode cell among the plurality of pin diode cells; and a driver circuit unit configured to control a drive of the predefined pin diode cell, wherein the driver circuit unit comprises: a direct-current conversion unit equipped with a dc-dc converter configured to drive a diode load of the cell pattern by applying an output voltage to a pin diode cell corresponding to the cell patterns formed in the cell array unit; and a constant current controller configured to controlling a plasma concentration of the pin diode cell by controlling a constant current for the diode load of the cell pattern..
Electronics And Telecommunications Research Institute

new patent

Perovskite solar cell

A perovskite solar cell includes: a first electrode; an electron transport layer on the first electrode, containing a semiconductor; a porous layer on the electron transport layer, containing a porous material; a light-absorbing layer on the porous layer, containing a first compound and a second compound different from the first compound, the first compound having a perovskite structure represented by a compositional formula abx3 where a represents a monovalent cation, b represents a divalent cation, and x represents a halogen anion, the second compound containing the divalent cation; and a second electrode on the light-absorbing layer. A ratio of a number of moles of the monovalent cation in the light-absorbing layer to a number of moles of the divalent cation in the light-absorbing layer is 0.5 or more and 0.9 or less..
Panasonic Corporation

new patent

Crystal growth control agent, forming p-type semiconductor microparticles or p-type semiconductor microparticle film, composition for forming hole transport layer, and solar cell

First, there is provided a crystal growth control agent which is capable of suppressing an increase in a crystal size of a p-type semiconductor, and performing chemical modification on a surface of p-type semiconductor microparticle. Second, there is provided a composition for forming a hole transport layer which is capable of prompting crystallization and fine pulverization of the p-type semiconductor and performing the chemical modification on the surface of the p-type semiconductor microparticle even in the case where an organic salt (an ionic liquid) containing an anion other than the thiocyanate ion is used.
Tokyo Ohka Kogyo Co., Ltd.

new patent

Sinterable metal particles and the use thereof in electronics applications

Provided herein are sinterable metal particles and compositions containing same. Such compositions can be used in a variety of ways, i.e., by replacing solders as die attach materials.
Henkel Ip & Holding Gmbh

new patent

Random number generation circuit and semiconductor system including the same

A random number generation circuit may include a memory block. The random number generation circuit may include a fuse block configured to store an address of a failed memory cell from a memory cell array of the memory block, as a repair address, and generate a match signal by comparing the repair address with a normal address inputted from an exterior.
Sk Hynix Inc.

new patent

Semiconductor apparatus and repair method thereof

A semiconductor apparatus includes a memory region; a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region; a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; and a control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected.. .
Sk Hynix Inc.

new patent

Semiconductor devices and semiconductor systems including the same

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output command signals and setting signals.
Sk Hynix Inc.

new patent

Semiconductor integrated circuit device having groung wiring portions connected to at least two memories that store identical data

On an ic chip, a first ground wiring line and a second ground wiring line that extends from a connection site with the first ground wiring line are disposed in a doubled manner. Among eproms storing identical data, the source of a first eprom is connected to the second ground wiring line and the source of a second eprom is connected to the first ground wiring line.
Fuji Electric Co., Ltd.

new patent

Refresh verification circuit, semiconductor apparatus and semiconductor system

A refresh verification circuit may include a filtering circuit configured to receive a refresh pulse and to generate a filtering pulse in response to a duration of the enable period of the refresh pulse.. .
Sk Hynix Inc.

new patent

Semiconductor memory device outputting read-busy signal and memory system including the same

A semiconductor memory device includes a plurality of memory cells; a peripheral circuit suitable for controlling the memory cells, and operating in first and second modes respectively corresponding to enablement and disablement of a chip selection signal; and a ready-busy signal generator suitable for biasing a ready-busy line according to whether the peripheral circuit is in a ready or busy state during the enablement of the chip selection signal. Communication between the semiconductor memory device and an external device is allowed in the first mode.
Sk Hynix Inc.

new patent

Bitline senseamplifier and semiconductor memory apparatus using the same

A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.. .
Sk Hynix Inc.

new patent

Semiconductor memory device and i/o control circuit therefor

An i/o control circuit, includes a mode setting unit configured to generate a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal in accordance with one of a plurality of i/o option modes, a first control signal generation unit configured to generate a first mode determination signal and a first control signal enable signal in response to the first i/o option signal and the first mode signal, and a second control signal generation unit configured to generate a second control signal enable signal, a third control signal enable signal, and a fourth control signal enable signal in response to a second i/o option signal, the first mode determination signal, the second mode signal, the third mode signal, and the fourth mode signal.. .
Sk Hynix Inc.



Semiconductor topics:
  • Semiconductor
  • Semiconductor Substrate
  • Semiconductor Device
  • Semiconductor Material
  • Electric Conversion
  • Conductive Layer
  • Molybdenum
  • Camera Module
  • Semiconductor Devices
  • Semiconductors
  • Integrated Circuit
  • Surfactant
  • Photoelectric Conversion
  • Electronic Device
  • Transparent Conductive Oxide


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