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Semiconductor patents

      

This page is updated frequently with new Semiconductor-related patent applications.




 Printed circuit board patent thumbnailPrinted circuit board
Disclosed is a printed circuit hoard. The printed circuit board includes a plurality of insulation layers and a plurality of pattern layers alternately stacked, the printed circuit board includes a plurality of device areas on which semiconductor packages are mounted and a peripheral area adjacent the device areas.
Samsung Electronics Co., Ltd.


 Backlight module with mjt led and backlight unit incluing the same patent thumbnailBacklight module with mjt led and backlight unit incluing the same
A backlight unit including a backlight module and a backlight control module. The backlight module includes a printed circuit board including blocks, and light emitting diode (led) chips disposed on the blocks, and the backlight control module is configured to perform a dimming control of the led chips.
Seoul Semiconductor Co., Ltd.


 Rgb-rwb dual images by multi-layer sensors towards better image quality patent thumbnailRgb-rwb dual images by multi-layer sensors towards better image quality
Using improved image signal processing (isp) along with a multi-layer color filter array (cfa) architecture to capture both the red-green-blue (rgb) as well as the red-x-blue (rxb) images substantially simultaneously on the same complementary metal oxide semiconductor (cmos) image sensor chip in a single shot so that subsequent image processing stage(s) can choose between rgb and rxb images to improve the quality of the final image. The color “x” in the rxb image may be a white color, a yellow color, or a cyan color.

 Pixel cell having a reset device with asymmetric conduction patent thumbnailPixel cell having a reset device with asymmetric conduction
Embodiments of the disclosure provide a solution to carry out high dynamic range (hdr) imaging based on dynamic well capacity adjustment without incurring additional spatial-temporal noise and consequent signal-to-noise ratio (snr) dips caused by the sub-threshold operation of a cmos (complementary metal-oxide-semiconductor) reset transistor in a pixel cell. Embodiments of the disclosure employ realizations of transistors other than cmos, e.g.

 Solid-state imaging element and camera system patent thumbnailSolid-state imaging element and camera system
A solid-state imaging element that includes a plurality of semiconductor layers stacked, a plurality of stack-connecting parts for electrically connecting the plurality of semiconductor layers, a pixel array part in which pixel cells that include a photoelectric conversion part and a signal output part are arrayed in a two-dimensional shape, and an output signal line through which signals from the signal output part of the pixel cells are propagated, in which the plurality of semiconductor layers includes at least a first semiconductor layer and a second semiconductor layer, and, in the first semiconductor layer, the plurality of pixel cells are arrayed in a two-dimensional shape, the signal output part of a pixel group formed with the plurality of pixel cells shares an output signal line wired from the stack-connecting parts, and the output signal line has a separation part which can separate each output signal line.. .
Sony Corporation


 Method and  secure energy delivery patent thumbnailMethod and secure energy delivery
A solar power conversion device embedded security module creates trusted metering data in relation to power generated and outputs it as metering data. The security module might be constructed as an ic card using semiconductor chip fabrication and assembly techniques integral with the solar power conversion device.
Trusted Renewables Limited


 Semiconductor device and communication system including the same patent thumbnailSemiconductor device and communication system including the same
Provided are a semiconductor device including a modulator for psk communication and a semiconductor device including a demodulator for psk communication, and a psk communication system. The semiconductor device includes a reference clock generator to generate a reference clock signal, a phase locked loop (pll) to receive the reference clock signal and generate a first clock signal, an integer divider circuit to generate a second clock signal by delaying a rising edge of the reference clock signal by a product of a predetermined integer value included in transmission data and a phase interval, and a processing unit to generate a first transmission signal.
Samsung Electronics Co., Ltd.


 Reconfigurable semiconductor device patent thumbnailReconfigurable semiconductor device
There is provided a reconfigurable semiconductor device including a plurality of logic units connected to each other using an address line or a data line, each logic unit including a plurality of address lines, a plurality of data lines, a clock signal line configured to receive a system clock signal, a delay element configured to delay the system clock signal, a memory cell unit configured to operate in synchronization with a clock signal, and an address decoder configured to decode an address signal to output the decoded signal to the memory cell unit. The logic unit configuring a combination logic circuit operates in synchronization with a delayed clock signal outputted from the delay element..
Taiyo Yuden Co., Ltd.


 Simplified gate driver for power transistors patent thumbnailSimplified gate driver for power transistors
A pulse-transformer-based isolated gate driver circuit uses a small count of high-temperature-qualified components to drive a power semiconductor switch with asymmetrical voltage biases. A differential driver generates a pulse signal from a pulse-width-modulated signal, which is passed to a charge and lock circuit through a transformer.
Halliburton Energy Services, Inc.


 Semiconductor module patent thumbnailSemiconductor module
In a semiconductor module, second semiconductor chips (e.g., diodes) are disposed closer to a laminated substrate than first semiconductor chips (mosfets). When a control signal supplied to gate electrodes of the first semiconductor chips (mosfets) is off, an electric current produced by a voltage from source terminals to a drain board mainly flows through the second semiconductor chips..
Fuji Electric Co., Ltd.


Bidirectional semiconductor switch with passive turnoff

A symmetrically-bidirectional bipolar transistor circuit where the two base contact regions are clamped, through a low-voltage diode and a resistive element, to avoid bringing either emitter junction to forward bias. This avoids bipolar gain in the off state, and thereby avoids reduction of the withstand voltage due to bipolar gain..
Ideal Power Inc.

Electronic circuit and semiconductor device

An electronic circuit includes a first level shift circuit, a second level shift circuit, an internal circuit, a high voltage circuit, first and second transistors, and first and second protective circuits. The first and second protective circuits perform control the first and second transistors so as to make them non-conductive when at least one of a plurality of types of power supply voltages becomes equal to or less than a predetermined value..
Hitachi, Ltd.

Semiconductor device

A semiconductor device includes a first circuit block that is connected between a first power supply voltage line and a first reference voltage line, a second circuit block that is connected between a second power supply voltage line and a second reference voltage line and transmits and receives signals with the first circuit block, a first clamp circuit that clamps a potential difference between the second power supply voltage line and the first reference voltage line, a resistor circuit that is connected between the second power supply voltage line and the second circuit block and includes a resistance value that is greater than an impedance of the first clamp circuit, and a second clamp circuit that clamps a potential difference between a line connected between the resistor circuit and the second circuit block and the first reference voltage line.. .
Renesas Electronics Corporation

Method of forming a semiconductor device and structure therefor

In one embodiment, a semiconductor device may include forming a first inverter and a second inverter to selectively receive separate inputs of a differential input signal and directly connecting each of the first and second inverters to receive power directly from a voltage input and a voltage return. The first inverter may be configured to include a first control switch that is configured to selectively couple together an upper transistor and a lower transistor of the first inverter.
Semiconductor Components Industries, Llc

Device for operating a rectifier, in particular a semi-controlled rectifier bridge, and operating a rectifier

In a device for operating a rectifier, in particular a semi-controlled rectifier bridge, and a method for operating a rectifier, in particular a power converter, the rectifier is supplied from system phases, in particular from a three-phase ac voltage system, and supplies a unipolar voltage on the output side, the rectifier including controllable switches, in particular semiconductor switches such as thyristors, etc., a respective system phase supplying a respective current source, the current generated in each case being used as trigger signal for the controllable switch allocated to the respective system phase as a function of the state of a controllable switch unit.. .
Sew-eurodrive Gmbh & Co. Kg

Converter module for converting electrical power and inverter for a photovoltaic system having at least two converter modules

A converter module for converting electrical power by means of a converter circuit having at least one power electronic semiconductor switch driven in a clocked manner is disclosed. The converter module includes a housing, a first dc link circuit terminal, and a capacitance arranged in the housing and connected to the first dc link circuit terminal and to the converter circuit and serving for stabilizing a dc voltage present at the first dc link circuit terminal.
Sma Solar Technology Ag

Optical amplifier

An optical amplifier is described. The optical amplifier (1) comprises a semiconductor disk gain medium (2) including at least one quantum well layer (9) and a pump field source (17) for generating an optical pump field (3) for the semiconductor disk gain medium.
Solus Technologies Limited

Contactor and wiring board

A contactor coupled to an electrode of a semiconductor package mounted on a mounting surface of a wiring board, the contactor includes: a cable including a core line; a connector attached to a front end of the cable, and to be inserted into a through hole that penetrates the wiring board in a thickness direction thereof; and a signal land formed on a front end surface of the connector, and electrically coupled with the core line.. .
Fujitsu Limited

Dual gate device and manufacturing method thereof

The embodiment of the disclosure discloses a method of manufacturing the dual gate device, comprising: forming a first metal layer on a substrate; patterning the first metal layer through a first mask to form a bottom gate electrode; coating a first organic isolation layer on the bottom gate electrode and the substrate; sputtering a second metal layer on the first organic isolation layer; patterning the second metal layer to form a source-drain electrode; disposing an organic semiconductor layer, a second organic isolation layer and a third metal layer sequentially on the source-drain electrode and the first organic isolation layer; and patterning the organic semiconductor layer, the second organic isolation layer and the third metal layer through a third mask to form a top gate electrode. The top gate electrode overlapping the source-drain electrode makes the dual gate device to reduce the device contact resistance and saves the power consumption..
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Shadow-effect compensated fabrication of magnetic tunnel junction (mtj) elements

Shadow-effect compensated fabrication of magnetic tunnel junction (mtj) semiconductor elements is disclosed. Providing shadow-effect compensated fabrication of mtj elements can provide reduced free layer sizing for enhanced mtj operational margin.
Qualcomm Incorporated

Devices using cavities to distribute conductive patterning residue and devices fabricated using the same

Methods of manufacturing a semiconductor device include forming a conductive layer on a substrate, forming an air gap or other cavity between the conductive layer and the substrate, and patterning the conductive layer to expose the air gap. The methods may further include forming conductive pillars between the substrate and the conductive layer.
Samsung Electronics Co., Ltd.

Semiconductor devices and semiconductor packages including magnetic shielding layers and methods of manufacturing semiconductor devices and semiconductor packages

A magnetic random-access memory (mram) device and a semiconductor package include a magnetic shielding layer that may suppress at least one of magnetic orientation errors and deterioration of magnetic tunnel junction (mtj) structures due to external magnetic fields. A semiconductor device includes: a mram chip including a mram; and a magnetic shielding layer including an upper shielding layer and a via shielding layer.

Optoelectronic semiconductor device with ferromagnetic domains

An optoelectronic semiconductor device with one or more ferromagnetic domains and method for processing an optoelectronic semiconductor device and/or devices with the ferromagnetic domain(s) is described. In one embodiment, the optoelectronic semiconductor device can include a semiconductor structure having a substrate, an n-type contact layer formed over the substrate, an active layer formed over the n-type contact layer, and a p-type contact layer formed over the active layer; and at least one ferromagnetic domain located on the semiconductor structure.
Sensor Electronic Technology, Inc.

Light-emitting device

A light-emitting device, including a substrate; a plurality of light-emitting units formed on the substrate, wherein the plurality of light-emitting units include a first light-emitting unit; a second light-emitting unit; and a group of light-emitting units formed between the first light-emitting unit and the second light-emitting unit, wherein each of the plurality of light-emitting unit includes a first-type semiconductor layer, a second-type semiconductor layer and an active layer formed between the first-type semiconductor layer and the second-type semiconductor layer; a plurality of electrical connections formed on the plurality of light-emitting units, electrically connecting each two of the light-emitting units adjacent; a first pad formed on the first light-emitting unit; a second pad and a third pad formed on the second light-emitting unit; wherein one of the plurality of electrical connection connects and extends from the second pad.. .
Epistar Corporation

Light emitting device on a mount with a reflective layer

Embodiments of the invention include a semiconductor light emitting diode (led) attached to a top surface of a mount. A multi-layer reflector is disposed on the top surface of the mount adjacent to the led.
Koninklijke Philips N.v.

Optoelectronic device and producing an optoelectronic device

An optoelectronic component (100) comprises an optoelectronic semiconductor chip (10), a first contact area (31) and a second contact area (32), which is laterally offset with respect to the first contact area and is electrically insulated therefrom, and a housing element (40). The first contact area (31) is electrically conductively connected to the first semiconductor layer (21) and the second contact area (32) is electrically conductively connected to the second semiconductor layer (22) of the optoelectronic semiconductor chip.
Osram Opto Semiconductors Gmbh

Semiconductor light emitting structure

A semiconductor light emitting structure includes a first type semiconductor layer, an active layer, a second type semiconductor layer, an electrode, a transparent conductive layer, a bragg reflective layer and a metal layer. The first type semiconductor layer, the active layer and the second type semiconductor layer are stacked sequentially to form an epitaxy layer.
Lextar Electronics Corporation

Light emitting diode chip having electrode pad

Disclosed herein is an led chip including electrode pads. The led chip includes a semiconductor stack including a first conductive type semiconductor layer, a second conductive type semiconductor layer on the first conductive type semiconductor layer, and an active layer interposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer; a first electrode pad located on the second conductive type semiconductor layer opposite to the first conductive type semiconductor layer; a first electrode extension extending from the first electrode pad and connected to the first conductive type semiconductor layer; a second electrode pad electrically connected to the second conductive type semiconductor layer; and an insulation layer interposed between the first electrode pad and the second conductive type semiconductor layer.
Seoul Viosys Co., Ltd.

Nitride semiconductor device and producing the same

A method for producing a nitride semiconductor device. The method comprises providing a substrate made of a material other than a nitride semiconductor.
Nichia Corporation

Semiconductor modification process and structures

There is herein described a process for providing improved device performance and fabrication techniques for semiconductors. More particularly, the present invention relates to a process for forming features, such as pixels, on gan semiconductors using a p-gan modification and annealing process.
Mled Limited

Semiconductor optical device and display device

A semiconductor optical device includes: a ridge stripe structure portion 20 in which a first compound semiconductor layer 31, an active layer 32, and a second compound semiconductor layer 32 are stacked and which has a first end surface 21 which emits light and a second end surface 22 opposite to the first end surface 21; and a current regulation region 41 provided to be adjacent to at least one of ridge stripe adjacent portions 40 positioned at both sides of the ridge stripe structure portion 20, at the second end surface side, and to be away from the ridge stripe structure portion 20. A bottom surface of the current regulation region 41 is under the active layer 33, and a top surface of the ridge stripe adjacent portion 40 excluding the current regulation region 41 is above the active layer 33..
Sony Corporation

Method for producing a semiconductor layer sequence

A method for producing a semiconductor layer sequence is disclosed. In an embodiment the includes growing a first nitridic semiconductor layer at the growth side of a growth substrate, growing a second nitridic semiconductor layer having at least one opening on the first nitridic semiconductor layer, removing at least pail of the first nitridic semiconductor layer through the at least one opening in the second nitridic semiconductor layer, growing a third nitridic semiconductor layer on the second nitridic semiconductor layer, wherein the third nitridic semiconductor layer covers the at least one opening at least in places in such a way that at least one cavity free of a semiconductor material is present between the growth substrate and a subsequent semiconductor layers and removing the growth substrate..
Osram Opto Semiconductors Gmbh

Light-emitting device

A light-emitting device comprises a first light-emitting semiconductor stack comprising a first active layer; a second light-emitting semiconductor stack below the first light-emitting semiconductor stack, wherein the second light-emitting semiconductor stack comprises a second active layer; a wavelength filter between the first light-emitting semiconductor stack and the second light-emitting semiconductor stack; a protecting layer between the wavelength filter and the second light-emitting semiconductor stack; and wherein the first light-emitting semiconductor stack further comprises a first semiconductor layer and a second semiconductor layer sandwiching the first active layer, the second light-emitting semiconductor stack further comprises a third semiconductor layer and a fourth semiconductor layer sandwiching the second active layer, wherein the second semiconductor layer has a first band gap, the third semiconductor layer has a second band gap, and the protecting layer has a third band gap between the first band gap and the second band gap.. .
Epistar Corporation

Light-emitting metal-oxide-semiconductor devices and associated systems, devices, and methods

Various embodiments of solid state transducer (“sst”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (mos) capacitor, an active region operably coupled to the mos capacitor, and a bulk semiconductor material operably coupled to the active region.
Micron Technology, Inc.

Method and equipment for treating a precursor of a heterojunction photovoltaic cell and associated producing a photovoltaic cell

The precursor comprises at least one layer of doped crystalline silicon and a layer of doped amorphous semiconductor material. The method comprises the steps of placing the cell precursor sandwiched between a grounded conducting plate and a plate made of insulating material coated with a conducting layer, then applying a state change electrical voltage (u1) between the conducting layer and ground, the said state change electrical voltage (u1) being designed to bring the fermi level at the interface between crystalline silicon and amorphous semiconductor material closer to the middle of the band gap of the said amorphous semiconductor material, while at the same time heating the cell precursor to a defect equilibration temperature (te), and finally cooling down the cell precursor (10) prior to interrupting the application of the state change electrical voltage (u1)..
Commissariat A L'energie Atomique Et Aux Energies Alternatives

Thin-film semiconductor optoelectronic device with textured front and/or back surface prepared from template layer and etching

A method for providing a textured layer in an optoelectronic device is disclosed. The method includes depositing a template layer on a first layer.
Alta Devices, Inc.

Proximity sensor having light-blocking structure in leadframe and making same

A method for fabricating a semiconductor proximity sensor includes providing a flat leadframe with a first and a second surface. The second surface is solderable.
Texas Instruments Incorporated

Inverted metamorphic multijunction solar cell with a single metamorphic layer

The present disclosure provides a multijunction solar cell that includes: a first sequence of layers of semiconductor material forming a first set of one or more solar subcells; a graded interlayer adjacent to said first sequence of layers; a second sequence of layers of semiconductor material forming a second set of one or more solar subcells; and a high band gap contact layer adjacent said second sequence of layers, wherein the high band gap contact layer is composed of p++ type ingaalas or ingaas.. .
Solaero Technologies Corp.

Solar cell and manufacturing the same

A solar cell and a method for manufacturing the same are disclosed. The method for manufacturing the solar cell includes injecting impurities of a second conductive type opposite a first conductive type into an entire first surface of a semiconductor substrate containing impurities of the first conductive type, the semiconductor substrate having the first surface, a side surface, and a second surface opposite the first surface, forming a doping barrier layer on the entire first surface and the entire side surface of the semiconductor substrate, and at an edge portion of the second surface of the semiconductor substrate, injecting the impurities of the first conductive type into the second surface of the semiconductor substrate at which the doping barrier layer is not formed, at a higher concentration than the semiconductor substrate, performing a thermal process on the semiconductor substrate to simultaneously form an emitter region of the second conductive type at the entire first and side surfaces of the semiconductor substrate and a back surface field region of the first conductive type at the second surface of the semiconductor substrate, and removing the doping barrier layer..
Lg Electronics Inc.

Photovoltaic module

A photovoltaic module capable of suppressing separation of a tab electrode can be obtained. The photovoltaic module includes a plurality of semiconductor layers including a photoelectric conversion layer, a plurality of photovoltaic elements including a finger electrode for collecting generated currents, formed on the semiconductor layers on a side of a light receiving surface, and a tab electrode for electrically connecting the plurality of photovoltaic elements, in which the tab electrode is electrically connected to the finger electrode in a region corresponding to a power generation region of the photovoltaic element and bonded on the light receiving surface through an insulating bonding material..
Panasonic Intellectual Property Management Co., Ltd.

Tunnel barrier schottky

A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (algan) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.. .
Hrl Laboratories, Llc

Transistor, clocked inverter circuit, sequential circuit, and semiconductor device including sequential circuit

A transistor with excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) is provided. The transistor includes an oxide semiconductor layer including a channel formation region, a first gate electrode, a second gate electrode, a source electrode, and a drain electrode.
Semiconductor Energy Laboratory Co., Ltd.

Optical sensor element and photoelectric conversion device

Two gate electrodes are provided on upper and lower sides of an oxide semiconductor active layer through respective insulating films. In addition, a first read-out electrode and a second read-out electrode are provided on right and left sides of the oxide semiconductor active layer.
Nlt Technologies, Ltd.

Charge carrier transport facilitated by strain

A semiconductor structure and formation thereof. The semiconductor structure has a first semiconductor layer with a first lattice structure and a second epitaxial semiconductor layer that is lattice-matched with the first semiconductor layer.
International Business Machines Corporation

Semiconductor device and fabricating the same

A semiconductor device and a method of fabricating the same, the semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure is disposed on the silicon substrate and includes a silicon germanium (sige) layer extending downwardly from a top end and at least occupying 80% to 90% of the fin shaped structure.
United Microelectronics Corp.

Hybrid substrate engineering in cmos finfet integration for mobility improvement

A method for forming a hybrid complementary metal oxide semiconductor (cmos) device includes orienting a semiconductor layer of a semiconductor-on-insulator (soi) substrate with a base substrate of the soi, exposing the base substrate in an n-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region.
International Business Machines Corporation

Semiconductor device and manufacturing semiconductor device

A second electrode provided on the third semiconductor region and on the second insulating portion, and arranged. With the second portion in the second direction..

Semiconductor device comprising a transistor cell including a source contact in a trench, manufacturing the semiconductor device and integrated circuit

A semiconductor device is provided including a transistor cell in a semiconductor substrate having a first main surface. The transistor cell includes a gate electrode in a gate trench in the first main surface adjacent to a body region.
Infineon Technologies Dresden Gmbh

Semiconductor device

A semiconductor device includes a first conductivity type semiconductor layer, a second conductivity type body region in a semiconductor layer surface portion, a first conductivity type source region in a body region surface, apart from a peripheral edge of the body region, a first conductivity type drain region in the semiconductor layer surface portion apart from the body region, a gate electrode opposing the body region across a gate insulating film between the source and drain regions, an insulating layer on the semiconductor layer, resin on the insulating layer, a source electrode in the insulating layer, electrically connected to the source region, a drain electrode in the insulating layer, electrically connected to the drain region, and conductive shielding in the insulating layer, overlapping in a plan view from a direction normal to a semiconductor layer surface, the drain region and the gate electrode, and covering a region between them.. .
Rohm Co., Ltd.

Semiconductor device and manufacturing the same

A semiconductor device according to the present invention includes a semiconductor layer provided with a gate trench, a first conductivity type source region formed to be exposed on a surface side of the semiconductor layer, a second conductivity type channel region formed on a side of the source region closer to a back surface of the semiconductor layer to be in contact with the source region, a first conductivity type drain region formed on a side of the channel region closer to the back surface of the semiconductor layer to be in contact with the channel region, a gate insulating film formed on an inner surface of the gate trench, and a gate electrode embedded inside the gate insulating film in the gate trench, while the channel region includes a channel portion formed along the side surface of the gate trench so that a channel is formed in operation and a projection projecting from an end portion of the channel portion closer to the back surface of the semiconductor layer toward the back surface.. .
Rohm Co., Ltd.

Semiconductor device

A semiconductor device according to embodiments includes, a sic substrate, sic layer, a trench having a side face and a bottom face, a first conductivity type first sic region, a second conductivity type second sic region between the first sic region and the sic substrate, a first conductivity type third sic region between the second sic region and the sic substrate, a boundary between the second sic region and the third sic region provided at a side of the side face, the boundary including a first region, a distance between the first region and a front face of the sic layer increasing as a distance from the side face to the first region increasing, and distance from the side face to the first region being 0 μm or more and 0.3 μm or less, a gate insulating film and gate insulating film.. .
Kabushiki Kaisha Toshiba

Semiconductor device and a manufacturing method thereof

The characteristics of a semiconductor device are improved. A semiconductor device has an impurity-containing potential fixed layer, and a gate electrode.
Renesas Electronics Corporation

Method for making thim film transistor

A method for making a thin film transistor includes a step of forming a semiconducting layer, a source electrode, a drain electrode, a gate electrode, and an insulating layer on an insulating substrate. A process of forming the semiconducting layer comprises a step of sputtering an oxide semiconductor film on a substrate by using a sputtering target comprising in2cexzno4+2x, wherein x=0.5˜2..
Hon Hai Precision Industry Co., Ltd.

Semiconductor device, manufacturing method thereof, and display device including the semiconductor device

The transistor includes a gate electrode, a gate insulating film over the gate electrode, an oxide semiconductor film over the gate insulating film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film on the gate electrode side and a second oxide semiconductor film over the first oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.

Thin film transistor substrate and fabricating the same

A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the gate electrode and includes an oxide semiconductor material; and a source electrode and a drain electrode disposed on the semiconductor layer, where the drain electrode is spaced apart from the source electrode. The source electrode and the drain electrode each include a barrier layer and a main wiring layer, the a main wiring layer is disposed on the barrier layer, and the barrier layer includes a first metal layer disposed on the semiconductor layer, and a second metal layer disposed on the first metal layer..
Samsung Display Co., Ltd.

Semiconductor device and fabricating the same

A semiconductor device includes a semiconductor substrate comprising a group iii element and a group v element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region.
Seoul National University R&db Foundation

Integrated circuit structure with substrate isolation and un-doped channel

The present disclosure provides a method of fabricating a nonplanar circuit device. The method includes receiving a substrate having a first semiconductor layer of a first semiconductor material and a second semiconductor layer of a second semiconductor material on the first semiconductor layer, wherein the second semiconductor material is different from the first semiconductor material in composition.
Taiwan Semiconductor Manufacturing Company, Ltd.

Asymmetric semiconductor device

A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region.
Taiwan Semiconductor Manufacturing Company Limited

Method for producing semiconductor device

A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer; a second step of forming a first pillar-shaped semiconductor layer, a first dummy gate, a second pillar-shaped semiconductor layer, and a second dummy gate; a third step of forming a third dummy gate and a fourth dummy gate; a fourth step of forming a third diffusion layer in an upper portion of the fin-shaped semiconductor layer, in a lower portion of the first pillar-shaped semiconductor layer, and in a lower portion of the second pillar-shaped semiconductor layer; a fifth step of forming a gate electrode and a gate line around the first pillar-shaped semiconductor layer and forming a contact electrode and a contact line around the second pillar-shaped semiconductor layer; and a sixth step of forming first to fifth contacts.. .
Unisantis Electronics Singapore Pte. Ltd.

Method for fabricating semiconductor device

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a spacer is formed around the gate structure, and an epitaxial layer is formed in the substrate adjacent to the spacer.
United Microelectronics Corp.

Complementary metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect transistor and manufacturing method thereof

A complementary metal oxide semiconductor field-effect transistor (mosfet) includes a substrate, a first mosfet and a second mosfet. The first mosfet is disposed on the substrate within a first transistor region and the second mosfet is disposed on the substrate within a second transistor region.
United Microelectronics Corp.

Growing groups iii-v lateral nanowire channels

In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the <111> direction of the silicon.
International Business Machines Corporation

Method for manufacturing vertically integrated semiconductor device

A vertically integrated semiconductor device in accordance with various embodiments may include: a first semiconducting layer; a second semiconducting layer disposed over the first semiconducting layer; a third semiconducting layer disposed over the second semiconducting layer; and an electrical bypass coupled between the first semiconducting layer and the second semiconducting layer.. .
Infineon Technologies Ag

Semiconductor device and a fabrication method thereof

A semiconductor device includes a substrate, gate electrodes, spacers and contact structures. The gate electrodes are disposed on the substrate, and the spacers are disposed on the sidewalls of the gate electrodes.
United Microelectronics Corp.

Semiconductor device having dual work function gate structure, fabricating the same, transistor circuit having the same, memory cell having the same, and electronic device having the same

A semiconductor device including a substrate in which a trench is formed, a first impurity region and a second impurity region formed in the substrate separated from each other by the trench, a gate electrode formed to fill a lower part of the trench, and a capping layer formed over the gate electrode to fill an upper part of the trench. The gate electrode includes a first work function liner formed over a bottom surface and sidewalls of the lower part of the trench without overlapping with the first impurity region and the second impurity region, and including an aluminum-containing metal nitride; and a second work function liner formed over the sidewalls of the lower part of the trench over the first work function liner, overlapping with the first impurity region and the second impurity region, and including a silicon-containing non-metal material..
Sk Hynix Inc.

Barrier layer for dielectric layers in semiconductor devices

A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device

A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and a second pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A metal contact electrode is around the second pillar-shaped semiconductor layer, and a metal contact line is connected to the metal contact electrode.
Unisantis Electronics Singapore Pte. Ltd.

Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates

Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate.

Silicon carbide semiconductor device and manufacturing same

A silicon carbide semiconductor device includes a silicon carbide substrate, a gate oxide film, and a gate electrode. A trench is provided in the main surface to have a side surface and a bottom portion.
Sumitomo Electric Industries, Ltd.

Semiconductor device and manufacturing the same

A semiconductor device with enhanced reliability in which a gate electrode for a trench-gate field effect transistor is formed through a gate insulating film in a trench made in a semiconductor substrate. The upper surface of the gate electrode is in a lower position than the upper surface of the semiconductor substrate in an area adjacent to the trench.
Renesas Electronics Corporation

Nitride semiconductor device

A nitride semiconductor device according to the present invention includes a nitride semiconductor layer including an electron transit layer and an electron supply layer which is in contact with the electron transit layer and which has a composition different from that of the electron transit layer, a gate electrode on the nitride semiconductor layer and a gate insulating film between the gate electrode and the nitride semiconductor layer. A region whose depth is 250 nm from an interface between the gate insulating film and the gate electrode includes a region which has a deep acceptor concentration equal to or more than 1.0×1016 cm−3..
Rohm Co., Ltd.

Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins

A method of making a semiconductor device includes forming a fin in a substrate; depositing a first spacer material to form a first spacer around the fin; depositing a second spacer material to form a second spacer over the first spacer; recessing the first spacer and the second spacer; removing the first spacer; and performing an epitaxial growth process to form epitaxial growth on an end of the fin, along a sidewall of the fin, and adjacent to the fin.. .
Globalfoundries, Inc.

Nitride semiconductor device

A nitride semiconductor device includes: a nitride semiconductor layer; a gate electrode finger having at least one end portion, and extending along a surface of the nitride semiconductor layer; and a drain electrode finger having at least one end portion on the same side as that of the one end portion of the gate electrode finger, and extending along the gate electrode finger, wherein the one end portion of the drain electrode finger protrudes relative to the one end portion of the gate electrode finger.. .
Rohm Co., Ltd.

Semiconductor device and manufacturing semiconductor device

In a semiconductor device (misfet) having a gate electrode formed over a nitride semiconductor layer with a gate insulating film interposed therebetween, the gate insulating film includes a first gate insulating film (oxide film of first metal) formed on the nitride semiconductor layer and a second gate insulating film (oxide film of second metal). The second metal (for example, hf) has electronegativity lower than that of the first metal (for example, al).
Renesas Electronics Corporation

Method of manufacturing silicon carbide semiconductor device

A method of manufacturing a silicon carbide semiconductor device. The method includes providing an n-type semiconductor substrate having first and second principal surfaces, introducing an impurity from a first principal surface of the semiconductor substrate at a first position, activating the impurity to form a diffusion layer in the semiconductor substrate at a second position, implanting protons at a third position that is deeper from the first principal surface than the first position, the protons generating crystal defects in a region through which the protons pass, converting by thermal treating the protons into hydrogen induced donors to form an n-type field stop layer at a fourth position deeper from the first principal surface than the second position, reducing by the thermal treating the generated crystal defects to form an n-type crystal defect reduction region, and forming an electrode on the second principal surface after implanting the protons..
Fuji Electric Co., Ltd.

Semiconductor material having a compositionally-graded transition layer

The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer.
Infineon Technologies Americas Corp.

Uniaxially strained nanowire structure

Uniaxially strained nanowire structures are described. For example, a semiconductor device includes a plurality of vertically stacked uniaxially strained nanowires disposed above a substrate.

Semiconductor structure with multilayer iii-v heterostructures

The source/drain of a fully iii-v semiconductor or si-based transistor includes a bottom barrier layer that may be lattice matched to the channel, a lower layer of a wide bandgap iii-v material and a top layer of a comparatively narrow bandgap iii-v material, with a compositionally graded layer between the lower layer and top layer gradually transitioning from the wide bandgap material to the narrow bandgap material.. .
Globalfoundries Inc.

Semiconductor device and manufacturing the same

An element isolation portion includes a projection portion that projects from an soi substrate and comes into contact with a piled-up layer. The height of the upper surface of the projection portion is configured to be lower than or equal to the height of the upper surface of the piled-up layer and higher than or equal to a half of the height of the upper surface of the piled-up layer with reference to a surface of a silicon layer of the soi substrate..
Renesas Electronics Corporation

Semiconductor device including nanowire transistor

A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire.
Samsung Electronics Co., Ltd.

Semiconductor devices with germanium-rich active layers and doped transition layers

semiconductor device stacks and devices made there from having ge-rich device layers. A ge-rich device layer is disposed above a substrate, with a p-type doped ge etch suppression layer (e.g., p-type sige) disposed there between to suppress etch of the ge-rich device layer during removal of a sacrificial semiconductor layer richer in si than the device layer.
Intel Corporation

Integration methods to fabricate internal spacers for nanowire devices

A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack.
Intel Corporation

Growing groups iii-v lateral nanowire channels

In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the <111> direction of the silicon.
International Business Machines Corporation

Electronic component and manufacturing method thereof

The electronic component includes a semiconductor substrate, a first doped region, a second doped region, a gate structure, a dielectric layer and a conductive portion. The semiconductor substrate has an upper surface.
Mediatek Inc.

Power semiconductor devices having superjunction structures with implanted sidewalls and methods of fabricating such devices

A semiconductor device has a drift region having an upper surface and a lower surface. A first contact is on the upper surface of the drift region and a second contact is on the lower surface of the drift region.
Cree, Inc.

Silicon carbide semiconductor device and manufacturing silicon carbide semiconductor device

In a silicon carbide semiconductor device, a trench penetrates a source region and a first gate region and reaches a drift layer. On an inner wall of the trench, a channel layer of a first conductivity-type is formed by epitaxial growth.
Denso Corporation

Display tile structure and tiled display

A display tile structure includes a tile layer with opposing emitter and backplane sides. A light emitter having first and second electrodes for conducting electrical current to cause the light emitter to emit light is disposed in the tile layer.
X-celeprint Limited

Organic light emitting diode display and manufacturing method thereof

An organic light emitting diode display comprises a substrate including a display area in which a pixel is disposed and a peripheral area surrounding the display area, a driving semiconductor layer disposed in the display area on the substrate, a driving gate electrode disposed in the display area on the driving semiconductor layer, a common voltage line disposed in the peripheral area on the substrate and disposed on a same layer as the driving gate electrode, a gate electrode anti-oxidation layer disposed on the driving gate electrode, a common voltage line anti-oxidation layer disposed on the common voltage line, an interlayer insulating layer disposed on the driving semiconductor layer, the driving gate electrode, the common voltage line, the gate electrode anti-oxidation layer, and the common voltage line anti-oxidation layer. A driving source electrode and a driving drain electrode are disposed in the display area on the interlayer insulating layer, and a common voltage applying electrode is disposed in the peripheral area on the interlayer insulating layer and on the same layer as the driving source electrode and the driving drain electrode..
Samsung Display Co., Ltd.

Memory device and manufacturing the same

A memory device is provided. The memory device includes a substrate, a plurality of alternately stacked semiconductor layers and oxide layers disposed on the substrate, at least one through hole penetrating the stacked semiconductor layers and oxide layers, and an electrode layer disposed in the through hole.
Macronix International Co., Ltd.

Semiconductor storage device

A semiconductor storage device includes: a semiconductor substrate; a first storage unit; a second storage unit including a plurality of the first storage units formed in a first direction parallel to the semiconductor substrate; a third storage unit including a plurality of the second storage units formed in a second direction perpendicular to the first direction and parallel to the semiconductor substrate; and a fourth storage unit including a plurality of the third storage units in a third direction perpendicular to the semiconductor substrate. A plurality of contacts coupling signal lines each configured to select an address in the second direction and the semiconductor substrate, is arranged in a region in which no interference with bit lines extending in the first direction occurs.
Hitachi, Ltd.

Method for reducing crosstalk in cmos image sensor

A method of manufacturing a cmos image sensor includes providing a semiconductor substrate having a front side and a back side, forming at least two pixels in the front side, forming a shallow trench isolation in the front side between the at least two pixels, forming a deep trench in the back side at a location above the shallow trench isolation, and depositing a dielectric layer in the deep trench to form a crosstalk reduction element.. .
Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor photomultiplier

The present disclosure relates to a semiconductor photomultiplier comprising a a substrate; an array of photosensitive elements formed on a first major surface of the substrate; a plurality of primary bus lines interconnecting the photosensitive elements; at least one segmented secondary bus line provided on a second major surface of the substrate which is operably coupled to one or more terminals; and multiple vertical interconnect access (via) extending through the substrate operably coupling the primary bus lines to the at least one segmented secondary bus line.. .
Sensl Technologies Ltd

Cmos image sensor with peninsular ground contracts and manufacturing the same

A complementary metal oxide semiconductor (cmos) image sensor with peninsular ground contacts includes (a) a substrate having a plurality of pixel units arranged in rows of pixel units and (b) a plurality of ground contacts for grounding the pixel units, wherein the ground contacts are formed in respective peninsular regions of the substrate within respective ones of the pixel units, and wherein each of the peninsular regions is only partly enclosed by a shallow trench isolation and the peninsular regions have alternating orientation along each of the rows of pixel units.. .
Omnivision Technologies, Inc.

Semiconductor apparatus, manufacturing semiconductor apparatus, designing semiconductor apparatus, and electronic apparatus

A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.. .
Sony Corporation

Imaging device and manufacturing the same

In an imaging device having a waveguide, a surface of an insulating film covering a seal ring is prevented from getting rough. A pixel region, a peripheral circuit region, and a seal region are defined over a semiconductor substrate.
Renesas Electronics Corporation

Image sensors with light channeling reflective layers therein

An image sensor includes a two-dimensional array of image sensor pixels, which are formed in a semiconductor layer. Each image sensor pixel is formed in a substrate having a corresponding semiconductor region therein.
Samsung Electronics Co., Ltd.

Solid-state imaging device and manufacturing solid-state imaging device, and electronic device

A solid-state imaging device includes a first-conductivity-type semiconductor well region, a plurality of pixels each of which is formed on the semiconductor well region and is composed of a photoelectric conversion portion and a pixel transistor, an element isolation region provided between the pixels and in the pixels, and an element isolation region being free from an insulation film and being provided between desired pixel transistors.. .
Sony Corporation

Display apparatus and manufacturing the same

A display apparatus includes a substrate and a plurality of pixels disposed on the substrate. Each pixel includes a gate electrode on the substrate, a common electrode insulated from the gate electrode on the substrate, a first insulating layer covering the gate electrode and the common electrode, a semiconductor pattern disposed on the first insulating layer to overlap with the gate electrode, source and drain electrodes disposed on the semiconductor pattern and spaced apart from each other, and a pixel electrode disposed on the first insulating layer to cover the drain electrode and form an electric field with the common electrode.
Samsung Display Co., Ltd.

Semiconductor device and manufacturing method thereof

It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and peeling off method and manufacturing semiconductor device

The present invention provides a peeling off method without giving damage to the peeled off layer, and aims at being capable of peeling off not only a peeled off layer having a small area but also a peeled off layer having a large area over the entire surface at excellent yield ratio. The metal layer or nitride layer 11 is provided on the substrate, and further, the oxide layer 12 being contact with the foregoing metal layer or nitride layer 11 is provided, and furthermore, if the lamination film formation or the heat processing of 500° c.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and display device including the semiconductor device

A semiconductor device including a transistor and a connection portion is provided. The transistor includes a gate electrode, a first insulating film over the gate electrode, an oxide semiconductor film over the first insulating film and at a position overlapping with the gate electrode, and source and drain electrodes electrically connected to the oxide semiconductor film; and the connection portion includes a first wiring on the same surface as a surface on which the gate electrode is formed, a second wiring on the same surface as a surface on which the source and drain electrodes are formed, and a third wiring connecting the first wiring and the second wiring.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and display device

A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch.
Semiconductor Energy Laboratory Co., Ltd.

Structure and method to form a finfet device

A method for fabricating a finfet device includes forming a silicon-on-insulator (soi) substrate having a semiconductor layer overlaying a buried oxide (box) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the box layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.. .
Globalfoundries Inc.

Display device

Even when a light shielding film is provided between a transistor and a substrate, a threshold voltage of the transistor can be prevented or suppressed from being shifted. A display device includes light shielding films provided between a substrate and a semiconductor layer of a transistor including a gate electrode and the semiconductor layer.
Japan Display Inc.

Semiconductor device with self-aligned back side features

Various methods and devices that involve self-aligned features on a semiconductor on insulator process are provided. An exemplary method comprises forming a gate on a semiconductor on insulator wafer.
Qualcomm Incorporated

Semiconductor devices

A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.. .
Samsung Electronics Co., Ltd.

Three-dimensional semiconductor memory device

Provided is a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The horizontal semiconductor layer may include a first semiconductor layer disposed on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration, and a second semiconductor layer disposed on the first semiconductor layer and doped with first conductivity type impurities of a second impurity concentration lower than the first impurity concentration or undoped..

Semiconductor device having channel holes

A semiconductor device includes a gate stack including gate electrodes stacked vertically on a substrate. Channel holes penetrate through the gate stack to extend vertically to the substrate.

Semiconductor device and manufacturing same

According to one embodiment, the electrode films are stacked with gaps interposed between the electrode films. The first insulating film is provided between a lowermost electrode film of the electrode films and the substrate and being a metal oxide film, a silicon carbide film, or a silicon carbonitride film.
Kabushiki Kaisha Toshiba

3 - d semiconductor device and manufacturing the same

A 3-d semiconductor device comprising a plurality of memory cells and a plurality of selection transistors, each of said plurality of memory cells comprises: a channel layer, distributed along a direction perpendicular to the substrate surface; a plurality of inter-layer insulating layers and a plurality of gate stack structures, alternately laminating along the sidewall of the channel layer; a plurality of floating gates, located between the plurality of inter-layer insulating layers and the sidewall of the channel layer; a plurality of drains, located at the top of the channel layer; and a plurality of sources, located in the said substrate between two adjacent memory cells of the said plurality of memory cells.. .
Institute Of Microelectronics, Chinese Academy Of Sciences

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes, forming a first insulating film over the plurality of gate electrodes such that the first insulating film is embedded in a space between the plurality of gate electrodes, forming a second insulating film over the first insulating film, forming a third insulating film over the second insulating film, forming a photosensitive pattern over the third insulating film, performing etching using the photosensitive pattern as a mask to form a trench extending through the first to third insulating films and reaching a semiconductor substrate, removing the photosensitive pattern, performing etching using the exposed third insulating film as a mask to extend the trench in the semiconductor substrate, removing the third and second insulating films, and forming a fourth insulating film in the trench and over the first insulating film.. .
Renesas Electronics Corporation

Nonvolatile semiconductor memory device and manufacturing the same

A nonvolatile semiconductor memory device according to an embodiment comprises: a silicon substrate; and a plurality of memory cells that nonvolatilely accumulate a charge as data, disposed along at least a first direction, on the substrate. A diffusion layer is disposed continuously in a surface of the substrate of a region straddling the plurality of memory cells disposed along the first direction.
Kabushiki Kaisha Toshiba

Semiconductor structure including a nonvolatile memory cell and the formation thereof

A semiconductor structure includes a nonvolatile memory cell including a source region, a channel region and a drain region that are provided in a semiconductor material. The channel region includes a first portion adjacent the source region and a second portion between the first portion of the channel region and the drain region.
Globalfoundries Inc.

Semiconductor device and manufacturing the same

The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line.
Samsung Electronics Co., Ltd.

Semiconductor integrated circuit device

In an image information chip or the like, a multi-port sram is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port.
Renesas Electronics Corporation

Hybrid substrate engineering in cmos finfet integration for mobility improvement

A method for forming a hybrid complementary metal oxide semiconductor (cmos) device includes orienting a semiconductor layer of a semiconductor-on-insulator (soi) substrate with a base substrate of the soi, exposing the base substrate in an n-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region.
International Business Machines Corporation

Semiconductor device having metal gate

A semiconductor device having metal gate includes a first metal gate structure and a second metal gate structure disposed in a first device region and in a second device region on a substrate respectively. The first metal gate structure includes a gate insulating layer, a first bottom barrier layer, a top barrier layer, and a metal layer disposed on the substrate in order, wherein the top barrier layer is directly in contact with the first bottom barrier layer.
United Microelectronics Corp.

Semiconductor device with surrounding gate transistors in a nand circuit

A semiconductor device employs surrounding gate transistors (sgts) which are vertical transistors to constitute a cmos nand circuit. The nand circuit is formed by using a plurality of mos transistors arranged in m rows and n columns.
Unisantis Electronics Singapore Pte. Ltd.

Finfet with reduced capacitance

A structure including a plurality of fins etched from a semiconductor substrate, a gate electrode above and perpendicular to the plurality of fins, a pair of sidewall spacers disposed on opposing sides of the gate electrode, a gap fill material above the semiconductor substrate and between the plurality of fins, the gap fill material is directly below the gate electrode and directly below the pair of sidewall spacers, wherein the gate electrode separates the gap fill material from each of the plurality of fins, and an epitaxially grown region above a portion of the plurality of fins not covered by the gate electrode, the epi region separates the gap fill material from each of the plurality of fins.. .
International Business Machines Corporation

Semiconductor device

A semiconductor device includes a substrate including a first trench, a first fin pattern on the substrate that is defined by the first trench, a gate electrode on the substrate, and a field insulating layer on the substrate. The first fin pattern includes an upper part on a lower part.
Samsung Electronics Co., Ltd.

Selective contact etch for unmerged epitaxial source/drain regions

A semiconductor structure includes a plurality of semiconductor material fins located on a surface of a substrate. At least one gate structure straddles over a portion of each semiconductor material fin.
International Business Machines Corporation

Semiconductor device and manufacturing semiconductor device

A semiconductor device, including a semiconductor substrate, a plurality of trenches formed on a front surface of the semiconductor substrate, a plurality of gate electrodes formed in the trenches, a base region and an anode region formed between adjacent trenches respectively in first and second element regions of the semiconductor substrate, a plurality of emitter regions and contact regions selectively formed in the base region, an interlayer insulating film covering the gate electrodes, first and second contact holes penetrating the interlayer insulating film, a plurality of contact plugs embedded in the first contact holes, a first electrode contacting the contact plugs and contacting the anode region via the second contact hole, a collector region and a cathode region formed on a back surface of the semiconductor substrate respectively in the first and second element regions, and a second electrode contacting the collector region and the cathode region.. .
Fuji Electric Co., Ltd.

Semiconductor device and manufacturing the same

A semiconductor device includes a drift layer of a first conductivity-type, having a superjunction structure, including a plurality of columns of a second conductivity-type, a plane pattern of each of the columns extends along a parallel direction to the principal surface of the layer, the columns are arranged at regular intervals; a plurality of well regions of the second conductivity-type provided in a surface-side layer of the layer of the first conductivity-type; a plurality of source regions of the first conductivity-type selectively provided in the plurality of well regions; a gate insulating film provided on the principal surface; an array of gate electrodes disposed on the gate insulating film, each of the gate electrodes is provided so as to bridge the corresponding source regions in a pair of neighboring two well regions; and a temperature detection diode provided at a partial area defined in the array of the gate electrodes.. .
Fuji Electric Co., Ltd.

Semiconductor device

To improve a tradeoff between on voltage and on/off loss while maintaining short-circuit tolerance, provided is a semiconductor device including an igbt element; a super junction transistor element connected in parallel with the igbt element; and a limiting section that limits a voltage applied to a gate terminal of the igbt element more than a voltage applied to a gate terminal of the super junction transistor element.. .
Fuji Electric Co., Ltd.

Semiconductor device and semiconductor device manufacturing method

An sj-mosfet and igbt are provided in a single semiconductor chip. Furthermore, a balance is made between a carrier amount of n-type columns and a carrier amount of p-type columns, to encourage formation of a depletion layer in when a reverse voltage is applied in the sj-mosfet section.
Fuji Electric Co., Ltd.

Semiconductor device

A semiconductor device includes a first semiconductor region of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, each comprising a first part, on the first semiconductor region, wherein the second semiconductor regions are spaced apart in a first direction, a third semiconductor region of the first conductivity type on each of the second semiconductor regions, an insulation portion between two of the second semiconductor regions, the insulation portion having one side in contact with one of the first parts and the other side in contact with one of the third semiconductor regions, a first electrode within the insulation portion, a gate electrode spaced apart from the first electrode and within the insulation portion, and a second electrode on the third semiconductor region and electrically connected to the first electrode and the third semiconductor region.. .
Kabushiki Kaisha Toshiba

Method of manufacturing a multi-chip semiconductor power device

A method of manufacturing a semiconductor device includes mounting a first semiconductor power chip on a first carrier, mounting a second semiconductor power chip on a second carrier, bonding a contact clip to the first semiconductor power chip and to the second semiconductor power chip, and mounting a third semiconductor chip over the contact clip.. .
Infineon Technologies Austria Ag

Packaging optoelectronic components and cmos circuitry using silicon-on-insulator substrates for photonics applications

Package structures and methods are provided to integrate optoelectronic and cmos devices using soi semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (ic) chip, and an optoelectronics device and interposer mounted to the ic chip.
International Business Machines Corporation

Semiconductor package and manufacturing the same

A semiconductor package may include a package substrate, a semiconductor chip and a molding member. A protrusion may be formed on a side surface of the package substrate.
Samsung Electronics Co., Ltd.

Fabricating semiconductor device

A fabricating method of a semiconductor device, in which a first semiconductor chip having a desired first thickness and a semiconductor chip having a desired second thickness are used to fabricate a semiconductor device having a desired third thickness that is greater than the sum of the first and second thicknesses includes providing the first semiconductor chip, which has the first thickness, forming the second semiconductor chip, which is connected to the first semiconductor chip via through silicon vias (tsvs) and has the second thickness, on the first semiconductor chip, and providing a dummy semiconductor chip, which is not electrically connected to the semiconductor chip and has a fourth thickness, on the second semiconductor chip, wherein the fourth thickness is generated based on a difference between about the third thickness and about a sum of the first and second thicknesses.. .
Samsung Electronics Co., Ltd.

Semiconductor device and forming inverted pyramid cavity semiconductor package

A semiconductor device has a first substrate. A conductive layer is formed over the first substrate.
Semtech Corporation

Printable component structure with electrical contact

A printable component structure includes a chiplet having a semiconductor structure with a top side and a bottom side, one or more top electrical contacts on the top side of the semiconductor structure, and one or more bottom electrical contacts on the bottom side of the semiconductor structure. One or more electrically conductive spikes are in electrical contact with the one or more top electrical contacts.
X-celeprint Limited

Semiconductor device structure and forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor substrate having a first surface, a second surface, and a recess.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device and manufacturing method thereof

In a semiconductor device according to an embodiment, a second semiconductor chip is mounted on a first rear surface of a first semiconductor chip. Also, the first rear surface of the first semiconductor chip includes a first region in which a plurality of first rear electrodes electrically connected to the second semiconductor chip via a protrusion electrode are formed and a second region which is located on a peripheral side relative to the first region and in which a first metal pattern is formed.
Renesas Electronics Corporation

Semiconductor package and manufacturing method thereof

A semiconductor package includes a package member and a stress controlling layer. The package member includes an encapsulation layer and at least one chip.
Samsung Electronics Co., Ltd.

Semiconductor packages having emi shielding parts and methods of fabricating the same

A semiconductor package may include a semiconductor device mounted on a package substrate, a conductive roof located over the semiconductor device, a plurality of conductive walls disposed on the package substrate and arrayed in a closed loop line surrounding the semiconductor device. Conductive pillars may be disposed in regions between the conductive walls on the package substrate and bonded to the conductive roof.
Sk Hynix Inc.

Methods and devices for metal filling processes

Metal filling processes for semiconductor devices and methods of fabricating semiconductor devices. One method includes, for instance: obtaining a wafer with at least one contact opening; depositing a metal alloy into at least a portion of the at least one contact opening; separating the metal alloy into a first metal layer and a second metal layer; depositing a barrier stack over the wafer; forming at least one trench opening; forming at least one via opening; and depositing at least one metal material into the trench openings and via openings.
Globalfoundries Inc.

Semiconductor device including fuse structure

An efuse structure of a semiconductor device may include a first metal formed at a first level on a substrate, a second metal formed at a second level between the first level and the substrate, a third metal formed at a third level between the second level and the substrate, a first via connecting the first metal to the second metal, and a second via connecting the second metal to the third metal. The first metal may include a first portion extending in a first direction, a second portion extending in the first direction and being adjacent to the first portion, and a third portion connecting the first portion to the second portion.
Samsung Electronics Co., Ltd.

Method and structure for forming on-chip anti-fuse with reduced breakdown voltage

A fully depleted field effect transistor (fet) and an anti-fuse structure are provided on a same chip. The fully depleted fet and the anti-fuse structure share a same high dielectric (k) constant dielectric material.
International Business Machines Corporation

Method for fabricating semiconductor structure

A semiconductor structure is provided. The semiconductor structure includes a substrate; and a plurality of parallel first conductive layers formed on the substrate.
Semiconductor Manufacturing International (shanghai) Corporation

Conductive through-polymer vias for capacitative structures integrated with packaged semiconductor chips

An electronic system comprising an electronic body (301) with terminal pads (310) and at least one capacitor embedded in the electronic body. The capacitor including an insulating and adhesive first polymeric film (302) covering the body surface except the terminal pads; a sheet (320) of high-density capacitive elements, the first capacitor terminal being a metal foil (321) attached to film (302), the second terminal a conductive polymeric compound (324), and the insulator a dielectric skin (323).
Texas Instruments Incorporated

Reducing liner corrosion during metallization of semiconductor devices

Reducing liner corrosion during metallization of semiconductor devices at beol includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.. .
Globalfoundries Inc.

Semiconductor device

A semiconductor device includes a resin case which houses a semiconductor element, a plurality of lead frames disposed in the principal plane of a base of the resin case with spaces therebetween, and a block portion disposed over a space between adjacent lead frames along the adjacent lead frames. With the semiconductor device, the disposition of the block portion makes creepage distance long, compared with a case where the block portion is not disposed and therefore a space between the adjacent lead frames is flat.
Fuji Electric Co., Ltd.

Semiconductor structure

Provided is a semiconductor structure including a first die and a second die. The first die has a first conductive structure embedded in a dielectric layer.
Powertech Technology Inc.

Semiconductor device package and manufacturing the same

The present disclosure relates to a semiconductor device package and a method for manufacturing the same. The semiconductor device package comprises a substrate, a first patterned conductive layer, an insulator layer, a second patterned conductive layer, and a dielectric layer.
Advanced Semiconductor Engineering, Inc.

Reducing lead stress in micro-electronic packages

Consistent with an example embodiment, there is a semiconductor device that comprises a lead frame assembly having a non-conductive material (ncm) sheet placed on a location of the lead frame assembly. A device die having a length, width, and thickness, is attached to the ncm sheet, the device die being attached to the ncm with an adhesive.
Nxp B.v.

Tape chip on lead using paste die attach material

According to various embodiments, systems and methods for packaging a semiconductor device are provided. The disclosure discusses a semiconductor die having a top side and a bottom side that is disposed on a lead frame.
Cypress Semiconductor Corporation

Method for making a semiconductor device having an interposer

A semiconductor device and a method for making the semiconductor device are provided. The semiconductor device comprises a leadframe and a metal interposer.
Freescale Semiconductor, Inc.

Semiconductor devices with through electrodes and methods of fabricating the same

Provided herein are semiconductor devices with through electrodes and methods of fabricating the same. The methods may include providing a semiconductor substrate having top and bottom surfaces facing each other, forming on the top surface of the semiconductor substrate a main via having a hollow cylindrical structure and a metal line connected to the main via, forming an interlayered insulating layer on the top surface of the semiconductor substrate to cover the main via and the metal line, removing a portion of the semiconductor substrate to form a via hole exposing a portion of a bottom surface of the main via, and forming in the via hole a through electrode that is electrically connected to the main via.

Semiconductor device, manufacturing method thereof, and electronic apparatus

A semiconductor device includes a substrate and a semiconductor element mounted on the top surface of the substrate. On the top surface of the substrate, one or more pads are disposed outside the mounted semiconductor element when seen in a plan view.
Socionext Inc.

Semiconductor device

A semiconductor device includes a semiconductor module having a semiconductor element, a radiator plate which is connected to the semiconductor element and which has at least one radiator plate through hole formed therein, and resin covering the semiconductor element and the radiator plate with a lower surface of the radiator plate exposed, a cooler, first insulating grease provided between the lower surface of the radiator plate and the cooler to thermally connect the radiator plate and the cooler, and second insulating grease provided in the at least one radiator plate through hole to be connected to the first insulating grease.. .
Mitsubishi Electric Corporation

Semiconductor packages and methods of fabricating the same

semiconductor packages and methods of fabricating the same are disclosed. The semiconductor package may include a package substrate, a semiconductor chip, which is mounted on the package substrate to have a bottom surface facing the package substrate and a top surface opposite to the bottom surface, a mold layer provided on the package substrate to encapsulate the semiconductor chip, and a heat dissipation layer provided on the top surface of the semiconductor chip.

Thermosetting resin molded article

A thermosetting resin molded article including: a metal member; a first thermosetting resin layer containing a chelating agent in an amount of 0.5% by mass or more; and a second thermosetting resin layer containing no chelating agent or containing a chelating agent in an amount of less than 0.5% by mass, in which the metal member, the first thermosetting resin layer, and the second thermosetting resin layer are stacked in this order is provided. A semiconductor device including: a semiconductor element mounted on a substrate and metal members, which are sealed with a sealant, in which the sealant includes: a first thermosetting resin layer stacked on the semiconductor element and the metal member; and a second thermosetting resin layer stacked on the first thermosetting resin layer is also provided..
Fuji Electric Co., Ltd.

Methods for manufacturing a semiconductor device

A method for manufacturing a semiconductor device includes forming gate structures spaced apart from each other on a substrate, gate spacers covering sidewalls of the gate structures, and an interlayer insulating layer covering the gate spacers, forming a contact hole that penetrates the interlayer insulating layer to expose a sidewall of at least one of the gate spacers, forming a sacrificial gap-fill pattern filling a lower portion of the contact hole, forming a contact spacer on a sidewall of the contact hole having the sacrificial gap-fill pattern, and forming a contact filling the contact hole after removing the sacrificial gap-fill pattern.. .
Samsung Electronics Co., Ltd.

Forming a contact for a tall fin transistor

A method of making a semiconductor device includes forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the substrate; performing an epitaxial growth process over the recessed fin to form a source/drain over the recessed fin; and disposing a conductive metal around the source/drain.. .
Globalfoundries, Inc.

Field effect transistors having multiple effective work functions

Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions.
Globalfoundries Inc.

Method of manufacturing a semiconductor device including forming a dielectric layer around a patterned etch mask

A method of manufacturing a semiconductor device includes: providing a semiconductor having active regions; depositing a dielectric layer on the semiconductor; forming a patterned etch mask on the dielectric layer; depositing a further dielectric layer on the dielectric layer and the patterned etch mask; planarizing the further dielectric layer until the patterned etch mask is exposed; and forming a further patterned etch mask having an opening on the further dielectric layer so that portions of the patterned etch mask are exposed from the opening.. .
United Microelectronics Corp.

Methods for producing interconnects in semiconductor devices

A method for forming metallization in a workpiece includes electrochemically depositing a second metallization layer on the workpiece comprising a nonmetallic substrate having a dielectric layer disposed over a substrate and a continuous first metallization layer disposed on the dielectric layer and having at least one microfeature comprising a recessed structure, wherein the first metallization layer at least partially fills a feature on the workpiece, where the first metallization layer is a cobalt or nickel metal layer, and wherein the second metallization layer is a cobalt or nickel metal layer that is different from the metal of the first metallization layer, electrochemically depositing a copper cap layer after filling the feature, and annealing the workpiece to diffuse the metal of the second metallization layer into the metal of the first metallization layer.. .
Applied Materials, Inc.

Semiconductor device having insulating layers containing oxygen and a barrier layer containing manganese

A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.. .
Fujitsu Semiconductor Limited

Semiconductor devices having isolation insulating layers and methods of manufacturing the same

The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer..
Samsung Electronics Co., Ltd.

Low pressure encapsulant for size-reduced semiconductor package

The present disclosure relates to a packaging process using a low pressure encapsulant. According to an exemplary process, an assembly including a substrate, a surface mounted device (smd) mounted on the substrate, and a space between the smd and the substrate is provided.
Qorvo Us, Inc.

Method of fabricating an electrical contact for use on a semiconductor device

According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride.
Infineon Technologies Americas Corp.

Method of manufacturing semiconductor device

The present invention is provided to improve quality or manufacturing throughput of a semiconductor device. A method includes supplying a source gas to a substrate in a process chamber; exhausting an inside of the process chamber; supplying a reaction gas to the substrate; and exhausting the inside of the process chamber, wherein the source gas and/or the reaction gas is supplied in temporally separated pulses in the supply of the source gas and/or in the supply of the reaction gas.
Hitachi Kokusai Electric Inc.

Forming a contact for a tall fin transistor

A method of making a semiconductor device includes forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the substrate; performing an epitaxial growth process over the recessed fin to form a source/drain over the recessed fin; and disposing a conductive metal around the source/drain.. .
Globalfoundries, Inc.

Epitaxial growth of gallium arsenide on silicon using a graphene buffer layer

Epitaxial growth of gallium arsenide (gaas) on a semiconductor material (e.g., si) using quasi-van der waals epitaxy (qvdwe). Prior to gaas growth a buffer layer (e.g., graphene) is deposited which relieves lattice mismatch/thermal expansion.
King Abdulaziz City For Science And Technology

Structures and methods for forming fin structures

Structures and methods are provided for forming fin structures. A first fin structure is formed on a substrate.
Taiwan Semiconductor Manufacturing Company Limited

Oxide sintered body, sputtering target, and oxide semiconductor thin film obtained using sputtering target

Provided are: a sintered oxide which achieves low carrier density and high carrier mobility when configured as an oxide semiconductor thin-film by using the sputtering method; and a sputtering target using the same. This sintered oxide contains indium, gallium and magnesium as oxides.
Sumitomo Metal Mining Co., Ltd.

Method for manufacturing tungsten-based capacitor element

The present invention provides a method for producing a capacitor element having good lc characteristics, wherein, after a chemical conversion process to form a dielectric layer on the surface layer of an anode body obtained by forming a powder mainly comprising tungsten, followed by sintering, a semiconductor layer and a conductor layer are sequentially formed on the dielectric layer; an etching process is conducted before forming the dielectric layer to remove a natural oxide film formed on the surface layer on the outer surface and on the surface inside the pores of the anode body so as to adjust the film thickness to a range of 0.5 to 5.0 nm; and the chemical conversion process is conducted at a temperature from −4 to 18° c. For 7 to 110 minutes after reaching a predetermined voltage..
Showa Denko K.k.

Semiconductor memory cell multi-write avoidance encoding apparatus, systems and methods

Data words to be written to a memory location are delta encoded in multi-write avoidance (“mwa”) code words. Mwa code words result in no re-writing of single-bit storage cells containing logical “0's” to a “0” state and no re-writing of logical “1's” to cells that have already been written once to a logical “1.” potential mwa code words stored in a look-up table (“lut”) are indexed by a difference word delta_d.
Texas Instruments Incorporated

Semiconductor storage device and test method thereof using a common bit line

Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.. .
Renesas Electronics Corporation

Nonvolatile semiconductor memory

A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected wordline, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.. .
Kabushiki Kaisha Toshiba

Non-volatile semiconductor memory device and erase method thereof

Provided is an erase method for a non-volatile semiconductor memory device to compensate for the change in property of a memory cell, in proportion to the number of data rewrites to the memory cell. The erase method has an erase step to erase charges of a charge accumulation layer by applying an erase voltage to a channel region of a selected memory cell, and a soft-programming step to perform soft-programming to the charges in the accumulation layer by virtue of applying a soft-programming voltage which is smaller than a programming voltage to program the memory cell.
Winbond Electronics Corp.

Semiconductor device and control the semiconductor device

A semiconductor device includes a memory array having a plurality of complementary cells, each including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, and a control circuit for initializing the complementary cells. The control circuit performs a first initialization control of reducing the threshold voltage of both the first memory element and the second memory element of the complementary cell and changing the threshold voltage of at least one of the first memory element and the second memory element at an intermediate level lower than a first writing level and higher than an initialization level, a first writing control of changing the threshold voltage of one of the first memory element and the second memory element of the complementary cell at the first writing level, and a second initialization control of changing the threshold voltage of both the first memory element and the second memory element of the complementary cell at the initialization level..
Renesas Electronics Corporation

Semiconductor memory device managing flexible refresh skip area

A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area..
Samsung Electronics Co., Ltd.

Semiconductor memory device and semiconductor memory system including the same

A semiconductor memory device includes: a memory cell array including a plurality of word lines; a word line driving unit suitable for activating a first word line among the plurality of word lines corresponding to an input address signal; an activation time detection unit suitable for enabling a detection signal by detecting an activation time of the first word line; an address latch unit suitable for latching an address information for a second word line corresponding to the first word line in response to the detection signal; and an address output unit suitable for providing the word line driving unit with the latched address information for the second word line during a refresh operation.. .
Sk Hynix Inc.

Nonvolatile semiconductor memory

According to one embodiment, a nonvolatile semiconductor memory includes a resistance-change element having first and second terminals, a transistor having third and fourth terminals and a control terminal, the third terminal being connected to the second terminal, and a first driver electrically connected to the control terminal, applying a first potential to the control terminal in a first write operation, and applying a second potential larger than the first potential to the control terminal in a second write operation.. .
Kabushiki Kaisha Toshiba

Semiconductor storage device

According to one embodiment, a semiconductor storage device includes a first semiconductor storage area; a second semiconductor storage area; a reference circuit; a sense amplifier senses data stored in the first semiconductor storage area and the second semiconductor storage area; and a control circuit.. .
Kabushiki Kaisha Toshiba

Integrated circuit device body boas circuits and methods

A system having an integrated circuit (ic) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.. .
Mie Fujitsu Semiconductor Limited

Semiconductor device and data processing system selectively operating as one of a big endian or little endian system

The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register.
Renesas Electronics Corporation

Semiconductor device, liquid crystal display panel, and mobile information terminal

A semiconductor device includes a plurality of sets of external drive terminals in a marginal region along one long side of a rectangular semiconductor substrate, a plurality of sets of esd protection circuits arranged in the marginal region and coupled to corresponding sets of the drive terminals, and a plurality of output circuits coupled to corresponding sets of the drive terminals. Each set of drive terminals in a plurality of n columns along a y direction is laid out in a staggered arrangement with drive terminals in adjacent columns shifted relative to each other.
Renesas Electronics Corporation



Semiconductor topics:
  • Semiconductor
  • Semiconductor Substrate
  • Semiconductor Device
  • Semiconductor Material
  • Electric Conversion
  • Conductive Layer
  • Molybdenum
  • Camera Module
  • Semiconductor Devices
  • Semiconductors
  • Integrated Circuit
  • Surfactant
  • Photoelectric Conversion
  • Electronic Device
  • Transparent Conductive Oxide


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