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Semiconductor patents

      

This page is updated frequently with new Semiconductor-related patent applications.




 Printed circuit board, semiconductor package and  manufacturing the same patent thumbnailnew patent Printed circuit board, semiconductor package and manufacturing the same
A printed circuit board, a semiconductor package, and a method of producing the same are provided. The printed circuit board (pcb) includes an insulating layer and a circuit layer including metal pads exposed on a side surface and a lower surface of the insulating layer..
Samsung Electro-mechanics Co., Ltd.


 Semiconductor light source drive device patent thumbnailnew patent Semiconductor light source drive device
A semiconductor light source drive device includes a semiconductor light source; a switching element that controls a current flowing through the semiconductor light source by being on/off-controlled by a pwm signal provided to the control end; a current detection element that detects a current flowing through the semiconductor light source; a switching power source that supplies power supply voltage to a series connection of the semiconductor light source, the switching element, and the current detection element; a pwm supply circuit supplies the pwm signal and its on-time ratio information; a target value setting part converts the on-time ratio information to a target average current value and outputs the target average current value; and a comparator compares the target average current value with an average current value detected by the current detection element and outputs comparison output to the switching power source as a signal for control.. .
Panasonic Intellectual Property Management Co., Ltd.


 Component having a micromechanical microphone pattern patent thumbnailnew patent Component having a micromechanical microphone pattern
Measures are provided for increasing the resistance to compression of a component having a micromechanical microphone pattern. In particular, the robustness of the microphone pattern to highly dynamic pressure fluctuations is to be increased, without the microphone sensitivity, i.e.
Robert Bosch Gmbh


 Secure provisioning of semiconductor chips in untrusted manufacturing factories patent thumbnailnew patent Secure provisioning of semiconductor chips in untrusted manufacturing factories
One embodiment of the present invention includes a boot read only memory (rom) with an embedded, private key provision key (kpk) set that enables secure provisioning of chips. As part of taping-out a chip, the chip provider establishes the kpk set and provides the boot rom exclusive access to the kpk.
Nvidia Corportion


 Partial cqi feedback in wireless networks patent thumbnailnew patent Partial cqi feedback in wireless networks
A lead frame (410) including a die pad (100) for mounting at least one integrated circuit (405) thereon and a plurality of lead fingers (413). The die pad (100) includes a metal including substrate (105) having a periphery that includes a plurality of sides (111-114), an intersection of the sides forming corners (115).
Texas Instruments Incorporated


 Semiconductor device patent thumbnailnew patent Semiconductor device
According to one embodiment, a semiconductor device includes: a first circuit including a first transistor, a second transistor, the first and second transistors being capable of receiving first and second signals, respectively; a second circuit including a third transistor and a fourth transistor, a gate and one end of the third transistor being connected to one end of the first transistor, the fourth transistor being capable of receiving the first signal, one end of the fourth transistor being connected to the other end of the third transistor; and a third circuit configured to charge or discharge a node being connected to the one end of the first transistor according to the first signal.. .
Kabushiki Kaisha Toshiba


 Distributed mach-zehnder modulator (mzm) driver delay compensation patent thumbnailnew patent Distributed mach-zehnder modulator (mzm) driver delay compensation
An electronic driver circuit for use with a modulator such as a segmented mach-zehnder modulator (mzm) is provided. The electronic driver circuit includes a first delay buffer implemented as a first complementary metal-oxide-semiconductor (cmos) inverter and a second delay buffer implemented as a second cmos inverter.
Futurewei Technologies, Inc.


 Semiconductor device, electronic component, and electronic device patent thumbnailnew patent Semiconductor device, electronic component, and electronic device
A semiconductor device includes a logic circuit capable of storing configuration data. The logic circuit includes a latch circuit, an arithmetic circuit, a delay circuit, and a first output timing generation circuit.
Semiconductor Energy Laboratory Co., Ltd.


 Method and system for a pseudo-differential low-noise amplifier at ku-band patent thumbnailnew patent Method and system for a pseudo-differential low-noise amplifier at ku-band
Methods and systems for a pseudo-differential low-noise amplifier at ku-band may comprise a low-noise amplifier (lna) integrated on a semiconductor die, where the lna comprises differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may comprise: a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors.
Maxlinear, Inc.


 Magnetic sensor integrated circuit, motor assembly and application device patent thumbnailnew patent Magnetic sensor integrated circuit, motor assembly and application device
A magnetic sensor integrated circuit, a motor assembly and an application device are provided. The integrated circuit includes a housing, a semiconductor substrate, at least one input port and an output port, and an electronic circuit arranged on the semiconductor substrate.
Johnson Electric S.a.


new patent

Magnetic sensor integrated circuit, motor assembly and application device

A magnetic sensor integrated circuit includes an electronic circuit arranged on a semiconductor substrate, and input ports and first and second output ports extending out from a housing. The electronic circuit includes a magnetic field detection circuit and an output control circuit.
Johnson Electric S.a.

new patent

Power module

A power module includes a substrate, a first sub-module and a second sub-module. The substrate includes plural first conducting parts, plural second conducting parts and a third conducting part.
Delta Electronics Int'l (singapore) Pte Ltd

new patent

Semiconductor module

A semiconductor module is provided with a high potential wiring, an output wiring, a low potential wiring, an upper arm switching device, an upper arm diode, a lower arm switching device, and a lower arm diode. A ratio of steady loss to switching loss of the upper arm switching device is configured to be smaller than a ratio of steady loss to switching loss of the lower arm switching device.
Toyota Jidosha Kabushiki Kaisha

new patent

Integrated circuit, driving circuit for motor, motor assembly and application equipment therefor

An integrated circuit includes a housing, a semiconductor substrate arranged in the housing, several pins extended out from the housing, and an electronic circuitry having a rectifier arranged on the semiconductor substrate. The rectifier includes a controllable switch..
Johnson Electric S.a.

new patent

Semiconductor laser device

A semiconductor laser device includes an n-type nitride semiconductor layer; a first layer disposed above the n-type nitride semiconductor and composed of inaga1-an (0≦a<1); a second layer disposed above the first layer and composed of inbga1-bn (0<b<1, a<b), the second layer having a thickness smaller than that of the first layer and containing an n-type impurity; a third layer composed of incga1-cn (0≦c<1, c<b) and having a thickness smaller than that of the second layer, the third layer being disposed on (i) a surface of the second layer on the active layer side and/or (ii) a surface of the second layer on the first layer side; an active layer disposed above the second layer and the third layer, and having a single quantum well structure or a multiple quantum well structure; and a p-type nitride semiconductor layer disposed above the active layer.. .
Nichia Corporation

new patent

Semiconductor laser diode and fabricating the same

Provided are a semiconductor laser diode and a method for fabricating the same. The semiconductor laser diode includes a c-plane substrate, a group iii nitride layer disposed on the c-plane substrate, and a first semiconductor layer, an active layer, and a second semiconductor layer disposed on the group iii nitride layer in the stated order, wherein each of the first semiconductor layer and the second semiconductor layer is exposed to the outside of the semiconductor laser diode..
Korea Photonics Technology Institute

new patent

Semiconductor laser device

A semiconductor laser device includes an active layer including a well layer and a barrier layer formed of a iii-v group semiconductor crystal containing as as a primary component of a v group. A v group element other than as has been introduced at a concentration of 0.02 to 5% into a v group site of the iii-v group semiconductor crystal in at least one of the well layer and the barrier layer, and a iii group site of the iii-v group semiconductor crystal in at least one of the well layer and the barrier layer contains al..
Furukawa Electric Co., Ltd.

new patent

Semiconductor device header and semiconductor device

A semiconductor device header is provided with a base including a main body and a heat sink. A lead is inserted through a through hole extending through the main body.
Shinko Electric Industries Co., Ltd.

new patent

Mode-locked multi-mode fiber laser pulse source

A laser utilizes a cavity design which allows the stable generation of high peak power pulses from mode-locked multi-mode fiber lasers, greatly extending the peak power limits of conventional mode-locked single-mode fiber lasers. Mode-locking may be induced by insertion of a saturable absorber into the cavity and by inserting one or more mode-filters to ensure the oscillation of the fundamental mode in the multi-mode fiber.
Imra America, Inc.

new patent

Tunable optical filter and tunable light source

A tunable filter structure comprising of a rotating disk made of metal parts in which n diffractive elements like bulk gratings are adjusted and mounted individually to disperse the incoming light and form a littman-metcalf configuration for selecting different wavelength of light, a servo motor to rotate the disk, a reflective element like mirror and a multi-branch configuration comprising of m branches that are synchronized in time and are combined by an optical coupler or an optical switch. In the second embodiment, the diffractive elements are replaced by the reflective elements to form a littrow configuration.

new patent

Integration of area efficient antennas for phased array or wafer scale array antenna applications

Package structures are provided for integrally packaging antennas with semiconductor rfic (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems that operate in the millimeter-wave and terahertz frequency ranges. For example, a package structure includes an rfic chip, and an antenna package bonded to the rfic chip.
International Business Machines Corporation

new patent

Semiconductor device and electronic device

A semiconductor device in which a circuit and a battery are efficiently stored is provided. In the semiconductor device, a first transistor, a second transistor, and a secondary battery are provided over one substrate.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Thin film device with protective layer

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided.
International Business Machines Corporation

new patent

Organic thin-film transistor

Provided is an organic thin-film transistor which is a bottom-gate type organic thin-film transistor including a substrate; a gate electrode provided on the substrate; a first gate insulating layer provided to cover the gate electrode; a second gate insulating layer provided on the first gate insulating layer; an organic semiconductor layer provided on the second gate insulating layer; and a source electrode and a drain electrode provided in contact with the organic semiconductor layer and connected to each other through the organic semiconductor layer, in which the surface of the first gate insulating layer on the second gate insulating layer side is subjected to an alignment treatment, and the second gate insulating layer is a layer formed by polymerizing and immobilizing a polymerizable crystalline compound aligned in accordance with the alignment treatment, in the aligned state.. .
Fujifilm Corporation

new patent

Compounds having semiconducting properties and related compositions and devices

Disclosed are new compounds having semiconducting properties. Such compounds can be processed in solution-phase at a temperature of less than about 50° c.
Polyera Corporation

new patent

Thin film transistor

Provided is a thin film transistor including a gate electrode, a semiconductor layer, a gate insulating layer provided between the gate electrode and the semiconductor layer and formed of an organic polymer compound, and a source electrode and a drain electrode provided in contact with the semiconductor layer and connected via the semiconductor layer, on a substrate, in which the content of metals selected from mg, ca, ba, al, sn, pb, cr, mn, fe, ni, cu, zn, and ag in the gate insulating layer is 10 ppb to 1 ppm in terms of total amount, or the content of non-metal ionic materials selected from halogen ions, sulfate ions, nitrate ions, and phosphate ions is 1 ppm to 100 ppm in terms of total amount.. .
Fujifilm Corporation

new patent

Phenazine-based molecular and polymeric semiconductors

The present invention relates to new semiconducting compounds having at least one optionally substituted phenazine moiety. The compounds disclosed herein can exhibit high carrier mobility and/or efficient light absorption/emission characteristics, and can possess certain processing advantages such as solution-processability and/or good stability at ambient conditions..
Polyera Corporation

new patent

Methods and compositions for enhancing processability and charge transport of polymer semiconductors

A method of making a solid state semiconducting film. The method includes blending a non-conjugated semiconducting polymer matrix containing crystalline aggregates with intentionally placed conjugation-break spacers along the polymer backbone, and fully conjugated semiconducting polymer.
Purdue Research Foundation

new patent

Manufacturing thin film transistor and thin film transistor , array substrate

The present disclosure pertains to the technical field of display, which relates to a manufacturing method of a thin film transistor and a thin film transistor, and an array substrate. The manufacturing method of a thin film transistor comprises: forming, above a substrate, patterns comprising different surface energies; coating, above said substrate, a composite solution containing organic semiconductor material and polymer insulating material, and forming a composite film layer; patterning said composite film layer according to the patterns with different surface energies above said substrate, preserving said composite film layer corresponding to the pattern areas with relatively high surface energies; layering said patterned composite film layer by means of an organic solvent steam treatment method; forming two separate metal electrodes at two opposite sides of said patterned composite film layer..
Ordos Yuansheng Optoelectronics Co., Ltd.

new patent

Electric field control element for phonons

Generally discussed herein are techniques for and systems and apparatuses configured to control phonons using an electric field. In one or more embodiments, an apparatus can include electrical contacts, two quantum dots embedded in a semiconductor such that when an electrical bias is applied to the electrical contacts, the electric field produced by the electrical bias is substantially parallel to an axis through the two quantum dots, and a phononic wave guide coupled to the semiconductor, the phononic wave guide configured to transport phonons therethrough..
The Regents Of The University Of California

new patent

Method for manufacturing the magnetic field sensor module

In the method of manufacturing a magnetoresistive sensor module, at first a composite arrangement out of a semiconductor substrate and a metal-insulator arrangement is provided, wherein a semiconductor circuit arrangement is integrated adjacent to a main surface of the semiconductor substrate into the same, wherein the metal-insulator arrangement is arranged on the main surface of the semiconductor substrate and comprises a structured metal sheet and insulation material at least partially surrounding the structured metal sheet, wherein the structured metal sheet is electrically connected to the semiconductor circuit arrangement. Then, a magnetoresistive sensor structure is applied onto a surface of the insulation material of the composite arrangement, and finally an electrical connection between the magnetoresistive sensor structure and the structured metal sheet is established, so that the magnetoresistive sensor structure is connected to the integrated circuit arrangement..
Infineon Technologies Ag

new patent

Magnetic memory cells, semiconductor devices, and methods of operation

A magnetic cell core includes at least one stressor structure proximate to a magnetic region (e.g., a free region or a fixed region). The magnetic region may be formed of a magnetic material exhibiting magnetostriction.
Micron Technology, Inc.

new patent

Light emitting device

Disclosed is a light emitting device which includes a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, a first current blocking layer, a second current blocking layer arranged on the light emitting structure to be separated from each other, a light-transmitting conductive layer arranged on the first current blocking layer, the second current blocking layer and the light emitting structure, first electrode and second electrode electrically coupled to the first conductive semiconductor layer and the second conductive semiconductor layer, respectively, a through hole formed through the light-transmitting conductive layer, the second conductive semiconductor layer and the active layer to a portion of the first conductive semiconductor layer, and a through electrode arranged inside the through hole. Here, the through electrode does not overlap the first current blocking layer in a vertical direction..
Lg Innotek Co., Ltd.

new patent

Semiconductor light-emitting device package

A semiconductor light-emitting device package includes: a light-emitting structure having a first surface, a second surface opposite to the first surface and side surfaces disposed between the first and the second surfaces, the light-emitting structure comprising a first light-emitting laminate and a second light-emitting laminate, each of the first and the second light emitting laminates including: a first conductivity-type semiconductor layer; an active layer, and a second conductivity-type semiconductor layer, an interconnector provided on the second surface of the light-emitting structure and configured to electrically connect the first and the second light-emitting laminates; a metal guide surrounding the side surfaces of the light-emitting structure; and an encapsulant surrounding the metal guide and the second and the side surfaces of the light-emitting structure and exposing the first surface of the light-emitting structure.. .

new patent

Semiconductor light emitting device

A semiconductor light emitting device includes: a light emitting structure including a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer respectively providing a first surface and a second surface, opposite to each other, of the light emitting structure, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, a region of the first conductivity-type semiconductor layer being open toward the second surface, and the first surface having a concavo-convex portion disposed thereon; a first electrode and a second electrode disposed on the region of the first conductivity-type semiconductor layer and a region of the second conductivity-type semiconductor layer, respectively; a transparent support substrate disposed on the first surface of the light emitting structure; and a transparent adhesive layer disposed between the first surface of the light emitting structure and the transparent support substrate.. .
Samsung Electronics Co., Ltd.

new patent

Jacketed led assemblies and light strings containing same

A jacketed light emitting diode assembly is provided, which includes a light emitting diode including a set of positive and negative contacts, and a lens body containing a semiconductor chip and end portions of the contacts. An electrical wire set of first and second electrical wires are connected to the positive contact and the negative contact, respectively.
Fiber Optic Designs, Inc.

new patent

Light emitting diode chip having wavelength converting layer and fabricating the same, and package having the light emitting diode chip and fabricating the same

A light-emitting diode (led) includes a substrate, a semiconductor stacked structure disposed on the substrate, the semiconductor stacked structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, a wavelength converting layer configured to convert a wavelength of light emitted from the semiconductor stacked structure, the wavelength converting layer covering side surfaces of the substrate and the semiconductor stacked structure, and a distributed bragg reflector (dbr) configured to reflect at least a portion of light wavelength-converted by the wavelength converting layer, in which at least a portion of the dbr is covered with a metal layer configured to reflect light transmitted through the dbr.. .
Seoul Semiconductor Co., Ltd.

new patent

Optoelectronic semiconductor component

The invention relates to an optoelectronic semiconductor component (1) comprising:—an optoelectronic semiconductor chip (2), comprising—a growth substrate (21) having a growth surface (21a),—a layer sequence (22) with a semiconductor layer sequence (221, 222, 223) with an active zone (222) grown on the growth surface (21a),—contact points (29) for electrically contacting the semiconductor layer sequence (221, 222, 223) and—and insulation layer (26), which is formed in an electrically insulting manner—a connection carrier (4), which is mounted to the cover surface (2a) of the optoelectronic semiconductor chip facing away from the growth surface (21a), wherein—the semiconductor layer sequence (221, 222, 223) is connected to the connection carrier (4) in an electrically conducting manner and—a conversion layer (5) is applied to a bottom surface (21c) of the growth substrate (21) facing away from the growth surface (21a) and to all side surfaces (21b) of the growth substrate (21).. .
Osram Opto Semiconductors Gmbh

new patent

Light emitting device package and manufacturing the same

In one embodiment, a light emitting device package includes a light emitting device including a substrate and a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, stacked on the substrate; a reflective conductive layer provided on the light emitting structure; and a first electrode and a second electrode overlying the reflective conductive layer separated from each other in a first region. The first electrode and the second electrode are electrically insulated from the reflective metal layer and penetrate through the reflective metal layer to be electrically connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively..
Samsung Electronics Co., Ltd.

new patent

Semiconductor light-emitting device

A semiconductor light-emitting device having improved light extraction efficiency provided by a reflector including a separation layer. The separation layer may be interposed between first and second bragg layers including one or more pairs of refractive layers having different refractive indices, the first pairs being stacked on one side of the separation layer and the second pairs being stacked on an opposing side of the separation layer..

new patent

Semiconductor light emitting structure and manufacturing method thereof

A semiconductor light emitting structure and a manufacturing method thereof are provided. The semiconductor light emitting structure includes a substrate, an epitaxial layer and a stepped electrode.
Lextar Electronics Corporation

new patent

Fabrication nitride light emitting diodes

A fabrication method of nitride leds, which reduces electron leakage and efficiency droop and improves hole concentration and light emitting efficiency, the method including: (1) providing an intermediate substrate; (2) growing a p-type semiconductor layer and a first bonding layer on the intermediate substrate in sequence; (3) providing a permanent substrate; (4) growing an n-type semiconductor layer, a light emitting layer and a second bonding layer on the permanent substrate; (5) bonding the intermediate substrate with the p-type semiconductor layer and the permanent substrate with the n-type semiconductor layer and the light emitting layer through the first bonding layer and the second bonding layer.. .
Xiamen Sanan Optoelectronics Technology Co., Ltd.

new patent

Method of manufacturing semiconductor substrate and substrate for semiconductor growth

A method of manufacturing a semiconductor substrate may include: forming a buffer layer on a growth substrate; forming a plurality of openings in the buffer layer, the plurality of openings penetrating through the buffer layer and being spaced apart from one another; forming a plurality of cavities on the growth substrate, the plurality of cavities being aligned to respectively correspond to the plurality of openings; growing a semiconductor layer on the buffer layer, the growing the semiconductor layer including filling the plurality of openings with the semiconductor layer; and separating the buffer layer and the semiconductor layer from the growth substrate, wherein a diameter of each of the plurality of openings at a boundary between the growth substrate and the buffer layer is smaller than a diameter of each of the plurality of cavities at the boundary.. .
Samsung Electronics Co., Ltd.

new patent

High quantum efficiency photodetector

A photodetector including a photoelectric conversion structure made of a semiconductor material and, on a light-receiving surface of the conversion structure, a stack of first and second diffractive elements, the second element being above the first element, wherein: the first element includes at least one pad made of a material having an optical index n1, laterally surrounded with a region made of a material having an optical index n2 different from n1; the second element includes at least one pad made of a material having an optical index n3, laterally surrounded with a region made of a material having an optical index n4 different from n3; the pads of the first and second elements are substantially vertically aligned; and optical index differences n1−n2 and n3−n4 have opposite signs.. .
Stmicroelectronics Sa

new patent

Semiconductor device and manufacturing the same

A semiconductor device includes a silicon substrate and a detection element and p-type and n-type mos transistors, which are arranged on the silicon substrate, wherein the detection element includes a semiconductor layer, electrodes, and a schottkey barrier disposed therebetween, the semiconductor layer is arranged just above a layer having the same composition and height as those of an impurity diffusion layer in the source or drain of the p-type or n-type mos transistor, a region, in the silicon substrate, having the same composition and height as those of a channel region, in the silicon substrate, just below a gate oxide film of the p-type mos transistor or the n-type mos transistor, or a region, in the silicon substrate, having the same composition and height as those of a region just below a field oxide film disposed between the p-type and the n-type mos transistor.. .
Canon Kabushiki Kaisha

new patent

Semiconductor layered structure, producing semiconductor layered structure, and producing semiconductor device

A semiconductor layered structure includes a substrate formed of a iii-v compound semiconductor, a buffer layer disposed on and in contact with the substrate and formed of a iii-v compound semiconductor, and a quantum well layer disposed on and in contact with the buffer layer and including a plurality of component layers formed of iii-v compound semiconductors. The substrate has a diameter of 55 mm or more.
Sumitomo Electric Industries, Ltd.

new patent

Semiconductor devices, a fluid sensor and a forming a semiconductor device

A semiconductor device comprises a plurality of quantum structures comprising predominantly germanium. The plurality of quantum structures are formed on a first semiconductor layer structure.
Infineon Technologies Ag

new patent

Solar cell and manufacturing the same

Disclosed is a method of manufacturing a solar cell, the method including forming a tunneling layer over one surface of a semiconductor substrate, forming a semiconductor layer over the tunneling layer, forming a conductive area including a first conductive area of a first conductive type and a second conductive area of a second conductive type in the semiconductor layer, and forming an electrode including a first electrode connected to the first conductive area and a second electrode connected to the second conductive area. The forming of the conductive area includes forming a mask layer over the semiconductor layer, forming a doping opening corresponding to at least one of the first conductive area and the second conductive area in the mask layer using a laser, and performing doping using the doping opening..
Lg Electronics Inc.

new patent

Semiconductor photodetector

Wherein the semiconductor layer is completely etched in areas of the semiconductor layer that are neither covered by the metal pads nor by the connection strips, and wherein each metal pad forming an antenna for collecting incident photons of the light beam on an effective collection surface (Σ′) of the light at least twice larger than a physical collection surface (a) of the semiconductor layer covered by said metal pad.. .

new patent

Electronic device and producing the same

An electronic device includes a structure including a first resin layer, an electronic component buried in the first resin layer, a reflector element for antenna disposed on the first resin layer, and an insulating layer disposed on the reflector element;a semiconductor device;a second resin layer in which the structure and the semiconductor device are buried; and a radiating element of the antenna, the radiating element being disposed on the insulating layer and electrically coupled the semiconductor device.. .
Fujitsu Limited

new patent

Module fabrication of solar cells with low resistivity electrodes

One embodiment of the present invention provides a solar module. The solar module includes a front-side cover, a back-side cover, and a plurality of solar cells situated between the front- and back-side covers.
Solarcity Corporation

new patent

Co-planar oxide semiconductor tft substrate structure and manufacture method thereof

The present invention provides a co-planar oxide semiconductor tft substrate structure and a manufacture method thereof. In the co-planar oxide semiconductor tft substrate structure, the active layer comprises a main body and a plurality of short channels connected to the main body, and the plurality of short channels are separated with the plurality of strip metal electrodes to make the active layer possess higher mobility and lower leak current.
Shenzhen China Star Optoelectronics Technology Co. Ltd.

new patent

Semiconductor device

In a semiconductor device using a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. The semiconductor device includes a gate electrode over an insulating surface; an oxide semiconductor film overlapping with the gate electrode; a gate insulating film that is between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film; a protective film in contact with a surface of the oxide semiconductor film that is an opposite side of a surface in contact with the gate insulating film; and a pair of electrodes in contact with the oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor device, manufacturing the same, or display device including the same

To suppress a change in electrical characteristics and improve reliability in a transistor. The transistor includes a first gate electrode, a first insulating film over the first gate electrode, a second insulating film over the first insulating film, an oxide semiconductor film over the second insulating film, a source electrode electrically connected to the oxide semiconductor film, a drain electrode electrically connected to the oxide semiconductor film, a third insulating film over the oxide semiconductor film, a fourth insulating film over the third insulating film, a second gate electrode over the fourth insulating film, and a fifth insulating film over the second gate electrode.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Thin film transistor and manufacturing same

A method for manufacturing a thin film transistor include following steps. A substrate is provided.
Hon Hai Precision Industry Co., Ltd.

new patent

Thin film transistor and manufacturing method thereof

A thin film transistor (tft) includes a gate, a gate insulation layer, a channel, a source, and a drain. The gate is formed on a substrate.
Hon Hai Precision Industry Co., Ltd.

new patent

Semiconductor devices and methods of fabricating the same

A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region.
Samsung Electronics Co., Ltd.

new patent

Semiconductor device, manufacturing the same, and evaluating semiconductor device

A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate..
Fujitsu Semiconductor Limited

new patent

Semiconductor device and a manufacturing the same

A semiconductor device includes an n channel conductivity type fet having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type fet having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel fet has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel fet to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel fet.
Renesas Electronics Corporation

new patent

Method for increasing stress in the channel region of fin field effect transistor

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an interlayer dielectric (ild) layer around the gate structure; removing the gate structure to form a recess; forming a stress layer in the recess, wherein the stress layer comprises metal; and forming a work function layer on the stress layer..
United Microelectronics Corp.

new patent

Semiconductor device having at least one stressor and manufacturing the same

A method of manufacturing a semiconductor device includes forming a word line trench in an active region, forming a gate dielectric layer to cover at least a portion of the word line trench, forming a word line within the word line trench to define a capping trench, and/or forming a stressor having a compressive stress within the capping trench. The stressor is formed by using a plasma source..
Samsung Electronics Co., Ltd.

new patent

Field effect transistor with elevated active regions and methods of manufacturing the same

A field effect transistor having a higher breakdown voltage can be provided by forming a contiguous dielectric material layer over gate stacks, forming via cavities laterally spaced from the gate stacks, selectively depositing a single crystalline semiconductor material, and converting upper portions of the deposited single crystalline semiconductor material into elevated source/drain regions. Lower portions of the selectively deposited single crystalline semiconductor material in the via cavities can have a doping of a lesser concentration, thereby effectively increasing the distance between two steep junctions at edges of a source region and a drain region.
Sandisk Technologies, Inc.

new patent

Semiconductor device

A semiconductor device includes a lateral transistor having: a semiconductor substrate including a drift layer; a first impurity layer in the drift layer; a channel layer in the drift layer; a second impurity layer in the channel layer; a separation insulation film on the drift layer between the channel layer and the first impurity layer; a gate insulation film on a channel region between the second impurity layer and the drift layer connected with the separation insulation film; a gate electrode on the gate insulation film and the separation insulation film; a first electrode connected with the first impurity layer; a second electrode connected with the second impurity layer and the channel layer; and a field plate on the separation insulation film between the gate electrode and the first electrode and connected with the first electrode. The field plate is larger than the gate electrode in a current direction..
Denso Corporation

new patent

Power integrated devices, electronic devices including the same, and electronic systems including the same

A power integrated device includes a semiconductor layer having first conductivity, a source region and a drain region each having second conductivity and disposed in the semiconductor layer, wherein the source region and the drain region are spaced apart from each other, a first drift region having the second conductivity, disposed in the semiconductor layer, and surrounding the drain region a second drift region having the second conductivity, disposed in the semiconductor layer, contacting a sidewall of the first drift region, and having an impurity concentration lower than an impurity concentration of the first drift region, a gate insulation layer disposed over a channel region between the source region and the second drift region and extending, over the second drift region a field insulation plate disposed over the second drift region and the first drift region, contacting a sidewall of the gate insulation layer, and having a planar structure, and a gate conductive pattern disposed over the gate insulation layer, wherein the gate conductive pattern extends over the field insulation plate.. .
Sk Hynix Inc.

new patent

High voltage semiconductor device and manufacturing the same

In embodiments, a high voltage semiconductor device includes a gate structure disposed on a substrate, a source region disposed at a surface portion of the substrate adjacent to one side of the gate structure, a drift region disposed at a surface portion of the substrate adjacent to another side of the gate structure, a drain region disposed at a surface portion of the drift region spaced from the gate structure, and an electrode structure disposed on the drift region to generate a vertical electric field between the gate structure and the drain region.. .
Dongbu Hitek Co. Ltd.

new patent

Semiconductor device capable of high-voltage operation

A semiconductor device includes a semiconductor substrate and a first well region formed in the semiconductor substrate. An insulator is formed in and over a portion of the first well region and a second well region is formed in the first well region at a first side of the insulator.
Mediatek Inc.

new patent

Semiconductor device

A control electrode ge1 is formed in a lower portion of a trench tr1 formed in a semiconductor substrate sub, and a gate electrode ge2 is formed in an upper portion inside the trench tr1. An insulating film g1 is formed between the control electrode ge1 and a side wall and a bottom surface of the trench tr1, an insulating film g2 is formed between the side wall of the trench tr1 and the gate electrode ge2, and an insulating film g3 is formed between the control electrode ge1 and the gate electrode ge2.

new patent

Structure and formation semiconductor device structure

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure.
Taiwan Semiconductor Manufacturing Co., Ltd

new patent

Crystalline-amorphous transition material for semiconductor devices and formation

The present disclosure presents a novel structure for a dielectric material for use with group iii-v material systems and a method of fabricating such a structure. More specifically, the present disclosure describes a novel dielectric layer that is formed on the top surface of a iii-v material where the dielectric layer comprises a first region in contact with the top surface of the iii-v material crystalline and a second region adjacent to the first region and at the upper side of the dielectric layer.
Toshiba Corporation

new patent

Semiconductor module with two auxiliary emitter conductor paths

A semiconductor module comprises a semiconductor chip comprising a semiconductor switch having a collector, emitter and gate, a collector terminal connected to the collector, gate terminal connected to the gate, an emitter terminal connected to the emitter via an emitter conductor path having an emitter inductance, an auxiliary emitter terminal connected to the emitter, a first conductor path connected to the emitter, and a second conductor path connected to the emitter having a different mutually inductive coupling with the emitter conductor path as the first conductor path. The first conductor path and the second conductor path are connectable to the auxiliary emitter terminal and/or the first conductor path is connected to the auxiliary emitter terminal and the second conductor path is connected to a second auxiliary emitter terminal.
Abb Schweiz Ag

new patent

Semiconductor device and manufacturing method thereof

A semiconductor device according to an embodiment includes a semiconductor layer. A gate dielectric film is provided on the semiconductor layer.
Kabushiki Kaisha Toshiba

new patent

Semiconductor device and manufacturing method thereof

A semiconductor device with a structure in which an increase in the number of oxygen vacancies in an oxide semiconductor layer can be suppressed and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an oxide insulating layer; intermediate layers apart from each other over the oxide insulating layer; a source electrode layer and a drain electrode layer over the intermediate layers; an oxide semiconductor layer that is electrically connected to the source electrode layer and the drain electrode layer and is in contact with the oxide insulating layer; a gate insulating film over the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and a gate electrode layer that is over the gate insulating film and overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer..
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor device and manufacturing method thereof

It is an object to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. An oxide semiconductor film serving as a channel formation region of a transistor is formed by a sputtering method at a temperature higher than 200° c., so that the number of water molecules eliminated from the oxide semiconductor film can be 0.5/nm3 or less according to thermal desorption spectroscopy.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor strips with undercuts and methods for forming the same

An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Trench power mosfet

A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Method of forming high voltage metal-oxide-semiconductor transistor device

A method of forming a hvmos transistor device is provided. A substrate is provided.
United Microelectronics Corp.

new patent

Semiconductor structure with an l-shaped bottom plate

A method of forming a semiconductor structure is provided. The method including forming a first vertical channel on a first layer of source/drain material that is perpendicular relative to the first vertical channel, and forming a first source/drain semiconductor structure by removing one or more portions of the first layer of source/drain material such that i) the first source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel and ii) a width of the source/drain is greater than a width of the first vertical channel, wherein the first source/drain semiconductor structure extends perpendicularly from its vertical side farther than the first vertical channel extends perpendicularly from its vertical side..
International Business Machines Corporation

new patent

Method of manufacturing insulated gate switching device

A method of manufacturing an insulated gate switching device includes: forming a trench in a front surface of a semiconductor substrate; forming a gate insulating film in the trench; depositing an electrode layer made of semiconductor in the trench and on the front surface after forming the gate insulating film; polishing the electrode layer so as to remove a portion of the electrode layer on the front surface and expose an underlayer of the removed portion of the electrode layer; forming a cap insulating film in a surface layer of a portion of the electrode layer in the trench by heating the semiconductor substrate after exposing the underlayer; and implanting impurities from above the front surface into a range extending across the portion of the electrode layer in the trench and the semiconductor substrate.. .
Toyota Jidosha Kabushiki Kaisha

new patent

Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation

semiconductor-oxide-containing gate dielectrics can be formed on surfaces of semiconductor fins prior to formation of a disposable gate structure. A high dielectric constant (high-k) dielectric spacer can be formed to protect each semiconductor-oxide-containing gate dielectric.
International Business Machines Corporation

new patent

Pmos transistor and fabrication method thereof

The disclosed subject matter provides a p-channel metal-oxide-semiconductor (pmos) and fabrication method thereof. The pmos transistor is fabricated by a method including forming a dummy gate structure on a semiconductor substrate, forming a source region and a drain region in the semiconductor substrate on both sides of the dummy gate structure, forming an intermediate layer to cover the dummy gate structure and the semiconductor substrate, and forming a multiple-level etching stop layer including at least a first etching stop layer and a second etching stop layer.
Semiconductor Manufacturing International (shanghai) Corporation

new patent

Sidewall passivation for hemt devices

Some embodiments of the present disclosure relate to a high electron mobility transistor (hemt) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary iii/v semiconductor layer made of a first iii-nitride material to act as a channel region of the e-hemt, and a ternary iii/v semiconductor layer arranged over the binary iii/v semiconductor layer and made of a second iii-nitride material to act as a barrier layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Silicon germanium heterojunction bipolar transistor structure and method

Disclosed is an improved semiconductor structure (e.g., a silicon germanium (sige) hetero-junction bipolar transistor) having a narrow essentially interstitial-free sic pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the sic pedestal to produce both a narrow sic pedestal and an essentially interstitial-free collector.
Ultratech, Inc.

new patent

Methods of forming replacement fins for a finfet device using a targeted thickness for the patterned fin etch mask

One method disclosed herein includes, among other things, forming a patterned fin having a thickness that is equal to or greater than a target final fin height for a replacement fin, performing an etching process through the patterned fin etch mask to form a plurality of trenches in a semiconductor substrate to define a substrate fin and forming a recessed layer of insulating material in the trenches so as to expose the patterned fin etch. The method also includes forming a layer of cte-matching material around the exposed patterned fin etch mask, removing the patterned fin etch mask to thereby define a replacement fin cavity and expose a surface of the substrate fin, forming the replacement fin on the substrate fin and in the replacement fin cavity, removing the layer of cte-matching material and forming a gate structure around at least a portion of the replacement fin..
International Business Machines Corporation

new patent

Method for manufacturing insulated gate type switching device, and insulated gate type switching device

A method is provided for manufacturing an insulated gate type switching device. The method includes: implanting second conductivity type impurities into a surface of a semiconductor substrate so as to form a second region of a second conductivity type in the surface; forming a third region of the second conductivity type having a second conductivity type impurity density lower than the second region on the surface by epitaxial growth: and forming a trench gate electrode..
Denso Corporation

new patent

Thin film device with protective layer

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided.
International Business Machines Corporation

new patent

Method for fabricating semiconductor device

The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ild) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ild), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ild), and filling a second conductive type metal layer in the gap.. .
Nanya Technology Corp.

new patent

Semiconductor device

In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion.
Panasonic Intellectual Property Management Co., Ltd.

new patent

Integrated circuits and methods for fabricating integrated circuits having replacement metal gate electrodes

Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes defining a pfet region and an nfet region of a semiconductor substrate.
Globalfoundries, Inc.

new patent

Semiconductor structure

A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface.
United Microelectronics Corp.

new patent

Semiconductor component and fabricating the same

A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Semiconductor memory device including slimming structure

Disclosed is a semiconductor memory device, including: a slimming structure extended from a cell structure in a direction parallel to the semiconductor substrate, the cell structure having a plurality of cell transistors stacked over a semiconductor substrate; vertical insulating materials extended in a direction crossing the semiconductor substrate and configured to divide the cell structure and the slimming structure into a plurality of memory blocks; contact plugs passing through the vertical insulating materials, respectively, within an area in which the slimming structure is formed; and junctions formed within the semiconductor substrate under the vertical insulating materials, in which the junctions are coupled to the contact plugs, respectively.. .
Sk Hynix Inc.

new patent

Method for forming via profile of interconnect structure of semiconductor device structure

A method for forming the semiconductor device structure is provided. The method includes forming a first metal layer over a substrate and forming a dielectric layer over the first metal layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Stripe-shaped electrode structure including a main portion with a field electrode and an end portion terminating the electrode structure

A semiconductor device includes a stripe-shaped electrode structure that extends from a first surface into a semiconductor portion. The electrode structure includes a main portion and an end portion terminating the electrode structure.
Infineon Technologies Ag

new patent

Silicon carbide semiconductor device and manufacturing same

A silicon carbide epitaxial layer includes: a first impurity region; a second impurity region; and a third impurity region. A gate insulating film is in contact with the first impurity region, the second impurity region, and the third impurity region.
Sumitomo Electric Industries, Ltd.

new patent

Semiconductor device

A semiconductor device is provided with a semiconductor substrate and a trench gate. The semiconductor substrate is provided with a drift region of a first conductive type, wherein the drift region is in contact with the trench gate; a body region of a second conductive type, wherein the body region is disposed above the drift region and is in contact with the trench gate; a source region of the first conductive type, wherein the source region is disposed above the body region, exposed on the front surface of the semiconductor substrate and is in contact with the trench gate; and a front surface region of the second conductive type, wherein the front surface region is disposed above the source region, exposed on the front surface of the semiconductor substrate and is in contact with the trench gate..
Toyota Jidosha Kabushiki Kaisha

new patent

Aspect ratio for semiconductor on insulator

A method comprises forming one or more fins in a first region on an insulated substrate. The method also comprises forming one or more fins formed in a second region on the insulated substrate.
International Business Machines Corporation

new patent

Semiconductor device having an inactive-fin and a forming the same

A semiconductor device includes a multi-fin active region having a plurality of sub-fins sequentially arranged on a substrate. A gate electrode crosses the multi-fin active region.

new patent

Finfets with high quality source/drain structures

A semiconductor structure is provided that includes a silicon germanium alloy fin located on a portion of a topmost surface of an insulator layer. A functional gate structure straddles a portion of the silicon germanium alloy fin and is located on other portions of the topmost surface of the insulator layer.
International Business Machines Corporation

new patent

Process for producing mos transistors having a larger channel width from an soi and in particular fdsoi substrate, and corresponding integrated circuit

An integrated circuit includes a substrate with an isolation region that bounds a zone. A transistor includes a concave semiconductor region that is supported by the isolation region in a first direction and has a concavity turned to face towards the zone.
Stmicroelectronics (crolles 2) Sas

new patent

Method for local isolation between transistors produced on an soi substrate, in particular an fdsoi substrate, and corresponding integrated circuit

An integrated circuit may include an soi substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first mos transistors and also first dummy gate regions.
Stmicroelectronics (crolles 2) Sas

new patent

High voltage field balance metal oxide field effect transistor (fbm)

A semiconductor device includes a semiconductor substrate and epitaxial layer of a first conductivity type with the epitaxial layer on a top surface of the substrate. A body region of a second conductivity type opposite the first conductivity type is disposed near a top surface of the epitaxial layer.
Alpha And Omega Semiconductor Incorporated

new patent

Configurations and methods for manufacturing charged balanced devices

This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate.

new patent

Semiconductor apparatus

A semiconductor apparatus includes a semiconductor substrate including a device region and a peripheral region. The peripheral region includes guard rings.
Toyota Jidosha Kabushiki Kaisha

new patent

Semiconductor integrated circuit

A semiconductor integrated circuit includes an inductor and a plurality of high permeability patterns. The inductor includes one conductive loop.
Mediatek Inc.

new patent

Image sensor, manufacturing the same, and image processing device having the image sensor

An image sensor comprising: a first layer having a plurality of groups of photodiodes formed in a semiconductor substrate, each group representing a 2×2 array of photodiodes, with 2 first pixels configured to detect light of a first wavelength and 2 second pixels configured to detect light of a second wavelength, each first pixel positioned adjacent to the second pixels; and a second layer overlapping the first layer, the second layer is organic, having a plurality of organic photodiodes configured to detect light of a third wavelength, each organic photodiode positioned to partially overlap 2 first photodiodes and 2 second photodiodes of the first layer.. .
Samsung Electronics Co., Ltd.

new patent

Semiconductor memory device

In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films.
Kabushiki Kaisha Toshiba

new patent

Recessed high voltage metal oxide semiconductor transistor for rram cell

A recessed high voltage metal oxide semiconductor (mos) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed mos transistor.
Crossbar, Inc.

new patent

Semiconductor memory device and manufacturing the same

According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate.
Kabushiki Kaisha Toshiba

new patent

Semiconductor memory and manufacturing the same

A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode..
Kabushiki Kaisha Toshiba

new patent

Method of forming an infrared filter associated with an image sensor

An image sensor having a portion including interconnection levels formed on a semiconductor substrate covered with a first layer of a dielectric material, including conductive tracks separated from one another by insulating layers interconnected by vias crossing the insulating layers, and an infrared bandpass filter comprising filter levels adjacent to the interconnection levels formed by an alternation of second layers of the dielectric material and of silicon layers, the refraction index of the dielectric material being smaller than 2.5 at the maximum transmission wavelength of the filter, one of the second dielectric layers of each filter level being identical to the insulating layer of the adjacent interconnection level.. .
Commissariat à I'Énergie Atomique Et Aux Énergies Alternatives

new patent

Image sensor with heating effect and related methods

An image sensor including a semiconductor layer. A light absorber layer couples with the semiconductor layer at a pixel of the image sensor and absorbs incident light to substantially prevent the incident light from entering the semiconductor layer.
Semiconductor Components Industries, Llc

new patent

Semiconductor device including a solid state imaging device

A semiconductor device is reduced in power consumption, the semiconductor device including a solid-state imaging device that includes pixels each having a plurality of light receiving elements. A pixel having first and second photodiodes is provided with a first transfer transistor that transfers charge in the first photodiode to a floating diffusion capacitance section, and a second transfer transistor that combines charge in the first photodiode and charge in the second photodiode, and transfers the combined charge to the floating diffusion capacitance section.
Renesas Electronics Corporation

new patent

Solid-state imaging device, manufacturing the same, and electronic apparatus

The solid-state imaging device includes a photoelectric conversion film that performs photoelectric conversion of light emitted from the back surface side of the semiconductor substrate. Also, in each pixel, a charge accumulation layer is formed to be in contact with the photoelectric conversion film on the back surface of the semiconductor substrate, a transfer path unit is formed to extend from the charge accumulation layer to a point near the front surface of the semiconductor substrate, and a memory unit is disposed near the back surface side of the semiconductor substrate, with a charge transfer gate being interposed between the memory unit and the transfer path unit.

new patent

Manufacturing method and manufacturing equipment of thin film transistor substrate

A manufacturing method and a manufacturing equipment of a thin film transistor substrate are provided. In the manufacturing method, after forming a gate and a gate insulating layer of a thin film transistor, a semiconductor layer and a first protection layer are sequentially deposited.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

new patent

Semiconductor device and manufacturing the same

A region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are formed separately in one oxide semiconductor film. The region containing a high proportion of crystal components is formed so as to serve as a channel formation region and the other region is formed so as to contain a high proportion of amorphous components.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor device

An object is to provide a semiconductor device using an oxide semiconductor having stable electric characteristics and high reliability. A transistor including the oxide semiconductor film in which a top surface portion of the oxide semiconductor film is provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film and functioning as a channel protective film is provided.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Aspect ratio for semiconductor on insulator

A method comprises forming one or more fins in a first region on an insulated substrate. The method also comprises forming one or more fins formed in a second region on the insulated substrate.
International Business Machines Corporation

new patent

Semiconductor device, finfet transistor and fabrication method thereof

The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure..
Semiconductor Manufacturing International (shanghai) Corporation

new patent

Preventing strained fin relaxation

A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures.
International Business Machines Corporation

new patent

Semiconductor device and manufacturing the same

A semiconductor device that occupies a small area and has a high degree of integration is provided. The semiconductor device includes a first insulating layer, a conductive layer, and a second insulating layer.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor device and display device

A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Integrated circuit, semiconductor device based on intergrated circuit, and standard cell library

An integrated circuit (ic) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.. .
Samsung Electronics Co., Ltd.

new patent

Semiconductor device

Provided is a semiconductor device including a substrate, gate electrodes vertically stacked on the substrate, insulating patterns between the gate electrodes, an active pillar provided to penetrate the gate electrodes and the insulating patterns and electrically coupled with the substrate, and a memory pattern provided between the gate electrodes and the active pillar and between the insulating patterns and the active pillar. The gate electrodes include edge portions extending between the memory pattern and the insulating patterns..

new patent

Semiconductor device and manufacturing the same

A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.. .
Sk Hynix Inc.

new patent

Semiconductor device

A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor structure and forming the same

The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region.
United Microelectronics Corp.

new patent

Semiconductor device and manufacturing the same

One memory cell region includes memory cells that are aligned in a first direction and a second direction orthogonal to the first direction, a word line contact region adjacent to the memory cell region in the first direction interposed by a dummy pattern region, and first and second word lines that span a plurality of active regions aligned in the first direction and extend from the memory cell region to the word line contact region. A first word line and a second word line adjacent to each other within one active region located in the memory cell region constitute a word line pair.

new patent

Semiconductor device and driving semiconductor device

The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor.
Semiconductor Energy Laboratory Co., Ltd.

new patent

Semiconductor device

Provided is a semiconductor device including a gate structure, a first doped region of a first conductivity type, a plurality of second doped regions of a second conductivity type, a third doped region of the first conductivity type, and a plurality of fourth doped regions of the second conductivity type. The gate structure is located on a substrate.
Macronix International Co., Ltd.

new patent

Semiconductor devices including varied depth recesses for contacts

A first conductivity type finfet device can include first embedded sources/drains of a first material that have a first etch rate. The first embedded sources/drains can each include an upper surface having a recessed portion and an outer raised portion relative to the recessed portion.
Samsung Electronics Co., Ltd.

new patent

Semiconductor device and manufacturing the same

Provided are a semiconductor device in which a multi-threshold voltage is embodied by controlling a work function, and a method of manufacturing the same. The device includes a semiconductor substrate including a first region and a second region, a first active region formed in an upper portion of the first region of the semiconductor substrate, a second active region formed in an upper portion of the second region of the semiconductor substrate, a first gate structure formed on the semiconductor substrate across the first active region, the first gate structure including an interfacial layer, a high-k dielectric layer, a capping metal layer, and a work function metal layer that are stacked sequentially, and a second gate structure formed on the semiconductor substrate across the second active region, the second gate structure including the interfacial layer, the high-k dielectric layer, the capping metal layer, a dielectric layer, and the work function metal layer that are stacked sequentially..
Samsung Electronics Co., Ltd.

new patent

Structure and formation semiconductor device structure

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Switching device for switching radio frequency signals

The invention relates to a switching device for switching radio frequency signals. The switching devices comprises at least a first field effect transistor that comprises a first source node, a first gate node and a first drain node, wherein the first gate node is arranged between a first drain region and a first source region on a semiconductor substrate.
Rohde & Schwarz Gmbh & Co. Kg

new patent

Method for forming source/drain contacts during cmos integration using confined epitaxial growth techniques and the resulting semiconductor devices

A semiconductor device includes an isolation region laterally defining an active region in a semiconductor substrate, a gate structure positioned above the active region, and a sidewall spacer positioned adjacent to sidewalls of the gate structure. An etch stop layer is positioned above and covers a portion of the active region, an interlayer dielectric material is positioned above the active region and covers the etch stop layer, and a confined raised source/drain region is positioned on and in contact with an upper surface of the active region.
Globalfoundries Inc.

new patent

Semiconductor structure with a spacer layer

A multi-layer semiconductor structure is disclosed for use in iii-nitride semiconductor devices, including a channel layer, a band-offset layer having a wider bandgap than the channel layer, a spacer layer having a narrower bandgap than the band-offset layer, and a cap layer comprising at least two sublayers. Each sublayer is selectively etchable with respect to sublayers immediately below and above, each sublayer comprises a iii-n material alxinygazn in which 0≦x≦1, 0≦y≦1, and 0≦z≦1, at least one sublayer has a non-zero ga content, and a sublayer immediately above the spacer layer has a wider bandgap than the spacer layer.
Cambridge Electronics, Inc.

new patent

Semiconductor structure and manufacturing process thereof

A process of manufacturing a semiconductor structure is provided. The process begins with forming a work function metal layer on a substrate, and a hardmask is covered over the work function metal layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Semiconductor device

In a plan view of a semiconductor substrate, the semiconductor substrate includes a pillar exposing area in which the pillar region is exposed on the front surface of the semiconductor substrate, a pillar contacting area in which the pillar region is in contact with a deeper side of the anode contact region, and an anode contacting area in which the anode region is in contact with the deeper side of the anode contact region. In a direction along which the pillar contacting area and the anode contacting area are aligned, a width of the pillar contacting area is smaller than a width of the anode contacting area..
Toyota Jidosha Kabushiki Kaisha

new patent

Reverse conducting igbt

A reverse conducting igbt is provided with a trench gate member that is provided in an igbt region and has a lattice-pattern layout, and a trench member that is provided in a diode region and has a stripe-pattern layout. The diode region of the semiconductor substrate includes an anode region of a first conductive type, a drift region of a second conductive type and a barrier region of the second conductive type.
Toyota Jidosha Kabushiki Kaisha

new patent

Schottky barrier diode

An sbd includes a semiconductor substrate; an anode electrode which is in schottky contact with a front surface of the semiconductor substrate; and a cathode electrode which is in ohmic contact. With a rear surface of the semiconductor substrate.
Toyota Jidosha Kabushiki Kaisha

new patent

Operational gallium nitride devices

A power circuit is described that includes a semiconductor body having a common substrate and a gallium nitride (gan) based substrate. The gan based substrate includes one or more gan devices adjacent to a front side of the common substrate.
Infineon Technologies Austria Ag

new patent

Fin type electrostatic discharge protection device

A fin type esd protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin.
United Microelectronics Corp.

new patent

Semiconductor device comprising electrostatic discharge protection structure

A semiconductor device includes a semiconductor body having first and second opposing surfaces, a first isolation layer on the first surface of the semiconductor body, and an electrostatic discharge protection structure. The electrostatic discharge protection structure includes a diode structure on the first isolation layer, a first terminal and a second terminal.
Infineon Technologies Dresden Gmbh

new patent

Variable capacitance device

A variable capacitance device that includes a semiconductor substrate, a redistribution layer disposed on a surface of the semiconductor substrate, and a plurality of terminal electrodes including first and second input/output terminals, a ground terminal and a control voltage application terminal. Moreover, a variable capacitance element section is formed in the redistribution layer from a pair of capacitor electrodes connected to the first and second input/output terminals, respectively, and a ferroelectric thin film disposed between the capacitor electrodes.
Murata Manufacturing Co., Ltd.

new patent

Semiconductor device with modified current distribution

semiconductor devices having modified current distribution and methods of forming the same are described herein. As an example, a memory die in contact with a logic die can be configured to draw a sum amount of current from a current source.
Micron Technology, Inc.

new patent

Light-emitting arrangement and producing a light-emitting arrangement

A light-emitting arrangement includes a radiation-emitting semiconductor chip that, during operation, emits primary radiation at least from a main emission surface, a first conversion element that absorbs part of the primary radiation and emits secondary radiation, and a deflection element that causes a direction change for part of the primary radiation, wherein the first conversion element is arranged in a lateral direction next to the radiation-emitting semiconductor chip, the deflection element guides part of the primary radiation onto the first conversion element, and the light-emitting arrangement, in operation, emits mixed light including the primary radiation and the secondary radiation.. .
Osram Opto Semiconductors Gmbh

new patent

Thermally enhanced face-to-face semiconductor assembly with built-in heat spreader and making the same

A face-to-face semiconductor assembly is characterized in that first and second semiconductor devices are face-to-face mounted on two opposite sides of a first routing circuitry and is further electrically connected to an interconnect board through the first routing circuitry. The interconnect board has a heat spreader to provide thermal dissipation for the second semiconductor device, and a second routing circuitry formed on the heat spreader and electrically coupled to the first routing circuitry.
Bridge Semiconductor Corporation

new patent

Semiconductor device having stacked chips

According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, wherein these chips are stacked to be electrically connected via the first and second vias.
Kabushiki Kaisha Toshiba

new patent

Printed circuit board, method, and semiconductor package

A printed circuit board includes first and second insulating layers forming a cavity, a first heat releasing layer formed on an exterior surface of the cavity, and a circuit layer formed above or below the first the insulating layer and at least between a surface of the cavity and the first insulating layer. The heat releasing layer is electrically connected to at least a portion of the circuit layer..
Samsung Electro-mechanics Co., Ltd.

new patent

Semiconductor device

A semiconductor device includes a first substrate, a second substrate stacked over the first substrate, and a pillar member extending obliquely between the first and second substrates. The first substrate includes a mounting surface on which a semiconductor chip is mounted, with a resin interposed between the semiconductor chip and the mounting surface and extending beyond the periphery of the semiconductor chip on the mounting surface.
Shinko Electric Industries Co., Ltd.

new patent

Semiconductor device

According to one embodiment, a semiconductor device includes a first semiconductor chip including a first circuit, a second circuit, a first interconnect connected to the first circuit, a second interconnect connected to the second circuit, and a third interconnect connecting the first interconnect and the second interconnect.. .
Kabushiki Kaisha Toshiba

new patent

Semiconductor device

A semiconductor device includes a semiconductor chip in which a first bump is provided on a first surface, a plurality of first adhesives are provided on the first surface of the semiconductor chip, and a second adhesive is provided on the first surface of the semiconductor chip, and of which a layout area on the first surface is smaller than a layout area of the plurality of first adhesives. In comparison to a first adhesive that is farthest from the center or a moment of inertia of the first surface of the semiconductor chip among the plurality of the first adhesives, the second adhesive is provided farther from the center or the moment of inertia of the semiconductor chip..
Kabushiki Kaisha Toshiba

new patent

Semiconductor device and manufacturing semiconductor device

A semiconductor device includes a first substrate, an aluminum pad, a first nickel electrode, a second substrate, a second nickel electrode, and a connection layer. The first substrate includes a wiring therein.
Kabushiki Kaisha Toshiba

new patent

Wire bonding apparatus and manufacturing semiconductor device

A wire bonding apparatus includes: a bonding tool 40 into and through a wire 42 passes; a control unit 80 that performs a movement process of the bonding tool 40 for cutting the wire 42 after forming a wire loop 90 between first and second bonding points of a bonding target 100; and a monitoring unit 70 that supplies a predetermined electric signal between the wire 42 through the bonding tool 40 and the bonding target 100, and monitors whether the wire 42 is cut or not based on an output of the supplied electric signal. The control unit 80 continues the movement process of the bonding tool 40 while the wire 42 is determined not to be cut, and stops the movement process of the bonding tool 40 when the wire 42 is determined to be cut, based on a monitoring result from the monitoring unit 70.
Shinkawa Ltd.

new patent

Method of manufacturing semiconductor device and wire bonding apparatus

A method of manufacturing a semiconductor device includes: a wire tail forming step of forming a wire loop 130 between a first bonding point and a second bonding point with a bonding tool 40, and then cutting a portion of a wire 42 extending from a tip of the bonding tool 40 to thereby form a wire tail 43 at the tip of the bonding tool 40; and a wire tail bending step of bending the wire tail 43 so as to direct a tip 43a of the wire tail 43 upward by descending the bonding tool 40 toward the second bonding point with the wire loop 130 formed thereat and pressing the wire tail 43 against a portion of the wire loop 130 located above the second bonding point. Thus, the wire tail can be bent easily and efficiently..
Shinkawa Ltd.

new patent

Printed circuit boards having blind vias, testing electric current flowing through blind via thereof and manufacturing semiconductor packages including the same

A method of manufacturing a semiconductor package is provided. The method includes providing a strip substrate having a plurality of unit substrate regions that are spaced apart from each other by a periphery region and have blind vias, a peripheral conductive pattern layer disposed in the periphery region, and a connection pattern layer electrically connecting the blind vias to the peripheral conductive pattern layer.
Sk Hynix Inc.

new patent

Semiconductor devices and packages including conductive underfill material and related methods

semiconductor devices and device packages include at least one semiconductor die electrically coupled to a substrate through a plurality of conductive structures. The at least one semiconductor die may be a plurality of memory dice, and the substrate may be a logic die.
Micron Technology, Inc.

new patent

Bonding material, bonding method and semiconductor device for electric power

The present invention has an object to achieve bonding which satisfies both in heat resistivity and in stress-relaxation ability, and the bonding material according to this invention is a sheet-like bonding material 1 made of a silver-bismuth alloy which, when heated in a state being in contact with a metal material as a bonding target (for example, surface layers 2f, 3f), forms in the metal material (as its material, for example, gold, silver or copper) a diffusion layer ld2, ld3 of silver due to solid-phase diffusion reaction, so as to be bonded to the metal material, said bonding material being characterized by containing not less than 1 mass % but not more than 5 mass % of bismuth.. .
Mitsubishi Electric Corporation

new patent

Semiconductor device and manufacturing semiconductor device

A semiconductor device includes a semiconductor substrate provided with a through hole that extends therethrough from a first surface to a second surface on a side opposite to the first surface, a device layer provided at the first surface of the semiconductor substrate which includes an electrode, an insulating layer that covers the device layer, a first through electrode that extends through the insulating layer, an insulating layer that extends from the second surface of the semiconductor substrate to a bottom surface of the through hole through an inner surface of the through hole of the semiconductor substrate, and in which the portion thereof in contact with the bottom surface has a tapered shape, and a second through electrode electrically connected to the electrode in the device layer that is exposed to the bottom surface of the through hole.. .
Kabushiki Kaisha Toshiba

new patent

Semiconductor device

A semiconductor chip includes a substrate, an electrode pad formed on the substrate, an insulating layer covering the substrate and the electrode pad, and having an opening exposing a portion of a surface of the electrode pad, a first conductive layer formed on the exposed portion of the surface of the electrode pad and extending to a surface of the insulating layer, and a second conductive layer formed on the first conductive layer, covering the first conductive layer in a plan view, and having an outer edge portion which is located further out than an outer edge of the first conductive layer in a plan view. The outer edge portion of the second conductive layer has at least one curved portion.
Rohm Co., Ltd.

new patent

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Solder metallization stack and methods of formation thereof

A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.. .
Infineon Technologies Ag

new patent

Method of producing a semiconductor device with protruding contacts

A wiring (3) comprising electrical conductors (4, 5, 6, 7) is formed in a dielectric layer (2) on or above a semiconductor substrate (1), an opening is formed in the dielectric layer to uncover a contact pad (8), which is formed by one of the conductors, and a further opening is formed in the dielectric layer to uncover an area of a further conductor (5), separate from the contact pad. The further opening is filled with an electrically conductive material (9), and the dielectric layer is thinned from a side opposite the substrate, so that the electrically conductive material protrudes from the dielectric layer..
Ams Ag

new patent

Semiconductor device

A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body.
Renesas Electronics Corporation

new patent

Semiconductor package

A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of a, the stress relaxation layer has an elastic modulus of b, and the encapsulation material has an elastic modulus of c under a same temperature condition, the relationship of a>c>b or c>a>b is obtained..
J-devices Corporation

new patent

Thermosetting adhesive sheet and semiconductor device manufacturing method

A thermosetting adhesive sheet comprises a thermosetting binder, a transparent filler having an average primary particle diameter from 1 nm to 1000 nm and a colorant; wherein content of the transparent filler is from 30 to 100 pts. Mass with respect to 80 pts.
Dexerials Corporation

new patent

Creating unique device identification for semiconductor devices

Systems and methods for creating unique device identification for semiconductor devices are described. In some embodiments, a method may include receiving a wafer identification mark printed on a semiconductor wafer having a plurality of dies fabricated thereon; receiving a leadframe identification mark printed on a leadframe configured to receive the plurality of dies during a die attach operation; and for each of the plurality of dies: (a) recording a wafer location of a given die prior to the die attach operation; (b) recording a leadframe location of the given die after the die attach operation; (c) creating a device identification mark for the given die based upon the wafer identification mark, the leadframe identification mark, the wafer location, and the leadframe location; and (d) printing the device identification mark on a package of the given die..
Texas Instruments Incorporated

new patent

Power semiconductor module

A power semiconductor module includes: a positive arm and a negative arm that are formed by series connection of self-arc-extinguishing type semiconductor elements, the positive arm and the negative arm being connected at a series connection point between the self-arc-extinguishing type semiconductor elements; a positive-side electrode, a negative-side electrode, and an ac electrode connected to the positive arm and the negative arm; and a substrate on which a plurality of wiring patterns are formed, the wiring patterns connecting the self-arc-extinguishing type semiconductor elements of the positive arm and the negative arm to the positive-side electrode, the negative-side electrode, and the ac electrode. Respective directions of current flowing in adjacent wiring patterns are identical to each other, and one of the adjacent wiring patterns is arranged in mirror symmetry with the other of the adjacent wiring patterns..
Mitsubishi Electric Corporation

new patent

Semiconductor package and mounting structure thereof

A semiconductor package includes an interposer, a semiconductor element installed on a first surface of the interposer, bumps formed on a second surface of the interposer, and a chip component installed on the second surface of the interposer. The interposer is a silicon interposer; the semiconductor element is flip-chip mounted on the first surface of the interposer; the chip component is a thin film passive element formed by carrying out a thin film process on a silicon substrate, and a pad being formed on one surface of the thin film passive element; and the pad of the chip component is connected to a land formed on the second surface of the interposer using a conductive bonding material.
Murata Manufacturing Co., Ltd.

new patent

Method of manufacturing semiconductor device, and semiconductor device

A semiconductor device includes a semiconductor substrate provided with a through-hole, a device layer including a lower layer wiring, an insulating layer that covers the device layer, a first through-electrode that passes through the insulating layer, a first insulating film provided with an opening having a diameter that is substantially the same as or greater than an opening diameter of the through-hole of the semiconductor substrate, a second insulating film positioned on an upper side of the first insulating film and on an inner side surface of the through-hole of the semiconductor substrate, and a second through-electrode electrically connected to the lower layer wiring in the device layer from an upper side of the second insulating film through the inside of the through-hole of the semiconductor substrate.. .
Kabushiki Kaisha Toshiba

new patent

Semiconductor device

According to one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip outputs a first signal by a first bus width and includes a first via which transfers the first signal.
Kabushiki Kaisha Toshiba

new patent

Semiconductor device having air-gap and manufacturing the same

A semiconductor device in which an air-gap located at a side of a bit line stack is extended to an upper part of the bit line stack is disclosed. An embodiment includes: a bit line stack; a plurality of storage node contacts located at both sides of the bit line stack; and an air-gap located between the bit line stack and the storage node contacts, and extended above the bit line stack..
Sk Hynix Inc.

new patent

Via, trench or contact structure in the metallization, premetallization dielectric or interlevel dielectric layers of an integrated circuit

A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate.
Stmicroelectronics, Inc.

new patent

Semiconductor device and electronic device

A semiconductor device includes a semiconductor substrate, a through hole via which pierces the semiconductor substrate, and a wiring layer (multilayer wirings) disposed under the semiconductor substrate and including plural layers of a group of lands disposed under the through hole via. The group of lands includes a land in a first layer which is disposed on an under surface of the through hole via and which is equal in external size to or smaller in external size than the through hole via in planar view and a land in a second layer which is disposed under the land in the first layer and which is larger in external size than the land in the first layer in the planar view.
Fujitsu Limited

new patent

Cobalt-containing conductive layers for control gate electrodes in a memory structure

A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a backside blocking dielectric layer is formed in the backside recesses and sidewalls of the memory stack structures.
Sandisk Technologies Llc

new patent

Semiconductor structure and fabrication method thereof

A method for fabricating a semiconductor structure includes providing a dielectric layer on a semiconductor substrate, forming an opening in the dielectric layer to expose a portion of the surface of the semiconductor substrate, forming a metal layer to fill up the opening, and removing the portion of the metal layer formed above the top surface of the dielectric layer by polishing. A metal oxide layer is formed on the surface of the metal layer after polishing.
Semiconductor Manufacturing International (shanghai) Corporation

new patent

Semiconductor device and manufacturing the same

A semiconductor device is provided, which includes a first conductive layer disposed on a substrate, a dielectric layer with at least an opening disposed on the first conductive layer, and a plurality of plugs filling up the openings. At least a portion of the dielectric layer adjacent to the openings is si-rich, and each of the plugs includes a second conductive layer surrounded by a barrier layer..
Macronix International Co., Ltd.

new patent

Semiconductor device and manufacturing semiconductor device

A through electrode and a multilayer wiring are provided on a semiconductor substrate, and a bottom layer connection wiring, a lower layer connection wiring, an upper layer connection wiring, and a top layer connection wiring are provided in the multilayer wiring. The through electrode is connected to the bottom layer connection wiring, and a via is arranged at a position other than a position immediately above the through electrode..
Kabushiki Kaisha Toshiba

new patent

Semiconductor device and manufacturing the same

The semiconductor device 1 includes an insulating substrate 2, a conductive part 3 that extends in a first direction, a conductive part 4 that is separated in a second direction and extends in the first direction, conductive parts 5 that are lined along the first direction between the part 3 and the part 4, high-side switches 11, 12 and 13, low-side switches 14, 15 and, signal terminals that are arrayed along the first direction, a power supply terminal 21 that is electrically connected to the part 3, a ground terminal 22 that is electrically connected to the part 4, and output terminals 23, 24 and 25 that are electrically connected respectively to the corresponding parts 5, arrayed along the first direction on the other end side of the substrate 2, and provided over a straight line l that passes through the part 4 and extends in the first direction.. .
Shindengen Electric Manufacturing Co., Ltd.

new patent

Semiconductor device and production method therefor

Provided is a semiconductor device having a wiring structure on a semiconductor element and capable of securing high quality and high reliability in response to the desire for high-temperature operations, a large-current specification, thinner wafers, smaller device size, and reduced loss. A semiconductor device that includes an insulating circuit board; a semiconductor element implemented on the insulating circuit board; a first insulating resin layer laminated on the insulating circuit board; a copper-plated wiring which contacts the semiconductor element via a window portion formed in the first insulating resin layer, which enables contact with the semiconductor element; and a second insulating resin layer laminated so as to seal the copper-plated wiring, and a method for producing the semiconductor device are provided..
Fuji Electronic Co., Ltd

new patent

Semiconductor device and forming substrate including embedded component with symmetrical structure

A semiconductor device comprises a first conductive layer. A second conductive layer is formed over the first conductive layer.
Stats Chippac, Ltd.

new patent

Semiconductor module and drive device equipped with semiconductor module

Provided is a semiconductor module having an integrated insulating sheet structure, wherein detachment of the insulating sheet can be suppressed and improved reliability of the semiconductor module is achieved, by adopting a structure in which at least one location of the insulating sheet is sunken inside a mold, and a sealing resin body and the insulating sheet of the semiconductor module form a protrusion.. .
Mitsubishi Electric Corporation

new patent

Molded module

An object of this invention is to obtain a molded module with which improvements are achieved in the packaging ability and heat dissipation performance of an inverter module itself, and in the mounting capacity of a peripheral mounting component such as a substrate, which must be taken into consideration in relation to the shape of the module. Provided is a molded module for use in power electronics, having an inbuilt semiconductor element used to supply and control a large amount of power, the molded module including at least one semiconductor switching element provided in the module and a lead frame that dissipates heat from the switching element and electrically connects an element packaged in the module to an external circuit, wherein at least one end of the module is molded in a curved shape or a polygonal shape..
Mitsubishi Electric Corporation

new patent

Power module

A power module includes a substrate, a first sub-module and a second sub-module. Each of the first sub-module and the second sub-module includes a semiconductor switch and a diode.
Delta Electronics Int'l (singapore) Pte Ltd

new patent

Package for a surface-mount semiconductor device and manufacturing method thereof

A method for manufacturing a surface-mount electronic device includes making a first partial cut from a bottom of an assembly that includes a first semiconductor body that is disposed on a first die pad, a second semiconductor body that is disposed on a second die pad, and a plurality of terminal regions that is disposed between the first and second die pads. The first partial cut forms a recess by removing a portion of each of the terminal regions.
Stmicroelectronics S.r.l.

new patent

Process for manufacturing a surface-mount semiconductor device, and corresponding semiconductor device

A process for manufacturing surface-mount semiconductor devices, in particular of the quad-flat no-leads multi-row type, comprising providing a metal leadframe, in particular a copper leadframe, which includes a plurality of pads, each of which is designed to receive the body of the device, the pads being separated from adjacent pads by one or more rows of wire-bonding contacting areas, outermost rows from among the one or more rows of wire-bonding contacting areas identifying, together with outermost rows corresponding to the adjacent pads, separation regions.. .
Stmicroelectronics S.r.l.

new patent

Semiconductor device including lead frames with downset

A semiconductor device includes a planar first lead frame including a die pad, a semiconductor chip coupled to the die pad, and a second lead frame coupled to the first lead frame. The second lead frame includes leads arranged such that the die pad is downset with respect to the leads..
Infineon Technologies Ag

new patent

Semiconductor device and fabricating semiconductor device

A semiconductor device includes: a semiconductor substrate; a wiring layer provided on a front-surface side of the semiconductor substrate; a through-via that penetrates through the semiconductor substrate from a back-surface side of the semiconductor substrate and is coupled to a wire included in the wiring layer; and a stress relaxation part that protrudes toward a through-via side and is disposed on a section in the wire and coupled to the through-via, the stress relaxation part including at least one insulating portion containing an insulating material having a smaller thermal expansion coefficient than a material of the through-via.. .
Fujitsu Limited

new patent

Semiconductor device and producing semiconductor device

A semiconductor device includes a semiconductor substrate, a device layer located at an upper surface of the semiconductor substrate, an insulating layer located on the device layer, and a through electrode. The through electrode includes a body located in a through hole provided in the insulating layer and a head located on the body and the insulating layer and is electrically connected to an upper-layer wiring in the device layer.
Kabushiki Kaisha Toshiba

new patent

Integrated circuit device and manufacturing the same

An integrated circuit device is provided as follows. A connection terminal is disposed on a first surface of a semiconductor structure.

new patent

Method for manufacturing component built-in substrate

A substrate is disclosed, which can remove heat from a stacked body of semiconductor elements through a phase change of a coolant. The substrate of the application includes: a stacked body of semiconductor elements; a first channel forming a path, receiving circulation of a first coolant, in a surface of the stacked body; and a second channel forming a path, receiving circulation of a second coolant having a boiling point higher than the boiling point of the first coolant, in an inter-layer portion of the stacked body..
Fujitsu Limited

new patent

Semiconductor device

In a semiconductor device, a first to a sixth switching elements are joined to a second main surface of a substrate with their electrode surfaces facing the second main surface of the substrate. Non-electrode surfaces of the switching elements are provided with respective heat spreaders joined thereto.
Jtekt Corporation

new patent

Limiting electronic package warpage

An electronic package includes a carrier, semiconductor chip, a lid, and a lid-ring. The carrier includes a top surface and a bottom surface configured to be electrically connected to a system board.
International Business Machines Corporation

new patent

Semiconductor structure having thermal backside core

A semiconductor structure includes a semiconductor substrate having a recess disposed beneath a semiconductor device. The semiconductor structure also includes a thermally conductive core disposed in the recess, and a package substrate including a heat sink.
Avago Technologies General Ip (singapore) Pte. Ltd.

new patent

Semiconductor device package

Elastic modulus of the resin member is set in a prescribed range such that drift of an output voltage of the circuit is in a range within not less than 0.0 mv and not more than 1.5 mv.. .

new patent

Fan-out wafer level package and fabrication method thereof

A semiconductor package includes a semiconductor die having an active face. At least one pad is disposed on the active face of the semiconductor die.
Inotera Memories, Inc.

new patent

Epoxy resin composition for encapsulating semiconductor device and semiconductor device encapsulated by the same

An epoxy resin composition for encapsulating a semiconductor device and a semiconductor device encapsulated by the epoxy resin composition, the composition including a base resin; a filler; a colorant; and a thermochromic pigment, wherein a color of the thermochromic pigment is irreversibly changed when a temperature thereof exceeds a predetermined temperature.. .
Samsung Sdi Co., Ltd.

new patent

Embedded electronic packaging and associated methods

An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (lcp) body surrounding the semiconductor die and having openings therein receiving respective ones of the conductive pillars. A first interconnect layer is on the lcp body and contacts the openings.
Harris Corporation

new patent

Ion implantation methods and structures thereof

A method for fabricating a semiconductor device using a high-temperature ion implantation process includes providing a substrate including a plurality of fins. In some examples, a mask material is deposited and patterned to expose a group of fins of the plurality of fins and a test structure.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Test pattern structure for monitoring semiconductor fabrication process

A test pattern structure includes a substrate, a first layer formed over the substrate and including a plurality of box-shaped portions, and a second layer formed over the first layer and including a line portion that continuously extends across centers of the box-shaped portions.. .
Macronix International Co., Ltd.

new patent

Silicon-germanium fin formation

Forming a set of semiconductor fins is disclosed. Forming the set of semiconductor fins can include forming a base structure including a silicon substrate, an insulator layer stacked on the silicon substrate, and a plurality of silicon semiconductor fins each stacked directly on the insulator layer.
International Business Machines Corporation

new patent

Methods and mos capacitors in replacement gate process

Methods and apparatus for polysilicon mos capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer.
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent

Semiconductor device and manufacturing semiconductor device

A semiconductor device includes a semiconductor substrate, a metal member, and a metal oxide film. The semiconductor substrate is provided with a through-hole that passes through the semiconductor substrate from one surface to another surface opposite to the one surface.
Kabushiki Kaisha Toshiba

new patent

Method of manufacturing semiconductor device

A barrier metal is formed from a surface of an interlayer insulating film 2 to a trench that is formed in a semiconductor portion exposed in a contact hole. After rta treatment and a plasma nitriding process, a plug is embedded at an inner side of the barrier metal inside the trench and the contact hole.
Fuji Electric Co., Ltd.

new patent

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device may include forming an insulating layers on a substrate, forming a plurality of holes in an upper portion of the insulating layer, forming a mask layer having openings exposing at least a first set of the plurality of holes, etching a lower portion of the insulating layer exposed by one of the plurality of holes which is exposed by the mask layer to form a through hole in the insulating layer in combination with the one of the plurality of holes, and forming a conductive structure in the through hole.. .
Samsung Electronics Co., Ltd.

new patent

Semiconductor device and semiconductor device manufacturing method

According to present invention, a semiconductor device includes a semiconductor substrate formed of gaas, an adhesion layer formed of pd or an alloy containing pd on the semiconductor substrate, a barrier layer formed of co or an alloy containing co on the adhesion layer, and a metal layer formed of cu, ag or au on the barrier layer.. .
Mitsubishi Electric Corporation

new patent

Method of manufacturing semiconductor device

According to an embodiment, a method of manufacturing a semiconductor device includes forming a first opening that extends from a second surface of a semiconductor substrate opposite to a first surface toward the first surface and extending to a first insulating layer in the semiconductor substrate, performing a first annealing process in a first gas atmosphere that contains hydrogen after formation of the first opening, forming a second insulating layer on a side wall of the semiconductor substrate in the first opening, performing a second annealing process after formation of the second insulating layer, forming a second opening that extends to the conductive layer in the first insulating layer through the first opening, and forming a via that is connected to the conductive layer in the first and second openings.. .
Kabushiki Kaisha Toshiba

new patent

Method of manufacturing semiconductor device

According to one embodiment, a method of manufacturing a semiconductor device comprises forming a first insulating film and a wiring pattern and forming a second insulating film on the upper side of these. Further, a process of making holes in the second insulating film simultaneously at position where the wiring pattern is placed and position where the wiring pattern is not formed is performed.
Kabushiki Kaisha Toshiba

new patent

Aspect ratio for semiconductor on insulator

A method comprises forming one or more fins in a first region on an insulated substrate. The method also comprises forming one or more fins formed in a second region on the insulated substrate.
International Business Machines Corporation

new patent

High resistivity soi wafers and a manufacturing thereof

A high resistivity single crystal semiconductor handle structure for use in the manufacture of soi structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer.
Sunedison Semiconductor Limited

new patent

Shallow trench isolation trenches and methods for nand memory

A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a first dielectric material in the trench, forming a second dielectric material above the first dielectric material, forming a first air gap in the first dielectric material in the trench, and forming a second air gap in the second dielectric material above the first air gap..
Sandisk Technologies Inc.

new patent

Film for semiconductor back surface and its use

It is an object of the present invention to provide a film for semiconductor back surface having reworkability, and an application of the film. A film for semiconductor back surface has: an adhering strength at 70° c.
Nitto Denko Corporation

new patent

Member peeling method, member processing method, and manufacturing semiconductor chip

A member peeling method includes a step for preparing a first member having a first main face and an outer edge thereof and a second member having a second main face and an outer edge thereon, a step for disposing a photothermal conversion layer on at least one portion of the outer edge on the first main face, a step for mutually joining the first main face and the second main face via an adhesive layer, a step for irradiating a laser light to the photothermal conversion layer, and a step for at least partially peeling the first member from the second member by applying a force to an outer peripheral portion of either of the first member or the second member in a direction away from the other member.. .
3m Innovative Properties Company

new patent

Light irradiation type heat treatment apparatus

A plurality of support pins that support a semiconductor wafer are located upright on a top surface of a susceptor. A condenser lens is located on a bottom surface of the susceptor opposite to the support pins with respect to the susceptor.
Screen Holdings Co., Ltd.

new patent

Semiconductor apparatus and adjustment method

A semiconductor apparatus is provided. The semiconductor apparatus includes a wafer chuck configured to hold a wafer, and a first nozzle configured to dispense first chemical liquid onto the wafer.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Semiconductor device and balancing surfaces of an embedded pcb unit with a dummy copper pattern

A semiconductor device has a substrate. A conductive via is formed through the substrate.
Stats Chippac Pte. Ltd.

new patent

Semiconductor substrate for flash lamp anneal, anneal substrate, semiconductor device, and manufacturing semiconductor device

A semiconductor substrate for flash lamp anneal is used in a manufacturing process of performing ion implantation to form a p-n junction on a semiconductor substrate surface and recovering an ion implantation defect by the flash lamp anneal, carbon concentration of the semiconductor substrate being 0.5 ppma or less. Consequently, it is possible to provide the semiconductor substrate for flash lamp anneal which can easily and surely prevent the ion implantation defect from remaining in a device using a flash lamp anneal process..
Shin-etsu Handotai Co., Ltd.

new patent

Systems and methods for annealing semiconductor structures

Systems and methods are provided for annealing a semiconductor structure. In one embodiment, the method includes providing an energy-converting structure proximate a semiconductor structure, the energy-converting structure comprising a material having a loss tangent larger than that of the semiconductor structure; providing a heat reflecting structure between the semiconductor structure and the energy-converting structure; and providing microwave radiation to the energy-converting structure and the semiconductor structure.
Taiwan Semiconductor Manufacturing Company Limited

new patent

Method for processing a semiconductor layer, processing a silicon substrate, and processing a silicon layer

According to various embodiments, a method for processing a semiconductor layer may include: generating an etch plasma in a plasma chamber of a remote plasma source, wherein the plasma chamber of the remote plasma source is coupled to a processing chamber for processing the semiconductor layer; introducing the etch plasma into the processing chamber to remove a native oxide layer from a surface of the semiconductor layer and at most a negligible amount of semiconductor material of the semiconductor layer; and, subsequently, depositing a dielectric layer directly on the surface of the semiconductor layer.. .
Infineon Technologies Ag

new patent

Hybrid fin cutting processes for finfet semiconductor devices

One illustrative method disclosed herein includes, among other things, forming a fin-removal masking layer comprised of a plurality of line-type features, each of which is positioned above one of the fins, and a masking material positioned at least between adjacent features of the fin-removal masking layer and above portions of an insulating material in the trenches between the fins. The method also includes performing an anisotropic etching process through the fin-removal masking layer to remove the portions of the fins to be removed..
Globalfoundries Inc.

new patent

Method for forming patterns for semiconductor device

A method for forming patterns for semiconductor device includes following steps. A substrate is provided.
United Microelectronics Corp.

new patent

Methods for manufacturing a semiconductor device

Carbon-containing patterns are formed on an etch target layer, side surfaces of the carbon-containing patterns are treated by a hydrophilic process, poly-crystalline silicon spacers are formed on the side surfaces of the carbon-containing patterns after the hydrophilic process has been performed, and the etch target layer is patterned using the poly-crystalline silicon spacers as an etch mask.. .
Samsung Electronics Co., Ltd.

new patent

Semiconductor device and manufacturing semiconductor device

A method of manufacturing a semiconductor device, where the device includes a donor layer that is obtained by changing a crystal defect formed in a first-conduction-type drift layer by proton radiation into a donor and in which the donor layer has an impurity concentration distribution including a first portion with a maximum impurity concentration and a second portion with a concentration gradient in which the impurity concentration is reduced from the first portion to both surfaces of the first-conduction-type drift layer. The method includes performing proton radiation for a first-conduction-type semiconductor substrate which will be the first-conduction-type drift layer to form a crystal defect in the first-conduction-type semiconductor substrate; and performing a heat treatment at a temperature equal to or higher than 300° c.
Fuji Electric Co., Ltd.

new patent

Systems and methods for bidirectional device fabrication

Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer.
Ideal Power Inc.

new patent

Semiconductor element manufacturing method

Disclosed is a method of manufacturing a semiconductor element by implanting a dopant to a substrate to be processed. High frequency plasma is generated within a processing container by using microwaves.
Tokyo Electron Limited

new patent

Semiconductor device manufacturing method

A resist layer is applied to a metal film disposed on a semiconductor substrate, using a positive photoresist having photosensitivity to at least one wavelength. The resist layer is exposed to light including a region of the one wavelength.
Mitsubishi Electric Corporation

new patent

Semiconductor structure including patterned feature

A multiple patterning method is provided. The multiple patterning method includes providing a substrate; and forming a sacrificial film on the substrate.
Semiconductor Manufacturing International (shangha) Corporation

new patent

Embedded gallium-nitride in silicon

A method and structure for integrating gallium nitride into a semiconductor substrate. The method may also include means for isolating the gallium nitride from the semiconductor substrate..
International Business Machines Corporation

new patent

Semiconductor device

A semiconductor device includes a semiconductor layer formed of a iii-v group semiconductor crystal containing as as a primary component of a v group. A v group element other than as has been introduced at a concentration of 0.02 to 5% into a v group site of the iii-v group semiconductor crystal in the semiconductor layer..
Furukawa Electric Co., Ltd.

new patent

Semiconductor nanowire fabrication

Methods are provided for fabricating semiconductor nanowires on a substrate. A nanowire template is formed on the substrate.
International Business Machines Corporation

new patent

Modification processing method and manufacturing semiconductor device

A modification processing method includes preparing a substrate having a silicon layer on which a damage layer is formed through plasma processing. The method further includes removing the damage layer formed on the silicon layer by processing the substrate with a first process gas containing a fluorine gas..
Tokyo Electron Limited

new patent

Embedded gallium-nitride in silicon

A method and structure for integrating gallium nitride into a semiconductor substrate. The method may also include means for isolating the gallium nitride from the semiconductor substrate..
International Business Machines Corporation

new patent

Semiconductor devices including semiconductor structures and methods of fabricating the same

semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a semiconductor device includes a semiconductor structure.
Gm Global Technology Operations Llc

new patent

Plasma processing apparatus and focus ring

A plasma processing apparatus includes a chamber, a mounting table 2 and a focus ring 8. The chamber is configured to process a semiconductor wafer w with plasma.
Tokyo Electron Limited

new patent

Ion beam scanner for an ion implanter

A magnetic system for uniformly scanning an ion beam across a semiconductor wafer comprises a magnetic scanner having ac and dc coil windings each of which extend linearly along internal pole faces of a magnetic core. The ac and dc coil windings are mutually orthogonal; a time dependent magnetic component causes ion beam scanning whilst a substantially static (dc) field component allows the ion beam to be bent in an orthogonal plane.
Nissin Ion Equipment Co., Ltd.

new patent

Photoelectric conversion element

A photoelectric conversion element has a photoelectric conversion cell. The cell includes a first base material having a transparent substrate, a second base material facing the first base material, and an oxide semiconductor layer provided between the first base material and the second base material.
Fujikura, Ltd.

new patent

Composition and making picocrystalline artificial carbon atoms

Materials containing picocrystalline quantum dots that form artificial atoms are disclosed. The picocrystalline quantum dots (in the form of boron icosahedra with a nearly-symmetrical nuclear configuration) can replace corner silicon atoms in a structure that demonstrates both short range and long-range order as determined by x-ray diffraction of actual samples.
Seminuclear, Inc.

new patent

Semiconductor memory device and test operation method thereof

A semiconductor memory device includes: a word line driving unit suitable for performing activation operations for a plurality of normal word lines and a plurality of redundancy word lines in response to test addresses; and a test control unit suitable for controlling a number of activations of each of the plural normal and redundancy word lines to be equal based on repair information corresponding to a repair target word line among the plural normal word lines during a test operation.. .
Sk Hynix Inc.

new patent

Semiconductor device

A semiconductor device includes a memory circuit, a first fifo, a second fifo and an input/output circuit. The memory circuit outputs data.
Kabushiki Kaisha Toshiba

new patent

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes memory units each includes a first transistor, memory cell transistors, and a second transistor serially coupled between first and second ends. A memory cell transistor of each memory unit has its gate electrode coupled to each other.
Kabushiki Kaisha Toshiba

new patent

Resistive memory

A memory device includes one or more first semiconductor ridges formed on a first semiconductor wafer. The first semiconductor ridges are configured to be first electrodes.
University Of Massachusetts

new patent

Semiconductor storage device

The disclosed invention provides a semiconductor storage device that creates no trouble, independently of power-on sequence. A semiconductor storage device includes a first power supply for the memory cells, a second power supply which is turned on independently of the first power supply and provided for a peripheral circuit which is electrically coupled to the memory cells, and a word line level fixing circuit for fixing the level of the word lines, which operates in accordance with turn-on of the first power supply.
Renesas Electronics Corporation

new patent

Semiconductor device suppressing bti deterioration

Disclosed herein is a device includes a command generation circuit that activates first and second command signals, an internal circuit that includes a plurality of transistors that are brought into a first operation state when at least one of the first and second command signals is activated, and an output gate circuit that receives a first signal output from the internal circuit, the output gate circuit being configured to pass the first signal when the second command signal is deactivated and to block the first signal when the second command signal is activated.. .
Micron Technology, Inc.

new patent

Reception circuit, adjusting timing in reception circuit, and semiconductor device

A reception circuit includes a control signal generation circuit that generates a first enable signal based on a strobe signal and a second enable signal based on a core clock signal and a pointer control signal. A pattern data generation circuit generates determination pattern data from the first enable signal.
Socionext Inc.

new patent

Electronic device

An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high..
Sk Hynix Inc.

new patent

Electronic device including a semiconductor memory

This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a contact plug; a first stack structure disposed over the contact plug and coupled to the contact plug, wherein the first stack structure includes a pinning layer controlling a magnetization of a pinned layer; and a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a mtj (magnetic tunnel junction) structure which includes the pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein a width of the first stack structure is larger than a width of the contact plug and a width of the second stack structure..
Sk Hynix Inc.

new patent

Electronic devices having semiconductor memory units and fabricating the same

Electronic devices have a semiconductor memory unit including a magnetization compensation layer in a contact plug. One implementation of the semiconductor memory unit includes a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer, and a contact plug arranged in at least one side of the variable resistance element and comprising a magnetization compensation layer.
Sk Hynix Inc.

new patent

Semiconductor device and semiconductor system

A semiconductor system may include a controller and a semiconductor device. The controller may output command/address signals.
Sk Hynix Inc.

new patent

Semiconductor device and operating method thereof

A semiconductor device includes memory blocks including a plurality of strings in which memory cells are coupled between select transistors; a peripheral circuit suitable for erasing or programming the select transistors and the memory cells, which are included in a selected memory block among the memory blocks; and a control circuit suitable for controlling the peripheral circuit to erase the select transistors and the memory cells, increasing a threshold voltage of the select transistors within a range below an erase level, and increasing the threshold voltage of the select transistors up to a program level.. .
Sk Hynix Inc.

new patent

Semiconductor devices having initialization circuits and semiconductor systems including the same

A semiconductor device may include a boot-up operation circuit configured for executing a boot-up operation during a boot-up operation period after a power supply voltage signal reaches a predetermined level. The boot-up operation circuit may be configured for generating a boot-up period signal.
Sk Hynix Inc.

new patent

Semiconductor device

According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller.
Kabushiki Kaisha Toshiba

new patent

Chip on film package and display device including the same

A chip on film (cof) package includes a base film, a semiconductor chip disposed on the base film, first signal wires, and second signal wires. The semiconductor chip includes a pads and a driving integrated circuit.
Samsung Electronics Co., Ltd.

new patent

Goa circuit based on oxide semiconductor thin film transistor

The present invention provides a goa circuit based on oxide semiconductor thin film transistor, which cannot only prevent the electrical leakage to raise the reliability of the goa circuit but also avoid the generation of the crossfire current in the non-function period by shorting the gate and the source of the fortieth thin film transistor (t40) in the first pull-down module (400) for avoiding the influence of the constant high voltage level (dch) to the pull-down holding of the first node by electrically coupling both the gate and the drain of the seventy-fifth thin film transistor (t75) in the pull-down holding module (600) to the first node (q(n)), and clearing the interference of the residual charge to the goa circuit by providing the reset module (700) to reset the first node (q(n)) before generating the each frame to guarantee the normal output of the goa circuit and the normal display of the image.. .
Shenzhen China Star Optoelectronics Technology Co. Ltd.

new patent

Goa circuit based on ltps semiconductor tft

The present invention provides a goa circuit based on ltps semiconductor tft, comprising a plurality of goa units which are cascade connected, and n is set to be a positive integer and an nth goa unit comprises a pull-up control part (100), a pull-up part (200), a first pull-down part (400) and a pull-down holding part (500); the pull-down holding part (500) utilizes a high/low voltage reverse design and comprises a first, a second and a third dc constant low voltage levels (vss1, vss2, vss3) which are sequentially abated and a dc constant high voltage level (h), the influence of electrical property of the ltps semiconductor tft to the goa driving circuit, and particularly the bad function due to the electric leakage issue can be solved; meanwhile, the existing issue that the second node voltage level and the pull-down holding circuit part in the goa circuit based on the ltps semiconductor tft cannot be at higher voltage level in the non-functioning period can be solved to effectively maintain the first node (q(n)) and the output end (g(n)) at low voltage level.. .
Shenzhen China Star Optoelectronics Technology Co., Ltd.



Semiconductor topics:
  • Semiconductor
  • Semiconductor Substrate
  • Semiconductor Device
  • Semiconductor Material
  • Electric Conversion
  • Conductive Layer
  • Molybdenum
  • Camera Module
  • Semiconductor Devices
  • Semiconductors
  • Integrated Circuit
  • Surfactant
  • Photoelectric Conversion
  • Electronic Device
  • Transparent Conductive Oxide


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