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Semiconductor Substrate patents

      

This page is updated frequently with new Semiconductor Substrate-related patent applications.




 Semiconductor device and  manufacturing semiconductor device patent thumbnailSemiconductor device and manufacturing semiconductor device
A semiconductor device includes a plurality of semiconductor switching elements disposed on a single semiconductor substrate comprising a semiconductor having a bandgap that is wider than that of silicon; and a plurality of electrode pads that are disposed in a predetermined planar layout on a front surface of the semiconductor substrate, the plurality of electrode pads each being electrically connected to the plurality of semiconductor switching elements. A plurality of terminal pins to externally carry out voltage of the electrode pads is bonded through a plated film to all of the plurality of electrode pads by solder..
Fuji Electric Co., Ltd.


 Semiconductor memory device patent thumbnailSemiconductor memory device
A semiconductor memory device includes a selection transistor on a semiconductor substrate, a lower contact plug connected to a drain region of the selection transistor, and a magnetic tunnel junction pattern on the lower contact plug, the magnetic tunnel junction pattern including a bottom electrode in contact with the lower contact plug, the bottom electrode being an amorphous tantalum nitride layer, a top electrode on the bottom electrode, first and second magnetic layers between the top and bottom electrodes, and a tunnel barrier layer between the first and second magnetic layers.. .

 Semiconductor device patent thumbnailSemiconductor device
A planar mosfet is provided on the upper surface of the n−-type semiconductor substrate in a mesa portion between the trenches. A p+-type emitter layer is provided between the trench and the planar mosfet in the mesa portion.
Mitsubishi Electric Corporation


 Semiconductor device patent thumbnailSemiconductor device
To provide a semiconductor device in which an edge termination structure can be made smaller easily. A semiconductor device is provided, the semiconductor device including an active region and an edge termination structure formed on a front surface side of a semiconductor substrate, wherein an edge termination structure has a guard ring provided surrounding an active region on a front surface side of a semiconductor substrate, a first field plate provided on a front surface side of a guard ring, an electrode unit provided on a front surface side of a first field plate, a second field plate provided between a first field plate and a electrode unit, and a conductive connecting unit which mutually electrically connects a first field plate, an electrode unit, a second field plate, and a guard ring..
Fuji Electric Co., Ltd.


 Vertical tunneling field-effect transistor cell and fabricating the same patent thumbnailVertical tunneling field-effect transistor cell and fabricating the same
A method for forming a tunneling field-effect transistor (tfet) is disclosed. The method includes etching a semiconductor substrate to form a semiconductor protrusion that protrudes out from a top surface of the semiconductor substrate, forming a drain region in lower portion of the semiconductor protrusion, and patterning a gate stack layer to form a gate stack.
Taiwan Semiconductor Manufacturing Co., Ltd.


 Method for fabricating finfet isolation structure patent thumbnailMethod for fabricating finfet isolation structure
A method for forming a semiconductor device. In this method, a semiconductor fin is formed on a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


 Semiconductor device and  manufacturing the same patent thumbnailSemiconductor device and manufacturing the same
A method of manufacturing a semiconductor device that includes a junction field effect transistor, the junction field effect transistor including a semiconductor substrate of a first conductivity type, an epitaxial layer of the first conductivity type formed on the semiconductor substrate, a source region of the first conductivity type formed on a surface of the epitaxial layer, a channel region of the first conductivity type formed in a lower layer of the source region, a pair of trenches formed in the epitaxial layer so as to sandwich the source region therebetween, and a pair of gate regions of a second conductivity type, opposite to the first conductivity type, formed below a bottom of the pair of trenches.. .
Renesas Electronics Corporation


 Reduction of defect induced leakage in iii-v semiconductor devices patent thumbnailReduction of defect induced leakage in iii-v semiconductor devices
A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 10 cm−2. An n-type layer is formed on or in the p-doped layer.
International Business Machines Corporation


 Semiconductor device and  manufacturing semiconductor device patent thumbnailSemiconductor device and manufacturing semiconductor device
A semiconductor device includes a wide-bandgap semiconductor substrate of a first conductivity type, a wide-bandgap semiconductor deposition layer of the first conductivity type, semiconductor regions of a second conductivity type, a wide-bandgap semiconductor layer of the second conductivity type, first regions of the first conductivity type, and second regions of the first conductivity type. The width w of a plating film formed on a source electrode of the semiconductor device is greater than or equal to 10 μm.
Fuji Electric Co., Ltd.


 Semiconductor integrated circuit device capable of reducing a leakage current patent thumbnailSemiconductor integrated circuit device capable of reducing a leakage current
A semiconductor integrated circuit device may include a semiconductor substrate, a source pattern, a drain pattern, a nano wire pattern and a gate. The source pattern may be formed on an upper surface of the semiconductor substrate.
Sk Hynix Inc.


Magnetoresistive sensor module and manufacturing the same

In the method of manufacturing a magnetoresistive sensor module, at first a composite arrangement out of a semiconductor substrate and a metal-insulator arrangement is provided, wherein a semiconductor circuit arrangement is integrated adjacent to a main surface of the semiconductor substrate into the same, wherein the metal-insulator arrangement is arranged on the main surface of the semiconductor substrate and comprises a structured metal sheet and insulation material at least partially surrounding the structured metal sheet, wherein the structured metal sheet is electrically connected to the semiconductor circuit arrangement. Then, a magnetoresistive sensor structure is applied onto a surface of the insulation material of the composite arrangement, and finally an electrical connection between the magnetoresistive sensor structure and the structured metal sheet is established, so that the magnetoresistive sensor structure is connected to the integrated circuit arrangement..
Infineon Technologies Ag

Phase detection autofocus techniques

The present disclosure relates to an image sensor having autofocus function and associated methods. In some embodiments, the integrated circuit has a photodiode array with a plurality of photodiodes disposed within a semiconductor substrate and a composite grid overlying the photodiode array and having a first plurality of openings and a second plurality of openings extending vertically through the composite grid.
Taiwan Semiconductor Manufacturing Co., Ltd.

Solid-state imaging apparatus, manufacturing method therefor, and electronic apparatus

A charge accumulation section that is formed on a first semiconductor substrate and accumulates photoelectrically converted charges, a charge-retaining section that is formed on a second semiconductor substrate and retains charges accumulated in the charge accumulation section, and a transfer transistor that is formed on the first semiconductor substrate and the second semiconductor substrate and transfers charges accumulated in the charge accumulation section to the charge-retaining section are provided. A bonding interface between the first semiconductor substrate and the second semiconductor substrate is formed in a channel of the transfer transistor..

Semiconductor device

A plurality of pixel regions are aligned in a matrix in a semiconductor substrate, and each of the plurality of pixel regions includes an active region, two photoelectric conversion elements, two floating capacitance regions, and a first transistor. Each of the plurality of pixel regions includes two transfer transistors each having each of the two photoelectric conversion elements and each of the two floating capacitance regions.
Renesas Electronics Corporation

Semiconductor device and forming the same

A semiconductor device includes a semiconductor substrate, a radiation-sensing region, at least one isolation structure, and a doped passivation layer. The radiation-sensing region is present in the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor structure and manufacturing method thereof

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, a non-volatile memory cell, and a gate stack.
United Microelectronics Corp.

Semiconductor structure and forming the same

A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor apparatus

A semiconductor apparatus includes a semiconductor substrate, a semiconductor element, an edge termination region that surrounds the semiconductor element, a protective diode that has a first terminal and a second terminal, where the first terminal is positioned within the edge termination region and the second terminal is positioned outside the edge termination region, and a diffusion layer that has a floating potential, where the diffusion layer is provided in a gap portion between a region of the edge termination region that is aligned with the protective diode and the protective diode.. .
Fuji Electric Co., Ltd.

Semiconductor device

A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion..
Renesas Electronics Corporation

Semiconductor device with an anti-pad peeling structure and associated method

A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a through substrate via (tsv); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the tsv when being seen from a top-down perspective..
Taiwan Semiconductor Manufacturing Company Ltd.

Compound semiconductor substrate

A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an fwhm of an x-ray diffraction peak of the buffer layer obtained by an x-ray diffraction rocking curve measurement is 800 arcsec or less.. .
Coorstek Kk

Method of forming deep trench and deep trench isolation structure

A method of forming a deep trench in a semiconductor substrate includes: forming a first mask pattern over the semiconductor substrate, in which the first mask pattern has a first opening exposing a portion of the semiconductor substrate; forming a second mask pattern over the first mask pattern, in which the second mask pattern has a second opening substantially aligned with the first opening to expose the portion of the semiconductor substrate, and the second opening has a width greater than a width of the first opening to further expose a portion of the first mask pattern; and removing the portion of the semiconductor substrate, the portion of first mask pattern and another portion of the semiconductor substrate beneath the portion of the first mask pattern to form the deep trench.. .
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor package assembly with through silicon via interconnect

The invention provides a semiconductor package assembly with a tsv interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of tsv interconnects and a second array of tsv interconnects formed through the semiconductor substrate, wherein the first array and second array of tsv interconnects are separated by an interval region.
Mediatek Inc.

Trench mosfet with self-aligned body contact with spacer

Trench mosfet with self-aligned body contact with spacer. In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor substrate, and at least two gate trenches formed in the semiconductor substrate.
Vishay-siliconix

Layout compound semiconductor integrated circuits

A layout method for compound semiconductor integrated circuits, comprising following steps of: forming a first metal layer within a first circuit layout area which intersects with a second circuit layout area at an intersection area on a compound semiconductor substrate; defining an adjacent crossover area including said intersection area and a peripheral adjacent area thereof; a first dielectric area located within said adjacent crossover area and intersected with at least part of said intersection area; forming a first dielectric block within said first dielectric area or forming said first dielectric block within said first dielectric area and a second dielectric block outside said first dielectric area, the thickness of said second dielectric block is no greater than and the thickness of at least part of said second dielectric block is smaller than the thickness of said first dielectric block; forming a second metal layer within said second circuit layout area.. .
Win Semiconductors Corp.

Semiconductor package structure and manufacturing the same structure

A semiconductor package structure includes a first semiconductor substrate, a second semiconductor substrate, a semiconductor die electrically connected to the first semiconductor substrate, an interconnection element and an encapsulant. The first semiconductor substrate includes a first top pad, and the second semiconductor substrate includes a second bottom pad.
Advanced Semiconductor Engineering, Inc.

External gettering

Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed.
Micron Technology, Inc.

Complementary metal-oxide-semiconductor field-effect transistor and method thereof

This invention application provides a complementary metal-oxide-semiconductor field-effect transistor and method thereof. The transistor comprises a semiconductor substrate, a n-type field-effect transistor positioned in the semiconductor substrate, and a p-type field-effect transistor positioned in the semiconductor substrate and spaced apart the n-type field-effect transistor.
Zing Semiconductor Corporation

Dielectric with air gaps for use in semiconductor devices

Aspects of the invention are directed to a method for forming a semiconductor device. A dielectric layer is formed on a semiconductor substrate.
International Business Machines Corporation

Methods for forming semiconductor devices

A method for forming a semiconductor device includes etching, in a masked etching process, through a layer stack located on a surface of a semiconductor substrate to expose the semiconductor substrate at unmasked regions of the layer stack. The method further includes etching, in a selective etching process, at least a first layer of the layer stack located adjacently to the semiconductor substrate.
Infineon Technologies Austria Ag

Local semiconductor wafer thinning

A local thinning process is employed on the backside of a semiconductor substrate such as a wafer in order to improve the thermal performance of the electronic device built on or in the front side of the wafer.. .
Vishay General Semiconductor Llc

Semiconductor forming a semiconductor device

A method for forming a semiconductor device includes implanting doping ions into a semiconductor substrate. A deviation between a main direction of a doping ion beam implanting the doping ions and a main crystal direction of the semiconductor substrate is less than ±0.5° during the implanting of the doping ions into the semiconductor substrate.
Infineon Technologies Ag

Apparatus of processing semiconductor substrate

An apparatus of processing a semiconductor substrate include a chuck, a holder, a liquid supplying system and a positive pressure unit. The chuck has a principal surface and at least a hole formed thereon.
Taiwan Semiconductor Manufacturing Co., Ltd.

Test line patterns in split-gate flash technology

The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed.
Taiwan Semiconductor Manufacturing Co., Ltd.

Test line letter for embedded non-volatile memory technology

The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, the substrate has a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method for fabricating semiconductor memory device having integrated dosram and nosram

A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared.
United Microelectronics Corp.

Mechanical quantity measuring device and sensor unit

A mechanical quantity measuring device includes: a sensor chip having a strain detector formed on a surface of a semiconductor substrate and a plurality of electrodes connected to the strain detector; a stem having ascot that protrudes from an adjacent peripheral portion and has an upper surface that is attached to a lower surface of the sensor chip by a bonding material formed from a metallic material or a glass material; a lead-out wiring part including a plurality of wires that are electrically connected to the plurality of electrodes; and a fixing part for fixing the stem, wherein: the stem and the fixing part are integrally molded or fixed through metallic bonding or mechanical bonding.. .
Hitachi Automotive Systems, Ltd.

Integrated bound-mode spectral/angular sensors

A 2-d sensor array includes a semiconductor substrate and a plurality of pixels disposed on the semiconductor substrate. Each pixel includes a coupling region and a junction region, and a slab waveguide structure disposed on the semiconductor substrate and extending from the coupling region to the region.
Stc.unm

Radio-frequency isolation using front side opening

A transistor device includes a transistor implemented over a semiconductor substrate, one or more dielectric layers formed over the transistor, and a handle wafer layer disposed on at least a portion of the one or more dielectric layers, the handle wafer layer including a topside trench defined at least in part by sidewall portions of the handle wafer layer.. .
Skyworks Solutions, Inc.

Semiconductor laser light source and fabrication method

A semiconductor laser light source includes a semiconductor substrate formed of a first conductivity type semiconductor material, a lower cladding layer formed of the first conductivity type semiconductor material on the semiconductor substrate, a waveguide layer on the lower cladding layer, and an upper cladding layer formed of a second conductivity type semiconductor material on the waveguide layer. The waveguide layer includes a core area and rib areas thinner than the core area on either side of the core area.
Fujitsu Limited

Solar cell module and manufacturing the same

A solar cell module is discussed. The solar cell module includes a plurality of solar cells each including a semiconductor substrate and a plurality of first electrodes and a plurality of second electrodes, which are formed on a back surface of the semiconductor substrate and are separated from each other, the plurality of solar cells disposed in a first direction; a plurality of first conductive lines connected to the plurality of first electrodes included in a first solar cell of the plurality of solar cells, and the plurality of first conductive lines extended in the first direction; a plurality of second conductive lines connected to the plurality of second electrodes included in a second solar cell of the plurality of solar cells which is adjacent to the first solar cell, and the plurality of second conductive lines extended in the first direction..
Lg Electronics Inc.

Back-contact solar cell and manufacturing the same

A method for manufacturing a back-contact solar cell, comprising the steps of: (i) preparing a semiconductor substrate comprising an n-layer and a p-layer at the back side of the semiconductor substrate; (ii) applying a conductive paste on both the n-layer and the p-layer, wherein the conductive paste comprises a silver (ag) powder, a palladium (pd) powder, an additional metal powder selected from the group consisting of molybdenum (mo), boron (b) and a mixture thereof, a glass frit, and an organic medium; and (iii) firing the applied conductive paste.. .
E I Du Pont De Nemours And Company

Solar cell module

A solar cell module includes a plurality of solar cells each including a semiconductor substrate and first electrodes and second electrodes extended on a back surface of the semiconductor substrate, first conductive lines connected to the first electrodes at crossings between the first electrodes and the first conductive lines through first conductive adhesive layers, second conductive lines connected to the second electrodes at crossings between the second electrodes and the second conductive lines through the first conductive adhesive layers, and an intercell connector extended between a first solar cell and a second solar cell that are adjacent to each other. The first conductive lines connected to the first solar cell and the second conductive lines connected to the second solar cell are commonly connected to the intercell connector..
Lg Electronics Inc.

Semiconductor device including dual-layer source/drain region

A semiconductor device includes a semiconductor substrate having a channel region interposed between a first active region and a second active region, and a gate structure formed on the channel region. A first dual-layer source/drain region is on the first active region and a second dual-layer source/drain region is on the second active region.
International Business Machines Corporation

Semiconductor device

A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.. .
Fujitsu Limited

Semiconductor device comprising a field electrode

A semiconductor device is manufactured by forming a gate electrode adjacent to a body region in a semiconductor substrate, forming a field plate trench in a main surface of the substrate, the field plate trench having an extension length in a first direction parallel to the main surface, and forming a field electrode and a field dielectric layer in the field plate trench so that the field electrode is insulated from an adjacent drift zone by the field dielectric layer. The extension length of the field plate trench in the first direction is less than double an extension length of the field electrode in a second direction that is perpendicular to the first direction and is parallel to the main surface.
Infineon Technologies Austria Ag

Semiconductor device and fabricating the same

A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface.
United Microelectronics Corp.

Semiconductor device including dual-layer source/drain region

A semiconductor device includes a semiconductor substrate having a channel region interposed between a first active region and a second active region, and a gate structure formed on the channel region. A first dual-layer source/drain region is on the first active region and a second dual-layer source/drain region is on the second active region.
International Business Machines Corporation

Image sensors using different photoconversion region isolation structures for different types of pixel regions

An image sensor includes a semiconductor substrate, a first pair of photoelectric conversion regions in a first pixel region of the substrate and a first isolation structure between the photoelectric conversion regions of the first pair of photoelectric conversion regions. The sensor further includes a second pair of photoelectric conversion regions in a second pixel region of the substrate adjacent the first pixel region and a second isolation structure between the photoelectric conversion regions of the second pair of photoelectric conversion regions and having different optical properties than the first isolation structure.
Samsung Electronics Co., Ltd.

Co-fabricated bulk devices and semiconductor-on-insulator devices

Bulk semiconductor devices are co-fabricated on a bulk semiconductor substrate with soi devices. The soi initially covers the entire substrate and is then removed from the bulk device region.
Globalfoundries Inc.

Semiconductor memory device

A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.. .
Kabushiki Kaisha Toshiba



Semiconductor Substrate topics:
  • Semiconductor Substrate
  • Semiconductor
  • Semiconductor Device
  • Gallium Nitride
  • Memory Cell
  • Phase Change Memory
  • Phase Change Material
  • Memory Device
  • Semiconductor Memory
  • Integrated Circuit
  • Transistors
  • Field Effect Transistor
  • Planarization
  • Conductive Layer
  • Semiconductor Devices


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    This listing is a sample listing of patent applications related to Semiconductor Substrate for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Semiconductor Substrate with additional patents listed. Browse our RSS directory or Search for other possible listings.


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