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Semiconductor Substrate patents



      

This page is updated frequently with new Semiconductor Substrate-related patent applications.




Date/App# patent app List of recent Semiconductor Substrate-related patents
06/16/16
20160172512 
 Laminated backplane for solar cells patent thumbnailLaminated backplane for solar cells
A back contact solar cell structure having a light receiving frontside and a metallized backside of on-cell patterned base and emitter metallization electrically connected to base and emitter regions on a back contact solar cell semiconductor substrate. A backplane laminate layer made of resin and fibers and having a coefficient of thermal expansion relatively matched to the back contact solar cell semiconductor substrate is attached to the on-cell base and emitter metallization and to portions of the back contact solar cell semiconductor substrate not covered by the on-cell base and emitter metallization..
Solexel, Inc.


06/16/16
20160172509 
 Manufacturing  semiconductor device, and semiconductor device patent thumbnailManufacturing semiconductor device, and semiconductor device
To enhance the performance of a semiconductor device. In a method for manufacturing a semiconductor device, a metal film is formed over a semiconductor substrate having an insulating film formed on a surface thereof, and then the metal film is removed in a memory cell region, whereas, in a part of a peripheral circuit region, the metal film is left.
Renesas Electronics Corporation


06/16/16
20160172493 
 Integrated circuits with dual silicide contacts and methods for fabricating same patent thumbnailIntegrated circuits with dual silicide contacts and methods for fabricating same
Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures having source/drain regions in pfet areas and in nfet areas.
Globalfoundries, Inc.


06/16/16
20160172486 
 Semiconductor device patent thumbnailSemiconductor device
A semiconductor device includes a semiconductor substrate having a first conductivity type, an epitaxial layer having a second conductivity type, an isolation area in the epitaxial layer to define an active area of the semiconductor substrate, a body area having a first conductivity type and a drift area having a second conductivity type adjacent to each other in the epitaxial layer, a locos insulating layer in the drift area and surrounded by the drift area, a drain area adjacent to a side part of the locos insulating layer and surrounded by the drift area, a body contact area and a source area in the body area and surrounded by the body area, and a gate area overlapping the drift area and a part of the locos insulating layer from a direction of the body area.. .
Samsung Electronics Co., Ltd.


06/16/16
20160172485 
 Semiconductor device patent thumbnailSemiconductor device
A semiconductor device includes a semiconductor substrate and a semiconductor element arranged on a predetermined surface side of the semiconductor substrate. The semiconductor element includes: a first region portion at which a first conductivity type semiconductor region is arranged on the surface side of the semiconductor substrate; a second region portion at a position separated from the first region portion; and a gate electrode arranged between the first region portion and the second region portion through an insulating film.
Denso Corporation


06/16/16
20160172482 
 Integrating enhancement mode depleted accumulation/inversion channel devices with mosfets patent thumbnailIntegrating enhancement mode depleted accumulation/inversion channel devices with mosfets
A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are formed into the epitaxial region, each between two adjacent gate trenches.
Alpha And Omega Semiconductor Incorporated


06/16/16
20160172468 
 Method of forming a silicon-carbide device with a shielded gate patent thumbnailMethod of forming a silicon-carbide device with a shielded gate
A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed.
Infineon Technologies Ag


06/16/16
20160172467 
 Replacement metal gate including dielectric gate material patent thumbnailReplacement metal gate including dielectric gate material
A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin.
Globalfoundries Inc.


06/16/16
20160172466 
 Method to reduce etch variation using ion implantation patent thumbnailMethod to reduce etch variation using ion implantation
The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


06/16/16
20160172465 
 Planar iii-v field effect transistor (fet) on dielectric layer patent thumbnailPlanar iii-v field effect transistor (fet) on dielectric layer
A method of forming a semiconductor substrate including a type iii-v semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A iii-v semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench..
International Business Machines Corporation


06/16/16
20160172464 

Electronic device having an electronic component and a process of forming the same


In an embodiment, a process of forming an electronic device can include providing a semiconductor substrate having a first major side and an electronic component at least partly within the semiconductor substrate along the first major side; the process can further include thinning the semiconductor substrate to define a second major surface along a second major side opposite the first major side; and selectively removing a portion of the semiconductor substrate along the second major side to define a trench having a distal surface. The process can further include forming a feature adjacent to or within the trench.
Semiconductor Components Industries, Llc


06/16/16
20160172462 

Fin replacement in a field-effect transistor


In a method for fabricating a field-effect transistor (fet) structure, forming a fin on a semiconductor substrate. The method further includes forming a gate on a portion of the fin and the semiconductor substrate.
International Business Machines Corporation


06/16/16
20160172445 

Finfet transistor


A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric.
Sang U. Kim


06/16/16
20160172443 

Method and apparatus to tune threshold voltage of device with high angle source/drain implants


A method for tuning a threshold voltage of a semiconductor device includes implanting at least one dopant in a semiconductor substrate at an angle to form a source region and/or a drain region of a transistor. The angle is oblique to a surface of the substrate.
Texas Instruments Incorporated


06/16/16
20160172440 

Semiconductor device including sti structure


Semiconductor devices including sti structures and their fabrication methods are provided. A mask layer is provided on a semiconductor substrate and patterned to form an opening in the mask layer to expose a surface portion of the semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


06/16/16
20160172438 

Method of manufacturing semiconductor devices using light ion implantation and semiconductor device


A first doped region is formed in a single crystalline semiconductor substrate. Light ions are implanted through a process surface into the semiconductor substrate to generate crystal lattice vacancies between the first doped region and the process surface, wherein a main beam axis of an implant beam used for implanting the light ions deviates by at most 1.5 degree from a main crystal direction along which channeling of the light ions occurs.
Infineon Technologies Ag


06/16/16
20160172437 

Wide band gap semiconductor device


A semiconductor substrate (epitaxial substrate) having a main surface (upper surface) and made of a wide band gap semiconductor is provided, the semiconductor substrate including a device region formed in the semiconductor substrate, and a peripheral region formed to surround the device region. In the peripheral region, the semiconductor substrate includes a first semiconductor region (drift layer) having a first conductivity type, and a second semiconductor region (electric field relaxing region) formed on the first semiconductor region (drift layer) and having the main surface, the second semiconductor region having a second conductivity type different from the first conductivity type, and a plurality of trenches annularly surrounding the device region are formed in the main surface of the second semiconductor region (electric field relaxing region).
Sumitomo Electric Industries, Ltd.


06/16/16
20160172418 

Method of manufacturing cmos image sensor


Methods of manufacturing a complementary metal oxide semiconductor (cmos) image sensor, include forming, in a semiconductor substrate, at least one device isolation layer defining an active area; forming at least one gate dielectric layer on the active area; forming at least one gate on the active area and the at least one device isolation layer, wherein first conductive-type impurity ions are injected into the at least one gate; and injecting second conductive-type impurity ions into portions of the at least one gate arranged on the at least one device isolation layer and edges of the active area adjacent to the at least one device isolation layer.. .
Samsung Electronics Co., Ltd.


06/16/16
20160172407 

Solid-state imaging device, imaging apparatus, and driving the solid-state imaging device


A solid-state imaging device including a semiconductor substrate; plural photoelectric conversion units formed side by side on the semiconductor substrate to form a light receiving unit; a peripheral circuit formed in a portion on an outside of the light receiving unit on the semiconductor substrate; a wiring section formed on the light receiving unit and formed for connecting the plural photoelectric conversion units and the peripheral circuit; and a dummy wiring section formed on an opposite side of the wiring section for at least one photoelectric conversion unit among the plural photoelectric conversion units on the light receiving unit and formed for functioning as a non-connected wiring section not connected to the photoelectric conversion units and the peripheral circuit, wherein the dummy wiring section has a predetermined potential.. .
Sony Corporation


06/16/16
20160172406 

Semiconductor device and solid-state imaging device


Certain embodiments provide a semiconductor device including a semiconductor substrate having an element portion, an insulating film provided on a main surface of the semiconductor substrate, at least one wire provided on the insulating film and electrically connected to the element portion, an uneven portion provided on the main surface side of the semiconductor substrate, and a protection film provided in contact with the wire and the uneven portion, and also in contact with the insulating film.. .
Kabushiki Kaisha Toshiba


06/16/16
20160172364 

Semiconductor device and forming the same


A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film, a bit line contact plug that is coupled to the active region and that includes a first ion implantation region buried in a first inner void, and a storage node contact plug that is coupled to the active region and includes a second ion implantation region buried in a second inner void.
Sk Hynix Inc.


06/16/16
20160172354 

Semiconductor device with electro-static discharge protection device above semiconductor device area


A semiconductor device includes a semiconductor substrate on which a semiconductor device is formed; first and second pads; a first insulating film which is formed above the semiconductor substrate; a plurality of wiring lines which are embedded in ditches provided in the first insulating film; a second insulating film provided to cover the first insulating film and the plurality of wiring lines; a semiconductor layer formed on the second insulating film; a source electrode connected with the semiconductor layer; and a drain electrode connected with the semiconductor layer. The plurality of wiring lines includes a gate electrode provided in a position which is opposite to the semiconductor layer.
Renesas Electronics Corporation


06/16/16
20160172311 

Ic with insulating trench and related methods


An ic may include a semiconductor substrate having circuitry formed in the substrate, an interconnect layer above the semiconductor substrate and having an antenna coupled to the circuitry, and a seal ring around a periphery of the interconnect layer. The ic may include an electrically insulating trench extending vertically into the semiconductor substrate and extending laterally across the semiconductor substrate from adjacent one side to adjacent another side..
Stmicroelectronics S.r.l.


06/16/16
20160172301 

Semiconductor device and manufacturing method therefor


A semiconductor device includes a first insulating film located on the semiconductor substrate and including a first contact hole; a contact plug located in the first contact hole; a first surface electrode extending on the first insulating film and the contact plug; a conductive layer; a second insulating film located on the conductive layer and including a second contact hole wider than the first contact hole; a side metal layer covering a corner portion in the second contact hole and configured of a same kind of metal as the contact plug; and a second surface electrode extending on the second insulating film and in the second contact hole, covering the side metal layer, and configured of a different kind of metal from the contact plug. A bonding pad is located in a part of the second surface electrode on the bottom surface of the second contact hole..
Toyota Jidosha Kabushiki Kaisha


06/16/16
20160172251 

Integrated circuits and methods of forming the same with effective dummy gate cap removal


Integrated circuits and methods of forming the same are provided. An exemplary method of forming an integrated circuit includes forming a dummy gate structure overlying a semiconductor substrate.
Globalfoundries, Inc.


06/16/16
20160172250 

Semiconductor isolation structure with air gaps in deep trenches


A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an inter-layer dielectric (ild) layer over the semiconductor substrate, with the contact plug being disposed in the ild. An air gap is sealed by a portion of the ild and the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/16/16
20160172241 

Electroless metal through silicon via


A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions.
Silex Microsystems Ab


06/16/16
20160172236 

Device substrates, integrated circuits and methods for fabricating device substrates and integrated circuits


Integrated circuits and methods for fabricating device substrates and integrated circuits are provided. Integrated circuits in accordance with those described herein include a semiconductor substrate with a substrate surface and having a low voltage (lv) region and a second voltage region that is either a medium voltage (mv) region or a high voltage (hv) region.
Globalfoundries Singapore Pte. Ltd.


06/16/16
20160172235 

In-situ doped polysilicon filler for trenches


A method of fabricating an integrated circuit (ic) includes etching a trench in a semiconductor substrate having an aspect ratio (ar) ≧5 and a trench depth ≧10 μm. A dielectric liner is formed along the walls of the trench to form a dielectric lined trench.
Texas Instruments Incorporated


06/16/16
20160172228 

Method of laser separation of the epitaxial film or the epitaxial film layer from the growth substrate of the epitaxial semiconductor structure (variations)


The present invention proposes variations of the laser separation method allowing separating homoepitaxial films from the substrates made from the same crystalline material as the epitaxial film. This new method of laser separation is based on using the selective doping of the substrate and epitaxial film with fine donor and acceptor impurities.

06/16/16
20160172027 

Polymer memory


A integrated circuit device with a polymer memory array includes active circuits formed in lower layers of a multi-level interconnect structure and a semiconductor substrate and also includes an array of polymer memory cells formed in an upper interconnect level having a plurality of cell node electrodes and source line electrodes for the polymer memory array, each polymer memory cell including a passive layer having at least one conductivity-facilitating compound that is formed on top and sidewall surfaces of a source line electrode, and an active layer having an impedance state that can change that is formed on top and sidewall surfaces of an adjacent cell node electrode with sufficient thickness to make direct physical contact with the passive layer.. .
Conversant Intellectual Property Management Inc.


06/16/16
20160169819 

Semiconductor inspection apparatus, semiconductor inspection method, and recording medium


A semiconductor inspection apparatus according to an embodiment includes a calculator and an output unit. While a contour of an inspection object pattern on a semiconductor substrate and a closed curve obtained by approximation of the contour are superimposed on each other, the calculator acquires the total area of the area of the first region inside the contour and outside the closed curve and the area of the second region outside the contour and inside the closed curve.
Kabushiki Kaisha Toshiba


06/16/16
20160169734 

Photodetector and electronic apparatus


A photodetector includes a semiconductor substrate; a light receiving part for signal detection and an infrared light receiving part which are formed in the semiconductor substrate and are covered at least by first color filters having a common color; and second color filters which overlap with the first color filters on the infrared light receiving part and are configured to block light in a wavelength range transmitting through the first color filters.. .
Rohm Co., Ltd.


06/16/16
20160167957 

Method of manufacturing an integrated circuit comprising a pressure sensor


Disclosed is an integrated circuit, comprising a semiconductor substrate carrying a plurality of circuit elements; and a pressure sensor including a cavity on said semiconductor substrate, said cavity comprising a pair of electrodes laterally separated from each other; and a flexible membrane over and spatially separated from said electrodes such that said membrane interferes with a fringe field between said electrodes, said membrane comprising at least one aperture. A method of manufacturing such an ic is also disclosed..
Ams International Ag


06/16/16
20160167954 

Monolithically integrated multi-sensor device on a semiconductor substrate and method therefor


A monolithically integrated multi-sensor (mims) is disclosed. A mims integrated circuit comprises a plurality of sensors.
Versana Micro Inc.


06/16/16
20160167953 

Monolithically integrated multi-sensor device on a semiconductor substrate and method therefor


A monolithically integrated multi-sensor (mims) is disclosed. A mims integrated circuit comprises a plurality of sensors.
Versana Micro Inc.


06/16/16
20160167369 

Liquid discharging apparatus, head unit, capacitive load driving circuit, and integrated circuit device for capacitive load driving


There is provided a liquid discharging apparatus including: a modulation portion which generates a modulation signal pulse-modulated from a source signal; a ground terminal which electrically connects the modulation portion to a ground potential; a transistor which generates an amplification modulation signal amplified from the modulation signal; a low pass filter which demodulates the amplification modulation signal and generates a driving signal; a feedback circuit which generates a feedback signal based on the driving signal, and sends back the feedback signal to the modulation portion via a feedback terminal; and a piezoelectric element which is displaced as the driving signal is applied, in which the modulation portion, the ground terminal, and the feedback terminal are formed on the same semiconductor substrate, and in which, in a plan view, the ground terminal and the feedback terminal are disposed being adjacent to each other.. .
Seiko Epson Corporation


06/16/16
20160167366 

Liquid discharging apparatus, head unit, capacitive load driving circuit, and integrated circuit device for capacitive load driving


There is provided a liquid discharging apparatus including: a low voltage system circuit block including a modulation portion which generates a modulation signal pulse-modulated from a source signal; a high voltage system circuit block including a gate driver which generates an amplification control signal based on the modulation signal; a transistor which generates an amplification modulation signal amplified from the modulation signal based on the amplification control signal; a low pass filter which demodulates the amplification modulation signal and generates a driving signal; and a piezoelectric element which is displaced as the driving signal is applied, in which the low voltage system circuit block and the high voltage system circuit block are formed on the same semiconductor substrate, in which the semiconductor substrate has one substrate potential supply terminal to which a substrate potential of the semiconductor substrate is supplied.. .
Seiko Epson Corporation


06/09/16
20160164478 

Semiconductor device, manufacturing the same, and mobile phone


A technique capable of maintaining the filter characteristics of a transmitting filter and a receiving filter by reducing the influences of heat from the power amplifier given to the transmitting filter and the receiving filter as small as possible in the case where the transmitting filter and the receiving filter are formed on the same semiconductor substrate together with the power amplifier in a mobile communication equipment typified by a mobile phone is provided. A high heat conductivity film hcf is provided on a passivation film pas over the entire area of a semiconductor substrate 1s including an area ar1 on which an ldmosfet is formed and an area ar2 on which a thin-film piezoelectric bulk wave resonator baw is formed.
Renesas Electronics Corporation


06/09/16
20160164259 

Optical semiconductor device and manufacturing method thereof


A semiconductor laser in a ridge waveguide structure includes: a semiconductor substrate; a lower cladding layer which is formed on the semiconductor substrate; an active layer and a semiconductor layer which are in parallel on the lower cladding layer and are connected with each other; a first upper cladding layer locally aligned above the active layer; a second upper cladding layer locally aligned above the semiconductor layer; and a third upper cladding layer locally aligned above the active layer to confine light which is guided in the active layer, wherein the semiconductor layer has a band gap which is larger than that of the active layer. According to this constitution, an optical semiconductor device with high reliability in which the ridge waveguide structure whose manufacturing is relatively easy is applied, and current diffusion and electrical crosstalk between lasers in the ridge waveguide structure are suppressed is enabled..
Fujitsu Limited


06/09/16
20160164257 

Semiconductor integrated optical device, manufacturing method thereof and optical module


Provided is a butt-jointed (bj) semiconductor integrated optical device having a high manufacturing yield. A semiconductor integrated optical device, which is configured such that, on a semiconductor substrate, a first semiconductor optical element including an active layer and a second semiconductor optical element including a waveguide layer are butt-jointed to each other with their optical axes being aligned with each other, includes: a semiconductor regrowth layer including at least one of a diffraction grating layer or an etching stop layer, which is formed by one epitaxial growth across an entire surface above the active layer and the waveguide layer; and a cladding layer formed above the semiconductor regrowth layer..
Oclaro Japan, Inc.


06/09/16
20160163898 

Photovoltaic device


A photovoltaic device is provided that prevents a short circuit in an p-n junction even if the distance between the electrodes on the n-type semiconductor strips and the electrodes on the p-type semiconductor strips is reduced. A photovoltaic device includes n-type amorphous semiconductor strips 102 and p-type amorphous semiconductor strips 102p provided on the back face of a semiconductor substrate 101.
Sharp Kabushiki Kaisha


06/09/16
20160163883 

Bidirectional zener diode


A bidirectional zener diode of the present invention includes a semiconductor substrate of a first conductivity type, a first electrode and a second electrode which are defined on the semiconductor substrate, and a plurality of diffusion regions of a second conductivity type, which are defined at intervals from one another on a surface portion of the semiconductor substrate, to define p-n junctions with the semiconductor substrate, and the plurality of diffusion regions include diode regions which are electrically connected to the first electrode and the second electrode, and pseudo-diode regions which are electrically isolated from the first electrode and the second electrode.. .
Rohm Co., Ltd.


06/09/16
20160163882 

Semiconductor device and manufacturing same


A memory cell has control and memory gate electrodes on a semiconductor substrate via an insulating film and another insulating film having first, second, and third films stacked one after another in order of mention, respectively. The memory and control gate electrodes are adjacent to each other via the stacked insulating film.

06/09/16
20160163876 

Semiconductor device structure and forming the same


A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


06/09/16
20160163875 

Silicide process using od spacers


A device includes a semiconductor substrate including an active region. The active region includes a first sidewall.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/09/16
20160163861 

Semiconductor devices and methods for manufacturing the same


Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode..

06/09/16
20160163838 

Method of fabricating thin-film semiconductor substrate


A method of fabricating a thin-film transistor substrate including a thin-film semiconductor includes: forming a metal film mainly comprising cu above a substrate; forming a source electrode and a drain electrode by processing the metal film in a predetermined shape; irradiating the source electrode and the drain electrode with nitrogen plasma; exposing surfaces of a top and an end portion of the source electrode and the drain electrode with silane (sih4) gas; and forming an insulating layer comprising an oxide on the source electrode and the drain electrode.. .
Joled Inc.


06/09/16
20160163831 

Finfet device including a dielectrically isolated silicon alloy fin


A method includes forming a fin on a semiconductor substrate. An isolation structure is formed adjacent the fin.
Globalfoundries Inc.


06/09/16
20160163830 

Method for reducing gate height variation due to overlapping masks


A method includes forming at least one fin in a semiconductor substrate. A placeholder gate structure is formed above the fin.
Globalfoundries, Inc.


06/09/16
20160163827 

Selective etching in the formation of epitaxy regions in mos devices


A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. After the step of performing the selective epitaxial growth, a selective etch-back is performed to the epitaxy region.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/09/16
20160163826 

Finfet with wide unmerged source drain epi


A method including forming fin spacers on opposite sidewalls of a semiconductor fin made from a semiconductor substrate, forming a dielectric layer in direct contact with the fin spacers such that a top surface of the fin and a top surface of the fin spacers remain exposed, recessing a portion of the fin between the fin spacers, removing the fin spacers to create an opening, and epitaxially growing an unmerged source drain region in the opening, where lateral growth of the unmerged source drain region is constrained on opposite sides by the dielectric layer.. .
Globalfoundries Inc.


06/09/16
20160163824 

Integrated circuits including replacement gate structures and methods for fabricating the same


Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming sidewall spacer structures laterally adjacent to a dummy gate structure that overlies a semiconductor substrate.
Globalfoundries, Inc.


06/09/16
20160163815 

Method of forming a semiconductor device structure and such a semiconductor device structure


The present disclosure provides in one aspect for a semiconductor device structure which may be formed by providing source/drain regions within a semiconductor substrate in alignment with a gate structure formed over the semiconductor substrate, wherein the gate structure has a gate electrode structure, a first sidewall spacer and a second sidewall spacer, the first sidewall spacer covering sidewall surfaces of the gate electrode structure and the sidewall spacer being formed on the first sidewall spacer. Furthermore, forming the semiconductor device structure may include removing the second sidewall spacer so as to expose the first sidewall spacer, forming a third sidewall spacer on a portion of the first sidewall spacer such that the first sidewall spacer is partially exposed, and forming silicide regions in alignment with the third sidewall spacer in the source/drain regions..
Globalfoundries Inc.


06/09/16
20160163812 

Semiconductor device


A semiconductor device including a semiconductor substrate and an electrode formed from an alloy containing aluminum, silicon and titanium. The silicon content in the electrode is from 0.5 to 1.0% by weight relative to the total weight of the electrode, the titanium content in the electrode is from 0.8 to 3.0% by weight relative to the total weight of the electrode, and the thickness of the electrode is at least 1 μm..
Toyota Jidosha Kabushiki Kaisha


06/09/16
20160163808 

Semiconductor device with low-k gate cap and self-aligned contact


A semiconductor device includes at least a gate formed upon a semiconductor substrate, a contact trench self aligned to the gate, and a multilayered gate caps comprising a first gate cap formed upon each gate and a low-k gate cap formed upon the first gate cap. The multilayered gate cap may electrically isolate the gate from a self aligned contact formed by filling the contact trench with electrically conductive material.
International Business Machines Corporation


06/09/16
20160163798 

Semiconductor devices and methods for manufacturing the same


Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode..

06/09/16
20160163786 

Semiconductor device and producing semiconductor device


Hydrogen atoms and crystal defects are introduced into an n− semiconductor substrate by proton implantation. The crystal defects are generated in the n− semiconductor substrate by electron beam irradiation before or after the proton implantation.
Fuji Electric Co., Ltd.


06/09/16
20160163784 

Coaxial carbon nanotube capacitor for edram


A deep trench (dt) opening is provided in a semiconductor substrate and then conducting carbon nanotubes are formed within the dt. Each conducting carbon nanotube is coated with a high k dielectric material and thereafter the remaining volume of the dt is filled with a conductive material..
International Business Machines Corporation


06/09/16
20160163783 

Semiconductor device and semiconductor memory devices having first, second, and third insulating layers


Disclosed herein is a device that includes: a semiconductor substrate; a first insulating layer over a surface of the semiconductor substrate; first and second contact plugs each including side and upper surfaces, the side surfaces of the first and second contact plugs being surrounded by the first insulating film, the upper surfaces of the first and second contact plugs being substantially on the same plane with an upper surface of the first insulating layer; a second insulating layer over the first insulating layer; a first conductive layer including a bottom portion on the first contact plug and a side portion surrounded by the second insulating layer; a third insulating layer over the first conductive layer; and a second conductive layer on the second contact plug, apart of a side surface of the second conductive layer being surrounded by both the second and third insulating layers.. .
Micron Technology, Inc.


06/09/16
20160163766 

Integrated circuit comprising a gas sensor


An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate having a major surface.
Ams International Ag


06/09/16
20160163764 

Method of manufacturing semiconductor device


An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, in an n-type semiconductor substrate, a p-type well as a p-type semiconductor region forming a part of a photodiode is formed and a gate electrode of a transfer transistor is formed.
Renesas Electronics Corporation


06/09/16
20160163749 

Deep trench spacing isolation for complementary metal-oxide-semiconductor (cmos) image sensors


An image sensor employing deep trench spacing isolation is provided. A plurality of pixel sensors is arranged over or within a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


06/09/16
20160163732 

Semiconductor devices


Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate.

06/09/16
20160163719 

Non-volatile semiconductor memory device


Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction. One stack structure has a plurality of semiconductor layers stacked between interlayer insulating layers.
Kabushiki Kaisha Toshiba


06/09/16
20160163717 

Embedded sram and methods of forming the same


A chip includes a semiconductor substrate, and a first n-type metal oxide semiconductor field effect transistor (nmosfet) at a surface of the semiconductor substrate. The first nmosfet includes a gate stack over the semiconductor substrate, a source/drain region adjacent to the gate stack, and a dislocation plane having a portion in the source/drain region.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/09/16
20160163709 

Semiconductor device


Disclosed herein is a method includes: forming first and second cavities, the first cavity having a first width, each of the second cavities having a second width narrower than the first width; forming a first conductive layer buried in the second cavities and formed on bottom and side surface of the semiconductor substrate defined by the first cavity so that a third cavity is defined by the first conductive layer formed on the bottom and side surface of the semiconductor substrate; subjecting an etch back process to the first conductive layer so that a first conductive portion is formed at a bottom corner of the first cavity, further a fourth cavity is formed on the semiconductor substrate uncovered with the first conductive portion in the first cavity; and forming a first insulating layer in the fourth cavity and in the second cavity.. .
Micron Technology, Inc.


06/09/16
20160163708 

Semiconductor device including transistors


A semiconductor device includes a semiconductor substrate having a first transistor region and a second transistor region, a first mosfet including a first gate insulating layer structure and a first gate electrode structure, and a second mosfet including a group iv compound semiconductor layer, a second gate insulating layer structure, and a second gate electrode structure. The first gate insulating layer structure and the first gate electrode structure are disposed on the first transistor region of the semiconductor substrate.
Samsung Electronics Co., Ltd.


06/09/16
20160163707 

Epitaxially grown silicon germanium channel finfet with silicon underlayer


Embodiments of the present invention provide a method for epitaxially growing a finfet. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region..
Globalfoundries Inc.


06/09/16
20160163703 

Semiconductor device


A semiconductor device includes a first mos transistor and a second mos transistor of a second conductivity type. The first mos transistor includes a first main electrode connected to a first potential and a second main electrode connected to a second potential.
Mitsubishi Electric Corporation


06/09/16
20160163700 

Fin deformation modulation


A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/09/16
20160163696 

Power semiconductor device


Switching loss is reduced. A first surface of a semiconductor substrate has a portion included in an igbt region and a portion included in a diode region.
Mitsubishi Electric Corporation


06/09/16
20160163666 

Semiconductor device and manufacturing the same


The semiconductor device includes a plurality of wiring layers formed on the semiconductor substrate, a pad electrode formed on an uppermost wiring layer among the plurality of wiring layers, a base insulating film having a pad opening above the pad electrode, and a rewiring electrically connected to the pad electrode and extending over the base insulating film. Further, the semiconductor device includes a protective film covering an upper surface of the rewiring and having an external pad opening exposing part of the upper surface of the rewiring, an external pad electrode electrically connected to the rewiring through the external pad opening and extending over the protective film, and a wire connected to the external pad electrode.

06/09/16
20160163664 

Semiconductor substrate and manufacturing method thereof


A method of manufacturing a semiconductor substrate includes a device-forming process of forming a plurality of device areas in a substrate section, a first wiring process of forming circuit wirings connected to the plurality of device areas, an electrode pad-forming process of forming a plurality of electrode pads, a second wiring process of forming a potential adjustment wiring electrically connecting at least a part of the electrode pads, an electrode-forming process of forming electrode bodies on the electrode pads by electroless plating after the second wiring process, and a potential adjustment-releasing process of releasing a connection by the potential adjustment wiring after the electrode-forming process.. .
Olympus Corporation


06/09/16
20160163660 

Semiconductor device having high frequency wiring and dummy metal layer at multilayer wiring structure


A semiconductor device includes a semiconductor substrate, a plurality of wiring layers provided on the semiconductor substrate, a high frequency wiring provided at a first layer in the plurality of wiring layers, and a plurality of dummy metals provided in a second layer provided between the semiconductor substrate and the first layer having the high frequency wiring. The plurality of wiring layers at a top view includes a high frequency wiring vicinity region and an external region surrounding the high frequency wiring vicinity region, the high frequency wiring vicinity region including a first region enclosed by an outer edge of the high frequency wiring and a second region surrounding the first region.
Renesas Electronics Corporation


06/09/16
20160163656 

Semiconductor device


A semiconductor device includes: a semiconductor substrate having an element; a front surface electrode connected to the element; a rear surface electrode connected to the element; a protective film disposed on the front surface of the semiconductor substrate in a separation region; and a temperature sensor disposed on a front surface side of the semiconductor substrate. The front surface electrode is divided into multiple pieces along at least two directions with the protective film.
Fuji Electric Co., Ltd.


06/09/16
20160163654 

Semiconductor device


In a back surface hole injection type diode, by more effectively securing the effect of hole injection from the back surface of a semiconductor substrate, the performance of a semiconductor device is improved. In the semiconductor device, in a diode formed of a p-n junction including an anode p-type layer formed in the main surface of a semiconductor substrate and a back surface n+-type layer formed in the back surface of the semiconductor substrate, a back surface p+-type layer is formed in the back surface, and a surface p+-type layer is formed in the main surface right above the back surface p+-type layer to thereby promote the effect of hole injection from the back surface..
Renesas Electronics Corporation


06/09/16
20160163653 

Semiconductor device


A semiconductor device and a method of making the same. The semiconductor device includes a semiconductor substrate mounted on a carrier.
Nxp B.v.


06/09/16
20160163649 

Semiconductor device and fabrication the same


The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer..
Pannova Semic, Llc


06/09/16
20160163637 

Semiconductor device and manufacturing the same


A semiconductor device includes a semiconductor substrate including active portions including first and second dopant regions, word lines on the substrate and extending in a first direction to intersect the active portions, first and second bit lines on the substrate and extending in a second direction to intersect the word lines, and contact structures in regions between the word lines and between the first and second bit lines when viewed from a plan view. The first and second bit lines are connected to the first dopant regions.

06/09/16
20160163635 

Semiconductor device


A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate.

06/09/16
20160163607 

Semiconductor device, semiconductor system and testing semiconductor device


A semiconductor device may include a semiconductor substrate doped with a first type impurity; a through electrode inserted in the semiconductor substrate; an active area formed in the semiconductor substrate to surround an upper portion of sidewalls of the through electrode, and doped with a second type impurity; an insulating layer formed between the semiconductor substrate and the through electrode, and between the active area and the through electrode; a drive circuit suitable for applying a first voltage to the through electrode in a test operation; and a test pad connected to the active area electrically in the test operation, to which a voltage is applied from outside.. .
Sk Hynix Inc.


06/09/16
20160163605 

Semiconductor structure and fabrication method thereof


A method for fabricating a semiconductor structure is provided. The method includes providing a semiconductor substrate; and forming a plurality of semiconductor devices on the semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


06/09/16
20160163594 

Method for forming void-free polysilicon and fabricating semiconductor device using the same


A method for fabricating a semiconductor device includes forming a buried gate electrode in a semiconductor substrate. An insulating layer is formed over the buried gate electrode and is etched to form a contact hole exposing the semiconductor substrate.
Sk Hynix Inc.


06/09/16
20160163561 

Technique to deposit sidewall passivation for high aspect ratio cylinder etch


Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner.
Lam Research Corporation


06/09/16
20160163558 

Technique to deposit metal-containing sidewall passivation for high aspect ratio cylinder etch


Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner.
Lam Research Corporation


06/09/16
20160163556 

Technique to deposit sidewall passivation for high aspect ratio cylinder etch


Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner.
Lam Research Corporation


06/09/16
20160163555 

Methods of forming features having differing pitch spacing and critical dimensions


Methods of forming features having differing pitch spacing and critical dimensions are disclosed herein. One method includes forming an underlying layer of material above a semiconductor substrate.
Globalfoundries Inc.


06/09/16
20160163550 

Gate electrodes with notches and methods for forming the same


A device includes a semiconductor substrate, and a device isolation (di) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the di region.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/09/16
20160163545 

Silicon carbide semiconductor substrate, manufacturing silicon carbide semiconductor substrate, and manufacturing silicon carbide semiconductor device


A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; an epitaxial layer formed on the main surface; and a deformation suppression layer formed on a backside surface of the base substrate opposite to the main surface. In this way, the deformation suppression layer suppresses the substrate from being deformed (for example, warped during high-temperature treatment).
Sumitomo Electric Industries, Ltd.


06/09/16
20160161529 

Current detection circuit and magnetic detection device provided with same


A current detection circuit includes a coil that is constituted by a metal wiring formed on a semiconductor substrate, a resistor that is provided in a position near the coil on the semiconductor substrate, constituted by a metal wiring formed on the semiconductor substrate, which is made of a metal material being same as that of the coil, and arranged so as to prevent any magnetic field from being generated due to a current flowing in the resistor, an output circuit that outputs currents in accordance with a resistance ratio between the coil and the resistor to the coil and the resistor correspondingly through a common terminal, and a detection circuit that detects the current flowing in the resistor to thereby detect the current flowing in the coil.. .
Yamaha Corporation


06/09/16
20160159638 

Microelectromechanical systems devices with improved reliability


An electronic device may include components that are formed using microelectromechanical systems (mems) technology. A mems device may include a mems structure bonded to a semiconductor substrate.
Apple Inc.


06/09/16
20160157791 

Imaging apparatus


A tomographic imaging system includes a source configured to irradiate an object; a first image sensor including a first semiconductor substrate having a first face upon which a monolithic first pixel array is located; and a gantry configured to hold the first image sensor and rotate the image sensor around the object about a first rotation axis, the first pixel array including a first plurality of pixels configured to receive light that travels through or from the object based on the irradiation, the first plurality of pixels of the first pixel array being arranged in one or more rows and a plurality of columns such that, a total number of the one or more rows is less than a total number of the plurality of columns, and the one or more rows extend in a first direction, the first image sensor being arranged such that an angle between the first direction and a second direction is greater than 45 degrees and equal to or less than 90 degrees, the second direction being a direction parallel to the rotation axis or a direction in which the object moves during analysis of the object by the imaging system.. .

06/02/16
20160157023 

Acoustic transducer


Provided is an acoustic transducer including: a semiconductor substrate; a vibrating membrane provided above the semiconductor substrate, including a vibrating electrode; and a fixed membrane provided above the semiconductor substrate, including a fixed electrode, the acoustic transducer detecting a sound wave according to changes in capacitances between the vibrating electrode and the fixed electrode, converting the sound wave into electrical signals, and outputting the electrical signals. At least one of the vibrating electrode and the fixed electrode is divided into a plurality of divided electrodes, and the plurality of divided electrodes outputting the electrical signals..
Stmicroelectronics S.r.l.


06/02/16
20160156154 

Semiconductor optical element and surface-emitting semiconductor optical element


A semiconductor optical element has a semiconductor substrate, a diffraction grating, a diffraction grating embedding layer, an active layer and a cladding layer. The diffraction grating includes a plurality of grating elements arranged on the semiconductor substrate along a direction (z direction) in which laser light is emitted.
Mitsubishi Electric Corporation


06/02/16
20160155939 

Memory device, semiconductor device, producing memory device, and producing semiconductor device


A method for producing a semiconductor device includes forming a fin-shaped semiconductor layer on a semiconductor substrate and a first pillar-shaped semiconductor layer, a second pillar-shaped semiconductor layer, and a contact line, the contact line extending in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends. A pillar-shaped phase-change layer and a lower electrode are formed overlying the first pillar-shaped semiconductor layer.
Unisantis Electronics Singapore Pte. Ltd.


06/02/16
20160155877 

Solar cell and manufacturing the same


A solar cell and a method for manufacturing the same are disclosed. The solar cell includes a semiconductor substrate containing impurities of a first conductive type, a front surface field region which is positioned at a front surface of the semiconductor substrate, contains impurities of the first conductive type at a higher concentration than the semiconductor substrate, and has a crystal structure or a crystallinity different from the semiconductor substrate, an emitter region which is positioned at a back surface of the semiconductor substrate and has a second conductive type opposite the first conductive type, a back surface field region which is positioned at the back surface of the semiconductor substrate and contains impurities of the first conductive type at a higher concentration than the semiconductor substrate, a first electrode connected to the emitter region, and a second electrode connected to the back surface field region..
Lg Electronics Inc.


06/02/16
20160155866 

Solar cell and manufacturing the same


Disclosed are a solar cell and a method for manufacturing the same. A solar cell includes a semiconductor substrate, a tunnel layer on the first surface of the semiconductor substrate, a first conductive type semiconductor region on the tunnel layer and includes impurities of a first conductive type, a second conductive type semiconductor region on a second surface and includes impurities of a second conductive type opposite the first conductive type, a first passivation film on the first conductive type semiconductor region, a first electrode formed on the first passivation film and connected to the first conductive type semiconductor region through an opening portion formed in the first passivation film, a second passivation film on the second conductive type semiconductor region, and a second electrode formed on the second passivation film and connected to the second conductive type semiconductor region through an opening portion formed in the second passivation film..
Lg Electronics Inc.


06/02/16
20160155845 

Asymmetric field effect transistor cap layer


A device includes a field effect transistor on an insulating film. A first fin extends vertically from a top side of a horizontal surface of a semiconductor substrate.
International Business Machines Corporation


06/02/16
20160155843 

Multi-threshold voltage devices and associated techniques and configurations


Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness.
Intel Corporation


06/02/16
20160155838 

Semiconductor device and fabricating the same


A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region.
Samsung Electronics Co., Ltd.


06/02/16
20160155836 

High voltage semiconductor device and manufacturing method thereof


In an embodiment, on an n−type sic layer on an n+-type sic semiconductor substrate and a p+ layer selectively formed on the n−type sic layer, a p base layer is formed on which, a p+ contact layer is selectively formed. From a surface, an n counter layer penetrates the p base layer to the n−type sic layer.
National Institute Of Advanced Industrial Science And Technology


06/02/16
20160155834 

Iii-nitride device having a buried insulating region


A semiconductor device includes a compound semiconductor material on a semiconductor substrate, the compound semiconductor material having a channel region, a source region, a drain region spaced apart from the source region, the channel region extending between the source region and the drain region, and an insulating region positioned under the channel region in an active region of the semiconductor device so that the insulating region is separated from the channel region by a portion of the compound semiconductor material in the active region. The active region includes the source, the drain and the channel region.
Infineon Technologies Austria Ag


06/02/16
20160155832 

Igbt with buried emitter electrode


There are disclosed herein various implementations of an insulated gate bipolar transistor (igbt) with buried emitter electrodes. Such an igbt may include a collector at a bottom surface of a semiconductor substrate, a drift region having a first conductivity type situated over the collector, and a base layer having a second conductivity type opposite the first conductivity type situated over the drift region.
Infineon Technologies Americas Corp.


06/02/16
20160155819 

Transistor strain-inducing scheme


A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure.
Taiwan Semiconductor Manufacturing Co., Ltd.


06/02/16
20160155812 

Semiconductor device and manufacturing the same


According to one embodiment, a semiconductor device includes a semiconductor substrate in which a recess is provided on a back surface thereof, and a shape of the recess is reflected on a surface of a metal film which is also provided on the back surface of the semiconductor substrate.. .
Kabushiki Kaisha Toshiba


06/02/16
20160155805 

Secondary use of aspect ratio trapping holes as edram structure


A semiconductor structure is provided according to a method in which an aspect ratio trapping process is employed. The structure includes a semiconductor substrate comprising a first semiconductor material having a first lattice constant.
International Business Machines Corporation


06/02/16
20160155802 

Semiconductor device having ridges running in different directions


A semiconductor device includes a first ridge and a second ridge extending from a first main surface of a semiconductor substrate, the first and second ridges running in a first direction. A body region is disposed in a portion of the semiconductor substrate between the first ridge and the second ridge, the first and second ridges being connected with the body region.
Infineon Technologies Austria Ag


06/02/16
20160155779 

Stack type semiconductor memory device


A stack type memory device and a method of manufacturing the same are provided. The stack type memory device includes a semiconductor substrate, a plurality of active layers stacked on the semiconductor substrate, and a gate structure overlapping the plurality of active layers.
Sk Hynix Inc.


06/02/16
20160155771 

Grids in backside illumination image sensor chips and methods for forming the same


A device includes a semiconductor substrate having a front side and a backside, a photo-sensitive device disposed on the front side of the semiconductor substrate, and a first and a second grid line parallel to each other. The first and the second grid lines are on the backside of, and overlying, the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/02/16
20160155758 

Semiconductor device with three or four-terminal-finfet


Semiconductor devices and fabrication methods for simultaneously forming a 3t-finfet and a 4t-finfet on a same substrate are provided. A first fin and a second fin can be formed on a semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


06/02/16
20160155747 

Semiconductor device and a manufacturing method thereof


The reliability and performances of a semiconductor device having a nonvolatile memory are improved. A selection gate electrode is formed over a semiconductor substrate via a first insulation film.
Renesas Electronics Corporation


06/02/16
20160155746 

Static memory cell


The present disclosure provides a static memory cell and fabrication method. A first fin part is formed on a semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


06/02/16
20160155740 

Cmos devices having dual high-mobility channels


A method for forming a semiconductor structure includes providing a semiconductor substrate including a first region and a second region; and forming a first and a second metal-oxide-semiconductor (mos) device. The step of forming the first mos device includes forming a first silicon germanium layer over the first region of the semiconductor substrate; forming a silicon layer over the first silicon germanium layer; forming a first gate dielectric layer over the silicon layer; and patterning the first gate dielectric layer to form a first gate dielectric.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/02/16
20160155732 

Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate


Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed..
Marvell World Trade Ltd.


06/02/16
20160155724 

Semiconductor devices having stacked structures and methods for fabricating the same


Semiconductor devices having stacked structures and methods for fabricating the same are provided. A semiconductor device includes at least one single block including a first semiconductor chip and a second semiconductor chip stacked thereon.

06/02/16
20160155707 

Rf soi switch with backside cavity and the method to form it


An integrated circuit includes a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer, a transistor disposed on the second semiconductor substrate and having a bottom insulated by the insulating layer, a plurality of shallow trench isolations disposed on opposite sides of the transistor, a cavity disposed below the bottom of the transistor, and a plurality of isolation plugs disposed on opposite sides of the cavity. By having a cavity located below the transistor, parasitic couplings between the transistor and the substrate are reduced and the performance of the integrated circuit is improved..
Semiconductor Manufacturing International (shanghai) Corporation


06/02/16
20160155684 

Semiconductor packaging structure and method


A semiconductor packaging method is provided. The method includes providing a semiconductor substrate.
Nantong Fujitsu Microelectronics Co., Ltd.


06/02/16
20160155678 

Semiconductor device and fabricating thereof


A semiconductor device and a method of fabricating the same are disclosed. A semiconductor device according to an embodiment of the present invention includes: a first type doped semiconductor substrate; a second type doped deep well configured such that one or more semiconductor device elements are formed therein; a first type doped first well formed inside a region surrounded by the deep well of the one surface of the semiconductor substrate, and separated from the semiconductor substrate by the deep well; a first electrical contact formed on a part of the one surface of the semiconductor substrate, and electrically connected to the first well; and a second electrical contact formed on another surface of the semiconductor substrate..
Seoul National University R&db Foundation


06/02/16
20160155673 

Semiconductor device having tungsten gate electrode and fabricating the same


The present invention provides a semiconductor device in which the threshold voltage of nmos and the threshold voltage of pmos are independently controllable, and a method for fabricating the same. The method includes: forming a gate insulating film over an nmos region and a pmos region of a semiconductor substrate; forming a carbon-containing tungsten over the gate insulating film formed over one of the nmos region and the pmos region; forming a carbon-containing tungsten nitride over the gate insulating film formed over the other one of the pmos region or the nmos region; forming a tungsten film over the carbon-containing tungsten and the carbon-containing tungsten nitride; post-annealing the carbon-containing tungsten and the carbon-containing tungsten nitride; and etching the tungsten film, the carbon-containing tungsten, and the carbon-containing tungsten nitride, to form a gate electrode in the nmos region and the pmos region.
Sk Hynix Inc.


06/02/16
20160155672 

Simultaneous formation of source/drain openings with different profiles


A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/02/16
20160155653 

System and opening a load lock door valve at a desired pressure after venting


A system and method for reducing particulate contamination during the loading and unloading of semiconductor substrates into a load lock chamber of a semiconductor processing tool. One sensor that measures the differential pressure between the inside of the load lock and the outside atmosphere is provided.
Varian Semiconductor Equipment Associates, Inc.


06/02/16
20160155652 

Method of degassing


A method of degassing semiconductor substrates includes sequentially loading a plurality of semiconductor substrates into a degas apparatus, and degassing the semiconductor substrates in parallel, the degassing of each semiconductor substrate commencing at a different time related to the time at which the semiconductor substrate was loaded into the degas apparatus. The method further includes unloading a semiconductor substrate from the degas apparatus when the semiconductor substrate has been degassed, while semiconductor substrates which were loaded later in the sequence are still being degassed.
Spts Technologies Limited


06/02/16
20160155640 

Manufacturing silicon carbide semiconductor device


A method of manufacturing a silicon carbide semiconductor device includes grinding a back surface of a semiconductor substrate formed of silicon carbide to reduce thickness thereof and provide an altered layer that is ground; removing by polishing or etching, the altered layer from the back surface; forming a nickel film on the back surface of the semiconductor substrate after removing the altered layer; heat treating the nickel film to forming a nickel silicide layer by silicidation; and forming a metal electrode on a surface of the nickel silicide layer.. .
Fuji Electric Co., Ltd.




Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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