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Semiconductor Substrate patents



      
           
This page is updated frequently with new Semiconductor Substrate-related patent applications. Subscribe to the Semiconductor Substrate RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Substrate RSS RSS


Through silicon via bonding structure

Taiwan Semiconductor Manufacturing

Through silicon via bonding structure

Through silicon via bonding structure

International Business Machines

Heterojunction bipolar transistors with an airgap between the extrinsic base and collector

Date/App# patent app List of recent Semiconductor Substrate-related patents
05/21/15
20150140829
 Method for semiconductor manufacturing patent thumbnailnew patent Method for semiconductor manufacturing
A method includes followings operations. A semiconductor substrate is provided.
Taiwan Semiconductor Manufacturing Company Ltd.
05/21/15
20150140820
 Cleaning agent for semiconductor substrates and  processing semiconductor substrate surface patent thumbnailnew patent Cleaning agent for semiconductor substrates and processing semiconductor substrate surface
A cleaning agent is provided for a semiconductor substrate superior in corrosion resistance of a tungsten wiring or a tungsten alloy wiring, and superior in removal property of polishing fines (particle) such as silica or alumina, remaining at surface of the semiconductor substrate, in particular, at surface of a silicon oxide film such as a teos film, after a chemical mechanical polishing process; and a method for processing a semiconductor substrate surface. A cleaning agent for a semiconductor substrate is to be used in a post process of a chemical mechanical polishing process of the semiconductor substrate having a tungsten wiring or a tungsten alloy wiring, and a silicon oxide film, comprising (a) a phosphonic acid-based chelating agent, (b) a primary or secondary monoamine having at least one alkyl group or hydroxyalkyl group in a molecule and (c) water, wherein a ph is over 6 and below 7..
Wako Pure Chemical Industries, Ltd.
05/21/15
20150140815
 Via in substrate with deposited layer patent thumbnailnew patent Via in substrate with deposited layer
An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which leaves the opening with a rough interior surface. A smoothing layer such as a polysilicon layer is applied over the interior surfaces of the openings.
Invensas Corporation
05/21/15
20150140804
 Semiconductor device and  manufacturing the same patent thumbnailnew patent Semiconductor device and manufacturing the same
A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes adjacent storage node contact plugs having different heights, and lower-electrode bowing profiles having different heights, such that a spatial margin between the lower electrodes is assured and a bridge fail is prevented, resulting in improved device operation characteristics.
Sk Hynix Inc.
05/21/15
20150140758
 Method for fabricating finfet on germanium or group iii-v semiconductor substrate patent thumbnailnew patent Method for fabricating finfet on germanium or group iii-v semiconductor substrate
The present invention provides a method for fabricating a finfet on a germanium or group iii-v semiconductor substrate. The process flow of the method mainly includes: forming a pattern structure for a source, a drain and a fine bar connecting the source and the drain; forming an oxide isolation layer; forming a gate structure, a source and a drain structure; and forming metal contacts and metal interconnections.
Peking University
05/21/15
20150140752
 Multiple-time programming memory cells and methods for forming the same patent thumbnailnew patent Multiple-time programming memory cells and methods for forming the same
A method includes forming shallow trench isolation (sti) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the sti regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150140747
 Semiconductor device including transistor and  manufacturing the same patent thumbnailnew patent Semiconductor device including transistor and manufacturing the same
A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface..
Samsung Electronics Co., Ltd.
05/21/15
20150140721
 Patterning of silicon oxide layers using pulsed laser ablation patent thumbnailnew patent Patterning of silicon oxide layers using pulsed laser ablation
Various laser processing schemes are disclosed for producing various types of hetero junction and homo-junction solar cells. The methods include base and emitter contact opening, selective doping, metal ablation, annealing to improve passivation, and selective emitter doping via laser heating of aluminum.
Solexel, Inc.
05/21/15
20150140719
 Vertical conductive connections in semiconductor substrates patent thumbnailnew patent Vertical conductive connections in semiconductor substrates
An embodiment of a die comprising: a semiconductor body including a front side, a back side, and a lateral surface; an electronic device, formed in said semiconductor body and including an active area facing the front side; a vertical conductive connection, extending through the semiconductor body and defining a conductive path between the front side and the back side of the semiconductor body; and a conductive contact, defining a conductive path on the front side of the semiconductor body, between the active area and the vertical conductive connection, wherein the vertical conductive connection is formed on the lateral surface of the die, outside the active area.. .
Stmicroelectronics, S.r.l.
05/21/15
20150140692
 Advanced process control  controlling width of spacer and dummy sidewall in semiconductor device patent thumbnailnew patent Advanced process control controlling width of spacer and dummy sidewall in semiconductor device
An advanced process control (apc) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer.. .
Taiwan Semiconductor Manufacturing Co., Ltd.
05/21/15
20150137852
new patent

Level shift circuit utilizing resistance in semiconductor substrate


An apparatus such as a level shift circuit includes a first signal output device configured to output a first level shifting signal, a second signal output device configured to output a second level shifting signal, and first and second detector devices. The level shifting signals are to control an output switching element of a high potential side of an output device that includes a power source and a load.
Fuji Electric Co., Ltd.
05/21/15
20150137805
new patent

Vertical hall sensor with series-connected hall effect regions


A vertical hall sensor includes first and second vertical hall effect regions formed in a semiconductor substrate and of the same doping type, with first and second pluralities of contacts arranged at one side of the first or second vertical hall effect regions, respectively. The second vertical hall effect region is connected in series with the first vertical hall effect region regarding a power supply to the first and second vertical hall effect regions.
Infineon Technologies Ag
05/21/15
20150137387
new patent

Integrated circuit device including through-silicon via structure and manufacturing the same


An integrated circuit (ic) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer..
05/21/15
20150137373
new patent

Integrated circuits and methods for fabricating integrated circuits with improved contact structures


Integrated circuits with improved contact structures and methods for fabricating integrated circuits with improved contact structures are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a device in and/or on a semiconductor substrate.
Globalfoundries, Inc.
05/21/15
20150137368
new patent

Landing structure for through-silicon via


Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (tsv) using interconnect structures of interconnect layers. In one embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more tsvs and configured to provide one or more corresponding landing structures of the one or more tsvs.
Intel Corporation
05/21/15
20150137328
new patent

Through silicon via bonding structure


System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining tsvs that protrude from the buffer layer in order to prevent potential voids that might form.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150137326
new patent

Semiconductor devices having through-electrodes and methods for fabricating the same


A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer..
05/21/15
20150137320
new patent

Semiconductor device and fabricating the same


A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region.
Samsung Electronics Co., Ltd.
05/21/15
20150137319
new patent

Iii nitride semiconductor substrate, epitaxial substrate, and semiconductor device


In a semiconductor device 100, it is possible to prevent c from piling up at a boundary face between an epitaxial layer 22 and a group iii nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of s and 2 at % to 20 at % of oxide in terms of o in a surface layer 12. By thus preventing c from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group iii nitride semiconductor substrate 10.
Sumitomo Electric Industies, Ltd.
05/21/15
20150137313
new patent

Coil arrangement with metal filling


Devices, methods and production devices that relate to the forming of a coil on a semiconductor substrate are provided. Arranged within the coil is a metal filling, for example with a density of less than 20%..
Lantiq Deutschland Gmbh
05/21/15
20150137308
new patent

Self-aligned dual-height isolation for bulk finfet


A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate.
Globalfoundries Inc.
05/21/15
20150137306
new patent

Semiconductor device and manufacturing the same


An n type diffusion layer in which a high-side circuit region is disposed is formed from a surface of a p type epitaxial layer covering a surface of a p type semiconductor substrate to reach the surface of the semiconductor substrate. An n type high breakdown voltage isolation region is formed with a prescribed width to surround high-side circuit region.
Mitsubishi Electric Corporation
05/21/15
20150137305
new patent

Protective structure and producing a protective structure


Described herein is a protective structure. The protective structure includes a semiconductor substrate, a first diode disposed at least one of in or on the semiconductor substrate and a diode arrangement disposed at least one of in or on the semiconductor substrate.
Infineon Technologies Ag
05/21/15
20150137300
new patent

Infrared sensor device and producing an infrared sensor device


An infrared sensor device includes a semiconductor substrate, at least one sensor element that is micromechanically formed in the semiconductor substrate, and at least one calibration element, which is micromechanically formed in the semiconductor substrate, for the sensor element. An absorber material is arranged on the semiconductor substrate in the area of the sensor element and the calibration element.
Robert Bosch Gmbh
05/21/15
20150137298
new patent

Light detection device


A semiconductor light detection element has a plurality of channels, each of which consists of a photodiode array including a plurality of avalanche photodiodes operating in geiger mode, quenching resistors connected in series to the respective avalanche photodiodes, and signal lines to which the quenching resistors are connected in parallel. A mounting substrate is configured so that a plurality of electrodes corresponding to the respective channels are arranged on a third principal surface side and so that a signal processing unit for processing output signals from the respective channels is arranged on a fourth principal surface side.
Hamamatsu Photonics K.k.
05/21/15
20150137268
new patent

Non-planar sige channel pfet


Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a channel layer formed of a germanium compound having a germanium concentration b formed on a semiconductor substrate having a germanium concentration of a, the germanium concentration of the substrate a being less than the germanium concentration of the channel layer b.
Taiwan Semiconductor Manfacturing Company Limited
05/21/15
20150137265
new patent

Fin field effect transistor and forming the same


A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions.
Taiwan Semiconductor Manufacturing Co., Ltd
05/21/15
20150137260
new patent

Semiconductor device


A plurality of unit misfet elements connected in parallel with each other to make up a power misfet are formed in an ldmosfet forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power misfet is formed in a driver circuit region on the main surface of the semiconductor substrate.
Renesas Electronics Corporation
05/21/15
20150137242
new patent

Insulation wall between transistors on soi


An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.. .
Stmicroelectronics (crolles 2) Sas
05/21/15
20150137240
new patent

Semiconductor device with a low-k spacer and forming the same


A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer.
International Business Machines Corporation
05/21/15
20150137238
new patent

High-frequency semiconductor device and manufacturing the same


A high-frequency semiconductor device, wherein on one surface of a semiconductor substrate, a first insulating layer, an undoped epitaxial polysilicon layer in a state of column crystal, a second insulating layer, and a semiconductor layer are formed in order from a side of the one surface, and a high-frequency transistor is formed in a location of the semiconductor layer facing the undoped epitaxial polysilicon layer with the second insulating layer in between.. .
Sony Corporation
05/21/15
20150137236
new patent

Silicon-on-insulator finfet with bulk source and drain


Embodiments of the invention provide a semiconductor structure including a finfet having an epitaxial semiconductor region in direct physical contact with a plurality of fins, wherein the epitaxial semiconductor region traverses an insulator layer and is in direct physical contact with the semiconductor substrate. The gate of the finfet is disposed over an insulator layer, such as a buried oxide layer.
Globalfounderies Inc.
05/21/15
20150137231
new patent

Lateral double diffused metal-oxide-semiconductor device and fabricating the same


A lateral double diffused metal-oxide-semiconductor device includes: a semiconductor substrate; an epitaxial semiconductor layer disposed over the semiconductor substrate; a gate structure disposed over the epitaxial semiconductor layer; a first doped region disposed in the epitaxial semiconductor layer at a first side of the gate structure; a second doped region disposed in the epitaxial semiconductor layer at a second side of the gate structure; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a trench formed in the third doped region, the first doped region and the epitaxial semiconductor layer under the first doped region; a conductive contact formed in the trench; and a fifth doped region disposed in the epitaxial semiconductor layer under the trench.. .
Vanguard International Semiconductor Corporation
05/21/15
20150137226
new patent

Semiconductor device and producing a semiconductor device


A semiconductor device includes a semiconductor substrate having first regions of a first conductivity type and body regions of the first conductivity type, which are arranged in a manner adjoining the first region and overlap the latter in each case on a side of the first region which faces a first surface of the semiconductor substrate, and having a multiplicity of drift zone regions arranged between the first regions and composed of a semiconductor material of a second conductivity type, which is different than the first conductivity type. The first regions and the drift zone regions are arranged alternately and form a superjunction structure.
Infineon Technologies Ag
05/21/15
20150137213
new patent

Nonvolatile semiconductor storage device


According to one embodiment, a control gate is formed on the semiconductor substrate and includes a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole.
Kabushiki Kaisha Toshiba
05/21/15
20150137211
new patent

Semiconductor device manufacturing method and semiconductor device


A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.. .
Fujitsu Semiconductor Limited
05/21/15
20150137206
new patent

Hk embodied flash memory and methods of forming the same


A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150137201
new patent

High density linear capacitor


A methods for fabricating a capacitor structure includes fabricating polysilicon structures on a semiconductor substrate. The method further includes fabricating m1 to diffusion (md) interconnects on the semiconductor substrate.
Qualcomm Incorporated
05/21/15
20150137186
new patent

Formation of an asymmetric trench in a semiconductor substrate and a bipolar semiconductor device having an asymmetric trench isolation region


Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench.
International Business Machines Corporation
05/21/15
20150137185
new patent

Heterojunction bipolar transistors with an airgap between the extrinsic base and collector


Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base.
International Business Machines Corporation
05/21/15
20150137181
new patent

Stress inducing contact metal in finfet cmos


A method of forming a semiconductor structure includes forming a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a semiconductor substrate. A gate structure is formed covering a first portion of the first and second plurality of fins.
International Business Machines Corporation
05/21/15
20150137175
new patent

Charge reservoir igbt top structure


An igbt device includes one or more trench gates disposed over a semiconductor substrate and a floating body region of the first conductivity type disposed between two neighboring trench gates and between a semiconductor substrate and a heavily doped top region of the second conductivity type. A body region of the first conductivity type disposed over the top region has a doping concentration higher than that of the floating body region of the first conductivity type.
Alpha And Omega Semiconductor Incorporated
05/21/15
20150137174
new patent

Methods and increased holding voltage in silicon controlled rectifiers for esd protection


Methods and apparatus for increased holding voltage scrs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150137146
new patent

Transistor device


Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer.
Semiconductor Manufacturing International Corp
05/21/15
20150137136
new patent

Gallium nitride semiconductor substrate with semiconductor film formed therein


A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more signal crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis.
Sumitomo Electric Industries, Ltd.
05/21/15
20150137135
new patent

Semiconductor devices with integrated schotky diodes and methods of fabrication


An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a schottky metal layer disposed over the substrate adjacent the gate electrode. The schottky metal layer includes a schottky contact electrically coupled to the channel which provides a schottky junction and at least one alignment mark disposed over the semiconductor substrate.
05/21/15
20150137066
new patent

Electronic device


An electronic device includes a memory. The memory includes a first cell array including a plurality of flash memory cells, a first peripheral circuit suitable for controlling the first cell array, a second cell array including a plurality of variable resistance memory cells, and a second peripheral circuit suitable for controlling the second cell array.
Sk Hynix Inc.
05/21/15
20150136957
new patent

Optical receiver module and optical transmitter module


An optical receiver module includes: a lens array including a plurality of condenser lenses arranged in one direction to define a plane with optical axes in parallel to each other; and a light receiving element array including a plurality of light receiving elements each configured to receive light emitted from each of the condenser lenses. The light receiving element array includes: a semiconductor substrate to which the light from each of the condenser lenses is input and through which the light is transmitted; and light receiving portions each configured to receive the light transmitted through the semiconductor substrate and convert the light into an electrical signal.
Oclaro Japan, Inc.
05/21/15
20150136755
new patent

Optical design for line generation using microlens array


Embodiments of the present disclosure relate to an apparatus for thermally processing a semiconductor substrate. In one embodiment, the apparatus includes a substrate support, a beam source having a fast axis for emitting a beam along an optical path intersecting the substrate support, and a homogenizer disposed along the optical path between the beam source and the substrate support.
Applied Materials, Inc.
05/21/15
20150136228
new patent

Processes for uniform metal semiconductor alloy formation for front side contact metallization and photovoltaic device formed therefrom


A method of forming a photovoltaic device is provided that includes a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion, wherein an upper exposed surface of one of the semiconductor portions represents a front side surface of the semiconductor substrate. Patterned antireflective coating layers are formed on the front side surface of the semiconductor surface to provide a grid pattern including a busbar region and finger region.
International Business Machines Corporation
05/21/15
20150136221
new patent

Solar cell element


To improve characteristics, reliability, and the like of a solar cell element, the solar cell element includes: a semiconductor substrate which includes a first main surface and a second main surface that is positioned opposite to the first main surface, and in which a p-type semiconductor region and an n-type semiconductor region are stacked in such a manner that the p-type semiconductor region is positioned closest to the first main surface and the n-type semiconductor region is positioned closest to the second main surface; a first passivation layer which is disposed on the p-type semiconductor region that is positioned closest to the first main surface, and which includes aluminum oxide; and a first protective layer that is disposed on the first passivation layer. The first protective layer includes an oxide that contains at least one kind of zirconium and hafnium..
Kyocera Corporation
05/21/15
20150136186
new patent

System for processing substrates with two or more ultraviolet light sources that provide different wavelengths of light


Systems for cleaning substrates including cleaning of semiconductor substrates, use atmospheric or sub-atmospheric ultraviolet (uv) light to improve selectivity of conventional wet chemical cleaning in the manufacture of semiconductor devices. The uv light systems are configured to improve front-end-of-line (feol) (e.g., non-metal) or back-end-of-line (beol) (e.g., metal) removal of etch by-products (e.g., polymers) and/or mask layers from underlying materials.
Tokyo Electron Limited
05/21/15
20150135549
new patent

Supercritical drying semiconductor substrate


According to one embodiment, a supercritical drying method for a semiconductor substrate comprises introducing a semiconductor substrate, a surface of the semiconductor substrate being wet with a water-soluble organic solvent, to the inside of a chamber, hermetically sealing the chamber and increasing a temperature inside the chamber to not lower than a critical temperature of the water-soluble organic solvent, thereby bringing the water-soluble organic solvent into a supercritical state, decreasing a pressure inside the chamber and changing the water-soluble organic solvent in the supercritical state to a gas, thereby discharging the water-soluble organic solvent from the chamber, starting a supply of an inert gas into the chamber as the pressure inside the chamber decreases to atmospheric pressure, and cooling the semiconductor substrate in a state where the inert gas exists inside the chamber.. .
Kabushiki Kaisha Toshiba
05/14/15
20150132949

Fabrication methods of chip device packages


A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface.
05/14/15
20150132948

Method of fabricating a semiconductor device, and chemical mechanical polish tool


The present disclosure provides a method of fabricating a semiconductor device with metal interconnections and a design of a tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device, the method includes providing a semiconductor substrate, depositing a dielectric layer over the semiconductor substrate, forming at least one trench in the dielectric layer, and forming a metallization layer in the trench and over the dielectric layer.
05/14/15
20150132947

Method of manufacturing a semiconductor device


A method of manufacturing a semiconductor device may include: forming an opening in a dielectric layer, the opening exposing a non-conductive layer disposed over a semiconductor substrate; forming a self-assembled monolayer (sam) within the opening and over the non-conductive layer; forming a catalytic layer within the opening and over the sam; filling the opening having the sam and the catalytic layer with a conductive material to form a plug; and forming a barrier layer on sidewalls of the plug.. .
05/14/15
20150132937

Method of manufacturing semiconductor device


There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate having an active region; forming a dielectric layer for gate insulation on the active region; forming a curing layer with a material containing germanium (ge) on the dielectric layer; heat-treating the curing layer; and removing the curing layer. The germanium-containing material may be silicon germanium (sige) or germanium (ge)..
05/14/15
20150132935

Semiconductor device and fabricating the same


A semiconductor device includes a semiconductor substrate having an active region defined by an isolation layer, a gate line defining a bit line contact region in the active region and extending in one direction, and a dielectric layer covering the semiconductor substrate and the gate line formed in the semiconductor substrate. The semiconductor device is provided with a bit line contact hole formed in the dielectric layer and exposing the bit line contact region.
05/14/15
20150132932

Semiconductor device with selectively etched surface passivation


A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel..
05/14/15
20150132930

Method for manufacturing semiconductor device and annealing method


A semiconductor device manufacturing method includes: amorphizing the impurity diffusion layer formation region; doping the impurity diffusion layer formation region of the semiconductor substrate with impurities; and performing an annealing treatment including lamp annealing in which a heating lamp is used and microwave annealing in which microwaves are irradiated, on the semiconductor substrate doped with the impurities, for activating the impurities. In addition to activation of the impurity, re-crystallization and removing of crystal defects also take place in the annealing treatment..
05/14/15
20150132921

Gap-fill methods


Provided are gap-fill methods. The methods comprise: (a) providing a semiconductor substrate having a relief image on a surface of the substrate, the relief image comprising a plurality of gaps to be filled; (b) applying a gap-fill composition over the relief image, wherein the gap-fill composition comprises a self-crosslinkable polymer and a solvent, wherein the self-crosslinkable polymer comprises a first unit comprising a polymerized backbone and a crosslinkable group pendant to the backbone; and (c) heating the gap-fill composition at a temperature to cause the polymer to self-crosslink.
05/14/15
20150132914

Methods for fabricating integrated circuits with robust gate electrode structure protection


Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate.
05/14/15
20150132913

Mechanisms for forming semiconductor device having stable dislocation profile


Embodiments that relate to mechanisms for providing a stable dislocation profile are provided. A semiconductor substrate having a gate stack is provided.
05/14/15
20150132905

Structure and single gate non-volatile memory device having a capacitor well doping design with improved coupling efficiency


The nvm device includes a semiconductor substrate having a first region and a second region. The nvm device includes a data-storing structure formed in the first region and designed operable to retain charges.
05/14/15
20150132904

Semiconductor device and a manufacturing the same


A semiconductor device includes an n channel conductivity type fet having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type fet having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel fet has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel fet to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel fet.
05/14/15
20150132902

Polysilicon design for replacement gate technology


The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate.
05/14/15
20150132895

Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device is provided. The semiconductor device includes a cathode region of the diode, a first buffer region adjacent to the cathode region at a rear surface side of a semiconductor substrate, a collector region of the igbt, and a second buffer region adjacent to the collector region at the rear surface side.
05/14/15
20150132865

Method for forming bumps, semiconductor device and manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus


A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face.
05/14/15
20150131942

Polarization splitter/combiner based on a one-dimensional grating coupler


A grating coupler comprising a semiconductor substrate, a one-dimensional (1d) grating element coupled to the semiconductor substrate, wherein the 1d grating element is adapted to simultaneously couple a first polarization component of an incident optical beam with a transverse electric (te) waveguide mode in a first propagation direction and a second polarization component of the incident optical beam with a transverse magnetic (tm) waveguide mode in a second propagation direction, and wherein the first propagation direction is opposite of the second propagation direction.. .
05/14/15
20150131940

Integrated optical sub-assembly


An optical subassembly includes a thru optical via (104) formed through a semiconductor substrate (102), an optoelectronic component (108) secured to the substrate (102) such that an active region (106) of the optoelectronic component is aligned with the thru optical via (104), and circuitry (110) formed into the substrate (102), the circuitry to connect to and operate in accordance with the optoelectronic component (108).. .
05/14/15
20150130531

System and remote temperature sensing with routing resistance compensation


An integrated circuit die includes multiple temperature sensor units each for measuring the temperature of respective regions of a semiconductor substrate of the integrated circuit die. The temperature sensor units are each coupled to a multiplexer by respective groups of signal lines.
05/14/15
20150130084

Package structure and manufacturing the same


A fan-out package structure including a heat radiating side edge that includes a semiconductor substrate; a bond pad located on the semiconductor substrate; and a redistribution layer connected with the bond pad and located on the semiconductor substrate, wherein an end of the redistribution layer extends to a sidewall of the semiconductor substrate, and the end is coplanar with the sidewall.. .
05/14/15
20150130067

Ohmic contact structure and semiconductor device having the same


This invention provides an ohmic contact structure including: a semiconductor substrate having a top surface which includes a plurality of micro-structures; and a conductive layer, which is formed on the micro-structures. An ohmic contact is formed by the conductive layer and the semiconductor substrate.
05/14/15
20150130032

Ultra high voltage electrostatic discharge protection device with current gain


A semiconductor device configured to provide increased current gain comprises a semiconductor substrate having a first conductivity type. The device also comprises a first semiconductor region having a second conductivity type.
05/14/15
20150130029

Semiconductor constructions having through-substrate interconnects


Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening.
05/14/15
20150130028

Method of manufacturing semiconductor chip, semiconductor chip, and semiconductor device


A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.. .
05/14/15
20150130013

Semiconductor device and forming a semiconductor device


A semiconductor device includes at least one ohmic contact region between a semiconductor substrate of the semiconductor device and an electrically conductive structure arranged adjacent to the semiconductor substrate. Further, the semiconductor device includes at least one schottky contact region between the semiconductor substrate of the semiconductor device and the electrically conductive structure.
05/14/15
20150130009

Semiconductor device and manufacturing same


To provide a semiconductor device having a photoelectric conversion element having a high sensitivity, causing less blooming, and capable of providing a highly reliable image. The semiconductor device has a semiconductor substrate, a first p type epitaxial layer, a second p type epitaxial layer, and a first photoelectric conversion element.


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Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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