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Semiconductor Substrate patents



      
           
This page is updated frequently with new Semiconductor Substrate-related patent applications. Subscribe to the Semiconductor Substrate RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Substrate RSS RSS


Method for manufacturing semiconductor device

Toyota Jidosha

Method for manufacturing semiconductor device

Semiconductor memory apparatus and fabrication method thereof

Sk Hynix

Semiconductor memory apparatus and fabrication method thereof

Semiconductor memory apparatus and fabrication method thereof

Renesas Electronics

Method of manufacturing semiconductor device


Date/App# patent app List of recent Semiconductor Substrate-related patents
07/23/15
20150208011 
 Photodetector comprising a pinned photodiode that is formed by an optically sensitive layer and a silicon diode patent thumbnailnew patent Photodetector comprising a pinned photodiode that is formed by an optically sensitive layer and a silicon diode
In various embodiments, a photodetector includes a semiconductor substrate and a plurality of pixel regions. Each of the plurality of pixel regions comprises an optically sensitive layer over the semiconductor substrate.
Invisage Technologies, Inc.


07/23/15
20150207505 
 Semiconductor device including enhanced variability patent thumbnailnew patent Semiconductor device including enhanced variability
A physical unclonable function (puf) semiconductor device includes a semiconductor substrate, and a well formed in the semiconductor substrate. The well includes a first region having a first concentration of ions, and at least one second region having a second concentration that is less than the first concentration.
International Business Machines Corporation


07/23/15
20150207298 
 Method for producing semiconductor optical device patent thumbnailnew patent Method for producing semiconductor optical device
A method for producing a semiconductor optical device includes the steps of forming a first semiconductor substrate having a stacked semiconductor layer; adjusting a proportion of h2o molecules in a process chamber, the process chamber having an inner surface on which an alumite film is formed by anodizing; and, after the step of adjusting the proportion of h2o molecules, forming a substrate product by arranging the first semiconductor substrate in the process chamber and etching the stacked semiconductor layer using a dry etching method in which a halogen-based gas is used as an etching gas. In addition, the step of adjusting the proportion of h2o molecules in the process chamber includes a first substep of evacuating the process chamber; a second substep of dry-cleaning the inner surface of the process chamber; and a third substep of generating a plasma in the process chamber using a halogen-based gas..
Sumitomo Electric Industries, Ltd.


07/23/15
20150207073 
 Semiconductor memory apparatus and fabrication method thereof patent thumbnailnew patent Semiconductor memory apparatus and fabrication method thereof
Semiconductor memory apparatus and a method of fabricating the same are provided. The semiconductor memory apparatus includes a semiconductor substrate in which a cell area and a peripheral area are defined, a plurality of pillars formed in the a cell area of the semiconductor substrate to a first depth, a stepped part formed in the peripheral area to a height corresponding to the first depth, a recessed part formed in the stepped part to a second depth, and a core switching device formed in the recessed part..
Sk Hynix Inc.


07/23/15
20150206990 
 Solar cell production method, and solar cell produced by same production method patent thumbnailnew patent Solar cell production method, and solar cell produced by same production method
This solar cell production method involves productively forming an antireflection film comprising silicon nitride, said antireflection film having an excellent passivation effect. In an embodiment, a remote plasma cvd is used to form a first silicon nitride film on a semiconductor substrate (102) using the plasma flow from a first plasma chamber (111), then to form a second silicon nitride film, which has a different composition than the first silicon nitride film, using the plasma flow from a second plasma chamber (112), into which ammonia gas and silane gas have been introduced at a different flow ratio than that of the first plasma chamber (111).
Shin-etsu Chemical Co., Ltd.


07/23/15
20150206974 
 Semiconductor device and  fabricating the same patent thumbnailnew patent Semiconductor device and fabricating the same
A semiconductor device includes a semiconductor substrate comprising a group iii element and a group v element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region.

07/23/15
20150206973 
 Semiconductor device and  manufacturing same patent thumbnailnew patent Semiconductor device and manufacturing same
[solution] a method according to the present invention comprises: a step of forming dopant-diffused layers 5a, 5b on the main surface of a semiconductor substrate 1; a step of forming a trench 11 on a bottom surface of which is erected at least one semiconductor beam 4, each connected at one end to the dopant-diffused layer 5a and connected at the other end to the dopant-diffused layer 5b; a step of forming a gate insulating film 6 on an inner surface of the trench 11, including the side surfaces of each at least one semiconductor beam 4, and on an upper surface of each at least one semiconductor beam 4; a step of depositing a gate electrode material having a film thickness that fills the trench 11, after the gate insulating film 6 has been formed; and a step of removing the gate electrode material that is located outside the trench 11 as seen in a plan view, while leaving the gate electrode material that is located inside the trench 11 as seen in a plan view.. .

07/23/15
20150206970 
 Body-tied, strained-channel multi-gate device and methods of manufacturing same patent thumbnailnew patent Body-tied, strained-channel multi-gate device and methods of manufacturing same
A fin-fet or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206969 
 Semiconductor device, related manufacturing method, and related electronic device patent thumbnailnew patent Semiconductor device, related manufacturing method, and related electronic device
A semiconductor device may include a semiconductor substrate. The semiconductor device may further include a gate electrode that overlaps the semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/23/15
20150206967 
 Semiconductor device patent thumbnailnew patent Semiconductor device
A semiconductor device includes a silicon carbide semiconductor substrate, a silicon carbide layer, a switching element section, and an overvoltage detection element section whose area is smaller than that of the switching element section. The switching element section includes a first electrode pad, a first terminal section surrounding the first electrode pad and provided in the silicon carbide layer, and a first insulating film covering the first terminal section.
Panasonic Intellectual Property Management Co., Ltd.


07/23/15
20150206959 
new patent

Formation of a high aspect ratio trench in a semiconductor substrate and a bipolar semiconductor device having a high aspect ratio trench isolation region


Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening.
International Business Machines Corporation


07/23/15
20150206958 
new patent

Tunnel field-effect transistor


A tunnel field-effect transistor (tfet) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure comprises a channel region and a source region disposed on the channel region.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206956 
new patent

Semiconductor device and manufacturing the same


A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (seg) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate..
Samsung Electronics Co., Ltd.


07/23/15
20150206943 
new patent

Edge termination configurations for high voltage semiconductor power devices


This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench..

07/23/15
20150206936 
new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a base dielectric layer, a semiconductor substrate layer disposed on the base dielectric layer, and a transistor disposed in the semiconductor substrate layer. The transistor includes a gate dielectric layer disposed on the semiconductor substrate layer, a gate electrode disposed on the gate dielectric layer, source and drain electrodes disposed within the semiconductor substrate layer on opposite sides of the gate electrode, an undoped channel region, a base dopant region, and a threshold voltage setting region.
Semiconductor Manufacturing International (shanghai) Corporation


07/23/15
20150206934 
new patent

Method of manufacturing semiconductor device


Provided is a semiconductor device having improved reliability. Over a semiconductor substrate, a first coil is formed via a first insulating film.
Renesas Electronics Corporation


07/23/15
20150206925 
new patent

Solid state imaging element, production method thereof and electronic device


There is provided a solid state imaging element including: an insulation film laminated on a semiconductor substrate; a lower transparent electrode film formed and separated by the insulation film per pixel; a hydrophobic treatment layer laminated on a flat surface of the insulation film and the lower transparent electrode film; an organic photoelectric conversion layer laminated on the hydrophobic treatment layer; and an upper transparent electrode film laminated on the organic photoelectric conversion layer. Also, there is provided a production method thereof and an electronic device..
Sony Corporation


07/23/15
20150206923 
new patent

Semiconductor device and manufacturing semiconductor device


A semiconductor device includes a first fin-shaped semiconductor layer on a semiconductor substrate, a first insulating film around the first fin-shaped semiconductor layer, a first pillar-shaped semiconductor layer on the first fin-shaped semiconductor layer, a first gate insulating film around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film and extending in a direction perpendicular to the first fin-shaped semiconductor layer, a second diffusion layer disposed in a lower portion of the first pillar-shaped semiconductor layer, a third gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer, a first contact electrode surrounding the third gate insulating film, a second contact electrode that connects an upper portion of the first contact electrode to an upper portion of the first pillar-shaped semiconductor layer, and a first magnetic tunnel junction memory element on the second contact electrode.. .
Unisantis Electronics Singapore Pte. Ltd.


07/23/15
20150206919 
new patent

Cmos integrated fabrication of thermopile pixel on semiconductor substrate with buried insulation regions


A method for manufacturing an imaging device in a semiconductor substrate is disclosed. The substrate includes a first surface, a second surface substantially opposite the first surface, and a thickness defined by a distance between the first surface and the second surface.
Excelitas Technologies Singapore Pte. Ltd.


07/23/15
20150206917 
new patent

Image-sensor device structure and manufacturing


Embodiments of an image-sensor device structure and a method of manufacturing thereof are provided. The image-sensor device structure includes a semiconductor substrate and a light-sensing region in the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/23/15
20150206915 
new patent

Image-sensor device and manufacturing the same


An image-sensor device includes a first semiconductor substrate. The image-sensor device further includes a second semiconductor substrate under the first semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


07/23/15
20150206911 
new patent

Solid-state imaging device and manufacturing the same


According to one embodiment, there is a solid-state imaging device including an imaging region. In the imaging region, a plurality of pixels are arranged two-dimensionally.
Kabushiki Kaisha Toshiba


07/23/15
20150206888 
new patent

Static random access memory and fabrication methods thereof


A method for fabricating a static random access memory is provided. The method includes providing a semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/23/15
20150206883 
new patent

Manufacturing capacitor structure and semiconductor device using the same


The instant disclosure relates to a semiconductor device which includes a semiconductor substrate, at least one patterned reinforcing layer, a plurality of lower electrodes, and a supporting layer. The at least one patterned reinforcing layer is arranged above the semiconductor substrate, wherein the at least one patterned reinforcing layer has a plurality of reinforcing structures configured to define a plurality of alignment apertures.
Inotera Memories, Inc.


07/23/15
20150206881 
new patent

Formation of silicide contacts in semiconductor devices


Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nfet) region and a p-type field effect transistor (pfet) region; performing a pre-amorphized implantation (pai) process to an n-type doped silicon (si) feature in on the nfet region and a p-type doped silicon germanium (sige) feature in the pfet region, thereby forming an n-type amorphous silicon (a-si) feature and a p-type amorphous silicon germanium (a-sige) feature; depositing a metal layer over each of the a-si and a-sige features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-si and the p-type a-sige features.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206873 
new patent

Alignment marks in non-sti isolation formation and methods of forming the same


A method includes forming a photo resist over a semiconductor substrate of a wafer, patterning the photo resist to form a first opening in the photo resist, and implanting the semiconductor substrate using the photo resist as an implantation mask. An implanted region is formed in the semiconductor substrate, wherein the implanted region is overlapped by the first opening.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206840 
new patent

Semiconductor device structure and manufacturing the same


Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


07/23/15
20150206835 
new patent

Method, structures and designing reduced delamination integrated circuits


An integrated circuit wire structure. The structure includes a set of interconnect levels over a semiconductor substrate, each interconnect level of the set of interconnect levels comprising operational wires embedded in an interlevel dielectric layer; a dielectric barrier layer on an uppermost interconnect level of the set of interconnect levels and a bonding pad on the passivation layer; a stress reduction zone surrounding a perimeter of the bonding pad and extending into the set of interconnect levels; elongated fill wires in each of the interconnect levels in the stress reduction zone, the elongated fill wires not connected to any of the non-ground operational wires; and the elongated fill wires of each interconnect level of each set of interconnect levels physically connected to elongated fill wires of immediately upper and lower interconnect levels of the set of fill levels..
International Business Machines Corporation


07/23/15
20150206827 
new patent

Semiconductor device with through silicon via and alignment mark


A semiconductor device with a semiconductor substrate having a first surface and an opposite-facing second surface, a through electrode electrically connected to the semiconductor element and penetrating the semiconductor substrate from the first surface to the second surface, and a conductor, not electrically connected to the semiconductor element, penetrating the semiconductor substrate from the first surface to the second surface, where the through electrode and the conductor have different shapes in plan view.. .
Ps4 Luxco S.a.r.l.


07/23/15
20150206826 
new patent

Semiconductor device and manufacturing semiconductor device


A semiconductor device including: a base material portion that includes a semiconductor substrate and an insulating film that is formed on one face of the semiconductor substrate and on which a vertical hole is formed along the thickness direction of the semiconductor substrate; a vertical hole wiring portion that includes a vertical hole electrode formed on a side wall of the base material portion that forms the vertical hole; a metallic film that is formed within the insulating film and that is electrically connected to the vertical hole wiring portion; and a conductive protective film that is formed to be in contact with the metallic film within the insulating film and that is formed in a region that includes a contact region of a probe during a probe test that is performed in the middle of manufacture on a film face of the metallic film.. .
Sony Corporation


07/23/15
20150206813 
new patent

Methods and structures for processing semiconductor devices


Methods of processing a semiconductor device include attaching a semiconductor substrate to a carrier substrate, forming a silane material over an exposed portion of the carrier substrate, and curing the silane material to form a hydrophobic coating over the carrier substrate. The hydrophobic coating may reduce or prevent undercut of the semiconductor substrate due to wicking of adhesive from between the semiconductor substrate and the carrier substrate during processing.
Micron Technology, Inc.


07/23/15
20150206810 
new patent

Stacked semiconductor structure and manufacturing the same


A stacked semiconductor structure and a manufacturing method for the same are provided. The stacked semiconductor structure is provided, which comprises a first semiconductor substrate, a second semiconductor substrate, a dielectric layer, a trench, a via, and a conductive structure.
United Microelectronics Corp.


07/23/15
20150206806 
new patent

Method and system of measuring semiconductor device and fabricating semiconductor device using the same


The measurement method may include obtaining first measurement data from a recess region formed in a semiconductor substrate, obtaining second measurement data from a conductive pattern filling a portion of the recess region, calculating a first volume of the recess region from the first measurement data, calculating a second volume of the conductive pattern from the second measurement data, and calculating a measurement target parameter using a difference between the first and second volumes.. .

07/23/15
20150206794 
new patent

Method for removing micro scratches in chemical mechanical polishing processes


A chemical mechanical polishing process for manufacturing a semiconductor device includes forming a conductive layer over a first dielectric layer formed over a semiconductor substrate. The conductive layer is patterned to form a patterned conductive layer with a plurality of openings.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206791 
new patent

Method for forming semiconductor device structure


In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer on a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/23/15
20150206788 
new patent

Double patterning forming semiconductor active areas and isolation regions


A method of forming active areas and isolation regions in a semiconductor substrate using a double patterning process. The method include forming a first material on the substrate surface, forming a second material on the first material, forming a plurality of first trenches into the second material wherein the plurality of first trenches are parallel to each other, forming a second trench into the second material wherein the second trench is perpendicular to and crosses the plurality of first trenches in a central region of the substrate, filling the first and second trenches with a third material, removing the second material to form third trenches in the third material that are parallel to each other and do not extend through the central region of the substrate, and extending the third trenches through the first material and into the substrate..
Silicon Storage Technology, Inc.


07/23/15
20150206758 
new patent

Method for manufacturing semiconductor device


A method includes: forming a front surface structure of a semiconductor element on a front surface side of a semiconductor substrate; forming crystal defects in the semiconductor substrate by implanting charged particles into the semiconductor substrate; subjecting the semiconductor substrate to a heat treatment after having formed the crystal defects; attaching a supporting plate on the front surface side of the semiconductor substrate after the heat treatment; thinning the semiconductor substrate by grinding a back surface side of the semiconductor substrate to which the supporting plate has been attached; and forming a back surface structure of the semiconductor element on a back surface of the thinned semiconductor substrate.. .
Toyota Jidosha Kabushiki Kaisha


07/23/15
20150206754 
new patent

Gate contact with vertical isolation from source-drain


A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ild) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed.
International Business Machines Corporation


07/23/15
20150206746 
new patent

Semiconductor fins on a trench isolation region in a bulk semiconductor substrate and a forming the semiconductor fins


Disclosed are semiconductor structures with monocrystalline semiconductor fins, which are above a trench isolation region in a semiconductor substrate and which can be incorporated into semiconductor device(s). Also disclosed are methods of forming such structures by forming sidewall spacers on opposing sides of mandrels on a dielectric cap layer.
International Business Machines Corporation


07/23/15
20150206740 
new patent

Electrical charge regulation for a semiconductor substrate during charged particle beam processing


A method for preparing a semiconductor target (10), the method comprising providing a semiconductor substrate (12) including a main substrate surface (14) which defines a substrate periphery (20) along an outer edge. The semiconductor substrate (12) further has an structure layer (30) arranged on the main substrate surface, and comprising a structure layer periphery (32) that is located inwards with respect to the substrate periphery, so as to leave exposed a peripheral substrate region (22) along the substrate periphery.
Mapper Lithography Ip B.v


07/23/15
20150206595 
new patent

Antifuse array architecture


An anti-fuse including a program transistor which can be short-circuited depending on whether the program transistor is programmed, and also including a read transistor which is coupled with the program transistor and a bit line, and outputs information to the bit line based on whether the program transistor is short-circuited, comprising: an active region formed in a first direction in a semiconductor substrate; a bit line contact formed over the active region and coupled with the bit line; a program gate electrode the entire or part of which is buried in the active region over the program transistor; and a read gate electrode disposed over the read transistor and formed between the program gate electrode and the bit line contact.. .
Sk Hynix Inc.


07/23/15
20150205897 
new patent

Method of simulating semiconductor devices and designing semiconductor devices using the same


Provided are an apparatus and a method for simulating a semiconductor device. The method includes: modeling, through an input interface of a simulation device, a flat transistor as a first transistor; modeling, through the input interface, a first corner transistor as a second transistor; and calculating, by a processor of the simulation device, an output electrical signal in response to an input electrical signal applied to the first transistor and the second transistor to simulate at least one electrical characteristic of the semiconductor device.
Samsung Electronics Co., Ltd.


07/23/15
20150203351 
new patent

Semiconductor device and fabrication method


Semiconductor devices and fabrication methods are provided. In a semiconductor device, a semiconductor substrate includes a first electrode layer having a top surface coplanar with a top surface of the semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/16/15
20150200627 

Phase noise reduction in voltage controlled oscillators


A voltage controlled oscillator (vco), a method of designing a voltage controlled oscillator, and a design structure comprising a semiconductor substrate including a voltage controlled oscillator are disclosed. In one embodiment, the vco comprises an lc tank circuit for generating an oscillator output at an oscillator frequency, and an oscillator core including cross-coupled semiconductor devices to provide feedback to the tank circuit.
International Business Machines Corporation


07/16/15
20150200368 

Semiconductor integrated circuit device having phase-change structure and manufacturing the same


A semiconductor integrated circuit device including a phase-change structure and a method of manufacturing the same are provided. The method includes providing a semiconductor substrate including a lower electrode, sequentially stacking a plurality of phase-change material layers on the semiconductor substrate, and patterning the stacked plurality of phase-change material layers in a stepwise manner to form a phase-change structure..
Sk Hynix Inc.


07/16/15
20150200362 

Two terminal resistive switching device structure and fabricating


A semiconductor device having a memory device includes a semiconductor substrate, a first dielectric layer disposed above the semiconductor substrate, a first adhesion layer disposed upon the first dielectric layer, a bottom wiring metal disposed upon the first adhesion layer, a first barrier layer disposed upon the bottom wiring metal, a resistive switching material disposed in electrical contact with the first barrier layer, wherein the resistive switching material comprises a silicon material having a plurality of defect regions, a conductive metal material disposed upon the resistive switching material, wherein the conductive metal material comprises a plurality of conductive metal particles, a second barrier layer disposed upon the conductive metal material, a top wiring metal disposed upon the second barrier layer, and wherein at least some of the plurality of conductive metal particles are removably disposed in defect regions from the plurality of defect regions in the resistive switching material.. .
Crossbar, Inc.


07/16/15
20150200358 

Semiconductor integrated circuit device having variable resistive layer and manufacturing the same


A semiconductor integrated circuit device includes a semiconductor substrate, a lower electrode disposed on the semiconductor substrate wherein an upper surface of the lower electrode has a recess, an interlayer insulating layer disposed on the semiconductor substrate and the lower electrode, the interlayer insulating layer including a variable resistive region exposing the upper surface of the lower electrode, and a variable resistive layer filled in the variable resistive region that contacts the recess of the lower electrode. The variable resistive layer is formed to have an increased width toward a top and a bottom thereof..
Sk Hynix Inc.


07/16/15
20150200307 

Semiconductor storage device


A semiconductor storage device according to the present embodiment includes a semiconductor substrate. A tunnel insulating film is provided on the semiconductor substrate.
Kabushiki Kaisha Toshiba


07/16/15
20150200296 

Process design to improve transistor variations and performance


The present disclosure relates to a method of forming a transistor device having a carbon implantation region that provides for a low variation of voltage threshold, and an associated apparatus. The method is performed by forming a well region within a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/16/15
20150200280 

Semiconductor device and manufacturing semiconductor device


A semiconductor device includes a fin-shaped semiconductor layer disposed on a semiconductor substrate, a first insulating film disposed around the fin-shaped semiconductor layer, a first pillar-shaped semiconductor layer disposed on the fin-shaped semiconductor layer, a first gate insulating film that is disposed around the first pillar-shaped semiconductor layer and includes a charge storing layer, a second gate insulating film disposed around the first pillar-shaped semiconductor layer and at a position higher than the first gate insulating film, a fifth gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer, and a first contact electrode surrounding the fifth gate insulating film.. .
Unisantis Electronics Singapore Pte. Ltd.


07/16/15
20150200275 

Finfet and manufacturing the same


A finfet with reduced leakage between source and drain regions, and a method for manufacturing the finfet are disclosed. In one aspect, the method includes forming, on a semiconductor substrate, at least two openings to define a semiconductor fin.
Institute Of Microelectronics, Chinese Academy Of Sciences


07/16/15
20150200273 

Semiconductor device, printing apparatus, and manufacturing method thereof


A manufacturing method of a semiconductor device including a dmos transistor, an nmos transistor and a pmos transistor arranged on a semiconductor substrate, the dmos transistor including a first impurity region and a second impurity region formed to be adjacent to each other, the first impurity region being of the same conductivity type as a drain region and a source region of the dmos transistor, forming to enclose the drain region, and the second impurity region being of a conductivity type opposite to the first impurity region, forming to enclose the source region, the manufacturing method of the semiconductor device comprising forming the first impurity region and one of the nmos transistor and the pmos transistor, and forming the second impurity region and the other of the nmos transistor and the pmos transistor.. .
Canon Kabushiki Kaisha


07/16/15
20150200272 

Transistor having replacement gate and epitaxially grown replacement channel region


The disclosure provides a method of forming a transistor. In this method, a dummy gate structure is formed over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/16/15
20150200263 

Semiconductor device and manufacturing the same


A semiconductor device and a method for manufacturing the same are disclosed, which can form a gate electrode material only in a recess of a buried gate cell structure, improve a gate induced drain leakage (gidl) of a gate electrode material and a junction (i.e., drain region), prevent the gate electrode material from overlapping with the junction (i.e., drain region), and adjust the depth of junction, thereby improving channel resistance. The method for manufacturing a semiconductor device includes forming a device isolation region defining an active region over a semiconductor substrate, burying a gate electrode material in the semiconductor substrate, forming a gate electrode pattern by etching the gate electrode material, wherein the gate electrode pattern is formed at sidewalls of the active region including a source region, and forming a capping layer in the exposed active region..
Sk Hynix Inc.


07/16/15
20150200253 

Transistor design


Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/16/15
20150200250 

Trench mos device having a termination structure with multiple field-relaxation trenches for high voltage applications


A termination structure for a semiconductor device includes a semiconductor substrate having an active region and a termination region. Two or more trench cells are located in the termination region and extend from a boundary of the active region toward an edge of the semiconductor substrate.
Vishay General Semiconductor Llc


07/16/15
20150200226 

Image sensor and electronic device including the same


An image sensor includes a semiconductor substrate integrated with at least one first photo-sensing device configured to sense light in a blue wavelength region and at least one second photo-sensing device configured to sense light in a red wavelength region, a color filter layer on the semiconductor substrate and including a blue color filter configured to selectively absorb light in a blue wavelength region and a red color filter configured to selectively absorb light in a red wavelength region, and a third photo-sensing device on the color filter layer and including a pair of electrodes facing each other, and a photoactive layer between the pair of electrodes and configured to selectively absorb light in a green wavelength region.. .
Samsung Electronics Co., Ltd.


07/16/15
20150200224 

Unit pixel and image pixel array including the same


A unit pixel includes a sensing transistor, a photo diode, and a reset drain region. The sensing transistor includes a reference active region, an output active region, and a gate.
Samsung Electronics Co., Ltd.


07/16/15
20150200200 

Non-volatile semiconductor memory device


Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction. One stack structure has a plurality of semiconductor layers stacked between interlayer insulating layers.
Kabushiki Kaisha Toshiba


07/16/15
20150200194 

Method of manufacturing a semiconductor device


A method of manufacturing a semiconductor device is provided. The method includes forming a fin structure on a semiconductor substrate and forming a well region in the semiconductor substrate by ion implantation so as to form transistors.
Semiconductor Manufacturing International (shanghai) Corporation


07/16/15
20150200193 

Semiconductor device and manufacturing the same


A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.. .
Sony Corporation


07/16/15
20150200178 

Connection structure and electronic component


A connection structure is provided that includes a semiconductor substrate, a first layer arranged on the semiconductor substrate, the first layer being configured to provide shielding against radioactive rays, a second layer arranged on the first layer, the second layer including solder including pb, and an electrically conductive member arranged on the second layer.. .
Infineon Technologies Austria Ag


07/16/15
20150200158 

Method of manufacturing semiconductor device and semiconductor device


Characteristics of a semiconductor device are improved. An opening that exposes a pad region of a top-layer wiring containing aluminum is formed in a protection film over the wiring, and aluminum nitride is formed on a surface of the exposed wiring.
Renesas Electronics Corporation


07/16/15
20150200152 

Semiconductor device and fabricating the same


Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a gate structure formed in the interlayer insulating layer, an isolation layer formed in the semiconductor substrate, a through-silicon via formed to penetrate the semiconductor substrate, the interlayer insulating layer, and the isolation layer, and a first conduction type first impurity region coming in contact with the isolation layer and formed to surround only a portion of a sidewall of the through-silicon via in the semiconductor substrate..
Samsung Electronics Co., Ltd.


07/16/15
20150200144 

Chuck and semiconductor process using the same


A semiconductor process is described in this application. The process includes the following steps: providing a semiconductor substrate; measuring a warpage level of the semiconductor substrate; and holding the semiconductor substrate by providing at least one vacuum suction according to the warpage level, so that the semiconductor substrate is subjected to a plurality of varied suction intensities.
United Microelectronics Corporation


07/16/15
20150200142 

Methods for fabricating integrated circuits with fully silicided gate electrode structures


A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure.
Globalfoundries, Inc.


07/16/15
20150200140 

Methods for fabricating finfet integrated circuits using laser interference lithography techniques


A method for fabricating an integrated circuit includes providing a semiconductor substrate with a pad layer overlying the semiconductor substrate and a photoresist layer overlying the pad layer, exposing the photoresist layer to a split laser beam to form a plurality of parallel linear void regions in the photoresist layer, and etching the pad layer and the semiconductor substrate beneath the plurality of parallel linear void regions to form a plurality of extended parallel linear void regions. The method further includes depositing a first dielectric material over the semiconductor substrate, patterning a photoresist material over the semiconductor substrate to cover a portion of the semiconductor substrate, and etching portions of the pad layer, the first dielectric material, and the semiconductor substrate.
Globalfoundries, Inc.


07/16/15
20150200134 

Semiconductor device structure and forming


Embodiments of a semiconductor device structure and a method of forming a semiconductor device structure are provided. The semiconductor device structure includes an insulating layer having a top surface, a bottom surface and a side surface.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/16/15
20150200133 

Method for forming semiconductor device structure


Embodiments of the disclosure provide a method for forming a semiconductor device structure. The method includes forming a dielectric layer over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/16/15
20150200127 

Mechanisms for forming semiconductor device having isolation structure


Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate having an upper surface.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/16/15
20150200120 

Systems and transferring a semiconductor substrate


In accordance with some embodiments, systems and methods for processing a semiconductor substrate are provided. The method includes loading a semiconductor substrate from a chamber to a transfer module, detecting a center and a notch of the semiconductor substrate by the transfer module, and transferring the semiconductor substrate from the transfer module to a process chamber..
Taiwan Semiconductor Manufacturing Co., Ltd.


07/16/15
20150200111 

Planarization scheme for finfet gate height uniformity control


Embodiments of the present invention provide improved methods for fabrication of finfets. During finfet fabrication, a film, such as amorphous silicon, is deposited on a semiconductor substrate which has regions with fins and regions without fins.
Globalfoundries Inc.


07/16/15
20150200100 

N metal for finfet and methods of forming


An n work function metal for a gate stack of a field effect transistor (finfet) and method of forming the same are provided. An embodiment finfet includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a gate stack formed over the channel region of the fin, the gate stack including an n work function metal layer comprising an oxidation layer on opposing sides of a tantalum aluminide carbide (taalc) layer..
Taiwan Semiconductor Manufacturing Company, Ltd.


07/16/15
20150200094 

Carbon film stress relaxation


Methods are described for treating a carbon film on a semiconductor substrate. The carbon may have a high content of sp3 bonding to increase etch resistance and enable new applications as a hard mask.
Applied Materials, Inc.


07/16/15
20150200086 

Semiconductor manufacturing apparatus and manufacturing semiconductor device


A semiconductor manufacturing apparatus includes a chamber configured to house a semiconductor substrate therein. A vacuum part depressurizes inside of the chamber.
Kabushiki Kaisha Toshiba


07/16/15
20150200074 

Charged particle beam exposure apparatus


Provided is a charged particle beam exposure apparatus configured as follows. An electron beam emitted from an electron gun is deformed by an asymmetric illumination optical system to have an elongated section.
Advantest Corporation


07/09/15
20150194894 

Trench mosfet having an independent coupled element in a trench


A trench mosfet is disclosed that includes a semiconductor substrate having a vertically oriented trench containing a gate. The trench mosfet further includes a source, a drain, and a conductive element.
Renesas Electronics America Inc.


07/09/15
20150194547 

Systems and methods for monolithically isled solar photovoltaic cells


The method for forming a monolithically isled solar cell comprises forming a first metal layer having base and emitter metallization on a passivated backside of a semiconductor substrate. An insulating support backplane is attached to a surface of the first metal layer and at least a portion of the semiconductor substrate passivated backside.
Solexel, Inc.


07/09/15
20150194544 

Light sensors having dielectric optical coating filters


A light sensor includes a photodetector sensor region formed in a semiconductor substrate. To shape the spectral response of the light sensor, a dielectric optical coating filter covers the photodetector sensor region and a circumferential region of the substrate that surrounds the photodetector sensor region.
Intersil Americas Llc


07/09/15
20150194542 

Photoconductive antenna


A pca is provided including: a semiconductor substrate; a metallic antenna, formed on one surface of the semiconductor substrate; and a first pattern structure, formed on the same surface of the semiconductor substrate as the surface on which the metallic antenna is formed, to obstruct surface waves and/or back-scattered waves.. .
Samsung Electronics Co., Ltd.


07/09/15
20150194528 

Semiconductor device


A semiconductor device in one embodiment includes a semiconductor substrate, a fin disposed on a surface of the semiconductor substrate, an insulator including a gate insulator disposed on a side surface of the fin, and a gate electrode disposed on the insulator that is disposed on side surfaces of the fin and an upper surface of the fin. The device further includes a plurality of epitaxial stripe shaped layers disposed horizontally on the side surface of the fin at different heights, and an interlayer dielectric disposed on the semiconductor substrate to cover the fin and applying a stress to the fin and the epitaxial layers.
Kabushiki Kaisha Toshiba


07/09/15
20150194526 

Method for manufacturing semiconductor device with recess, epitaxial growth and diffuson


A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate..
Sony Corporation


07/09/15
20150194520 

Nonvolatile semiconductor memory element, nonvolatile semiconductor memory, and operating nonvolatile semiconductor memory element


According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.. .
Kabushiki Kaisha Toshiba


07/09/15
20150194510 

Self-aligned emitter-base-collector bipolar junction transistors with a single crystal raised extrinsic base


Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer.
International Business Machines Corporation


07/09/15
20150194500 

Method for manufacturing semiconductor devices using self-aligned process to increase device packing density


A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure; forming and patterning a composite dielectric layer, a second polysilicon layer, and a second capping layer to form an interconnect structure; forming a composite spacer; removing the photo-resist layer; forming a third polysilicon layer; making blanket removal of the third polysilicon layer to leave a remain third polysilicon layer; removing the first and the second capping layer; forming a source and a drain; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure.. .

07/09/15
20150194491 

Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate and in a semiconductor device


Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer.. .
Infineon Technologies Austria Ag


07/09/15
20150194484 

Fabricating shallow-trench isolation semiconductor devices to reduce or eliminate oxygen diffusion


A method is disclosed for forming a semiconductor device. A first opening is formed for an sti on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening.
International Business Machines Corporation


07/09/15
20150194465 

Pad structures formed in double openings in dielectric layers


An image sensor device includes a semiconductor substrate having a front side and a backside. A first dielectric layer is on the front side of the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/09/15
20150194462 

Method of manufacturing solid-state image sensor


A method of manufacturing a solid-state image sensor includes forming a resist film with a thickness of not less than 7 μm on a semiconductor substrate including an active region and an element isolation region, forming a resist pattern including an opening by performing a photolithography process on the resist film, and implanting ions into a pixel array region on the semiconductor substrate through the opening, wherein the opening of the resist pattern includes a corner portion, and the corner portion is positioned not above the element isolation region but above the active region.. .
Canon Kabushiki Kaisha


07/09/15
20150194457 

Solid-state imaging device, camera, and design solid-state imaging device


A solid-state imaging device including two semiconductor substrates arranged in layers is provided. Each semiconductor substrate has a semiconductor region in which a circuit constituting a part of a pixel array is formed.
Canon Kabushiki Kaisha


07/09/15
20150194452 

Photoelectric conversion apparatus and imaging system using the photoelectric conversion apparatus


In a photoelectric conversion apparatus including a charge holding portion, a part of an element isolation region contacting with a semiconductor region constituting the charge holding portion extends from a reference surface including the light receiving surface of a photoelectric conversion element into a semiconductor substrate at a level equal to or deeper than the depth of the semiconductor region in comparison with the semiconductor region.. .
Canon Kabushiki Kaisha


07/09/15
20150194432 

Butted contact shape to improve sram leakage current


The present disclosure relates to an sram memory cell. The sram memory cell has a semiconductor substrate with an active area and a gate region positioned above the active area.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/09/15
20150194431 

Static random access memory cell and forming method thereof


A sram cell and a forming method thereof are provided. The sram cell includes: a pull-up transistor, a pull-down transistor, a pass gate transistor, a tensile stress film which covers the pull-up transistor and the pull-down transistor, and an interlayer dielectric isolating layer which covers the tensile stress film and the pass gate transistor.
Shanghai Huahong Grace Semiconductor Manufacturing Corporation


07/09/15
20150194419 

Three-dimensional electrostatic discharge semiconductor device


Three-dimensional electrostatic discharge (esd) semiconductor devices are fabricated together with three-dimensional non-esd semiconductor devices. For example, an esd diode and finfet are fabricated on the same bulk semiconductor substrate.
Globalfoundries Inc.


07/09/15
20150194414 

Integrated circuit interposer and manufacturing the same


Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate.
Marvell Israel (m.i.s.l) Ltd.


07/09/15
20150194402 

Method of fabricating bump structure and bump structure


A method of forming a semiconductor device includes forming an under-bump metallurgy (ubm) layer overlying a portion of a metal pad region within an opening of an encapsulating layer over a semiconductor substrate, and forming a bump layer overlying the ubm layer to fill the opening of the encapsulating layer. A removal process is initiated on an upper surface of the encapsulating layer and a coplanar top surface of the bump layer to remove the upper surface of the encapsulating layer until a top portion of the bump layer protrudes from the encapsulating layer..
Taiwan Semiconductor Manufacturing Company, Ltd.


07/09/15
20150194393 

Protection of an integrated circuit against attacks


An integrated circuit, including: a semiconductor substrate of a first conductivity type; a plurality of regions of the first conductivity type vertically extending from the surface of the substrate, each of the regions being laterally delimited all along its periphery by a region of the second conductivity type; and a device for detecting a variation of the substrate resistance between each region of the first conductivity type and an area for biasing the substrate to a reference voltage.. .
Stmicroelectronics (rousset) Sas


07/09/15
20150194383 

Air gap forming techniques based on anodic alumina for interconnect structures


An aluminum (al) layer is formed over a semiconductor substrate. A selective portion of the al layer is removed to form openings.
Taiwan Semicondutor Manufacturing Co., Ltd.


07/09/15
20150194342 

Formation of carbon-rich contact liner material


Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material including a carbon-containing species and an elemental carbon disposed therein, the carbon-containing species and the elemental carbon together defining a set carbon content within the carbon-rich contact liner material; and depositing the carbon-rich contact liner material conformally within the at least one contact opening disposed over the semiconductor substrate..
Globalfoundries Inc.


07/09/15
20150194339 

Conductive layer routing


Methods of fabricating middle of line (mol) layers and devices including mol layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask across active contacts to terminals of semiconductor devices of a semiconductor substrate.
Qualcomm Incorporated


07/09/15
20150194334 

Fabricating shallow-trench isolation semiconductor devices to reduce or eliminate oxygen diffusion


A method is disclosed for forming a semiconductor device. A first opening is formed for an sti on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening.
International Business Machines Corporation


07/09/15
20150194319 

Flat sic semiconductor substrate


Methods for manufacturing silicon carbide wafers having superior specifications for bow, warp, total thickness variation (ttv), local thickness variation (ltv), and site front side least squares focal plane range (sfqr). The resulting sic wafer has a mirror-like surface that is fit for epitaxial deposition of sic.
Dow Corning Corporation


07/09/15
20150194312 

Method of manufacturing semiconductor device using organic underlayer film forming composition for solvent development lithography process


A method of manufacturing a semiconductor device by use of an underlayer film material can form a good pattern without deteriorating the resolution limit. A method of manufacturing a semiconductor device, including: forming an organic underlayer film on a semiconductor substrate; forming an inorganic hard mask on organic underlayer film; forming a resist film on inorganic hard mask; performing irradiation of light or electron beam and solvent development to form a resist pattern; etching inorganic hard mask using resist pattern; etching organic underlayer film using patterned inorganic hard mask; and processing semiconductor substrate using patterned organic underlayer film, wherein the organic underlayer film is an organic underlayer film obtained by applying and heating an organic underlayer film forming composition containing a compound including an organic group having a functional group selected from group consisting of epoxy group, isocyanate group, blocked isocyanate group, and benzocyclobutene ring group, and an organic solvent..
Nissan Chemical Industries, Ltd.




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Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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