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Semiconductor Substrate patents



      

This page is updated frequently with new Semiconductor Substrate-related patent applications.




Date/App# patent app List of recent Semiconductor Substrate-related patents
12/31/15
20150381122 
 Monolithic transistor circuits with tapered feedback resistors, rf amplifier devices, and methods of manufacture thereof patent thumbnailMonolithic transistor circuits with tapered feedback resistors, rf amplifier devices, and methods of manufacture thereof
Embodiments of an integrated resistor may be incorporated into monolithic transistor circuits and packaged rf amplifier devices. An embodiment of an integrated resistor includes a semiconductor substrate and a resistor formed over the top surface of the semiconductor substrate from resistive material.

12/31/15
20150381121 
 Integrated passive device assemblies for rf amplifiers, and methods of manufacture thereof patent thumbnailIntegrated passive device assemblies for rf amplifiers, and methods of manufacture thereof
An embodiment of an integrated passive device (ipd) assembly includes a first capacitor formed over a semiconductor substrate, where the first capacitor includes a first capacitor electrode, a second capacitor electrode, and dielectric material that electrically insulates the first capacitor electrode from the second capacitor electrode. The ipd assembly also includes a first contact pad exposed at a top surface of the ipd assembly and electrically coupled to the second capacitor electrode, and a second contact pad exposed at the top surface of the ipd.

12/31/15
20150380925 
 Overvoltage protection component patent thumbnailOvervoltage protection component
An integrated circuit includes a vertical shockley diode and a first vertical transistor. The diode is formed by, from top to bottom of a semiconductor substrate, a first region of a first conductivity type, a substrate of a second conductivity type, and a second region of the first conductivity type having a third region of the second conductivity type formed therein.
Stmicroelectronics (tours) Sas


12/31/15
20150380901 
 Method and apparatus including improved vertical-cavity surface-emitting lasers patent thumbnailMethod and apparatus including improved vertical-cavity surface-emitting lasers
Vcsels and methods having improved characteristics. In some embodiments, these include a semiconductor substrate; a vertical-cavity surface-emitting laser (vcsel) on the substrate; a first electrical contact formed on the vcsel; a second electrical contact formed on the substrate, wherein the vcsel includes: a first resonating cavity having first and second mirrors, at least one of which partially transmits light incident on that mirror, wherein the first second mirrors are electrically conductive.
Vixar Inc.


12/31/15
20150380580 
 Backside-illuminated energy ray detection element patent thumbnailBackside-illuminated energy ray detection element
A back-illuminated energy ray detecting element 1 includes a semiconductor substrate and a protective film. The semiconductor substrate has a first principal surface as an energy ray incident surface and a second principal surface opposite to the first principal surface, and a charge generating region configured to generate an electric charge according to incidence of an energy ray is disposed on the second principal surface side.
Hamamatsu Photonics K.k.


12/31/15
20150380575 
 Back contact solar cell and fabrication method thereof patent thumbnailBack contact solar cell and fabrication method thereof
The present invention discloses a back contact solar cell. The back contact solar cell includes a semiconductor substrate having a front surface and a rear surface; and a first conductive type semiconductor region having a first conductive type and a second conductive type semiconductor region having a second conductive type, the first conductive type semiconductor region and the second conductive type semiconductor region being disposed with an interval on the rear surface of the semiconductor substrate.
Lg Electronics Inc.


12/31/15
20150380571 
 Solar cell module patent thumbnailSolar cell module
A solar cell module is disclosed. The solar cell module includes a plurality of solar cells each including a semiconductor substrate, in which a p-n junction is formed, and a plurality of first and second electrodes which are formed on a back surface of the semiconductor substrate and are separated from each other, a plurality of interconnectors which are connected to the first electrodes or the second electrodes included in each solar cell and connect the plurality of solar cells in series, and a conductive adhesive attaching the interconnectors to the first electrodes or the second electrodes.
Lg Electronics Inc.


12/31/15
20150380568 
 Split gate flash memory structure with a damage free select gate and a  making the split gate flash memory structure patent thumbnailSplit gate flash memory structure with a damage free select gate and a making the split gate flash memory structure
A method of manufacturing a semiconductor structure of a pair of split gate flash memory cells is provided. A pair of select gates spaced on a semiconductor substrate is formed, and a sacrificial spacer filling a central region between the select gates is formed.
Taiwan Semiconductor Manufacturing Co., Ltd.


12/31/15
20150380559 
 Germanium-containing finfet and methods for forming the same patent thumbnailGermanium-containing finfet and methods for forming the same
A method includes forming isolation regions in a semiconductor substrate, forming a first semiconductor strip between opposite portions of isolation regions, forming a second semiconductor strip overlying and contacting the first semiconductor strip, and performing a first recessing to recess the isolation regions. A portion of the second semiconductor strip over top surfaces of remaining portions of the isolation regions forms a semiconductor fin.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/31/15
20150380548 
 Vertical device architecture patent thumbnailVertical device architecture
The present disclosure relates to a vertical transistor device having rectangular vertical channel bars extending between a source region and a drain region, and an associated method of formation. In some embodiments, the vertical transistor device has a source region disposed over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


12/31/15
20150380538 

Trench gate mos semiconductor device and manufacturing the same


A p-type base region, in which an n+ emitter region is formed, and a p-type floating region are provided in a surface layer of one main surface of an n-type semiconductor substrate and are separated from each other by a trench. An emitter electrode is provided so as to cover the p-type floating region, with an interlayer insulating film interposed there between, and to come into contact with the p-type base region and the n+ emitter region.
Fuji Electric Co., Ltd.


12/31/15
20150380537 

Semiconductor device


A semiconductor device in which a first region of a first conductivity type, a second region of a second conductivity type, and a third region of the first conductivity type are laminated in this order from a front surface side of a semiconductor substrate, a trench gate electrode extending to the third region through the first region and the second region is formed, a front surface electrode is formed on the front surface, and an insulating region covering a top surface of the trench gate electrode insulates the front surface electrode and the trench gate electrode is known. The insulating region is formed to stay within a trench.
Toyota Jidosha Kabushiki Kaisha


12/31/15
20150380536 

Semiconductor device


A semiconductor device in which an element region including at least an igbt region is formed on a semiconductor substrate is presented. The igbt region including: a collector layer; a drift layer; a body layer; a gate electrode placed inside a trench extending from the front surface of the semiconductor substrate to the drift layer; an emitter layer; and a contact layer having a higher impurity concentration than the body layer.
Toyota Jidosha Kabushiki Kaisha


12/31/15
20150380533 

Insulated gate bipolar transistor device, semiconductor device and forming said devices


An insulated gate bipolar transistor device includes a semiconductor substrate having a drift region of an insulated gate bipolar transistor structure. Further, the insulated gate bipolar transistor device includes a first nanowire structure and a first gate structure.
Infineon Technologies Ag


12/31/15
20150380522 

Methods of forming low noise semiconductor devices


Disclosed herein are lateral diffused metal oxide semiconductor (ldmos) device and trench isolation related devices, methods, and techniques. In one illustration, a doped region is formed within a semiconductor substrate.
Infineon Technologies Ag


12/31/15
20150380516 

Doped protection layer for contact formation


A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with a gate stack formed on the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


12/31/15
20150380513 

Bipolar transistor device fabrication methods


A method of fabricating a bipolar transistor device includes performing a first plurality of implantation procedures to implant dopant of a first conductivity type to form emitter and collector regions laterally spaced from one another in a semiconductor substrate, and performing a second plurality of implantation procedures to implant dopant of a second conductivity type in the semiconductor substrate to form a composite base region. The composite base region includes a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region.
Freescale Semiconductor, Inc.


12/31/15
20150380509 

Improved formation of silicide contacts in semiconductor devices


Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nfet) region and on a p-type field effect transistor (pfet) region; performing a pre-amorphized implantation (pai) process to an n-type doped silicon (si) feature in on the nfet region and a p-type doped silicon germanium (sige) feature in the pfet region, thereby forming an n-type amorphous silicon (a-si) feature and a p-type amorphous silicon germanium (a-sige) feature; depositing a metal layer over each of the a-si and a-sige features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-si and the p-type a-sige features.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/31/15
20150380508 

Semiconductor device


A semiconductor device includes a semiconductor substrate including a plurality of active areas, a bit line crossing the plurality of active areas, a direct contact connecting a first active area of the plurality of active areas with the bit line, an insulating spacer covering a side wall of the bit line and extending at a level lower than a level of an upper surface of the semiconductor substrate, a contact pad connected with a side wall of a second active area of the plurality of active areas, which neighbors the first active area, a first insulating pattern defining a contact hole exposing the insulating spacer and the contact pad, and a buried contact connected with the contact pad and filling the contact hole.. .
Samsung Electronics Co., Ltd.


12/31/15
20150380494 

Semiconductor device


A semiconductor device capable of reducing on-resistance changes with temperature, including a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a first well region of a second conductivity type formed in the front surface of the drift layer, a second well region of the second conductivity type formed in the front surface of the drift layer, and a gate structure that is formed on the front surface of the drift layer and forms a channel in the first well region and a channel in the second well region. A channel resistance of the channel formed in the first well region has a temperature characteristic that the channel resistance decreases with increasing temperature and a channel resistance of the channel formed in the second well region has a temperature characteristic that the channel resistance increases with increasing temperature..
Mitsubishi Electric Corporation


12/31/15
20150380487 

Semiconductor device


Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit ldmosfet elements.
Renesas Electronics Corporation


12/31/15
20150380478 

Semiconductor device with metal extrusion formation


Embodiments disclose a method of fabrication and a semiconductor structure comprising a metal-insulator-metal (mim) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate.
International Business Machines Corporation


12/31/15
20150380463 

Semiconductor device and manufacturing same


A semiconductor device including a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening.. .
Sony Corporation


12/31/15
20150380457 

Detector, pet system and x-ray ct system


Each semiconductor chip of a detector comprises a semiconductor substrate having a plurality of photodetector units, an insulating layer formed on a front face of the semiconductor substrate, a common electrode arranged on the insulating layer, a readout line for electrically connecting a quenching resistance of each photodetector unit and the common electrode to each other, and a through electrode extending from the common electrode to a rear face of the semiconductor substrate through a through hole of the semiconductor substrate.. .
Hamamatsu Photonics K.k.


12/31/15
20150380456 

Solid-state imaging device, manufacturing solid-state imaging device, and imaging apparatus


A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of amos transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of amos transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion.. .
Sony Corporation


12/31/15
20150380454 

Camera module and manufacturing the same


Embodiments of the present invention provide a camera module and a method of manufacturing the same, the camera module comprising a sensor assembly, at least one semiconductor substrate, and a molding compound; wherein the sensor assembly comprises a semiconductor die, a sensor circuit disposed on the top surface of the semiconductor die, and a transparent cover coupled to the semiconductor die over the top surface of the semiconductor die; wherein each semiconductor substrate is disposed around the sensor assembly in a horizontal direction; and wherein the molding compound is filled between each semiconductor substrate and the sensor assembly.. .
Stmicroelectronics (shenzhen) R&d Co. Ltd


12/31/15
20150380447 

Deep trench isolation shrinkage enhanced device performance


Some embodiments of the present disclosure relate to a deep trench isolation (dti) structure configured to enhance efficiency and performance of a photovoltaic device. The photovoltaic device comprises a functional layer disposed over an upper surface of a semiconductor substrate, and a pair of pixels formed within the semiconductor substrate, which are separated by the dti structure.
Taiwan Semiconductor Manufacturing Co., Ltd.


12/31/15
20150380421 

Semiconductor memory devices and methods of fabricating the same


Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench..
Samsung Electronics Co., Ltd.


12/31/15
20150380416 

Semiconductor device


Disclosed embodiments relate to a semiconductor device having a plurality of unit transistors that include element isolation regions formed on a semiconductor substrate and a gate electrode formed in the shape of a frame and disposed on an active region sandwiched between the element isolation regions in such a way that the two ends of the outer periphery of the gate electrode extend onto the element isolation regions and the inner periphery thereof closes the active region. The active regions of unit transistors adjacent to one another in a first direction are electrically isolated from one another by means of the element isolation regions, and the active regions of unit transistors adjacent to one another in a second direction which intersects the first direction are linked to one another..
Ps4 Luxco S.a.r.l.


12/31/15
20150380415 

Semiconductor device and fabricating the same


A semiconductor device includes a bit line disposed over a semiconductor substrate, a supporting film being perpendicular to the bit line, a first storage node contact disposed at a lower part of a region disposed between the bit line and the supporting film, and a second storage node contact having a line shape, disposed over the first storage node contact and the bit line, isolated by the supporting film, and patterned in a diagonal direction across the bit line.. .
Sk Hynix Inc.


12/31/15
20150380412 

Fin-last finfet and methods of forming same


Embodiments of the present disclosure are a finfet device, and methods of forming a finfet device. An embodiment is a method for forming a finfet device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/31/15
20150380411 

Semiconductor structure and manufacturing the same


The present invention provides a semiconductor structure, which comprises a semiconductor substrate and at least two semiconductor fins located on the semiconductor substrate, wherein: the at least two semiconductor fins are parallel to each other; and the parallel sidewall surfaces of the at least two semiconductor fins have different crystal planes. The present invention further provides a method for manufacturing aforesaid semiconductor structure.

12/31/15
20150380404 

Non-planar structure with extended exposed raised structures and same-level gate and spacers


A starting non-planar semiconductor structure is provided having a semiconductor substrate, raised semiconductor structures coupled to the substrate, and a layer of isolation material(s) surrounding the raised structures. The isolation layer is recessed to expose about 40 nm to about 70 nm of the raised structures.
Globalfoundries Inc.


12/31/15
20150380401 

Semiconductor device


A semiconductor device includes a first element portion including an igbt and a second element portion including a circuit that controls the igbt on the same semiconductor substrate. The novel structure reduces the size of the entire circuit and includes a drift region on a front surface of the substrate; a region in a surface layer of the drift region which is opposite to the substrate; an insulator layer that passes through the region in a depth direction and reaches the drift region, the insulator layer provided at a boundary between the first and second element portions, and separating the region into a first region in the first element portion and having the emitter potential of the igbt and a second region in the second element portion; and a first contact electrode that contacts the second region, and that is electrically connected to an emitter electrode of the igbt..
Fuji Electric Co., Ltd.


12/31/15
20150380388 

Fan-out package structure and methods for forming the same


A package includes a device die including a first plurality of metal pillars at a top surface of the device die. The package further includes a die stack including a plurality of dies bonded together, and a second plurality of metal pillars at a top surface of the die stack.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/31/15
20150380341 

Three-dimensional semiconductor device


A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/31/15
20150380317 

Semiconductor device and driver circuit with drain and isolation structure interconnected through a diode circuit, and manufacture thereof


Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type.
Freescale Semiconductor, Inc.


12/31/15
20150380297 

Method for manufacturing mosfet


Provided is a method for manufacturing a mosfet, comprising: epitaxially growing a first semiconductor layer on a semiconductor substrate; epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a shallow trench isolation in the first semiconductor layer and the second semiconductor layer to define an active region for the mosfet; forming on the second semiconductor layer a gate stack and a spacer surrounding the gate stack; forming openings in the second semiconductor layer using the shallow trench isolation, the gate stack and the spacer as a hard mask; epitaxially growing, in each of the openings, a third semiconductor layer using a bottom surface and sidewalls of the opening as a growth seed layer, wherein the third semiconductor layer comprises a material different from that of the second semiconductor layer; and performing ion implantation into the third semiconductor layer to form source and drain regions.. .
The Institute Of Microelectronics, Chinese Academy Of Sciences


12/31/15
20150380290 

Composite substrate, semiconductor device, and manufacturing semiconductor device


A composite substrate 10 includes a semiconductor substrate 12 and an insulating support substrate 14 that are laminated together. The support substrate 14 includes first and second substrates 14a and 14b made of the same material and bonded together with a strength that allows the first and second substrates 14a and 14b to be separated from each other with a blade.
Ngk Insulators, Ltd.


12/31/15
20150380281 

Ceramic showerhead including central gas injector for tunable convective-diffusive gas flow in semiconductor substrate processing apparatus


An inductively coupled plasma processing apparatus comprises a vacuum chamber, a vacuum source, and a substrate support on which a semiconductor substrate is supported. A ceramic showerhead forms an upper wall of the vacuum chamber.
Lam Research Corporation


12/31/15
20150380275 

Method of manufacturing semiconductor package


A method of forming a semiconductor package includes forming a passivation layer over a semiconductor substrate. The semiconductor substrate includes a first chip region, a second chip region and a scribe line region.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/31/15
20150380116 

Shielding device for substrate edge protection and using same


A shielding device for shielding an edge of a semiconductor substrate can include a multisided frame defining a perimeter of an enclosed area, and a shield coupled to the frame. The shield may be configured to move between a first position where the shield is retracted to the perimeter and a second position where shield advanced into the enclosed area.
Varian Semiconductor Equipment Associates, Inc.


12/31/15
20150378064 

Piezoelectric optical mems device with embedded moisture layers


A piezoelectric optical micro-electro-mechanical systems (pomems) device includes a glass layer having a bottom surface and a top surface. The device may also include an upper moisture barrier layer having a top surface and a bottom surface in which the bottom surface of the top moisture barrier layer is substantially coextensive with and interfaces with the top surface of the glass layer.
Texas Instruments Incorporated


12/31/15
20150377954 

Method for testing semiconductor dies and a test apparatus


A method includes: providing a test apparatus; providing an electrically conductive carrier; providing a semiconductor substrate having a first main face, a second main face opposite to the first main face, and a plurality of semiconductor dies, the semiconductor dies including a first contact element on the first main face and a second contact element on the second main face; placing the semiconductor substrate on the carrier with the second main face facing the carrier; electrically connecting the carrier to a contact location disposed on the first main face; and testing a semiconductor die by electrically connecting the test apparatus with the first contact element of the semiconductor die and the contact location.. .
Infineon Technologies Ag


12/31/15
20150377813 

Semiconductor gas sensor device and manufacturing method thereof


A semiconductor gas sensor device includes a first cavity that is enclosed by opposing first and second semiconductor substrate slices. At least one conducting filament is provided to extend over the first cavity, and a passageway is provided to permit gas to enter the first cavity.
Stmicroelectronics S.r.l.


12/31/15
20150377696 

Integrated optoelectronic modules


A beam generating device includes a semiconductor substrate, having an optical passband. A first array of vertical-cavity surface-emitting lasers (vcsels) is formed on a first face of the semiconductor substrate and are configured to emit respective laser beams through the substrate at a wavelength within the passband.
Apple Inc.


12/31/15
20150376768 

Systems and methods for implementing digital vapor phase patterning using variable data digital lithographic printing techniques


A system and method are provided for implementing a unique scheme by which to execute digital vapor phase patterning on metals, semiconductor substrates and other surfaces using a proposed variable data digital lithographic image forming architecture or technique. For certain substrate printing and manufacturing applications, including some printed electronics applications, the disclosed schemes implement techniques to digitally pattern metal layers with bulk material properties in a manner that is aligned with underlying layers on the fly.
Palo Alto Research Center Incorporated


12/31/15
20150376463 

Copper barrier chemical-mechanical polishing composition


A chemical-mechanical polishing composition includes colloidal silica abrasive particles having a chemical compound incorporated therein. The chemical compound may include a nitrogen-containing compound such as an aminosilane or a phosphorus-containing compound.
Cabot Microelectronics Corporation


12/31/15
20150376462 

Tungsten chemical-mechanical polishing composition


A chemical-mechanical polishing composition includes colloidal silica abrasive particles having a chemical compound incorporated therein. The chemical compound may include a nitrogen-containing compound such as an aminosilane or a phosphorus-containing compound.
Cabot Microelectronics Corporation


12/24/15
20150372231 

Methods to fabricate non-metal films on semiconductor substrates using physical vapor deposition


Embodiments of the invention relate generally to semiconductor device fabrication and processes, and more particularly, to methods for implementing arrangements of magnetic field generators configured to facilitate physical vapor deposition (“pvd”) and/or for controlling impedance matching associated with a non-metal-based plasma used to modify a non-metal film, such as a chalcogenide-based film.. .
Semicat, Inc.


12/24/15
20150372230 

Method of forming a memory and forming a memory array


A method of forming a memory includes forming a first electrode and a second electrode within a first layer over a semiconductor substrate, forming a resistive-switching memory element and an antifuse element over the first layer, wherein the resistive-switching memory element includes a metal oxide layer and is electrically contacting the first electrode, wherein the metal oxide layer has a first thickness and a forming voltage that corresponds to the first thickness, wherein the antifuse element includes a dielectric layer and is electrically contacting the second electrode, and wherein the dielectric layer has a second thickness that is less than the first thickness and a dielectric breakdown voltage that is less than the forming voltage, and forming a third electrode and a fourth electrode within a second layer over the resistive-switching memory element and the antifuse element, wherein the third electrode is electrically contacting the resistive-switching memory element and the fourth electrode is electrically contacting the antifuse element.. .
Infineon Technologies Ag


12/24/15
20150372216 

Thermodiode element for a photosensor for infrared radiation measurement, photosensor and producing a thermodiode element


A thermodiode element for a photosensor of a thermocamera usable for infrared radiation measurement includes a semiconductor substrate that has a first layer, and a second layer adjoining the first layer. The first layer has a base doping zone, and the second layer has a side doping zone that is the same doping type as the base doping zone.
Robert Bosch Gmbh


12/24/15
20150372183 

Solar cell and manufacturing method thereof


A solar cell is formed to have a silicon semiconductor substrate of a first conductive type; an emitter layer having a second conductive type opposite the first conductive type and formed on a first surface of the silicon semiconductor substrate; a back surface field layer having the first conductive type and formed on a second surface of the silicon semiconductor substrate opposite to the first surface; and wherein the emitter layer includes at least a first shallow doping area and the back surface field layer includes at least a second shallow doping area, and wherein a thickness of the first shallow doping area of the emitter layer is different from a thickness of the second shallow doping area of the back surface field layer.. .
Lg Electronics Inc.


12/24/15
20150372177 

Solar cell module


A solar cell module includes a plurality of solar cells each including a semiconductor substrate, and first electrodes and second electrodes formed on the semiconductor substrate, a plurality of lines connected to the first and second electrodes of first and second solar cells, which are positioned adjacent to each other among the plurality of solar cells, the plurality of lines using a conductive adhesive or insulated from the first and second electrodes of the first and second solar cells through an insulating layer, and a connector positioned between the first and second solar cells and connected to the plurality of lines. A width of the connector is equal to or greater than at least one of a first distance between the first solar cell and the connector or a second distance between the second solar cell and the connector..
Lg Electronics Inc.


12/24/15
20150372144 

Integrated circuit structure and method with solid phase diffusion


The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate; a channel region of a first type conductivity, defined in the fin active region and having a first carrier concentration; and an anti-punch through (apt) feature of the first type conductivity, wherein the apt feature is formed in the semiconductor substrate, is directly underlying the channel region, and has a second carrier concentration greater than the first carrier concentration..
Taiwan Semiconductor Manufacturing Company, Ltd.


12/24/15
20150372139 

Constraining epitaxial growth on fins of a finfet device


A method includes forming at least one fin in a semiconductor substrate, forming a fin spacer on at least a first portion of the fin, the fin spacer having an upper surface, recessing the at least one fin to thereby define a recessed fin with a recessed upper surface that it is at a level below the upper surface of the fin spacer, and forming a first epitaxial material on the recessed fin, wherein a lateral extension of the epitaxial material is constrained by the fin spacer.. .
Globalfounders Inc.


12/24/15
20150372136 

Pattern layout to prevent split gate flash memory cell failure


A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region.
Taiwan Semiconductor Manufacturing Co., Ltd.


12/24/15
20150372135 

Semiconductor device having vertical channel, resistive memory device including the same, and manufacturing the same


A semiconductor device includes a semiconductor substrate having a first conductivity type, a plurality of pillars extending to a direction perpendicular to a surface of the semiconductor substrate, a stress providing layer formed in the semiconductor substrate between pillars and forming a junction with the semiconductor substrate below each pillar to cause lattice deformation in the pillar, a source region having a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate below the pillar, a drain region having the second conductivity type formed in an upper portion of the pillar, a gate insulating layer formed on a lateral surface of the pillar and a surface of the stress providing layer, and a gate electrode formed to surround the lateral surface of the pillar.. .
Sk Hynix Inc.


12/24/15
20150372131 

Charged balanced devices with shielded gate trench


This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench mosfet cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches.

12/24/15
20150372129 

High voltage field balance metal oxide field effect transistor (fbm)


A semiconductor device includes a semiconductor substrate of a first conductivity type. A first conductivity type epitaxial layer disposed on a top surface of the substrate includes a surface shielded region above a less heavily doped voltage blocking region.
Alpha And Omega Semiconductor Incorporated


12/24/15
20150372125 

Compound semiconductor device and manufacturing the same


A compound semiconductor device includes: a semiconductor substrate; a channel layer over the semiconductor substrate; a carrier supply layer over the channel layer; and a gate electrode, a source electrode and a drain electrode above the carrier supply layer. The semiconductor substrate includes an impurity-containing region containing an impurity, the impurity forms a level lower than a lower edge of a conduction band of silicon by 0.25 ev or more, the impurity forms the level higher than an upper edge of a valence band of silicon..
Fujitsu Limited


12/24/15
20150372121 

Asymmetric formation approach for a floating gate of a split gate flash memory structure


A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate having a source region and a drain region.
Taiwan Semiconductor Manufacturing Co., Ltd.


12/24/15
20150372111 

Methods of forming nanowire devices with spacers and the resulting devices


A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces.
Globalfoundries Inc.


12/24/15
20150372100 

Integrated circuits having improved contacts and methods for fabricating same


Integrated circuits having improved contacts and improved methods for fabricating integrated circuits having contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a source/drain region.
Globalfoundries, Inc.


12/24/15
20150372087 

Semiconductor switching devices with different local transconductance


A semiconductor device includes a semiconductor substrate having an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim. Each of the switchable cells includes a body region, a gate electrode structure and a source region.
Infineon Technologies Austria Ag


12/24/15
20150372086 

Semiconductor switching device with different local threshold voltage


A semiconductor device includes a semiconductor substrate having a plurality of switchable cells defining an active area of the semiconductor device, an outer rim, and an edge termination region arranged between the switchable cells and the outer rim. Each of the switchable cells includes a body region, a gate electrode structure and a source region.
Infineon Technologies Austria Ag


12/24/15
20150372080 

Self-aligned dual-height isolation for bulk finfet


A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate.
Renesas Electronics Corporation


12/24/15
20150372079 

Non-volatile semiconductor memory device and manufacturing non-volatile semiconductor memory device


According to an embodiment, a non-volatile semiconductor memory device includes plural gate electrodes in which a first insulating film, a charge storage layer, a second insulating film, and a control gate electrode layer are sequentially stacked on a semiconductor substrate, in which the control gate electrode layer includes a polysilicon layer that is formed on the second insulating film and a metal layer that is formed on the polysilicon layer, and a portion of the metal layer having the maximum width dimension is positioned above a lower end portion of the metal layer.. .
Kabushiki Kaisha Toshiba


12/24/15
20150372076 

Semiconductor switching device with different local cell geometry


A semiconductor device includes a semiconductor substrate having an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim. Each of the switchable cells includes a body region, a gate electrode structure and a source region.
Infineon Technologies Austria Ag


12/24/15
20150372074 

Semiconductor device and manufacturing semiconductor device


A method for manufacturing a semiconductor device includes a capacitor element in which a capacitance dielectric film is provided between an upper electrode film and a lower electrode film, includes forming the lower electrode film over the semiconductor substrate, forming the capacitance dielectric film over the lower electrode film, and forming the upper electrode film over the capacitance dielectric film, wherein, an entire surface layer of the lower electrode film is formed of a polycrystalline titanium nitride. At the portion of the capacitance dielectric film where directly contacting the entire surface layer of the lower electrode is formed of a polycrystalline metal oxide, and the polycrystalline metal oxide is formed by an ald method and inherits a crystallinity of the polycrystalline titanium nitride..
Renesas Electronics Corporation


12/24/15
20150372058 

Method for fabricating semiconductor apparatus


A method for fabricating a semiconductor apparatus includes forming a diffusion barrier film on a semiconductor substrate, forming a first film on a semiconductor substrate including a common source region, forming a second film on the first film, forming a conductive film on the second film, patterning the conductive film and the second film, to form an active pattern, and patterning the first film and the semiconductor substrate using the active pattern as a mask, to form a pillar; and forming a gate electrode on an outer circumference of the pillar.. .
Sk Hynix Inc.


12/24/15
20150372057 

Three dimensional semiconductor device having lateral channel


A 3d semiconductor device and a method of manufacturing the same are provided. The 3d semiconductor device includes a semiconductor substrate, an active line formed on the insulating layer, including a source region, a drain region and a channel region positioned between the source region and the drain region, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes.
Sk Hynix Inc.


12/24/15
20150372049 

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device includes forming a first film on a semiconductor substrate. The semiconductor substrate includes metal impurities, which may cause defects in the semiconductor device.
Kabushiki Kaisha Toshiba


12/24/15
20150372045 

Backside illumination image sensor chips and methods for forming the same


A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/24/15
20150372038 

Image sensor and image processing system including the same


An image sensor capable of boosting a voltage of a floating diffusion node is provided. The image sensor includes a floating diffusion node and a storage element which are in a semiconductor substrate.

12/24/15
20150372037 

Solid-state image sensor and its manufacturing method, curable composition for forming infrared cut-off filters, and camera module


A solid-state image sensor includes a semiconductor substrate, photoelectric conversion elements arranged on a light receiving surface side of the semiconductor substrate and making up pixels, and a filter layer disposed on a light incidence side of the photoelectric conversion elements so as to correspond to the photoelectric conversion elements. The filter layer includes at least red color filters, green color filters, blue color filters and infrared cut-off filters.
Fujifilm Corporation


12/24/15
20150372036 

Image sensor and image processing system including the same


An image sensor is provided. The image sensor includes a first photoelectric conversion element and a second photoelectric conversion element, which are formed in a semiconductor substrate; a red color filter formed on the first photoelectric conversion element; a cyan color filter formed on the second photoelectric conversion element; and an organic photoelectric conversion layer formed on the red color filter and the cyan color filter, the organic photoelectric conversion layer configured to absorb wavelengths in a green range..
Samsung Electronics Co., Ltd.


12/24/15
20150372034 

High dielectric constant structure for the vertical transfer gates of a complementary metal-oxide semiconductor (cmos) image sensor


A vertical-gate transfer transistor of an active pixel sensor (aps) is provided. The transistor includes a semiconductor substrate, a vertical trench extending into the semiconductor substrate, a dielectric lining the vertical trench, and a vertical gate filling the lined vertical trench.
Taiwan Semiconductor Manufacturing Co., Ltd.


12/24/15
20150372032 

Solid-state imaging device with channel stop region with multiple impurity regions in depth direction and manufacturing the same


Channel stop sections formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a p-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented.
Sony Corporation




Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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