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Semiconductor Substrate patents

      

This page is updated frequently with new Semiconductor Substrate-related patent applications.




 Package and methods for the fabrication and testing thereof patent thumbnailPackage and methods for the fabrication and testing thereof
Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure.
Nuvotronics, Inc.


 Solar cell and solar cell module patent thumbnailSolar cell and solar cell module
A solar cell and a solar cell module are disclosed. The solar cell includes a semiconductor substrate containing a crystalline silicon material, a first conductive region on a back surface of the semiconductor substrate, a second conductive region positioned in a portion except the first conductive region from the back surface of the semiconductor substrate and having a conductive type opposite the first conductive region, a first electrode connected to the first conductive region, and a second electrode connected to the second conductive region.
Lg Electronics Inc.


 Photoelectric conversion device patent thumbnailPhotoelectric conversion device
Provided is a photoelectric conversion device with an excellent conversion efficiency in which a series resistance between a semiconductor substrate and an electrode is reduced. The photoelectric conversion device includes a semiconductor substrate; a first conductivity region formed on the semiconductor substrate; and an electrode electrically connected to the first conductivity region, in which the first conductivity region includes an electrode region which faces the electrode, and crystal defects in the semiconductor substrate which faces the electrode region..
Sharp Kabushiki Kaisha


 Method for producing semiconductor device and semiconductor device patent thumbnailMethod for producing semiconductor device and semiconductor device
A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate; a third step of forming a second dummy gate on side walls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a fifth insulating film and a sixth insulating film around the second dummy gate; a fifth step of depositing a first interlayer insulating film, removing the second dummy gate and the first dummy gate, forming a gate insulating film around the pillar-shaped semiconductor layer, depositing metal, and performing etch back to form a gate electrode and a gate line; and a sixth step of forming a first diffusion layer in an upper portion of the pillar-shaped semiconductor layer.. .
Unisantis Electronics Singapore Pte. Ltd.


 Method for producing semiconductor device and semiconductor device patent thumbnailMethod for producing semiconductor device and semiconductor device
A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate, and forming a first insulating film; a second step of forming a second insulating film, and forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; a third step of forming a second hard mask on a side wall of the first hard mask, and etching a second polysilicon so as to be left on side walls of the first dummy gate and the pillar-shaped semiconductor layer to form a second dummy gate; and a fourth step of forming a fifth insulating film around the second dummy gate, etching the fifth insulating film so as to have a sidewall shape to form a sidewall formed of the fifth insulating film, and forming a first epitaxially grown layer on the fin-shaped semiconductor layer.. .
Unisantis Electronics Singapore Pte. Ltd.


 Structure and formation  semiconductor device structure patent thumbnailStructure and formation semiconductor device structure
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


 Semiconductor device patent thumbnailSemiconductor device
A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate. A first insulating film is around the fin-shaped semiconductor layer and a pillar-shaped semiconductor layer is on the fin-shaped semiconductor layer.
Unisantis Electronics Singapore Pte. Ltd.


 Semiconductor devices with vertical field floating rings and methods of fabrication thereof patent thumbnailSemiconductor devices with vertical field floating rings and methods of fabrication thereof
A semiconductor device includes a semiconductor substrate having a first conductivity type. A gate structure is supported by a surface of the semiconductor substrate, and a current carrying region (e.g., a drain region of an ldmos transistor) is disposed in the semiconductor substrate at the surface.
Freescale Semiconductor, Inc.


 Method for producing semiconductor device and semiconductor device patent thumbnailMethod for producing semiconductor device and semiconductor device
A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate; a third step of forming a second dummy gate; a fourth step of forming a fifth insulating film and a sixth insulating film; a fifth step of depositing a first interlayer insulating film, removing the second dummy gate and the first dummy gate, forming a gate insulating film, depositing metal, and performing etch back to form a gate electrode and a gate line; a seventh step of forming a seventh insulating film; and an eighth step of forming insulating film sidewalls, forming a first epitaxially grown layer on the fin-shaped semiconductor layer, and forming a second epitaxially grown layer on the pillar-shaped semiconductor layer.. .
Unisantis Electronics Singapore Pte. Ltd.


 (110) surface orientation for reducing fermi-level-pinning between high-k dielectric and group iii-v compound semiconductor device patent thumbnail(110) surface orientation for reducing fermi-level-pinning between high-k dielectric and group iii-v compound semiconductor device
A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group iii-v compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group iii-v compound semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


Structure and formation semiconductor device structure

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack.
Taiwan Semiconductor Manufacturing Co., Ltd

Iii-v mosfet with strained channel and semi-insulating bottom barrier

Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a semiconductor substrate. A channel is formed on the bottom barrier.
International Business Machines Corporation

Semiconductor device and manufacturing the same

According to one embodiment, a semiconductor device includes a semiconductor substrate in which a recess is provided on a back surface thereof, and a shape of the recess is reflected on a surface of a metal film which is also provided on the back surface of the semiconductor substrate.. .
Kabushiki Kaisha Toshiba

Device with a conductive feature formed over a cavity and method therefor

An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the first substrate surface and electrically coupled to the transistor, and a second conductive feature covering only a portion of the second substrate surface to define a first conductor-less region. A cavity vertically aligned with the first conductive feature within the first conductor-less region extends into the semiconductor substrate.
Freescale Semiconductor, Inc.

Semiconductor device with metal extrusion formation

Embodiments disclose a method of fabrication and a semiconductor structure comprising a metal-insulator-metal (mim) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate.
International Business Machines Corporation

Semiconductor device with metal extrusion formation

Embodiments disclose a method of fabrication and a semiconductor structure comprising a metal-insulator-metal (mim) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate.
International Business Machines Corporation

Capacitor structure and forming the same

A capacitor structure includes first and second interdigitated conductive elements formed over different portions of a semiconductor substrate, and a dielectric layer formed between the first and second interdigitated conductive elements. The first interdigitated conductive element that is formed includes a first base portion and a plurality of first protrusion portions.
Mediatek Inc.

Semiconductor device for optical applications and producing such a semiconductor device

A sensor (2) is arranged at a main surface (10) of a semiconductor substrate (1), and a filter (3) is arranged above the sensor. A through-substrate via (4) penetrates the substrate outside the region of the sensor.
Ams Ag

Backside illuminated image sensor and manufacturing the same

A backside illuminated (bsi) image sensor comprises a semiconductor substrate having a first surface and a second surface opposite to the first surface; a photosensitive element in the semiconductor substrate; a gate structure partially over the first surface of the semiconductor substrate; and a temporary carrier depository in proximity to the first surface of the semiconductor substrate, wherein the gate structure has a plug portion extending from the first surface toward the second surface. The plug portion of the gate structure helps to increase the charge transfer efficiency so as to improve quantum efficiency of the bsi image sensor..
Taiwan Semiconductor Manufacturing Company Ltd

Flash memory device

A method is provided for fabricating a flash memory device. The method includes providing a semiconductor substrate and thrilling a first polysilicon layer.

Structure and finfet device

A semiconductor device includes a first fin structure extending from a semiconductor substrate. A second fin structure is disposed over the first fin structure.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device

A semiconductor device includes a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other, an isolation pattern disposed between the first and second active regions, a semiconductor extension layer disposed between the first and second active regions, a first source/drain semiconductor layer disposed on the first active region, and a second source/drain semiconductor layer disposed on the second active region. The facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern..
Samsung Electronics Co., Ltd.

Contact structure and extension formation for iii-v nfet

Finfet devices including iii-v fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the iii-v fin structures to form n-type junctions.
International Business Machines Corporation

Semiconductor device and manufacturing the same

A semiconductor device is capable of accurately sensing a temperature of a semiconductor element incorporated in a semiconductor substrate. The semiconductor device includes a temperature sensor.
Toyota Jidosha Kabushiki Kaisha

Zener triggered silicon controlled rectifier with small silicon area

A semiconductor device includes a p-type semiconductor substrate, an n-well and a p-well disposed adjacent to each other and extending along a first direction within the p-type semiconductor substrate, a first n+ doped region and a first p+ doped region extending along the first direction within the n-well and spaced away from each other along a second direction perpendicular to the first direction, a second n+ doped region and a second p+ doped region extending along the first direction within the p-well and spaced away from each other along the second direction, and a plurality of third n+ doped regions and a plurality of p+ doped regions alternatively disposed in a junction region formed between the n-well and p-well the third n+ doped regions. The third n+ doped regions and the third p+ doped regions form a zener diode..
Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor device

A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad.
Fuji Electric Co., Ltd.

Semiconductor device assembly with heat transfer structure formed from semiconductor material

Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate.
Micron Technology, Inc.

Semiconductor device

A semiconductor device includes a pad group including pads provided on a semiconductor substrate and arranged in a row to form a pad row as a whole. The pad group includes at least one first pad provided with a first via-connection part electrically connected therewith and extending in a first direction perpendicular to a row direction of the pad row, and at least one second pad provided with a second via-connection part electrically connected therewith and extending in a second direction opposite to the first direction.
Lapis Semiconductor Co., Ltd.

Conductive paths through dielectric with a high aspect ratio for semiconductor devices

Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a plurality of conductive connection pads are formed on a semiconductor substrate to connect to circuitry formed on the substrate.
Intel Ip Corporation

Substrate dividing method

A substrate dividing method which can thin and divide a substrate while preventing chipping, and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness..
Hamamatsu Photonics K.k.

Seal ring structure to avoid delamination defect

A semiconductor device includes a semiconductor substrate, a plurality of integrated circuit devices on the semiconductor substrate, and a seal ring structure surrounding each one of the integrated circuit devices. The seal ring structure includes a plurality of interlayer dielectric layers and a plurality of hollow through-hole structures disposed within each of the interlayer dielectric layers.
Semiconductor Manufacturing International (shanghai) Corporation

Material and process for copper barrier layer

A method of fabricating a semiconductor device comprises forming a first dielectric material layer on a semiconductor substrate. The first dielectric material layer is patterned to form a plurality of vias therein.
Taiwan Semiconductor Manufacturing Company, Ltd.

Directly forming sige fins on oxide

Semiconductor mandrel structures are formed extending upward from a remaining portion of a semiconductor substrate. A first oxide isolation structure is formed on exposed surfaces of the remaining portion of the semiconductor substrate and between each semiconductor mandrel structure.
International Business Machines Corporation

Substrate dividing method

A substrate dividing method which can thin and divide a substrate while preventing chipping, and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness..
Hamamatsu Photonics K.k.

Substrate dividing method

A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness..
Hamamatsu Photonics K.k.

Substrate dividing method

A substrate dividing method which can thin and divide a substrate while preventing chipping, and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness..
Hamamatsu Photonics K.k.

Shallow trench isolation trenches and methods for nand memory

A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a liner in the trench, wherein the liner includes a first dielectric material, adhering a halogen element to the liner, forming a second dielectric material in the trench, annealing the first dielectric material and the second dielectric material, exposing a portion of a surface of the second dielectric material, and isotropically etching the exposed portion of the surface of the second dielectric material to form an air gap in the shallow trench isolation trench..
Sandisk Technologies Inc.

Air gap forming techniques based on anodic alumina for interconnect structures

An aluminum (al) layer is formed over a semiconductor substrate. A selective portion of the al layer is removed to form openings.
Taiwan Semiconductor Manufacturing Co., Ltd.

Solvent-based oxidation on germanium and iii-v compound semiconductor materials

A method to provide an isolation feature over a semiconductor structure is disclosed. The method includes forming a fin structure over a semiconductor substrate, forming an oxide layer over the fin structure, wherein forming the oxide layer includes performing a wet chemical oxidation process on the fin structure with a solvent mixture, forming a dielectric layer over the oxide layer, and forming at least one isolation feature over the semiconductor structure..
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device manufacturing method and foup to be used therefor

A semiconductor device manufacturing method which uses a foup capable of suppressing semiconductor substrate defects due to outgas. The foup includes: a main body having an opening for taking in or out a semiconductor wafer; a cover detachably attached to the main body in close contact with the main body in a manner to cover the opening; an intake hole and an exhaust hole which are formed in the main body; and a first filter provided on the intake hole and a second filter provided on the exhaust hole.
Renesas Electronics Corporation

Contact structure and extension formation for iii-v nfet

Finfet devices including iii-v fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the iii-v fin structures to form n-type junctions.
International Business Machines Corporation

Technique to deposit sidewall passivation for high aspect ratio cylinder etch

Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner.
Lam Research Corporation

Methods for manufacturing semiconductor devices

A method for forming a semiconductor device includes providing a semiconductor substrate having an upper side and comprising, in a vertical cross-section substantially orthogonal to the upper side, a plurality of semiconductor mesas of a first monocrystalline semiconductor material which are spaced apart from each other by sacrificial layers selectively etchable with respect to the first monocrystalline semiconductor material and arranged in trenches extending from the upper side into the semiconductor substrate, forming on the semiconductor mesas a support structure mechanically connecting the semiconductor mesas, at least partly replacing the sacrificial layers while the semiconductor mesas remain mechanically connected via the support structure, and at least partly removing the support structure.. .
Infineon Technologies Dresden Gmbh

Method for forming polysilicon

A method for forming polysilicon on a semiconductor substrate that include providing amorphous silicon on a semiconductor substrate, exposing at least an area of the amorphous silicon to a first laser beam and a second laser beam, characterized in that during exposing the area to the second laser beam no displacement of the laser beam relative to the area occurs. In addition, the use of such method for producing large grain polysilicon.
Laser Systems & Solutions Of Europe

Optical biosensor device

The present disclosure relates to an integrated chip having an integrated optical bio-sensor, and an associated method of fabrication. In some embodiments, the integrated optical bio-sensor has a sensing device arranged within a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Electronic device and magnetic sensor integrated circuit

An electronic device and a magnetic sensor integrated circuit thereof are provided. The magnetic sensor integrated circuit includes a shell, a semiconductor substrate installed in the shell and a first to a third port extending from the shell.
Johnson Electric S.a.

Apparatus and method related to reaction chamber with shutter system

A reaction chamber assembly with a shutter system may be used in the processing of semiconductor substrates. The shutter system may facilitate gas flow control and temperature control within the reaction chamber assembly..
Asm Ip Holding B.v.

Solid-state imaging device and electronic apparatus

A solid-state imaging device including a phase difference pixel that includes: a photoelectric conversion unit formed in a semiconductor substrate; a light blocking film that is provided in an insulating layer stacked on the semiconductor substrate, and shields substantially a half of the phase difference pixel from light, with the boundary being the pupil position; and a polarizing structure that polarizes light passing through an opening portion not shielded from light by the light blocking film. The present technology can be applied to solid-state imaging devices capable of image plane phase difference autofocusing, for example..

High-efficiency vertical emitters with improved heat sinking

A method for production of an optoelectronic device includes fabricating a plurality of vertical emitters on a semiconductor substrate. Respective top surfaces of the emitters are bonded to a heat sink, after which the semiconductor substrate is removed below respective bottom surfaces of the emitters.
Apple Inc.

Semiconductor device and manufacturing same

A fet is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction..
Semiconductor Energy Laboratory Co., Ltd.

Annealing for damage free laser processing for high efficiency solar cells

Annealing solutions providing damage-free laser patterning utilizing auxiliary heating to anneal laser damaged ablation regions are provided herein. Ablation spots on an underlying semiconductor substrate are annealed during or after pulsed laser ablation patterning of overlying transparent passivation layers..
Solexel, Inc.

Solar cell and manufacturing the same

Disclosed is a solar cell including a semiconductor substrate, a conductive area including a first conductive area and a second conductive area formed on one surface of the semiconductor substrate, a passivation film formed on the conductive area, the passivation film having a contact hole, a protective film formed on the conductive area inside the contact hole, the protective film being formed on at least one of at least a portion of an inner side surface of the contact hole and the passivation film, and an electrode electrically connected to the conductive area through the contact hole with the protective film interposed therebetween.. .
Lg Electronics Inc.

Solar cell

A solar cell includes: a semiconductor substrate having a light-receiving surface and a back surface; a first-conductivity-type first semiconductor layer on the back surface; a second-conductivity-type second semiconductor layer on the back surface; a first electrode electrically connected to the first semiconductor layer; a second electrode electrically connected to the second semiconductor layer; and an insulating layer in a boundary region between a first-conductivity-type region of the first semiconductor layer and a second-conductivity-type region of the second semiconductor layer. The insulating layer has an inclined side surface adjacent the second-conductivity-type region inclined such that the thickness of the insulating layer decreases with decreasing distance from the second-conductivity-type region.
Panasonic Intellectual Property Management Co., Ltd.

Solar cell and manufacturing the same

A solar cell includes: a semiconductor substrate having a light receiving surface and a back surface; a first semiconductor layer of the first conductivity type on the back surface; a second semiconductor layer of the second conductivity type on the back surface; a first electrode electrically connected to the first semiconductor layer; and an insulating layer for electrically insulating the first semiconductor layer and the second semiconductor layer from each other in a region in which an edge of the first semiconductor layer and an edge of second semiconductor layer overlap. The first electrode includes a first transparent electrode layer and a first collection electrode layer on the first transparent electrode layer.
Panasonic Intellectual Property Management Co., Ltd.

Semiconductor transistor having buffer layer between channel and substrate

Finfet and fabrication method thereof. The finfet fabrication method includes providing a semiconductor substrate; forming a plurality of trenches in the semiconductor substrate, forming a buffer layer on the semiconductor substrate by filling the trenches and covering the semiconductor substrate, and forming a fin body by etching the buffer layer.
Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor device and manufacturing the same

In a vertical mosfet in which bottom portions of each gate electrode formed in a ditch are extended toward the drain region, the on resistance is reduced while preventing voltage resistance reduction and switching speed reduction caused by a capacitance increase between the gate and drain. A vertical mosfet includes first ditches, second ditches, and gate electrodes.
Renesas Electronics Corporation

Integrated high side gate driver structure and circuit for driving high side power transistors

The present invention relates to an integrated high side gate driver structure for driving a power transistor. The high side gate driver structure comprises a semiconductor substrate comprising a first polarity semiconductor material in which a first well diffusion comprising a second polarity semiconductor material is formed.
Merus Audio Aps

Super junction device and manufacturing the same

A method of manufacturing super junction device includes forming a first epitaxial layer on a semiconductor substrate. The first epitaxial layer is patterned to form a trench.
Super Group Semiconductor Co., Ltd.

Semiconductor device

When formed to have a lattice pattern, trenches are deeper at the portions thereof corresponding to the vertices of the lattice pattern than at the portions thereof corresponding to the sides. Such variations in the depths of trenches may disadvantageously result in variations in the gate threshold voltages (vth).
Fuji Electric Co., Ltd.

Memory cell structure for improving erase speed

A split-gate flash memory cell for improved erase speed is provided. An erase gate and a floating gate are laterally spaced over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Recess array device with reduced contact resistance

A recess array device includes a semiconductor substrate having a main surface; a recessed trench in the main surface of the semiconductor substrate; a gate electrode disposed at a lower portion of the recessed trench; a liner layer disposed on directly on the gate electrode and being in direct contact with the gate electrode; a gate dielectric layer disposed only between the gate electrode and the semiconductor substrate and between the liner layer and the semiconductor substrate; and an epitaxial silicon layer disposed at an upper portion of the recessed trench.. .
Inotera Memories, Inc.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a semiconductor substrate, at least one dielectric layer, a dielectric spacer liner (dsl) layer, and at least one conductor. The dielectric layer is present on the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Reduction of defect induced leakage in iii-v semiconductor devices

A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 108 cm−2. An n-type layer is formed on or in the p-doped layer.
International Business Machines Corporation

Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods

A semiconductor device may include a semiconductor substrate, and a plurality of field effect transistors (fets) on the semiconductor substrate. Each fet may include a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices..
Atomera, Incorporated

Semiconductor devices with superlattice and punch-through stop (pts) layers at different depths and related methods

A semiconductor device may include a semiconductor substrate and first transistors having a first operating voltage. Each first transistor may include a first channel and a first punch-through stop (pts) layer in the semiconductor substrate, and the first pts layer may be at a first depth below the first channel.
Atomera, Incorporated

Semiconductor device

A semiconductor device includes a semiconductor substrate, a base region formed in the semiconductor substrate on a front surface side thereof, a gate trench extending from a front surface side of the base region and penetrating thorough the base region, and a dummy trench extending from the front surface side of the base region and penetrating thorough the base region, where a portion of the dummy trench that extends beyond a back surface of the base region is longer than a portion of the gate trench that extends beyond the back surface of the base region.. .
Fuji Electric Co., Ltd.

Semiconductor device

A semiconductor device that includes a plurality of trench gate structures each having a gate electrode extending in a depth direction of an element, the plurality of trench gate structures including first trench gate structures respectively contributing to control of the element and second trench gate structures respectively not contributing to the control of the element, the semiconductor device including an electrode portion having a potential other than a gate potential, and an electrode pad that is disposed on a front face of a semiconductor substrate, wherein the electrode pad is used as a terminal to apply a predetermined voltage to gate insulator films, in screening that is executed by applying the predetermined voltage to the gate insulator films respectively in contact with the gate electrode connected to the electrode pad and that is executed before the electrode pad is short-circuited to the electrode portion.. .
Denso Corporation

Semiconductor device and manufacturing semiconductor device

A semiconductor device includes a plurality of trench gates provided abreast in a semiconductor substrate; an interlayer insulation film having opening from which a part of a front surface of the semiconductor substrate is exposed; and contact plugs provided in the openings. The interlayer insulation film comprises a plurality of first portions, each of which covers a corresponding one of the trench gates, and a plurality of second portions, each of which is provided between adjacent first portions and along a direction intersecting with the first portions.
Toyota Jidosha Kabushiki Kaisha

Semiconductor device

A semiconductor device includes a fin-shaped semiconductor layer on a surface of a semiconductor substrate having a longitudinal axis extending in a first direction parallel to the surface. A first insulating film is around the fin-shaped semiconductor layer and a pillar-shaped semiconductor layer is on the fin-shaped semiconductor layer.
Unisantis Electronics Singapore Pte. Ltd.

Nonvolatile memory cell with improved isolation structures

A method for forming a non-volatile memory cell is provided. The method comprises: forming a field region with a first impurity type in a semiconductor substrate, the field region having a first impurity concentration; forming a plurality of spaced apart higher concentration regions with the first impurity type within the field region, the higher concentration regions each having a higher concentration than the first impurity concentration; and forming a plurality of floating gate transistors in the field region between the higher concentration regions..
Wafertech, Llc

Reduction of defect induced leakage in iii-v semiconductor devices

A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 108 cm−2. An n-type layer is formed on or in the p-doped layer.
International Business Machines Corporation

New dual-gate trench igbt with buried floating p-type shield

A method of manufacturing an insulated gate bipolar transistor (igbt) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.. .
Alpha And Omega Semiconductor Incorporated

Method for producing semiconductor device

A method for producing a semiconductor device includes forming a fin-shaped semiconductor layer on a semiconductor substrate and a first pillar-shaped semiconductor layer, a first dummy gate layer and a second pillar-shaped semiconductor layer, and a second dummy gate layer. Third and fourth dummy gate layers are formed on sidewalls of the first dummy layer gate, the first pillar-shaped semiconductor layer, the second dummy gate layer and the second pillar-shaped semiconductor layer.
Unisantis Electronics Singapore Pte. Ltd.

Semiconductor integrated circuit device having vertical channel and manufacturing the same

A semiconductor integrated circuit device having a vertical channel and a method of manufacturing the same are provided. A plurality of active lines are formed in a semiconductor substrate.
Sk Hynix Inc.

Semiconductor devices and methods of manufacture thereof

A method of forming an sram cell includes forming a first vertical pull-down transistor, a second vertical pull-down transistor, a first vertical pass-gate transistor, and a second vertical pass-gate transistor over a semiconductor substrate. The method includes forming a first conductive trace over a top surface of the first vertical pull-down transistor and the first vertical pass-gate transistor, forming a second conductive trace over a top surface of the second vertical pull-down transistor and the second vertical pass-gate transistor, and forming a first vertical pull-up transistor over a first portion of the first conductive trace.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device including capacitor and manufacturing the same

A semiconductor device includes a semiconductor substrate having a first region and a second region; a first planar type capacitor including a gate electrode which is positioned in any one region of the first region and the second region; a non-planar type capacitor including a plurality of non-planar type electrodes which are positioned in the other region of the first region and the second region; a second planar type capacitor including a planar type electrode which is positioned over the first planar type capacitor to overlap with the first planar type capacitor; and a common node under the non-planar type capacitor.. .
Sk Hynix Inc.

Method for manufacturing semiconductor package structure

A method for manufacturing a semiconductor package structure is provided. A semiconductor substrate comprising a conductive pad is provided, wherein the conductive pad is coupled with a circuitry of the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company Ltd.

Connecting techniques for stacked cmos devices

In some embodiments, the present disclosure relates to an integrated chip having an inter-tier interconnecting structure having horizontal components, which is arranged within a semiconductor substrate and configured to electrically couple a first device tier to a second device tier. The integrated chip has a first device tier with a first semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5).
Rohm Co., Ltd.

Semiconductor substrate and semiconductor package structure having the same

A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump.
Advanced Semiconductor Engineering, Inc.

Cavity formation in semiconductor devices

Fabricating of radio-frequency (rf) devices involve providing a field-effect transistor (fet) formed over an oxide layer formed on a semiconductor substrate, removing at least part of the semiconductor substrate to expose at least a portion of a backside of the oxide layer, applying a sacrificial material to the backside of the oxide layer, applying an interface material to at least a portion of the backside of the oxide layer, the interface material at least partially covering the sacrificial material, and removing at least a portion of the sacrificial material to form a cavity at least partially covered by the interface layer.. .
Skyworks Solutions, Inc.

Semiconductor device and manufacturing the same

A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, a wiring having copper as a main component and formed above the insulating film, and a barrier metal film having a higher modulus of rigidity than copper and interposed between the insulating film and the wiring. The barrier metal film may have a lower thermal expansion coefficient than copper..
Rohm Co., Ltd.

Semiconductor device having gold metallization structures

A semiconductor device includes a semiconductor substrate having first and second terminals of one or more semiconductor devices, first and second barrier metal regions electrically connected to the first and second terminals, respectively, and first and second gold metallization structures electrically connected to the first and second terminals via the first and second barrier metal regions, respectively. The first and second gold metallization structures contain diffused copper atoms.
Infineon Technologies Austria Ag

Semiconductor device

A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor substrate; an electrode pad provided on the main plane of the semiconductor substrate and connected to the semiconductor element; a guard ring surrounding the semiconductor element and the electrode pad, and provided on the main plane of the semiconductor substrate; and an insulating film covering all region of a semiconductor of the main plane of the semiconductor substrate exposed inside the guard ring, wherein the insulating film is made of a water impermeable material.. .
Mitsubishi Electric Corporation

Method for wafer level reliability

A method for ensuring wafer level reliability is provided. The method involves: forming a gate oxide layer having a thickness of less than 50 Å on a semiconductor substrate; forming a pmos element having a channel length of less than 0.13 μm on the semiconductor substrate; and assessing hot carrier injection (hcl) for the pmos element..
Magnachip Semiconductor, Ltd.

Backside cavity formation in semiconductor devices

Fabrication of radio-frequency (rf) devices involves providing a field-effect transistor (fet) formed over an oxide layer formed on a semiconductor substrate, removing at least part of the semiconductor substrate to expose at least a portion of a backside of the oxide layer, applying an interface material to at least a portion of the backside of the oxide layer, removing at least a portion of the interface material to form a trench, and covering at least a portion of the interface material and the trench with a substrate layer to form a cavity.. .
Skyworks Solutions, Inc.

Method for manufacturing a semiconductor device

A method for manufacturing a semiconductor device includes etching a semiconductor substrate to form a fin-shaped semiconductor layer. After forming the fin-shaped semiconductor layer, a first insulating film is deposited around the fin-shaped semiconductor layer.
Unisantis Electronics Singapore Pte. Ltd.

Method for filling the trenches of shallow trench isolation (sti) regions

A method for manufacturing a shallow trench isolation (sti) region with a high aspect ratio is provided. A semiconductor substrate is provided with a trench.
Taiwan Semiconductor Manufacturing Co., Ltd.

High temperature substrate pedestal module and components thereof

A semiconductor substrate processing apparatus comprises a vacuum chamber in which a semiconductor substrate may be processed, a showerhead module through which process gas from a process gas source is supplied to a processing zone of the vacuum chamber, and a substrate pedestal module. The substrate pedestal module includes a platen, a stem having a side wall defining a cylindrical interior region thereof, a lower surface, and an upper end that supports the platen, and an adapter having a side wall defining a cylindrical interior region thereof and an upper surface that supports the stem.
Lam Research Corporation

Manufacturing semiconductor device

The reliability of a semiconductor device is improved. In a manufacturing method, a film to be processed is formed over a circular semiconductor substrate, and a resist layer whose surface has a water-repellent property is formed thereover.
Renesas Electronics Corporation



Semiconductor Substrate topics:
  • Semiconductor Substrate
  • Semiconductor
  • Semiconductor Device
  • Gallium Nitride
  • Memory Cell
  • Phase Change Memory
  • Phase Change Material
  • Memory Device
  • Semiconductor Memory
  • Integrated Circuit
  • Transistors
  • Field Effect Transistor
  • Planarization
  • Conductive Layer
  • Semiconductor Devices


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