|| List of recent Semiconductor Substrate-related patents
| Semiconductor memory device|
According to one embodiment, a semiconductor memory device includes: string units including a plurality of memory cells stacked above a semiconductor substrate; and a control circuit configured to perform an erase operation per a block, the block including the string units, the control circuit being configured to perform an erase verify operation per string unit.. .
| Method of manufacturing semiconductor device|
A method of manufacturing a semiconductor device according to the present invention includes the steps of (b) forming, on a back face of a dummy substrate and back faces of a plurality of semiconductor substrates, inorganic films having such thicknesses as to be resistant to a temperature of a thermal oxidizing treatment or a heat treatment and to sufficiently decrease an amount of oxidation or reducing gaseous species to reach the back faces of the dummy substrate and the plurality of semiconductor substrates, (c) disposing the dummy substrate and the plurality of semiconductor substrates in a lamination with surfaces turned in the same direction at an interval from each other, and (d) carrying out a thermal oxidizing treatment or post annealing over the surfaces of the semiconductor substrates in an oxidation gas atmosphere or a reducing gas atmosphere after the steps (b) and (c).. .
| Integrated platform for improved wafer manufacturing quality|
The present disclosure relates to a method and apparatus for performing a dry plasma procedure, while mitigating internal contamination of a semiconductor substrate. In some embodiments, the apparatus includes a semiconductor processing tool having a dry process stage with one or more dry process elements that perform a dry plasma procedure on a semiconductor substrate received from an input port.
| Semiconductor device manufacturing method|
A semiconductor device manufacturing method includes forming a dielectric film on a semiconductor substrate; performing a heat treatment on the dielectric film; forming an electrode on a first region of the dielectric film; irradiating an ionized gas cluster to a second region of the dielectric film where the electrode is not formed; and removing the second region of the dielectric film where the ionized gas cluster is irradiated by a wet etching after the irradiating of the ionized gas cluster.. .
| Phase change memory device having self-aligned bottom electrode and fabrication method thereof|
A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer..
| Method of manufacturing a semiconductor device|
After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed.
| Three dimensional non-volatile storage with asymmetrical vertical select devices|
A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate.
| Method for fabricating nonvolatile memory structure|
A nonvolatile memory structure includes a semiconductor substrate having thereon a first oxide define (od) region, a second od region and a third od region arranged in a row. The first, second, and third od regions are separated from one another by an isolation region.
| Tunable schottky diode with depleted conduction path|
A method of fabricating a schottky diode having an integrated junction field-effect transistor (jfet) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the schottky diode. The conduction path region has a first conductivity type.
| Solid-state imaging device, method of manufacturing same, and electronic apparatus|
A solid-state imaging device includes a plurality of photoelectric conversion units configured to receive light and generate signal charge, the plurality of photoelectric conversion units being provided in such a manner as to correspond to a plurality of pixels in a pixel area of a semiconductor substrate; and pixel transistors configured to output the signal charge generated by the photoelectric conversion units as electrical signals. Each of the pixel transistors includes at least a transfer transistor that transfers the signal charge generated in the photoelectric conversion unit to a floating diffusion corresponding to a drain.
| Material for forming passivation film for semiconductor substrate, passivation film for semiconductor substrate and method of producing the same, and photovoltaic cell element and method of producing the same|
The invention provides a material for forming a passivation film for a semiconductor substrate. The material includes a polymer compound having an anionic group or a cationic group..
| Light emitting device, manufacturing method thereof, and optical transceiver|
The light emitting device includes an active layer formed on a semiconductor substrate for emitting light, a semiconductor layer of a first conductivity type electrically connected to one end of the active layer, a semiconductor layer of a second conductivity type electrically connected to the other end of the active layer, first and second electrodes, a feedback mechanism for laser oscillation, and a waveguide for guiding the light emitted from the active layer, in which the active layer is made of a semiconductor having an affinity with a silicon cmos process, and the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type, and the waveguide are each made of silicon as a part of the semiconductor substrate.. .
| Quantum cascade laser|
A quantum cascade laser 1 includes a semiconductor substrate, an active layer 15 that is disposed on the semiconductor substrate and has a cascade structure in which a unit layered structure 16 including a quantum well light emitting layer and an injection layer is stacked in multiples to alternately stack the quantum well light emitting layer and the injection layer, and a diffraction grating layer 20 disposed on the active layer.. .
| Semiconductor memory device|
A memory cell array comprises first wiring lines, second wiring lines, and memory cells disposed at intersections thereof. A control circuit comprises a first power-supply line supplying a first voltage to selected ones of the first or second wiring lines, and first selection circuits connected between the first or second wiring lines and the first power-supply line, each first selection circuit comprising first and second transistors connected in series.
| Solid state imaging device, portable information terminal, and solid state imaging system|
A solid state imaging device according to an embodiment includes: an imaging element formed on a semiconductor substrate, and including pixel blocks each having pixels; a main lens forming an image of a subject on an imaging plane; a microlens array including microlenses corresponding to the pixel blocks, the microlens array reducing an image to be formed on the imaging plane by nf times or less and forming reduced images on the pixel blocks corresponding to the respective microlenses; and an image processing unit enlarging and synthesizing the reduced images formed by the microlenses, the solid state imaging device meeting conditions of an expression mtfmain(u)≦mtfml(u)≦mtfmain(u×nf) where u denotes an image spatial frequency, mtfml(u) denotes an mtf function of the microlenses, and mtfmain(u) denotes an mtf function of the main lens.. .
| Solid-state imaging device and electronic equipment|
A solid-state imaging device includes: a semiconductor substrate having a light receiving surface sectioned for red, green, blue, and white pixels arranged in a matrix with photodiodes formed thereon; color filters formed on the semiconductor substrate in light incident paths to the photodiodes of the respective formation regions of the red, green, and blue pixels and respectively transmitting lights in red, green, and blue wavelength regions; and photochromic films formed on the semiconductor substrate in the light incident path to the photodiodes in the formation regions of at least some of the white pixels, and containing a photochromic material having light transmittance varying in response to incident light intensity in a predetermined wavelength region, wherein a half period of the light transmittance of the photochromic films is shorter than one frame as a period in which pixel signals obtained in the pixels are read out with respect to all pixels.. .
| Semiconductor device|
A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage..
| Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof|
A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring.
| Semiconductor device and method for manufacturing semiconductor device|
A semiconductor device includes a semiconductor substrate. A through hole extends through the semiconductor substrate.
| Semiconductor device and manufacturing method thereof|
To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by cmp and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by cmp and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate..
| Silicided trench contact to buried conductive layer|
A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate.
| Method for forming sintered silver coating film, baking apparatus, and semiconductor device|
In a method for forming a sintered silver coating film, for use as a heat spreader, on a semiconductor substrate or a semiconductor package, a coating film of an ink or paste containing silver nanoparticles is formed on one surface of the semiconductor substrate or the substrate package. Further, the coating film is sintered by heating the coating film under an atmosphere of a humidity of 30% to 50% rh (30° c.) by a ventilation oven..
| Resin package|
A resin package includes: a die pad having a main surface on which a semiconductor substrate and a matching circuit substrate is mounted; at least one lead terminal electrically connected to the semiconductor substrate and the matching circuit substrate; a thin plate fixed to at least one of the main surface of the die pad and a main surface of the at least one lead terminal; and molding resin which covers the semiconductor substrate, the matching circuit substrate, and the thin plate.. .
| Multiple bonding layers for thin-wafer handling|
Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another.
| Semiconductor devices including a lateral bipolar structure and fabrication methods|
A semiconductor device includes an emitter region, a collector region and a base region. The emitter region is implanted in a semiconductor substrate.
| Semiconductor device and method of manufacturing the same|
A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area.
| Solid-state image sensor and electronic device|
There is provided a solid-state image sensor including a semiconductor substrate in which a plurality of pixels are arranged, and a wiring layer stacked on the semiconductor substrate and formed in such a manner that a plurality of conductor layers having a plurality of wirings are buried in an insulation film. In the wiring layer, wirings connected to the pixels are formed of two conductor layers..
| Image sensor and computing system having the same|
An image sensor includes a light receiving element, an anti-reflection layer, a high refractive pattern, a color filter, and a micro lens. The light receiving element is formed on a semiconductor substrate to generate charges responsive to incident light.
| Solid-state imaging device|
According to one embodiment, a photoelectric converting layer, a charge accumulating layer, and a light collecting unit are provided. The photoelectric converting layer is formed at a back surface side of a semiconductor substrate.
| Radiation detector|
A radiation detector has a semiconductor substrate of a first conductivity type, a plurality of semiconductor regions of a second conductivity type making junctions with the semiconductor substrate, and a plurality of electrodes joined to the corresponding semiconductor regions. The electrodes cover the corresponding semiconductor regions, when viewed from a direction perpendicular to a first principal face.
| Silicon nitride gate encapsulation by implantation|
A method of forming a finfet structure which includes forming fins on a semiconductor substrate; forming a gate wrapping around at least one of the fins, the gate having a first surface and an opposing second surface facing the fins; depositing a hard mask on a top of the gate; angle implanting nitrogen into the first and second surfaces of the gate so as to form a nitrogen-containing layer in the gate that is below and in direct contact with the hard mask on top of the gate; forming spacers on the gate and in contact with the nitrogen-containing layer; and epitaxially depositing silicon on the at least one fin so as to form a raised source/drain. Also disclosed is a finfet structure..
| Semiconductor device having electrode and manufacturing method thereof|
The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench..
| Replacement metal gate transistor with controlled threshold voltage|
A method and structure for a semiconductor device includes a semiconductor substrate and an n-channel transistor and a p-channel transistor provided on the semiconductor substrate. Each of the n-channel transistor and the p-channel transistor has a gate dielectric film on the semiconductor substrate, and a gate electrode is formed on the gate dielectric.
| Silicon nitride gate encapsulation by implantation|
A finfet structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; a gate wrapping around at least one of the silicon fins, the gate having a first surface and an opposing second surface facing the at least one of the silicon fins; a hard mask on a top surface of the gate; a silicon nitride layer formed in each of the first and second surfaces so as to be below and in direct contact with the hard mask on the top surface of the gate; spacers on the gate and in contact with the silicon nitride layer; and epitaxially deposited silicon on the at least one of the silicon fins so as to form a raised source/drain.. .
| Insulated gate field effect transistor and method of manufacturing the same|
An insulated gate field effect transistor configured to reduce the occurrence of a short-circuit fault, and a method of manufacturing the insulated gate field effect transistor are provided. A fet includes a semiconductor substrate, a gate insulator, a gate electrode, and a conductive member.
| Nonvolatile semiconductor memory device provided with charge storage layer in memory cell|
A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film.
| Manufacturing method of semiconductor device, and semiconductor device|
To enhance the performance of a semiconductor device. In a method for manufacturing a semiconductor device, a metal film is formed over a semiconductor substrate having an insulating film formed on a surface thereof, and then the metal film is removed in a memory cell region, whereas, in a part of a peripheral circuit region, the metal film is left.
| Semiconductor storage device and method of manufacturing the same|
A semiconductor device including a first isolation region dividing a semiconductor substrate into first regions; memory cells each including a tunnel insulating film, a charge storing layer, an interelectrode insulating film, and a control gate electrode above the first region; a second isolation region dividing the substrate into second regions in a peripheral circuit region; and a peripheral circuit transistor including a gate insulating film and a gate electrode above the second region. The first isolation region includes a first trench, a first element isolation insulating film filled in a bottom portion of the first trench, and a first gap formed between the first element isolation insulating film and the interelectrode insulating film.
| Mos varactor optimized layout and methods|
Apparatus and methods for a mos varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer.
| Capacitors comprising slot contact plugs and methods of forming the same|
An integrated circuit includes a semiconductor substrate, and an insulation region extending from a top surface of the semiconductor substrate into the semiconductor substrate. An inter-layer dielectric (ild) is overlying the insulation region.
| Methods and apparatus for suppressing cross talk in cmos image sensors|
A cmos image sensor with reduced crosstalk includes a semiconductor substrate formed with a plurality of photodiodes formed therein, a dielectric layer formed on the semiconductor substrate, a reflective layer formed on the dielectric layer, and an insulating layer formed on the reflective layer. A plurality of grooves is formed in the dielectric layer, the reflective layer, and the insulating layer above a corresponding photodiode.
| Semiconductor device and a method of manufacturing the same, and solid-state image pickup device using the same|
A semiconductor device, including: a gate electrode formed on a semiconductor substrate through a gate insulating film; an extension region formed in the semiconductor substrate on a source side of the gate electrode; a source region formed in the semiconductor substrate on the source side of the gate electrode through the extension region; an ldd region formed in the semiconductor substrate on a drain side of the gate electrode; and a drain region formed in the semiconductor substrate on the drain side of the gate electrode through the ldd region; wherein the extension region is formed at a higher concentration than that of the ldd region so as to be shallower than the ldd region.. .
| Fin field-effect transistors and fabrication method thereof|
A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate; and forming a plurality of fins on top of the semiconductor substrate.
| Drain pad having a reduced termination electric field|
In an exemplary implementation, a semiconductor device includes a drain pad on a semiconductor substrate, the drain pad being coupled to a plurality of drain fingers. The semiconductor device further includes a source pad on the semiconductor substrate, the source pad being coupled to a plurality of source fingers.
| Structure and method for defect passivation to reduce junction leakage for finfet device|
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (sti) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate.
| Film thickness measurement method|
A measurement target including a semiconductor substrate, and a first epitaxial layer and a second epitaxial layer stacked in this order on the semiconductor substrate and having no difference in refractive index of a real part from the semiconductor substrate is subjected to reflection interference analysis using a fourier transform infrared spectroscopy. The thickness of the first epitaxial layer is used as a fitting parameter so as to prevent shift between an interference waveform of a resultant reflection interference pattern containing distortion appearing in a wave number range near an abnormal dispersion range of a refractive index caused by phonon absorption and an interference waveform of a numerically calculated reflection interference pattern in the same wave number range.
| Design of a mold for forming complex 3d mems components|
A mold structure having high-precision multi-dimensional components includes: depositing an oxide layer on a top surface of a plurality of semiconductor substrates, patterning a design integrated in one or more of the oxide layers; repositioning the substrates to enable the oxide layers make contact with one another; bonding in sequential order the repositioned substrates using a dielectric bonding, forming a three dimension (3d) mold; filling the 3d mold with filling material and removing the overburden filling material present on a top surface of the component.. .
| N-type silicon solar cell with contact/protection structures|
A solar cell is formed on an n-type semiconductor substrate having a p+ emitter layer by forming spaced-apart contact/protection structures on the emitter layer, depositing a blanket dielectric passivation layer over the substrate's upper surface, utilizing laser ablation to form contact openings through the dielectric layer that expose corresponding contact/protection structures, and then forming metal gridlines on the upper surface of the dielectric layer that are electrically connected to the contact structures by way of metal via structures extending through associated contact openings. The contact/protection structures serve both as protection against substrate damage during the contact opening formation process (i.e., to prevent damage of the p+ emitter layer caused by the required high energy laser pulses), and also serve as optional suicide sources that facilitate optimal contact between the metal gridlines and the p+ emitter layer..
| Photoelectric conversion device and manufacturing method thereof, and photoelectric conversion module|
A photoelectric conversion device in which a substantially intrinsic i-type amorphous hydrogen-containing semiconductor layer, a p-type amorphous hydrogen-containing semiconductor layer, and a first transparent conductive layer are stacked in this order on a first surface of an n-type semiconductor substrate that generates a photogenerated carrier by receiving light, wherein the first transparent conductive layer includes a hydrogen-containing area formed of a transparent conductive material that contains hydrogen and a hydrogen-diffusion suppression area that is present on a side of the p-type amorphous hydrogen-containing semiconductor layer with respect to the hydrogen-containing area and that is formed of a transparent conductive material that does not substantially contain hydrogen, and the hydrogen-diffusion suppression area has a hydrogen concentration distribution in which a hydrogen content on a side of the p-type amorphous hydrogen-containing semiconductor layer is lower than that on a side of the hydrogen-containing area.. .
| Apparatus and method for cleaning semiconductor substrate|
A semiconductor substrate cleaning method includes cleaning a semiconductor substrate formed with a line-and-space pattern, supplying rinse water to rinse the substrate, rinsing the substrate, and drying the substrate. The supplying rinse water includes supplying deionized water and hydrochloric acid into a mixing section to mix the deionized water and the hydrochloric acid into a mixture, heating the mixture in the mixing section by a heater, detecting a ph value and a temperature of the mixture by a ph sensor and a temperature sensor respectively, adjusting an amount of hydrochloric acid supplied into the mixing section so that the rinse water has a predetermined ph value indicative of acidity, and energizing or de-energizing the heater so that the temperature of the mixture detected by the temperature sensor reaches a predetermined temperature, thereby producing the rinse water which has a temperature of not less than 70° c.
|Diarylamine novolac resin|
(in formula (1), each of ar1 and ar2 is a benzene ring or a naphthalene ring). A method for manufacturing a semiconductor device, including: forming an underlayer film on a semiconductor substrate with the resist underlayer film-forming composition; forming a hardmask on the underlayer film; forming a resist film on the hardmask; forming a resist pattern by irradiation with light or an electron beam followed by development; etching the hardmask with the resist pattern; etching the underlayer film with the hardmask thus patterned; and processing the semiconductor substrate with the underlayer film thus patterned..
|Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches|
Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer.
|Multi-composition dielectric for semiconductor device|
The present disclosure provides a method of semiconductor device fabrication including forming a multi-composition ild layer by forming a first portion of an inter-layer dielectric (ild) layer on a semiconductor substrate; and forming a second portion of an ild layer on the first portion of the ild layer. The second portion may have a greater silicon content than the first portion.
|Semiconductor device and method of forming epitaxial layer|
A method for forming epitaxial layer is disclosed. The method includes the steps of providing a semiconductor substrate, and forming an undoped first epitaxial layer in the semiconductor substrate.
|Method of making mosfet integrated with schottky diode with simplified one-time top-contact trench etching|
Method for fabricating mosfet integrated with schottky diode (mosfet/sky) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein.
|Semiconductor manufacturing apparatus and manufacturing method of semiconductor device|
A semiconductor manufacturing apparatus according to the present embodiment comprises a vacuum chamber. A first stage is configured to temporarily attach a reticle thereonto in order to attract a foreign material present on a back surface of the reticle.
|Solid-state imaging device, manufacturing method thereof, and electronic apparatus|
A solid-state imaging device having a backside illuminated structure, includes: a pixel region in which pixels each having a photoelectric conversion portion and a plurality of pixel transistors are arranged in a two-dimensional matrix; an element isolation region isolating the pixels which is provided in the pixel region and which includes a semiconductor layer provided in a trench by an epitaxial growth; and a light receiving surface at a rear surface side of a semiconductor substrate which is opposite to a multilayer wiring layer.. .
|Digital camera with multiple pipeline signal processors|
A method includes sampling a first intensity of light with a first array of photo detectors of a digital camera. A second intensity of light is sampled with a second array of photo detectors of the digital camera.
|Semiconductor device and manufacturing method thereof|
A semiconductor device according to an embodiment includes a semiconductor substrate that includes a first region and a second region having a thickness that is less than a thickness of the first region, a first metal film having a same film thickness provided in each of a first through hole, and a second through hole, the first through hole penetrating the semiconductor substrate from the second surface to the first surface in the first region, and the second through hole penetrating the semiconductor substrate from the second surface to the first surface in the second region. A second metal film is formed on the first metal films and is provided inside the first through hole, and inside and outside of the second through hole.
|Semiconductor device and electronic apparatus|
A semiconductor device that is connected to a wiring substrate includes a semiconductor substrate, a circuit provided on the semiconductor substrate, a connection terminal, and a guard ring that is provided on a peripheral region. In the semiconductor device, the guard ring includes a plurality of wiring layers, and a wiring layer included in the guard ring, which is the farthest from the semiconductor substrate, corresponds to a wiring layer closer to the semiconductor substrate relative to a wiring layer of the connection terminal..
The present invention includes a semiconductor substrate and a back electrode (a back multilayer electrode in the preferred embodiment) provided on a back surface of the semiconductor substrate. A rough source pattern is formed in a peripheral edge portion of the back surface of the semiconductor substrate which faces the back multilayer electrode..
A semiconductor device is provided, including a semiconductor substrate that includes a semiconductor; an electrode layer formed above a first surface side inside the semiconductor substrate; a conductor layer formed above the electrode layer and above the first surface of the semiconductor substrate; a hole formed through the semiconductor substrate from a second surface of the semiconductor substrate to the conductor layer; and a wiring layer that is electrically connected to the electrode layer via the conductor layer at an end portion of the vertical hole, and that extends to the second surface of the semiconductor substrate, the wiring layer being physically separated from the electrode layer by an insulating layer disposed therebetween.. .
|Device bond pads over process control monitor structures in a semiconductor die|
A semiconductor die includes a semiconductor substrate having an edge region surrounding an active region, the active region containing devices of an integrated circuit. The semiconductor die further includes interconnect wiring over the active region in an interlayer dielectric and electrically connected to the devices in the active region, and ancillary wiring over the edge region in the interlayer dielectric and isolated from the interconnect wiring and the devices in the active device region.
|Back end of the line (beol) interconnect scheme|
The present disclosure relates to a method of forming a back-end-of-the-line metal interconnect layer. The method is performed by depositing one or more self-assembled monolayers on a semiconductor substrate to define a metal interconnect layer area.
|Bipolar junction transistor and method of manufacturing the same|
A bipolar junction transistor (bjt) is provided. The bjt can include a semiconductor substrate, a first well disposed in the substrate and implanted with a first impurity, a second well disposed at one side of the first well and implanted with a second impurity, a first device isolation layer disposed in the first well and defining an emitter area, and a second device isolation layer disposed in the second well and defining a collector area, the bjt can also include an emitter having a second impurity, a base having a first impurity, a collector having a second impurity, and a high concentration doping area having a second impurity at high concentration.
|Process of ultra thick trench etch with multi-slope profile|
The present disclosure relates to an integrated chip (ic) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ild) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the ic has an inter-level dielectric layer disposed above a semiconductor substrate.
|Integrated circuits with improved gate uniformity and methods for fabricating same|
Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, an integrated circuit includes a semiconductor substrate and a replacement metal gate structure overlying the semiconductor substrate.
|Fin deformation modulation|
A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench.
|Ldmos device with double-sloped field plate|
In one general aspect, an apparatus can include a channel region disposed in a semiconductor substrate, a gate dielectric disposed on the channel region and a drift region disposed in the semiconductor substrate adjacent to the channel region. The apparatus can further include a field plate having an end portion disposed between a top surface of the semiconductor substrate and the gate dielectric the end portion can include a surface in contact with the gate dielectric, the surface having a first portion aligned along a first plane non-parallel to a second plane along which a second portion of the surface is aligned, the first plane being non-parallel to the top surface of the semiconductor substrate and the second plane being non-parallel to the top surface of the semiconductor substrate..
|Super junction semiconductor device comprising implanted zones|
In a semiconductor substrate with a first surface and a working surface parallel to the first surface, columnar first and second super junction regions of a first and a second conductivity type are formed. The first and second super junction regions extend in a direction perpendicular to the first surface and form a super junction structure.
|Methods of inducing a desired stress in the channel region of a transistor by performing ion implantation/anneal processes on the gate electrode|
One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that allows implantation of ions into the gate electrode but not into areas of the active region where source/drain regions for the transistor will be formed, performing a gate ion implantation process to form a gate ion implant region in the gate electrode and performing an anneal process. An n-type transistor including sidewall spacer structures positioned adjacent a gate structure, a plurality of source/drain regions for the transistor and a gate implant region positioned in a gate electrode, wherein the gate implant region is comprised of ions of phosphorous, arsenic or an implant material with an atomic size that is equal to or greater than the atomic size of phosphorous at a concentration level that falls within the range of 5e18-5e21 ions/cm3..
|Nonvolatile semiconductor storage device and method of manufacturing the same|
A nonvolatile semiconductor storage device includes a semiconductor substrate; a first insulating film disposed above the semiconductor substrate; a first electrode film disposed above the first insulating film; a second insulating film disposed above the first electrode film; a second electrode film disposed above the second insulating film; a third electrode film filling a first trench and overlying the second electrode film, the first trench having a first width and a first depth and extending through the second electrode film and the second insulating film and into the first electrode film; and a first barrier metal film and a first metal film disposed above the third electrode film; wherein the third electrode film above the second electrode film has a first thickness equal to or less than ½ of the first width of the first trench.. .
|Mim capacitor in finfet structure|
A finfet structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride on the sides and horizontal surface of the silicon fins; a polysilicon gate layer over the second layer of titanium nitride on the silicon fins and over the semiconductor substrate such that first and second ends of the silicon fins protrude from the polysilicon layer; spacers adjacent to the polysilicon gate layer; epitaxial silicon over the first and second ends of the silicon fins to form sources and drains, wherein the combination of the first layer of titanium nitride, dielectric layer and second layer of titanium nitride forms a metal-insulator-metal capacitor situated between each silicon fin and the polysilicon layer.. .
|Mim capacitor in finfet structure|
A method of forming a finfet structure having a metal-insulator-metal capacitor. Silicon fins are formed on a semiconductor substrate followed by formation of the metal-insulator-metal capacitor on the silicon fins by depositing sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride.
|Integrated circuits and methods for fabricating integrated circuits having metal gate electrodes|
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a sacrificial gate structure over a semiconductor substrate.
A semiconductor device includes a semiconductor substrate and a first electrode. An element region, and a non-element region that surrounds this element region, are formed on the semiconductor substrate.
|Igbt and method of manufacturing the same|
An igbt has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region..
|High voltage electrostatic discharge protection device|
An electrostatic discharge protection device is provided. The electrostatic discharge protection device can include a semiconductor substrate having a first well and a second well, a silicon controller rectifier (scr) device, and first and second impurity areas disposed on the first and second wells to form a pn junction.
|Memory device using graphene as charge-trap layer and method of operating the same|
A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges..
|Light-receiving device, light receiver using same, and method of fabricating light-receiving device|
An apparatus includes a flip-chip semiconductor substrate, a light detection element configured to be formed over the flip-chip semiconductor substrate and to have a laminate structure including a first semiconductor layer of a first-conductive-type, a light-absorption layer formed over the first semiconductor layer, and a second semiconductor layer of a second-conductive-type formed over the light-absorption layer, an inductor configured to be connected to the light detection element over the flip-chip semiconductor substrate, an output electrode for bump connection configured to output a current generated by the light detection element through the inductor, a bias electrode for bump connection configured to apply a bias voltage to the light detection element through a bias electrode, and a line configured to cause a metal line of the inductor and the light detection element to be connected to the output electrode or the bias electrode.. .