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Semiconductor Substrate patents



      
           
This page is updated frequently with new Semiconductor Substrate-related patent applications. Subscribe to the Semiconductor Substrate RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Substrate RSS RSS


Method of scavenging impurities in forming a gate stack having an interfacial layer

Method of scavenging impurities in forming a gate stack having an interfacial layer

Semiconductor device fabricating method

Semiconductor device fabricating method

Semiconductor device fabricating method

Semiconductor device and method for manufacturing same

Date/App# patent app List of recent Semiconductor Substrate-related patents
10/23/14
20140315371
 Methods of forming isolation regions for bulk finfet semiconductor devices patent thumbnailMethods of forming isolation regions for bulk finfet semiconductor devices
One method disclosed herein includes forming a plurality of fin-formation trenches in a semiconductor substrate that define a plurality of spaced-apart fins, forming a patterned liner layer that covers a portion of the substrate positioned between the fins while exposing portions of the substrate positioned laterally outside of the patterned liner layer, and performing at least one etching process on the exposed portions of the substrate through the patterned liner layer to define an isolation trench in the substrate, wherein the isolation trench has a depth that is greater than a depth of the fin-formation trenches.. .
10/23/14
20140315360
 Method of scavenging impurities in forming a gate stack having an interfacial layer patent thumbnailMethod of scavenging impurities in forming a gate stack having an interfacial layer
A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a gate stack disposed over a semiconductor substrate includes an interfacial dielectric layer disposed over the semiconductor substrate, a high-k dielectric layer disposed over the interfacial dielectric layer, a first conductive layer disposed over the high-k dielectric layer, and a second conductive layer disposed over the first conductive layer.
10/23/14
20140315352
 Semiconductor device fabricating method patent thumbnailSemiconductor device fabricating method
A semiconductor device fabricating method includes forming device chip regions and a monitor chip region for processing management, on a substrate surface layer on one main surface side of a semiconductor substrate wafer, each device chip region having an active region and an edge region; after forming metal films on front surface of the device chip regions and the monitor chip region by vapor deposition and photolithography, forming protective films on the front surfaces of the device chip regions and monitor chip region; and grinding and polishing another main surface side of the semiconductor substrate wafer to thin the semiconductor substrate wafer. A difference between an area of one chip occupied by the protective film of the monitor chip region and an area of one chip occupied by the protective film of the device chip region is 20% or less..
10/23/14
20140312506
 Semiconductor device and method for manufacturing same patent thumbnailSemiconductor device and method for manufacturing same
A semiconductor device includes a semiconductor substrate including a first surface in which an integrated circuit and an i/o pad electrically connected to the integrated circuit are formed, and a second surface which is an opposite side to the first surface, where a two-stage through-hole is formed in the semiconductor substrate, the semiconductor substrate including a first shape portion having a tapered shape which has a wall surface and of which a diameter of an opening becomes smaller toward a bottom of the hole from the second surface side to a predetermined position of the semiconductor substrate in a thickness direction, and including a second shape portion having a cylindrical shape which extends from the first shape portion to the i/o pad on the first surface side, and that includes an inorganic insulating film which is formed on the wall surface of the two-stage through-hole and the second surface.. .
10/23/14
20140312494
 Wafer backside interconnect structure connected to tsvs patent thumbnailWafer backside interconnect structure connected to tsvs
An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via.
10/23/14
20140312470
 Seal ring structure with capacitor patent thumbnailSeal ring structure with capacitor
A semiconductor device includes a semiconductor substrate of a first conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate.
10/23/14
20140312469
 Laser-based material processing methods and systems patent thumbnailLaser-based material processing methods and systems
Various embodiments may be used for laser-based modification of target material of a workpiece while advantageously achieving improvements in processing throughput and/or quality. Embodiments of a method of processing may include focusing and directing laser pulses to a region of the workpiece at a pulse repetition rate sufficiently high so that material is efficiently removed from the region and a quantity of unwanted material within the region, proximate to the region, or both is reduced relative to a quantity obtainable at a lower repetition rate.
10/23/14
20140312462
 Semiconductor device patent thumbnailSemiconductor device
A first impurity diffusion region is provided within a semiconductor substrate, a second impurity diffusion region is provided within the first impurity diffusion region, a third impurity diffusion region is provided within the second impurity diffusion region, a first portion of a fourth impurity diffusion region is provided within the second impurity diffusion region so as to be spaced from the third impurity diffusion region, and a second portion of the fourth impurity diffusion region is provided in a third portion of the first impurity diffusion region on a side of a surface of the semiconductor substrate, a first contact is provided so as to be in contact with the second portion, the first contact and the third portion overlap in plan view, and a first power supply is connected to the third impurity diffusion region.. .
10/23/14
20140312461
 Defective p-n junction for backgated fully depleted silicon on insulator mosfet patent thumbnailDefective p-n junction for backgated fully depleted silicon on insulator mosfet
Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket.
10/23/14
20140312457
 Integrated circuit chip with discontinuous guard ring patent thumbnailIntegrated circuit chip with discontinuous guard ring
An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit.
10/23/14
20140312451
Solid-state imaging element, manufacturing method, and electronic device
A solid-state imaging element includes a pixel having a photoelectric conversion section and a side pinning layer. The photoelectric conversion section is formed in a semiconductor substrate.
10/23/14
20140312449
Lateral avalanche photodiode device and method of production
A lateral avalanche photodiode device comprises a semiconductor substrate (1) having a trench (4) with side walls (5) extending from a main surface (2) to a rear surface (3). A first doped region (11) is present at the side walls of the trench, and a second doped region (12) is arranged at a distance from the first doped region.
10/23/14
20140312444
Solid-state imaging device, production method of the same, and imaging apparatus
A solid-state imaging device in which a pixel circuit formed on the first surface side of a semiconductor substrate is shared by a plurality of light reception regions and second surface side of the semiconductor substrate is the light incident side of the light reception regions. The second surface side regions of the light reception regions are arranged at approximately even intervals and the first surface side regions of the light reception regions e are arranged at uneven intervals.
10/23/14
20140312440
Semiconductor device and manufacturing method thereof
An object of the present invention is to suppress an error in the value detected by a pressure sensor, which may be caused when environmental temperature varies. A semiconductor substrate has a first conductivity type.
10/23/14
20140312430
Semiconductor devices and methods of fabricating the same
A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate..
10/23/14
20140312428
Epitaxial replacement of a raised source/drain
Disclosed is a semiconductor article which includes a semiconductor substrate; a plurality of gate structures having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain adjacent to each of the gate structures, the raised source/drain filling the faceted space and having a surface parallel to the semiconductor substrate. At least one gate structure of the plurality of gate structures is for an nfet and at least one gate structure of the plurality of gate structures is for a pfet..
10/23/14
20140312417
Semiconductor device and method of manufacturing a semiconductor device
A semiconductor device formed in a semiconductor substrate includes an isolation trench in the semiconductor substrate to laterally insulate adjacent components of the semiconductor device. A lateral isolation layer is disposed in the isolation trench.
10/23/14
20140312415
Semiconductor device and manufacturing method therefor
A semiconductor device includes: a semiconductor substrate including a first surface; a body region positioned in the semiconductor substrate and positioned to be in contact with the first surface; a gate insulating film positioned to be in contact with the body region on the first surface; a gate electrode positioned on the gate insulating film; a first insulator film covering at least a portion of a side surface of the gate electrode; a contact region positioned to be in contact with the first surface at a position different from that of the gate electrode, in a plan view relative to the first surface, in the body region; and a second insulator film including a material different from that of the first insulator film, positioned on the body region, the gate electrode, and the first insulator film, and including a contact hole on the contact region.. .
10/23/14
20140312404
Non-volatile memory device integrated with cmos soi fet on a single chip
A structure and method provided for integrating soi cmos fets and nvram memory devices. The structure includes a soi substrate containing a semiconductor substrate, a soi layer, and a box layer formed between the semiconductor substrate and the soi layer.
10/23/14
20140312401
Memory cell having a recessed gate and manufacturing method thereof
A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region.
10/23/14
20140312383
Power semiconductor device and method of manufacturing the same
A power semiconductor device may include: abase substrate including a first conductive type drift layer; a second conductive type semiconductor substrate disposed on the other surface of the base substrate; a first conductive type diffusion layer disposed in the base substrate and having an impurity concentration higher than that of the drift layer; a second conductive type well layer disposed inside of one surface of the base substrate; a trench formed from one surface of the base substrate including the well layer so as to penetrate through the diffusion layer in a depth direction; a first insulation film disposed on a surface of the base substrate; and a first electrode disposed in the trench. A peak point of an impurity doping concentration of the diffusion layer in a transverse direction may be positioned in a region contacting a side surface of the trench..
10/23/14
20140312382
Power device and method of manufacturing the same
Provided are a power device having an improved field stop layer and a method of manufacturing the same. The power device includes: a first field stop layer formed of a semiconductor substrate and of a first conductive type; a second field stop layer formed on the first field stop layer and of the first conductive type, the second field stop layer having a region with an impurity concentration higher than the first field stop layer; a drift region formed on the second field stop layer and of the first conductive type, the drift region having an impurity concentration lower than the first field stop layer; a plurality of power device cells formed on the drift region; and a collector region formed below the first field stop layer, wherein the second field stop layer includes a first region having a first impurity concentration and a second region having a second impurity concentration higher than the first impurity concentration..
10/23/14
20140312381
Nanoelectronic structure and method of producing such
The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement.
10/23/14
20140312359
Method for bonding semiconductor substrates
A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate..
10/23/14
20140312356
Semiconductor device
A semiconductor device and a method of making the same. The device includes a semiconductor substrate.
10/23/14
20140312334
Organic electroluminescent display device
An organic el display device of active matrix type wherein insulated-gate field effect transistors formed on a single-crystal semiconductor substrate are overlaid with an organic el layer; characterized in that the single-crystal semiconductor substrate (413 in fig. 4) is held in a vacant space (414) which is defined by a bed plate (401) and a cover plate (405) formed of an insulating material, and a packing material (404) for bonding the bed and cover plates; and that the vacant space (414) is filled with an inert gas and a drying agent, whereby the organic el layer is prevented from oxidizing..
10/23/14
20140311567
Solar cell and method for manufacturing the same
A solar cell includes a semiconductor substrate, a tunneling layer on one surface of the semiconductor substrate, a first conductive type area on the tunneling layer, a second conductive type area on the tunneling layer such that the second conductive type area is separated from the first conductive type area, and a barrier area interposed between the first conductive type area and the second conductive type area such that the barrier area separates the first conductive type area from the second conductive type area.. .
10/23/14
20140311562
Solar cell
Disclosed is a solar cell including a semiconductor substrate, an emitter layer formed at the semiconductor substrate, the emitter layer being a conductive type different from that of the semiconductor substrate, a back surface field layer formed at the semiconductor substrate, the back surface field layer being the same conductive type as that of the semiconductor substrate, a first electrode electrically connected to the emitter layer, and a second electrode electrically connected to the back surface field layer. The second electrode includes a plurality of finger electrodes arranged at a first pitch, the back surface field layer includes a plurality of first portions corresponding to the respective finger electrodes, and at least one connecting projection protrudes from any one of each finger electrode and each first portion..
10/23/14
20140311558
Solar cell and method for manufacturing the same
A solar cell includes a semiconductor substrate containing impurities of a first conductive type, a back surface field region which is positioned on a back surface of the semiconductor substrate and is doped more than the semiconductor substrate with impurities of the first conductive type, an emitter region which is on the back surface of the semiconductor substrate adjacent to the back surface field region and contains impurities of a second conductive type different than the first conductive type, a metal layer which contains impurities of the second conductive type and on a back surface of the emitter region, a back passivation layer exposing a portion of the back surface field region and a portion of the metal layer.. .
10/23/14
20140311249
Semiconductor pressure sensor, pressure sensor apparatus, electronic equipment, and method of manufacturing semiconductor pressure sensor
A semiconductor pressure sensor (720) includes a thin film piezoelectric element (701) which applies strain to a portion of a semiconductor substrate that corresponds to a thin region (402). The thin film piezoelectric element (701) is formed at a distance away from diffusion resistors (406, 408, 410, and 412) functioning as strain gauges and is extended to the proximity of a bonding pad (716a) connected to an upper electrode layer of the thin film piezoelectric element and a bonding pad (716f) connected to a lower electrode thereof.
10/16/14
20140308819
Method of producing semiconductor substrate product, and etching method to be used therein
A method of producing a semiconductor substrate product, the method containing: a step of preparing an aqueous solution containing 7% by mass or more and 25% by mass or less of a quaternary alkyl ammonium hydroxide; a step of preparing a semiconductor substrate having a silicon film comprising a polycrystalline silicon film or an amorphous silicon film; and a step of heating the aqueous solution at 80° c. Or higher and applying the resultant aqueous solution onto the semiconductor substrate to etch at least a part of the silicon film..
10/16/14
20140308798
Multiple-time programming memory cells and methods for forming the same
A method includes forming shallow trench isolation (sti) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the sti regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region.
10/16/14
20140308786
High-integration semiconductor memory device and method of manufacturing the same
A semiconductor memory device includes a semiconductor substrate, an active region including a plurality of unit active regions and disposed over and spaced from the semiconductor substrate, a pair of word lines formed on a top surface and sides of the unit active region, a dummy word line disposed at a contact of the unit active regions and formed on top surfaces and sides of the unit active regions, a source region in the unit active region between the pair of word lines and electrically connected to the semiconductor substrate, drain regions formed in the unit active region between the pair of word lines and the dummy word line, and first storage layers formed on the drain regions and electrically connected to the drain regions.. .
10/16/14
20140308783
Semiconductor device and method of manufacturing semiconductor device
A first transistor includes a first impurity layer of a first conduction type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, a first gate electrode formed above the first gate insulating film, and first source/drain regions of a second conduction type formed in the first epitaxial semiconductor layer and in the semiconductor substrate in the first region. A second transistor includes a second impurity layer of the first conduction type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and being thinner than the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer, a second gate electrode formed above the second gate insulating film, and second source/drain regions of the second conduction type formed in the second epitaxial semiconductor layer and in the semiconductor substrate in the second region..
10/16/14
20140307151
Solid-state image sensor and camera
The solid-state image sensor includes image sensing pixels, first and second focus detection pixels configured to respectively detect lights passing through different regions of a pupil of an image sensing lens. The sensor includes a semiconductor substrate including photoelectric converters of the image sensing pixels, a photoelectric converter and a first well contact region of the first focus detection pixel, and a photoelectric converter and a second well contact region of the second focus detection pixel, a first contact plug electrically connected to the first well contact region, and a second contact plug electrically connected to the second well contact region.
10/16/14
20140306701
Vertical hall sensor circuit comprising stress compensation circuit
A vertical hall sensor circuit comprises an arrangement comprising a vertical hall effect region of a first doping type, formed within a semiconductor substrate and having a stress dependency with respect to a hall effect-related electrical characteristic. The vertical hall sensor circuit further comprises a stress compensation circuit which comprises at least one of a lateral resistor arrangement and a vertical resistor arrangement.
10/16/14
20140306354
Semiconductor package
A semiconductor package includes a package substrate. A first semiconductor chip is mounted on the package substrate.
10/16/14
20140306352
Semiconductor device and fabrication method
Various embodiments provide semiconductor devices and fabrication methods. In an exemplary method, a dielectric layer can be formed on a semiconductor substrate.
10/16/14
20140306345
Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same
A semiconductor device includes a first interconnect formed over the semiconductor substrate. An interlayer dielectric film is formed over the first interconnect, and a hole is formed in the interlayer dielectric film such that the hole reaches the first interconnect.
10/16/14
20140306342
Semiconductor device, having through electrodes, a manufacturing method thereof, and an electronic apparatus
A semiconductor device includes a semiconductor substrate and a through electrode provided in a through hole formed in the semiconductor substrate. The through electrode partially protrudes from a back surface of the semiconductor substrate, which is opposite to an active surface thereof.
10/16/14
20140306339
Semiconductor device and manufacturing method of semiconductor device
A semiconductor device has a semiconductor substrate having a first surface and a second surface, a through electrode penetrating through the semiconductor substrate and having a protrusion protruding from the second surface, and an insulation layer on the second surface, which covers the side surface of the protrusion, has an opening through which to expose the end surface of the protrusion, and has a thickness greater than the length of the protrusion.. .
10/16/14
20140306319
Semiconductor device and manufacturing method thereof
There are included: forming element isolation regions in a semiconductor substrate; introducing a first impurity of a first conductivity type, to thereby form a first well, and a second well of the first conductivity type; introducing a second impurity of a second conductivity type, to thereby form a third well of the second conductivity type and introducing the second impurity into a region between the first well and the second well, to thereby form a separation well of the second conductivity type; and further introducing a third impurity of the second conductivity type into the region between the first well and the second well.. .
10/16/14
20140306318
Trench formation method and a semiconductor structure thereof
In one embodiment, a method of making a trench for a semiconductor device can include: (i) providing a semiconductor substrate; (ii) forming a patterned hard mask layer with an opening on the semiconductor substrate, where a thickness of the patterned hard mask layer is from about 100 nm to about 400 nm; and (iii) using the patterned hard mask layer as a mask, and etching the semiconductor substrate to form the trench in the semiconductor substrate.. .
10/16/14
20140306317
Finfet fin height control
Fin height control techniques for finfet fabrication are disclosed. The technique includes a method for controlling the height of plurality of fin structures to achieve uniform height thereof relative to a top surface of isolation material located between fin structures on a semiconductor substrate.
10/16/14
20140306316
Semiconductor device and method of manufacturing the same
In one embodiment, a method of manufacturing a semiconductor device includes sequentially forming a first insulator, a second insulator, and a sacrificial layer on a semiconductor substrate, and forming plural core materials from the sacrificial layer and the second insulator. The method further includes forming first and second interconnects on side surfaces of each core material to form plural first interconnects and plural second interconnects alternately, each first interconnect having a first side surface in contact with a core material and a second side surface positioned on an opposite side of the first side surface, and each second interconnect having a third side surface in contact with a core material and a fourth side surface positioned on an opposite side of the third side surface.
10/16/14
20140306309
Photoelectric conversion apparatus
A photoelectric conversion apparatus includes a semiconductor substrate having a photoelectric conversion portion. An insulator is provided on the semiconductor substrate.
10/16/14
20140306294
Gap fill self planarization on post epi
The present disclosure relates to an integrated chip ic having transistors with structures separated by a flowable dielectric material, and a related method of formation. In some embodiments, an integrated chip has a semiconductor substrate and an embedded silicon germanium (sige) region extending as a positive relief from a location within the semiconductor substrate to a position above the semiconductor substrate.
10/16/14
20140306293
Semiconductor memory device including guard band
The semiconductor memory device including a first sense amplifier region including first metal-oxide-semiconductor (mos) transistors disposed in a well on a semiconductor substrate, a second sense amplifier region adjacent to the well and including second mos transistors disposed on the semiconductor substrate, a guard band having a bar type structure and provided between the first mos transistors in the well, and a guard ring partially or fully enclosing the second sense amplifier region in the semiconductor substrate may be provided.. .
10/16/14
20140306292
Semiconductor device and method of manufacturing semiconductor device
A first transistor includes a first impurity layer of a first conduction type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, a first gate electrode formed above the first gate insulating film, and first source/drain regions of a second conduction type formed in the first epitaxial semiconductor layer and in the semiconductor substrate in the first region. A second transistor includes a second impurity layer of the first conduction type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and being thinner than the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer, a second gate electrode formed above the second gate insulating film, and second source/drain regions of the second conduction type formed in the second epitaxial semiconductor layer and in the semiconductor substrate in the second region..
10/16/14
20140306289
Self-aligned structure for bulk finfet
A finfet structure which includes a bulk semiconductor substrate; semiconductor fins extending from the bulk semiconductor substrate, each of the semiconductor fins having a top portion and a bottom portion such that the bottom portion of the semiconductor fins is doped and the top portion of the semiconductor fins is undoped; a portion of the bulk semiconductor substrate directly underneath the plurality of semiconductor fins being doped to form an n+ or p+ well; and an oxide formed between the bottom portions of the fins. Also disclosed is a method for forming a finfet device..
10/16/14
20140306287
Semiconductor device and fabrication method thereof
A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a local silicon-on-insulator (soi) substrate in which a portion of a line-shaped active region is connected to a semiconductor substrate, and a remaining portion thereof is insulated from the semiconductor substrate, gate structures formed in a line shape to be substantially perpendicular to the active region on the active region insulated from the semiconductor substrate, and to surround a side and an upper surface of the active region, and having a stacking structure of a gate insulating layer, a liner conductive layer, a gate conductive layer, and a hard mask layer, a source region formed in the active region connected to the semiconductor substrate, and a drain region formed in the active region insulated from the semiconductor substrate between the gate structures..
10/16/14
20140306284
Semiconductor device and method for producing the same
A trench gate mos transistor is provided. It includes a semiconductor substrate with a trench including a gate electrode, a source region, a body contact region adjacent to a channel region, wherein the dopant concentration in the channel region varies in a lateral direction and has at least one minimal value in a direction from the gate electrode to the body contact region, which is distanced from the gate electrode.
10/16/14
20140306281
Nonvolatile semiconductor storage device and method for manufacturing the same
According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.. .
10/16/14
20140306277
Semiconductor storage device
A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate.
10/16/14
20140306276
Solid-state imaging device and imaging apparatus
The solid-state imaging device includes a semiconductor layer 11 in which a surface side becomes a circuit formation surface, photoelectric conversion units pd1 and pd2 of two layers or more that are stacked and formed in the semiconductor layer 11, and a longitudinal transistor tr1 in which a gate electrode 21 is formed to be embedded in the semiconductor layer 11 from a surface 15 of the semiconductor layer 11. The photoelectric conversion unit pd1 of one layer in the photoelectric conversion units of the two layers or more is formed over a portion 21a of the gate electrode 21 of the longitudinal transistor tr1 embedded in the semiconductor substrate 11 and is connected to a channel formed by the longitudinal transistor tr1..
10/16/14
20140306274
Self-aligned structure for bulk finfet
A finfet structure which includes a bulk semiconductor substrate; semiconductor fins extending from the bulk semiconductor substrate, each of the semiconductor fins having a top portion and a bottom portion such that the bottom portion of the semiconductor fins is doped and the top portion of the semiconductor fins is undoped; a portion of the bulk semiconductor substrate directly underneath the plurality of semiconductor fins being doped to form an n+ or p+ well; and an oxide formed between the bottom portions of the fins.. .
10/16/14
20140306271
Unltra-shallow junction semiconductor field-effect transistor and method of making
An ultra-shallow junction semiconductor field-effect transistor and its methods of making are disclosed. In the present disclosure, a mixture film is formed on a semiconductor substrate with a gate structure formed thereon using a physical vapor deposition (pvd) process, which employs a mixture of metal and semiconductor dopants as a target.
10/16/14
20140306267
Semiconductor device and method for manufacturing the same
A semiconductor device including a semiconductor substrate in which a diode region and an igbt region are formed is provided. In the semiconductor device, the diode region includes a second conductivity type cathode layer.
10/16/14
20140306239
Semiconductor device
A semiconductor device includes a first conduction type semiconductor substrate, a first conduction type semiconductor deposition layer, a trench, second conduction type wells, a jfet region, a first conduction type first source region, a first source region, a trench-type source electrode, a gate insulator film, a gate electrode, and a drain electrode. The trench is formed substantially perpendicularly to the semiconductor deposition layer so that the semiconductor deposition layer exposes to a bottom of the trench.
10/16/14
20140305812
Method for analyzing a gas
A method for analyzing a gas includes measuring a concentration of a chemical species of the gas in a measuring space of a gas sensor. The gas sensor has a semiconductor substrate with an electrical circuit and a first thin-film ion conductor that separates a reference space for a reference gas from the measuring space for the gas.
10/16/14
20140305504
Solar cell
A high voltage output solar cell which is small in size and high in power generation efficiency is provided. The solar cell is provided with a p-type or n-type monocrystalline semiconductor substrate (1) forming a power generation layer, a plurality of hole collecting layers (2), electron collecting layers (3), and grooves (7) provided inside of the semiconductor substrate (1) contiguous to a back surface which faces a light receiving surface of the semiconductor substrate (1), hole collecting layers (2) and electron collecting layers (3) being provided between adjoining grooves (7) and hole collecting layers (2) and electron collecting layers (3) being provided sandwiching grooves (7), and interconnect layers (8) which connect hole collecting layers (2) and electron collecting layers (3) sandwiching grooves (7), the grooves (7) being formed from the back surface side toward the inside of semiconductor substrate (1)..
10/16/14
20140304990
Heating system and method for microfluidic and micromechanical applications
An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port.
10/09/14
20140303919
Photoinduced carrier lifetime measurement device and photoinduced carrier lifetime measurement method
A photoinduced carrier lifetime measurement device includes light sources that respectively apply light that differs in wavelength and generates photoinduced carriers to a semiconductor substrate, a microwave generation section that generates microwaves that are applied to the semiconductor substrate, a detection section that detects the intensity of the microwaves that have passed through the semiconductor substrate, and a calculation section that calculates the effective carrier lifetime corresponding to the wavelength of each light based on the intensity of the microwaves detected when applying each light, and calculates the bulk carrier lifetime and a surface recombination velocity of the semiconductor substrate based on the effective carrier lifetime calculated corresponding to the wavelength of each light.. .
10/09/14
20140303776
Apparatus and method for detecting position drift in a machine operation using a robot arm
In an example embodiment, apparatus for detecting position drift in a machine operation using a robot arm, the robot arm being for operation on a semiconductor substrate, the robot arm and the semiconductor substrate being configured for relative movement therebetween, the apparatus includes an input for receiving an input signal from a sensor mounted on the robot arm; a detector for detecting, from the input signal, a detection of there being a predefined distance between the robot arm and the semiconductor substrate; wherein the apparatus is configured to determine, from the detection, whether there has been position drift.. .
10/09/14
20140302681
Internal plasma grid for semiconductor fabrication
The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers.
10/09/14
20140302680
Internal plasma grid for semiconductor fabrication
The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers.
10/09/14
20140302678
Internal plasma grid applications for semiconductor fabrication
The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers.
10/09/14
20140302668
Semiconductor device and manufacturing method thereof
An improvement is achieved in the performance of semiconductor device including a nonvolatile memory. In a split-gate nonvolatile memory, between a memory gate electrode and a p-type well and between a control gate electrode and the memory gate electrode, an insulating film is formed.
10/09/14
20140302655
Non-volatile memory device with vertical memory cells and method for fabricating the same
A non-volatile memory device includes a plurality of gate electrodes stacked over a semiconductor substrate and stretched in a first direction along the semiconductor substrate and a plurality of junction layers having a first region protruding from the semiconductor substrate and crossing the gate electrodes and a second region formed between the gate electrodes.. .
10/09/14
20140302651
Method for manufacturing semiconductor device with first and second gates over buried bit line
A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device.
10/09/14
20140302646
Method of manufacturing semiconductor device
A performance and reliability of a semiconductor device are improved. On a semiconductor substrate, a gate electrode for a first misfet and a dummy gate electrode for a second misfet are formed, and then, an insulating film is partially formed on the gate electrode.
10/09/14
20140302628
Optical semiconductor device and method of manufacturing optical semiconductor device
A method of manufacturing an optical semiconductor device including: forming a mesa structure including a first conductivity type cladding layer, an active layer and a second conductivity type cladding layer in this order on a first conductivity type semiconductor substrate, an upper most surface of the mesa structure being constituted of an upper face of the second conductivity type cladding layer; growing a first burying layer burying both sides of the mesa structure at higher position than the active layer; forming an depressed face by etching both edges of the upper face of the second conductivity type cladding layer; and growing a second burying layer of the first conductivity type on the depressed face of the second conductivity type cladding layer and the first burying layer.. .
10/09/14
20140302620
Method for manufacturing solar cell
A method for manufacturing a solar cell capable of significantly reducing the amount of wastewater generated during a wet-etching process and improving the efficiency of the solar cell. A method comprising: texturing to form an uneven structure on one semiconductor substrate surface by etching the semiconductor substrate surface with a texturing device; forming a temporary layer at an upper portion of the semiconductor substrate surface to surround a first byproduct layer formed at a predetermined region of the semiconductor substrate surface during the texturing; and doping the semiconductor substrate surface with a predetermined dopant using a doping device to form a first semiconductor layer and a second semiconductor layer disposed above the first semiconductor layer and having a different polarity than the first semiconductor layer.


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Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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