|| List of recent Semiconductor Substrate-related patents
| Texturing of monocrystalline semiconductor substrates to reduce incident light reflectance|
Monocrystalline semiconductor substrates are textured with alkaline solutions to form pyramid structures on their surfaces to reduce incident light reflectance and improve light absorption of the wafers. The alkaline baths include hydantoin compounds and derivatives thereof in combination with alkoxylated glycols to inhibit the formation of flat areas between pyramid structures to improve the light absorption..
| Protective coating for a plasma processing chamber part and a method of use|
A flexible polymer or elastomer coated rf return strap to be used in a plasma chamber to protect the rf strap from plasma generated radicals such as fluorine and oxygen radicals, and a method of processing a semiconductor substrate with reduced particle contamination in a plasma processing apparatus. The coated rf strap minimizes particle generation and exhibits lower erosion rates than an uncoated base component.
| High performance on-chip vertical coaxial cable, method of manufacture and design structure|
A high performance on-chip vertical coaxial cable structure, method of manufacturing and design structure thereof is provided. The coaxial cable structure includes an inner conductor and an insulating material that coaxially surrounds the inner conductor.
| Method of forming nonvolatile memory device|
A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.. .
| Manufacturing method of semiconductor device and semiconductor manufacturing apparatus|
According to one embodiment, a manufacturing method of a semiconductor device includes forming a crystal film on a semiconductor substrate by irradiating the semiconductor substrate with a first microwave, obtained by providing frequency modulation or phase modulation of a first carrier wave which is a sine wave with a first frequency, using a first signal wave which is a sine wave or a pulse wave with a third frequency lower than a first frequency, and irradiating the semiconductor substrate with a second microwave, obtained by providing frequency modulation or phase modulation of a second carrier wave, which is a sine wave with a second frequency higher than the first frequency, using a second signal wave which is a sine wave or a pulse wave with a fourth frequency lower than the second frequency.. .
| Group iii-v substrate material with particular crystallographic features and methods of making|
A method of forming a semiconductor substrate including providing a base substrate including a semiconductor material, and forming a first semiconductor layer overlying the base substrate having a group 13-15 material via hydride vapor phase epitaxy (hvpe), the first semiconductor layer having an upper surface having a n-face orientation.. .
| Allotropic or morphologic change in silicon induced by electromagnetic radiation for resistance turning of integrated circuits|
An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region.
| Large dimension device and method of manufacturing same in gate last process|
An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a capacitor having a doped region disposed in a semiconductor substrate, a dielectric layer disposed over the doped region, and an electrode disposed over the dielectric layer.
| Low loss sic mosfet|
A vertical multiple implanted silicon carbide power mosfet (vmimosfet) includes a first conductivity semiconductor substrate, a first conductivity semiconductor drift layer on the top of the substrate, a multitude of second conductivity layers implanted in the drift layer. The body layer is where the channel is formed.
| Fabrication method for semiconductor devices|
A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon.
| Chip package and fabrication method thereof|
An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region; and an auxiliary pattern having a hollow pattern formed in the spacing layer, a material pattern located between the spacing layer and the device region, or combinations thereof.. .
| Method for manufacturing solar cell|
A method for manufacturing a solar cell includes performing a dry etching process to form a textured surface including a plurality of minute protrusions on a first surface of a semiconductor substrate, performing a first cleansing process for removing damaged portions of surfaces of the minute protrusions using a basic chemical and removing impurities adsorbed on the surfaces of the minute protrusions, performing a second cleansing process for removing impurities remaining or again adsorbed on the surfaces of the minute protrusions using an acid chemical after performing the first cleansing process, and forming an emitter region at the first surface of the semiconductor substrate.. .
| Method of manufacturing solid-state image sensor|
A method of manufacturing a solid-state image sensor having a pixel region and a peripheral circuit region, includes forming an oxide film on a semiconductor substrate, forming an insulating film on the oxide film, forming a first opening in the insulating film and the oxide film in the peripheral circuit region, forming a trench in the semiconductor substrate in the peripheral circuit region by etching the semiconductor substrate through the first opening using the insulating film as a mask, forming a second opening in the insulating film to penetrate through the insulating film in the pixel region and to reach a predetermined depth of the oxide film, and forming insulators in the trench and the second opening.. .
| Leakage measurement of through silicon vias|
A method of testing a semiconductor substrate having through substrate vias for current leakage which includes: forming a current leakage measurement structure that includes substrate contacts, sensing circuits to sense current leakage from the through substrate vias, the sensing circuits connected to the through substrate vias and to the substrate contacts so that there is a one-to-one correspondence of a substrate contact and sensing circuit to each through substrate via, and a built-in self test (bist) engine to sense one of the through substrate vias for current leakage. A reference current is applied to the sensing circuits to set a current leakage threshold for the through substrate vias.
| Chuck and semiconductor process using the same|
An apparatus of semiconductor process including a chuck and a vacuum source is provided. The chuck has a plurality of holes for holding a semiconductor substrate, and the vacuum source is used for providing vacuum suction through the holes to make the semiconductor substrate be subjected to varied suction intensities according to a warpage level thereof..
| Semiconductor memory device and method of operating the same|
A semiconductor memory device and a method of manufacturing the same are provided. The device includes a memory block and one or more peripheral circuits.
| Semiconductor device having buried gate, method of fabricating the same, and module and system having the same|
A semiconductor device includes junction regions formed in upper portions of both sidewalls of a trench formed in a semiconductor substrate, a first gate electrode buried in the trench and having a stepped upper surface, and a second gate electrode formed on the first gate electrode to overlap a junction region.. .
| Nonvolatile semiconductor memory device and operating method of the same|
According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, and a memory cell which is arranged on the semiconductor substrate and comprises a variable resistance element. The variable resistance element comprises a laminated structure including a phase-change element which has at least two different crystalline resistance states by varying a crystalline state, and a magnetoresistive element which has at least two different magnetization resistance states by varying a magnetization state, and applies or does not apply a magnetic field to the phase-change element in accordance with the magnetization state..
| Methods for combining camera and projector functions in a single device|
Described are handheld devices with combined image capture and image projection functions. One embodiment includes modulating and capturing a light beam along the same optic path.
| Image pickup apparatus|
An image pickup apparatus in which a pixel area including arrangement of a plurality of pixels each having a photoelectric conversion portion and a common output portion for sequentially amplifying and outputting signals from the plurality of pixels included in the pixel area are formed on a single semiconductor substrate, comprises a power supply unit for effecting power supply control of the common output portion independently of control on power supply to the pixel area, and a control circuit for effecting control to supply no power to the common output portion in a predetermined period after starting photo charge accumulation in the photoelectric conversion portion and supply the power to the common output portion before the end of a photo charge accumulation period in the photoelectric conversion portion.. .
| Wiring defect inspecting method, wiring defect inspecting apparatus, and method for manufacturing semiconductor substrate|
A wiring defect inspecting method in accordance with the present invention comprises: obtaining a resistance of a short-circuited path of a semiconductor substrate; applying a voltage, which is specified on the basis of the resistance obtained, to the semiconductor substrate having a defect portion so as to cause the defect portion to generate heat; and capturing, with use of an infrared camera, an image of the semiconductor substrate whose temperature has increased due to the heat generated from the defect portion.. .
| Semiconductor devices having bit line contact plugs and methods of manufacturing the same|
A semiconductor device including active regions defined in a semiconductor substrate to be non-parallel with a first direction and a second direction which are perpendicular to each other, word lines intersecting active regions and extending in first directions to be spaced apart from each other in the second direction, bit lines crossing over word lines and extending in second directions to be spaced apart from each other in the first direction, first impurity regions disposed in respective ones of central portions of active regions to non-overlap with the word lines, second impurity regions disposed in both ends of each of the active regions to non-overlap with the word lines, and bit line contact plugs disposed between the first impurity regions and the bit lines. The bit line contact plugs having longish shapes including major axes substantially parallel with the second direction and minor axes substantially parallel with the first direction..
| Semiconductor device and manufacturing method thereof|
A semiconductor device according to the present embodiment includes a semiconductor substrate. A lower-layer wiring is provided above a surface of the semiconductor substrate.
| Semiconductor device|
A semiconductor device includes: a first insulating film formed on a semiconductor substrate; a first interconnect formed on the first insulating film; a second insulating film formed on the first insulating film to cover the first interconnect; and a second interconnect formed on the second insulating film. The second interconnect includes a barrier layer formed on the second insulating film, and a plated layer formed on the barrier layer.
| Semiconductor device and method for forming the same|
A semiconductor device includes a metal line and a metal pad formed at different integration levels of a semiconductor substrate, and an isolation layer by which the metal line and the metal pad are spaced apart from each other. The semiconductor device prevents short-circuiting between the metal pad and the metal line although the isolation layer is dislocated..
| Semiconductor structure|
A semiconductor structure includes a semiconductor substrate, a metal layer formed on the semiconductor substrate, a conductive pillar, and a solder ball. The conductive pillar is formed on and electrically connected with the metal layer, wherein the conductive pillar has a bearing surface and a horizontal sectional surface under the bearing surface, and the contact surface area of the bearing surface is larger than the area of the horizontal sectional surface.
| Semiconductor device and method for fabricating the same|
An exemplary semiconductor device comprises a through silicon via penetrating a semiconductor substrate including a circuit pattern on one side of the substrate, a first doped layer formed in the other side, and a bump connected with the through silicon via.. .
| Semiconductor device and method of manufacturing the same|
A semiconductor device includes a semiconductor substrate, an insulator film that is arranged above the semiconductor substrate, a first passivation film that is arranged above the insulator film, a second passivation film that is arranged above the first passivation film, a stress relaxation layer that is arranged above the second passivation film, an organic coated film that is arranged above the stress relaxation layer, and a resin layer that is arranged above the organic coated film, wherein a young's modulus of the stress relaxation layer is smaller than a young's modulus of the organic coated film, and is smaller than a young's modulus of the second passivation film.. .
| Semiconductor device and fabrication method|
Various embodiments provide semiconductor devices including high-k dielectric layer(s) and fabrication methods. An exemplary high-k dielectric layer can be formed by providing a semiconductor substrate including a first region and a second region, and forming a first silicon oxide layer on the semiconductor substrate in the first region.
| Method of manufacturing a semiconductor device and a semiconductor device|
A method of manufacturing a semiconductor device with an son structure having a thick cavity inside a semiconductor substrate is disclosed. The method forms a plurality of trenches with a predetermined distance between adjacent trenches.
| Semiconductor chip and semiconductor package having the same|
A semiconductor chip includes a semiconductor substrate having one surface, the other surface which faces away from the one surface, and an integrated circuit which is formed on the one surface; and a shielding layershielding layer formed in the semiconductor substrate to correspond to the other surface.. .
| Semiconductor substrate having crack preventing structure and method of manufacturing the same|
Disclosed herein is a semiconductor substrate having a crack preventing structure, the semiconductor substrate including: a plurality of wiring layers and a plurality of insulating layers sequentially stacked on a device divided into integrated circuit device areas and a cutting area separating the device areas from each other; opening parts formed to spatially separate the insulating layers in the device areas and the insulating layers in the cutting area from each other; and chamfering parts formed at outer sides of the insulating layers in the device areas contacting the opening parts, wherein the plurality of wiring layers are formed between the insulating layers in the cutting area and the device.. .
| Method for producing a semiconductor layer|
A method for producing a semiconductor layer is disclosed. One embodiment provides for a semiconductor layer on a semiconductor substrate containing oxygen.
| Semiconductor fin on local oxide|
A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate.
| Semiconductor device with diagonal conduction path|
A method of fabricating a bipolar transistor including emitter and base regions having first and second conductivity types, respectively, includes forming an isolation region at a surface of a semiconductor substrate, the isolation region having an edge that defines a boundary of an active area of the emitter region, and implanting dopant of the second conductivity type through a mask opening to form the base region in the semiconductor substrate. The mask opening spans the edge of the isolation region such that an extent to which the dopant passes through the isolation region varies laterally to establish a variable depth contour of the base region..
| Unbalanced parallel circuit protection fuse device|
In one general aspect, an apparatus can include a semiconductor substrate, and a first conductive fuse bus having a triangular-shaped portion with a bottom surface aligned along a plane substantially parallel to a surface of the semiconductor substrate. The apparatus can include a second conductive fuse bus having a bottom surface aligned along the plane, and a plurality of fuse links coupled between the triangular-shaped portion of the first conductive fuse bus and the second conductive fuse bus..
| Semiconductor device comprising a schottky barrier diode|
The present invention aims to enhance the reliability of a semiconductor device equipped with a schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto.
| Optical device|
An optical device includes a first region and an isolating layer which are each provided in a semiconductor substrate. The first region configures a photoelectric converter and includes at least an impurity of a first conductivity type.
| Multiple metal film stack in bsi chips|
A method includes forming an opening extending from a back surface of a semiconductor substrate to a metal pad on a front side of the semiconductor substrate, and forming a first conductive layer including a first portion overlapping active image sensors in the semiconductor substrate, a second portion overlapping black reference image sensors in the semiconductor substrate, and a third portion in the opening to contact the metal pad. A second conductive layer is formed over and contacting the first conductive layer.
| Manufacturing method for edge illuminated type photodiode and semiconductor wafer|
A manufacturing method for an edge illuminated type photodiode has: a process of forming an impurity-doped layer of a first conductivity type in each of device forming regions in a semiconductor substrate; a process of forming an impurity-doped layer of a second conductivity type in each of the device forming regions; a process of forming a trench extending in a direction of thickness of the semiconductor substrate from a principal surface, at a position of a boundary between adjacent device forming regions, by etching to expose side faces of the device forming regions; a process of forming an insulating film on the exposed side faces of the device forming regions; a process of forming an electrode for each corresponding impurity-doped layer on the principal surface side of the semiconductor substrate; and a process of implementing singulation of the semiconductor substrate into the individual device forming regions. .
| Multiple metal film stack in bsi chips|
A device includes a semiconductor substrate, a black reference circuit in the semiconductor substrate, a metal pad on a front side of, and underlying, the semiconductor substrate, and a first and a second conductive layer. The first conductive layer includes a first portion penetrating through the semiconductor substrate to connect to the metal pad, and a second portion forming a metal shield on a backside of the semiconductor substrate.
| Semiconductor light-detecting element|
Prepared is an n− type semiconductor substrate 1 having a first principal surface 1a and a second principal surface 1b opposed to each other, and having a p+ type semiconductor region 3 formed on the first principal surface 1a side. At least a region opposed to the p+ type semiconductor region 3 in the second principal surface 1b of the n− type semiconductor substrate 1 is irradiated with a pulsed laser beam to form an irregular asperity 10.
| Conductive paste composition and semiconductor devices made therewith|
A conductive paste composition contains a source of an electrically conductive metal, a ti—te—li oxide, and an organic vehicle. An article such as a high-efficiency photovoltaic cell is formed by a process of deposition of the paste composition on a semiconductor substrate (e.g., by screen printing) and firing the paste to remove the organic vehicle and sinter the metal and establish electrical contact between it and the device..
| Bulk finfet with controlled fin height and high-k liner|
A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate.
| Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for cmos devices|
A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer.
| Ion implantation device and a method of semiconductor manufacturing by the implantation of boron hydride cluster ions|
A method of manufacturing a semiconductor device includes the steps of: providing a supply of molecules containing a plurality of dopant atoms into an ionization chamber, ionizing said molecules into dopant cluster ions, extracting and accelerating the dopant cluster ions with an electric field, selecting the desired cluster ions by mass analysis, modifying the final implant energy of the cluster ion through post-analysis ion optics, and implanting the dopant cluster ions into a semiconductor substrate. In general, dopant molecules contain n dopant atoms, where n is an integer number greater than 10.
| Semiconductor device and method of fabricating the same|
A semiconductor device comprises: a semiconductor substrate comprising a first region and a second region; and first and second transistors on the first and second regions, respectively, wherein the first transistor comprises a first gate insulating layer pattern, the second transistor comprises a second gate insulating layer pattern, the first and second transistors both comprise a work function adjustment film pattern and a gate metal pattern, wherein the work function adjustment film pattern of the first transistor comprises the same material as the work function adjustment film pattern of the second transistor and the gate metal pattern of the first transistor comprises the same material as gate metal pattern of the second transistor, and a concentration of a metal contained in the first gate insulating layer pattern to adjust a threshold voltage of the first transistor is different from a concentration of the metal contained in the second gate insulating layer pattern to adjust a threshold voltage of the second transistor.. .
| Semiconductor device and method for fabricating the same|
A semiconductor device includes a semiconductor substrate including a first region and a second region, a first high-k dielectric film pattern on the first region, a second high-k dielectric film pattern on the second region and having the same thickness as the first high-k dielectric film pattern. First and second work function control film patterns are positioned on the high-k dielectric film patterns of the first region.
| Semiconductor structures and fabrication method|
A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, and forming a shallow trench isolation structure in the semiconductor substrate.
| Semiconductor device and method for manufacturing|
A semiconductor device includes a gate structure penetrating an interlayer insulating layer formed on a semiconductor substrate, an epitaxial growth layer grown on the interlayer insulating layer, a first transistor including a first channel region in the semiconductor substrate formed by a bias applied to source/drain contacts penetrating the interlayer insulating layer, and a second transistor including a second channel region formed in the epitaxial growth layer by the bias applied to the source/drain contacts and sharing the gate structure. A current flowable path flows more current at any given time, so that operation current is increased and operation speed is improved.
| Semiconductor device and method of manufacturing semiconductor device|
Provided is a semiconductor device including active regions formed in a semiconductor substrate and arranged in a first direction parallel to a surface of the semiconductor substrate; a first element isolating region formed in the semiconductor substrate and electrically isolating adjacent active regions from each other; and gate electrodes extending over the active regions respectively and arranged in the first direction. The first element isolating region includes a first region extending in a second direction orthogonal to the first direction and a second region extending in a direction intersecting the first region, one gate electrode of adjacent gate electrodes has a first edge side which includes a first overlap part placed on the second region, and another gate electrode of the adjacent gate electrodes has a second edge side which faces the first edge side and includes a second overlap part placed on the second region..
| Semiconductor device and method for manufacturing the same|
An antifuse of a semiconductor device includes a semiconductor substrate including a device isolation layer and an active region, a gate structure extending across an interface between the device isolation layer and the active region, a contact coupled to at least a portion of a sidewall of the gate structure, and a metal interconnection provided on the contact and gate structure.. .
| Field effect transistor devices with recessed gates|
A field effect transistor device includes a bulk semiconductor substrate, a fin arranged on the bulk semiconductor substrate, the fin including a source region, a drain region, and a channel region, a first shallow trench isolation (sti) region arranged on a portion of the bulk semiconductor substrate adjacent to the fin, a first recessed region partially defined by the first sti region and the channel region of the fin, and a gate stack arranged over the channel region of the fin, wherein a portion of the gate stack is partially disposed in the first recessed region.. .
| Mos transistor|
A mos transistor is described, including: a source region and a drain region in a semiconductor substrate, an isolation between the source region and the drain region, a first gate conductor between the source region and the isolation, at least one conductive plug electrically connected to the first gate conductor and penetrating into the isolation, and at least one second gate conductor on the isolation, which is electrically connected to the first gate conductor and the at least one conductive plug. One of the at least one conductive plug is between the first gate conductor and the at least one second gate conductor..
| Semiconductor device having tungsten gate electrode and method for fabricating the same|
The present invention provides a semiconductor device in which the threshold voltage of nmos and the threshold voltage of pmos are independently controllable, and a method for fabricating the same. The method includes: forming a gate insulating film over an nmos region and a pmos region of a semiconductor substrate; forming a carbon-containing tungsten over the gate insulating film formed over one of the nmos region and the pmos region; forming a carbon-containing tungsten nitride over the gate insulating film formed over the other one of the pmos region or the nmos region; forming a tungsten film over the carbon-containing tungsten and the carbon-containing tungsten nitride; post-annealing the carbon-containing tungsten and the carbon-containing tungsten nitride; and etching the tungsten film, the carbon-containing tungsten, and the carbon-containing tungsten nitride, to form a gate electrode in the nmos region and the pmos region.
| Semiconductor device and method of fabricating the same|
A semiconductor device and a method for manufacturing the same are capable of improving gidl in a buried gate, and preventing degradation of device characteristics and reliability due to reduction in gate resistance. The semiconductor device may include: junction regions formed at both sidewalls of a trench formed in a semiconductor substrate; a first gate electrode formed in a lower portion of the trench; a second gate electrode formed on at least one inner sidewall of the trench which overlaps one of the junction regions on the first gate electrode; and a third gate electrode formed on one side of the second gate electrode on the first gate electrode..
| Semiconductor device including a gate dielectric layer|
A semiconductor device is fabricated by, inter alia, forming a sacrificial liner on an active portion of a semiconductor substrate, oxidizing the sacrificial liner to transform the sacrificial liner into a gate dielectric layer, and forming a gate on the gate dielectric layer.. .
| Semiconductor device having buried bit lines and method for fabricating the same|
A semiconductor device includes semiconductor bodies formed substantially perpendicular to a semiconductor substrate, buried bit lines formed in the semiconductor bodies and including a metal silicide; and barrier layers formed under and over the buried bit lines and containing germanium.. .
| System and method for a field-effect transistor with a raised drain structure|
A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes forming a frustoconical source by etching a semiconductor substrate, the frustoconical source protruding above a planar surface of the semiconductor substrate; forming a transistor gate, a first portion of the transistor gate surrounding a portion of the frustoconical source and a second portion of the gate configured to couple to a first electrical contact; and forming a drain having a raised portion configured to couple to a second electrical contact and located at a same level above the planar surface of the semiconductor substrate as the second portion of the transistor gate.
| Non-volatile memory devices having charge storage layers at intersecting locations of word lines and active region|
Nonvolatile memory devices are provided. Devices include active regions that may be defined by device isolation layers formed on a semiconductor substrate and extend in a first direction.
| Memory device with charge trap|
A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.. .
| Semiconductor device and manufacturing method of the same|
According to one embodiment, a nonvolatile semiconductor storage device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge accumulation film formed on the first insulating film, a second insulating film formed on the charge accumulation film, and a control electrode formed on a second insulating film, and one of the first and the second insulating film includes a layer containing nitrogen, a layer that is formed on the layer containing nitrogen and that includes a first oxygen containing aluminum atoms and oxygen atoms, and a layer that is formed on the layer including the first oxygen and that includes a second oxygen containing silicon atoms and oxygen atoms; and a concentration of the aluminum atoms is from 1e12 atoms/cm2 to 1e16 atoms/cm2.. .
| Nonvolatile semiconductor memory device|
According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode. The first gate insulating film is arranged on the semiconductor substrate.
| Semiconductor devices and methods of fabricating the same|
A semiconductor device includes a semiconductor substrate having a plurality of active regions defined by a trench. A gate electrode crosses the plurality of active regions.
| Non-volatile semiconductor storage device|
A non-volatile semiconductor storage device disclosed in the embodiment has a semiconductor substrate, a first insulating film, a first charge storage film, a second insulating film, a second charge storage film, a third insulating film, and a control electrode. In this non-volatile semiconductor storage device, the first and second charge storage films comprise a metallic material, a semi-metallic material or a semiconductor material.
| Semiconductor device|
According to one embodiment, a semiconductor device includes a semiconductor substrate and a memory cell provided on the semiconductor substrate. The memory cell includes a first insulating film provided on the semiconductor substrate, a first conductive layer provided on the first insulating film, a first insulating layer provided on the first conductive layer, and a first silicide layer including a silicide provided on the first insulating layer to contact the first insulating layer..
| Semiconductor device with buried bit line and method for fabricating the same|
A method for fabricating a semiconductor device includes etching a semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.. .
| Finfet circuit|
A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate.
| Semiconductor device and method for manufacturing the same|
A semiconductor device comprises a bit line formed over a semiconductor substrate. The bit line has an upper portion and a lower portion, and the upper portion is narrower than the lower portion.
| Tunable schottky diode|
A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an ohmic contact and a schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device.
| Semiconductor device|
A semiconductor device includes: an electron transit layer formed with a semiconductor material, the electron transit layer being formed on a semiconductor substrate; an n-type semiconductor layer formed with a semiconductor material having a wider bandgap than the electron transit layer, the n-type semiconductor layer being formed on the electron transit layer; a δ doping area having an n-type impurity doped in a sheet-shaped region, the δ doping area being formed on the n-type semiconductor layer; and a barrier layer formed with a semiconductor material having a wider bandgap than the electron transit layer, the barrier layer being formed on the δ doping area.. .
| Opto-electronic sensor|
Some embodiments of the present disclosure relate to an infrared (ir) opto-electronic sensor having a silicon waveguide implemented on a single silicon integrated chip. The ir sensor has a semiconductor substrate having a silicon waveguide extends along a length between a radiation input conduit and a radiation output conduit.
| Semiconductor device|
A semiconductor device includes an active region in which current flows when the semiconductor device is in an on state and a breakdown voltage structure portion which surrounds the active region. In the active region, a mos gate structure includes, a p well region, an n+ source region, a gate electrode, and a source electrode is provided on the front surface of a semiconductor substrate.
| Gan dual field plate device with single field plate metal|
A low leakage current transistor (2) is provided which includes a gan-containing substrate (11-14) covered by a passivation surface layer (17) in which a t-gate electrode with sidewall extensions (20) is formed and coated with a multi-level passivation layer (30-32) which includes an intermediate etch stop layer (31) which is used to define a continuous multi-region field plate (33) having multiple distances between the bottom surface of the field plate 33 and the semiconductor substrate in the gate-drain region of the transistor.. .
| Method for extreme ultraviolet electrostatic chuck with reduced clamping effect|
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate..
| Defect inspection apparatus, defect inspection method and non-transitory computer readable recording medium|
In accordance with an embodiment, a defect inspection apparatus includes an electron beam applying unit, a detection unit, a signal processing unit, and a control unit. The electron beam applying unit applies an electron beam to a semiconductor substrate on which first to n-th (n is a natural number equal to or more than 2) patterns are periodically provided.