FreshPatents.com Logo
Enter keywords:  

Track companies' patents here: Public Companies RSS Feeds | RSS Feed Home Page
Popular terms

[SEARCH]

Semiconductor Substrate topics
Semiconductor Substrate
Semiconductor
Semiconductor Device
Gallium Nitride
Memory Cell
Phase Change Memory
Phase Change Material
Memory Device
Semiconductor Memory
Integrated Circuit
Transistors
Field Effect Transistor
Planarization
Conductive Layer
Semiconductor Devices

Follow us on Twitter
twitter icon@FreshPatents

Web & Computing
Cloud Computing
Ecommerce
Search patents
Smartphone patents
Social Media patents
Video patents
Website patents
Web Server
Android patents
Copyright patents
Database patents
Programming patents
Wearable Computing
Webcam patents

Web Companies
Apple patents
Google patents
Adobe patents
Ebay patents
Oracle patents
Yahoo patents

[SEARCH]

Semiconductor Substrate patents



      
           
This page is updated frequently with new Semiconductor Substrate-related patent applications. Subscribe to the Semiconductor Substrate RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Substrate RSS RSS


Method for fabricating photovoltaic cells with plated contacts

Katholieke Universiteit LeuvenKu Leuven R&d

Method for fabricating photovoltaic cells with plated contacts

Semiconductor substrate having stress-absorbing surface layer

Texas Instruments

Semiconductor substrate having stress-absorbing surface layer

Semiconductor substrate having stress-absorbing surface layer

Lift-off of epitaxial layers from silicon carbide or compound semiconductor substrates

Date/App# patent app List of recent Semiconductor Substrate-related patents
01/22/15
20150024594
 Cooled pin lifter paddle for semiconductor substrate processing apparatus patent thumbnailnew patent Cooled pin lifter paddle for semiconductor substrate processing apparatus
A semiconductor substrate processing apparatus includes a cooled pin lifter paddle for raising and lowering a semiconductor substrate. The semiconductor substrate processing apparatus comprises a processing chamber in which the semiconductor substrate is processed, a heated pedestal for supporting the semiconductor substrate in the processing chamber, and the cooled pin lifter paddle located below the pedestal.
Lam Research Corporation
01/22/15
20150024584
 Methods for forming integrated circuits with reduced replacement metal gate height variability patent thumbnailnew patent Methods for forming integrated circuits with reduced replacement metal gate height variability
Methods for fabricating integrated circuits with reduced replacement metal gate height variability are provided. In an embodiment, a method includes providing a semiconductor substrate with a fin supported thereon and forming a conformal material layer overlying the fin and the semiconductor substrate.
Global Foundries, Inc.
01/22/15
20150024581
 Method for manufacturing a semiconductor device patent thumbnailnew patent Method for manufacturing a semiconductor device
A method for manufacturing a semiconductor device in which an electrode structure is formed on a silicon carbide semiconductor substrate, includes forming a schottky layer including a metal selected from the group titanium, tungsten, molybdenum, and chrome on a front surface of the silicon carbide semiconductor substrate; heating the schottky layer to form a schottky electrode which has a schottky contact with the silicon carbide semiconductor substrate; and forming a surface electrode composed of aluminum or aluminum including silicon on a surface of the schottky electrode, while heating at a temperature range effective for the surface electrode to closely cover any uneven portion of the schottky electrode, and provide a surface electrode having a predetermined reflectance or less that is suitable for use in an automatic wire bonding apparatus for image recognition such as positioning.. .
Fuji Electric Co., Ltd.
01/22/15
20150024578
 Methods for etching dielectric materials in the fabrication of integrated circuits patent thumbnailnew patent Methods for etching dielectric materials in the fabrication of integrated circuits
Methods for etching dielectric materials in the fabrication of integrated circuits are disclosed herein. In one exemplary embodiment, a method for fabricating an integrated circuit includes forming a layer of a first dielectric material over a gate electrode structure formed on a semiconductor substrate.
Globalfoundries, Inc.
01/22/15
20150024563
 Semiconductor device,  manufacturing the semiconductor device, and electronic device patent thumbnailnew patent Semiconductor device, manufacturing the semiconductor device, and electronic device
The upper end of a gate electrode is situated below the surface of a semiconductor substrate. An insulating layer is formed over the gate electrode and over the semiconductor substrate situated at the periphery thereof.
Renesas Electronics Corporation
01/22/15
20150024558
 Asymmetrical replacement metal gate field effect transistor patent thumbnailnew patent Asymmetrical replacement metal gate field effect transistor
An asymmetrical field effect transistor (fet) device includes a semiconductor substrate, a buried oxide layer disposed on the semiconductor substrate, an extended source region disposed on the buried oxide layer and a drain region disposed on the buried oxide layer. The asymmetrical fet device also includes a silicon on insulator region disposed between the extended source region and the drain region and a gate region disposed above the extended source region and the silicon on insulator region..
International Business Machines Corporation
01/22/15
20150024556
 Method for manufacturing semiconductor device patent thumbnailnew patent Method for manufacturing semiconductor device
A semiconductor device includes an input electrode provided on a front surface of a semiconductor substrate of a first conductivity type and an output electrode provided on a rear surface of the semiconductor substrate. The device has reduced deterioration of electrical characteristics when manufactured by a method including introducing impurities into the rear surface of the semiconductor substrate; activating the impurities using a first annealing process to form a first semiconductor layer, which is a contact portion in contact with the output electrode, in a surface layer of the rear surface; radiating protons to the rear surface; and activating the protons radiated using a second annealing process to form a second semiconductor layer of the first conductivity type, which has a higher impurity concentration than the semiconductor substrate, in a region that is deeper than the first semiconductor layer from the rear surface of the semiconductor substrate..
Fuji Electric Co., Ltd.
01/22/15
20150024546
 System, structure, and  manufacturing a semiconductor substrate stack patent thumbnailnew patent System, structure, and manufacturing a semiconductor substrate stack
A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a tsv structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.
01/22/15
20150024541
 Method for fabricating photovoltaic cells with plated contacts patent thumbnailnew patent Method for fabricating photovoltaic cells with plated contacts
The disclosed technology relates generally to photovoltaic cells, and more particularly to photovoltaic cells with plated metal contacts. In one aspect, a method of fabricating a photovoltaic cell with a metal contact pattern on a surface of a semiconductor substrate includes locally smoothening portions of the surface of the semiconductor substrate by using a first laser, at predetermined locations.
Katholieke Universiteit Leuven, Ku Leuven R&d
01/22/15
20150024520
 Semiconductor device manufacturing method and manufacturing device patent thumbnailnew patent Semiconductor device manufacturing method and manufacturing device
A marker which is a reference of a coordinate position defining a region of a chip that is manufactured in a semiconductor substrate is formed. A crystal defect on the semiconductor substrate is detected.
Fuji Electric Co., Ltd.
01/22/15
20150024518
new patent

Method of forming a selectively adjustable gate structure


The present disclosure relates to a method of forming a gate structure that can be selectively adjusted to reduce critical-dimension (cd) variations. In some embodiments, the method is performed by forming a gate structure having a first length over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.
01/22/15
20150023570
new patent

Finger biometric sensor including stacked die each having a non-rectangular shape and related methods


A finger biometric sensor may include first and second integrated circuit (ic) dies arranged in a stacked relation. The first ic die may include a first semiconductor substrate and an array of finger biometric sensing pixels thereon, and the second ic die may include a second semiconductor substrate and processing circuitry thereon coupled to the array of finger biometric sensing pixels.
Apple Inc.
01/22/15
20150023380
new patent

Semiconductor laser device


A semiconductor laser device includes a first conductivity type semiconductor substrate, a first conductivity type cladding layer, a first light guide layer, an active layer, a second light guide layer, and a second conductivity type cladding layer laminated on the semiconductor substrate in that order. The semiconductor laser device supports at least one of a first-order and higher-order mode of oscillation in the semiconductor laser in crystal growth direction of the active layer.
Mitsubishi Electric Corporation
01/22/15
20150023111
new patent

Nonvolatile semiconductor memory device


A nonvolatile semiconductor memory device of an embodiment includes a p-type semiconductor substrate, a first p-well formed in the semiconductor substrate, and on which a plurality of memory cells is formed, an first n-well surrounding the first p-well and electrically separating the first p-well from the semiconductor substrate, a first negative voltage generation unit configured to generate a first negative voltage, a boost unit configured to boost a voltage and generate a boosted voltage, and a well voltage transmission unit connected to the first negative voltage generation unit, the boost unit, and the first p-well, and configured to switch a voltage between the first negative voltage and the boosted voltage, the voltage being applied to the first p-well.. .
Kabushiki Kaisha Toshiba
01/22/15
20150022248
new patent

Semiconductor device and driving system


An output mos transistor has a drain connected with a power supply and a source connected with an output terminal. The short-circuit mos transistor has a source connected with the output terminal.
Renesas Electronics Corporation
01/22/15
20150022198
new patent

Method and magnetic sensor producing a changing magnetic field


Methods and apparatus for detecting a magnetic field include a semiconductor substrate, a coil configured to provide a changing magnetic field in response to a changing current in the coil; and a magnetic field sensing element supported by the substrate. The coil receives the changing current and, in response, generates a changing magnetic field.
Allegro Microsystems, Llc
01/22/15
20150021786
new patent

Bonded semiconductor structures


A method is disclosed that includes the steps outlined below. A first oxide layer is formed to divide a first semiconductor substrate into a first part and a second part.
Taiwan Semiconductor Manufacturing Co., Ltd.
01/22/15
20150021777
new patent

Mounting structure and mounting structure manufacturing method


A mounting structure which reduces the mechanical stress added to a low-κ material due to warping caused by the difference in thermal expansion coefficients between a chip and a chip support during mounting. This mounting structure includes: a low-κ layer formed on top a semiconductor substrate; an electrode layer formed on the low-κ layer; a protective layer formed the low-κ layer and the electrode layer and having an opening reaching the electrode layer; a first solder layer filling the opening and formed on the electrode layer inside; a second solder layer formed on the first solder layer and having an elastic modulus smaller than the first solder layer; and a support layer connected to the second solder layer and supporting the semiconductor substrate.
International Business Machines Corporation
01/22/15
20150021773
new patent

Through semiconductor via structure with reduced stress proximity effect


An integrated circuit device and associated fabrication process are disclosed for forming a through semiconductor via (tsv) conductor structure in a semiconductor substrate with active circuitry formed on a first substrate surface where the tsv conductor structure includes multiple small diameter conductive vias extending through the first substrate surface and into the semiconductor substrate by a predetermined depth and a large diameter conductive via formed to extend from the multiple small diameter conductive vias and through a second substrate surface opposite to the first substrate surface.. .
Conversant Intellectual Property Management Inc.
01/22/15
20150021765
new patent

Semiconductor device


Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5).
Rohm Co., Ltd.
01/22/15
20150021762
new patent

Semiconductor substrate having stress-absorbing surface layer


An assembly (101) comprising a semiconductor device (110) with solderable bumps (112); a substrate (120) with a layer (130) of a first insulating compound and an underlying metal layer (140) patterned in contact pads (141) and connecting traces (142), the insulating layer having openings (132) to expose the surface (142a) and sidewalls (142b) of underlying traces; the device bumps soldered onto the contact pads, establishing a gap (150) between device and top insulating layer; and a second insulating compound (160) cohesively filling the gap and the second openings, thereby touching the underlying traces, the second insulating compound having a higher glass transition temperature, a higher modulus, and a lower coefficient of thermal expansion than the first insulating compound.. .
Texas Instruments Incorporated
01/22/15
20150021758
new patent

Mechanisms for forming bump structures over wide metal pad


Embodiments of mechanisms for forming a semiconductor die are provided. The semiconductor die includes a semiconductor substrate and a protection layer formed over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.
01/22/15
20150021741
new patent

Bonded semiconductor structures


A method is disclosed that includes the steps outlined below. An epitaxial layer is formed on a first semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.
01/22/15
20150021732
new patent

Semiconductor device


A semiconductor device includes: a first well provided in a semiconductor substrate; a second well provided in the semiconductor substrate, so as to be isolated from the first well; a schottky barrier diode formed in the first well; and a pn junction diode formed in the second well, with an impurity concentration of the pn junction thereof set higher than an impurity concentration of the schottky junction of the schottky barrier diode, and being connected antiparallel with the schottky barrier diode.. .
Fujitsu Semiconductor Limited
01/22/15
20150021731
new patent

Solid-state imaging device and manufacturing method thereof


The solid-state imaging device according to the present invention includes a semiconductor substrate including an imaging region and a peripheral circuit region, a wiring layer formed on the semiconductor substrate, a plurality of pixel electrodes arranged in a matrix on the wiring layer above the imaging region, a photoelectric conversion film formed on the wiring layer and the plurality of pixel electrodes above the imaging region, and an upper electrode formed on the photoelectric conversion film. The photoelectric conversion film has a laminated structure in which a plurality of well layers and a plurality of barrier layers are alternately laminated, the well layers made of a first semiconductor having a fundamental absorption edge in a wavelength region longer than a near-infrared light wavelength, and the barrier layers made of an insulator or a second semiconductor having a band gap wider than that of the first semiconductor..
Panasonic Intellectual Property Management Co., Ltd.
01/22/15
20150021728
new patent

Dielectric structure for color filter array


An integrated circuit device in which an array of photodiodes are formed at the surface of a semiconductor substrate. A dielectric structure comprising multiple layers of dielectric is formed over the photodiodes.
Taiwan Semiconductor Manufacturing Co., Ltd.
01/22/15
20150021714
new patent

Integrated circuits having a metal gate structure and methods for fabricating the same


Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming an interfacial layer material over a semiconductor substrate and forming a gate insulation layer over the interfacial layer material that includes a combination of a layer of a hafnium oxide material and a layer of hafnium silicate material.
Globalfoundries, Inc.
01/22/15
20150021705
new patent

Method of fabricating dual high-k metal gates for mos devices


The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack..
Taiwan Semiconductor Manufacturing Company, Ltd.
01/22/15
20150021703
new patent

Gate oxide quality for complex mosfet devices


In various aspects, methods of forming a semiconductor device and semiconductor devices are provided. In some illustrative embodiments herein, a silicon/germanium layer is provided on a semiconductor substrate.
Globalfoundries Inc.
01/22/15
20150021698
new patent

Intrinsic channel planar field effect transistors having multiple threshold voltages


Intrinsic channels one or more intrinsic semiconductor materials are provided in a semiconductor substrate. A high dielectric constant (high-k) gate dielectric layer is formed on the intrinsic channels.
International Business Machines Corporation
01/22/15
20150021697
new patent

Thermally tuning strain in semiconductor devices


A method includes performing a first epitaxy to grow a silicon germanium layer over a semiconductor substrate, performing a second epitaxy to grow a silicon layer over the silicon germanium layer, and performing a first oxidation to oxidize the silicon germanium layer, wherein first silicon germanium oxide regions are generated. A strain releasing operation is performed to release a strain caused by the first silicon germanium oxide regions.
Taiwan Semiconductor Manufacturing Company, Ltd.
01/22/15
20150021696
new patent

Mos devices having epitaxy regions with reduced facets


An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage.
Taiwan Semiconductor Manufacturing Company, Ltd.
01/22/15
20150021694
new patent

Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating the same


Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate.
Globalfoundries, Inc.
01/22/15
20150021691
new patent

Finfet with electrically isolated active region on bulk semiconductor substrate and fabricating same


A semiconductor stack of a finfet in fabrication includes a bulk silicon substrate, a selectively oxidizable sacrificial layer over the bulk substrate and an active silicon layer over the sacrificial layer. Fins are etched out of the stack of active layer, sacrificial layer and bulk silicon.
Globalfoundries Inc.
01/22/15
20150021689
new patent

Asymmetrical replacement metal gate field effect transistor


An asymmetrical field effect transistor (fet) device includes a semiconductor substrate, a buried oxide layer disposed on the semiconductor substrate, an extended source region disposed on the buried oxide layer and a drain region disposed on the buried oxide layer. The asymmetrical fet device also includes a silicon on insulator region disposed between the extended source region and the drain region and a gate region disposed above the extended source region and the silicon on insulator region..
International Business Machines Corporation
01/22/15
20150021688
new patent

Mos devices with non-uniform p-type impurity profile


An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A silicon germanium region is disposed in the opening, wherein the silicon germanium region has a first p-type impurity concentration.
Taiwan Semiconductor Manufacturing Company, Ltd.
01/22/15
20150021663
new patent

Finfet with insulator under channel


A finfet has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region.
Globalfoundries Inc.
01/22/15
20150021625
new patent

Semiconductor fin isolation by a well trapping fin portion


A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate.
International Business Machines Corporation
01/22/15
20150021624
new patent

Lift-off of epitaxial layers from silicon carbide or compound semiconductor substrates


A method to remove epitaxial semiconductor layers from a substrate by growing an epitaxial sacrificial layer on the substrate where the sacrificial layer is a transition metal nitride (tmn) or a tmn ternary compound, growing one or more epitaxial device layers on the sacrificial layer, and separating the device layers from the substrate by etching the sacrificial layer to completely remove the sacrificial layer without damaging or consuming the substrate or any device layer. Also disclosed are the related semiconductor materials made by this method..
01/22/15
20150021578
new patent

Solid-state imaging device and electronic apparatus


A solid-state imaging device includes: a plurality of laminated photoelectric conversion sections; a reading section configured of a semiconductor region formed inside a semiconductor substrate and reading electric charge that has been subjected to photoelectric conversion in the photoelectric conversion sections; a charge accumulation section accumulating the electric charge read by the reading section; and a light shielding structure shielding, from light, a portion other than the reading section and the photoelectric conversion sections.. .
Sony Corporation
01/22/15
20150021554
new patent

Direct formation of graphene on semiconductor substrates


The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer.
Kansas State University Research Foundation
01/22/15
20150021410
new patent

System and miniaturization of synthetic jets


A micro-electromechanical (mem) synthetic jet actuator includes a semiconductor substrate having a cavity extending therethrough, such that a first opening is formed in a first surface of the semiconductor substrate and such that a second opening is formed in a second surface of the semiconductor substrate. A first flexible membrane is formed on at least a portion of the front surface of the semiconductor substrate and extends over the first opening.
General Electric Company
01/22/15
20150021409
new patent

System and miniaturization of synthetic jets


A micro-electromechanical (mem) synthetic jet actuator includes a semiconductor substrate having a cavity extending therethrough, such that a first opening is formed in a first surface of the semiconductor substrate and such that a second opening is formed in a second surface of the semiconductor substrate. A first flexible membrane is formed on at least a portion of the front surface of the semiconductor substrate and extends over the first opening.
General Electric Company
01/15/15
20150018619

Space-saving flat interconnection


Apparatus, consisting of an integrated circuit (ic) die, and a circuit. The ic die includes a semiconductor substrate having a substrate plane face and a substrate edge, an imaging array formed on the substrate plane face, and a plurality of array pads mounted on the substrate plane face and connected to the imaging array.
Gyrus Acmi Inc. (d.b.a. Olympus Surgical Technologies America)
01/15/15
20150017812

Sequential precursor dosing in an ald multi-station/batch reactor


Disclosed herein are methods of depositing layers of material on multiple semiconductor substrates at multiple processing stations within one or more reaction chambers. The methods may include dosing a first substrate with film precursor at a first processing station and dosing a second substrate with film precursor at a second processing station with precursor flowing from a common source, wherein the timing of said dosing is staggered such that the first substrate is dosed during a first dosing phase during which the second substrate is not substantially dosed, and the second substrate is dosed during a second dosing phase during which the first substrate is not substantially dosed.
Lam Research Corporation
01/15/15
20150017810

Dual chamber plasma etcher with ion accelerator


The embodiments herein generally deal with semiconductor processing methods and apparatus. More specifically, the embodiments relate to methods and apparatus for etching a semiconductor substrate.
Lam Research Corporation
01/15/15
20150017797

Method of manufacturing semiconductor device including metal-containing conductive line


A semiconductor device includes: a semiconductor substrate having a trench therein, a metal-containing barrier layer extending along an inner wall of the trench and defining a wiring space in the trench, the wiring space having a first width along a first direction, and a metal-containing conductive line on the metal-containing barrier layer in the wiring space, and including at least one metal grain having a particle diameter of about the first width along the first direction.. .
Samsung Electronics Co., Ltd.
01/15/15
20150017796

Techniques providing metal gate deviceswith multiple barrier layers


A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features.
Taiwan Semiconductor Manufacturing Company, Ltd.
01/15/15
20150017769

Vertical semiconductor device, module and system each including the same, and manufacturing the vertical semiconductor device


A vertical semiconductor device having a vertical channel region is disclosed. The vertical semiconductor device includes a pillar having a vertical channel region, a bit line buried in a semiconductor substrate located at a lower part of the pillar, and a body connection unit configured to couple at least one sidewall of the pillar to the semiconductor substrate.
Sk Hynix Inc.
01/15/15
20150017768

Semiconductor device and forming the same


A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions.
Taiwan Semiconductor Manufacturing Company Ltd.
01/15/15
20150017754

Composition for forming n-type diffusion layer, producing semiconductor substrate having n-type diffusion layer, and producing solar cell element


The invention provides composition for forming an n-type diffusion layer, the composition comprising a compound containing a donor element, a dispersing medium, and an organic filler; a method for producing a semiconductor substrate having an n-type diffusion layer; and a method for producing a photovoltaic cell element.. .
Hitachi Chemical Company, Ltd.
01/15/15
20150017747

Method for forming a solar cell with a selective emitter


A method for producing a solar cell with a selective emitter is disclosed. A semiconductor substrate (1) is provided.
Rec Solar Pte. Ltd.
01/15/15
20150016926

Pod having top cover aperture for detecting surrounding gas within the pod


A storage pod for semiconductor substrates includes a top cover formed from a non-air permeable (nap) material having faces including a top and a plurality of sides. A bottom base plate has a locking structure configured for providing a locking position for locking the sides, and for providing an unlocked position where the sides are detached from the bottom base plate.
Texas Instruments Incorporated
01/15/15
20150016769

Semiconductor devices including photodetectors integrated on waveguides and methods for fabricating the same


Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a method for fabricating a semiconductor device includes etching a waveguide layer in a detector region of a semiconductor substrate to form a recessed waveguide layer section.
Globalfoundries Singapore Pte. Ltd.
01/15/15
20150016767

Optical semiconductor device


An optical semiconductor device includes a laser oscillator on a semiconductor substrate; and an optical modulator on the semiconductor substrate. The laser oscillator includes a pair of reflecting mirrors at least one of which is a loop mirror, and the loop mirror includes a loop waveguide and a plurality of first ring resonators serially inserted in the loop waveguide.
Fujitsu Limited
01/15/15
20150016180

Memory architectures having dense layouts


Some embodiments relate to a memory cell to store one or more bits of data. The memory cell includes a capacitor including first and second capacitor plates which are separated from one another by a dielectric.
Taiwan Semiconductor Manufacturing Co., Ltd.
01/15/15
20150015768

Imaging element and imaging device


An imaging element includes: a semiconductor substrate in which a plurality of pixels is arranged in a two-dimensional array; a color filter layer which is laminated in a position corresponding to the pixel on an upper layer of the semiconductor substrate; a plurality of micro lenses which is laminated on an upper layer of the color filter layer to condense light which is incident onto the pixel; and an isolated columnar reflective wall which is vertically provided in an intermediate layer between the semiconductor substrate and the micro lens at every position of a gap enclosed by the plurality of adjacent micro lenses and reflects the light which is incident onto the color filter from the gap to a direction facing the pixel corresponding to the color filter.. .
Fujifilm Corporation
01/15/15
20150015758

Image sensor, production apparatus, production method, and electronic device


Provided is an image sensor including a photoelectric conversion unit for converting a received light into an electric charge; a semiconductor substrate including the photoelectric conversion unit; and a plurality of areas each having a refractive index different from a refractive index of the semiconductor substrate formed between a surface of the semiconductor substrate on which light is incident and the photoelectric conversion unit. Also, provided are an apparatus and a method of producing the image sensor, and an electronic device including the image sensor..
Sony Corporation
01/15/15
20150015489

System and digital recording of handpainted, handdrawn and handwritten information


A system and method of digital recording of painted, drawn and written information and navigating a cursor on the display defined by free moving at least one part of a painter body has steps of providing a computing device with a display serving as a digital electronic canvas; providing an input device comprising: an interchangeable end-point; a single mems sensor of mechanical parameters integrated on a semiconductor substrate chip, which is included in the interchangeable end-point; providing any working surface suitable for moving the input device relative to the working surface in a process of painting, drawing, writing or cursor navigating; moving the input device with at least one part of a painter body such that the interchangeable end-point is interacting with the working surface while recording the change of a vectors of mechanical parameters applied to the sensor; digitizing this information and processing the data related to the change of the vectors of mechanical parameters; and providing a description in digital format of how the input device has been moved over and how it has been pressed to the working surface based on the change of the corresponding vectors of mechanical parameters.. .
01/15/15
20150015336

Cmos cascode power cells


A circuit includes a first cmos device forming a gain stage of a power amplifier and a second cmos device forming a voltage buffer stage of the power amplifier. The first cmos device includes a first doped well formed in a substrate, a first drain region and a first source region spaced laterally from one another in the first doped well, and a first gate structure formed over a first channel region in the first doped well.
Taiwan Semiconductor Manufacturing Co., Ltd.
01/15/15
20150015335

Sense amplifier layout for finfet technology


A sense amplifier (sa) comprises a semiconductor substrate having an oxide definition (od) region, a pair of sa sensing devices, a sa enabling device, and a sense amplifier enabling signal (sae) line for carrying an sae signal. The pair of sa sensing devices have the same poly gate length lg as the sa enabling device, and they all share the same od region.
Taiwan Semiconductor Manufacturing Co., Ltd.
01/15/15
20150014866

Semiconductor device and producing a glass-like layer


A method for producing a glass-like layer (3) on a substrate, e.g. A power semiconductor substrate (1), is disclosed.
01/15/15
20150014851

Interconnect structure and fabricating same


A structure comprises a passivation layer formed over a semiconductor substrate, a connection pad enclosed by the passivation layer, a redistribution layer formed over the passivation layer, wherein the redistribution layer is connected to the connection pad, a bump formed over the redistribution layer, wherein the bump is connected to the redistribution layer and a molding compound layer formed over the redistribution layer. The molding compound layer comprises a flat portion, wherein a bottom portion of the bump is embedded in the flat portion of the molding compound layer and a protruding portion, wherein a middle portion of the bump is surrounded by the protruding portion of the molding compound layer..
Taiwan Semiconductor Manufacturing Company, Ltd.
01/15/15
20150014846

Self-alignment structure for wafer level chip scale package


A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.
01/15/15
20150014792

Iii-v compound semiconductor device having metal contacts and making the same


A semiconductor device comprises a semiconductor substrate; a channel layer of at least a first iii-v semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second iii-v semiconductor compound above a second portion of the channel layer; and a first metal contact structure above the s/d regions comprising a first metallic contact layer contacting the s/d regions. The first metallic contact layer comprises at least one metal-iii-v semiconductor compound..
Taiwan Semiconductor Manufacturing Co., Ltd.
01/15/15
20150014790

Fin deformation modulation


A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench.
Taiwan Semiconductor Manufacturing Company, Ltd.
01/15/15
20150014787

Semiconductor device and manufacturing the same


A method for manufacturing a semiconductor device includes: forming a first insulation film on a portion of a first region of a semiconductor substrate and forming a second insulation film between a second region and a third region of the semiconductor substrate; etching an upper portion of the first insulation film such that the thickness of the first insulation film is less than the thickness of the second insulation film; forming a third insulation film in the second region and forming a fourth insulation film in the third region; and forming a first gate electrode on the first insulation film whose upper portion was etched, forming a second gate electrode on the third insulation film, and forming a third gate electrode on the fourth insulation film.. .
Seiko Epson Corporation
01/15/15
20150014783

Semiconductor integrated circuit device


An mv-pmos and mv-nmos configuring a high side drive circuit are formed in an n-type isolation region formed on a p-type semiconductor substrate. The mv-nmos is connected to a p-type isolation region of an intermediate potential in the interior of the n-type isolation region.
Fuji Electric Co., Ltd.
01/15/15
20150014776

Finfet integrated circuits and methods for their fabrication


A fin field effect transistor integrated circuit (finfet ic) has a plurality of fins extending from a semiconductor substrate, where a trough is defined between adjacent fins. A second dielectric is positioned within the trough, and a protruding portion of the fins extends above the second dielectric.
Globalfoundries, Inc.
01/15/15
20150014770

High-voltage field-effect transistor having multiple implanted layers


A method for fabricating a high-voltage field-effect transistor includes forming a body region, a source region, and a drain region in a semiconductor substrate. The drain region is separated from the source region by the body region.
Power Integrations, Inc.
01/15/15
20150014767


A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film; a gate electrode filled in the active region; a bit line contact structure coupled to an active region between the gate electrodes; and a line-type bit line electrode formed over the bitline contact structure. The bit line contact structure includes a bit line contact formed over the active region; and an ohmic contact layer formed over the bit line contact..
Sk Hynix Inc.
01/15/15
20150014764

Super junction mosfet, manufacturing the same, and complex semiconductor device


A super junction mosfet is disclosed. The super junction mosfet includes a plurality of mutually parallel pn junctions extending in a vertical direction on a first principal surface of an n-type semiconductor substrate; a parallel pn layer in which n-type drift regions and p-type partition regions, each sandwiched between the adjacent pn junctions, are disposed alternately in contact with each other; and an mos gate structure on the first principal surface side of the parallel pn layer, wherein an n-type first buffer layer and second buffer layer are in contact in that order on the opposite principal surface side, and the impurity concentration of the first buffer layer is a concentration that is equal to or less than the same level as that of the impurity concentration of the n-type drift region..
Fuji Electric Co., Ltd.
01/15/15
20150014762

Nonvolatile semiconductor storage device and manufacturing the same


A semiconductor storage device is disclosed. The semiconductor device includes a semiconductor substrate; and a gate electrode disposed above the semiconductor substrate.
Kabushiki Kaisha Toshiba
01/15/15
20150014761

Semiconductor device and manufacturing method thereof


A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces.
United Microelectronics Corp.
01/15/15
20150014757

Semiconductor device


A semiconductor device includes: a spin torque written in-plane magnetization magnetoresistive element, placed over the main surface of a semiconductor substrate, whose magnetization state can be changed according to the direction of a current flow; and a first wiring electrically coupled with the magnetoresistive element and extended toward the direction along the main surface. The aspect ratio of the magnetoresistive element as viewed in a plane is a value other than 1.
Renesas Electronics Corporation
01/15/15
20150014750

Solid-state imaging apparatus, manufacturing the same, and electronic apparatus


A solid-state imaging apparatus includes a semiconductor substrate in which a charge transfer section configured to transfer a charge generated in a photoelectric conversion section is formed. The semiconductor substrate includes a surface that is formed in a convex shape in an area in which the charge transfer section is formed..
Sony Corporation
01/15/15
20150014742

Semiconductor device and production semiconductor device


Depth of a termination p base region provided in a termination portion of an active region close to an edge termination structure portion is more than depth of a p-type base region provided inside the termination p base region. An n-type high-concentration region is provided from one main surface of the semiconductor substrate in the entire surface layer of one surface of a semiconductor substrate within a depth of 20 μm or less below the bottom of the termination p base region.
Fuji Electric Co., Ltd.
01/15/15
20150014741

Semiconductor device


A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth p layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth p layers respectively have surface concentrations p(1) to p(4) that decrease in this order, bottom-end distances d(1) to d(4) that increase in this order, and distances b(1) to b(4) to the edge of the semiconductor substrate that increase in this order.
Mitsubishi Electric Corporation
01/15/15
20150014664

Semiconductor device and manufacturing same


A fet is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction..
Semiconductor Energy Laboratory Co., Ltd.
01/15/15
20150014621

Variable resistance memory device and manufacturing the same


A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a multi-layered insulating layer including a plurality of holes formed on a semiconductor substrate, a lower electrode formed in a bottom of each of the holes, a first spacer formed on the lower electrode and a sidewall of each of the holes, a second spacer formed on an upper sidewall of the first spacer, a third spacer formed on a lower sidewall of the first spacer below the second spacer, a variable resistance part that is formed on the lower electrode has a height lower than a height of a top of each hole, and an upper electrode formed on the variable resistance part to be buried in each hole..
Sk Hynix Inc.
01/15/15
20150014579

Polishing composition and producing semiconductor substrate


A polishing composition contains: silicon dioxide having an average primary particle diameter of 40 nm or more as calculated from the specific surface area determined by the bet method; a nitrogen-containing water-soluble polymer; and a basic compound. The value of b/a is 1 or more and less than 7,000 and the value of c/a is 5,000 or more and less than 1,500,000 when in one liter of the polishing composition, a is defined as the number of silicon dioxide, b is defined as the number of monomer units of the nitrogen-containing water-soluble polymer, and c is defined as the number of molecules of the basic compound.
Fujimi Incorporated
01/15/15
20150014297

Heating plate having thermal shock resistance and corrosion resistance


Disclosed herein is a heating plate of a heating device for a semiconductor manufacturing process, including: a metal matrix, which is composed of a ni—fe—co alloy, and in which a heating element is buried; a first ceramic layer formed on one side of the metal matrix; and a second ceramic layer formed on the other side and circumference of the metal matrix. According to the heating plate for a semiconductor manufacturing process of the present invention, even when thermal shock caused by repetition of heating and cooling is applied to the metal matrix composed of a ni—fe—co alloy, the heating plate can exhibit excellent thermal shock resistance because the consistency between the metal matrix and the ceramic layer made of aln or the like is maintained, and can prevent the metal matrix from being damaged because the ceramic layer has excellent chemical resistance and wear resistance.
Korea Institute Of Machinery And Materials


Popular terms: [SEARCH]

Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

Follow us on Twitter
twitter icon@FreshPatents

###

This listing is a sample listing of patent applications related to Semiconductor Substrate for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Semiconductor Substrate with additional patents listed. Browse our RSS directory or Search for other possible listings.
     SHARE
  
         





0.5314

4835

0 - 1 - 82