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Semiconductor Substrate patents

      

This page is updated frequently with new Semiconductor Substrate-related patent applications.




Date/App# patent app List of recent Semiconductor Substrate-related patents
08/18/16
20160242292 
 Electronic device patent thumbnailElectronic device
An electronic device includes a semiconductor substrate, an electronic element mounted on the substrate, a conductive layer electrically connected to the electronic element, a sealing resin and a columnar conductor. The substrate has a recess formed in its obverse surface.
Rohm Co., Ltd.


08/18/16
20160241242 
 Drive unit patent thumbnailDrive unit
A drive unit includes a reverse conducting transistor including a transistor and a first diode being connected in inverse-parallel to the transistor, the transistor and the first diode being provided on a common semiconductor substrate; a second diode including a cathode being connected to a collector of the transistor the second diode being provided on the semiconductor substrate; and a detection portion configured to detect a voltage between the collector and an emitter of the transistor via an anode of the second diode.. .
Toyota Jidosha Kabushiki Kaisha


08/18/16
20160241196 
 Multi-band device having multiple miniaturized single-band power amplifiers patent thumbnailMulti-band device having multiple miniaturized single-band power amplifiers
Multi-band device having multiple miniaturized single-band power amplifiers. In some embodiments, a power amplifier die can include a semiconductor substrate, and a plurality of power amplifiers (pas) implemented on the semiconductor substrate.
Skyworks Solutions, Inc.


08/18/16
20160241190 
 Oscillation circuit, oscillator, electronic apparatus and moving object patent thumbnailOscillation circuit, oscillator, electronic apparatus and moving object
An oscillation circuit includes a circuit for oscillation that oscillates a resonator, an output circuit that has a signal, output from the circuit for oscillation, input thereto to thereby output an oscillation signal, a connection terminal to which power is applied, a first wiring that connects from the connection terminal to the output circuit, and a second wiring that is connected to the first wiring through a connection node provided on the first wiring and connects from the connection node to the circuit for oscillation. The circuit for oscillation, the output circuit, the connection terminal, the first wiring, and the second wiring are provided on a semiconductor substrate.
Seiko Epson Corporation


08/18/16
20160241186 
 Stress compensated oscillator circuitry and integrated circuit using the same patent thumbnailStress compensated oscillator circuitry and integrated circuit using the same
A stress compensated oscillator circuitry comprises a sensor arrangement for providing a sensor output signal ssensor, wherein the sensor output signal ssensor is based on an instantaneous stress or strain component σ in the semiconductor substrate, a processing arrangement for processing the sensor output signal ssensor and providing a control signal scontrol depending on the instantaneous stress or strain component σ in the semiconductor substrate, and an oscillator arrangement for providing an oscillator output signal sosc having an oscillator frequency fosc based on the control signal scontrol, wherein the control signal scontrol controls the oscillator output signal sosc, and wherein the control signal scontrol reduces the influence of the instantaneous stress or strain component σ in the semiconductor substrate onto the oscillator output signal sosc, so that the oscillator circuitry provides a stress compensated oscillator output signal.. .
Infineon Technologies Ag


08/18/16
20160241018 
 Semiconductor device and semiconductor module patent thumbnailSemiconductor device and semiconductor module
The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.. .
Rohm Co., Ltd.


08/18/16
20160240724 
 Method for producing a solar cell patent thumbnailMethod for producing a solar cell
The invention relates to a method for producing a solar cell (1) from crystalline semiconductor material. In a first surface (3a) of a semiconductor substrate (3), a first doping area (5) is formed by thermally diffusing a first dopant and in the second surface (3b) of the semiconductor substrate, a second doping area (7) is formed by implanting ions and thermally implanting a second dopant..
Ion Beam Services


08/18/16
20160240720 
 Improved semiconductor radiation detector patent thumbnailImproved semiconductor radiation detector
A semiconductor radiation detector device includes a semiconductor substrate. On one surface of the substrate are a mig layer (241) of semiconductor of second conductivity type, a barrier layer (251) of semiconductor of first conductivity type, and pixel dopings of semiconductor of the second conductivity type.

08/18/16
20160240718 
 Double-pass photodiode with embedded reflector patent thumbnailDouble-pass photodiode with embedded reflector
A photodiode, in particular photodiode for data transmission applications, can include a semiconductor substrate, which can also be referred to as a substrate layer, and a first semiconductor layer supported by, for instance arranged on, the semiconductor substrate. The photodiode can further include a second semiconductor layer supported by, for instance arranged on, the first semiconductor layer.
Fci Americas Technology Llc


08/18/16
20160240695 
 Mos p-n junction diode with enhanced response speed and manufacturing method thereof patent thumbnailMos p-n junction diode with enhanced response speed and manufacturing method thereof
A mos p-n junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the mos p-n junction diode, a mask layer is formed on a semiconductor substrate.
Pfc Device Holdings Ltd


08/18/16
20160240680 

Semiconductor device having a silicon and germanium material filling a cavity region comprising a notch region formed within a semiconductor substrate


The present invention is directed to semiconductor processes and devices. More specifically, embodiments of the present invention provide a semiconductor device that comprises a shaped cavity formed from two trench structures, and the shaped cavity is filled with silicon and germanium material.
Shanghai Huali Microelectronics Corporation


08/18/16
20160240675 

Structure and transistors with line end extension


A method includes forming an isolation feature in a semiconductor substrate; forming a first fin-like active region and a second fin-like active region in the semiconductor substrate and interposed by the isolation feature; forming a dummy gate stack on the isolation feature, wherein the dummy gate extends to the first fin-like active region from one side and to the second fin-like active region from another side.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240674 

Method for manufacturing semiconductor device with recess, epitaxial growth and diffusion


A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate..
Sony Corporation


08/18/16
20160240669 

System and fabricating high voltage power mosfet


A high voltage power mosfet includes a semiconductor substrate doped by a first conducting type, a source doped by a second conducting type and over the semiconductor substrate, and a drain region doped by the second conducting type and on the semiconductor substrate. One or more drain layers doped by the second conducting type and on the semiconductor substrate span between the body region and the drain region.
Powerwyse, Inc.


08/18/16
20160240664 

Semiconductor device


There is provided a semiconductor device having ldmos transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each ldmos transistor, the trench having a gate electrode partially embedded therein.
Renesas Electronics Corporation


08/18/16
20160240663 

Semiconductor device and fabricating the same


A semiconductor device includes: a semiconductor substrate; a semiconductor layer disposed over the semiconductor layer; a first well region disposed in the semiconductor layer and the semiconductor substrate; a second well region disposed in the semiconductor layer; a first isolation element disposed in the first well region; a second isolation element disposed in the second well region; a gate structure disposed in the semiconductor layer between the first isolation element and the second isolation element; a first doped region disposed in the first well region; and a second doped region disposed in the second well region. The bottom surface of the gate structure is above, below or substantially level with a bottom surface of the first isolation structure..
Vanguard International Semiconductor Corporation


08/18/16
20160240661 

Semiconductor device comprising a transistor array and a termination region and manufacturing such a semiconductor device


A semiconductor device formed in a semiconductor substrate having a first main surface comprises a transistor array and a termination region. The transistor array comprises a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region.

08/18/16
20160240654 

Semiconductor device manufacturing method and semiconductor device


In order to improve the performance of a semiconductor device, a p type impurity is ion implanted into an area of an n type semiconductor film that is epitaxially grown over a p type semiconductor substrate, and the p type impurity is not ion implanted into an area of the n type semiconductor film, which is adjacent to the area in which the p type impurity is ion implanted. In this way, a p− type drift layer comprised of the area in which the p type impurity is introduced, as well as an n− type semiconductor region comprised of the area in which the p type impurity is not introduced are formed..
Renesas Electronics Corporation


08/18/16
20160240652 

Finfets with wrap-around silicide and ming the same


A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240651 

Structure and formation finfet device


Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a fin structure over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


08/18/16
20160240644 

Semiconductor devices and a forming a semiconductor device


A semiconductor device includes a first transistor structure including a first transistor body region of a first conductivity type located within a semiconductor substrate. At least part of the first transistor body region is located between a first source/drain region of the first transistor structure and a second source/drain region of the first transistor structure.
Infineon Technologies Ag


08/18/16
20160240642 

Semiconductor devices and a forming a semiconductor device


Some embodiments relate to a method for forming a semiconductor device. The method includes forming a source region of a field effect transistor structure in a semiconductor substrate.
Infineon Technologies Ag


08/18/16
20160240641 

Semiconductor device and manufacturing the semiconductor device


A semiconductor device includes: a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode. In the semiconductor substrate, a body region, a pillar region, and a barrier region are formed.
Toyota Jidosha Kabushiki Kaisha


08/18/16
20160240640 

Power semiconductor device


A semiconductor substrate has a first surface and a second surface. A gate electrode has a part buried in a first trench.
Mitsubishi Electric Corporation


08/18/16
20160240637 

Semiconductor device and semiconductor module


In a semiconductor device, an element forming region formed with a semiconductor element for controlling a current is defined on a surface of a semiconductor substrate. A termination region is defined so as to surround the element forming region.
Mitsubishi Electric Corporation


08/18/16
20160240636 

Bipolar junction transistor (bjt) base conductor pullback


Some embodiments are directed to a bipolar junction transistor (bjt) with a collector region formed within a body of a semiconductor substrate, and an emitter region arranged over an upper surface of the semiconductor substrate. The bjt includes a base region arranged over the upper surface of the semiconductor substrate, which vertically separates the emitter and collector regions.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/18/16
20160240633 

Semiconductor device


A p-type well is formed in a semiconductor substrate, and an n+-type semiconductor region and a p+-type semiconductor region are formed in the p-type well to be spaced apart from each other. The n+-type semiconductor region is an emitter semiconductor region of a bipolar transistor, and the p-type well and the p+-type semiconductor region are base semiconductor regions of the bipolar transistor.
Renesas Electronics Corporation


08/18/16
20160240627 

Methods of forming metal silicide layers including dopant segregation


A method of forming a metal silicide layer can include implanting dopants to a first depth below a surface of a semiconductor substrate including an active area. A metal-silicon composite layer can be formed on the semiconductor substrate and the metal-silicon composite layer can be silicided to form the metal silicide layer on the active area..
Samsung Electronics Co., Ltd.


08/18/16
20160240618 

Depression filling method and processing apparatus


A method of filling a depression of a workpiece is provided. The depression passes through an insulating film and extends up to an inside of a semiconductor substrate.
Tokyo Electron Limited


08/18/16
20160240615 

Semiconductor device and a forming a semiconductor device


A semiconductor device comprises at least one strip-shaped cell compensation region of a vertical electrical element arrangement, at least one strip-shaped edge compensation region and a bridge structure. The at least one strip-shaped cell compensation regions extends into a semiconductor substrate and comprises a first conductivity type.
Infineon Technologies Austria Ag


08/18/16
20160240613 

Iii-v semiconductor devices with selective oxidation


Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer..
International Business Machines Corporation


08/18/16
20160240583 

Cis chips and methods for forming the same


A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240570 

Dual photodiode image pixels with preferential blooming path


An image sensor with an array of image sensor pixels is provided. Each image sensor pixel may include a set of photodiodes formed in a semiconductor substrate, a color filter structure formed over the set of photodiodes, a microlens formed over the color filter structure, and associated pixel circuitry coupled to the set of photodiodes.
Semiconductor Components Industries, Llc


08/18/16
20160240553 

Nonvolatile memory device and manufacturing the same


A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.. .
Samsung Electronics Co., Ltd.


08/18/16
20160240543 

Semiconductor device manufacturing method and semiconductor device


A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.. .
Fujitsu Semiconductor Limited


08/18/16
20160240538 

Semiconductor device having buried gate, fabricating the same, and module and system having the same


A semiconductor device includes junction regions formed in upper portions of both sidewalls of a trench formed in a semiconductor substrate, a first gate electrode buried in the trench and having a stepped upper surface, and a second gate electrode formed on the first gate electrode to overlap a junction region.. .
Sk Hynix Inc.


08/18/16
20160240536 

Structure and formation finfet device


Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack and a second gate stack over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


08/18/16
20160240532 

Gate-all-around semiconductor device and fabricating the same


The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between sti regions at least one suspended nanostructure anchored by a source region and a drain region.
Imec Vzw


08/18/16
20160240530 

Finfet structure and forming same


A method of forming a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes fins formed thereon and a patterned hard mask layer formed on a top surface of the fins.
Semiconductor Manufacturing International (shanghai) Corporation


08/18/16
20160240528 

Igbt with built-in diode and manufacturing method therefor


An insulated gate bipolar translator (igbt) with a built-in diode and a manufacturing method thereof are provided. The igbt comprises: a semiconductor substrate (1) of the first conduction type which has a first major surface (1s1) and a second major surface (1s2), wherein the semiconductor substrate (1) comprises an active region (100) and a terminal protection area (200) which is located at the outer side of the active region; an insulated gate transistor unit which is formed at the side of the first major surface (1s1) of the active region (100), wherein a channel of the first conduction type is formed thereon during the conduction thereof; and first semiconductor layers (10) of the first conduction type and second semiconductor layers (11) of the second conduction type of the active region, which are formed at the side of the second major surface (1s2) of the semiconductor substrate (1) alternately, wherein the igbt only comprises the second semiconductor layers (11) in the terminal protection area (200) which is located at the side of the second major surface (1s2) of the semiconductor substrate (1)..
Csmc Technologies Fab1 Co., Ltd.


08/18/16
20160240499 

Semiconductor device and manufacturing the same


The semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad formed on an uppermost wiring layer of the plurality of wiring layers, a surface protection film which includes an opening on the pad and is made of an inorganic insulating film, a rewiring formed on the surface protection film; a pad electrode formed on the rewiring, and a wire connected to the pad electrode. The rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion which couples the pad electrode mounting portion and the connection portion, and the pad electrode mounting portion has a rectangular shape when seen in a plan view..

08/18/16
20160240484 

Semiconductor device and manufacturing same


To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a cu film, an ni film, and a pd film which have been formed successively from the side of a semiconductor substrate.
Renesas Electronics Corporation


08/18/16
20160240474 

Method, system and computer readable medium using stitching for mask assignment of patterns


A method comprises: accessing data representing a layout of a layer of an integrated circuit (ic) comprising a plurality of polygons defining circuit patterns to be divided among a number (n) of photomasks for multi-patterning a single layer of a semiconductor substrate, where n is greater than one. For each set of n parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least n−1 stitches are inserted in each polygon within that set to divide each polygon into at least n parts, such that adjacent parts of different polygons are assigned to different photomasks from each other.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/18/16
20160240469 

Semiconductor substrate, semiconductor package structure and making the same


The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer.
Advanced Semiconductor Engineering, Inc.


08/18/16
20160240462 

Semiconductor substrate structure, semiconductor package and manufacturing the same


The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump.
Advanced Semiconductor Engineering, Inc.


08/18/16
20160240454 

Semiconductor structure having thermal backside core


A semiconductor structure includes a semiconductor substrate having a recess disposed beneath a semiconductor device. The semiconductor structure also includes a thermally conductive core disposed in the recess, and a package substrate including a heat sink.
Avago Technologies General Ip (singapore) Pte. Ltd.


08/18/16
20160240444 

Method of semiconductor fabrication with height control through active region profile


The present disclosure provides a method for fabricating an integrated circuit in accordance with some embodiments. The method includes forming a trench on a semiconductor substrate, thereby defining fin active regions; extracting a profile of the fin active regions; determining an etch dosage according to the profile of the fin active regions; filling in the trench with a dielectric material; and performing an etching process to the dielectric material using the etch dosage, thereby recessing the dielectric material and defining a fin height of the fin active regions..
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240439 

Semiconductor device and method


A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240379 

Depression filling method and processing apparatus


A method of filling a depression of a workpiece is provided. The method includes forming a first thin film made of a semiconductor material substantially not containing an impurity along a wall surface which defines the depression, forming an epitaxial region conforming to crystals of the semiconductor substrate from the semiconductor material of the first thin film moved toward a bottom of the depression by annealing, etching the first thin film remaining on the wall surface, performing gas phase doping upon the epitaxial region, forming a second thin film made of a semiconductor material substantially not containing an impurity along the wall surface, further forming an epitaxial region from the semiconductor material of the second thin film moved toward the bottom of the depression by annealing, and performing gas phase doping upon the second thin film remaining on the wall surface and the epitaxial region..
Tokyo Electron Limited


08/18/16
20160240373 

Method for forming oxide layer by oxidizing semiconductor substrate with hydrogen peroxide


In some embodiments, an oxide layer is grown on a semiconductor substrate by oxidizing the semiconductor substrate by exposure to hydrogen peroxide at a process temperature of about 500° c. Or less.
Asm Ip Holding B.v.


08/18/16
20160240368 

Method and composition for selectively removing metal hardmask and other residues from semiconductor device substrates comprising low-k dielectric material and copper


An aqueous removal composition having a ph in the range of from 2 to 14 and method for selectively removing an etching mask consisting essentially of tin, tan, tinxoy, tiw, w, or alloy of ti or w relative to low-k materials from a semiconductor substrate comprising said low-k materials having a tin, tan, tinxoy, tiw, w, or alloy of ti or w etching mask thereon wherein the removal composition comprises at least one oxidizing agent and a carboxylate compound.. .
Ekc Technology, Inc.


08/18/16
20160240260 

Flash memory system using complementary voltage supplies


A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns.
Silicon Storage Technology, Inc.


08/18/16
20160238834 

Hybrid mems scanning module


A scanning device includes a base containing one or more rotational bearings disposed along a gimbal axis. A gimbal includes a shaft that fits into the rotational bearings so that the gimbal rotates about the gimbal axis relative to the base.
Apple Inc.


08/18/16
20160237569 

Semiconductor manufacturing apparatus


A semiconductor manufacturing apparatus according to an embodiment includes a heater, a sidewall, and a moving mechanism. The heater is capable of heating a semiconductor substrate.
Kabushiki Kaisha Toshiba


08/11/16
20160234443 

Digital camera with multiple pipeline signal processors


A method includes sampling a first intensity of light with a first array of photo detectors of a digital camera. A second intensity of light is sampled with a second array of photo detectors of the digital camera.
Callahan Cellular L.l.c.


08/11/16
20160233962 

High electron mobility transistor-based terahertz wave space external modulator


Terahertz external modulator based on high election mobility transistors belongs to the field of electromagnetic functional devices technology. This invention includes the semiconductor substrate (1), the epitaxial layer (2), and the modulation-unit array (4).
University Of Electronic Science And Technology Of China


08/11/16
20160233374 

Methods, apparatus, and systems for passivation of solar cells and other semiconductor devices


A method of passivating semiconductor devices using existing tools of junction isolation and phosphosilicate glass (psg)/borosilicate glass (bsg) etch via room temperature wet chemical growth (rtwcg) processes is provided. Back side processing of the semiconductor device achieves passivation and junction isolation in a single step, while front side processing achieves passivation, psg/bsg etch, anti-reflection coating and potential induced degradation (pid) mitigation simultaneously.
Special Materials Research And Technology Inc (specmat)


08/11/16
20160233372 

Method for producing a solar cell involving doping by ion implantation and depositing an outdiffusion barrier


The invention relates to a method for producing a solar cell (1) from crystalline semiconductor material, wherein a first doping region (5) is formed by means of ion implantation (s2) of a first dopant in a first surface (3a) of a semiconductor substrate (3), and a second doping region (7) is formed by means of ion implantation (s3) or thermal indiffusion of a second dopant in the second surface (3b) of the semiconductor substrate. After the doping of the second surface, a cap (9b) acting as an outdiffusion barrier for the second dopant is applied and an annealing step (s4) is subsequently carried out..
International Solar Energy Research Center Konstan Z E.v.


08/11/16
20160233359 

Solar cell and manufacturing the same


Discussed is a solar cell including a single crystalline semiconductor substrate having a first transparent conductive oxide layer positioned on a non-single crystalline emitter layer; a second transparent conductive oxide layer positioned over a rear surface of the single crystalline semiconductor substrate; a first electrode part including a first seed layer directly positioned on the first transparent conductive oxide layer; and a second electrode part including a second seed layer directly positioned on the second transparent conductive oxide layer, wherein the first transparent conductive oxide layer and the first seed layer have different conductivities, and wherein the second transparent conductive oxide layer and the second seed layer have different conductivities.. .
Lg Electronics Inc.


08/11/16
20160233315 

Dielectric isolated fin with improved fin profile


A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer.
International Business Machines Corporation


08/11/16
20160233305 

Direct formation of graphene on semiconductor substrates and structures prepared thereby


The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer.
Kansas State University Research Foundation


08/11/16
20160233297 

Semiconductor device having shallow trench isolation structure


A semiconductor device is provided, which prevents a case where the widths of word lines become uneven because of a stress developing at the border between a memory cell area and a peripheral circuit area. The semiconductor device 1 has a semiconductor substrate 2 on which a memory cell area mc defined by a peripheral isolation region 3c.
Micron Technology, Inc.


08/11/16
20160233266 

Semiconductor device and manufacturing method thereof


A method of forming a semiconductor image sensing device includes: providing a semiconductor substrate; forming a radiation sensitive region and a peripheral region in the semiconductor substrate, wherein the peripheral region surrounds the radiation sensitive region and includes a top surface projected from a backside of the semiconductor substrate and a sidewall coplanar with a sidewall of the semiconductor substrate and perpendicular to the top surface; forming a photon blocking spacer in the peripheral region, wherein the photon blocking spacer covers a portion of the sidewall of the peripheral region; and forming an anti reflective coating adjacent to the photon blocking layer.. .
Taiwan Semiconductor Manufacturing Company Ltd.


08/11/16
20160233263 

Image pickup device and manufacturing the same


A p-type well is defined by an isolation region formed in a semiconductor substrate. A pixel region and a ground region are defined in the p-type well.
Renesas Electronics Corporation


08/11/16
20160233257 

Implant isolated devices and forming the same


A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate and extends over the implant isolation region.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/11/16
20160233256 

High-k dielectric liners in shallow trench isolations


A circuit structure includes a semiconductor substrate having a top surface. A dielectric material extends from the top surface into the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/11/16
20160233245 

Formation of strained fins in a finfet device


In an aspect of the present invention, a field-effect transistor (fet) structure is formed. The fet structure comprises a plurality of fins formed on a semiconductor substrate, wherein the plurality of fins includes a set of fins that include a base portion that is comprised of relaxed silicon-germanium (sige) and an upper portion that is comprised of semiconductor material.
International Business Machines Corporation


08/11/16
20160233221 

Flash memory semiconductor device


The present disclosure provides a method of fabricating a flash memory semiconductor device. In one embodiment, a method of fabricating a resistive memory array includes providing a semiconductor substrate having at least one memory cell array region and at least one shunt region, forming a control gate electrode on the memory cell array region and the shunt region, depositing a dielectric film lamination and a conductive film to cover the control gate electrode and the semiconductor substrate, forming two recesses respectively corresponding to two sides of the control gate electrode on the shunt region, patterning the conductive film to form two sidewall memory gate electrodes and one top memory gate electrode, removing one of the sidewall memory gate electrodes on the memory cell array region, and removing the dielectric film lamination which is exposed from the memory gate electrodes..
Taiwan Semiconductor Manufacturing Co., Ltd.


08/11/16
20160233219 

Coaxial carbon nanotube capacitor for edram


A deep trench (dt) opening is provided in a semiconductor substrate and then conducting carbon nanotubes are formed within the dt. Each conducting carbon nanotube is coated with a high k dielectric material and thereafter the remaining volume of the dt is filled with a conductive material..
International Business Machines Corporation


08/11/16
20160233215 

Formation of semiconductor device with resistors


A semiconductor device includes a semiconductor substrate, trench isolations, a sacrificial layer, a first resist protect oxide (rpo) layer, a second rpo layer and a silicide layer. The semiconductor substrate has first portions and second portions which are alternately disposed, and each of the second portions includes a first resist region with a first resistance, a second resist region with a second resistance and a silicide region.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/11/16
20160233214 

Semiconductor device


A semiconductor device includes a semiconductor substrate; and a temperature sense diode fixed on the semiconductor substrate. The temperature sense diode includes: an anode electrode; a p-type semiconductor layer being in contact with the anode electrode; an n-type semiconductor layer being in contact with the p-type semiconductor layer; and a cathode electrode being in contact with the n-type semiconductor layer; and the anode electrode.
Toyota Jidosha Kabushiki Kaisha


08/11/16
20160233212 

Metal-insulator-metal capacitor structure


A capacitor structure in a semiconductor device includes a semiconductor substrate having a top surface and a bottom surface opposite the top surface, an isolation region having a top surface and a bottom surface, opposite the top surface, the bottom surface of the isolation region being disposed on the top surface of the semiconductor substrate. The capacitor structure also includes a gate terminal structure disposed on the top surface of the isolation region and a diffusion contact structure disposed on the top surface of the isolation region and arranged parallel to the gate terminal structure.
Broadcom Corporation


08/11/16
20160233201 

Composite protection circuit, composite protection element, and led device for illumination


A zener diode used as an esd protection element is connected in parallel to a circuit to be protected, for example an led chip. The zener diode is connected in parallel to an antifuse element.
Murata Manufacturing Co., Ltd.


08/11/16
20160233176 

Method of manufacturing semiconductor device


A method for manufacturing a semiconductor device includes attaching a semiconductor substrate to a support substrate in a heated state, and processing the semiconductor substrate attached to the support substrate. The support substrate has a linear coefficient different from that of the semiconductor substrate.
Toyota Jidosha Kabushiki Kaisha


08/11/16
20160233155 

Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device


In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench.

08/11/16
20160233154 

Semiconductor device


The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover.
Renesas Electronics Corporation


08/11/16
20160233133 

Finfet with dummy gate on non-recessed shallow trench isolation (sti)


An embodiment fin field effect transistor (finfet) device includes fins formed from a semiconductor substrate, a non-recessed shallow trench isolation (sti) region disposed between the fins, and a dummy gate disposed on the non-recessed sti region.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


08/11/16
20160233130 

Method for manufacturing diode


A diode manufacturing method provided herein includes first-third implantations and a heating. The first implantation implants n-type impurities into a first range at a first depth.
Toyota Jidosha Kabushiki Kaisha


08/11/16
20160233123 

Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device is provided. The method includes a process of applying liquid to one surface of a support substrate; a process of warping the support substrate by a volume change due to a phase transition of the liquid by solidifying the liquid; a process of attaching a semiconductor substrate having a linear expansion coefficient different from that of the support substrate to the support substrate in a heated state; and a process of warping the support substrate due to a linear expansion coefficient difference between the semiconductor substrate and the support substrate by cooling the support substrate to which the semiconductor substrate is attached.
Toyota Jidosha Kabushiki Kaisha


08/11/16
20160233114 

Chambers for particle reduction in substrate processing systems


A substrate processing system includes a chamber configured to process a semiconductor substrate. At least one surface of the chamber includes a high surface area finish.
Lam Research Corporation


08/11/16
20160233105 

Method of forming a trench in a semiconductor device


A method to make a semiconductor device, a first sio2 layer and a first si3n4 layer are sequentially formed on the semiconductor substrate. The first sio2 layer and the first si3n4 layer are then patterned as etching mask to form a trench in a semiconductor substrate by a trench etching process.
Changzhou Zhongmin Semi-tech Co. Ltd.


08/11/16
20160233101 

Polishing apparatus, polishing method, and semiconductor manufacturing method


A polishing apparatus includes a polisher, a holder, and a supplier. The polisher polishes a semiconductor substrate or a polishing target film on a semiconductor substrate.
Kabushiki Kaisha Toshiba


08/11/16
20160233093 

Method for photodepositing a particle on a graphene-semiconductor hybrid panel and a semiconductor structure


A method for photodepositing a particle on a graphene-semiconductor hybrid panel is disclosed. The method for photodepositing the particle on the graphene-semiconductor includes providing a graphene-semiconductor hybrid panel, dipping the graphene-semiconductor hybrid panel in a fluid containing a precursor, and irradiating the graphene-semiconductor hybrid panel using a light source until the precursor has been reduced or oxidized to form a particle photodeposited on a surface of a graphene sheet.
National Sun Yat-sen University


08/11/16
20160233081 

Apparatuses and methods for depositing sic/sicn films via cross-metathesis reactions with organometallic co-reactants


Disclosed herein are methods of forming sic/sicn film layers on surfaces of semiconductor substrates. The methods may include introducing a silicon-containing film-precursor and an organometallic ligand transfer reagent into a processing chamber, adsorbing the silicon-containing film-precursor, the organometallic ligand transfer reagent, or both onto a surface of a semiconductor substrate under conditions whereby either or both form an adsorption-limited layer, and reacting the silicon-containing film-precursor with the organometallic ligand transfer reagent, after either or both have formed the adsorption-limited layer.
Novellus Systems, Inc.


08/11/16
20160233080 

Silicon carbide semiconductor substrate and manufacturing same


A silicon carbide semiconductor substrate includes a first main surface and a second main surface opposite to the first main surface. The first main surface has a maximum diameter of more than 100 mm, and the silicon carbide semiconductor substrate has a thickness of not more than 700 μm.
Sumitomo Electric Industries, Ltd.


08/11/16
20160232828 

Electronic device with color sensing ambient light sensor


An electronic device may be provided with a display mounted in a housing. A color sensing ambient light sensor may measure the color of ambient light.
Apple Inc.


08/11/16
20160231265 

Analysis package


According to one embodiment, an analysis package including an analysis chip provided on a main surface of a semiconductor substrate, the chip including a flow channel, both ends of which are open at peripheral parts of the substrate, and a microaperture which is provided in a middle of the flow channel and which allows a particle to pass therethrough, a package board on which the chip is mounted, liquid receivers provided on the package board, the liquid receivers being connected to openings, and electrodes, at least parts of which are provided on parts of bottom surfaces of the liquid receivers, the electrodes being provided at positions corresponding to an upstream side and a downstream side of the microaperture.. .
Kabushiki Kaisha Toshiba


08/11/16
20160230019 

Metal hardmask composition and processes for forming fine patterns on semiconductor substrates


The present invention relates to a novel composition with improved stability containing soluble, multi-ligand-substituted metal compound, a polyol compound and a solvent useful for filling material on photoresist patterns with good trench or via filling properties of microlithographic features, where the filled patterns having good plasma etch resistance in oxygen based plasmas and are used as a hard mask in forming fine patterns on semiconductor substrates by pattern transfer of this hard mask. The present invention further relates to using the novel composition in methods for manufacturing electronic devices..
Az Electronic Materials (luxembourg) S.a.r.l


08/04/16
20160227603 

Front-end integrated circuit for wlan applications


Front-end integrated circuit for wireless local area network wlan applications. In some embodiments, a semiconductor die can include a semiconductor substrate, and a power amplifier implemented on the semiconductor substrate and configured for wlan transmit operation associated with a frequency range.
Skyworks Solutions, Inc.


08/04/16
20160227330 

Acoustic sensor


An acoustic sensor adapted to convert acoustic vibration to a change in an electrostatic capacitance to detect the acoustic vibration is provided. The acoustic sensor includes a semiconductor substrate, a back plate including a fixed plate arranged to face a surface of the semiconductor substrate, and a fixed electrode film arranged on the fixed plate, and a vibrating electrode film arranged to face the back plate with a space formed therebetween.
Omron Corporation


08/04/16
20160226510 

D/a conversion circuit, oscillator, electronic apparatus, and moving object


A d/a conversion circuit includes a plurality of resistors that are formed on a semiconductor substrate and that are connected in series to each other and a plurality of switches that are connected to the plurality of resistors, respectively, in which the plurality of resistors are configured using resistive element and a plurality of contacts that are provided to the resistive element, in which the plurality of switches are arranged side by side along a first direction when the semiconductor substrate is viewed from above, in which distances in the first direction between the plurality of contacts are equal to each other, and in which lengths in a second direction that is perpendicular to the first direction, of the plurality of resistors are unequal to each other.. .
Seiko Epson Corporation


08/04/16
20160226487 

Semiconductor device


A semiconductor device includes: a first external terminal which receives an input voltage; a second external terminal which outputs a switch voltage; a third external terminal connected to a first ground; a fourth external terminal connected to a second ground; a first internal switch element formed on a semiconductor substrate to be connected between the first and second external terminals; a second internal switch element formed on the semiconductor substrate to be connected between the second external terminal and the third external terminal; and a control circuit connected to the fourth external terminal to drive at least one of the first internal switch element and the second internal switch element. The semiconductor substrate is electrically connected with the third external terminal rather than the fourth external terminal, and parasitic elements accompanied between the semiconductor substrate and each of the first internal switch element and the second internal switch element..
Rohm Co., Ltd.


08/04/16
20160226486 

Semiconductor device and semiconductor relay using same


A semiconductor device includes an input circuit, an output circuit, an insulation circuit, and a semiconductor substrate. The insulation circuit includes at least one capacitor for electrically insulating the input circuit and the output circuit from each other.
Panasonic Intellectual Property Management Co., Ltd.


08/04/16
20160226442 

Phase noise reduction in voltage controlled oscillators


A voltage controlled oscillator (vco), a method of designing a voltage controlled oscillator, and a design structure comprising a semiconductor substrate including a voltage controlled oscillator are disclosed. In one embodiment, the vco comprises an lc tank circuit for generating an oscillator output at an oscillator frequency, and an oscillator core including cross-coupled semiconductor devices to provide feedback to the tank circuit.
International Business Machines Corporation


08/04/16
20160226441 

Phase noise reduction in voltage controlled oscillators


A voltage controlled oscillator (vco), a method of designing a voltage controlled oscillator, and a design structure comprising a semiconductor substrate including a voltage controlled oscillator are disclosed. In one embodiment, the vco comprises an lc tank circuit for generating an oscillator output at an oscillator frequency, and an oscillator core including cross-coupled semiconductor devices to provide feedback to the tank circuit.
International Business Machines Corporation


08/04/16
20160226222 

Complementary metal oxide semiconductor device with iii-v optical interconnect having iii-v epitaxial semiconductor material formed using lateral overgrowth


An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate.
International Business Machines Corporation


08/04/16
20160225989 

Variable resistance memory device and manufacturing the same


A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed.
Sk Hynix Inc.


08/04/16
20160225985 

Variable resistance memory device and manufacturing the same


A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed.
Sk Hynix Inc.


08/04/16
20160225938 

Method for producing a photovoltaic solar cell having at least one heterojunction passivated by means of hydrogen diffusion


The invention relates to a method for producing a photovoltaic solar cell having at least one hetero-junction, including the following steps: a) providing a semiconductor substrate having base doping; b) producing a hetero-junction on at least one side of the semiconductor substrate, which hetero-junction has a doped hetero-junction layer and a dielectric tunnel layer arranged indirectly or directly between the hetero-junction layer and the semiconductor substrate; c) heating at least the hetero-junction layer in order to improve the electrical quality of the heterojunction. The invention is characterized in that, in a step d after step c, hydrogen is diffused into the hetero-junction layer and/or to the interface between the tunnel layer and the semiconductor substrate..
Fraunhofer-gesellschaft Zur Förderung Der Angewan Dten Forschung E.v.


08/04/16
20160225935 

Solar cell and manufacturing the same


A method for manufacturing a solar cell, the method comprising: forming an emitter region that forms a p-n junction with a semiconductor substrate of a first conductive type; forming a passivation layer on the semiconductor substrate; forming a dopant layer containing impurities of the first conductive type on the passivation layer; and locally forming a back surface field region at the semiconductor substrate by irradiating laser beams onto the semiconductor substrate to diffuse the impurities of the first conductive type into the semiconductor substrate.. .
Lg Electronics Inc.


08/04/16
20160225929 

Photovoltaic device


A photoelectric conversion device includes a crystalline semiconductor substrate having a first surface and a second surface and a first amorphous semiconductor layer formed over the first surface of the crystalline semiconductor substrate. An interface between the crystalline semiconductor substrate and the first amorphous semiconductor layer is an oxidized interface containing oxygen having a concentration of 1×1021/cm3 or greater.
Panasonic Intellectual Property Management Co., Ltd.


08/04/16
20160225910 

Nonvolatile semiconductor storage device and manufacturing the same


According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.. .
Kabushiki Kaisha Toshiba


08/04/16
20160225903 

Method and device for high k metal gate transistors


A method of manufacturing a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes a dummy gate structure formed thereon and an offset spacer formed on a sidewall of the dummy gate structure.
Semiconductor Manufacturing International (shanghai) Corporation


08/04/16
20160225900 

Semiconductor device and forming the same


A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line.
Sk Hynix Inc.


08/04/16
20160225899 

Ultra high voltage semiconductor device with electrostatic discharge capabilities


A method includes forming a drain region in a first layer on a semiconductor substrate. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/04/16
20160225895 

Non-planar semiconductor structure with preserved isolation region


A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, a drain well in each of the raised structures, and a drain in each drain well. The structure further includes an isolation region in each drain well adjacent the drain, each isolation region reaching to a top surface of the corresponding raised structure, and a conductive center gate on each raised structure, the conductive center gate covering a top surface, a front surface and a back surface thereof, and covering a portion of the isolation region opposite the drain.
Globalfoundries Inc.


08/04/16
20160225894 

Wide band gap semiconductor device


A semiconductor device comprises an n+ type sic semiconductor substrate, an n type low concentration drift layer of an sic semiconductor on the substrate, p type channel regions selectively arranged in the drift layer with a specified distance between the channel regions, an n type source region selectively arranged in the channel region, a source electrode in common contact with the source region and the channel region, and a gate electrode disposed over the drift layer between two channel regions, and over a part of the channel region positioned between the drift layer and the source region intercalating a gate oxide film therebetween. The drift layer has a low concentration of at most 70% of the concentration that is required to exhibit a specified withstand voltage at a minimum on resistance..
Fuji Electric Co., Ltd.


08/04/16
20160225887 

Control of current collapse in thin patterned gan


A gan device is formed on a semiconductor substrate having a plurality of recessed regions formed in a surface thereof. A seed layer, optional buffer layer, and gallium nitride layer such as a carbon-doped gallium nitride layer are successively deposited within the recessed regions improved current collapse response of the gan device is attributed to maximum length and width dimensions of the multilayer stack..
Massachusetts Institute Of Technology


08/04/16
20160225878 

Method of forming a self-aligned stack gate structure for use in a non-volatile memory array


A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction.
Silicon Storage Technology, Inc.


08/04/16
20160225877 

Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device may include forming a cavity between two insulating portions that are positioned on a semiconductor substrate. The cavity may include a first cavity portion and a second cavity portion.
Semiconductor Manufacturing International (shanghai) Corporation


08/04/16
20160225853 

Graphene growth on a carbon-containing semiconductor layer


A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms.
Globalfoundries Inc.


08/04/16
20160225851 

Semiconductor structure and forming the same


Disclosed is a semiconductor structure, comprising: a semiconductor substrate and multilayer superfine silicon lines, wherein a profile shape of each of the multilayer superfine silicon lines is controlled dually by a crystal orientation of the substrate and an axial crystal orientation of the line. Also disclosed is a method of forming the same comprises: forming a fin-shaped silicon island (fin) and a source-drain region on the two ends thereof via an etching process; preparing a corrosion shielding layer for silicon; and forming multilayer superfine silicon lines.
Peking University


08/04/16
20160225846 

Integration techniques for mim or mip capacitors with flash memory and/or high-k metal gate cmos technology


Some embodiments of the present disclosure relate to an integrated circuit (ic) arranged on a semiconductor substrate, which includes a flash region, a capacitor region, and a logic region. An upper substrate surface of the capacitor region is recessed relative to respective upper substrate surfaces of the flash and logic regions, respectively.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/04/16
20160225844 

Capacitor structure and making the same


A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/04/16
20160225804 

Backside illumination image sensor and reducing dark current of backside illumination image sensor


A backside illumination image sensor and a method for reducing a dark current of the backside illumination image sensor. The backside illumination image sensor comprises: a photodiode, a first conductive type isolated layer (120); a gate structure of a pass transistor, corresponding to the first conductive type isolated layer (120) and formed on an upper surface of a first conductive type semiconductor substrate (100), the gate structure (130) comprising: gate oxide (131), a gate layer (132), and a gate sidewall (133), and the gate structure (130) correspondingly covering the photodiode; and a floating diffusion zone (140), formed in the first conductive type semiconductor substrate (100) and having second conductive type heavy doping.
Galaxycore Shanghai Limited Corporation


08/04/16
20160225802 

Mechanisms for forming image-sensor device with deep-trench isolation structure


An image-sensor device is provided. The image-sensor device includes a semiconductor substrate having a front surface and a back surface, and an interconnection structure formed over the front surface.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/04/16
20160225780 

Method of forming a logic compatible flash memory


A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/04/16
20160225778 

Non-volatile memory device and manufacturing the same


A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a core region and a peripheral region, and prior to forming a metal silicide in the core region, forming a sidewall layer on opposite sides of a gate structure of a core region device. The sidewall layer includes sequentially, from the inside out, a silicon oxide layer, a first silicon nitride layer, a first silicon nitride layer, a second silicon oxide layer, and a second silicon nitride layer, or the sidewall layer includes, from inside out, a first silicon nitride layer and a second silicon nitride layer.
Semiconductor Manufacturing International (shanghai) Corporation


08/04/16
20160225776 

Method to improve floating gate uniformity for non-volatile memory devices


The present disclosure relates an integrated circuit (ic) for an embedded flash memory device. In some embodiments, the ic includes a memory array region and a boundary region surrounding the memory array region disposed over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/04/16
20160225761 

Semiconductor device having a plurality of fins and fabricating the same


A semiconductor device having a plurality of fins including at least one first fin and at least one second fin formed on a semiconductor substrate is provided. Each of the first fin and second fin has a first portion and a second portion.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/04/16
20160225722 

Semiconductor device and manufacturing method, and electronic apparatus


The present disclosure relates to a semiconductor device and a manufacturing method, and an electronic apparatus that enable manufacturing of a stacked structure with high precision. A solid-state image sensor includes a semiconductor substrate where a photodiode is formed, and an epitaxial layer where a transfer transistor to be stacked on the photodiode of the semiconductor substrate is formed, the epitaxial layer being formed by growing a crystalline layer with aligned crystal axes on the semiconductor substrate.
Sony Corporation


08/04/16
20160225711 

Semiconductor device


A semiconductor device includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.. .
Rohm Co., Ltd.


08/04/16
20160225708 

Semiconductor substrate and manufacturing method thereof


A semiconductor substrate includes an insulating layer and a conductive circuit layer embedded at a surface of the insulating layer. The conductive circuit layer includes a first portion and a second portion.
Advanced Semiconductor Engineering, Inc.


08/04/16
20160225668 

Tsv formation processes using tsv-last approach


A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/04/16
20160225659 

Methods of forming fin isolation regions on finfet semiconductor devices by implantation of an oxidation-retarding material


One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, the fin having a lower first section that contains an oxidation-retarding implant region and an upper second section that is substantially free of the oxidation-retarding implant region, forming a sidewall spacer on opposite sides of the upper portion of the fin, forming a first layer of insulating material adjacent the sidewall spacers and the upper second section of the lower portion of the fin, and, with the first layer of insulating material in position, performing a thermal anneal process to convert the portion of the upper second section of the fin that is in contact with the first layer of insulating material into an oxide fin isolation region positioned under the fin above the lower first section of the fin.. .
International Business Machines Corporation


08/04/16
20160225638 

Grass removal in patterned cavity etching


A method of manufacturing a semiconductor device includes providing a first semiconductor substrate having a first main surface and an opposing second main surface, and forming a pattern into the first semiconductor substrate. The pattern includes a plurality of trenches defining a plurality of mesas.
Icemos Technology Ltd.


08/04/16
20160225635 

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device includes forming a plurality of active fins over a semiconductor substrate, sequentially forming first and second hard mask layers over the active fins, forming a first hard mask pattern by etching the second hard mask layer, trimming the first hard mask pattern to form a trimmed hard mask pattern, forming a first photo resist pattern over the first hard mask layer, forming second hard mask patterns by etching the first hard mask layer by using the trimmed hard mask pattern and the first photo resist pattern as an etching mask, and forming active fin patterns by etching the active fins by using the second hard mask patterns as an etching mask.. .
Samsung Electronics Co., Ltd.


08/04/16
20160225634 

Method for quadruple frequency finfets with single-fin removal


A method of single-fin removal for quadruple density fins. A first double density pattern of first sidewall spacers is produced on a semiconductor substrate from first mandrels formed by a first mask using a minimum pitch.
International Business Machines Corporation


08/04/16
20160225630 

Structure and formation semiconductor device with metal gate stack


A method for forming a semiconductor device structure is provided. The method includes forming a metal gate stack over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/04/16
20160225608 

Preparing a semiconductor surface for epitaxial deposition


Provided is a method of epitaxial deposition, which involves dry-etching a semiconductor substrate with a fluorine containing species and exposing the dry-etched substrate to hydrogen atoms, prior to epitaxially depositing a semiconductor layer to the surface of the substrate.. .
Aixtron




Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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