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Semiconductor Substrate patents



      
           
This page is updated frequently with new Semiconductor Substrate-related patent applications. Subscribe to the Semiconductor Substrate RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Substrate RSS RSS


Stacked semiconductor nanowires with tunnel spacers

Stacked semiconductor nanowires with tunnel spacers

Iintegrated circuit package using silicon-on-oxide interposer substrate with through-silicon vias

Iintegrated circuit package using silicon-on-oxide interposer substrate with through-silicon vias

Iintegrated circuit package using silicon-on-oxide interposer substrate with through-silicon vias

Method and system for template assisted wafer bonding

Date/App# patent app List of recent Semiconductor Substrate-related patents
11/20/14
20140343223
 Process for the production of polyimide and polyamic ester polymers patent thumbnailnew patent Process for the production of polyimide and polyamic ester polymers
This disclosure relates to a process of purifying a polymer. The process includes (a) providing an organic solution containing a polyimide or polyamic ester in at least one polar, aprotic polymerization solvent; (b) adding at least one purification solvent to the organic solution to form a diluted organic solution, the at least one purification solvent is less polar than the at least one polymerization solvent and has a lower water solubility than the at least one polymerization solvent at 25° c.; (c) washing the diluted organic solution with water or an aqueous solution to obtain a washed organic solution; and (d) removing at least a portion of the at least one purification solvent in the washed organic solution to obtain a solution containing a purified polyimide or polyamic ester.
11/20/14
20140342546
 Copper pillar bump with cobalt-containing sidewall protection layer patent thumbnailnew patent Copper pillar bump with cobalt-containing sidewall protection layer
A method of forming an integrated circuit device comprises forming a metal pillar over a semiconductor substrate. The method also comprises forming a solder layer over the metal pillar.
11/20/14
20140342543
 Method and apparatus for single step selective nitridation patent thumbnailnew patent Method and apparatus for single step selective nitridation
Methods and apparatus for selective one-step nitridation of semiconductor substrates is provided. Nitrogen is selectively incorporated in silicon regions of a semiconductor substrate having silicon regions and silicon oxide regions by use of a selective nitridation process.
11/20/14
20140342539
 Semiconductor device having mixedly mounted components with common film layers and method of manufacturing the same patent thumbnailnew patent Semiconductor device having mixedly mounted components with common film layers and method of manufacturing the same
A metal gate electrode and a poly-silicon resistance element are mixedly mounted in the same semiconductor substrate. The metal gate electrode is formed on a first gate insulating film and includes a first gate metal film and a first gate silicon film.
11/20/14
20140342535
 Method for manufacturing semiconductor substrate patent thumbnailnew patent Method for manufacturing semiconductor substrate
A semiconductor substrate preventing a void from being generated in an epitaxial film buried in a trench. An n-type first epitaxial film and first trenches are formed on an n+-type substrate body.
11/20/14
20140342526
 Method for manufacturing semiconductor substrate patent thumbnailnew patent Method for manufacturing semiconductor substrate
A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an n−-type layer formed on an n+-type substrate.
11/20/14
20140342525
 Method for manufacturing semiconductor substrate patent thumbnailnew patent Method for manufacturing semiconductor substrate
A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an n−-type layer formed on an n+-type substrate.
11/20/14
20140342522
 Reducing variation by using combination epitaxy growth patent thumbnailnew patent Reducing variation by using combination epitaxy growth
A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (e/g) ratio of process gases used in the first growth stage; and performing a second growth stage with a second e/g ratio of process gases used in the second growth stage different from the first e/g ratio..
11/20/14
20140342518
 Power mosfet structure and method patent thumbnailnew patent Power mosfet structure and method
A power mosfet includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness.
11/20/14
20140342500
 Method and system for template assisted wafer bonding patent thumbnailnew patent Method and system for template assisted wafer bonding
A method of fabricating a composite semiconductor structure includes providing a substrate including a plurality of devices and providing a compound semiconductor substrate including a plurality of photonic devices. The method also includes dicing the compound semiconductor substrate to provide a plurality of photonic dies.
11/20/14
20140341503
new patent Semiconductor substrate for photonic and electronic structures and method of manufacture
A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and photolithographic technique is used to fabricate a mask defining openings for etching first and second trench isolation areas in a substrate, with the openings for the second trench isolation areas being wider than the openings for the first trench isolation areas.
11/20/14
20140340967
new patent Split gate nand flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
A split gate nand flash memory structure is formed on a semiconductor substrate of a first conductivity type. The nand structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region.
11/20/14
20140339707
new patent Thermal dissipation through seal rings in 3dic structure
A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die.
11/20/14
20140339706
new patent Integrated circuit package with an interposer formed from a reusable carrier substrate
An integrated circuit package includes an interposer and an integrated circuit die. The interposer is formed from a layer of semiconductor material that is separated from a bulk portion of a semiconductor substrate, and the integrated circuit die is coupled to the interposer.
11/20/14
20140339705
new patent Iintegrated circuit package using silicon-on-oxide interposer substrate with through-silicon vias
An integrated circuit package includes an integrated circuit package comprising an interposer and an integrated circuit die. The interposer is formed from a silicon-on-insulator semiconductor substrate and includes a plurality of through-silicon vias, and the integrated circuit die is electrically coupled to a first through-silicon via included in the plurality of through-silicon vias.
11/20/14
20140339698
new patent Semiconductor device with through-substrate via covered by a solder ball and related method of production
The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate.
11/20/14
20140339684
new patent Synthetic diamond coated compound semiconductor substrates
A method of fabricating a synthetic diamond coated compound semiconductor substrate, the method comprising: loading a composite substrate into a chemical vapour deposition (cvd) reactor, the composite substrate comprising a single crystal carrier wafer, a layer of single crystal compound semiconductor epitaxially grown on the carrier wafer, and an interface layer disposed on the layer of compound semiconductor, the interface layer forming a growth surface suitable for growth of synthetic diamond material thereon via a cvd technique; and growing a layer of cvd diamond material on the growth surface of the interface layer, wherein during growth of cvd diamond material a temperature difference at the growth surface between an edge and a centre point thereof is maintained to be no more than 80° c., and wherein the carrier wafer has an aspect ratio, defined by a ratio of thickness to width, of no less than 0.25/100.. .
11/20/14
20140339682
new patent Semiconductor device and method for manufacturing semiconductor device
Provided are a semiconductor device in which abrasive grain marks are formed in a surface of a semiconductor substrate, a dopant diffusion region has a portion extending in a direction which forms an angle included in a range of −5° to +5° with a direction in which the abrasive grain marks extend, and the dopant diffusion region is formed by diffusing a dopant from a doping paste placed on one surface of the semiconductor substrate; and a method for manufacturing the semiconductor device.. .
11/20/14
20140339680
new patent Iii-v device and method for manufacturing thereof
The disclosure relates to a method for manufacturing a iii-v device and the iii-v device obtained therefrom. The method comprises providing a semiconductor substrate including at least a recess area and forming a buffer layer overlying the semiconductor substrate in the recess area.
11/20/14
20140339679
new patent Nitride semiconductor substrate
A nitride semiconductor substrate suitable for a high withstand voltage power device is provided in which current collapse is controlled, while reducing leakage current. In a nitride semiconductor substrate, wherein a buffer layer, an active layer, and an electron supply layer, each comprising a group 13 nitride, are stacked one by one on a silicon single crystal substrate, the buffer layer has a structure where a multilayer stack in which a pair of nitride layers having different concentrations of al or ga are repeatedly deposited a plurality of times on an initial layer of alxga1-xn (0≦x≦1) is stacked, and includes a doping layer whose carbon concentration is 1×1018 to 1×1021 cm−3 and whose si concentration is 1×1017 to 1×1020 cm−3, a thickness of the doping layer is 15% or more of the total thickness of the buffer layer..
11/20/14
20140339645
new patent Methods of forming semiconductor devices with different insulation thicknesses on the same semiconductor substrate and the resulting devices
One method includes forming first and second devices by forming a first layer of gate insulation material having a first thickness for the first device, forming a layer of high-k insulation material having a second thickness that is less than the first thickness for the second device and forming first and second metal-containing gate electrode structures that contact the first layer of gate insulation material and the high-k insulation material. A device disclosed herein includes first and second semiconductor devices wherein the first gate structure comprises a layer of insulating material having a first portion of a first metal layer positioned on and in contact with the layer of insulating material and a second gate structure comprised of a layer of high-k insulation material and a second portion of the first metal layer positioned on and in contact with the layer of high-k insulation material..
11/20/14
20140339637
new patent Method of forming semiconductor device
A semiconductor device may include a semiconductor substrate, a first conductive type well and a second conductive type drift region in the semiconductor substrate, the drift region including a first drift doping region and a second drift doping region, the second drift doping region vertically overlapping the well, and a first conductive type body region in the well, the body region being in contact with a side of the first drift doping region. The first drift doping region and the second doping region may include a first conductive type dopant and a second conductive type dopant, and an average density of the first conductive type dopant in the first drift doping region may be less than an average density of the first conductive type dopant in the second drift doping region..
11/20/14
20140339626
new patent Memory device having stitched arrays of 4 f+hu 2 +l memory cells
A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts..
11/20/14
20140339622
new patent Nonvolatile semiconductor memory device and manufacturing method thereof
A nonvolatile semiconductor memory device includes a semiconductor substrate, a memory cell array having memory cells arranged along a first direction that is transverse to a second direction in which word lines for the memory cells extend, each memory cell including a charge accumulation layer provided over the semiconductor substrate, a control gate electrode provided over the charge accumulation layer, and an inter insulating film provided between the charge accumulation layer and the control gate electrode. The inter insulating film is wider along the first direction than the charge accumulation layer and covers opposing side surfaces of an upper portion of the charge accumulation layer in the first direction.
11/20/14
20140339619
new patent Semiconductor device
Solution: the semiconductor device 1, includes: a semiconductor substrate 10 of a p-type having a principal surface 10a; an element isolation insulating film 131 that partitions one end of an active region k1 embedded in the principal surface 10a; a gate electrode 311 embedded interposing a gate insulating film 30 in a gate trench gt1 provided on the principal surface 10a so as to pass through the active region k1; a semiconductor pillar p1 disposed between the gate trench gt1 and the element isolation insulating film 131; an upper diffusion layer 201 of an n-type disposed on an upper part of the semiconductor pillar p1; a lower diffusion layer 211 of an n-type disposed to span from a lower side of the gate trench gt1 to a lower side of the semiconductor pillar p1; and a side face diffusion layer 111 disposed between the element isolation insulating film 131 and the semiconductor pillar p1 and containing an impurity of a p-type having a concentration higher than an impurity concentration of the lower diffusion layer 211.. .
11/20/14
20140339614
new patent Image sensor and method of fabricating the same
The present invention provides an image sensor and a method of fabricating the same. The image sensor comprises a semiconductor substrate, a photosensitive component, and a pixel-readout circuit, characterized in that, the semiconductor substrate comprises a supporting substrate, a first insulating buried layer, a first semiconductor layer, a second insulating buried layer, and a second semiconductor layer covered on the semiconductor substrate in sequence; the first semiconductor layer and the second semiconductor layer have different thicknesses, such that the photosensitive component is in the thicker semiconductor layer, and the pixel-readout circuit is in the thinner semiconductor layer.
11/20/14
20140339613
new patent Semiconductor device and method of manufacturing same
In one embodiment, a semiconductor device includes a semiconductor substrate, and a gate insulator arranged on the semiconductor substrate. The device further includes a gate electrode including a semiconductor layer and a metal layer which are sequentially arranged on the gate insulator.
11/20/14
20140339611
new patent Stacked semiconductor nanowires with tunnel spacers
A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material.
11/20/14
20140339600
new patent Semiconductor device
A trench gate mos structure is provided on one main surface of a semiconductor substrate which will be an n− drift region. An n shell region is provided in the n− drift region so that it contacts a surface of a p base region close to the n− drift region forming the trench gate mos structure.
11/20/14
20140339589
new patent Method for producing a polychromatizing layer and substrate and also light-emitting diode having a polychromatizing layer
The invention relates to a method for applying a polychromatizing layer which contains at least one luminescent means on a semiconductor substrate, which layer is suitable for producing a monochromatic light. The polychromatizing layer is applied with a printing process, especially with a micro-contact printing process.
11/20/14
20140339559
new patent Semiconductor device having test structure
A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures.
11/20/14
20140339507
new patent Stacked semiconductor nanowires with tunnel spacers
A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material.
11/20/14
20140339313
new patent Semiconductor device and an identification tag
A semiconductor device includes a semiconductor substrate, a battery attached to the semiconductor substrate, and a sensor attached to the semiconductor substrate. The battery is electrically connected to the sensor and configured to supply the sensor with electrical power..
11/20/14
20140338747
new patent Solar cell and method for manufacturing the same
Discussed is a solar cell including a semiconductor substrate including a base area and a doping area, a doping layer formed on the semiconductor substrate, the doping layer having a conductive type different from the doping area, a tunneling layer interposed between the doping layer and the semiconductor substrate, a first electrode connected to the doping area, and a second electrode connected to the doping layer.. .
11/13/14
20140337897
Systems and methods for receiving and transferring video information
Devices and methods for receiving and/or processing digital data. The devices may include a satellite modem, a transport module, and/or a processing module.
11/13/14
20140335698
Component of a plasma processing apparatus having a protective in situ formed layer on a plasma exposed surface
A component of a plasma processing chamber having a protective liquid layer on a plasma exposed surface of the component. The protective liquid layer can be replenished by supplying a liquid to a liquid channel and delivering the liquid through liquid feed passages in the component.
11/13/14
20140335682
Semiconductor device and manufacturing method thereof
A semiconductor device according to an embodiment includes a first-conductive-type semiconductor substrate; a first-conductive-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductive-type second semiconductor layer epitaxially formed on the first semiconductor layer; and a second-conductive-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer. The semiconductor device also includes a recess formed in the third semiconductor layer, and at least a corner portion of a side face and a bottom surface is located in the second semiconductor layer.
11/13/14
20140335671
Non-volatile memory having 3d array of read/write elements with vertical bit lines and select devices and methods thereof
A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them.
11/13/14
20140335651
Inks and pastes for solar cell fabrication
A silicon solar cell is formed with an n-type silicon layer on a p-type silicon semiconductor substrate. An aluminum ink composition is printed on the back of the silicon wafer to form back contact electrodes.
11/13/14
20140334596
Electronic device
A single-crystal semiconductor layer is separated from a single-crystal semiconductor substrate and is fixed to an insulating substrate to form a tft over the insulating substrate. Then, a driver circuit is formed using the tft.
11/13/14
20140334052
Structure and method for self protection of power device with expanded voltage ranges
A vertical semiconductor power device includes a top surface and a bottom surface of a semiconductor substrate constituting a vertical current path for conducting a current there through. The semiconductor power device further includes an over current protection layer composed of a material having a resistance with a positive temperature coefficient (ptc) and the over current protection layer constituting as a part of the vertical current path connected to a source electrode and providing a feedback voltage a gate electrode of the vertical semiconductor power device for limiting a current passing there through for protecting the semiconductor power device at any voltage..
11/13/14
20140333149
Circuit device
A circuit device includes a semiconductor substrate, a first inductor provided over the semiconductor substrate, and a second inductor provided over the semiconductor substrate and coupled to the first inductor. The first inductor and second inductor are wound in a same direction with each other from respective inner end portions to respective outer end portions thereof..
11/13/14
20140332985
Chip package and manufacturing method thereof
A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area.
11/13/14
20140332977
Semiconductor device
A semiconductor device includes a metal pad formed over a semiconductor substrate; a dummy metal pad spaced apart from the metal pad by an open region; and a polymide isoindro quirazorindione (piq) layer formed to cover the open region and to define a pad open region by exposing a center part of the metal pad. The semiconductor device forms an additional open region at a region spaced apart from an edge part of the pad open region, preventing short-circuiting between the metal pad and the adjacent circuit line which might be caused by a crack generated at the edge of the pad open region when a probe is connected to the metal pad, and further preventing a defective semiconductor device from being generated..
11/13/14
20140332958
Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process
A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ono structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ono structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and etching the hard mask layer, the top-layer amorphous silicon, the ono structured hard mask and the bottom-layer amorphous silicon in accordance with the photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer α-si.
11/13/14
20140332954
Semiconductor device
Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5).
11/13/14
20140332932
Shallow trench and fabrication method
Various embodiments provide shallow trenches and fabrication methods. In an exemplary method, a semiconductor substrate can be provided.
11/13/14
20140332922
Programmable electrical fuse with temperature gradient between anode and cathode
In some examples, a programmable electrical fuse includes at least one structural feature that increases a thermal gradient between an anode and a cathode of the programmable electrical fuse. For example, a device may include a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and a programmable electrical fuse overlying a portion of the electrically insulating layer.
11/13/14
20140332919
Termination design for nanotube mosfet
A termination structure for a semiconductor power device includes a plurality of termination groups formed in a lightly doped epitaxial layer of a first conductivity type over a heavily doped semiconductor substrate of a second conductivity type. Each termination group includes a trench formed in the lightly doped epitaxial layer of the first conductivity type.
11/13/14
20140332904
System and methods for converting planar design to finfet design
A finfet structure layout includes a semiconductor substrate comprising a plurality of finfet active areas, and a plurality of fins within each finfet active area of the plurality of finfet active areas. The finfet structure layout further includes a gate having a gate length parallel to the semiconductor substrate and perpendicular to length of the plurality of fins within each finfet active area of the plurality of finfet active areas.
11/13/14
20140332901
Semiconductor device with notched gate
A semiconductor device includes a semiconductor substrate, a body region disposed in the semiconductor substrate and having a first conductivity type, a source region disposed in the semiconductor substrate adjacent the body region and having a second conductivity type, a drain region disposed in the semiconductor substrate, having the second conductivity type, and spaced from the source region to define a conduction path, a gate structure supported by the semiconductor substrate, configured to control formation of a channel in the conduction path during operation, and having a side adjacent the source region that comprises a notch, the notch defining a notch area, and a notch region disposed in the semiconductor substrate in the notch area and having the first conductivity type.. .
11/13/14
20140332896
Semiconductor device and method for forming the same
A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a peripheral region including the first region, the second region, and a third region; a second active region defined by the device isolation film contained in the semiconductor substrate of the third region; a buried metal layer buried in the recess; a first conductive layer formed over the semiconductor substrate of the first region; and a second conductive layer formed over the semiconductor substrate of the second region, wherein the first conductive layer or the second conductive layer is formed over the semiconductor substrate of the third region. A three-dimensional dual gate is formed in a peripheral region, such that performance or throughput of transistors is maximized even in the peripheral region..
11/13/14
20140332887
Silicon-on-insulator integrated circuits with local oxidation of silicon and methods for fabricating the same
Silicon-on-insulator integrated circuits with local oxidation of silicon and methods for fabricating the same are provided. An integrated circuit includes a semiconductor substrate and a plurality of shallow trench isolation (sti) regions, each extending at least a first depth below an upper surface of the semiconductor substrate.
11/13/14
20140332882
Trench junction barrier controlled schottky
A method for manufacturing a schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.. .
11/13/14
20140332881
Semiconductor device
A semiconductor device includes a transistor array, including first transistors and second transistors. Gate electrodes of the first transistors are disposed in first trenches in a first main surface of a semiconductor substrate, and gate electrodes of the second transistors are disposed in second trenches in the first main surface.
11/13/14
20140332877
Semiconductor device
A switching component includes a control element and an integrated circuit. The integrated circuit includes a first transistor element and a second transistor element electrically connected in parallel to the first transistor element.
11/13/14
20140332872
Semiconductor device and method for forming the same
A semiconductor device includes a semiconductor substrate including a pad region and a peripheral region, a first buffer layer formed to include a capacitor over the semiconductor substrate in the pad region, a second buffer layer formed to include a first contact pad over the first buffer layer, and a third buffer layer formed to include a second contact pad over the first contact pad. The semiconductor device, by additionally forming a buffer layer at a lower part in the pad region, reduces a stress caused by wire bonding.
11/13/14
20140332869
Solid-state image pickup device
A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2.
11/13/14
20140332855
Reduced short channel effect of iii-v field effect transistor via oxidizing aluminum-rich underlayer
In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of iii-v semiconductor substrate. The iii-v semiconductor substrate including a iii-v base substrate layer, an aluminum containing iii-v semiconductor layer that is present on the iii-v base substrate layer, and a iii-v channel layer.
11/13/14
20140332851
Reduced short channel effect of iii-v field effect transistor via oxidizing aluminum-rich underlayer
In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of iii-v semiconductor substrate. The iii-v semiconductor substrate including a iii-v base substrate layer, an aluminum containing iii-v semiconductor layer that is present on the iii-v base substrate layer, and a iii-v channel layer.
11/13/14
20140332846
Transistor-type protection device, semiconductor integrated circuit, and manufacturing method of the same
A transistor-type protection device includes: a semiconductor substrate; a well including a first-conductivity-type semiconductor formed in the semiconductor substrate; a source region including a second-conductivity-type semiconductor formed in the well; a gate electrode formed above the well via a gate insulating film at one side of the source region; a drain region including the second-conductivity-type semiconductor formed within the well apart at one side of the gate electrode; and a resistive breakdown region including a second-conductivity-type semiconductor region in contact with the drain region at a predetermined distance apart from the well part immediately below the gate electrode, wherein a metallurgical junction form and a impurity concentration profile of the resistive breakdown region are determined so that a region not depleted at application of a drain bias when junction breakdown occurs in the drain region or the resistive breakdown region may remain in the resistive breakdown region.. .
11/13/14
20140332845
Topside structures for an insulated gate bipolar transistor (igbt) device to achieve improved device perforemances
This invention discloses an insulated gate bipolar transistor (igbt) device formed in a semiconductor substrate. The igbt device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment.
11/13/14
20140332844
A process method and structure for high voltage mosfets
This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface.
11/13/14
20140332840
Semiconductor light emitting device and fabrication method of the semiconductor light emitting device
A semiconductor light emitting device which can control of current density and can optimize current density and in which a rise in luminosity is possible, and a fabrication method of the semiconductor light emitting device are provided. The semiconductor light emitting device including: a semiconductor substrate structure including a semiconductor substrate, a first metal layer placed on a first surface of the semiconductor substrate, and a second metal layer placed on a second surface of the semiconductor substrate; and a light emitting diode structure including a third metal layer placed on the semiconductor substrate structure, a current control layer placed on the third metal layer and composed of a transparent insulating film and a current control electrode, an epitaxial growth layer placed on the current control layer, and a surface electrode placed on the epitaxial growth layer, wherein the semiconductor substrate structure and the light emitting diode structure are bonded by using the first metal layer and the third metal layer..
11/13/14
20140332824
Semiconductor structure with different fins of finfets
A semiconductor structure for forming finfets is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the finfets on the substrate, and a plurality of even fins of the finfets on the substrate between the odd fins of the finfets.
11/13/14
20140332816
Semiconductor device
A semiconductor device includes a first insulating film formed on a memory cell region of the semiconductor substrate, a first polysilicon layer formed on the first insulating film, and memory cell transistors formed on the first polysilicon layer, each including a charge storage layer, an inter-electrode insulating film and a control gate electrode. The semiconductor device further includes a laminated structure formed on a peripheral circuit region of the semiconductor substrate that includes a second insulating film, a second polysilicon layer, a third insulating film, a third polysilicon layer, a fourth insulating film formed from the same material as a material of the inter-electrode insulating film, and a first electrode formed from the same material as a material of the control gate electrode.
11/13/14
20140332749
Semiconductor device and method of manufacturing same
A semiconductor device includes: a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening.. .
11/13/14
20140332692
Semiconductor drift detector and corresponding operating method
The invention relates to a semiconductor drift detector for detecting radiation, comprising a semiconductor substrate (hs), in which signal charge carriers are generated during operation, to be precise by incident photons (h·f) having a specific photon energy, more particularly in the form of x-ray fluorescent radiation, and/or by incident electrons (θ), having a specific signal charge carrier current, more particularly in the form of back-scattered electrons (θ), and comprising a read-out anode (a) for generating an electrical output signal in a manner dependent on the signal charge carriers, and comprising an erase contact (rc) for erasing the signal charge carriers that have accumulated in the semiconductor substrate (hs). The invention provides for the semiconductor drift detector to be optionally operable in a first operating mode or in a second operating mode, wherein the semiconductor drift detector in the first operating mode measures the photon energy of the incident photons (h·f), whereas the semiconductor drift detector in the second operating mode measures the signal charge carrier current.
11/13/14
20140332670
Photodetecting circuit, optical receiver, and photocurrent measurement method for photo detector
The present invention is a photodetecting circuit comprising a plurality of operational amplifiers provided so as to correspond to respective photo detectors disposed on a common semiconductor substrate, each operational amplifier having an inverting input terminal connected to a cathode of the photo detector and a non-inverting input terminal supplied with a voltage to be applied to the photo detector; a plurality of resistances connected between output terminals and inverting input terminals of the respective operational amplifiers; and a terminal, disposed on at least the inverting input terminal side in both ends of the resistance, for connecting with a meter for measuring a photocurrent of the photo detector.. .
11/13/14
20140332665
Photosensitive imaging devices and associated methods
A monolithic sensor for detecting infrared and visible light according to an example includes a semiconductor substrate and a semiconductor layer coupled to the semiconductor substrate. The semiconductor layer includes a device surface opposite the semiconductor substrate.
11/13/14
20140332663
Compact detection array having improved polarization conditions
An array of photodetector is organized along a first organizational axis on a semiconductor substrate of a first conductivity type. Each photodetector is at least partially formed in the substrate which forms a first electrode of the photodetector.


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Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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