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Semiconductor Substrate patents



      
           
This page is updated frequently with new Semiconductor Substrate-related patent applications. Subscribe to the Semiconductor Substrate RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Substrate RSS RSS


Chemical mechanical polishing pad with broad spectrum, endpoint detection window and method of polishing therewith

Process sheet resistance uniformity improvement using multiple melt laser exposures

Methods for fabricating integrated circuits utilizing silicon nitride layers

Date/App# patent app List of recent Semiconductor Substrate-related patents
09/11/14
20140256226
 Broad spectrum, endpoint detection window chemical mechanical polishing pad and polishing method patent thumbnailBroad spectrum, endpoint detection window chemical mechanical polishing pad and polishing method
A chemical mechanical polishing pad is provided, comprising: a polishing layer having a polishing surface; and, a broad spectrum, endpoint detection window block having a thickness along an axis perpendicular to a plane of the polishing surface; wherein the broad spectrum, endpoint detection window block, comprises an olefin copolymer; wherein the olefin copolymer, comprises, as initial components: ethylene, a branched or straight chain c3-30 α-olefin; a silane; and, optionally, a polyolefin; wherein the broad spectrum, endpoint detection window block exhibits a uniform chemical composition across its thickness; wherein the broad spectrum, endpoint detection window block exhibits a spectrum loss ≦60%; and, wherein the polishing surface is adapted for polishing a substrate selected from a magnetic substrate, an optical substrate and a semiconductor substrate.. .
09/11/14
20140256225
 Chemical mechanical polishing pad with broad spectrum, endpoint detection window and method of polishing therewith patent thumbnailChemical mechanical polishing pad with broad spectrum, endpoint detection window and method of polishing therewith
A chemical mechanical polishing pad is provided, comprising: a polishing layer having a polishing surface; and, a broad spectrum, endpoint detection window block having a thickness along an axis perpendicular to a plane of the polishing surface; wherein the broad spectrum, endpoint detection window block, comprises a cyclic olefin addition polymer; wherein the broad spectrum, endpoint detection window block exhibits a uniform chemical composition across its thickness; wherein the broad spectrum, endpoint detection window block exhibits a spectrum loss ≦40%; and, wherein the polishing surface is adapted for polishing a substrate selected from a magnetic substrate, an optical substrate and a semiconductor substrate.. .
09/11/14
20140256161
 Process sheet resistance uniformity improvement using multiple melt laser exposures patent thumbnailProcess sheet resistance uniformity improvement using multiple melt laser exposures
Embodiments described herein relate to apparatus and methods of thermal processing. More specifically, apparatus and methods described herein relate to laser thermal treatment of semiconductor substrates by increasing the uniformity of energy distribution in an image at a surface of a substrate..
09/11/14
20140256141
 Methods for fabricating integrated circuits utilizing silicon nitride layers patent thumbnailMethods for fabricating integrated circuits utilizing silicon nitride layers
A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (pecvd) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval.
09/11/14
20140256138
 Method and equipment for removing photoresist residue after dry etch patent thumbnailMethod and equipment for removing photoresist residue after dry etch
A method for removing photoresist residue includes etching a photoresist layer disposed over a front side of a semiconductor substrate during fabrication of a semiconductor device, and exposing at least one of the front side and the back side of the semiconductor substrate to an atmosphere comprising active oxygen. The method further includes cleaning at least one of the front side and the back side of the semiconductor substrate with a cleaning fluid..
09/11/14
20140256124
 In-situ metal gate recess process for self-aligned contact application patent thumbnailIn-situ metal gate recess process for self-aligned contact application
A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (cmp) processes to planarize the formed gate structure using a cmp tool.
09/11/14
20140256112
 Semiconductor devices and methods of fabricating the same patent thumbnailSemiconductor devices and methods of fabricating the same
Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate.
09/11/14
20140256107
 High gate density devices and methods patent thumbnailHigh gate density devices and methods
A method of forming a semiconductor device includes providing a semiconductor substrate and forming a plurality of dummy gate structures in the substrate. The method further includes forming sidewall spacers on sidewalls of the dummy gate structures and forming a plurality of epitaxial growth regions between the dummy gate structures.
09/11/14
20140256097
 Methods for forming integrated circuit systems employing fluorine doping patent thumbnailMethods for forming integrated circuit systems employing fluorine doping
A method for forming a semiconductor device is provided which includes providing a gate structure in an active region of a semiconductor substrate, wherein the gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to the gate structure and, thereafter, performing a fluorine implantation process. Also a method for forming a cmos integrated circuit structure is provided which includes providing a semiconductor substrate with a first active region and a second active region, forming a first gate structure in the first active region and a second gate structure in the second active region, wherein each gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to each of the first and second gate structures and, thereafter, performing a fluorine implantation process..
09/11/14
20140256067
 Structure and method for e-beam in-chip overlay mark patent thumbnailStructure and method for e-beam in-chip overlay mark
The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction.
09/11/14
20140256066
Radiofrequency adjustment for instability management in semiconductor processing
Methods, systems, and computer programs are presented for reducing chamber instability while processing a semiconductor substrate. One method includes an operation for identifying a first recipe with steps having an operating frequency equal to the nominal frequency of a radiofrequency (rf) power supply.
09/11/14
20140256063
Contactless communications using ferromagnetic material
A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil.
09/11/14
20140256031
Semiconductor micro-analysis chip and sample liquid flowing method
According to one embodiment, a semiconductor micro-analysis chip for detecting fine particles in sample liquid includes a semiconductor substrate, a flow channel formed in the semiconductor substrate and having a sample liquid inlet and sample liquid outlet at end portions thereof, and an absorber provided on at least part of the sample outlet of the flow channel to absorb the sample liquid.. .
09/11/14
20140256028
Semiconductor micro-analysis chip and manufacturing method thereof
According to one embodiment, a semiconductor micro-analysis chip for detecting fine particles in sample liquid includes a semiconductor substrate, a first flow channel that is formed in the semiconductor substrate and into which the sample liquid is introduced, and a plurality of columnar structures fully arranged in the first flow channel at regulation distance.. .
09/11/14
20140255863
Thermal treatment apparatus
An aspect of one embodiment, there is provided a heat treatment apparatus, the apparatus installing a substrate retainer, which retains a plurality of semiconductor substrates in shelf structure, in a thermal treatment furnace to perform heat treatment with respect to the semiconductor substrates, including, a housing, a base plate installed in the housing, a substrate carrier fork placing the semiconductor substrates on the substrate retainer, a vertical shift unit fixed to the base plate, the vertical shift unit vertically driving and moving the substrate carrier fork, a fixing member fixing the base plate to the housing which enable the base plate to vertically move.. .
09/11/14
20140255862
Pyrometry filter for thermal process chamber
Embodiments of the invention generally relate to pyrometry during thermal processing of semiconductor substrates. More specifically, embodiments of the invention relate to a pyrometry filter for a thermal process chamber.
09/11/14
20140254991
Isolator
An isolator comprising: a first semiconductor substrate including a first electrical circuit; a second semiconductor substrate including a second electrical circuit; and at least one optical waveguide for data exchange between the first and second electrical circuits.. .
09/11/14
20140254270
Semiconductor memory device and data writing method of the same
A semiconductor memory device includes memory cells which are laminated on a semiconductor substrate and include charge storage layers and control gates, a plurality of word lines each of which is commonly connected to the control gates of a plurality of the memory cells, and a control unit which performs programming and verification of data in units of a page of memory cells. The control unit consecutively performs programming of data in two or more pages of memory cells connected to the same word line, and then consecutively performs verification of the data programmed in the two or more pages of memory cells connected to the same word line..
09/11/14
20140254022
Apparatus for speckle reduction, pulse stretching, and beam homogenization
Embodiments described herein relate to thermal processing of semiconductor substrates. More specifically, embodiments described herein relate to laser thermal processing of semiconductor substrates.
09/11/14
20140253772
Solid-state imaging device, imaging apparatus, and method of driving the solid-state imaging device
A solid-state imaging device including a semiconductor substrate; plural photoelectric conversion units formed side by side on the semiconductor substrate to form a light receiving unit; a peripheral circuit formed in a portion on an outside of the light receiving unit on the semiconductor substrate; a wiring section formed on the light receiving unit and formed for connecting the plural photoelectric conversion units and the peripheral circuit; and a dummy wiring section formed on an opposite side of the wiring section for at least one photoelectric conversion unit among the plural photoelectric conversion units on the light receiving unit and formed for functioning as a non-connected wiring section not connected to the photoelectric conversion units and the peripheral circuit, wherein the dummy wiring section has a predetermined potential.. .
09/11/14
20140253769
Dark current reduction in image sensors via dynamic electrical biasing
In various embodiments, an image sensor and method of using an image sensor are described. In an example embodiment, the image sensor comprises a semiconductor substrate and a plurality of pixel regions with each pixel region comprising an optically sensitive material over the substrate and positioned to receive light.
09/11/14
20140252651
Anchor vias for improved backside metal adhesion to semiconductor substrate
Disclosed is a structure having anchor vias for improved backside metal adhesion and an associated method for the structure's fabrication. The structure includes at least one anchor via disposed in at least one corner of a semiconductor substrate.
09/11/14
20140252642
Chip package and method for forming the same
An embodiment of the invention provides a chip package which includes: a semiconductor substrate; a device region formed in the semiconductor substrate; at least a conducting pad disposed over a surface of the semiconductor substrate; a protection plate disposed over the surface of the semiconductor substrate; and a spacer layer disposed between the surface of the semiconductor substrate and the protection plate, wherein the protection plate and the spacer layer surround a cavity over the device region, the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface.. .
09/11/14
20140252627
Semiconductor component comprising copper metallizations
A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy..
09/11/14
20140252622
Method for forming recess-free interconnect structure
A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. An oxygen-rich layer is formed over the dielectric material layer.
09/11/14
20140252620
Material and process for copper barrier layer
A method of fabricating a semiconductor device comprises forming a first dielectric material layer on a semiconductor substrate. The first dielectric material layer is patterned to form a plurality of vias therein.
09/11/14
20140252618
Method for forming interconnect structure that avoids via recess
A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein.
09/11/14
20140252617
Barrier layer conformality in copper interconnects
A process of modulating the thickness of a barrier layer deposited on the sidewalls and floor of a recessed feature in a semiconductor substrate is disclosed. The process includes altering the surface of the conductive feature on which the barrier layer is deposited by annealing in a reducing atmosphere and optionally additionally, silylating the dielectric surface that forms the sidewalls of the recessed feature..
09/11/14
20140252616
Electroless fill of trench in semiconductor structure
A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier.
09/11/14
20140252611
Ball amount process in the manufacturing of integrated circuit
An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a post-passivation interconnect (ppi) over the polymer layer. The ppi is electrically connected to the metal pad.
09/11/14
20140252597
Directly sawing wafers covered with liquid molding compound
A method includes forming a passivation layer over a metal pad, wherein the metal pad is further overlying a semiconductor substrate of a wafer. A post-passivation interconnect (ppi) is formed to electrically couple to the metal pad, wherein a portion of the ppi is overlying the passivation layer.
09/11/14
20140252589
Charge dissipation of cavities
Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.. .
09/11/14
20140252562
Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied.
09/11/14
20140252550
Stack capacitor structure and manufacturing method thereof
The present invention provides a stack capacitor structure and a manufacturing method thereof, adapted for a random access memory. The stack capacitor structure is formed on a semiconductor substrate.
09/11/14
20140252546
Switched capacitor structure
A capacitor structure comprising semiconductor substrate and a matrix of capacitor units formed over the semiconductor substrate each capacitor unit. The matrix includes an interior structure comprised of one or more vertical plates, each vertical plate of the interior structure formed from a plurality of conductive portions connected vertically to each other, an exterior structure comprised of one or more vertical plates, each vertical plate of the exterior structure formed from a plurality of conductive portions connected vertically to each other, the exterior structure substantially encompassing the interior structure, and insulative material separating the interior and exterior structures.
09/11/14
20140252540
Semiconductor device and method of manufacturing thereof
A semiconductor device includes a semiconductor substrate having a first main surface in which a recess is formed. Further, the semiconductor device includes an electrical interconnect structure which is arranged at a bottom of the recess.
09/11/14
20140252535
Integrated passive device having improved linearity and isolation
Disclosed is a structure for improved electrical signal isolation in a semiconductor substrate between integrated passive devices (ipds) and an associated method for the structure's fabrication. The structure includes an amorphized region in the semiconductor substrate, a dielectric layer formed over the amorphized region, and ipds formed over the dielectric layer.
09/11/14
20140252528
Semiconductor photodetector and method for manufacturing the same
In order to improve reliability by preventing an edge breakdown in a semiconductor photodetector having a mesa structure such as a mesa apd, the semiconductor photodetector comprises a mesa structure formed on a first semiconductor layer of the first conduction type formed on a semiconductor substrate, the mesa structure including a light absorbing layer for absorbing light, an electric field buffer layer for dropping an electric field intensity, an avalanche multiplication layer for causing avalanche multiplication to occur, and a second semiconductor layer of the second conduction type, wherein the thickness of the avalanche multiplication layer at the portion in the vicinity of the side face of the mesa structure is made thinner than the thickness at the central portion of the mesa structure.. .
09/11/14
20140252521
Image sensor with improved dark current performance
Provided is a semiconductor image sensor device. The image sensor device includes a semiconductor substrate having a first side and a second side opposite the first side.
09/11/14
20140252505
Semiconductor analysis microchip and method of manufacturing the same
According to one embodiment, a semiconductor analysis microchip configured to detect a fine particle in a sample liquid, including a semiconductor substrate, a first flow channel provided in the semiconductor substrate, to which the sample liquid is introduced, and a pore provided in the first flow channel and configured to pass the fine particle in the sample liquid.. .
09/11/14
20140252501
Sacrificial replacement extension layer to obtain abrupt doping profile
At least one gate structure having a first spacer located on a vertical sidewall thereof is provided on an uppermost surface of a semiconductor substrate. Exposed portions of the semiconductor substrate are then removed utilizing the at least one gate structure and first spacer as an etch mask.
09/11/14
20140252500
Sacrificial replacement extension layer to obtain abrupt doping profile
At least one gate structure having a first spacer located on a vertical sidewall thereof is provided on an uppermost surface of a semiconductor substrate. Exposed portions of the semiconductor substrate are then removed utilizing the at least one gate structure and first spacer as an etch mask.
09/11/14
20140252493
Gate stack including a high-k gate dielectric that is optimized for low voltage applications
A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer.
09/11/14
20140252492
Gate stack including a high-k gate dielectric that is optimized for low voltage applications
A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer.
09/11/14
20140252479
Semiconductor fin isolation by a well trapping fin portion
A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate.
09/11/14
20140252472
Semiconductor device with increased safe operating area
A semiconductor device includes a substrate having a surface, a composite body region disposed in the substrate, having a first conductivity type, and comprising a body contact region at the surface of the substrate and a well in which a channel is formed during operation, a source region disposed in the semiconductor substrate adjacent the composite body region and having a second conductivity type, and an isolation region disposed between the body contact region and the source region. The composite body region further includes a body conduction path region contiguous with and under the source region, and the body conduction path region has a higher dopant concentration level than the well..
09/11/14
20140252465
Semiconductor device and method of producing the same
A semiconductor device has a semiconductor substrate including a body region, a drift region, a trench that extends from a surface of the semiconductor substrate into the drift region through the body region, and a source region located adjacent to the trench in a range exposed to the surface of the semiconductor substrate, the source region being isolated from the drift region by the body region. A specific layer is disposed on a bottom of the trench, and it has a characteristic of forming a depletion layer at a junction between the specific layer and the drift region.
09/11/14
20140252460
High density mosfet array with self-aligned contacts delimited by nitride-capped trench gate stacks and method
A high density trench-gated mosfet array and method are disclosed. It comprises semiconductor substrate partitioned into mosfet array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (anctgs) embedded till the epitaxial region.
09/11/14
20140252455
Structure and method for static random access memory device of vertical tunneling field effect transistor
The present disclosure provides one embodiment of a sram cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters. The pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (tfet) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel..
09/11/14
20140252444
Method of fabricating semiconductor device and device fabricated thereby
A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns.
09/11/14
20140252443
Nonvolatile semiconductor memory device
According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, a first layer formed above the semiconductor substrate, a first conductive layer, an inter-electrode insulating layer, and a second conductive layer sequentially stacked above the first layer, a memory film formed on an inner surface of each of a pair of through holes provided in the first conductive layer, the inter-electrode insulating layer, and the second conductive layer and extending in a stacking direction, a semiconductor layer formed on the memory film in the pair of through holes, and a metal layer formed in part of the pair of through holes and/or in part of a connection hole that is provided in the first layer and connects lower end portions of the pair of through holes, the metal layer being in contact with the semiconductor layer.. .
09/11/14
20140252442
Method and structure for vertical tunneling field effect transistor and planar devices
The present disclosure provides one embodiment of a method of forming a tunnel field effect transistor (tfet). The method includes forming a semiconductor mesa on a semiconductor substrate; performing a first implantation to the semiconductor substrate and the semiconductor mesa to form a drain of a first type conductivity; forming a first dielectric layer on the semiconductor substrate and sidewall of the semiconductor mesa; forming a gate stack on the sidewall of the semiconductor mesa and the first dielectric layer; forming a second dielectric layer on the first dielectric layer and the gate stack; and forming, on the semiconductor mesa, a source having a second type conductivity opposite to the first type conductivity.
09/11/14
20140252441
Semiconductor device and method of manufacturing same
A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed.
09/11/14
20140252435
Semiconductor device
A semiconductor device concerning an embodiment is provided with a plate-like semiconductor substrate, electrode pads, electrode connecting conductors, and a source electrode back pad. The semiconductor substrate has a first cutout section in a first side, and has a second cutout section and a third cutout section in a second side.
09/11/14
20140252434
Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes forming isolation layers in a first direction at trenches at isolation regions defined at a semiconductor substrate and forming gate lines in a second direction crossing the first direction over the isolation layers and active regions defined between the isolation layers, performing a dry-etch process to remove the isolation layers, and forming an insulating layer over the semiconductor substrate to form a first air gap extending in the first direction in the trenches and a second air gap extending in the second direction between the gate lines.. .
09/11/14
20140252431
Semiconductor device structure and method of forming same
An embodiment is a semiconductor device comprising a first gate structure over a semiconductor substrate, a first etch stop layer (esl) over the semiconductor substrate and the first gate, the first esl having a curved top surface, and a first inter-layer dielectric (ild) on the first esl, the first ild having a curved top surface. The semiconductor device further comprises a second esl on the first ild, the second esl having a curved top surface, and a second ild on the second esl..
09/11/14
20140252428
Semiconductor fin structures and methods for forming the same
An integrated circuit structure includes a semiconductor substrate, an insulation region extending into the semiconductor substrate, and a semiconductor strip between two opposite portions of the insulation region. The semiconductor strip includes an upper portion higher than top surfaces of the insulation regions and a lower portion in the insulation region.
09/11/14
20140252427
Self-aligned contacts for replacement metal gate transistors
Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface of the gate, depositing an insulating layer above the semiconductor device, and planarizing the insulating layer using the blocking region as a planarization stop.
09/11/14
20140252414
Passivated iii-v or ge fin-shaped field effect transistor
A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting of (a) iii-v compound layers and (b) a ge layer, and a coating overlaying the core.
09/11/14
20140252413
Silicon-germanium fins and silicon fins on a bulk substrate
A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is formed over a second region of the first silicon-germanium alloy layer.
09/11/14
20140252378
Semiconductor substrate and semiconductor device
According to one embodiment, a semiconductor substrate includes a substrate and a semiconductor layer. The substrate has a first surface and containing a silicon carbide.
09/11/14
20140252373
Semiconductor device and method for producing the same
A method for producing a semiconductor device is provided. The method includes providing a semiconductor substrate, providing at least one semiconductor device on the substrate, having a back face opposite the semiconductor substrate and a front face towards the semiconductor substrate, providing a contact layer on the back face of the semiconductor device, bonding the contact layer to an auxiliary carrier, and separating the at least one semiconductor device from the substrate.
09/11/14
20140252358
Methods and apparatus for mems devices with increased sensitivity
Methods and apparatus for forming mems devices. An apparatus includes at least a portion of a semiconductor substrate having a first thickness and patterned to form a moveable mass; a moving sense electrode forming the first plate of a first capacitance; at least one anchor patterned from the semiconductor substrate and having a portion that forms the second plate of the first capacitance and spaced by a first gap from the first plate; a layer of semiconductor material of a second thickness patterned to form a first electrode forming a first plate of a second capacitance and further patterned to form a second electrode overlying the at least one anchor and forming a second plate spaced by a second gap that is less than the first gap; wherein a total capacitance is formed that is the sum of the first capacitance and the second capacitance.
09/11/14
20140251424
Solar cell
A solar cell is disclosed. The solar cell includes a semiconductor substrate, a conductive region formed at the semiconductor substrate and having a conductive type identical to or different from that of the semiconductor substrate, a passivation film formed on the semiconductor substrate so as to cover the conductive region, and an electrode electrically connected to at least one of the semiconductor substrate and the conductive region.
09/11/14
20140251422
Solar cell with doping blocks
A solar cell with doping blocks is provided, which includes: a semiconductor substrate, an anti-reflection layer, a plurality of front electrodes, and a back electrode layer. The semiconductor substrate has a first surface, and a plurality of doping block layers is arranged under the first surface and spaced from each other.
09/11/14
20140251421
Solar cell and method of manufacturing the same
A method of manufacturing solar cell includes providing a semiconductor substrate. A coating layer is then formed on a plurality of sides.
09/11/14
20140251408
System and method for manufacturing a temperature difference sensor
An embodiment of the invention relates to a seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield.
09/11/14
20140250714
Supercritical drying method for semiconductor substrate and supercritical drying apparatus
According to one embodiment, a supercritical drying method for a semiconductor substrate, comprises introducing the semiconductor substrate into a chamber in a state, a surface of the semiconductor substrate being wet with alcohol, substituting the alcohol on the semiconductor substrate with a supercritical fluid of carbon dioxide by impregnating the semiconductor substrate to the supercritical fluid in the chamber, and discharging the supercritical fluid and the alcohol from the chamber and reducing a pressure inside the chamber. The method further comprises performing a baking treatment by supplying an oxygen gas or an ozone gas to the chamber after the reduction of the pressure inside the chamber..
09/11/14
20140250658
Vacuum chambers and components for semiconductor substrate processing and methods of fabrication
Embodiments of methods for fabricating a vacuum chamber for semiconductor substrate processing are provided herein. In some embodiments, a method for fabricating a vacuum chamber for semiconductor substrate processing may include: providing one or more plates of material that together form a desired shape of a body of the vacuum chamber; performing a friction stir weld on outer surfaces of adjacent ends of the one or more plates to form the body of the vacuum chamber; and coupling at least one of a top or bottom to a respective top or bottom of the body to form the vacuum chamber..
09/04/14
20140248781
Semi-aqueous polymer removal compositions with enhanced compatibility to copper, tungsten, and porous low-k dielectrics
A composition is provided that is effective for removing post etch treatment (pet) polymeric films and photoresist from semiconductor substrates. The composition exhibits excellent polymer film removal capability while maintaining compatibility with copper and low-κ dielectrics and contains water, ethylene glycol, a glycol ether solvent, morpholinopropylamine and a corrosion inhibiting compound and optionally one or more metal ion chelating agent, one or more other polar organic solvent, one or more tertiary amine, one or more aluminum corrosion inhibition agent, and one or more surfactant..
09/04/14
20140248778
Methods of forming asymmetric spacers on various structures on integrated circuit products
One illustrative method disclosed herein includes forming a structure above a semiconductor substrate, performing a conformal deposition process to form a layer of undoped spacer material above the structure, performing an angled ion implant process to form a region of doped spacer material in the layer of undoped spacer material while leaving other portions of the layer of undoped spacer material undoped, and, after performing the angled ion implant process, performing at least one etching process that removes the undoped portions of the layer of undoped spacer material and thereby results in a sidewall spacer comprised of the doped spacer material positioned adjacent at least one side, but not all sides, of the structure.. .
09/04/14
20140248770
Microwave-assisted heating of strong acid solution to remove nickel platinum/platinum residues
A method is provided for removing residual ni/pt and/or pt from a semiconductor substrate in a post salicidation cleaning process using microwave heating of a stripping solution. Embodiments include depositing a ni/pt layer on a semiconductor substrate; annealing the deposited ni/pt layer, forming a nickel/platinum silicide and residual ni/pt and/or pt; removing the residual ni/pt and/or pt from the semiconductor substrate by: microwave heating a strong acid solution in a non-reactive container; exposing the residual ni/pt and/or pt to the microwave heated strong acid solution; and rinsing the semiconductor substrate with water h2o..
09/04/14
20140248765
Semiconductor memory device having dummy conductive patterns on interconnection and fabrication method thereof
A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area..
09/04/14
20140248760
Methods of forming dual gate structures
Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material.
09/04/14
20140248752
Method for fabricating semiconductor device having spacer elements
The present disclosure describes a method of fabricating semiconductor device including providing a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is formed on the substrate abutting the first gate stack.
09/04/14
20140248750
Vertical type semiconductor device and fabrication method thereof
A vertical memory device and a method of fabricating the same are provided. The vertical type semiconductor device includes a common source region formed in a cell area of a semiconductor substrate.
09/04/14
20140248745
Three-dimensional integrated circuit (3dic)
An embodiment 3dic device includes a semiconductor chip, a die, and a polymer. The semiconductor chip includes a semiconductor substrate, wherein the semiconductor substrate comprises a first edge, and a dielectric layer over the semiconductor substrate.
09/04/14
20140248744
Semiconductor substrate and method for manufacturing semiconductor device
Provided is a method for manufacturing a semiconductor device, which prevents waste generation from being caused peeling of films and prevents failure of peeling from being caused by waste due to peeling of films. A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate.
09/04/14
20140248734
Cmos image sensors and methods for forming the same
A method includes forming a first implantation mask comprising a first opening, implanting a first portion of a semiconductor substrate through the first opening to form a first doped region, forming a second implantation mask comprising a second opening, and implanting a second portion of the semiconductor substrate to form a second doped region. The first portion of the semiconductor substrate is encircled by the second portion of the semiconductor substrate.


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Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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