FreshPatents.com Logo
Enter keywords:  

Track companies' patents here: Public Companies RSS Feeds | RSS Feed Home Page
Popular terms

[SEARCH]

Semiconductor Substrate topics
Semiconductor Substrate
Semiconductor
Semiconductor Device
Gallium Nitride
Memory Cell
Phase Change Memory
Phase Change Material
Memory Device
Semiconductor Memory
Integrated Circuit
Transistors
Field Effect Transistor
Planarization
Conductive Layer
Semiconductor Devices

Follow us on Twitter
twitter icon@FreshPatents

Web & Computing
Cloud Computing
Ecommerce
Search patents
Smartphone patents
Social Media patents
Video patents
Website patents
Web Server
Android patents
Copyright patents
Database patents
Programming patents
Wearable Computing
Webcam patents

Web Companies
Apple patents
Google patents
Adobe patents
Ebay patents
Oracle patents
Yahoo patents

[SEARCH]

Semiconductor Substrate patents



      
           
This page is updated frequently with new Semiconductor Substrate-related patent applications. Subscribe to the Semiconductor Substrate RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Substrate RSS RSS


Method of forming trench in semiconductor substrate

United Microelectronics Corp.

Method of forming trench in semiconductor substrate

Semiconductor device and method for forming the same

Sk Hynix

Semiconductor device and method for forming the same

Semiconductor device and method for forming the same

Taiwan Semiconductor Manufacturing

Fin spacer protected source and drain regions in finfets

Date/App# patent app List of recent Semiconductor Substrate-related patents
04/23/15
20150111804
 Cleaning formulations for removing residues on surfaces patent thumbnailnew patent Cleaning formulations for removing residues on surfaces
This disclosure relates to a cleaning composition that contains 1) at least one chelating agent, the chelating agent being a polyaminopolycarboxylic acid; 2) at least one organic solvent selected from the group consisting of water soluble alcohols, water soluble ketones, water soluble esters, and water soluble ethers; 3) at least one monocarboxylic acid containing a primary or secondary amino group and at least one additional basic group containing nitrogen; 4) at least one metal corrosion inhibitor, the metal corrosion inhibitor being a substituted or unsubstituted benzotriazole; and 5) water. This disclosure also relates to a method of using the above composition for cleaning a semiconductor substrate..
Fujifilm Electronic Materials U.s.a., Inc.
04/23/15
20150111394
 Mechanisms for forming uniform film on semiconductor substrate patent thumbnailnew patent Mechanisms for forming uniform film on semiconductor substrate
Embodiments of mechanisms for forming a film deposition tool are provided. The film deposition tool includes a plasma source and a substrate processing region connected to the plasma source.
Taiwan Semiconductor Manufacturing Co., Ltd.
04/23/15
20150111385
 Method of forming trench in semiconductor substrate patent thumbnailnew patent Method of forming trench in semiconductor substrate
The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate.
United Microelectronics Corp.
04/23/15
20150111382
 Polishing composition to be used to polish semiconductor substrate having silicon through electrode structure, and polishing method using polishing composition patent thumbnailnew patent Polishing composition to be used to polish semiconductor substrate having silicon through electrode structure, and polishing method using polishing composition
Provided is a polishing composition used for polishing a semiconductor substrate having a through-silicon via structure, comprising an oxidizing agent having a standard electrode potential of 350 mv or more and 740 mv or less, a silicon polishing accelerating agent, a through-silicon via material polishing speed increasing agent, a silicon contamination preventing agent, and water.. .
Fujimi Incorporated
04/23/15
20150111356
 Mos device with isolated drain and  fabricating the same patent thumbnailnew patent Mos device with isolated drain and fabricating the same
A method for fabricating a metal-oxide-semiconductor (mos) device with isolated drain. The method performing operations of: forming a first well region embedded in a portion of a semiconductor substrate; forming a first patterned mask layer over the semiconductor substrate, exposing portions of the semiconductor substrate; performing a first ion implant process on the portions of the semiconductor substrate exposed by the first patterned mask layer; performing a second ion implant process to a second well region exposed, forming a fourth well region between the first well region and the second well region; performing a third implant process to the second well region, forming a fifth well region overlying the fourth well region; forming a source region in a portion of the third well region; and forming a drain region in a portion of the fifth well region..
Media Tek Inc
04/23/15
20150111355
 Finfets with different fin heights patent thumbnailnew patent Finfets with different fin heights
An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height.
Taiwan Semiconductor Manufacturing Company, Ltd.
04/23/15
20150111354
 Superjunction devices having narrow surface layout of terminal structures, buried contact regions and trench gates, and methods of manufacturing the devices patent thumbnailnew patent Superjunction devices having narrow surface layout of terminal structures, buried contact regions and trench gates, and methods of manufacturing the devices
Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at least a first side of the body contact region other than a portion of a first main surface of the semiconductor substrate..
Icemos Technology Ltd.
04/23/15
20150111349
 Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and  the formation thereof patent thumbnailnew patent Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and the formation thereof
A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region.
Globalfoundries Inc.
04/23/15
20150111348
 Semiconductor device and manufacturing  the same patent thumbnailnew patent Semiconductor device and manufacturing the same
A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the soi substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed.
04/23/15
20150111310
 Semiconductor device and  manufacturing the same patent thumbnailnew patent Semiconductor device and manufacturing the same
A lower electrode film, a ferroelectric film, and an upper electrode film are formed on an insulation film covering a transistor formed on a semiconductor substrate. Furthermore, a pt film is formed as a cap layer on the upper electrode film.
Fujitsu Semiconductor Limited
04/23/15
20150108969
new patent

On-chip linear variable differential transformer


A linear variable differential transformer (“lvdt”) including a semiconductor substrate and a plurality of coils formed at least partially on the substrate.. .
Texas Instruments Incorporated
04/23/15
20150108649
new patent

Method of forming hybrid diffusion barrier layer and semiconductor device thereof


In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall.
Taiwan Semiconductor Manufacturing Co., Ltd.
04/23/15
20150108647
new patent

Hybrid manganese and manganese nitride barriers for back-end-of-line metallization and methods for fabricating the same


A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening.
Globalfoundries, Inc.
04/23/15
20150108627
new patent

Electronic component and manufacturing electronic component


An electronic component comprises: a resin frame; a semicionductor substrate housed in the resin frame; a plate shape metal member having at least one end fixed in the resin frame at a position spaced apart from the semiconductor substrate; an electrical connection region portion formed on the surface on the side of the plate shape metal member of the semiconductor substrate with an electrically conductive material; and a solder layer formed on the surface on the side of the plate shape metal member of the electrical connection region portion, wherein the plate shape metal member supports the semiconductor substrate without contact through the solder layer and the electrical connection region portion, and is electrically connected to the electrical connection region portion.. .
Sumida Corporation
04/23/15
20150108619
new patent

Method for patterning a semiconductor substrate


Embodiments of the present disclosure provide methods for patterning rectangular features with a sequence of lithography, atomic layer deposition (ald) and etching. Embodiment of the present disclosure includes forming first line clusters along a first direction and second line clusters over the first line clusters in a direction traversing the first direction.
Applied Materials, Inc.
04/23/15
20150108598
new patent

Solid-state imaging device, manufacturing solid-state imaging device, and electronic apparatus


There is provided a solid-state imaging device including: a semiconductor substrate that is formed with a photodiode for each pixel; a light shielding film that is laminated on the semiconductor substrate on a side of a light irradiated surface which is irradiated with light, and is formed to include an opening corresponding to a spot in which at least the photodiode is arranged; and a photoelectric conversion film that is laminated to cover the light irradiated surface of the semiconductor substrate and the light shielding film, and is configured to generate an electrical charge by absorbing light. The photoelectric conversion film is formed of a material which has higher light absorptivity than light absorptivity of the semiconductor substrate..
Sony Corporation
04/23/15
20150108579
new patent

Semiconductor device


The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover.
Renesas Electronics Corporation
04/23/15
20150108574
new patent

Semiconductor device and forming the same


A semiconductor device has a semiconductor substrate including a cell region and a peripheral region and includes: a silicon-metal-silicon (sms)-structured wafer formed in the cell region, which includes a stacked structure of a first silicon substrate, a metal layer, and a second silicon substrate; and a silicon on insulator (soi)-structured wafer formed in the peripheral region, which includes a stacked structure of the first silicon substrate, a silicon insulation film, and the second silicon substrate.. .
Sk Hynix Inc.
04/23/15
20150108557
new patent

Metal-insulator-metal capacitor structure


A capacitor structure in a semiconductor device includes a semiconductor substrate having a top surface and a bottom surface opposite the top surface, an isolation region having a top surface and a bottom surface, opposite the top surface, the bottom surface of the isolation region being disposed on the top surface of the semiconductor substrate. The capacitor structure also includes a gate terminal structure disposed on the top surface of the isolation region and a diffusion contact structure disposed on the top surface of the isolation region and arranged parallel to the gate terminal structure.
Broadcom Corporation
04/23/15
20150108549
new patent

Formation of a high aspect ratio trench in a semiconductor substrate and a bipolar semiconductor device having a high aspect ratio trench isolation region


Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening.
International Business Machines Corporation
04/23/15
20150108544
new patent

Fin spacer protected source and drain regions in finfets


An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and second portion on opposite sides of the semiconductor fin.
Taiwan Semiconductor Manufacturing Company, Ltd.
04/23/15
20150108541
new patent

Semiconductor device


A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of igbts (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an igbt located at an extreme end in the one direction and an igbt located more centrally than the igbt located at the extreme end.
Renesas Electronics Corporation
04/23/15
20150108539
new patent

Fabrication semiconductor device and the semiconductor device


A fabrication method of a semiconductor device includes forming a mask insulating film having a specified thickness on the top surface of an n-type semiconductor substrate, forming an opening at a specified position in the mask insulating film, carrying out ion implantation with p-type impurity ions onto the top surface, removing a layer portion formed in the mask insulating film with the p-type impurities included by the ion implantation, and carrying out heat treatment to diffuse the p-type impurities implanted into the n-type semiconductor substrate from the opening to a depth, thereby forming the p-type isolation region.. .
Fuji Electric Co., Ltd.
04/23/15
20150108518
new patent

Nitride semiconductor light emitting device


A semiconductor light emitting device includes: a nitride semiconductor light emitting element including a nitride semiconductor substrate having a polar or semipolar surface and a nitride semiconductor multilayer film stacked on the polar or semipolar surface; and a mounting section to which the element is mounted. The nitride semiconductor multilayer film includes an electron block layer.
Panasonic Intellectual Property Management Co., Ltd.
04/23/15
20150108501
new patent

Semiconductor device


In an active region, p+ regions are selectively disposed in a surface layer of an n− drift layer on an n+ semiconductor substrate. A p-base layer is disposed on surfaces of the n− drift layer and the p+ regions, and an mos structure is disposed on the p-base layer.
Fuji Electric Co., Ltd.
04/23/15
20150108331
new patent

Method for manufacturing solid-state imaging element, solid-state imaging element, manufacturing electronic apparatus, and electronic apparatus


Disclosed herein is a method for manufacturing a solid-state imaging element, the method including forming lenses that are each provided corresponding to a light receiving part of a respective one of a plurality of pixels arranged in an imaging area over a semiconductor substrate and collect light onto the light receiving parts; forming a light blocking layer by performing film deposition on the lenses by using a material having light blocking capability; and forming a light blocker composed of the material having light blocking capability at a boundary part between the lenses adjacent to each other by etching the light blocking layer in such a manner that the material having light blocking capability is left at the boundary part between the lenses.. .
Sony Corporation
04/16/15
20150105308

Aqua regia and hydrogen peroxide hcl combination to remove ni and nipt residues


A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The sc2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate..
Globalfoundries, Inc.
04/16/15
20150104953

High uv curing efficiency for low-k dielectrics


One embodiment is a method for semiconductor processing. In this method, a precursor film is provided over a semiconductor substrate, where the precursor film is made of a structural former and porogen.
Taiwan Semiconductor Manufacturing Co., Ltd.
04/16/15
20150104952

Method and composition for selectively removing metal hardmask and other residues from semiconductor device substrates comprising low-k dielectric material and copper


An aqueous removal composition having a ph in the range of from 2 to 14 and method for selectively removing an etching mask consisting essentially of tin, tan, tinxoy, tiw, w, or alloy of ti or w relative to low-k materials from a semiconductor substrate comprising said low-k materials having a tin, tan, tinxoy, tiw, w, or alloy of ti or w etching mask thereon wherein the removal composition comprises at least one oxidizing agent and a carboxylate compound.. .
Ekc Technology, Inc.
04/16/15
20150104942

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device includes processing a semiconductor substrate using a plasma etching apparatus provided with a processing chamber. The semiconductor substrate has an uneasily-etched material formed thereabove and at least an upper layer film formed above the uneasily-etched material.
Kabushiki Kaisha Toshiba
04/16/15
20150104919

Three-dimensional semiconductor device, variable resistive memory device including the same, and manufacturing the same


A three-dimensional semiconductor device, a resistive variable memory device including the same, and a method of manufacturing the same are provided. The method may include forming a source on a semiconductor substrate, sequentially forming a first semiconductor layer formed of a first material, a second semiconductor layer formed of a second material having a higher oxidation rate than that of the first material, and a third semiconductor layer formed of the first material on the source; patterning the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; forming a lightly doped drain (ldd) region in the second semiconductor layer and a drain in the third semiconductor layer; oxidizing outer circumferences of the first semiconductor layer, the ldd region and the drain region to form a gate insulating layer; forming a gate on an outer circumference of the gate insulating layer to overlap the first semiconductor layer and a portion of the ldd region; foaming a heating electrode on the drain; and forming a variable resistance layer on the heating electrode..
Sk Hynix Inc.
04/16/15
20150104913

Simultaneous formation of source/drain openings with different profiles


A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.
04/16/15
20150104898

Method for manufacturing inverted metamorphic multijunction solar cells


A method of fabricating both a multijunction solar cell and an inverted metamorphic multijunction solar cell in a single process using a mocvd reactor by forming a first multijunction solar cell on a semiconductor substrate; forming a release layer over the first solar cell; forming an inverted metamorphic second solar cell over the release layer; and etching the release layer so as to separate the multijunction first solar cell and the inverted metamorphic second solar cell.. .
Emcore Solar Power, Inc.
04/16/15
20150104569

Barrier layers for silver reflective coatings and hpc workflows for rapid screening of materials for such barrier layers


Provided is high productivity combinatorial (hpc) testing methodology of semiconductor substrates, each including multiple site isolated regions. The site isolated regions are used for testing different compositions and/or structures of barrier layers disposed over silver reflectors.
Intermolecular Inc.
04/16/15
20150103349

Photodetector with controllable spectral response


A photodetector includes a semiconductor substrate having an irradiation zone configured to generate charge carriers having opposite charge carrier types in response to an irradiation of the semiconductor substrate. The photodetector further includes an inversion zone generator configured to operate in at least two operating states to generate different inversion zones within the substrate, wherein a first inversion zone generated in a first operating state differs from a second inversion zone generated in a second operating state, and wherein the first inversion zone and the second inversion zone have different extensions in the semiconductor substrate.
Infineon Technologies Ag
04/16/15
20150102492

Semiconductor device and manufacturing same


A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a multilayered wiring formed in a prescribed area within the insulating film. The multilayered wiring includes a dual damascene wiring positioned on at least one layer of the multilayered wiring.
Renesas Electronics Corporation
04/16/15
20150102490

Semiconductor device having an airbridge and fabricating the same


A semiconductor device and a method of forming an airbridge extending from a conductive area of the semiconductor device are provided. The semiconductor device includes a device pattern formed on a semiconductor substrate, a seed layer formed on the device pattern, and an airbridge formed on the seed layer, where the airbridge includes a plated conductive material and defines an opening exposing a portion of the device pattern.
Avago Technologies General Ip (singapore) Pte. Ltd.
04/16/15
20150102472

Semiconductor device with shielding layer in post-passivation interconnect structure


A semiconductor device includes a semiconductor substrate, a dielectric layer, a passivation layer, a protective layer, a post-passivation interconnect (ppi) structure, and a shielding layer. The semiconductor substrate has electrical circuitry.
Taiwan Semiconductor Manufacturing Co., Ltd.
04/16/15
20150102456

Amorphorus silicon insertion for sti-cmp planarity improvement


A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a first cushion layer, a second cushion layer and an insulating filler.
Taiwan Semiconductor Manufacturing Co., Ltd.
04/16/15
20150102455

Method of fabricating dual trench isolated selective epitaxial diode array


Methods and devices associated with phase change memory include diodes operating as selector switches having a large driving current and high switching speed. A method of forming a semiconductor device includes providing a semiconductor substrate, defining a diode array region and a peripheral region on the semiconductor substrate, forming an n+ buried layer in the diode array region by performing an ion implantation process and an annealing process.
Semiconductor Manufacturing International (shanghai) Corporation
04/16/15
20150102454

Forming fins of different materials on the same substrate


A semiconductor substrate may be formed by providing an providing a semiconductor-on-insulator (soi) substrate including a base semiconductor layer, a buried insulator layer above the base semiconductor layer, and a soi layer comprising a first semiconductor material above the buried insulator layer; forming an isolation region in the soi layer isolating a first portion of the soi layer from a second portion of the soi layer; removing the second portion of the soi layer to expose a portion of the buried insulator layer; forming a hole in the exposed portion of the buried insulator layer to expose a portion of the base semiconductor layer; and forming a semiconductor layer made of a second semiconductor material on the exposed portion of the base semiconductor layer, so that the replacement semiconductor layer covers the exposed region of the buried insulator layer.. .
International Business Machines Corporation
04/16/15
20150102453

Fabricating shallow-trench isolation semiconductor devices to reduce or eliminate oxygen diffusion


A method is disclosed for forming a semiconductor device. A first opening is formed for an sti on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening.
International Business Machines Corporation
04/16/15
20150102451

Nanoscale silicon schottky diode array for low power phase change memory application


Methods and devices associated with a phase change memory include schottky diodes operating as selectors having a low turn-on voltage, low sneak current and high switching speed. A method of forming a semiconductor device includes providing a semiconductor substrate having a diode array region and a peripheral device region, forming an n+ buried layer in the diode array region, forming a semiconductor epitaxial layer on the n+ buried layer, and forming deep trench isolations through the epitaxial layer and the n+ buried layer along a first direction.
Semiconductor Manufacturing International (beijing) Corporation
04/16/15
20150102448

Image pickup device, manufacturing image pickup device, and electronic apparatus


Provided is an image pickup device, including: a first trench provided between a plurality of pixels in a light-receiving region of a semiconductor substrate, the semiconductor substrate including the light-receiving region and a peripheral region, the light-receiving region being provided with the plurality of pixels each including a photoelectric conversion section; and a second trench provided in the peripheral region of the semiconductor substrate, wherein the semiconductor substrate has a variation in thickness between a portion where the first trench is provided and a portion where the second trench is provided.. .
Sony Corporation
04/16/15
20150102446

Solid-state imaging device, manufacturing method thereof, and electronic apparatus


A solid-state imaging device includes a plurality of photoelectric conversion portions each provided in a semiconductor substrate and receives incident light through a light sensing surface, and a pixel separation portion provided to electrically separate a plurality of pixels. At least a pinning layer and a light shielding layer are provided in an inner portion of a trench provided on a side portion of each of the photoelectric conversion portions in an incident surface side, the trench includes a first trench and a second trench formed to be wider than the first trench in a portion shallower than the first trench, the pinning layer is formed in an inner portion of the first trench to cover an inside surface of the second trench, and the light shielding layer is formed to bury an inner portion of the second trench at least via the pinning layer..
Sony Corporation
04/16/15
20150102444

Light sensors having dielectric optical coating filters


Light sensors including dielectric optical coatings to shape their spectral responses, and methods for fabricating such light sensors in a manner that accelerates lift-off processes and increases process margins, are described herein. In an embodiment, a light sensor includes a photodetector sensor region formed in a semiconductor substrate, a dielectric optical coating filter covering the photodetector sensor region, and dummy dielectric optical coating features beyond the photodetector sensor region, wherein the dummy dielectric optical features include one or more dummy corners, dummy islands and/or dummy rings.
Intersil Americas Llc
04/16/15
20150102443

Infrared sensor device and producing an infrared sensor device


An infrared sensor device includes at least one sensor element formed in a semiconductor substrate, an soi wafer that defines a gap below and around the sensor element, and a suspension device that is configured to suspend the sensor element in the soi wafer. The sensor element is substantially arranged below the suspension device, thereby achieving a high sensitivity, low thermal capacity, low thermal coupling to the substrate and a high image refresh rate..
Robert Bosch Gmbh
04/16/15
20150102431

Mechanisms for forming gate dielectric layer


Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a nitride buffer layer over the semiconductor substrate, and the nitride buffer layer is in an amorphous state.
Taiwan Seminconductor Manufacturing Co., Ltd.
04/16/15
20150102428

Merged fin finfet with (100) sidewall surfaces and making same


A merged fin finfet and method of fabrication. The finfet includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are (100) surfaces and the longitudinal axes of the two or more fins aligned with a [100] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate..
International Business Machines Corporation
04/16/15
20150102424

Forming conductive sti liners for finfets


An integrated circuit device includes a semiconductor substrate, isolation regions extending into the semiconductor substrate, a semiconductor strip, and a semiconductor fin overlapping and joined to the semiconductor strip. A first dielectric layer and a second dielectric layer are disposed on opposite sidewalls of the semiconductor strip.
Taiwan Semiconductor Manufacturing Company, Ltd.
04/16/15
20150102422

Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same


Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate.
International Business Machines Corporation
04/16/15
20150102419

Semiconductor device and manufacturing method thereof


According to one embodiment, a semiconductor device includes a first complementary semiconductor device provided on a semiconductor substrate, and including a cmos circuit, a metal electrode provided above the first complementary semiconductor device, a semiconductor layer provided above the metal electrode, including an nmos region and a pmos region separated from each other, and containing ge; and a second complementary semiconductor device including an nmosfet provided on the first portion of the semiconductor layer and a pmosfet provided on the second portion of the semiconductor layer.. .
Kabushiki Kaisha Toshiba
04/16/15
20150102407

Lateral double diffused metal-oxide-semiconductor device and fabricating the same


A lateral double diffused metal-oxide-semiconductor device includes: an epitaxial semiconductor layer disposed over a semiconductor substrate; a gate dielectric layer disposed over the epitaxial semiconductor layer; a gate stack disposed over the gate dielectric layer; a first doped region disposed in the epitaxial semiconductor layer from a first side of the gate stack; a second doped region disposed in the epitaxial semiconductor layer from a second side of the gate stack; a third doped region disposed in the first doping region; a fourth doped region disposed in the second doped region; an insulating layer covering the third doped region, the gate dielectric layer, and the gate stack; a conductive contact disposed in the insulating layer, the third doped region, the first doped region and the epitaxial semiconductor layer; and a fifth doped region disposed in the epitaxial semiconductor layer under the conductive contact.. .
Vanguard International Semiconductor Corporation
04/16/15
20150102404

Semiconductor device


A semiconductor device includes a transistor formed in a semiconductor substrate including a main surface. The transistor includes a source region, a drain region, a channel region, and a gate electrode.
Infineon Technologies Ag
04/16/15
20150102402

Semiconductor component and manufacturing method thereof


A semiconductor component includes: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film.. .
Sony Corporation
04/16/15
20150102395

Semiconductor device including decoupling capacitor and forming the same


An integrated circuit device includes a semiconductor substrate having first and second semiconductor regions therein, a gate trench in the first semiconductor region and a gate electrode in the gate trench. The gate electrode has an upper surface below a surface of the semiconductor substrate.
04/16/15
20150102384

Esd protection with asymmetrical bipolar-based device


An electrostatic discharge (esd) protection device includes a semiconductor substrate comprising a buried insulator layer and a semiconductor layer over the buried insulator layer having a first conductivity type, and first and second bipolar transistor devices disposed in the semiconductor layer, laterally spaced from one another, and sharing a common collector region having a second conductivity type. The first and second bipolar transistor devices are configured in an asymmetrical arrangement in which the second bipolar transistor device includes a buried doped layer having the second conductivity type and extending along the buried insulator layer from the common collector region across a device area of the second bipolar transistor device..
Freescale Semiconductor, Inc.
04/16/15
20150102363

Silicon carbide semiconductor device and fabrication method thereof


A silicon carbide semiconductor device has a first-conductivity-type semiconductor layer having a lower impurity concentration and formed on a first-conductivity-type semiconductor substrate, a second-conductivity-type semiconductor layer having a higher impurity concentration and selectively formed in the first-conductivity-type semiconductor layer, a second-conductivity-type base layer having a lower impurity concentration formed on a surface of the second-conductivity-type semiconductor layer, a first-conductivity-type source region selectively formed in a surface layer of the base layer, a first-conductivity-type well region formed to penetrate the base layer from a surface to the first-conductivity-type semiconductor layer, and a gate electrode formed via a gate insulation film on a surface of the base layer interposed between the source region and the well region. Portions of the respective second-conductivity-type semiconductor layers of different cells can be connected to each other by a connecting portion in a region under the well region..
Fuji Electric Co., Ltd.
04/16/15
20150102287

Nanowire mosfet with support structures for source and drain


A transistor device and method for forming a nanowire field effect transistor (fet) device are provided. A device layer including a source region and a drain region is formed, where the source region and the drain region are connected by a suspended nanowire channel.
Taiwan Semiconductor Manufacturing Company Limited
04/09/15
20150099372

Sequential precursor dosing in an ald multi-station/batch reactor


Disclosed herein are methods of depositing layers of material on multiple semiconductor substrates at multiple processing stations within one or more reaction chambers. The methods may include dosing a first substrate with film precursor at a first processing station and dosing a second substrate with film precursor at a second processing station with precursor flowing from a common source, wherein the timing of said dosing is staggered such that the first substrate is dosed during a first dosing phase during which the second substrate is not substantially dosed, and the second substrate is dosed during a second dosing phase during which the first substrate is not substantially dosed.
Lam Research Corporation
04/09/15
20150099365

Tunable upper plasma-exclusion-zone ring for a bevel etcher


A bevel etcher for cleaning a bevel edge of a semiconductor substrate with plasma includes a lower electrode assembly having a lower support having a cylindrical top portion. An upper dielectric component is disposed above the lower electrode assembly having a cylindrical bottom portion opposing the top portion of the lower support.
Lam Research Corporation
04/09/15
20150099353

Non-volatile memory devices and methods of manufacturing the same


A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern..
04/09/15
20150099352

Composition for forming n-type diffusion layer, producing n-type diffusion layer, and producing photovoltaic cell element


A composition for forming an n-type diffusion layer includes a glass powder containing p2o5, sio2 and cao and a dispersion medium. An n-type diffusion layer and a photovoltaic cell element having an n-type diffusion layer are produced by applying the composition for forming an n-type diffusion layer on a semiconductor substrate and by subjecting the substrate to a thermal diffusion treatment..
Hitachi Chemical Company, Ltd.
04/09/15
20150099351

Method for fabricating semiconductor device


A method for fabricating a semiconductor device is provided. An ion implantation mask exposing a portion of a semiconductor substrate is formed on the semiconductor substrate.
Samsung Electronics Co., Ltd.
04/09/15
20150099343

Semiconductor memory device


A semiconductor memory device includes a plurality of auxiliary patterns formed over a semiconductor substrate, a plurality of gate line patterns disposed in parallel with one another over the semiconductor substrate between the plurality of auxiliary patterns, and an air gap formed between the plurality of gate line patterns and between each of the plurality of gate line patterns and each of the auxiliary patterns.. .
Sk Hynix Inc.
04/09/15
20150099338

Non-volatile memory device and manufacturing the same


A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate.. .
Sk Hynix Inc.
04/09/15
20150099336

Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions


Methods of manufacturing semiconductor integrated circuits having finfet structures with epitaxially formed source and drain regions are disclosed. A method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, epitaxially growing a silicon material on the fin structures, wherein a merged source/drain region is formed on the fin structures, and anisotropically etching at least one of the merged source drain regions to form an un-merged source/drain region..
Globalfoundries, Inc.
04/09/15
20150099326

Solar cell and manufacturing the same


A method for manufacturing a solar cell, comprising the steps of: a) providing a semiconductor substrate having a light-receiving side and a back side, wherein a passivation layer is formed on the back side; b) forming a silver conductor pattern comprising a metal resinate on the back side of the semiconductor substrate; c) forming an aluminum conductor pattern on the back side of the semiconductor substrate, at least part of the aluminum conductor pattern being superimposed on at least part of the silver conductor pattern; and d) firing the silver conductor pattern and the aluminum conductor pattern at the same time, thereby forming an electric contact between the semiconductor substrate and the aluminum conductor pattern by way of fire through in a region where the silver conductor pattern and the aluminum conductor pattern are superimposed.. .
E I Du Pont De Nemours And Company
04/09/15
20150099324

Bifacial tandem solar cells


A method of fabricating on a semiconductor substrate bifacial tandem solar cells with semiconductor subcells having a lower bandgap than the substrate bandgap on one side of the substrate and with subcells having a higher bandgap than the substrate on the other including, first, growing a lower bandgap subcell on one substrate side that uses only the same periodic table group v material in the dislocation-reducing grading layers and bottom subcells as is present in the substrate and after the initial growth is complete and then flipping the substrate and growing the higher bandgap subcells on the opposite substrate side which can be of different group v material.. .
Masimo Semiconductor, Inc.
04/09/15
20150098489

Semiconductor devices including electrodes for temperature measurement


A semiconductor device includes: a semiconductor substrate; a plurality of conductive lines formed on the semiconductor substrate; and an electrode for temperature measurement. The electrode is connected to the plurality of conductive lines.
Samsung Electronics Co., Ltd.
04/09/15
20150097999

Image capturing apparatus and control method thereof


An image capturing apparatus comprises an image sensor including a first semiconductor substrate on which a photodiode is arranged, a second semiconductor substrate on which a storage element is arranged, and a connection unit configured to electrically connect the photodiode and the storage element, a first transfer unit configured to transfer pixel signals of a first pixel group to the storage element, a first readout unit configured to read out the pixel signals of the first pixel group, a second transfer unit configured to transfer pixel signals of a second pixel group to the storage element, and a second readout unit configured to read out some of the pixel signals of the second pixel group, wherein an image of one frame is generated by composing the pixel signals of the second pixel group and the first pixel group.. .
Canon Kabushiki Kaisha
04/09/15
20150097966

Photoelectric conversion device and image pick-up device


A photoelectric conversion device includes a semiconductor substrate, an insulating layer provided on the semiconductor substrate, an electrode provided on the insulating layer, a photoelectric conversion film provided on the electrode for converting received light to charges, a line connected between the electrode and the semiconductor substrate, a first planar electrode provided in the insulating layer and connected to the electrode, and a second planar electrode provided in the insulating layer between the first planar electrode and the semiconductor substrate.. .
Rohm Co., Ltd.
04/09/15
20150097640

Transmission line for 3d integrated circuit


A semiconductor transmission line substructure and methods of transmitting rf signals are described. The semiconductor transmission line substructure can include a substrate; a first signal line over the substrate; a first ground line over the substrate; and a second semiconductor substrate over the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.
04/09/15
20150097302

Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof


A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring.
Tera Probe, Inc.
04/09/15
20150097298

Semiconductor substrate assembly


A semiconductor substrate assembly includes a semiconductor material layer, a first isolation layer, a second isolation layer, a first conductive pillar, and a second conductive pillar. The semiconductor material layer has a first surface and a second surface opposite to the first surface.
Industrial Technology Research Institute
04/09/15
20150097288

High density dielectric etch stop layer


A method of manufacturing an integrated circuit device includes forming an inter-level dielectric layer over a semiconductor substrate, forming a transformative layer over the inter-level dielectric layer, forming a protective layer over the transformative layer without allowing the transformative layer to undergo a substantive transformation, and after forming the protective layer, causing the transformative layer to undergo a volume-increasing transformation. The volume-increasing transformation produces a high density material that provides an effective etch stop..
Taiwan Semiconductor Manufacturing Co., Ltd.
04/09/15
20150097274

Through-silicon via structure and improving beol dielectric performance


An improved through-silicon via (tsv) is disclosed. A semiconductor substrate has a a back-end-of-line (beol) stack formed thereon.
International Business Machines Corporation
04/09/15
20150097270

Finfet with relaxed silicon-germanium fins


A method of forming a semiconductor structure includes forming a first fin in a p-fet device region of a semiconductor substrate and a second fin in an n-fet device region of the semiconductor substrate substantially parallel to the first fin. The first fin and the second fin each comprise a strained semiconductor material.
International Business Machines Corporation
04/09/15
20150097269

Transient voltage suppression device and manufacturing method thereof


The present invention discloses a transient voltage suppression (tvs) device and a manufacturing method thereof. The tvs device includes: a conductive layer; a p-type semiconductor substrate, which is formed on the conductive layer; an n-type buried layer, which is formed on the semiconductor substrate; a p-type lightly doped layer, which is formed on the buried layer; a p-type cap region, which is formed on the lightly doped layer; and an n-type reverse region, which is formed on the cap region, wherein a zener diode includes the reverse region and the cap region, and an npn bipolar junction transistor (bjt) includes the reverse region, the cap region, the lightly doped layer and the buried layer..
Richtek Technology Corporation
04/09/15
20150097265

Semiconductor device with buried conduction path


A device includes a semiconductor substrate, emitter and collector regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite base region disposed in the semiconductor substrate, having a second conductivity type, and including a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions..
Freescale Semiconductor, Inc.
04/09/15
20150097256

Semiconductor devices including avalanche photodetector diodes integrated on waveguides and methods for fabricating the same


Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a method for fabricating a semiconductor device includes etching a trench into a waveguide layer in a detector region of a semiconductor substrate.
Globalfoundries Singapore Pte. Ltd.
04/09/15
20150097251

Semiconductor device and fabricating the same


Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess.
04/09/15
20150097238

Mergeable semiconductor device with improved reliability


A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region.
Freescale Semiconductor, Inc.
04/09/15
20150097232

Dual gate oxide trench mosfet with channel stop trench


A semiconductor device has a plurality of gate electrodes over a gate insulator layer formed in active trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the semiconductor substrate and electrically connected to the gate electrodes.
Alpha And Omega Semiconductor Incorporated
04/09/15
20150097220

Fin-shaped field effect transistor and capacitor structures


A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface.
Broadcom Corporation
04/09/15
20150097217

Semiconductor attenuated fins


A semiconductor device includes a semiconductor substrate and attenuated semiconductor fins (e.g. Finfet fins) that include an outer portion that is a composite of a first material and a second material, an inner portion that is the second material, and an attenuation portion that is an attenuated composite of the first and second materials.
International Business Machines Corporation
04/09/15
20150097215

Mechanisms for forming micro-electro mechanical system device


Embodiments of mechanisms for forming a micro-electro mechanical system (mems) device are provided. The mems device includes a cmos substrate and a mems substrate bonded with the cmos substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.
04/09/15
20150097189

Semiconductor device and manufacturing the same


A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.. .
Kabushiki Kaisha Toshiba
04/09/15
20150097185

Semiconductor device having test unit, electronic apparatus having the same, and testing the semiconductor device


A semiconductor device can detect a defective or faulty part caused by copper (cu) ions migrated from a through silicon via (tsv), resulting in improvement of device characteristics and reliability. The semiconductor device includes: a semiconductor substrate including an active region defined by a device isolation region; a through silicon via (tsv) formed to pass through the semiconductor substrate; and a test unit formed in the vicinity of the tsv so as to determine the presence or absence of metal pollution caused by the tsv..
Sk Hynix Inc.
04/09/15
20150097184

Semiconductor device and a forming a semiconductor device


A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doping regions of a first doping structure arranged at a main surface of the semiconductor substrate and a plurality of second doping regions of the first doping structure arranged at the main surface of the semiconductor substrate.
Infineon Technologies Ag


Popular terms: [SEARCH]

Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

Follow us on Twitter
twitter icon@FreshPatents

###

This listing is a sample listing of patent applications related to Semiconductor Substrate for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Semiconductor Substrate with additional patents listed. Browse our RSS directory or Search for other possible listings.
     SHARE
  
         













0.632

5307

459194 - 0 - 90