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This page is updated frequently with new Semiconductor Substrate-related patent applications. Subscribe to the Semiconductor Substrate RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Substrate RSS RSS


Thermal processing by transmission of mid infra-red laser light through semiconductor substrate

Semiconductor device manufacturing method

Hybrid conductor through-silicon-via for power distribution and signal transmission

Date/App# patent app List of recent Semiconductor Substrate-related patents
07/17/14
20140201593
 Efficient memory architecture for low density parity check decoding patent thumbnailEfficient memory architecture for low density parity check decoding
A low density parity check (ldpc) decoder integrated on a single semiconductor substrate may comprise one or more arrays of first-type memory cells and one or more arrays of second-type memory cells. The ldpc decoder may be configured to store intrinsic messages in the array of first-type cells and to store extrinsic messages in the array of second-type cells.
07/17/14
20140199858
 Thermal processing by transmission of mid infra-red laser light through semiconductor substrate patent thumbnailThermal processing by transmission of mid infra-red laser light through semiconductor substrate
Thermal processing is performed by transmission of mid infra-red laser light through a substrate such as a semiconductor substrate with a limited mid infra-red transmission range. The laser light is generated by a rare-earth-doped fiber laser and is directed through the substrate such that the transmitted power is capable of altering a target material at a back side region of the substrate, for example, on or spaced from the substrate.
07/17/14
20140199847
 Semiconductor device manufacturing method patent thumbnailSemiconductor device manufacturing method
According to one embodiment, a semiconductor device manufacturing method includes depositing a silicon film above a semiconductor substrate, forming an insulating film which includes silicon oxide or silicon nitride on the silicon film, forming a physical guide having a depressed portion above the insulating film, forming a directed self-assembly material layer which includes a first polymer and a second polymer in the depressed portion of the physical guide, phase-separating the directed self-assembly material layer into a first region which includes the first polymer and a second region which includes the second polymer, removing the second region, processing the insulating film by using the physical guide and the first region as masks, and transferring a pattern corresponding to the second region to the insulating film. Further, the silicon film is processed by using the pattern transferred onto the insulating film as a mask..
07/17/14
20140199834
 Hybrid conductor through-silicon-via for power distribution and signal transmission patent thumbnailHybrid conductor through-silicon-via for power distribution and signal transmission
A method of providing signal, power and ground through a through-silicon-via (tsv), and an integrated circuit chip having a tsv that simultaneously provides signal, power and ground. In one embodiment, the method comprises forming a tsv through a semiconductor substrate, including forming a via in the substrate; and forming a multitude of conductive bars in the via.
07/17/14
20140199817
 Method for manufacturing multi-gate transistor device patent thumbnailMethod for manufacturing multi-gate transistor device
A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.. .
07/17/14
20140199803
 Solid state image pickup apparatus and method for manufacturing the same patent thumbnailSolid state image pickup apparatus and method for manufacturing the same
When forming a hollow portion between each color filter, in order to realize the formation of the hollow portions with a narrower width, a plurality of light receiving portions are formed on the upper surface of a semiconductor substrate, a plurality of color filters corresponding to each of the light receiving portions are formed above the semiconductor substrate, a photoresist is formed on each color filter, side walls are formed on the side surfaces of the photoresist, and a hollow portion is formed between each color filter by performing etching using at least the side walls as a mask.. .
07/17/14
20140199802
 Manufacturing method of solid-state imaging apparatus patent thumbnailManufacturing method of solid-state imaging apparatus
To realize simplification of a process of forming hollow portions in a solid-state imaging apparatus, a plurality of light receiving portions is formed on a semiconductor substrate, and color filter layers as hollow portion forming layers are formed above the semiconductor substrate (fig. 1a).
07/17/14
20140199801
 Manufacturing method of solid-state imaging apparatus patent thumbnailManufacturing method of solid-state imaging apparatus
A color filter 5 is formed above a semiconductor substrate sb, in an area above a predetermined light receiving portion among a plurality of light receiving portions 1. A sacrificial layer 8 is formed on upper and side of the first color filter 5.
07/17/14
20140199798
 Quantum cascade laser manufacturing method patent thumbnailQuantum cascade laser manufacturing method
A quantum cascade laser manufacturing method includes: a step of pressing a mother stamper against a resin film having flexibility to make a resin stamper 201 having a second groove pattern p2; a step of making a wafer with an active layer formed on a semiconductor substrate; a step of forming a resist film 304 on a surface on the active layer side of the wafer; a step of pressing the resin stamper against the resist film 304 by air pressure to form a third groove pattern p3 on the resist film 304; and a step of etching the wafer with the resist film 304 serving as a mask to form a diffraction grating on a surface of the wafer.. .
07/17/14
20140199785
 Multizone control of lamps in a conical lamphead using pyrometers patent thumbnailMultizone control of lamps in a conical lamphead using pyrometers
A method and apparatus for processing a semiconductor substrate is described. The apparatus is a process chamber having an optically transparent upper dome and lower dome.
07/17/14
20140199597
Semiconductor structures having a micro-battery and methods for making the same
The present disclosure provides an embodiment of an integrated structure that includes a first electrode of a first conductive material embedded in a first semiconductor substrate; a second electrode of a second conductive material embedded in a second semiconductor substrate; and a electrolyte disposed between the first and second electrodes. The first and second semiconductor substrates are bonded together through bonding pads such that the first and second electrodes are enclosed between the first and second semiconductor substrates.
07/17/14
20140197889
Semiconductor device, method for manufacturing the same, power supply device, and high-frequency amplifier
A semiconductor device includes: a compound semiconductor stack structure including a plurality of compound semiconductor layers stacked over a semiconductor substrate; a first insulating film covering the surface of the compound semiconductor stack structure; and a conductive film provided on the surface of the first insulating film.. .
07/17/14
20140197538
Copper etching integration scheme
The present disclosure is directed to an interconnect structure. The metal interconnect structure has a metal body disposed over a semiconductor substrate and a projection extending from the metal body.
07/17/14
20140197522
Hybrid conductor through-silicon-via for power distribution and signal transmission
A method of providing signal, power and ground through a through-silicon-via (tsv), and an integrated circuit chip having a tsv that simultaneously provides signal, power and ground. In one embodiment, the method comprises forming a tsv through a semiconductor substrate, including forming a via in the substrate; and forming a multitude of conductive bars in the via.
07/17/14
20140197518
Stacked structure semiconductor device
A semiconductor device includes a capacitor formed in a semiconductor substrate of a first conductivity type. The capacitor includes: a heavily-doped layer of a second conductivity type placed over the substrate, a first insulating layer placed over the heavily-doped layer of the second conductivity type, and a first metal layer placed over the first insulating layer.
07/17/14
20140197514
Semiconductor device and method of manufacturing the same
A semiconductor device that is equipped with a semiconductor substrate, a composite metal film, and a detection terminal is provided. The composite metal film is formed on a surface or a back face of the semiconductor substrate, and has a first metal film, and a second metal film that is joined to the first metal film and is different in seebeck coefficient from the first metal film.
07/17/14
20140197513
Image sensor with improved dark current performance
Provided is a semiconductor image sensor device. The image sensor device includes a semiconductor substrate that includes an array region and a black level correction region.
07/17/14
20140197509
Photosensitive imaging devices and associated methods
Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction.
07/17/14
20140197498
Integrated circuits and methods for fabricating integrated circuits with improved silicide contacts
Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure.
07/17/14
20140197496
Semiconductor structure with suppressed sti dishing effect at resistor region
An integrated circuit includes a semiconductor substrate; a first shallow trench isolation (sti) feature of a first width and a second sti feature of a second width in a semiconductor substrate. The first width is less than the second width.
07/17/14
20140197494
Trench silicide and gate open with local interconnect with replacement gate process
A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel.
07/17/14
20140197482
Semiconductor device and method of forming the same
A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls.
07/17/14
20140197476
Semiconductor device
A semiconductor device includes element active portion x and element peripheral portion y. An interlayer insulating film is formed on upper surfaces of portions x and y.
07/17/14
20140197474
Semiconductor integrated circuit device and a method of manufacturing the same
Semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.. .
07/17/14
20140197460
Semiconductor device, method for manufacturing the same, power supply device, and high-frequency amplifier
A semiconductor device includes: a compound semiconductor stack structure including a plurality of compound semiconductor layers stacked over a semiconductor substrate; and a first insulating film covering the surface of the compound semiconductor stack structure, the first insulating film being a silicon nitride film including, on the top side, a first region containing nitrogen element in excess of the stoichiometric ratio.. .
07/17/14
20140197458
Finfet device and method of fabricating same
An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions..
07/17/14
20140197448
Bidirectional semiconductor device for protection against electrostatic discharges
An integrated circuit is produced on a bulk semiconductor substrate in a given cmos technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate thyristors coupled in parallel and head-to-tail.
07/17/14
20140197356
Cmp compositions and methods for suppressing polysilicon removal rates
The present invention provides a chemical-mechanical polishing (cmp) composition suitable for polishing a silicon nitride-containing substrate while suppressing polysilicon removal from the substrate. The composition comprises abrasive particles suspended in an acidic aqueous carrier containing a surfactant comprising an alkyne-diol, an alkyne diol ethoxylate, or a combination thereof.
07/17/14
20140196850
Method and system for wafer level singulation
A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices.
07/17/14
20140196777
Solar cell and method for manufacturing the same
A solar cell and a method for manufacturing the solar cell are discussed. An embodiment of the method includes forming an emitter region containing impurities of a second conductive type opposite a first conductive type at a back surface of a semiconductor substrate containing impurities of the first conductive type, forming a passivation layer paste containing impurities of the first conductive type on the emitter region, selectively performing a thermal process on a first partial area of the passivation layer paste to form a back surface field region containing impurities of the first conductive type at a partial area of the emitter region, forming a plurality of openings in partial areas of the passivation layer paste to form a passivation layer, forming a first electrode connected to the emitter region, and forming a second electrode connected to the back surface field region..
07/17/14
20140196303
Process for curing low-dielectric constant material
Provided is a low-dielectric constant material curing process including irradiating a low-dielectric constant material on a semiconductor substrate with ultraviolet rays. In the low-dielectric constant material curing process, the ultraviolet light source is a fluorescent lamp including: a light-emitting tube sealed and filled with a discharge gas containing xenon gas; a pair of electrodes for inducing a discharge in the interior space of the light-emitting tube; a dielectric material being interposed between the interior space and at least one of the pair of electrodes; and a phosphor layer formed on a surface of the light-emitting tube and containing a phosphor that is excited by light generated from the discharge gas by a discharge in the interior space.
07/10/14
20140193983
Apparatuses and methods for depositing sic/sicn films via cross-metathesis reactions with organometallic co-reactants
Disclosed herein are methods of forming sic/sicn film layers on surfaces of semiconductor substrates. The methods may include introducing a silicon-containing film-precursor and an organometallic ligand transfer reagent into a processing chamber, adsorbing the silicon-containing film-precursor, the organometallic ligand transfer reagent, or both onto a surface of a semiconductor substrate under conditions whereby either or both form an adsorption-limited layer, and reacting the silicon-containing film-precursor with the organometallic ligand transfer reagent, after either or both have formed the adsorption-limited layer.
07/10/14
20140193971
Semiconductor device and method of manufacturing the same
The semiconductor device includes: a semiconductor substrate; an insulating film provided on a surface of the semiconductor substrate; a porous metal film provided on the insulating film; a protective film provided on the porous metal film, and having an opening portion for defining a pad region; and a wire wire-bonded to the porous metal film in the pad region. The stress generated by the impact of wire-bonding is mostly absorbed in the porous metal film owing to the distortion of the porous metal film, preventing generation of cracks in the insulating film..
07/10/14
20140193956
Transistor and fabriation method
Fabrication methods for junctionless transistor and complementary junctionless transistor are provided. An isolation layer doped with a first-type ion is formed on a semiconductor substrate and an active layer doped with a second-type ion is formed on the isolation layer.
07/10/14
20140192595
Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate.
07/10/14
20140192533
Apparatus and method for speckle reduction in laser processing equipment
Embodiments described herein provide apparatus and methods for processing semiconductor substrates with uniform laser energy. A laser pulse or beam is directed to a spatial homogenizer, which may be a plurality of lenses arranged along a plane perpendicular to the optical path of the laser energy, an example being a microlens array.
07/10/14
20140192243
Image pickup device, method of manufacturing same, and electronic apparatus
An image pickup device with a plurality of pixels, each of the pixels includes: a photoelectric conversion section formed in a semiconductor substrate; and a metallic member formed between the semiconductor substrate and a wiring layer provided in a layer on the semiconductor substrate, a part of the metallic member being configured to serve as a light-shielding member that blocks a part of light to be incident on the photoelectric conversion section.. .
07/10/14
20140191421
Semiconductor device
A semiconductor device includes a semiconductor substrate, an interlayer insulation film, multiple wiring layers, a first hard film, and an electrical pad. The semiconductor substrate has a semiconductor element.
07/10/14
20140191412
Interconnection structures and fabrication method thereof
A method is provided for fabricating an interconnection structure. The method includes providing a semiconductor substrate having certain semiconductor devices inside, a dielectric layer covering the semiconductor devices, and vias inside the dielectric layer connecting with connection pads of the semiconductor devices.
07/10/14
20140191404
Local interconnect structure and fabrication method
Local interconnect structures and fabrication methods are provided. A dielectric layer can be formed on a semiconductor substrate.
07/10/14
20140191373
Composite wafer and method for manufacturing the same
A composite wafer 10 includes a supporting substrate 12 and a semiconductor substrate 14 which are bonded to each other by direct bonding. The supporting substrate 12 is a translucent alumina substrate with an alumina purity of 99% or more.
07/10/14
20140191349
Solid-state imaging apparatus and method of manufacturing the same
The present invention provides a solid-state imaging apparatus which has hollow portions provided around each of color filters and achieves the prevention of the peeling of each of the color filters. The solid-state imaging apparatus having a plurality of light receiving portions provided on a semiconductor substrate includes: a plurality of color filters arranged correspondingly to each of the plurality of light receiving portions; and hollow portions formed around each of the plurality of color filters, wherein each of the color filters has one peripheral part contacting with adjacent one or more of the color filters..
07/10/14
20140191347
Solid-state imaging device
According to one embodiment, a solid-state imaging device includes a semiconductor substrate including a pixel area and a peripheral circuit area, an interconnection structure provided on a first principal surface of the semiconductor substrate and including first interconnection layers electrically connected to the peripheral circuit area, a second interconnection layer provided in the peripheral circuit area and on a second principal surface of the semiconductor substrate, a third interconnection layer provided above the second interconnection layer with an insulating layer therebetween, and through electrodes electrically connecting the second interconnection layer to the third interconnection layer.. .
07/10/14
20140191343
Sound transducer and microphone using same
Provided is an acoustic transducer including: a semiconductor substrate; a vibrating membrane, provided above the semiconductor substrate, including a vibrating electrode; and a fixed membrane, provided above the semiconductor substrate, including a fixed electrode, the acoustic transducer detecting a sound wave according to changes in capacitances between the vibrating electrode and the fixed electrode, converting the sound wave into electrical signals, and outputting the electrical signals. At least one of the vibrating electrode and the fixed electrode is divided into a plurality of divided electrodes, and the plurality of divided electrodes outputting the electrical signals..
07/10/14
20140191339
Semiconductor structures and fabrication method thereof
A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate.
07/10/14
20140191316
Mos transistors and fabrication method thereof
A method is provided for fabricating an mos transistor. The method includes providing a semiconductor substrate, and forming a gate structure having a gate dielectric layer and a gate metal layer on the semiconductor substrate.
07/10/14
20140191315
Multigate metal oxide semiconductor devices and fabrication methods
A semiconductor device includes a first well and a second well implanted in a semiconductor substrate. The semiconductor device further includes a gate structure above the first and second wells between a raised source structure and a raised drain structure.
07/10/14
20140191314
Semiconductor device and fabrication method
Semiconductor devices and fabrication methods are provided. A fin can be formed on a semiconductor substrate, a gate can be formed across the fin, and sidewall spacers can be formed across the fin on both sides of the gate.
07/10/14
20140191310
Power semiconductor device
A power semiconductor device according to an embodiment includes an element portion in which mosfet elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film.
07/10/14
20140191304
Cmos transistors, fin field-effect transistors and fabrication methods thereof
A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and configuring a channel region along a first direction.
07/10/14
20140191303
Semiconductor devices including back-side integrated circuitry
Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors.
07/10/14
20140191301
Transistor and fabrication method
Transistors and fabrication methods are provided. A first sidewall can be formed on each sidewall of a gate structure.
07/10/14
20140191298
Semiconductor device and manufacturing method of the same
A semiconductor device includes a semiconductor substrate, a metal gate structure, at least an epitaxial layer, an interlayer dielectric, at least a contact hole, at least a metal silicide layer and a fluorine-containing layer. The semiconductor substrate has at least a gate region and at least a source/drain region adjoining the gate region.
07/10/14
20140191291
Method of manufacturing a non-volatile memory
The disclosure relates to a method of manufacturing vertical gate transistors in a semiconductor substrate, comprising implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors; forming, in the substrate, parallel trench isolations and second trenches perpendicular to the trench isolations, reaching the isolation layer, and isolated from the substrate by a first dielectric layer; depositing a first conductive layer on the surface of the substrate and in the second trenches; etching the first conductive layer to form the vertical gates of the transistors, and vertical gate connection pads between the extremity of the vertical gates and an edge of the substrate, while keeping a continuity zone in the first conductive layer between each connection pad and a vertical gate; and implanting doped regions on each side of the second trenches, to form drain regions of the transistors.. .
07/10/14
20140191288
Semiconductor device and method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes forming an electron transit layer on a semiconductor substrate, forming an electron supply layer on the electron transit layer, forming a cap layer on the electron supply layer, forming a protection layer on the cap layer, the protection layer having an opening part, through which a part of the cap layer is exposed, and forming an oxidation film on an exposed surface of the cap layer by a wet process.. .
07/10/14
20140191287
Compressive strained iii-v complementary metal oxide semiconductor (cmos) device
A semiconductor device including a first lattice dimension iii-v semiconductor layer present on a semiconductor substrate, and a second lattice dimension iii-v semiconductor layer that present on the first lattice dimension iii-v semiconductor layer, wherein the second lattice dimension iii-v semiconductor layer has a greater lattice dimension than the first lattice dimension iii-v semiconductor layer, and the second lattice dimension iii-v semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension iii-v semiconductor layer, wherein the channel portion of second lattice dimension iii-v semiconductor layer has the compressive strain.
07/10/14
20140191286
Compressive strained iii-v complementary metal oxide semiconductor (cmos) device
A semiconductor device including a first lattice dimension iii-v semiconductor layer present on a semiconductor substrate, and a second lattice dimension iii-v semiconductor layer that present on the first lattice dimension iii-v semiconductor layer, wherein the second lattice dimension iii-v semiconductor layer has a greater lattice dimension than the first lattice dimension iii-v semiconductor layer, and the second lattice dimension iii-v semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension iii-v semiconductor layer, wherein the channel portion of second lattice dimension iii-v semiconductor layer has the compressive strain.
07/10/14
20140191252
Complementary metal oxide semiconductor device, optical apparatus including the same, and method of manufacturing the same
A complementary metal oxide semiconductor (cmos) device includes an n-type first transistor on a silicon substrate, the n-type first transistor including a group iii-v compound semiconductor substrate, and a p-type second transistor on the silicon substrate, the p-type second transistor including a germanium based substrate.. .
07/10/14
20140191248
Semiconductor device
A semiconductor device includes: a semiconductor substrate that has an element region and a peripheral region that surrounds the element region; and a gate pad that is disposed in an area that is on a surface side of the semiconductor substrate. The element region is formed with an insulated gate semiconductor element that has a gate electrode.
07/03/14
20140189635
Semiconductor device design method, system and computer-readable medium
A semiconductor device design system comprising at least one processor is configured to define a resistance-capacitance (rc) extraction tool for determining a distance between first and second through-semiconductor-vias extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second through-semiconductor-vias in the semiconductor substrate.
07/03/14
20140188264
Workflow manager and bar coding system for processing of samples/substrates in hpc (high productivity combinatorial) r&d environment
Methods of semiconductor processing are described. An experiment is designed for each process of a semiconductor substrate, which are implemented on respective multiple regions of the semiconductor substrate.
07/03/14
20140187052
Selective etching of hafnium oxide using diluted hydrofluoric acid
Provided are methods for processing semiconductor substrates having hafnium oxide structures as well as silicon nitride and/or silicon oxide structures. Etching solutions and processing conditions described herein provide high etching selectivity of hafnium oxide relative to these other materials.
07/03/14
20140187048
Plasma etching method
An object of the present invention is to provide a plasma etching method capable of forming a tapered recess portion in a wide-gap semiconductor substrate. As a solving means therefor, a high speed etching film e an etching speed of which is higher than that of a wide-gap semiconductor substrate k is formed on the wide-gap semiconductor substrate k, and a mask m having an opening is formed on the high speed etching film e.
07/03/14
20140187044
Addition of carboxyl groups plasma during etching for interconnect reliability enhancement
The present disclosure is directed to a method of manufacturing a semiconductor structure in which a low-k dielectric layer is formed over a semiconductor substrate. Features can be formed proximate to the low-k dielectric layer by plasma etching with a plasma formed of a mixture of a co2, co, or carboxyl-containing source gas and a fluorine-containing source gas.
07/03/14
20140187041
High dose ion-implanted photoresist removal using organic solvent and transition metal mixtures
Provided are methods for processing semiconductor substrates to remove high-dose ion implanted (hdi) photoresist structures without damaging other structures made of titanium nitride, tantalum nitride, hafnium oxide, and/or hafnium silicon oxide. The removal is performed using a mixture of an organic solvent, an oxidant, a metal-based catalyst, and one of a base or an acid.
07/03/14
20140187031
Semiconductor device with recess gate and method for fabricating the same
A method for fabricating a semiconductor device includes forming a conductive layer over first and second regions of a semiconductor substrate, forming a trench extended in the first region of the semiconductor substrate through the conductive layer, forming a recessed gate electrode in the trench, doping the conductive layer and the recessed first gate electrode, and forming a second gate electrode by etching the doped conductive layer.. .
07/03/14
20140187027
Ion implantation methods
Provided are methods of forming an ion implanted region in a semiconductor device. The methods comprise: (a) providing a semiconductor substrate having a plurality of regions to be ion implanted; (b) forming a photoresist pattern on the semiconductor substrate, wherein the photoresist pattern is formed from a chemically amplified photoresist composition comprising a matrix polymer having acid labile groups, a photoacid generator and a solvent; (c) coating a descumming composition over the photoresist pattern, wherein the descumming composition comprises: a matrix polymer; a free acid; and a solvent; (d) heating the coated semiconductor substrate; (e) contacting the coated semiconductor substrate with a rinsing agent to remove residual descumming composition and scum from the substrate; and (f) ion implanting the plurality of regions of the semiconductor substrate using the photoresist pattern as an implant mask.
07/03/14
20140187005
Semiconductor device, manufacturing method thereof, electronic device and vehicle
A method for manufacturing a semiconductor device includes forming a recess over a surface of an n-type semiconductor substrate, forming a gate insulation film over an inner wall and a bottom face of the recess, embedding a gate electrode into the recess, forming a p-type base layer in the surface layer of the substrate so as to be shallower than the recess; and forming an n-type source layer in the p-type base layer so as to be shallower than the p-type base layer. The impurity profile of the p-type base layer in a thickness direction includes a second peak being located closer to a bottom face side of the substrate than the first peak and being higher than the first peak, and a third peak located between the first peak and the second peak by implanting impurity ions three times or more at ion implantation energies different from each other..
07/03/14
20140186772
Photoresist pattern trimming methods
Provided are methods of trimming a photoresist pattern. The methods comprise: (a) providing a semiconductor substrate; (b) forming a photoresist pattern on the substrate, wherein the photoresist pattern is formed from a chemically amplified photoresist composition comprising: a matrix polymer comprising an acid labile group; a photoacid generator; and a solvent; (c) coating a photoresist trimming composition on the substrate over the photoresist pattern, wherein the trimming composition comprises: a matrix polymer, an aromatic acid that is free of fluorine; and a solvent; (d) heating the coated substrate, thereby causing a change in polarity of the photoresist matrix polymer in a surface region of the photoresist pattern; and (e) contacting the photoresist pattern with a rinsing agent to remove the surface region of the photoresist pattern, thereby forming a trimmed photoresist pattern.
07/03/14
20140183737
Diffusion barriers
Embodiments of the present invention include diffusion barriers, methods for forming the barriers, and semiconductor devices utilizing the barriers. The diffusion barrier comprises a self-assembled monolayer (sam) on a semiconductor substrate, where one surface of the sam is disposed in contact with and covalently bonded to the semiconductor substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer.
07/03/14
20140183725
Post-passivation interconnect structure and method of forming the same
A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.. .
07/03/14
20140183720
Methods of manufacturing integrated circuits having a compressive nitride layer
Methods of manufacturing semiconductor integrated circuits having a compressive nitride layer are disclosed. In one example, a method of fabricating an integrated circuit includes depositing an aluminum layer over a semiconductor substrate, depositing a tensile silicon nitride layer or a neutral silicon nitride layer over the aluminum layer, and depositing a compressive silicon nitride layer over the tensile silicon nitride layer or the neutral silicon nitride layer.
07/03/14
20140183708
Electrostatic discharge protection structure and fabricating method thereof
A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided.
07/03/14
20140183705
Semiconductor device with through silicon via and alignment mark
A semiconductor device includes: a plurality of semiconductor chips stacked on each other, each of the plurality of semiconductor chips having a semiconductor substrate and a wiring layer; a through electrode penetrating the semiconductor substrate in a thickness direction and electrically connected to each other between the semiconductor chips adjacent to each other; a conductor penetrating the semiconductor substrate in the thickness direction and not electrically connected between the other semiconductor chips; and an insulating separator penetrating the semiconductor substrate in the thickness direction and formed in a shape of a ring surrounding the conductor.. .
07/03/14
20140183704
Semiconductor chip, method for manufacturing semiconductor chip, and semiconductor device
A method of manufacturing a semiconductor device including a semiconductor substrate having first and second surfaces and a peripheral edge, the first and second surfaces being opposite to each other, includes forming an inter-layer insulator having a guard ring on the first surface, adjacent to the peripheral edge, forming a first groove on the second surface and adjacent to the peripheral edge, and forming a through electrode that penetrates the second surface to the inter-layer insulator near the first groove and on an opposite side of the groove with respect to the peripheral edge.. .
07/03/14
20140183689
Anti-fuse array of semiconductor device and method for forming the same
An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region..
07/03/14
20140183685
Image sensor
An image sensor arranged inside and on top of a semiconductor substrate, having a plurality of pixels, each including: a photosensitive area, a read area, and a storage area extending between the photosensitive area and the read area; at least one first insulated vertical electrode extending in the substrate between the photosensitive area and the storage area; and at least one second insulated vertical electrode extending in the substrate between the storage area and the read area.. .
07/03/14
20140183684
Photodetector array and method of manufacture
The present invention is directed to photodiode arrays comprising a dielectric structure containing an array of face conductive areas (pads) and. Each photodiode is fully separated from each other.
07/03/14
20140183681
Surface treatment for bsi image sensors
A backside illumination image sensor structure comprises an image sensor formed adjacent to a first side of a semiconductor substrate, wherein a first dielectric layer formed over the first side of the semiconductor substrate and an interconnect layer formed over the first dielectric layer. The image sensor structure further comprises a backside illumination film formed over a second side of the semiconductor substrate and a first silicon halogen compound layer formed between the second side of the semiconductor substrate and the backside illumination film..
07/03/14
20140183680
Semiconductor device and method of manufacturing the same
A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.. .
07/03/14
20140183666
Flourine-stabilized interface
Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-κ dielectric material is formed together with a layer containing fluorine on a semiconductor substrate.
07/03/14
20140183650
Cmos circuit and method for fabricating the same
A semiconductor device includes a semiconductor substrate and a gate insulation layer formed over the semiconductor substrate. A gate electrode is formed over the gate insulation layer.
07/03/14
20140183636
Method for manufacturing semiconductor substrate, substrate for forming semiconductor substrate, stacked substrate, semiconductor substrate, and electronic device
Film thickness variations are prevented in a plurality of single crystal semiconductor films separated at a fragile layer reliably and transferred to a base substrate. A method for manufacturing a soi substrate (33) in which a plurality of soi layers (15) are disposed on a base substrate (30) includes the steps of bonding a plurality of soi wafers (10), in which an oxide film (14), a soi layer (15), a box layer (12), and a si support substrate (13) having a fragile layer (17) formed by ion irradiation in the inside and being made from a single crystal semiconductor material are stacked sequentially, to a base substrate (30) in such a way that the oxide film (14) is located on the side close to the base substrate (30), applying heat to the plurality of soi wafers (10) to separate part of the si support substrate (13) at the fragile layer (17) and transfer the oxide film (14), the soi layer (15), the box layer (12), and a single crystal si layer (18) which is part of the si support substrate (13) to the base substrate (30), and subjecting the base substrate (30) to an etch back treatment to expose the box layer (12) by etching the transferred single crystal si layer (18)..
07/03/14
20140183629
Semiconductor device and method of manufacturing a semiconductor device
A semiconductor device includes a transistor, formed in a semiconductor substrate having a first main surface. The transistor includes a channel region, doped with dopants of a first conductivity type, a source region, a drain region, the source and the drain region being doped with dopants of a second conductivity type different from the first conductivity type, a drain extension region, and a gate electrode adjacent to the channel region.
07/03/14
20140183628
Metal oxide semiconductor devices and fabrication methods
A semiconductor device includes a first well and a second well implanted in a semiconductor substrate. The semiconductor device further includes a raised drain structure above and in contact with the second well and separate from the gate structure.
07/03/14
20140183620
Semiconductor device
A semiconductor substrate of a semiconductor device includes a first conductive body region that is formed in the element region; a second conductive drift region that is formed in the element region; a gate electrode that is formed in the element region, that is arranged in a gate trench, and that faces the body region; an insulating body that is formed in the element region and is arranged between the gate electrode and an inside wall of the gate trench; a first conductive floating region that is formed in the element region and that is surrounded by the drift region; a first voltage-resistance retaining structure that is formed in the peripheral region and that surrounds the element region; and a gate pad that is formed in the peripheral region, and is electrically connected to the gate electrode in a position on the element region-side of the first voltage-resistance retaining structure.. .
07/03/14
20140183615
Non-volatile memory devices including blocking insulation patterns with sub-layers having different energy band gaps
A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer.
07/03/14
20140183614
Semiconductor device
A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, at least a first gate, a shallow trench isolation (sti) and a third gate.
07/03/14
20140183612
Nonvolatile memory structure and fabrication method thereof
A nonvolatile memory structure includes a semiconductor substrate having thereon a first oxide define (od) region, a second od region and a third od region arranged in a row. The first, second, and third od regions are separated from one another by an isolation region.
07/03/14
20140183610
Decoupling capacitor for finfet compatible process
A decoupling capacitor formed from a fin field-effect transistor (finfet) and method of using the same are provided. An embodiment decoupling capacitor includes a fin field-effect transistor (finfet) having a semiconductor substrate supporting a gate stack, a source, and a drain, a first terminal coupled to the semiconductor substrate and to the gate stack, the first terminal configured to couple with a first power rail, and a second terminal coupled to the source and to the drain, the second terminal configured to couple with a second power rail having a higher potential than the first power rail..
07/03/14
20140183596
Electrostatic discharge protection structure
An electrostatic discharge protection structure includes a semiconductor substrate, a first well region, a gate structure, a second well region, a second well region, a second conductive region, and a deep well region. The first well region contains first type conducting carriers.
07/03/14
20140183562
Semiconductor device and method for fabricating the same
A semiconductor layer 102 having a drift region 132, a body region 103, and a source region 104 provided at a position next to the body region 103; an epitaxial layer 106 in contact with the body region; and a gate insulating film 107 provided on the epitaxial layer are formed on a principal surface of a semiconductor substrate 101. The epitaxial layer includes an interface epitaxial layer 106i in contact with the body region, a first epitaxial layer 106a on the interface epitaxial layer 106i, and a second epitaxial layer 106b on the first epitaxial layer 106a.


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Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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