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Semiconductor Substrate patents



      
           
This page is updated frequently with new Semiconductor Substrate-related patent applications. Subscribe to the Semiconductor Substrate RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Substrate RSS RSS


High-frequency power amplifier and method for manufacturing the same

Mitsubishi Electric

High-frequency power amplifier and method for manufacturing the same

Solar cell

Lg Electronics

Solar cell

Solar cell

Taiwan Semiconductor Manufacturing

Transistor strain-inducing scheme


Date/App# patent app List of recent Semiconductor Substrate-related patents
08/20/15
20150237276 
 Image sensor array with external charge detection circuitry patent thumbnailImage sensor array with external charge detection circuitry
An image sensor may include an array of pixels that, do not include any source follower, reset, or addressing transistors, which helps to increase pixel well capacity, reduces or eliminates random telegraph signal (rts) noise, and reduces undesirable dark current. Charge to voltage conversion may be performed by charge detection circuitry that is external to the array of pixels.
Semiconductor Components Industries, Llc


08/20/15
20150236649 
 High-frequency power amplifier and  manufacturing the same patent thumbnailHigh-frequency power amplifier and manufacturing the same
A high-frequency power amplifier includes: a semiconductor substrate; transistor cells separated from each other and located on the semiconductor substrate; and testing electrodes respectively connected to individual transistor cells, wherein an electrical signal and power to individually operate each corresponding transistor cell are supplied to each transistor cell, independently, from outside, using the testing electrodes.. .
Mitsubishi Electric Corporation


08/20/15
20150236176 
 Solar cell patent thumbnailSolar cell
A method for manufacturing a solar cell according to an embodiment of the present invention includes preparing a semiconductor substrate having a first conductivity type dopant; ion-implanting a pre-amorphization elements into a front surface of the semiconductor substrate to form an amorphous layer; and forming an emitter layer by ion-implanting second conductivity type dopant into the front surface of the semiconductor substrate. The method then further includes heat-treating the layers to activate the second conductivity type dopant.
Lg Electronics Inc.


08/20/15
20150236157 
 Transistor strain-inducing scheme patent thumbnailTransistor strain-inducing scheme
A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/20/15
20150236154 
 Anti-fuse and  forming the same patent thumbnailAnti-fuse and forming the same
An anti-fuse includes a first gate structure disposed in a semiconductor substrate and a second gate structure that is spaced apart from the first gate structure by a distance and disposed in the semiconductor substrate. The first and second gate structures have different depths from each other in the semiconductor substrate..
Sk Hynix Inc.


08/20/15
20150236126 
 Semiconductor device having vertical channel, resistive memory device including the same, and  manufacturing the same patent thumbnailSemiconductor device having vertical channel, resistive memory device including the same, and manufacturing the same
A semiconductor device, a resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device includes a pillar extending substantially perpendicular from a semiconductor substrate, the pillar including an inner portion and an outer portion surrounding the inner portion.
Sk Hynix Inc.


08/20/15
20150236125 
 Semiconductor device and manufacturing method thereof patent thumbnailSemiconductor device and manufacturing method thereof
A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of trenches in a semiconductor substrate, on opposite sides of a gate electrode of a p-type metal-oxide-semiconductor (pmos) disposed on the semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


08/20/15
20150236124 
 Epitaxy in semiconductor structure and manufacturing method thereof patent thumbnailEpitaxy in semiconductor structure and manufacturing method thereof
A semiconductor structure including a semiconductor substrate is provided. The semiconductor substrate includes a surface.
Taiwan Semiconductor Manufacturing Company Ltd.


08/20/15
20150236110 
 Split gate cells for embedded flash memory patent thumbnailSplit gate cells for embedded flash memory
In a method of forming a split gate memory cell, a sacrificial spacer is formed over a semiconductor substrate. A first layer of conductive material is formed over a top surface and sidewalls of the sacrificial spacer.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/20/15
20150236107 
 Ultra high voltage semiconductor device with electrostatic discharge capabilities patent thumbnailUltra high voltage semiconductor device with electrostatic discharge capabilities
A semiconductor device comprises a semiconductor substrate, a first layer over the semiconductor substrate, and a drain region in the first layer. The drain region comprises a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/20/15
20150236099 

Semiconductor device and manufacturing the same


A semiconductor device according to an embodiment includes: a semiconductor substrate; an n-type sic layer provided on one side of the semiconductor substrate; a p-type first sic region provided in the n-type sic layer; a metallic second sic region provided in the p-type first sic region, the second sic region containing at least one element selected from the group of mg, ca, sr, ba, sc, y, la, and lanthanoid; a gate electrode; a gate insulating film provided between the gate electrode and the n-type sic layer, the gate insulating film provided between the gate electrode and the first sic region; a first electrode provided on the second sic region; and a second electrode provided on a side of the semiconductor substrate opposite to the n-type sic layer.. .
Kabushiki Kaisha Toshiba


08/20/15
20150236095 

Semiconductor device


A semiconductor device and a method of making the same. The device includes a semiconductor substrate having an algan layer on a gan layer.
Taiwan Semiconductor Manufacturing Company Ltd.


08/20/15
20150236088 

Semiconductor device


A semiconductor device is provided. On one main surface side of an n-type semiconductor substrate, a p-type diffusion region to serve as an anode of a diode is formed.
Mitsubishi Electric Corporation


08/20/15
20150236067 

Grids in backside illumination image sensor chips and methods for forming the same


A device includes a semiconductor substrate having a front side and a backside, a photo-sensitive device disposed on the front side of the semiconductor substrate, and a first and a second grid line parallel to each other. The first and the second grid lines are on the backside of, and overlying, the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/20/15
20150236032 

Methods for fabricating integrated circuits with a high-voltage mosfet


Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate.
Globalfoundries Singapore Pte. Ltd.


08/20/15
20150236024 

Semiconductor structure having buried conductive elements


Embodiments for the present invention provide a semiconductor device and methods for fabrication. In an embodiment of the present invention, a semiconductor structure comprises a first conductor horizontally formed on a semiconductor substrate.
International Business Machines Corporation


08/20/15
20150236022 

Semiconductor device and manufacturing method thereof


Disclosed herein is a semiconductor device that includes: a semiconductor substrate; a well of a first conductive type that is formed in the semiconductor substrate; an element isolation region embedded in the semiconductor substrate so as to define an active region of the well; first and second gate electrodes each including a side surface and a bottom surface that are covered with the well such that the first and second gate electrodes are formed to traverse the active region, and a peak depth of the well corresponding to the active region is equal to or shallower than a peak depth of the well corresponding to the element isolation region.. .
Ps4 Luxco S.a.r.l.


08/20/15
20150235972 

Semiconductor device having high frequency wiring and dummy metal layer at multilayer wiring structure


A semiconductor device includes a semiconductor substrate, a first wiring layer including a plurality of first dummy metals provided inside an inductor wiring, a plurality of second dummy metals provided outside the inductor wiring, and a plurality of third dummy metals provided to overlap the inductor wiring in a plan view, and a second wiring layer provided between the semiconductor substrate and the first wiring layer. The second wiring layer includes the inductor wiring formed in the second wiring layer, a first region surrounding the inductor wiring which includes a plurality of fourth dummy metals, and a second region surrounding the first region which includes a plurality of fifth dummy metals.
Renesas Electronics Corporation


08/20/15
20150235968 

Method of forming an insulator layer in a semiconductor structure and structures resulting therefrom


An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a first semiconductor substructure over a semiconductor substrate, forming a first spacer layer over the first semiconductor substructure and the semiconductor substrate, and forming a second semiconductor substructure over at least a portion of the first spacer layer..
Intersil Americas Llc


08/20/15
20150235957 

Integrated circuits with improved contact structures


Integrated circuits with improved contact structures are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate disposed with a device therein and/or thereon.
Global Foundries, Inc.


08/20/15
20150235942 

Semiconductor device and manufacturing the same


A semiconductor device and a method for manufacturing the same are disclosed. In the semiconductor device, an upper part of a storage node contact plug is increased in size, and an area of overlap between a storage node formed in a subsequent process and a storage node contact plug is increased, such that resistance of the storage node contact plug is increased and device characteristics are improved.
Sk Hynix Inc.


08/20/15
20150235938 

Patterning methods and methods of forming electrically conductive lines


Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region.
Micron Technology, Inc.


08/20/15
20150235906 

Methods for etching dielectric materials in the fabrication of integrated circuits


Methods for etching dielectric materials in the fabrication of integrated circuits are disclosed herein. In one exemplary embodiment, a method for fabricating an integrated circuit includes forming a layer of a first dielectric material over a gate electrode structure formed on a semiconductor substrate.
Globalfoundries, Inc.


08/20/15
20150235905 

Structure and finfet device


A method of forming a fin field effect transistor (finfet) structure including forming a plurality of shallow trench isolation (sti) features in a semiconductor substrate, thereby defining a plurality of bulk-semiconductor areas separated from each other by the sti features. The method then forms a first hard mask layer on the semiconductor substrate, the first hard mask layer being patterned to have a plurality of openings over one of the bulk-semiconductor areas.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/20/15
20150235901 

Semiconductor device and manufacturing semiconductor device


A semiconductor device has a semiconductor substrate having a first surface and a second surface, a through electrode penetrating through the semiconductor substrate and having a protrusion protruding from the second surface, and an insulation layer on the second surface, which covers the side surface of the protrusion, has an opening through which to expose the end surface of the protrusion, and has a thickness greater than the length of the protrusion.. .
Fujitsu Semiconductor Limited


08/20/15
20150235896 

Methods for fabricating integrated circuits


Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes densifying an upper-surface portion of an ild layer of dielectric material that overlies a metallization layer above a semiconductor substrate to form a densified surface layer of dielectric material.
Globalfoundries, Inc.


08/20/15
20150235895 

Spacer enabled active isolation for an integrated circuit device


A method for forming an active isolation structure in a semiconductor integrated circuit die is disclosed. A first hard mask layer is deposited over a semiconductor substrate.
Microchip Technology Incorporated


08/20/15
20150235867 

Semiconductor device manufacturing method


A semiconductor device manufacturing method, the method including: forming an insulation layer having a protruding portion, the insulation layer having a surface and a rising surface that protrudes upward from the surface, on a semiconductor substrate; forming a conductive layer to cover the insulation layer having the protruding portion; and removing a predetermined region of the conductive layer by patterning the predetermined region according to an etching process using microwave plasma, which uses a microwave as a plasma source, while applying bias power of 70 mw/cm2 or above on the semiconductor substrate, under a high pressure condition of 85 mtorr or above.. .
Tokyo Electron Limited


08/20/15
20150235845 

Method of manufacturing semiconductor device


According to one embodiment, a method of manufacturing a semiconductor device, includes preparing a semiconductor substrate includes a connection pad to electrically connect to a circuit element formed on a main surface, or a rewiring line connected to the connection pad, forming an insulating photosensitive resin film on the substrate with the exclusion of at least an edge portion of the substrate by inkjet, patterning the photosensitive resin film by photolithography, and forming a rewiring line, ubm or an electrode for external connection on the substrate on which the patterned photosensitive resin film is formed.. .
Tera Probe, Inc.


08/20/15
20150235839 

Methods for fabricating integrated circuits using directed self-assembly including lithographically-printable assist features


Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming assisting etch resistant fill topographical features that overlie a semiconductor substrate and that define an assisting etch resistant fill confinement well using a photomask.
Globalfoundries, Inc.


08/20/15
20150235835 

High growth rate process for conformal aluminum nitride


Methods of depositing conformal aluminum nitride films on semiconductor substrates are provided. Disclosed methods involve (a) exposing a substrate to an aluminum-containing precursor, (b) purging the aluminum-containing precursor for a duration insufficient to remove substantially all of the aluminum-containing precursor in gas phase, (c) exposing the substrate to a nitrogen-containing precursor to form aluminum nitride, (d) purging the nitrogen-containing precursor, and (e) repeating (a) through (d).
Lam Research Corporation


08/20/15
20150235702 

Semiconductor device and operating method thereof


The semiconductor device includes a cam block including a plurality of vertical strings having a perpendicular configuration with respect to a semiconductor substrate, wherein each of the plurality of vertical strings is electrically coupled to a plurality of word lines and each of the plurality of word lines is electrically coupled to a plurality of cam cells, a peripheral circuit configured to program cam cells selected from the plurality of cam cells, and a control circuit configured to issue at least one command to the peripheral circuit to simultaneously apply a program voltage to an nth word line, an n−1th word line and an n+1th word line to simultaneously program cam cells electrically coupled to the n−1th word line, the nth word line and the n+1th word line, wherein the n−1th word line and an n+1th word line are adjacent to the nth word line and the selected cam cells are electrically coupled to the nth word line.. .
Sk Hynix Inc.


08/20/15
20150231758 

Method of manufacturing chemical mechanical polishing layers


A method of making a polishing layer for polishing a substrate selected from at least one of a magnetic substrate, an optical substrate and a semiconductor substrate is provided, comprising: providing a liquid prepolymer material; providing a plurality of hollow microspheres; exposing the plurality of hollow microspheres to a carbon dioxide atmosphere for an exposure period to form a plurality of treated hollow microspheres; combining the liquid prepolymer material with the plurality of treated hollow microspheres to form a curable mixture; allowing the curable mixture to undergo a reaction to form a cured material, wherein the reaction is allowed to begin ≦24 hours after the formation of the plurality of treated hollow microspheres; and, deriving at least one polishing layer from the cured material; wherein the at least one polishing layer has a polishing surface adapted for polishing the substrate.. .
Rohm And Haas Electronic Materials Cmp Holdings, Inc.


08/13/15
20150229293 

High-pass filter circuit and band-pass filter circuit


Two types of high-pass filter circuit and a band-pass filter circuit are provided. Both types of high-pass filter circuit include a capacitor configured to input an input signal, a resistor connected between an output terminal of the capacitor and a prescribed bias voltage, and a signal output circuit connected to the output terminal of the capacitor and configured to buffer-amplify the input signal for output.
Ricoh Company, Ltd.


08/13/15
20150228841 

Solar cell manufacturing method


The present invention relates to a method for manufacturing a solar cell having excellent long-term reliability and high efficiency, said method including: a step (7) for applying a paste-like electrode agent to an antireflection film formed on the light receiving surface side of a semiconductor substrate having at least a pn junction, said electrode agent containing a conductive material; and an electrode firing step (9) having local heat treatment (step (9a)) for applying heat such that at least a part of the conductive material is fired by irradiating merely the electrode agent-applied portion with a laser beam, and whole body heat treatment (step (9b)) for heating the whole semiconductor substrate to a temperature below 800° c.. .
Shin-etsu Chemical Co., Ltd.


08/13/15
20150228837 

Photodetector and facricating the same


The present invention provides a photodetector, which comprises a semiconductor substrate and a light absorbing layer (including metal layer, silicide layer) and the opening structures. In addition, a method of fabricating the abovementioned photodetector is also disclosed in the present invention..
National Applied Research Laboratories


08/13/15
20150228819 

Lead-free conductive paste composition and semiconductor devices made therewith


A lead-free conductive paste composition contains a source of an electrically conductive metal, a fusible material, an optional additive, and an organic vehicle. An article such as a high-efficiency photovoltaic cell is formed by a process of deposition of the lead-free paste composition on a semiconductor substrate (e.g., by screen printing) and firing the paste to remove the organic vehicle and sinter the metal and fusible material..
E I Du Pont De Nemours And Company


08/13/15
20150228816 

Solar cell


A solar cell is provided with a semiconductor substrate upon which a textured structure that includes multiple convex parts is formed. The textured structure has chamfered sections between main sloped surfaces of the convex parts, and sharp trough parts, which are sandwiched by adjacent multiple convex parts..
Panasonic Intellectual Property Management Co., Ltd.


08/13/15
20150228814 

Solar cell


A solar cell is provided with: a semiconductor substrate upon which a textured structure is formed; and transparent conductive layers that are formed on the substrate, the thicknesses of which are substantially fixed in a trough part of the textured structure.. .
Panasonic Intellectual Property Management Co., Ltd.


08/13/15
20150228812 

Composition for forming passivation layer, semiconductor substrate having passivation layer, producing semiconductor substrate having passivation layer, photololtaic cell element, producing photovoltaic cell element, and photovoltaic cell


A composition for forming a passivation layer, including a resin and a compound represented by formula (i): m(or1)m. In formula (i), m includes at least one metal element selected from the group consisting of nb, ta, v, y and hf, each r1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5..
Hitachi Chemical Company, Ltd.


08/13/15
20150228806 

Chip diode and manufacturing same


The present invention is directed to a chip diode with a zener voltage vz of 4.0 v to 5.5 v, including a semiconductor substrate having a resistivity of 3 mΩ·cm to 5 mΩ·cm and a diffusion layer formed on a surface of the semiconductor substrate and defining a diode junction region with the semiconductor substrate therebetween, in which the diffusion layer has a depth of 0.01 μm to 0.2 μm from the surface of the semiconductor substrate.. .
Rohm Co., Ltd.


08/13/15
20150228786 

Semiconductor device


A semiconductor device includes a semiconductor substrate having an active region. A gate trench is disposed to cross the active region.
Samsung Electronics Co., Ltd.


08/13/15
20150228779 

Semiconductor device and semiconductor device manufacturing method


In aspects of the invention, an n-type epitaxial layer that forms an n− type drift layer is formed on the upper surface of an n-type semiconductor substrate formed by being doped with a high concentration of antimony. A p-type anode layer is formed on a surface of the n− type drift layer.
Fuji Electric Co., Ltd.


08/13/15
20150228775 

Semiconductor structures and methods for multi-dimension of nanowire diameter to improve drive current


A semiconductor device having a channel formed from a nanowire with a multi-dimensional diameter is provided. The semiconductor device comprises a drain region formed on a semiconductor substrate.
Taiwan Semiconductor Manufacturing Company Limited


08/13/15
20150228769 

Formation of an asymmetric trench in a semiconductor substrate and a bipolar semiconductor device having an asymmetric trench isolation region


Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench.
International Business Machines Corporation


08/13/15
20150228767 

Semiconductor memory device and manufacturing the same


A semiconductor memory device and a method of manufacturing the same are provided. The device includes a semiconductor substrate in which active regions and isolation regions are alternately defined, and a support region is defined in a direction crossing the active regions and the isolation regions, first trenches formed in the isolation regions, second trenches formed under the first trenches in the active regions and the isolation regions; and a support layer formed under the first trenches in the support region..
Sk Hynix Inc.


08/13/15
20150228765 

Method of finfet formation


A method of fabricating a fin for a finfet device includes providing a semiconductor substrate, forming a patterned silicon germanium layer on the semiconductor substrate, epitaxially growing a silicon layer on a top surface and sidewalls of the patterned silicon germanium layer, forming a sacrificial layer covering the patterned silicon germanium layer, and removing the sacrificial layer and a portion of the silicon layer disposed on the top surface of the patterned silicon germanium layer until a top surface of the sacrificial layer is co-planar with the top surface of the patterned silicon germanium layer. The method further includes removing the patterned silicon germanium layer and removing the sacrificial layer to form the fin.
Semiconductor Manufacturing International (shanghai) Corporation


08/13/15
20150228761 

Diamond shaped epitaxy


In a first embodiment of the present invention, a semiconductor device manufacturing process includes forming a plurality of fins on a semiconductor substrate, forming diamond shaped epitaxy on fin sidewalls, merging the diamond shaped epitaxy, and removing the merged epitaxy. In another embodiment of the present invention, a semiconductor device includes a semiconductor substrate including a plurality of fins formed thereupon and unmerged diamond shaped epitaxy formed upon the sidewalls of each fin.
International Business Machines Corporation


08/13/15
20150228758 

Semiconductor device and manufacturing the same


A method for manufacturing a semiconductor device having a field-effect transistor, including forming a trench in a semiconductor substrate, forming a first insulating film in the trench, forming an intrinsic polycrystalline silicon film over the first insulating film, and introducing first conductive type impurities into the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench.
Renesas Electronics Corporation


08/13/15
20150228757 

Side gate assist in metal gate first process


A method of making a semiconductor device in a gate first process with side gate assists. A first gate may be formed within a gate region.
International Business Machines Corporation


08/13/15
20150228752 

Semiconductor device and semiconductor device manufacturing method


In aspects of the invention, an n-type epitaxial layer that forms an n− type drift layer is formed on the upper surface of an n-type semiconductor substrate formed by being doped with a high concentration of antimony. A p-type anode layer is formed on a surface of the n− type drift layer.
Fuji Electric Co., Ltd.


08/13/15
20150228745 

Self-aligned liner formed on metal semiconductor alloy contacts


Metal semiconductor alloy contacts are provided on each of a source region and a drain region which are present in a semiconductor substrate. A transition metal is then deposited on each of the metal semiconductor alloy contacts, and during the deposition of the transition metal, the deposited transition metal reacts preferably, but not necessarily always, in-situ with a portion of each the metal semiconductor alloy contacts forming a transition metal-metal semiconductor alloy liner atop each metal semiconductor alloy contact.
International Business Machines Corporation


08/13/15
20150228743 

Fin field-effect transistors having controlled fin height


An apparatus includes a semiconductor substrate having a plurality of fins, wherein the plurality of fins includes a first group of fins and a second group of fins. The apparatus further includes a high fin density area on the semiconductor substrate including a first dielectric between the first group of fins in the high fin density area, said first dielectric having a first dopant concentration.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/13/15
20150228742 

Method for manufacturing semiconductor device


A semiconductor device and a method of manufacturing the semiconductor device includes forming a first and a second gate electrode on a semiconductor substrate, forming a first and a second insulator on the first and second gate electrodes, forming a third insulator on the second insulator, a first thickness of the third insulator on the first gate electrode being different than a second thickness of the third insulator on the second gate electrode, and etching-back the first, second and third insulators to form a first spacer beside the first gate electrode and a second spacer beside the second gate electrode. Herein, a horizontal length of the first spacer being contacted with a surface of the semiconductor substrate is different from a horizontal length of the second spacer being contacted with a surface of the semiconductor substrate..
Magnachip Semiconductor, Ltd.


08/13/15
20150228737 

Semiconductor device


A semiconductor device includes a base region of a second conduction type provided over a drain region of a first conduction type, an outer peripheral well region of a second conduction type provided to cover the outer peripheral end of the base region and having an impurity concentration lower than that of the base region, a buried electrode buried in the semiconductor substrate not to overlap the outer peripheral well region, plural gate electrodes connected to the buried electrode and buried in the substrate such that each of them is adjacent to a source region, a gate interconnect provided over the substrate to overlap a portion of the outer peripheral well region in a plan view and connected to the buried electrode, and a grounding electrode provided over the substrate and connected to a portion of the outer peripheral well region not overlapping the gate interconnect in a plan view.. .
Renesas Electronics Corporation


08/13/15
20150228736 

Semiconductor device and manufacturing the same


A method for manufacturing a semiconductor device includes processes of: (a) implant first conductivity type first impurities in a first region of a first surface; (b) form a second conductivity type semiconductor region exposed in the second region of the first surface by implanting second conductivity type second impurities in the second region; (c) implant charged particles at a dose amount larger than those of the first and the second impurities in a third region of the first surface which at least partially overlaps with the first region and is adjacent to the second region so that an implantation depth of the charged particles becomes shallower than that of the first impurities. After having performed the processes of (a) to (c), a metal is deposited on the second and the third regions, and the metal is caused to react with the semiconductor substrate to form the silicide layer..
Toyota Jidosha Kabushiki Kaisha


08/13/15
20150228731 

Modified channel position to suppress hot carrier injection in finfets


Some embodiments relate to an integrated circuit (ic) including one or more finfet devices. A finfet includes a fin of semiconductor material extending upwards from a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/13/15
20150228724 

Modulating germanium percentage in mos devices


An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage.

08/13/15
20150228695 

Magnetic memory device


According to one embodiment, a magnetic memory device includes a semiconductor substrate, a memory cell array area on the semiconductor substrate, the memory cell array area including magnetoresistive elements, each of the magnetoresistive elements having a reference layer with an invariable magnetization, a storage layer with a variable magnetization, and a tunnel barrier layer therebetween, a magnetic field generating area which generates a first magnetic field cancelling a second magnetic field applying from the reference layer to the storage layer, and which is separated from the magnetoresistive elements, and a closed magnetic path area functioning as a closed magnetic path of the first magnetic field, and surrounding the memory cell array area and the magnetic field generating area.. .
Kabushiki Kaisha Toshiba


08/13/15
20150228690 

Pad structure including glue layer and non-low-k dielectric layer in bsi image sensor chips


An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/13/15
20150228688 

Image sensor and manufacturing method thereof


According to one embodiment, an image sensor includes an image-sensing element region formed by arranging a plurality of image-sensing elements on a semiconductor substrate, and a logic circuit region formed in a region different from the image-sensing element region on the substrate and including a plurality of gate patterns. Further, dummy gate patterns are formed with a constant pitch on the image-sensing element region..
Kabushiki Kaisha Toshiba


08/13/15
20150228684 

Solid-state imaging device


According to one embodiment, in a solid-state imaging device, a signal storage portion in each of a plurality of pixels includes a first semiconductor region and a second semiconductor region. The first semiconductor region is of a first conductive type.
Kabushiki Kaisha Toshiba


08/13/15
20150228679 

Unit pixel of image sensor and image sensor including the same


A unit pixel of an image sensor includes a photoelectric conversion region, an isolation region, a floating diffusion region and a transfer gate. The photoelectric conversion region is formed in a semiconductor substrate.

08/13/15
20150228652 

Semiconductor device including nanowire transistors with hybrid channels


A semiconductor device is provided that includes an n-type field effect transistor including a plurality of vertically stacked silicon-containing nanowires located in one region of a semiconductor substrate, and a p-type field effect transistor including a plurality of vertically stacked silicon germanium alloy nanowires located in another region of a semiconductor substrate. Each vertically stacked silicon-containing nanowire of the n-type field effect transistor has a different shape than the shape of each vertically stacked silicon germanium alloy nanowire of the p-type field effect transistor..
International Business Machines Corporation


08/13/15
20150228645 

Semiconductor device and manufacturing


A semiconductor device includes a semiconductor substrate, and first and second transistors over the semiconductor substrate. Both the first and second transistors are p-type transistors or both the first and second transistors are n-type transistors.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/13/15
20150228603 

Semiconductor constructions and methods of planarizing across a plurality of electrically conductive posts


Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate.
Micron Technology, Inc.


08/13/15
20150228600 

Packages with stress-reducing structures and methods of forming same


A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/13/15
20150228599 

Self-alignment structure for wafer level chip scale package


A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/13/15
20150228598 

Semiconductor device with post-passivation interconnect structure and forming the same


A semiconductor device, including a protective layer overlying a contact pad and a dummy pad on a semiconductor substrate, an interconnect structure overlying the protective layer and contacting part of the dummy pad through a contact via passing through the protective layer, a bump overlying the interconnect structure positioned over the dummy pad.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


08/13/15
20150228597 

Copper post structure for wafer level chip scale package


In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/13/15
20150228573 

Semiconductor device


Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate having a contact region.
Samsung Electronics Co., Ltd.


08/13/15
20150228557 

Chip package and forming the same


A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess.
Xintec Inc.


08/13/15
20150228545 

Methods of making a monolithic microwave integrated circuit


Low q associated with passive components of monolithic integrated circuits (ics) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 ohm-cm) semiconductor substrates and lower resistance inductors for the ic. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate.
Freescale Semiconductor, Inc.


08/13/15
20150228542 

Method of patterning features of a semiconductor device


A method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/13/15
20150228540 

Semiconductor device producing method


In a method for producing a semiconductor device having a through electrode structure, a masking material is formed so as to bridge over a through hole formed in a second semiconductor substrate, and a hole is formed in the masking material at a position corresponding to the through hole. A contact hole is formed in an insulating film via this hole.
Denso Corportion


08/13/15
20150228538 

Semiconductor device and manufacturing method thereof


According to one embodiment, a semiconductor device includes a semiconductor substrate, an interlayer insulation film, a plug, a first mark, a second mark, and an upper wiring. The substrate has a device region and a mark formation region.
Kabushiki Kaisha Toshiba


08/13/15
20150228536 

Chip package and forming the same


A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate and adjoins a side edge of the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess.
Xintec Inc.


08/13/15
20150228534 

Semiconductor device with shallow trench isolation


A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a trench isolation.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/13/15
20150228511 

Methods and systems for vibratory chemical mechanical planarization


Methods and a system for processing semiconductor substrates are provided. A method of processing a semiconductor substrate includes selecting a predetermined vibration profile that will achieve predetermined material removal characteristics from the semiconductor substrate in a chemical mechanical planarization (cmp) polish, actuating a vibration actuator based on the predetermined vibration profile, and polishing the semiconductor substrate based substantially entirely on the predetermined vibration profile achieved by actuation of the vibration actuator..
Globalfoundries, Inc.


08/13/15
20150228503 

Hardmask trimming in semiconductor fin patterning


Embodiments may involve a method of semiconductor patterning, which includes patterning a first hardmask layer on top of a second hardmask layer. This patterning may define a feature with a first width.
Applied Materials, Inc.


08/13/15
20150228493 

Manufacturing semiconductor device


A technique of reducing the contact resistance between a semiconductor substrate and a metal layer is provided. A manufacturing method of a semiconductor device comprises a process of forming a metal layer on an n surface of a nitride semiconductor substrate.
Toyoda Gosei Co., Ltd.


08/13/15
20150228482 

Silicon carbide semiconductor substrate and manufacturing same


A silicon carbide semiconductor substrate is made of a silicon carbide single crystal and is formed with a stamp on at least a surface as an identification indication formed of a crystal defect. When a silicon carbide single crystal is allowed to grow using the silicon carbide semiconductor substrate as a seed crystal, the stamp can be propagated to the silicon carbide single crystal as a crystal defect.
Denso Corporation


08/13/15
20150228347 

Nonvolatile semiconductor memory device and data erase method thereof


A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, memory strings, drain side selection transistors, source side selection transistors, word lines, bit lines, a source line, a drain side selection gate line, a source side selection gate line, and a control circuit. The control circuit applies a first voltage to a selected bit line, thereby executing an erase operation on a selected memory string connected to the selected bit line, and the control circuit applies a second voltage to a non-selected bit line, thereby prohibiting the erase operation for the selected memory string connected to the non-selected bit line.
Kabushiki Kaisha Toshiba




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Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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