|| List of recent Semiconductor Substrate-related patents
|Diarylamine novolac resin|
(in formula (1), each of ar1 and ar2 is a benzene ring or a naphthalene ring). A method for manufacturing a semiconductor device, including: forming an underlayer film on a semiconductor substrate with the resist underlayer film-forming composition; forming a hardmask on the underlayer film; forming a resist film on the hardmask; forming a resist pattern by irradiation with light or an electron beam followed by development; etching the hardmask with the resist pattern; etching the underlayer film with the hardmask thus patterned; and processing the semiconductor substrate with the underlayer film thus patterned..
|Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches|
Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer.
|Multi-composition dielectric for semiconductor device|
The present disclosure provides a method of semiconductor device fabrication including forming a multi-composition ild layer by forming a first portion of an inter-layer dielectric (ild) layer on a semiconductor substrate; and forming a second portion of an ild layer on the first portion of the ild layer. The second portion may have a greater silicon content than the first portion.
|Semiconductor device and method of forming epitaxial layer|
A method for forming epitaxial layer is disclosed. The method includes the steps of providing a semiconductor substrate, and forming an undoped first epitaxial layer in the semiconductor substrate.
|Method of making mosfet integrated with schottky diode with simplified one-time top-contact trench etching|
Method for fabricating mosfet integrated with schottky diode (mosfet/sky) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein.
|Semiconductor manufacturing apparatus and manufacturing method of semiconductor device|
A semiconductor manufacturing apparatus according to the present embodiment comprises a vacuum chamber. A first stage is configured to temporarily attach a reticle thereonto in order to attract a foreign material present on a back surface of the reticle.
|Solid-state imaging device, manufacturing method thereof, and electronic apparatus|
A solid-state imaging device having a backside illuminated structure, includes: a pixel region in which pixels each having a photoelectric conversion portion and a plurality of pixel transistors are arranged in a two-dimensional matrix; an element isolation region isolating the pixels which is provided in the pixel region and which includes a semiconductor layer provided in a trench by an epitaxial growth; and a light receiving surface at a rear surface side of a semiconductor substrate which is opposite to a multilayer wiring layer.. .
|Digital camera with multiple pipeline signal processors|
A method includes sampling a first intensity of light with a first array of photo detectors of a digital camera. A second intensity of light is sampled with a second array of photo detectors of the digital camera.
|Semiconductor device and manufacturing method thereof|
A semiconductor device according to an embodiment includes a semiconductor substrate that includes a first region and a second region having a thickness that is less than a thickness of the first region, a first metal film having a same film thickness provided in each of a first through hole, and a second through hole, the first through hole penetrating the semiconductor substrate from the second surface to the first surface in the first region, and the second through hole penetrating the semiconductor substrate from the second surface to the first surface in the second region. A second metal film is formed on the first metal films and is provided inside the first through hole, and inside and outside of the second through hole.
|Semiconductor device and electronic apparatus|
A semiconductor device that is connected to a wiring substrate includes a semiconductor substrate, a circuit provided on the semiconductor substrate, a connection terminal, and a guard ring that is provided on a peripheral region. In the semiconductor device, the guard ring includes a plurality of wiring layers, and a wiring layer included in the guard ring, which is the farthest from the semiconductor substrate, corresponds to a wiring layer closer to the semiconductor substrate relative to a wiring layer of the connection terminal..
The present invention includes a semiconductor substrate and a back electrode (a back multilayer electrode in the preferred embodiment) provided on a back surface of the semiconductor substrate. A rough source pattern is formed in a peripheral edge portion of the back surface of the semiconductor substrate which faces the back multilayer electrode..
A semiconductor device is provided, including a semiconductor substrate that includes a semiconductor; an electrode layer formed above a first surface side inside the semiconductor substrate; a conductor layer formed above the electrode layer and above the first surface of the semiconductor substrate; a hole formed through the semiconductor substrate from a second surface of the semiconductor substrate to the conductor layer; and a wiring layer that is electrically connected to the electrode layer via the conductor layer at an end portion of the vertical hole, and that extends to the second surface of the semiconductor substrate, the wiring layer being physically separated from the electrode layer by an insulating layer disposed therebetween.. .
|Device bond pads over process control monitor structures in a semiconductor die|
A semiconductor die includes a semiconductor substrate having an edge region surrounding an active region, the active region containing devices of an integrated circuit. The semiconductor die further includes interconnect wiring over the active region in an interlayer dielectric and electrically connected to the devices in the active region, and ancillary wiring over the edge region in the interlayer dielectric and isolated from the interconnect wiring and the devices in the active device region.
|Back end of the line (beol) interconnect scheme|
The present disclosure relates to a method of forming a back-end-of-the-line metal interconnect layer. The method is performed by depositing one or more self-assembled monolayers on a semiconductor substrate to define a metal interconnect layer area.
|Bipolar junction transistor and method of manufacturing the same|
A bipolar junction transistor (bjt) is provided. The bjt can include a semiconductor substrate, a first well disposed in the substrate and implanted with a first impurity, a second well disposed at one side of the first well and implanted with a second impurity, a first device isolation layer disposed in the first well and defining an emitter area, and a second device isolation layer disposed in the second well and defining a collector area, the bjt can also include an emitter having a second impurity, a base having a first impurity, a collector having a second impurity, and a high concentration doping area having a second impurity at high concentration.
|Process of ultra thick trench etch with multi-slope profile|
The present disclosure relates to an integrated chip (ic) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ild) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the ic has an inter-level dielectric layer disposed above a semiconductor substrate.
|Integrated circuits with improved gate uniformity and methods for fabricating same|
Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, an integrated circuit includes a semiconductor substrate and a replacement metal gate structure overlying the semiconductor substrate.
|Fin deformation modulation|
A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench.
|Ldmos device with double-sloped field plate|
In one general aspect, an apparatus can include a channel region disposed in a semiconductor substrate, a gate dielectric disposed on the channel region and a drift region disposed in the semiconductor substrate adjacent to the channel region. The apparatus can further include a field plate having an end portion disposed between a top surface of the semiconductor substrate and the gate dielectric the end portion can include a surface in contact with the gate dielectric, the surface having a first portion aligned along a first plane non-parallel to a second plane along which a second portion of the surface is aligned, the first plane being non-parallel to the top surface of the semiconductor substrate and the second plane being non-parallel to the top surface of the semiconductor substrate..
|Super junction semiconductor device comprising implanted zones|
In a semiconductor substrate with a first surface and a working surface parallel to the first surface, columnar first and second super junction regions of a first and a second conductivity type are formed. The first and second super junction regions extend in a direction perpendicular to the first surface and form a super junction structure.
|Methods of inducing a desired stress in the channel region of a transistor by performing ion implantation/anneal processes on the gate electrode|
One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that allows implantation of ions into the gate electrode but not into areas of the active region where source/drain regions for the transistor will be formed, performing a gate ion implantation process to form a gate ion implant region in the gate electrode and performing an anneal process. An n-type transistor including sidewall spacer structures positioned adjacent a gate structure, a plurality of source/drain regions for the transistor and a gate implant region positioned in a gate electrode, wherein the gate implant region is comprised of ions of phosphorous, arsenic or an implant material with an atomic size that is equal to or greater than the atomic size of phosphorous at a concentration level that falls within the range of 5e18-5e21 ions/cm3..
|Nonvolatile semiconductor storage device and method of manufacturing the same|
A nonvolatile semiconductor storage device includes a semiconductor substrate; a first insulating film disposed above the semiconductor substrate; a first electrode film disposed above the first insulating film; a second insulating film disposed above the first electrode film; a second electrode film disposed above the second insulating film; a third electrode film filling a first trench and overlying the second electrode film, the first trench having a first width and a first depth and extending through the second electrode film and the second insulating film and into the first electrode film; and a first barrier metal film and a first metal film disposed above the third electrode film; wherein the third electrode film above the second electrode film has a first thickness equal to or less than ½ of the first width of the first trench.. .
|Mim capacitor in finfet structure|
A finfet structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride on the sides and horizontal surface of the silicon fins; a polysilicon gate layer over the second layer of titanium nitride on the silicon fins and over the semiconductor substrate such that first and second ends of the silicon fins protrude from the polysilicon layer; spacers adjacent to the polysilicon gate layer; epitaxial silicon over the first and second ends of the silicon fins to form sources and drains, wherein the combination of the first layer of titanium nitride, dielectric layer and second layer of titanium nitride forms a metal-insulator-metal capacitor situated between each silicon fin and the polysilicon layer.. .
|Mim capacitor in finfet structure|
A method of forming a finfet structure having a metal-insulator-metal capacitor. Silicon fins are formed on a semiconductor substrate followed by formation of the metal-insulator-metal capacitor on the silicon fins by depositing sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride.
|Integrated circuits and methods for fabricating integrated circuits having metal gate electrodes|
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a sacrificial gate structure over a semiconductor substrate.
A semiconductor device includes a semiconductor substrate and a first electrode. An element region, and a non-element region that surrounds this element region, are formed on the semiconductor substrate.
|Igbt and method of manufacturing the same|
An igbt has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region..
|High voltage electrostatic discharge protection device|
An electrostatic discharge protection device is provided. The electrostatic discharge protection device can include a semiconductor substrate having a first well and a second well, a silicon controller rectifier (scr) device, and first and second impurity areas disposed on the first and second wells to form a pn junction.
|Memory device using graphene as charge-trap layer and method of operating the same|
A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges..
|Light-receiving device, light receiver using same, and method of fabricating light-receiving device|
An apparatus includes a flip-chip semiconductor substrate, a light detection element configured to be formed over the flip-chip semiconductor substrate and to have a laminate structure including a first semiconductor layer of a first-conductive-type, a light-absorption layer formed over the first semiconductor layer, and a second semiconductor layer of a second-conductive-type formed over the light-absorption layer, an inductor configured to be connected to the light detection element over the flip-chip semiconductor substrate, an output electrode for bump connection configured to output a current generated by the light detection element through the inductor, a bias electrode for bump connection configured to apply a bias voltage to the light detection element through a bias electrode, and a line configured to cause a metal line of the inductor and the light detection element to be connected to the output electrode or the bias electrode.. .
|Eda tool and method, and integrated circuit formed by the method|
A method comprises: accessing data representing a layout of a layer of an integrated circuit (ic) comprising a plurality of polygons defining circuit patterns to be divided among a number (n) of photomasks for multi-patterning a single layer of a semiconductor substrate, where n is greater than one. For each set of n parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least n−1 stitches are inserted in each polygon within that set to divide each polygon into at least n parts, such that adjacent parts of different polygons are assigned to different photomasks from each other.
|Apparatus and methods for improving the intensity profile of a beam image used to process a substrate|
Methods and apparatuses are provided for improving the intensity profile of a beam image used to process a semiconductor substrate. At least one photonic beam may be generated and manipulated to form an image having an intensity profile with an extended uniform region useful for thermally processing the surface of the substrate.
|Semiconductor processing systems having multiple plasma configurations|
An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access.
|Methods for fabricating integrated circuits with improved semiconductor fin structures|
Methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes providing a mandrel layer overlying a semiconductor substrate and patterning the mandrel layer into mandrel structures.
|Semiconductor device and method of fabricationg the same|
A method of fabricating a semiconductor device includes forming first gate patterns on a semiconductor substrate using an etch mask pattern, forming a trench in the semiconductor substrate between the first gate patterns, forming an insulating layer in the trench, such that the insulating layer fills the trench and is disposed on the etch mask pattern, planarizing the insulating layer until a top surface of the etch mask pattern is exposed, etching a portion of the planarized insulating layer to form a device isolation layer in the trench, forming a second gate layer covering the etch mask pattern and disposed on the device isolation pattern, and planarizing the second gate layer until the top surface of the etch mask pattern is exposed, such that a second gate pattern is formed.. .
|Methods of forming multiple n-type semiconductor devices with different threshold voltages on a semiconductor substrate|
One illustrative method disclosed herein involves forming an integrated circuit product comprised of first and second n-type transistors formed in and above first and second active regions, respectively. The method generally involves performing a common threshold voltage adjusting ion implantation process on the first and second active regions, forming the first and second transistors, performing an amorphization ion implantation process to selectively form regions of amorphous material in the first active region but not in the second active region, after performing the amorphization ion implantation process, forming a capping material layer above the first and second transistors and performing a re-crystallization anneal process to convert at least portions of the regions of amorphous material to a crystalline material.
|Method of manufacturing a semiconductor device|
A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of misfet are formed in the peripheral circuit region.
|Method of manufacturing semiconductor device|
Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a misfet is formed.
|Method of manufacturing semiconductor device|
A method of manufacturing a semiconductor device which includes forming first and second gate patterns, forming first and second sidewall spacers on sidewalls of the first and second gate patterns respectively, implanting a first impurity into the semiconductor substrate, forming a third sidewall spacer on the first sidewall spacer and a fourth sidewall spacer on the second sidewall spacer in such a manner that the third sidewall spacer is in contact with the fourth sidewall spacer between the first and second gate patterns, implanting a second impurity into the semiconductor substrate, and removing the third and the fourth sidewall spacers.. .
|Method to package multiple mems sensors and actuators at different gases and cavity pressures|
A method for fabricating a multiple mems device. A semiconductor substrate having a first and second mems device, and an encapsulation wafer with a first cavity and a second cavity, which includes at least one channel, can be provided.
|Semiconductor manufacturing apparatus and manufacturing method of semiconductor device|
A semiconductor manufacturing apparatus according to the present embodiment includes a vacuum chamber. A stage mounts a semiconductor substrate thereon within the vacuum chamber.
|Device package and methods for the fabrication and testing thereof|
Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure.
|Solid-state imaging device and control system|
A solid-state imaging device is provided. The solid-state imaging device includes an imaging region having a plurality of pixels arranged on a semiconductor substrate, in which each of the pixels includes a photoelectric converting portion and a charge converting portion for converting a charge generated by photoelectric conversion into a pixel signal and blooming is suppressed by controlling a substrate voltage of the semiconductor substrate..
|Electric connection method|
An electric connection method for connection between a semiconductor substrate and an electric wiring substrate includes a first process for providing the semiconductor substrate having a heating member and a pad and the electric wiring substrate having first wiring and second wiring, a second process for electrically connecting the first wiring and the heating member, a third process for causing the heating member to generate heat by supplying power to the heating member through the first wiring, and a fourth process for electrically connecting the pad and the second wiring at a temperature higher than a temperature for electrically connecting the first wiring and the heating member.. .
|System in package (sip) with dual laminate interposers|
There is provided a semiconductor device assembly with an interposer and method of manufacturing the same. More specifically, in one embodiment, there is provided a semiconductor device assembly comprising a semiconductor substrate, at least one semiconductor die attached to the semiconductor substrate, an interposer disposed on the semiconductor die, and a controller attached to the interposer.
|Isolation structure for stacked dies|
An isolation structure for stacked dies is provided. A through-silicon via is formed in a semiconductor substrate.
An embodiment of the disclosure provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed on the first surface and extending into the first recess and/or the second recess; an insulating layer located between the wire layer and the semiconductor substrate; a chip disposed on the first surface; and a conducting structure disposed between the chip and the first surface.. .
|Semiconductor device and manufacturing method for same|
The present invention is directed to a semiconductor device including a semiconductor substrate, a through hole penetrating the semiconductor substrate, a base film covering the through hole, a conductive layer disposed on the base film, an insulating film formed on the side wall of the through hole, and a conductive material embedded in the through hole via the insulating film, in which the base film has a stepped portion formed by an opening pattern that selectively exposes the conductive layer therethrough into the through hole, and in which the conductive material is connected electrically to the conductive layer through the opening pattern.. .
|Interconnect structure including a continuous conductive body|
Some embodiments of the present disclosure relate to an interconnect structure for connecting devices of a semiconductor substrate. The interconnect structure includes a dielectric layer over the substrate and a continuous conductive body passing through the dielectric layer.
|Semiconductor module system having encapsulated through wire interconnect (twi)|
A semiconductor module system includes a module substrate and a semiconductor substrate having a through wire interconnect bonded to an electrode on the module substrate. The through wire interconnect includes a via, a wire in the via having a first end bonded to a substrate contact on the semiconductor substrate and a polymer layer at least partially encapsulating the wire.
|Finfets with reduced parasitic capacitance and methods of forming the same|
An integrated circuit structure includes a semiconductor substrate, a semiconductor strip over a portion of the semiconductor substrate, and a shallow trench isolation (sti) region on a side of the semiconductor strip. The sti region includes a dielectric layer, which includes a sidewall portion on a sidewall of the semiconductor strip and a bottom portion.
|Solid-state imaging device, production method of the same, and imaging apparatus|
A solid-state imaging device in which a pixel circuit formed on the first surface side of a semiconductor substrate is shared by a plurality of light reception regions and second surface side of the semiconductor substrate is the light incident side of the light reception regions. The second surface side regions of the light reception regions are arranged at approximately even intervals and the first surface side regions of the light reception regions e are arranged at uneven intervals.
|Enhancing mosfet performance with corner stresses of sti|
The present invention relates to enhancing mosfet performance with the corner stresses of sti. A method of manufacturing a mos device comprises the steps of: providing a semiconductor substrate; forming trenches on the semiconductor substrate and at least a pmos region and at least an nmos region surrounded by the trenches; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each of the pmos and nmos regions so as to form exposed regions; filling the exposed regions with a insulating material; and forming pmos and nmos devices on the pmos region and the nmos region, respectively, wherein each of the pmos and nmos devices comprises a channel, a gate formed above the channel, and a source and a drain formed at both sides of the channel; wherein in a channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position of the channel, or the boundary of each exposed region extends along the channel length direction to be aligned with the boundary of corresponding pmos or nmos region..
|Laterally difffused metal oxide semiconductor device and method of forming the same|
A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region.
|Method of fabricating semiconductor device|
In a method of fabricating a semiconductor device having a misfet of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.. .
|Device structure and manufacturing method using hdp deposited source-body implant block|
This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate.
|Flash memory cells having trenched storage elements|
An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench.
|Esd protection with integrated ldmos triggering junction|
An electrostatic discharge (esd) protection device includes a semiconductor substrate, a base region in the semiconductor substrate and having a first conductivity type, an emitter region in the base region and having a second conductivity type, a collector region in the semiconductor substrate, spaced from the base region, and having the second conductivity type, a breakdown trigger region having the second conductivity type, disposed laterally between the base region and the collector region to define a junction across which breakdown occurs to trigger the esd protection device to shunt esd discharge current, and a gate structure supported by the semiconductor substrate over the breakdown trigger region and electrically tied to the base region and the emitter region. The lateral width of the breakdown trigger region is configured to establish a voltage level at which the breakdown occurs..
|Gallium nitride semiconductor device with improved termination scheme|
This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein..
|Semiconductor device and method of manufacturing semiconductor device|
A semiconductor device including: a base material portion that includes a semiconductor substrate and an insulating film that is formed on one face of the semiconductor substrate and on which a vertical hole is formed along the thickness direction of the semiconductor substrate; a vertical hole wiring portion that includes a vertical hole electrode formed on a side wall of the base material portion that forms the vertical hole; a metallic film that is formed within the insulating film and that is electrically connected to the vertical hole wiring portion; and a conductive protective film that is formed to be in contact with the metallic film within the insulating film and that is formed in a region that includes a contact region of a probe during a probe test that is performed in the middle of manufacture on a film face of the metallic film.. .
An electronic device (1) includes a semiconductor substrate (3) having a front surface (7), a first electrode (8) and a second electrode (9) disposed on the front surface (7) of the substrate (3), wherein the first electrode (8) and the second electrode (9) each have at least one epitaxial graphene monolayer (10). The at least one epitaxial graphene monolayer (10) of the first electrode (8) forms an ohmic contact with the substrate (3) and the at least one epitaxial graphene monolayer (10) of the second electrode (9) forms a schottky barrier with the substrate (3)..
|Methods for fabricating integrated circuits having gate to active and gate to gate interconnects|
Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode.
|Methods of forming semiconductor devices by forming a semiconductor layer above source/drain regions prior to removing a gate cap layer|
One example of a method disclosed herein for forming a gate electrode in a field effect transistor comprises forming a gate structure above a semiconductor substrate, the gate structure comprising a gate electrode and a gate cap layer positioned above the gate electrode, forming sidewall spacers adjacent the sidewalls of the gate structure, forming a semiconductor layer above portions of the source/drain regions not covered by the gate structure and the sidewall spacers and performing at least one etching process to remove the gate cap layer from above the gate electrode and to remove at least a portion of the semiconductor layer.. .
|Methods for forming semiconductor regions in trenches|
A method includes recessing a portion of a semiconductor substrate between opposite isolation regions to form a recess. After the step of recessing, the portion of the semiconductor substrate includes a top surface.
|Fully isolated ligbt and methods for forming the same|
A method includes growing an epitaxy semiconductor layer over a semiconductor substrate. The epitaxy semiconductor layer is of a first conductivity type.
|Semiconductor device manufacturing method|
A semiconductor device includes: a semiconductor substrate; a heat sink mounted on an upper surface of the semiconductor substrate; wirings formed on a lower surface of the semiconductor substrate; and the like. The heat sink is mounted on the upper surface of the semiconductor substrate, and a planar size thereof is approximately the same as that of the semiconductor substrate.
|Capacitor-less memory cell, device, system and method of making same|
A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line.
|Solid-state imaging device, method of manufacturing solid-state imaging device, and imaging apparatus|
There is provided a solid-state imaging device including a semiconductor substrate having an effective region in which a photodiode performing a photoelectric conversion is formed and, an optical black region shielded by a light shielding film; a first film which is formed on the effective region and in which at least one layer or more of layers having a negative fixed charge are laminated; and a second film which is formed on the light shielding region and in which at least one layer or more of layers having a negative fixed charge are laminated, in which the number of layers formed in the first film is different from the number of layers formed in the second film.. .
|Semiconductor device and method of fabricating the same|
A semiconductor device includes a bonding pad on a semiconductor substrate, a bump on the bonding pad, a solder on the bump, and an anti-wetting layer between the bump and the solder extending along a sidewall of the bump, the anti-wetting layer having a first thickness t1 along the sidewall of the bump closer to the solder and a second thickness t2 along the sidewall of the bump closer to the bonding pad, wherein t2<t1.. .
|Power semiconductor device with an edge termination region|
A power semiconductor device includes a semiconductor substrate, an active device region disposed in the semiconductor substrate, an edge termination region spaced laterally outward from the active device region in the semiconductor substrate, and first and second trenches. The first trench is disposed in the edge termination region and has an inner sidewall, an outer sidewall and a bottom, the inner sidewall being spaced closer to the active device region than the outer sidewall.
A semiconductor device includes a semiconductor substrate having a first surface, a through silicon via (tsv) that is formed so that at least a part thereof penetrates through the semiconductor substrate, and an insulation ring. The insulation ring is formed so as to penetrate through the semiconductor substrate and so as to surround the tsv.
|Semiconductor devices having through silicon vias and methods of fabricating the same|
A semiconductor device is provided having an insulating layer on a semiconductor substrate. The insulating layer and the semiconductor substrate define a through hole penetrating the semiconductor substrate and the insulating layer.
|Semiconductor device and manufacturing method thereof|
A semiconductor device according to the present embodiment includes a semiconductor substrate. A plurality of line patterns are formed into stripes present above the semiconductor substrate.
|Methods of forming a transistor device on a bulk substrate and the resulting device|
One illustrative method disclosed herein includes forming a trench within an isolated region of a bulk semiconductor substrate, forming a region of an insulating material in the trench and forming a semiconductor material within the trench and above the upper surface of the region of insulating material. A substrate disclosed herein includes an isolated substrate region in a bulk semiconductor substrate, a region of an insulating material that is positioned within a trench defined in the isolated substrate region and a semiconductor material positioned within the trench and above the upper surface of the region of insulating material..
|Semiconductor optoelectronics devices|
A semiconductor device comprising a semiconductor substrate with a plurality of photo-diodes arranged in the semiconductor substrate with interconnect layers defining apertures at the photo-diodes and a first polymer which fills the gaps such as to cover the photo-diode. Further, layers of color filters are arranged on top the gap filling polymer layer opposite to the photo-diodes and a second polymer arranged on the interconnect layers covers and planarizes and passivates the color filter layers.
|Semiconductor device and method of manufacturing the same|
A transistor device comprising epitaxial ldd and halo regions and a method of manufacturing the same are disclosed. According to embodiments of the present disclosure, the method may comprise: forming a gate stack on a semiconductor substrate; forming a gate spacer which covers the top of the gate stack and sidewalls of the gate stack; forming source/drain grooves; epitaxially growing a halo material layer in the source/drain grooves, wherein the halo material layer has a first doping element therein; epitaxially growing source/drain regions which apply stress to a channel region of the device, wherein the source/drain regions have a second doping element, opposite in conductivity to the first doping element, therein; isotropically etching the source/drain regions to remove portions of the source/drain regions, wherein the etching also removes portions of the halo material layer directly under the gate spacer and extends to the channel region to some extent, wherein remaining portions of the halo material layer constitute halo regions of the device; and epitaxially growing an ldd material layer to form ldd regions of the device..
|Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same|
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate.
|Methods for forming semiconductor regions in trenches|
A structure includes a semiconductor substrate including a first semiconductor material. A portion of the semiconductor substrate extends between insulation regions in the semiconductor substrate.
|One-time programmable memory and method for making the same|
A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate..
|Integrated circuits having replacement gate structures and methods for fabricating the same|
A method of fabricating an integrated circuit includes forming an interlayer dielectric (ild) layer over a dummy gate stack. The dummy gate stack includes a dummy gate structure, a hardmask layer, and sidewall spacers formed over a semiconductor substrate.
|Unit pixel of image sensor and image sensor including the same|
A unit pixel of an image sensor includes a photoelectric conversion region, a floating diffusion region, and a transfer gate. The photoelectric conversion region is in an active region defined by an isolation region of a semiconductor substrate.
|Method for fabricating mesa sidewall with spin coated dielectric material and semiconductor element thereof|
A method for fabricating a mesa sidewall with a spin coated dielectric material and a semiconductor element fabricated by the same are provided in the present invention. The method includes the steps of: disposing an object on a semiconductor substrate; performing a spin coating process to coat with a liquid dielectric material; performing a drying process to dry the liquid dielectric material; performing a first etching process to remove an upper part of the dried dielectric material to expose a metal part (unaffected by ion bombardment) of the object; performing a deposition process to insulate the metal part (unaffected by ion bombardment) of the object; and performing a second etching process to form a semiconductor element with a mesa sidewall..
A semiconductor device in which a diode region and an igbt region are formed on a same semiconductor substrate is provided. The diode region includes a plurality of first conductivity type anode layers exposed to a surface of the semiconductor substrate and separated from each other.
|Light emitting device and electronic apparatus|
There is provided a light emitting device including: a semiconductor substrate; a plurality of pixel circuits that is disposed in a display region of the semiconductor substrate; a first wiring that is formed of a conductive material so as to be supplied with a predetermined electric potential; and a plurality of first contact portions that is formed of a conductive material so as to connect the semiconductor substrate and the first wiring. The plurality of first contact portions and the first wiring are provided in the display region..
|Semiconductor device and method of manufacturing semiconductor device|
A donor layer that is formed by performing a heat treatment for a crystal defect formed by proton radiation is provided in an n-type drift layer of an n− semiconductor substrate. The donor layer has an impurity concentration distribution including a portion with the maximum impurity concentration and a portion with a concentration gradient in which the impurity concentration is reduce to the same impurity concentration as that of the n-type drift layer in a direction from the portion with the maximum impurity concentration to both surfaces of the n-type drift layer.