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Semiconductor Substrate patents



      
           
This page is updated frequently with new Semiconductor Substrate-related patent applications. Subscribe to the Semiconductor Substrate RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Substrate RSS RSS


Integrated circuits and methods of forming the same with embedded interconnect connection to through-semiconductor via

Solid-state photodetector pixel and photodetecting method

Date/App# patent app List of recent Semiconductor Substrate-related patents
07/24/14
20140208283
 Dummy shoulder structure for line stress reduction patent thumbnailnew patent Dummy shoulder structure for line stress reduction
Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate.
07/24/14
20140206202
 Manufacturing method of semiconductor device and semiconductor manufacturing apparatus patent thumbnailnew patent Manufacturing method of semiconductor device and semiconductor manufacturing apparatus
A manufacturing method of a semiconductor device according to the present invention comprises cleaning a semiconductor substrate. A first chemical liquid for forming a water-repellent protection film and a second chemical liquid coating the first chemical liquid are supplied on a surface of the semiconductor substrate.
07/24/14
20140206194
 Method for manufacturing a semiconductor device patent thumbnailnew patent Method for manufacturing a semiconductor device
A method for manufacturing a semiconductor device includes forming an etch-target layer over a semiconductor substrate having a lower structure, forming a first mask pattern over the etch-target layer, forming a spacer material layer with a uniform thickness over the etch-target layer including the first mask pattern, forming a second mask pattern on an indented region of the space material layer, and etching the etch-target layer with the first mask pattern and the second mask pattern as an etch mask to form a fine pattern.. .
07/24/14
20140206190
 Silicide formation in high-aspect ratio structures patent thumbnailnew patent Silicide formation in high-aspect ratio structures
Embodiments of the present invention include methods of forming a silicide layer on a semiconductor substrate. In an exemplary embodiment, a metal layer may first be deposited above a semiconductor substrate using a chemical vapor deposition process with a metal amidinate precursor and then the semiconductor substrate may be annealed, causing the semiconductor substrate to react with the metal layer forming a metal-rich silicide layer on the semiconductor substrate.
07/24/14
20140206188
 Method of forming a metal silicide layer patent thumbnailnew patent Method of forming a metal silicide layer
A method for forming a metal silicide layer is disclosed. The method includes the steps of: forming a first metal layer with a thickness less than 10 nm on a silicon substrate; forming a second metal layer with a thickness more than 10 nm on the first metal layer; annealing the metal layers and the silicon substrate, so that a part of the second metal layer penetrates through the first metal layer, and both the part of the second metal layer penetrating through the first metal layer and a part of the first metal layer react with the silicon substrate to form the metal silicide layer, while the remaining part of the first and second metal layers form a third metal layer; and removing the third metal layer, so that the metal silicide layer can be formed in the semiconductor substrate..
07/24/14
20140206174
 Method of making semiconductor device patent thumbnailnew patent Method of making semiconductor device
A method for fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, and a first region, a second region and a third region are defined thereon.
07/24/14
20140206163
 Electronic component, a semiconductor wafer and a method for producing an electronic component patent thumbnailnew patent Electronic component, a semiconductor wafer and a method for producing an electronic component
An electronic component includes a semiconductor substrate defined by a generally planar first face, a generally planar second face and side faces extending between the generally planar second face and the generally planar first face. The semiconductor substrate has a curved contour between the generally planar second face and the side faces..
07/24/14
20140206161
 Method of fabricating a semiconductor device having a capping layer patent thumbnailnew patent Method of fabricating a semiconductor device having a capping layer
A method of semiconductor device fabrication includes forming a first dummy gate structure in a first region of a semiconductor substrate and forming a second dummy gate structure in a second region of the semiconductor substrate. A protective layer (e.g., oxide and/or silicon nitride hard mask) is formed on the second dummy gate structure.
07/24/14
20140206145
 Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods patent thumbnailnew patent Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate.
07/24/14
20140203894
 Notch filter structure with open stubs in semiconductor  substrate and design structure patent thumbnailnew patent Notch filter structure with open stubs in semiconductor substrate and design structure
On-chip millimeter wave (mmw) notch filters with via stubs, methods of manufacture and design structures are disclosed. The notch filter includes a signal line comprising a metal trace line connected to a metal via stub partially extending into a semiconductor substrate.
07/24/14
20140203827
new patent Integrated circuits and methods of forming the same with embedded interconnect connection to through-semiconductor via
Integrated circuits, methods of forming integrated circuits, and methods of sensing voiding between a through-semiconductor via and a subsequent layer that overlies the through-semiconductor via in integrated circuits are provided. An exemplary method of forming an integrated circuit includes forming a plurality of semiconductor devices on a semiconductor substrate.
07/24/14
20140203449
new patent Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via
Integrated circuits and methods of forming integrated circuits are provided herein, in which a plurality of semiconductor devices is formed on a semiconductor substrate. At least one through-semiconductor via is formed in the semiconductor substrate and an interlayer dielectric layer is formed overlying the at least one through-semiconductor via and the plurality of semiconductor devices.
07/24/14
20140203448
new patent Random coded integrated circuit structures and methods of making random coded integrated circuit structures
Randomized coded arrays and methods of forming a randomized coded array. The methods include: forming a dielectric layer on a semiconductor substrate; forming an array of openings extending through the dielectric layer; introducing particles into a random set of less than all of the openings; and forming a conductive material in each opening of the array of openings, thereby creating the randomized coded array, wherein a first resistance of a pathway through the conductive material in openings containing the particles is different from a second resistance of a path through openings not containing the particles.
07/24/14
20140203441
new patent Semiconductor device and method of manufacturing the same
The semiconductor device includes a first conductive layer, a first interlayer insulating film, a bit line, a first insulating film, a second interlayer insulating film, and a second conductive layer. The first insulating film that covers a side surface of the bit line has a portion perpendicular to a main surface of a semiconductor substrate in a region lower than a position lower than an uppermost portion of the first insulating film by a thickness, in a direction along the main surface of the semiconductor substrate, of the first insulating film that covers the side surface of the bit line at a lowermost portion of the bit line..
07/24/14
20140203412
new patent Through silicon vias for semiconductor devices and manufacturing method thereof
The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad.
07/24/14
20140203410
new patent Die edge sealing structures and related fabrication methods
Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region.
07/24/14
20140203392
new patent Semiconductor radiation detector
A semiconductor radiation detector having a semiconductor substrate and first and second metal layers. The semiconductor substrate has substantially planar upper and lower opposing surfaces which have respective first and second surface areas.
07/24/14
20140203391
new patent Integrated circuit including a directional light sensor
An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate having a major surface.
07/24/14
20140203390
new patent Solid-state imaging device and electronic apparatus
An solid-state imaging device includes a pixel region formed on a semiconductor substrate, an effective pixel region and a shielded optical black region in the pixel region, a multilayer wiring layer formed on a surface of the side opposite to a light incident side of the semiconductor substrate, a supporting substrate bonded to a surface of the multilayer wiring layer side, and an antireflection structure that is formed on the bonding surface side of the supporting substrate.. .
07/24/14
20140203389
new patent Solid-state photodetector pixel and photodetecting method
A pixel is formed in a semiconductor substrate (s) with a plane surface for use in a photodetector. It comprises an active region for converting incident light (in) into charge carriers, photogates (pgl, pgm, pgr) for generating a lateral electric potential (Φ(x)) across the active region, and an integration gate (ig) for storing charge carriers generated in the active region and a dump site (ddiff).
07/24/14
20140203388
new patent Optical sensor with integrated pinhole
An optical sensor includes a semiconductor substrate having a first conductive type. The optical sensor further includes a photodiode disposed on the semiconductor substrate and a metal layer.
07/24/14
20140203373
new patent Device and methods for high-k and metal gate stacks
A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate.
07/24/14
20140203371
new patent Finfet device formation
A method includes patterning a fin on a semiconductor substrate, depositing a local trench isolation (lti) layer on the semiconductor substrate, patterning a gate stack over a channel region of the fin and over a portion of the lti layer, depositing a first capping layer over exposed portions of the lti layer, performing an etching process to remove oxide material from exposed portions of the fin, and epitaxially growing a semiconductor material from exposed portions of the fin to define active regions.. .
07/24/14
20140203369
new patent Fin field-effect transistors and fabrication method thereof
A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate, and forming a plurality of fins with hard mask layers and an isolation structure.
07/24/14
20140203368
new patent Electrostatic discharge protection device
The invention provides an electrostatic discharge (esd) protection device. The esd protection device includes a semiconductor substrate having an active region.
07/24/14
20140203358
new patent Semiconductor device with enhanced 3d resurf
A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region..
07/24/14
20140203333
new patent Semiconductor device having modified profile metal gate
In one embodiment, a method includes providing a semiconductor substrate having a trench disposed thereon and forming a plurality of layers in the trench. The plurality of layers formed in the trench is etched thereby providing at least one etched layer having a top surface that lies below a top surface of the trench.
07/24/14
20140203332
new patent Self-aligned biosensors with enhanced sensitivity
Non-planar semiconductor fet based sensors are provided that have an enhanced sensing area to volume ratio which results in faster response times than existing planar fet based sensors. The fet based sensors of the present disclosure include a v-shaped gate dielectric portion located in a v-shaped opening formed in a semiconductor substrate.
07/24/14
20140203331
new patent Solid state imaging device and imaging apparatus
A solid-state imaging device has, in a semiconductor substrate, plural pds arranged two-dimensionally and signal reading circuits which are formed as mos transistors and read out signals corresponding to charges generated in the respective pds. Microlenses for focusing light beams are formed over the respective pds.
07/24/14
20140203324
new patent A strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof
The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof, belonging to a field of field effect transistor logic device and the circuit in cmos ultra large scale integrated circuit (ulsi). The tunneling field effect transistor includes a control gate, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, where the highly-doped source region and the highly-doped drain region lie on both sides of the control gate, respectively, the control gate has a strip-shaped structure with a gate length greater than a gate width, and at one side thereof is connected to the highly-doped drain region and at the other side thereof extends laterally into the highly-doped source region; a region located below the control gate is a channel region; and the gate width of the control gate is less than twice width of a source depletion layer.
07/24/14
20140202837
new patent Low-cost process-independent rf mems switch
A mems switch includes a semiconductor substrate, a movable cantilever and a cantilever anchor. The semiconductor substrate includes a device layer and a handle.
07/17/14
20140201593
Efficient memory architecture for low density parity check decoding
A low density parity check (ldpc) decoder integrated on a single semiconductor substrate may comprise one or more arrays of first-type memory cells and one or more arrays of second-type memory cells. The ldpc decoder may be configured to store intrinsic messages in the array of first-type cells and to store extrinsic messages in the array of second-type cells.
07/17/14
20140199858
Thermal processing by transmission of mid infra-red laser light through semiconductor substrate
Thermal processing is performed by transmission of mid infra-red laser light through a substrate such as a semiconductor substrate with a limited mid infra-red transmission range. The laser light is generated by a rare-earth-doped fiber laser and is directed through the substrate such that the transmitted power is capable of altering a target material at a back side region of the substrate, for example, on or spaced from the substrate.
07/17/14
20140199847
Semiconductor device manufacturing method
According to one embodiment, a semiconductor device manufacturing method includes depositing a silicon film above a semiconductor substrate, forming an insulating film which includes silicon oxide or silicon nitride on the silicon film, forming a physical guide having a depressed portion above the insulating film, forming a directed self-assembly material layer which includes a first polymer and a second polymer in the depressed portion of the physical guide, phase-separating the directed self-assembly material layer into a first region which includes the first polymer and a second region which includes the second polymer, removing the second region, processing the insulating film by using the physical guide and the first region as masks, and transferring a pattern corresponding to the second region to the insulating film. Further, the silicon film is processed by using the pattern transferred onto the insulating film as a mask..
07/17/14
20140199834
Hybrid conductor through-silicon-via for power distribution and signal transmission
A method of providing signal, power and ground through a through-silicon-via (tsv), and an integrated circuit chip having a tsv that simultaneously provides signal, power and ground. In one embodiment, the method comprises forming a tsv through a semiconductor substrate, including forming a via in the substrate; and forming a multitude of conductive bars in the via.
07/17/14
20140199817
Method for manufacturing multi-gate transistor device
A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.. .
07/17/14
20140199803
Solid state image pickup apparatus and method for manufacturing the same
When forming a hollow portion between each color filter, in order to realize the formation of the hollow portions with a narrower width, a plurality of light receiving portions are formed on the upper surface of a semiconductor substrate, a plurality of color filters corresponding to each of the light receiving portions are formed above the semiconductor substrate, a photoresist is formed on each color filter, side walls are formed on the side surfaces of the photoresist, and a hollow portion is formed between each color filter by performing etching using at least the side walls as a mask.. .
07/17/14
20140199802
Manufacturing method of solid-state imaging apparatus
To realize simplification of a process of forming hollow portions in a solid-state imaging apparatus, a plurality of light receiving portions is formed on a semiconductor substrate, and color filter layers as hollow portion forming layers are formed above the semiconductor substrate (fig. 1a).
07/17/14
20140199801
Manufacturing method of solid-state imaging apparatus
A color filter 5 is formed above a semiconductor substrate sb, in an area above a predetermined light receiving portion among a plurality of light receiving portions 1. A sacrificial layer 8 is formed on upper and side of the first color filter 5.
07/17/14
20140199798
Quantum cascade laser manufacturing method
A quantum cascade laser manufacturing method includes: a step of pressing a mother stamper against a resin film having flexibility to make a resin stamper 201 having a second groove pattern p2; a step of making a wafer with an active layer formed on a semiconductor substrate; a step of forming a resist film 304 on a surface on the active layer side of the wafer; a step of pressing the resin stamper against the resist film 304 by air pressure to form a third groove pattern p3 on the resist film 304; and a step of etching the wafer with the resist film 304 serving as a mask to form a diffraction grating on a surface of the wafer.. .
07/17/14
20140199785
Multizone control of lamps in a conical lamphead using pyrometers
A method and apparatus for processing a semiconductor substrate is described. The apparatus is a process chamber having an optically transparent upper dome and lower dome.
07/17/14
20140199597
Semiconductor structures having a micro-battery and methods for making the same
The present disclosure provides an embodiment of an integrated structure that includes a first electrode of a first conductive material embedded in a first semiconductor substrate; a second electrode of a second conductive material embedded in a second semiconductor substrate; and a electrolyte disposed between the first and second electrodes. The first and second semiconductor substrates are bonded together through bonding pads such that the first and second electrodes are enclosed between the first and second semiconductor substrates.
07/17/14
20140197889
Semiconductor device, method for manufacturing the same, power supply device, and high-frequency amplifier
A semiconductor device includes: a compound semiconductor stack structure including a plurality of compound semiconductor layers stacked over a semiconductor substrate; a first insulating film covering the surface of the compound semiconductor stack structure; and a conductive film provided on the surface of the first insulating film.. .
07/17/14
20140197538
Copper etching integration scheme
The present disclosure is directed to an interconnect structure. The metal interconnect structure has a metal body disposed over a semiconductor substrate and a projection extending from the metal body.
07/17/14
20140197522
Hybrid conductor through-silicon-via for power distribution and signal transmission
A method of providing signal, power and ground through a through-silicon-via (tsv), and an integrated circuit chip having a tsv that simultaneously provides signal, power and ground. In one embodiment, the method comprises forming a tsv through a semiconductor substrate, including forming a via in the substrate; and forming a multitude of conductive bars in the via.
07/17/14
20140197518
Stacked structure semiconductor device
A semiconductor device includes a capacitor formed in a semiconductor substrate of a first conductivity type. The capacitor includes: a heavily-doped layer of a second conductivity type placed over the substrate, a first insulating layer placed over the heavily-doped layer of the second conductivity type, and a first metal layer placed over the first insulating layer.
07/17/14
20140197514
Semiconductor device and method of manufacturing the same
A semiconductor device that is equipped with a semiconductor substrate, a composite metal film, and a detection terminal is provided. The composite metal film is formed on a surface or a back face of the semiconductor substrate, and has a first metal film, and a second metal film that is joined to the first metal film and is different in seebeck coefficient from the first metal film.
07/17/14
20140197513
Image sensor with improved dark current performance
Provided is a semiconductor image sensor device. The image sensor device includes a semiconductor substrate that includes an array region and a black level correction region.
07/17/14
20140197509
Photosensitive imaging devices and associated methods
Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction.
07/17/14
20140197498
Integrated circuits and methods for fabricating integrated circuits with improved silicide contacts
Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure.
07/17/14
20140197496
Semiconductor structure with suppressed sti dishing effect at resistor region
An integrated circuit includes a semiconductor substrate; a first shallow trench isolation (sti) feature of a first width and a second sti feature of a second width in a semiconductor substrate. The first width is less than the second width.
07/17/14
20140197494
Trench silicide and gate open with local interconnect with replacement gate process
A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel.
07/17/14
20140197482
Semiconductor device and method of forming the same
A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls.
07/17/14
20140197476
Semiconductor device
A semiconductor device includes element active portion x and element peripheral portion y. An interlayer insulating film is formed on upper surfaces of portions x and y.
07/17/14
20140197474
Semiconductor integrated circuit device and a method of manufacturing the same
Semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.. .
07/17/14
20140197460
Semiconductor device, method for manufacturing the same, power supply device, and high-frequency amplifier
A semiconductor device includes: a compound semiconductor stack structure including a plurality of compound semiconductor layers stacked over a semiconductor substrate; and a first insulating film covering the surface of the compound semiconductor stack structure, the first insulating film being a silicon nitride film including, on the top side, a first region containing nitrogen element in excess of the stoichiometric ratio.. .
07/17/14
20140197458
Finfet device and method of fabricating same
An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions..
07/17/14
20140197448
Bidirectional semiconductor device for protection against electrostatic discharges
An integrated circuit is produced on a bulk semiconductor substrate in a given cmos technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate thyristors coupled in parallel and head-to-tail.
07/17/14
20140197356
Cmp compositions and methods for suppressing polysilicon removal rates
The present invention provides a chemical-mechanical polishing (cmp) composition suitable for polishing a silicon nitride-containing substrate while suppressing polysilicon removal from the substrate. The composition comprises abrasive particles suspended in an acidic aqueous carrier containing a surfactant comprising an alkyne-diol, an alkyne diol ethoxylate, or a combination thereof.
07/17/14
20140196850
Method and system for wafer level singulation
A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices.
07/17/14
20140196777
Solar cell and method for manufacturing the same
A solar cell and a method for manufacturing the solar cell are discussed. An embodiment of the method includes forming an emitter region containing impurities of a second conductive type opposite a first conductive type at a back surface of a semiconductor substrate containing impurities of the first conductive type, forming a passivation layer paste containing impurities of the first conductive type on the emitter region, selectively performing a thermal process on a first partial area of the passivation layer paste to form a back surface field region containing impurities of the first conductive type at a partial area of the emitter region, forming a plurality of openings in partial areas of the passivation layer paste to form a passivation layer, forming a first electrode connected to the emitter region, and forming a second electrode connected to the back surface field region..
07/17/14
20140196303
Process for curing low-dielectric constant material
Provided is a low-dielectric constant material curing process including irradiating a low-dielectric constant material on a semiconductor substrate with ultraviolet rays. In the low-dielectric constant material curing process, the ultraviolet light source is a fluorescent lamp including: a light-emitting tube sealed and filled with a discharge gas containing xenon gas; a pair of electrodes for inducing a discharge in the interior space of the light-emitting tube; a dielectric material being interposed between the interior space and at least one of the pair of electrodes; and a phosphor layer formed on a surface of the light-emitting tube and containing a phosphor that is excited by light generated from the discharge gas by a discharge in the interior space.
07/10/14
20140193983
Apparatuses and methods for depositing sic/sicn films via cross-metathesis reactions with organometallic co-reactants
Disclosed herein are methods of forming sic/sicn film layers on surfaces of semiconductor substrates. The methods may include introducing a silicon-containing film-precursor and an organometallic ligand transfer reagent into a processing chamber, adsorbing the silicon-containing film-precursor, the organometallic ligand transfer reagent, or both onto a surface of a semiconductor substrate under conditions whereby either or both form an adsorption-limited layer, and reacting the silicon-containing film-precursor with the organometallic ligand transfer reagent, after either or both have formed the adsorption-limited layer.
07/10/14
20140193971
Semiconductor device and method of manufacturing the same
The semiconductor device includes: a semiconductor substrate; an insulating film provided on a surface of the semiconductor substrate; a porous metal film provided on the insulating film; a protective film provided on the porous metal film, and having an opening portion for defining a pad region; and a wire wire-bonded to the porous metal film in the pad region. The stress generated by the impact of wire-bonding is mostly absorbed in the porous metal film owing to the distortion of the porous metal film, preventing generation of cracks in the insulating film..
07/10/14
20140193956
Transistor and fabriation method
Fabrication methods for junctionless transistor and complementary junctionless transistor are provided. An isolation layer doped with a first-type ion is formed on a semiconductor substrate and an active layer doped with a second-type ion is formed on the isolation layer.
07/10/14
20140192595
Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate.
07/10/14
20140192533
Apparatus and method for speckle reduction in laser processing equipment
Embodiments described herein provide apparatus and methods for processing semiconductor substrates with uniform laser energy. A laser pulse or beam is directed to a spatial homogenizer, which may be a plurality of lenses arranged along a plane perpendicular to the optical path of the laser energy, an example being a microlens array.
07/10/14
20140192243
Image pickup device, method of manufacturing same, and electronic apparatus
An image pickup device with a plurality of pixels, each of the pixels includes: a photoelectric conversion section formed in a semiconductor substrate; and a metallic member formed between the semiconductor substrate and a wiring layer provided in a layer on the semiconductor substrate, a part of the metallic member being configured to serve as a light-shielding member that blocks a part of light to be incident on the photoelectric conversion section.. .
07/10/14
20140191421
Semiconductor device
A semiconductor device includes a semiconductor substrate, an interlayer insulation film, multiple wiring layers, a first hard film, and an electrical pad. The semiconductor substrate has a semiconductor element.
07/10/14
20140191412
Interconnection structures and fabrication method thereof
A method is provided for fabricating an interconnection structure. The method includes providing a semiconductor substrate having certain semiconductor devices inside, a dielectric layer covering the semiconductor devices, and vias inside the dielectric layer connecting with connection pads of the semiconductor devices.
07/10/14
20140191404
Local interconnect structure and fabrication method
Local interconnect structures and fabrication methods are provided. A dielectric layer can be formed on a semiconductor substrate.
07/10/14
20140191373
Composite wafer and method for manufacturing the same
A composite wafer 10 includes a supporting substrate 12 and a semiconductor substrate 14 which are bonded to each other by direct bonding. The supporting substrate 12 is a translucent alumina substrate with an alumina purity of 99% or more.
07/10/14
20140191349
Solid-state imaging apparatus and method of manufacturing the same
The present invention provides a solid-state imaging apparatus which has hollow portions provided around each of color filters and achieves the prevention of the peeling of each of the color filters. The solid-state imaging apparatus having a plurality of light receiving portions provided on a semiconductor substrate includes: a plurality of color filters arranged correspondingly to each of the plurality of light receiving portions; and hollow portions formed around each of the plurality of color filters, wherein each of the color filters has one peripheral part contacting with adjacent one or more of the color filters..
07/10/14
20140191347
Solid-state imaging device
According to one embodiment, a solid-state imaging device includes a semiconductor substrate including a pixel area and a peripheral circuit area, an interconnection structure provided on a first principal surface of the semiconductor substrate and including first interconnection layers electrically connected to the peripheral circuit area, a second interconnection layer provided in the peripheral circuit area and on a second principal surface of the semiconductor substrate, a third interconnection layer provided above the second interconnection layer with an insulating layer therebetween, and through electrodes electrically connecting the second interconnection layer to the third interconnection layer.. .
07/10/14
20140191343
Sound transducer and microphone using same
Provided is an acoustic transducer including: a semiconductor substrate; a vibrating membrane, provided above the semiconductor substrate, including a vibrating electrode; and a fixed membrane, provided above the semiconductor substrate, including a fixed electrode, the acoustic transducer detecting a sound wave according to changes in capacitances between the vibrating electrode and the fixed electrode, converting the sound wave into electrical signals, and outputting the electrical signals. At least one of the vibrating electrode and the fixed electrode is divided into a plurality of divided electrodes, and the plurality of divided electrodes outputting the electrical signals..
07/10/14
20140191339
Semiconductor structures and fabrication method thereof
A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate.
07/10/14
20140191316
Mos transistors and fabrication method thereof
A method is provided for fabricating an mos transistor. The method includes providing a semiconductor substrate, and forming a gate structure having a gate dielectric layer and a gate metal layer on the semiconductor substrate.
07/10/14
20140191315
Multigate metal oxide semiconductor devices and fabrication methods
A semiconductor device includes a first well and a second well implanted in a semiconductor substrate. The semiconductor device further includes a gate structure above the first and second wells between a raised source structure and a raised drain structure.
07/10/14
20140191314
Semiconductor device and fabrication method
Semiconductor devices and fabrication methods are provided. A fin can be formed on a semiconductor substrate, a gate can be formed across the fin, and sidewall spacers can be formed across the fin on both sides of the gate.
07/10/14
20140191310
Power semiconductor device
A power semiconductor device according to an embodiment includes an element portion in which mosfet elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film.
07/10/14
20140191304
Cmos transistors, fin field-effect transistors and fabrication methods thereof
A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and configuring a channel region along a first direction.
07/10/14
20140191303
Semiconductor devices including back-side integrated circuitry
Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors.
07/10/14
20140191301
Transistor and fabrication method
Transistors and fabrication methods are provided. A first sidewall can be formed on each sidewall of a gate structure.
07/10/14
20140191298
Semiconductor device and manufacturing method of the same
A semiconductor device includes a semiconductor substrate, a metal gate structure, at least an epitaxial layer, an interlayer dielectric, at least a contact hole, at least a metal silicide layer and a fluorine-containing layer. The semiconductor substrate has at least a gate region and at least a source/drain region adjoining the gate region.
07/10/14
20140191291
Method of manufacturing a non-volatile memory
The disclosure relates to a method of manufacturing vertical gate transistors in a semiconductor substrate, comprising implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors; forming, in the substrate, parallel trench isolations and second trenches perpendicular to the trench isolations, reaching the isolation layer, and isolated from the substrate by a first dielectric layer; depositing a first conductive layer on the surface of the substrate and in the second trenches; etching the first conductive layer to form the vertical gates of the transistors, and vertical gate connection pads between the extremity of the vertical gates and an edge of the substrate, while keeping a continuity zone in the first conductive layer between each connection pad and a vertical gate; and implanting doped regions on each side of the second trenches, to form drain regions of the transistors.. .
07/10/14
20140191288
Semiconductor device and method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes forming an electron transit layer on a semiconductor substrate, forming an electron supply layer on the electron transit layer, forming a cap layer on the electron supply layer, forming a protection layer on the cap layer, the protection layer having an opening part, through which a part of the cap layer is exposed, and forming an oxidation film on an exposed surface of the cap layer by a wet process.. .
07/10/14
20140191287
Compressive strained iii-v complementary metal oxide semiconductor (cmos) device
A semiconductor device including a first lattice dimension iii-v semiconductor layer present on a semiconductor substrate, and a second lattice dimension iii-v semiconductor layer that present on the first lattice dimension iii-v semiconductor layer, wherein the second lattice dimension iii-v semiconductor layer has a greater lattice dimension than the first lattice dimension iii-v semiconductor layer, and the second lattice dimension iii-v semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension iii-v semiconductor layer, wherein the channel portion of second lattice dimension iii-v semiconductor layer has the compressive strain.
07/10/14
20140191286
Compressive strained iii-v complementary metal oxide semiconductor (cmos) device
A semiconductor device including a first lattice dimension iii-v semiconductor layer present on a semiconductor substrate, and a second lattice dimension iii-v semiconductor layer that present on the first lattice dimension iii-v semiconductor layer, wherein the second lattice dimension iii-v semiconductor layer has a greater lattice dimension than the first lattice dimension iii-v semiconductor layer, and the second lattice dimension iii-v semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension iii-v semiconductor layer, wherein the channel portion of second lattice dimension iii-v semiconductor layer has the compressive strain.
07/10/14
20140191252
Complementary metal oxide semiconductor device, optical apparatus including the same, and method of manufacturing the same
A complementary metal oxide semiconductor (cmos) device includes an n-type first transistor on a silicon substrate, the n-type first transistor including a group iii-v compound semiconductor substrate, and a p-type second transistor on the silicon substrate, the p-type second transistor including a germanium based substrate.. .
07/10/14
20140191248
Semiconductor device
A semiconductor device includes: a semiconductor substrate that has an element region and a peripheral region that surrounds the element region; and a gate pad that is disposed in an area that is on a surface side of the semiconductor substrate. The element region is formed with an insulated gate semiconductor element that has a gate electrode.


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Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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