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Date/App# patent app List of recent Semiconductor Substrate-related patents
04/17/14
20140106576
 Inorganic polysilazane, silica film-forming coating liquid containing same, and method for forming silica film patent thumbnailInorganic polysilazane, silica film-forming coating liquid containing same, and method for forming silica film
Disclosed is an inorganic polysilazane that undergoes less shrinkage during a calcination step in an oxidizing agent such as water vapor and is less prone to allow a silica film to suffer from the formation of cracks or peel off from a semiconductor substrate, and a silica film-forming coating liquid containing the inorganic polysilazane, and also provides an inorganic polysilazane and a silica film-forming coating liquid containing the same. The value of a/(b+c) is 0.9-1.5 and the value of (a+b)/c is 4.2-50.
04/17/14
20140106574
 Gapfill of variable aspect ratio features with a composite peald and pecvd method patent thumbnailGapfill of variable aspect ratio features with a composite peald and pecvd method
Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features.
04/17/14
20140106568
 Method of forming opening on semiconductor substrate patent thumbnailMethod of forming opening on semiconductor substrate
The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided.
04/17/14
20140106555
 Method for forming a semiconductor device patent thumbnailMethod for forming a semiconductor device
A method for forming a semiconductor device. One embodiment provides a semiconductor substrate having a trench with a sidewall isolation.
04/17/14
20140106538
 Dummy pattern design for thermal annealing patent thumbnailDummy pattern design for thermal annealing
The present disclosure provides a semiconductor structure including a semiconductor substrate having a device region and a dummy region adjacent the device region; a plurality of active regions in the device region; and a plurality of dummy active regions in the dummy region, where each of the active regions has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, and the first dimension is substantially greater than the second dimension; and each of the dummy active regions has a third dimension in the first direction and a fourth dimension in the second direction, and the third dimension is substantially greater than the fourth dimension. The plurality of dummy active regions are configured such that thermal annealing effect in the dummy region is substantially equal to that of the device region..
04/17/14
20140106535
 Methods of manufacturing semiconductor devices patent thumbnailMethods of manufacturing semiconductor devices
A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.. .
04/17/14
20140106531
 Field effect transistor device having a hybrid metal gate stack patent thumbnailField effect transistor device having a hybrid metal gate stack
A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer.
04/17/14
20140106516
 Self-doped ohmic contacts for compound semiconductor devices patent thumbnailSelf-doped ohmic contacts for compound semiconductor devices
A compound semiconductor device is manufactured by forming an iii-nitride compound semiconductor device structure on a silicon-containing semiconductor substrate, the iii-nitride compound semiconductor device structure including a gan alloy on gan and a channel region arising near an interface between the gan alloy and the gan. One or more silicon-containing insulating layers are formed on a surface of the iii-nitride compound semiconductor device structure adjacent the gan alloy, and a contact opening is formed which extends through the one or more silicon-containing insulating layers to at least the gan alloy.
04/17/14
20140106481
 Method for wafer level reliability patent thumbnailMethod for wafer level reliability
A method for ensuring wafer level reliability is provided. The method involves: forming a gate oxide layer having a thickness of less than 50 Å on a semiconductor substrate; forming a pmos element having a channel length of less than 0.13 μm on the semiconductor substrate; and assessing hot carrier injection (hci) for the pmos element..
04/17/14
20140105582
 Minimal contact edge ring for rapid thermal processing patent thumbnailMinimal contact edge ring for rapid thermal processing
Embodiments of edge rings for substrate supports of semiconductor substrate process chambers are provided herein. In some embodiments, an edge ring for a semiconductor process chamber may include an annular body having a central opening, an inner edge, an outer edge, an upper surface, and a lower surface, an inner lip disposed proximate the inner edge and extending downward from the upper surface, and a plurality of protrusions extending upward from the inner lip and disposed along the inner edge of the annular body, wherein the plurality of protrusions are arranged to support a substrate above the inner lip and over the central opening, wherein the inner lip is configured to substantially prevent light radiation from travelling between a first volume disposed above the edge ring and a second volume disposed below the edge ring when a substrate is disposed on the plurality of protrusions..
04/17/14
20140104942
Recess gate transistors and devices including the same
A recess gate transistor includes: a drain region and a source region in a semiconductor substrate and doped with first-type impurities; a recess region recessed in the semiconductor substrate between the drain region and the source region; a gate insulation layer on the recess region, a gate electrode on the gate insulation layer filling the recess region; and a charge pocket region below the recess region and doped with second-type impurities. A semiconductor chip includes a plurality of recess gate transistors, and an image sensor includes a semiconductor chip including a plurality of recess gate transistors..
04/17/14
20140104466
Method of operating a cmos imager using color interpolation
An imager has first and second photosensitive sites and an interpolator located in a semiconductor substrate. The first photosensitive site is configured to receive light having a spectral component, and the second photosensitive site is configured to measure the level of the spectral component in light received by the second photosensitive site.
04/17/14
20140103547
Alignment key of semiconductor device and method of fabricating the same
An alignment key of a semiconductor device includes: a material layer formed at a scribe region of a semiconductor substrate, a first dummy hole and a second dummy hole passing through the material layers, a first channel insulation layer formed inside the first dummy hole, a second channel insulation layer formed inside the second dummy hole, a first capping layer formed on a side wall of an upper portion of the first dummy hole and an upper portion of the first channel insulation layer, and a second capping layer formed on a side wall of an upper portion of the second dummy hole and an upper portion of the channel insulation layer, having a height of a lower surface portion greater than that of a lower surface portion of the first capping layer.. .
04/17/14
20140103540
Cooling channels in 3dic stacks
An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through..
04/17/14
20140103532
Chip-level humidity protection
An electronic apparatus includes a semiconductor substrate, a device structure supported by the semiconductor substrate, and a guard ring surrounding the device structure. The guard ring includes a plurality of conductive structures spaced apart from one another, supported by the semiconductor substrate, and coupled to a voltage source to establish an operating voltage for the guard ring..
04/17/14
20140103528
Semiconductor device
A semiconductor device, that is approximately identical in package size to a semiconductor chip, such as a w-csp, is devised to secure a wider area for sealing such as laser marking. A semiconductor substrate has a plurality of via electrodes extending from the bottom of the semiconductor substrate to top electrodes, a bottom wire net formed at the bottom of the semiconductor substrate such that the bottom wire net is connected to the via electrodes, and an insulative film covering the bottom wire net.
04/17/14
20140103522
Semiconductor substrate, semiconductor device, and method of manfacturing semiconductor substrate
A semiconductor substrate having a base material and a connection portion provided on at least one surface of the base material. The connection portion includes: a non-conductive wall portion so as to surround a concave portion formed on the base material; an electrode portion disposed on a bottom surface of a concave portion; and a metal portion disposed in contact with the electrode portion..
04/17/14
20140103483
Semiconductor device
A semiconductor device comprises a semiconductor substrate; an element-forming region that includes semiconductor elements formed on the semiconductor substrate; a buried electrode plug formed so as to penetrate through the semiconductor substrate; and a trench-type electrode that is buried in a trench within the semiconductor substrate positioned between the element-forming region and the buried electrode plug.. .
04/17/14
20140103482
Semiconductor device having vertical channels and method of manufacturing the same
A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions.
04/17/14
20140103481
Semiconductor substrate, semiconductor device, solid-state imaging device, and method of manufacturing semiconductor sustrate
A semiconductor substrate according to the present invention includes: a substrate; an electrode array which is provided on the surface on one side in a thickness direction of the substrate and in which a plurality of electrodes is two-dimensionally arranged in a plan view; and a resin layer which is provided on the surface on one side and seals peripheries of the plurality of electrodes. The plurality of electrodes protrudes by greater than or equal to 5% of its own height on the resin layer and is capable of being accommodated in the resin layer by being compressed in the thickness direction..
04/17/14
20140103461
Mems devices and fabrication methods thereof
A method for fabricating a mems device includes providing a micro-electro-mechanical system (mems) substrate having a sacrificial layer on a first side, providing a carrier including a plurality of cavities, bonding the first side of the mems substrate on the carrier, forming a first bonding material layer on a second side of the mems substrate, applying a sacrificial layer removal process to the mems substrate, providing a semiconductor substrate including a second bonding material layer and bonding the semiconductor substrate on the second side of the mems substrate.. .
04/17/14
20140103457
Field effect transistor device having a hybrid metal gate stack
A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer.
04/17/14
20140103455
Fet devices with oxide spacers
Transistors including oxide spacers and methods of forming the same. Embodiments include planar fets including a gate on a semiconductor substrate, oxide spacers on the gate sidewalls, and source or drain regions at least partially in the substrate offset from the gate by the oxide spacers.
04/17/14
20140103452
Isolation components for transistors formed on fin features of semiconductor substrates
In an embodiment, an apparatus includes a substrate including a surface having a planar portion and a fin feature extending in a direction substantially perpendicular to the planar portion and having a thickness less than a thickness of the substrate. The apparatus also includes a first transistor that includes a first gate region formed over the fin feature, a first source region formed from a body of the fin feature, and a first drain region formed from the body of the fin feature.
04/17/14
20140103445
Semiconductor sram structures and fabrication methods
Various embodiments provide semiconductor structures and their fabrication methods. An sram memory cell can include at least one semiconductor structure, and an sram memory can include at least one sram memory cell.
04/17/14
20140103442
Semiconductor device, method of forming semiconductor device, and data processing system
A semiconductor device includes a semiconductor substrate including a fin. The fin includes first and second fin portions.
04/17/14
20140103438
Multi-gate semiconductor devices and methods of forming the same
A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type.
04/17/14
20140103433
High-voltage metal-dielectric-semiconductor device and method of the same
A high-voltage metal-dielectric-semiconductor transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate surrounding an active area; a gate overlying the active area; a drain doping region of a first conductivity type in the active area; a source doping region of the first conductivity type in a first well of a second conductivity type in the active area; and a source lightly doped region of the first conductivity type between the gate and the source doping region; wherein no isolation is formed between the gate and the drain doping region.. .
04/17/14
20140103430
Lateral high-voltage transistor and method for manufacturing the same
A lateral high-voltage transistor includes: a semiconductor substrate; a semiconductor layer being provided on one main surface of the semiconductor substrate; a source region being provided selectively in a surface of the semiconductor layer; a drain region being provided selectively in the surface of the semiconductor layer; a gate electrode provided on a part of the semiconductor layer between the source region and the drain region with interposition of the gate insulating film; and a drift region being provided selectively in the surface of the semiconductor layer. The drift region includes a stripe-shaped diffusion layer extending in parallel with a direction from the drain region toward the source region.
04/17/14
20140103429
Method and structure to boost mosfet performance and nbti
The present disclosure provides one embodiment of a method forming a p-type field effect transistor (pfet) structure. The method includes forming a mask layer on a semiconductor substrate, the mask layer including an opening that exposes a semiconductor region of the semiconductor substrate within the opening; forming a n-type well (n-well) in the semiconductor region by performing an ion implantation of a n-type dopant to the semiconductor substrate through the opening of the mask layer; and performing a germanium (ge) channel implantation to the semiconductor substrate through the opening of the mask layer, forming a ge channel implantation region in the n-well..
04/17/14
20140103419
Non-volatile memory device and method for forming the same
A method for forming a non-volatile memory device includes: (a) forming an isolation structure on a circuit-forming surface of a semiconductor substrate to define an array of cell forming regions; (b) forming a gate structure array including a plurality of gate structures disposed above the cell forming regions and each having a first side and a second side; (c) performing ion implantation to form drain regions and a common source region; and (d) forming drain contacts to the drain regions, and a common source contact to the common source region.. .
04/17/14
20140103400
Solid-state imaging device
A solid-state imaging device includes: a first electrode formed above a semiconductor substrate; a photoelectric conversion film formed on the first electrode and for converting light into signal charges; a second electrode formed on the photoelectric conversion film; a charge accumulation region electrically connected to the first electrode and for accumulating the signal charges converted from the light by the photoelectric conversion film; a reset gate electrode for resetting the charge accumulation region; an amplification transistor for amplifying the signal charges accumulated in the charge accumulation region; and a contact plug in direct contact with the charge accumulation region, comprising a semiconductor material, and for electrically connecting to each other the first electrode and the charge accumulation region.. .
04/17/14
20140103392
Semiconductor device
A semiconductor device comprises a vertical mos transistor including a semiconductor substrate having a silicon pillar, a gate electrode formed along a sidewall of the silicon pillar, a gate insulating film formed between the gate electrode and the silicon pillar, an upper diffusion layer formed on the top of the silicon pillar, and a lower diffusion layer formed lower than the upper diffusion layer in the semiconductor substrate; and a pad electrically connected to the lower diffusion layer. Breakdown occurs between the lower diffusion layer and the semiconductor substrate when a surge voltage is applied..
04/17/14
20140103391
Nitride light-emitting diode element and method of manufacturing same
A nitride led having improved light extraction efficiency and/or axial luminous intensity is provided. The nitride led contains a nitride semiconductor substrate having, on a front face thereof, a light-emitting structure made of a nitride semiconductor, wherein a roughened region is provided on a back face of the substrate, the roughened region has a plurality of protrusions, each of the plurality of protrusions has a top point or top plane and has a horizontal cross-section which is circular, except in areas where the protrusion is tangent to other neighboring protrusions, and which has a surface area that decreases on approaching the top point or top plane, the plurality of protrusions are arranged such that any one protrusion is in contact with six other protrusions, and light generated in the light-emitting structure is output to the exterior through the roughened region..
04/17/14
20140103294
Techniques and configurations to impart strain to integrated circuit devices
Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a quantum well channel coupled with the semiconductor substrate, a source structure coupled with the quantum well channel, a drain structure coupled with the quantum well channel and a strain-inducing film disposed on and in direct contact with material of the source structure and the drain structure to reduce resistance of the quantum well channel by imparting a tensile or compressive strain on the quantum well channel, wherein the quantum well channel is disposed between the strain-inducing film and the semiconductor substrate.
04/17/14
20140103250
Composition and method for polishing aluminum semiconductor substrates
The invention provides a chemical-mechanical polishing composition comprising coated α-alumina particles, an organic carboxylic acid, and water. The invention also provides a chemical-mechanical polishing composition comprising an abrasive having a negative zeta potential in the polishing composition, an organic carboxylic acid, at least one alkyls disulfonate surfactant, and water, wherein the polishing composition does not further comprise a heterocyclic compound.
04/17/14
20140102528
Photovoltaic device
A photovoltaic device is provided having a semiconductor substrate, an i-type amorphous layer formed over a front surface of the semiconductor substrate, a p-type amorphous layer formed over the i-type amorphous layer, an i-type amorphous layer formed over aback surface of the semiconductor substrate, and an n-type amorphous layer formed over the i-type amorphous layer. The i-type amorphous layer and the i-type amorphous layer have oxygen concentration profiles in which concentrations are reduced in a step-shape from regions near interfaces with the semiconductor substrate and along a thickness direction, and an oxygen concentration in the step-shape portion of the i-type amorphous layer is higher than an oxygen concentration in the step-shape portion of the i-type amorphous layer..
04/17/14
20140102527
Photovoltaic device
A photovoltaic device may be provided having a semiconductor substrate, an i-type amorphous layer or an i-type amorphous layer formed over a front surface or a back surface of the semiconductor substrate, and a p-type amorphous layer or an n-type amorphous layer formed over the i-type amorphous layer or the i-type amorphous layer. The i-type amorphous layer or the i-type amorphous layer has an oxygen concentration profile in which a concentration is reduced in a step-shape from a region near an interface with the semiconductor substrate and along a thickness direction..
04/17/14
20140102172
Integrated circuit comprising a thermal conductivity based gas sensor
An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate.
04/17/14
20140102010
Polishing pad for eddy current end-point detection
Polishing pads for polishing semiconductor substrates using eddy current end-point detection are described. Methods of fabricating polishing pads for polishing semiconductor substrates using eddy current end-point detection are also described..
04/10/14
20140099798
Uv-curing apparatus provided with wavelength-tuned excimer lamp and method of processing semiconductor substrate using same
A uv irradiation apparatus for processing a semiconductor substrate includes: a uv lamp unit having at least one dielectric barrier discharge excimer lamp which is constituted by a luminous tube containing a rare gas wherein an inner surface of the luminous tube is coated with a fluorescent substance having a peak emission spectrum in a wavelength range of 190 nm to 350 nm; and a reaction chamber disposed under the uv lamp unit and connected thereto via a transmission window.. .
04/10/14
20140099786
Methods of forming through substrate interconnects
A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate.
04/10/14
20140099775
Method for fabricating semiconductor device with mini sonos cell
A method for fabricating a semiconductor device with mini-sonos cell is disclosed. The method includes: providing a semiconductor substrate having a first mos region and a second mos region; forming a first trench in the semiconductor substrate between the first mos region and the second mos region; depositing a oxide liner and a nitride liner in the first trench; forming a sti in the first trench; removing a portion of the nitride liner for forming a second trench between the first mos region of the semiconductor substrate and the sti and a third trench between the sti and the second mos region of the semiconductor substrate; and forming a first conductive type nitride layer in the second trench..
04/10/14
20140099767
Manufacturing method of semiconductor device
An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film.
04/10/14
20140099763
Forming silicon-carbon embedded source/drain junctions with high substitutional carbon level
Embodiment of the present invention provides a method of forming a semiconductor device. The method includes providing a semiconductor substrate; epitaxially growing a silicon-carbon layer on top of the semiconductor substrate; amorphizing the silicon-carbon layer; covering the amorphized silicon-carbon layer with a stress liner; and subjecting the amorphized silicon-carbon layer to a solid phase epitaxy (spe) process to form a highly substitutional silicon-carbon film.
04/10/14
20140099758
Sram devices utilizing strained-channel transistors and methods of manufacture
A novel sram memory cell structure and method of making the same are provided. The sram memory cell structure comprises strained pmos transistors formed in a semiconductor substrate.
04/10/14
20140097866
Method of evaluating metal contamination in semiconductor sample and method of manufacturing semiconductor substrate
An aspect of the present invention relates to a method of evaluating metal contamination in a semiconductor sample by dlts method, which includes obtaining a first dlts spectrum by measuring a dlts signal while varying a temperature, the dlts signal being generated by alternatively and cyclically applying to a semiconductor junction on a semiconductor sample a reverse voltage vr to form a depletion layer and a weak voltage v1 to trap carriers in the depletion layer; obtaining a second dlts spectrum by measuring a dlts signal while varying a temperature, the dlts signal is being generated by cyclically applying the vr to the semiconductor junction; obtaining a differential spectrum of the first dlts spectrum with a correction-use spectrum in the form of the second dlts spectrum or a spectrum that is obtained by approximating the second dlts spectrum as a straight line or as a curve.. .
04/10/14
20140097861
Semiconductor device and test method
A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion.. .
04/10/14
20140097832
Integrated automatic compass for vehicle
An integrated automotive compass suitable for use in a vehicle includes an application specific integrated circuit that includes at least first and second magnetoresponsive sensing elements. The first and second magnetoresponsive sensing elements and at least a portion of associated circuitry are established on a common semiconductor substrate using cmos technology.
04/10/14
20140097522
Methods and apparatus for identifying and reducing semiconductor failures
The present disclosure provides multi-junction solar cell structures and fabrication methods thereof that improve electrical testing capability and reduce chip failure rates. In the present invention a special masking pattern is used in the layout such that all or some of the epitaxial layers are etched away in the corner areas of each solar cell.
04/10/14
20140097519
Semiconductor device and method for fabricating the same
A method for fabricating a semiconductor device includes forming a first semiconductor wafer, in which a circuit part and a first bonding layer are stacked, on a first semiconductor substrate, forming a second semiconductor wafer, which includes structures and an insulating layer for gap-filling between the structures, on a second semiconductor substrate, the structures including a pillar and bit lines stacked therein, bonding the first semiconductor wafer with the second semiconductor wafer so that the first bonding layer faces the insulating layer, and separating the second semiconductor substrate from the bonded second semiconductor wafer.. .
04/10/14
20140097517
Semiconductor device having localized charge balance structure and method
In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein.
04/10/14
20140097496
Guard rings on fin structures
A device includes a semiconductor substrate, isolation regions extending into the semiconductor substrate, a plurality of semiconductor fins higher than top surfaces of the isolation regions, and a plurality of gate stacks. Each of the gate stacks includes a gate dielectric on a top surface and sidewalls of one of the plurality of semiconductor fin, and a gate electrode over the gate dielectric.
04/10/14
20140097492
Semiconductor structure
A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a dielectric layer, a dielectric structure and an electrode structure.
04/10/14
20140097490
Semiconductor device
A semiconductor substrate of a semiconductor device includes a body region of a first conductivity type, a drift region of a second conductivity type coming into contact with a lower surface of the body region, a gate electrode that is provided in a gate trench passing through the body region and extending to the drift region and faces the body region, and a gate insulator that is provided between the gate electrode and a wall surface of the gate trench. An inverted u-shaped section is formed in a lower surface of the gate insulator, and a floating region of the first conductivity type is formed in the inverted u-shaped section.
04/10/14
20140097477
Magnetic random access memory and a method of fabricating the same
An aspect of the present embodiment, there is provided magnetic random access memory device including a semiconductor substrate, a selection transistor on the semiconductor substrate, the selection transistor including a diffusion layer, a contact plug on diffusion layer, an amorphous film on the contact plug, a lower electrode provided on the amorphous film, a first magnetic layer, a nonmagnetic layer, a second magnetic layer, an upper electrode stacked in an order and a sidewall contact film on the contact plug, the sidewall contact film being in contact with a sidewall of the upper electrode.. .
04/10/14
20140097465
Silicon controlled rectifier (scr) device for bulk finfet technology
Some aspects relate to a semiconductor device disposed on a semiconductor substrate. The device includes an sti region that laterally surrounds a base portion of a semiconductor fin.
04/10/14
20140097451
Proximity sensor and circuit layout method thereof
A proximity sensor and a circuit layout method thereof are disclosed. The proximity sensor includes a light sensor and a light emitting unit.
04/10/14
20140097448
Semiconductor device and method of manufacturing the same
A semiconductor device includes a drift layer including a trench formed on a semiconductor substrate. A well in the drift layer overlaps an edge of the trench, and at least one gate electrode is formed at this overlapping edge region.
04/10/14
20140096909
Heating plate with planar heater zones for semiconductor processing
A heating plate of a semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a first layer with an array of heater zones operable to tune a spatial temperature profile on the semiconductor substrate, and a second layer with one or more primary heaters to provide mean temperature control of the semiconductor substrate. The heating plate can be incorporated in a substrate support wherein a switching device independently supplies power to each one of the heater zones to provide time-averaged power to each of the heater zones by time divisional multiplexing of the switches..
04/10/14
20140096821
Solar cell and method for making thereof
A solar cell includes a doped layer disposed on a first surface of a semiconductor substrate, a doped polysilicon layer disposed in a first region of a second surface of the semiconductor substrate, a doped area disposed in a second region of the second surface, and an insulating layer covering the doped polysilicon layer and the doped area. The insulating layer has openings exposing portions of the doped polysilicon layer and the doped layer, and the doped polysilicon layer and doped layer are respectively connected to a first electrode and a second electrode through the openings.
04/10/14
20140096606
Detector of gravitational waves and method of detecting gravitational waves
A semiconductor detector of gravitational waves of a first frequency may include an oscillator having a metal coated oscillating member over a metal coated semiconductor substrate to be subjected to a casimir attraction force towards the semiconductor substrate. The oscillator may be configured to exert a force to counterbalance the casimir attraction force causing the oscillating member oscillates with a main harmonic resonance frequency equal to the first frequency.
04/03/14
20140096101
Semiconductor device and designing method of semiconductor device
A semiconductor device has: a first signal line formed in a first wiring layer formed on a semiconductor substrate, and disposed in a first direction; first and second shield lines formed in the first wiring layer, disposed on both sides of the first signal line in the first direction, and given a first fixed potential; and a plurality of third shield lines formed in a second wiring layer formed on the semiconductor substrate, disposed with a first wiring width and at a first wiring interval in a second direction almost orthogonal to the first direction in a manner to partially overlap with each of the first signal line and the first and second shield lines, and given the first fixed potential.. .
04/03/14
20140094014
Contact structures for semiconductor transistors
Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ild) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ild layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ild layer on top of the first ild layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region..
04/03/14
20140094008
Cmos devices with schottky source and drain regions
A semiconductor structure includes a semiconductor substrate, and an nmos device at a surface of the semiconductor substrate, wherein the nmos device comprises a schottky source/drain extension region. The semiconductor structure further includes a pmos device at the surface of the semiconductor substrate, wherein the pmos device comprises a source/drain extension region comprising only non-metal materials.
04/03/14
20140092680
Multiple well bias memory
A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a sense amplifier configured to sense and amplify data from the memory cell. The first and second wells have different doping concentrations and are biased to first and second voltages, respectively.
04/03/14
20140091477
System and method for chemical-mechanical planarization of a metal layer
A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a semiconductor substrate, depositing a porogen-containing low-k layer over the low-k inter-metal layer, and etching a space for the via through the low-k inter-metal layer and the porogen-containing low-k layer.
04/03/14
20140091464
Semiconductor device
The semiconductor device of the present invention includes a semiconductor substrate provided with semiconductor elements, a lower layer wiring pattern which includes first wiring and second wiring, the first wiring and the second wiring disposed separately so as to be flush with each other, and the first wiring and the second wiring being fixed at a mutually different potential, an uppermost interlayer film disposed on the lower layer wiring pattern, a titanium nitride layer disposed on the uppermost interlayer film so as to cover the first wiring and the second wiring, and the titanium nitride having the thickness of 800 Å or more, and a pad metal disposed on the titanium nitride layer.. .
04/03/14
20140091459
Chip-size, double side connection package and method for manufacturing the same
A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an lsi chip.
04/03/14
20140091430
Semiconductor device including operative capacitors and dummy capacitors
The semiconductor device according to the present invention comprises a plurality of actually operative capacitors formed, arranged in an actually operative capacitor part over a semiconductor substrate and each including a lower electrode, a ferroelectric film and an upper electrode; a plurality of dummy capacitors formed, arranged in a dummy capacitor part provided outside of the actually operative capacitor part over the semiconductor substrate and each including the lower electrode, the ferroelectric film and the upper electrode; a plurality of interconnections respectively formed on said plurality of the actually operative capacitors and respectively connected to the upper electrodes of said plurality of the actually operative capacitors; and the interconnections respectively formed on said plurality of the dummy capacitors.. .
04/03/14
20140091423
Infrared photosensor
A thermal diode for a photosensor of a thermal imaging camera includes a semiconductor substrate having a surface and two doped structures set apart from each other on the surface. Furthermore, a device is provided for influencing a current between the first and the second structure, in order to reduce a current density in an area near to the surface and to increase it in an area far from the surface.
04/03/14
20140091421
Solid-state image pickup element and solid-state image pickup element mounting structure
A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a principal face of the semiconductor substrate, a plurality of second electrode pads arrayed in a direction along a direction in which the plurality of first electrode pads are arrayed, on the principal face of the semiconductor substrate, and a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence. The plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line perpendicular to the array directions of the plurality of first and second electrode pads..
04/03/14
20140091416
Photoelectric conversion apparatus and manufacturing method for a photoelectric conversion apparatus
A photoelectric conversion apparatus has multiple photoelectric converting units disposed in a semiconductor substrate, and isolation portions disposed in the semiconductor substrate. Each photoelectric converting unit includes a second semiconductor region, a third semiconductor region, disposed below the second semiconductor region and a fourth semiconductor region disposed below the third semiconductor region.
04/03/14
20140091415
Solid-state imaging apparatus, manufacturing method for the same, and electronic apparatus
A solid-state imaging apparatus includes a semiconductor substrate, an upper layer film, and on-chip lenses. On the semiconductor substrate, a plurality of pixels are formed.
04/03/14
20140091395
Transistor
A method for fabricating a transistor device including the following processes. First, a semiconductor substrate having a first transistor region is provided.
04/03/14
20140091388
Semiconductor device and method of fabricating the same
Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer..
04/03/14
20140091380
Split gate flash cell
In one aspect, a disclosed method of fabricating a split gate memory device includes forming a gate dielectric layer overlying an channel region of a semiconductor substrate and forming an electrically conductive select gate overlying the gate dielectric layer. The method further includes forming a counter doping region in an upper region of the substrate.
04/03/14
20140091377
Implant isolated devices and method for forming the same
A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the implant isolation region.
04/03/14
20140091375
Implant isolated devices and method for forming the same
A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate and extends over the implant isolation region.
04/03/14
20140091368
Solid-state imaging device
A solid-state imaging device including: a semiconductor substrate of a first conductivity type, having a fixed electric potential; a dark-current drain region of a second conductivity type, formed on a portion of the semiconductor substrate; a connection region of the first conductivity type, formed on another portion of the semiconductor substrate where the dark-current drain region is not formed; a well region of the first conductivity type, covering the dark-current drain region and the connection region; and a first region and a second region, formed within the well region and constituting a part of a read transistor that reads signal charge generated by photoelectric conversion. The well region is maintained at a fixed electric potential by being connected to the semiconductor substrate via the connection region..
04/03/14
20140091362
Integrated circuit transistor structure with high germanium concentration sige stressor
An integrated circuit transistor structure includes a semiconductor substrate, a first sige layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first sige layer has a ge concentration of 50 percent or more..
04/03/14
20140091359
Semiconductor device
A semiconductor device includes a semiconductor substrate having one main surface in which an anode of a diode is formed. At a distance from the outer periphery of the anode, a guard ring is formed to surround the anode.


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Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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