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Semiconductor Substrate patents



      
           
This page is updated frequently with new Semiconductor Substrate-related patent applications. Subscribe to the Semiconductor Substrate RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Substrate RSS RSS


Singulation apparatus and method

Singulation apparatus and method

Solar cell

Solar cell

Solar cell

Capacitance type sensor and method of manufacturing the same

Date/App# patent app List of recent Semiconductor Substrate-related patents
12/18/14
20140370713
 Method of forming fine patterns of a semiconductor device patent thumbnailnew patent Method of forming fine patterns of a semiconductor device
A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region, where the widths of the narrow-width patterns are smaller than the resolution limitations in a photolithography process used to make the semiconductor device. The first and second regions may comprise cell array regions, with memory cells in the first region and peripheral circuits for operating the memory cells in the second region.
12/18/14
20140370711
 Nitrogen doped amorphous carbon hardmask patent thumbnailnew patent Nitrogen doped amorphous carbon hardmask
Embodiments described herein generally relate to the fabrication of integrated circuits and more particularly to nitrogen doped amorphous carbon layers and processes for depositing nitrogen doped amorphous carbon layers on a semiconductor substrate. In one embodiment, a method of forming a nitrogen doped amorphous carbon layer on a substrate is provided.
12/18/14
20140370674
 Semiconductor device and manufacturing method thereof patent thumbnailnew patent Semiconductor device and manufacturing method thereof
A vertical super junction mosfet and a lateral mosfet are integrated on the same semiconductor substrate. The lateral mosfet is electrically isolated from the vertical super junction mosfet by an n-buried isolating layer and an n-diffused isolating layer.
12/18/14
20140370671
 Reliable electrical fuse with localized programming and method of making the same patent thumbnailnew patent Reliable electrical fuse with localized programming and method of making the same
An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact.
12/18/14
20140370659
 Singulation apparatus and method patent thumbnailnew patent Singulation apparatus and method
A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon.
12/18/14
20140370645
 Method of manufacturing semiconductor device patent thumbnailnew patent Method of manufacturing semiconductor device
An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, in an n-type semiconductor substrate, a p-type well as a p-type semiconductor region forming a part of a photodiode is formed and a gate electrode of a transfer transistor is formed.
12/18/14
20140370644
 Method of manufacturing solar cell patent thumbnailnew patent Method of manufacturing solar cell
A method of manufacturing a solar cell including a crystalline semiconductor substrate, includes: etching or washing at least part of a first principal surface of the substrate by treatment with an aqueous alkaline solution; and depositing a p-type semiconductor layer containing boron on at least part of a second principal surface of the substrate before the treatment with the aqueous alkaline solution.. .
12/18/14
20140370642
 Process of forming a back side illumination image sensor patent thumbnailnew patent Process of forming a back side illumination image sensor
A process of forming a back side illumination (bsi) image sensor is disclosed. An n-type implant is formed in a semiconductor substrate, and a p-type implant region, surrounding n-type in each pixel, is formed in the n-type implant such that in cross sectional view an n-type implant region is sandwiched between the two p-type implant regions.
12/18/14
20140370445
 Method for manufacturing semiconductor device patent thumbnailnew patent Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes a photolithography process having steps of a developing solution immersing process. The steps of the developing solution immersing process includes step (a) of dropping a developing solution on a silicon carbide semiconductor substrate and forming a developing solution film so as to have a film thickness of more than 6 μm and step (b) of reducing the film thickness of the developing solution film to 6 μm or less..
12/18/14
20140369121
 Semiconductor device patent thumbnailnew patent Semiconductor device
Disclosed is a semiconductor device, including: an active region defined in a shape extended in at least four different directions in a semiconductor substrate; and gates of first to fourth transistors formed on extended portions of the active region, respectively, in which the first to fourth transistors share one junction area.. .
12/18/14
20140367864
new patent Semiconductor device and method for producing same
A method for producing a semiconductor device includes: a process for forming a first conductor on a first interlayer insulating film provided on a semiconductor substrate, a process for forming in order a first stopper interlayer film, a second interlayer insulating film, a second stopper interlayer film, and a third interlayer insulating film on the first interlayer insulating film to cover the first conductor, a process for penetrating the third interlayer insulating film, the second stopper interlayer film, and the second interlayer insulating film, and forming a first contact hole having a first inner diameter on a position corresponding to the first conductor, a process for expanding the inner diameter of the first contact hole on the second interlayer insulating film to a second inner diameter larger than the first inner diameter, and a process for forming on the first stopper interlayer film a second contact hole.. .
12/18/14
20140367837
new patent Semiconductor substrate and method for making the same
The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps.
12/18/14
20140367836
new patent Semiconductor apparatus and substrate
A semiconductor apparatus includes a semiconductor substrate having a main surface, a multilayer structure circuit formed over the main surface of the semiconductor substrate, a protective wall formed in the same layer as an uppermost layer of the multilayer structure circuit so as to surround the multilayer structure circuit in plan view, and an alignment mark formed in the same layer as the uppermost layer. The alignment mark is formed so as to contact at least part of the protective wall..
12/18/14
20140367831
new patent Variable capacitance devices
A variable capacitance device includes a capacitor having a first capacitance and a variable resistor coupled in series with the capacitor. The variable resistor includes a gate structure formed over a channel region defined in a doped well formed in a semiconductor substrate.
12/18/14
20140367823
new patent Image sensors employing sensitized semiconductor diodes
In various example embodiments, the inventive subject matter is an image sensor and methods of formation of image sensors. In an embodiment, the image sensor comprises a semiconductor substrate and a plurality of pixel regions.
12/18/14
20140367817
new patent Solid-state imaging apparatus and method for manufacturing the same
The present invention reduces color mixture (cross talk) and the degradation of sensitivity in a peripheral region of a pixel area to achieve a reduction of sensitivity irregularity in the pixel area. A solid-state imaging apparatus having a pixel area including a plurality of photoelectric conversion elements includes: a semiconductor substrate in which the plurality of photoelectric conversion elements are formed; a plurality of air gap formed layers which are arranged above the semiconductor substrate, and correspond to the photoelectric conversion elements in the plurality of photoelectric conversion elements, respectively; and air gaps arranged between the air gap formed layers in the plurality of air gap formed layers, respectively, wherein the air gap in a peripheral region b of the pixel area has a width larger than the air gap in a central region a of the pixel area..
12/18/14
20140367811
new patent Capacitance type sensor and method of manufacturing the same
A capacitance type sensor has a semiconductor substrate having a vertically opened penetration hole, a movable electrode film arranged above the penetration hole such that a periphery portion opposes to a top surface of the semiconductor substrate with a gap provided, and a fixed electrode film arranged above the movable electrode film with a gap with respect to the movable electrode film. A concave portion having at least a part thereof formed by an inclined surface is provided in the top surface of the semiconductor substrate in a region of the top surface of the semiconductor substrate which overlaps the periphery portion of the movable electrode film..
12/18/14
20140367802
new patent Self-aligned insulated film for high-k metal gate device
An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ild) on either side of the metal gate structure.. .
12/18/14
20140367801
new patent Mechanism for forming metal gate structure
Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate with a metal gate stack formed on the semiconductor substrate, and the metal gate stack includes a metal gate electrode.
12/18/14
20140367778
new patent Lateral diffusion metal oxide semiconductor (ldmos)
A lateral diffusion metal oxide semiconductor (ldmos) comprises a semiconductor substrate having an sti structure in a top surface of the substrate, a drift region below the sti structure, and a source region and a drain region on opposite sides of the sti structure. A gate conductor is on the substrate over a gap between the sti structure and the source region and partially overlaps the drift region.
12/18/14
20140367777
new patent Double-side process silicon mos and passive devices for rf front-end modules
A method for forming integrated circuit includes providing a first semiconductor substrate having a front surface and a back surface that is opposite to the front surface. One or more first trenches are in the first semiconductor substrate from the front surface side, the first trenches being characterized by a first depth.
12/18/14
20140367775
new patent Semiconductor device and method for forming the same
A semiconductor device and a method for forming the same can block a moving path of electrons between neighbor buried gates. A semiconductor device includes a device isolation film formed to define an active region over a semiconductor substrate.
12/18/14
20140367774
new patent Semiconductor devices having partially oxidized gate electrodes
Semiconductor devices are provided including a first trench in a semiconductor substrate; a first insulating film in the first trench; a first conductive film on the first insulating film, the first conductive film having upper and lower portions and filling at least a portion of the first trench; and a first work function adjustment film having first and second portions, a first lower work function adjustment film portion and a first upper work function adjustment portion. The first lower work function adjustment film portion overlaps the lower portion of the first conductive film and the first upper work function adjustment film portion overlaps the upper portion of the first conductive film between the first insulating film and the first conductive film..
12/18/14
20140367773
new patent Method of manufacturing a semiconductor device with self-aligned contact plugs and semiconductor device
Semiconductor oxide pillars are selectively grown on semiconductor mesas between precursor structures that extend from a main surface into a semiconductor substrate. Spaces between the semiconductor oxide pillars are filled with one or more auxiliary materials to form alignment plugs in a vertical projection of the precursor structures.
12/18/14
20140367767
new patent Semiconductor device and manufacturing method thereof
A semiconductor device according to the present embodiment includes a semiconductor substrate. An insulating film is provided on the semiconductor substrate.
12/18/14
20140367766
new patent Nonvolatile semiconductor storage device and method of manufacture thereof
A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked.
12/18/14
20140367756
new patent Capacitor of nonvolatile memory device
The capacitor of a nonvolatile memory device includes first and second electrodes formed in the capacitor region of a semiconductor substrate to respectively have consecutive concave and convex shape of side surfaces formed along each other and a dielectric layer formed between the first and the second electrodes.. .
12/18/14
20140367753
new patent Cmos device with double-sided terminals and method of making the same
A transistor device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate structure disposed on the first surface and configured to form a channel region, and source and drain regions disposed on opposite sides of the channel region. The device also includes a source terminal and a drain terminal disposed on the second surface.
12/18/14
20140367738
new patent Semiconductor device
A p-type thin-layer along a side wall surface of a v-shaped groove reaching the bottom portion of a p-type isolation layer from the back surface of an n− semiconductor substrate, couples a p-type collector layer with the p-type isolation layer. A collector electrode contacts the surfaces of the p-type collector layer and the p-type thin-layer.
12/18/14
20140367735
new patent Iii nitride semiconductor substrate, epitaxial substrate, and semiconductor device
In a semiconductor device 100, it is possible to prevent c from piling up at a boundary face between an epitaxial layer 22 and a group iii nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of s and 2 at % to 20 at % of oxide in terms of o in a surface layer 12 with a front surface 10a having a specific plane orientation. Accordingly, a high-resistivity layer is prevented from being formed at the boundary face between the epitaxial layer 22 and the group iii nitride semiconductor substrate 10.
12/18/14
20140367691
new patent Semiconductor substrate, thin film transistor, semiconductor circuit, liquid crystal display apparatus, electroluminescent apparatus, semiconductor substrate manufacturing method, and semiconductor substrate manufacturing apparatus
According to a semiconductor substrate (40), a space (a) between a plurality of si thin film (16), which are provide apart from one another on the insulating substrate (30), is (i) larger than a difference between elongation of part of the insulating substrate which part corresponds to the space (a) and elongation of each of si wafers (10) when a change is made from room temperature to 600° c. And (ii) smaller than 5 mm.
12/18/14
20140367685
new patent Semiconductor substrate and semiconductor chip
A semiconductor substrate capable of detecting operating current of a mosfet and diode current in a miniaturized mosfet such as a trench-gate type mosfet is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows.
12/18/14
20140367640
new patent Light-emitting element, epitaxial wafer, and method for producing the epitaxial wafer
Provided are an epitaxial wafer and a light-emitting element having a type-ii mqw formed of iii-v compound semiconductors and configured to emit light with a sufficiently high intensity. The method includes a step of growing an active layer having a type-ii multi-quantum well structure (mqw) on a iii-v compound semiconductor substrate, wherein, in the step of forming the type-ii multi-quantum well structure, the type-ii multi-quantum well structure is formed by metal-organic vapor phase epitaxy using only metal-organic sources such that a number of pairs of the type-ii multi-quantum well structure is 25 or more..
12/18/14
20140367279
new patent Tsv bath evaluation using field versus feature contrast
The embodiments herein relate to methods and apparatus for determining whether a particular test bath is able to successfully fill a feature on a substrate. In various cases, the substrate is a semiconductor substrate and the feature is a through-silicon-via.
12/18/14
20140366937
new patent Solar cell
A solar cell is disclosed, which includes: a semiconductor substrate, an anti-reflective layer, a passivation layer, a back electrode and back bus bar. The semiconductor substrate has a first surface and a second surface.
12/18/14
20140366936
new patent New pn structure formed by improved doping methods to simplify manufacturing process of diodes for solar cells
A method for doping a semiconductor substrate is disclosed wherein a layer of a first conductivity type is first formed followed by forming a blocking layer with an open area. An etch process is performed through the open area to remove the layer of the first conductivity type to exposed the top surface of the semiconductor substrate.
12/18/14
20140366360
new patent Installation fixture for elastomer bands and methods of using the same
A kit comprising an installation fixture, a plurality of mechanical fasteners and an embedding tool is provided which allows for an elastomer band to be disposed in a mounting groove around a semiconductor substrate support in a manner that relieves the internal stresses of the elastomer band, leading to an elastomer band with a longer operational lifetime. The installation fixture is secured to a substrate support with mechanical fasteners.
12/11/14
20140363986
Laser scanning for thermal processing
A system is provided for thermal processing of a semiconductor substrate including a laser configured for emitting a laser beam towards the semiconductor substrate and a scanning means configured for scanning the laser beam along a first plurality of paths on the semiconductor substrate such that the paths are spaced apart from each other by predetermined distances. Further, a method for thermal processing of a semiconductor substrate is provided including scanning a laser beam along a first plurality of paths on the semiconductor substrate such that the paths are spaced apart from each other by predetermined distances..
12/11/14
20140363981
Selective etching of titanium nitride
Provided are methods for processing semiconductor substrates having titanium nitride (tin) structures as well as aluminum (al) structures and, in some embodiments, other structures, such as silicon germanium (sige), tantalum nitride (tan), hafnium oxide (hfox), silicon nitride (sin), and/or silicon oxide (sio2) structures. Etching solutions and processing conditions described herein provide high etching selectivity of titanium nitride relative to these other materials.
12/11/14
20140363973
Cmp polishing liquid and polishing method
The cmp polishing liquid containing a medium and silica particles as an abrasive grain dispersed into the medium. The silica particles have a silanol group density of 5.0/nm2 or less and the biaxial average primary particle diameter when arbitrary 20 silica particles are selected from an image obtained by scanning electron microscope observation is 25 to 55 nm.
12/11/14
20140363967
Through silicon vias for semiconductor devices and manufacturing method thereof
The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad.
12/11/14
20140363964
Gate electrode with stabilized metal semiconductor alloy-semiconductor stack
A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric capping layer overlaying the metal semiconductor alloy layer.
12/11/14
20140363944
Aqua regia and hydrogen peroxide hcl combination to remove ni and nipt residues
A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The sc2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate..
12/11/14
20140363940
Method of manufacturing a semiconductor device
A transistor is formed by forming a ridge including a first ridge portion and a second ridge portion in a semiconductor substrate, the ridge extending along a first direction, forming a source region, a drain region, a channel region, a drain extension region and a gate electrode adjacent to the channel region, in the ridge, doping the channel region with dopants of a first conductivity type, and doping the source region and the drain region with dopants of a second conductivity type. Forming the drain extension region includes forming a core portion doped with the first conductivity type in the second ridge portion, and forming the drain extension region further includes forming a cover portion doped with the second conductivity type, the cover portion being formed so as to be adjacent to at least one or two sidewalls of the second ridge portion..
12/11/14
20140363930
Latch-up free vertical tvs diode array structure using trench isolation
A method for manufacturing a transient voltage suppressing (tvs) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches.
12/11/14
20140362359
Flexible wafer leveling design for various orientation of line/trench
The present disclosure relates to a photolithography system having an ambulatory projection and/or detection gratings that provide for high quality height measurements without the use of an air gauge. In some embodiments, the photolithography system has a level sensor having a projection source that generates a measurement beam that is provided to a semiconductor substrate via a projection grating.
12/11/14
20140362265
Solid-state imaging device, driving method thereof and electronic apparatus
A solid-state imaging device includes: a semiconductor substrate including a light receiving surface which is divided according to pixels arranged in a matrix shape and is formed with a photoelectric converting section; an electrochromic film which is formed on the semiconductor substrate on a light incident path corresponding to the photoelectric converting section, in a portion of pixels selected from the pixels, and has light transmittance changing from a first transmittance to a second transmittance according to voltage applied thereto; a lower electrode which is formed below the electrochromic film; and an upper electrode which is formed above the electrochromic film.. .
12/11/14
20140362151
Radiation-curable ink for ink jet recording, record made using the same, and ink jet recording method using the same
A radiation-curable ink for ink jet recording contains n-vinylcaprolactam. The n-vinylcaprolactam content is in a range of 5% by mass to 20% by mass, inclusive, relative to the total mass of the ink.
12/11/14
20140361404
Capacitor structure
One or more embodiments relate to a semiconductor device, comprising: a semiconductor device, comprising: a semiconductor substrate; a plurality of first conductive vias, the first conductive vias electrically coupled together, each of the first conductive vias passing through the substrate; and a plurality of second conductive vias, the second conductive vias electrically coupled together, each of the second conductive vias passing through the substrate, the second conductive vias spacedly disposed from the first conductive vias, each of the second conductive vias laterally surrounding a respective one of the first conductive vias.. .
12/11/14
20140361398
Semiconductor device and method of manufacturing same
A semiconductor device includes: a first conductive type semiconductor device; a first conductive type drift region formed by epitaxial growth on the semiconductor substrate; a plurality of first conductive type vertical implantation regions formed by multistage ion implantation in the drift region, the vertical implantation regions having a prescribed vertical implantation width and a prescribed drift region width; an anode electrode disposed on the front surface of the drift region opposite to the semiconductor substrate, the anode electrode being in schottky contact with the drift region and in ohmic contact with the first conductive type vertical implantation regions; and a cathode electrode disposed on the rear surface of the semiconductor substrate opposite to the drift region, the cathode electrode being in ohmic contact with the semiconductor substrate.. .
12/11/14
20140361380
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.. .
12/11/14
20140361374
High-voltage transistor device and production method
The high-voltage transistor device has a p-type semiconductor substrate (1) that is furnished with a p-type epitaxial layer (2). A well (3) and a body region (4) are located in the epitaxial layer.
12/11/14
20140361366
Lateral double diffusion metal-oxide-semiconductor (ldmos) transistors and fabrication method thereof
A lateral double diffusion metal-oxide-semiconductor (ldmos) transistor is provided. The ldmos transistor includes a semiconductor substrate having a well region and a drain region in the well region.
12/11/14
20140361364
Doped protection layer for contact formation
Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate having a first doped region and a second doped region, and a gate stack formed on the semiconductor substrate.
12/11/14
20140361356
Active pixel sensor with nanowire structured photodetectors
An imaging device formed as an active pixel array combining a cmos fabrication process and a nanowire fabrication process. The pixels in the array may include a single or multiple photogates surrounding the nanowire.
12/11/14
20140361355
Cmos image sensors including an isolation region adjacent a light-receiving region
Cmos image sensors are provided. A cmos image sensor may include a semiconductor substrate including a light-receiving region and a logic region adjacent the light-receiving region.
12/11/14
20140361351
Gate electrode with stabilized metal semiconductor alloy-semiconductor stack
A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric capping layer overlaying the metal semiconductor alloy layer.
12/11/14
20140361339
Pmos transistors and fabrication methods thereof
A method is provided for fabricating a pmos transistor. The method includes providing a semiconductor substrate; and forming gate structures on a surface of the semiconductor substrate.
12/11/14
20140361333
Semiconductor device
When a semiconductor substrate of a semiconductor device is viewed from above, an isolation region, an igbt region, and a diode region are all formed adjacent to each other. A deep region that is connected to a body region and an anode region is formed in the isolation region.
12/11/14
20140361319
Intergrated lighting apparatus and method of manufacturing the same
An integrated lighting apparatus comprises a first control device including a semiconductor substrate, an integrated circuit block formed above a first portion of the semiconductor substrate, and a plurality of power pads formed above the integrated circuit block; a first light emitting device formed above a second portion of the semiconductor substrate; and a through plug passing through the semiconductor substrate for electrically connecting the first control device and the first light emitting device.. .
12/11/14
20140361240
Semiconductor integrated circuit apparatus and method of manufacturing the same
A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain.
12/11/14
20140361233
3 dimensional semiconductor device and method of manufacturing the same
A 3d semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes..
12/11/14
20140360577
Photovoltaic device
This photovoltaic device is provided with a crystalline semiconductor substrate, and a first amorphous layer formed on the main surface of the substrate. At the interface between the substrate and the first amorphous layer, electrical conductivity can be improved while suppressing an increase in recombination centers, and power generation efficiency can be improved by having a p-type dopant density profile that decreases stepwise in the film thickness direction from the vicinity of the interface with the substrate..
12/11/14
20140360571
Solar cell and manufacturing method thereof
A manufacturing method of a solar cell is discussed. The manufacturing method of the solar cell includes forming a tunneling layer on one surface of a semiconductor substrate, forming a semiconductor layer on the tunneling layer, doping the semiconductor layer with a first conductive dopant and a second conductive dopant to form a first conductive semiconductor layer and a second conductive semiconductor layer, and diffusing hydrogen into the first and second conductive semiconductor layers to hydrogenate the first and second conductive semiconductor layers..
12/04/14
20140359388
Core circuit test architecture
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths.
12/04/14
20140357092
Chamber wall of a plasma processing apparatus including a flowing protective liquid layer
A semiconductor plasma processing apparatus includes a vacuum chamber in which semiconductor substrates are processed, a process gas source in fluid communication with the vacuum chamber for supplying a process gas into the vacuum chamber, and an rf energy source adapted to energize the process gas into the plasma state in the vacuum chamber. The apparatus can also include a chamber wall wherein the chamber wall includes a means for supplying a plasma compatible liquid to a plasma exposed surface thereof wherein the plasma compatible liquid flows over the plasma exposed surface thereby forming a flowing protective liquid layer thereon.
12/04/14
20140357090
Cyclic aluminum nitride deposition in a batch reactor
A process for depositing aluminum nitride is disclosed. The process comprises providing a plurality of semiconductor substrates in a batch process chamber and depositing an aluminum nitride layer on the substrates by performing a plurality of deposition cycles without exposing the substrates to plasma during the deposition cycles.
12/04/14
20140357064
Tensile stressed doped amorphous silicon
The method and apparatus disclosed herein relate to preparing a stack structure for an electronic device on a semiconductor substrate. A particularly beneficial application of the method is in reduction of internal stress in a stack containing multiple layers of silicon.
12/04/14
20140357063
Manufacturing methods of semiconductor substrates
The present invention discloses manufacturing methods of semiconductor substrates. The method includes following steps: providing a semiconductor substrate with a nucleation layer, forming a microparticle etching mask on the nucleation layer, etching the nucleation layer, filling sol-gel into etched notches of the semiconductor substrate, removing the microparticle etching mask, performing growth of epitaxy rods and performing lateral connection of the top of the epitaxy rods to form a defect-free semiconductor substrate.
12/04/14
20140357059
Schottky rectifier
A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate.
12/04/14
20140357038
Through silicon via processing method for lateral double-diffused mosfets
The present invention features methods for forming a field effect transistor on a semiconductor substrate having gate, source and drain regions, with the gate region having a lateral gate channel. A plurality of spaced-apart trenches or through semiconductor vias (tsv) each having an electrically conductive plug formed therein in electrical communication with the gate, source and drain regions are configured to lower the resistance of the bottom source.
12/04/14
20140357035
Semiconductor device and method of manufacturing the same
Provided are a semiconductor device including a high voltage transistor and a low voltage transistor and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate including a high voltage region and a low voltage region; a high voltage transistor formed in the high voltage region and including a first active region, a first source/drain region, a first gate insulating layer, and a first gate electrode; and a low voltage transistor formed in the low voltage region and including a second active region, a second source/drain region, a second gate insulating layer, and a second gate electrode.
12/04/14
20140357034
Multi-height finfets with coplanar topography
A semiconductor structure is provided that has semiconductor fins having variable heights without any undue topography. The semiconductor structure includes a semiconductor substrate having a first semiconductor surface and a second semiconductor surface, wherein the first semiconductor surface is vertically offset and located above the second semiconductor surface.
12/04/14
20140357030
Fabrication of mos device with schottky barrier controlling layer
Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into a drain; forming a schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region contact trench. The schottky barrier controlling layer controls schottky barrier height of a schottky diode formed by the contact electrode and the drain..
12/04/14
20140357026
Production method for semiconductor device
A method for producing a semiconductor device includes an implantation step of performing proton implantation from a rear surface of a semiconductor substrate of a first conductivity type and a formation step of performing an annealing process for the semiconductor substrate in an annealing furnace to form a first semiconductor region of the first conductivity type which has a higher impurity concentration than the semiconductor substrate after the implantation step. In the formation step, the furnace is in a hydrogen atmosphere and the volume concentration of hydrogen is in the range of 6% to 30%.
12/04/14
20140357011
Solid-state image pick-up device and manufacturing method thereof, image-pickup apparatus, semiconductor device and manufacturing method thereof, and semiconductor substrate
A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer.. .
12/04/14
20140357009
Process for manufacturing a photovoltaic cell
A method of manufacturing a photovoltaic cell including forming a semiconductor substrate comprising opposite first and second surfaces; forming, on the first surface of the substrate, a first semiconductor area doped by implantation of first dopant elements across the substrate thickness and by thermal activation of the first implanted dopant elements at a first activation temperature; forming, on the second surface of the substrate, a second semiconductor area doped by implantation of second dopant elements across the substrate thickness and by thermal activation of the second implanted dopant elements at a second activation temperature lower than the first activation temperature; at least the thermal activation of the first dopant elements is performed by laser irradiation, the irradiation parameters being selected so that the radiation is absorbed at most down to a depth of the first micrometer of the substrate.. .
12/04/14
20140357008
Method of manufacturing solar cell and method of forming doping region
A method of manufacturing a solar cell is disclosed. The method includes forming a doping region including first and second portions having different doping concentrations by ion-implanting a dopant into a semiconductor substrate and forming an electrode connected to the doping region.


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Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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