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Semiconductor Substrate patents

      

This page is updated frequently with new Semiconductor Substrate-related patent applications.




 Quantum cascade laser patent thumbnailQuantum cascade laser
A quantum cascade laser is configured with a semiconductor substrate, and an active layer provided on a first surface of the substrate and having a cascade structure in the form of a multistage lamination of unit laminate structures each of which includes an emission layer and an injection layer. The active layer is configured to be capable of generating first pump light of a frequency ω1 and second pump light of a frequency ω2 by intersubband emission transitions of electrons, and to generate output light of a difference frequency ω by difference frequency generation from the first pump light and the second pump light.
Hamamatsu Photonics K.k.


 Solar cell and  manufacturing the same patent thumbnailSolar cell and manufacturing the same
A solar cell and a method for manufacturing the solar cell are discussed. The method for manufacturing the solar cell includes applying an electrode paste on a semiconductor substrate and sintering the electrode paste using a light sintering device to form an electrode.
Lg Electronics Inc.


 Solar cell and solar cell panel including the same patent thumbnailSolar cell and solar cell panel including the same
Disclosed is a solar cell including a semiconductor substrate, a first conductive area formed on one surface of the semiconductor substrate, a second conductive area formed on a remaining surface of the semiconductor substrate, a first electrode connected to the first conductive area, and a second electrode connected to the second conductive area. The second electrode includes a pad portion and an electrode portion that include different conductive materials as main components.
Lg Electronics Inc.


 Solar cell patent thumbnailSolar cell
Disclosed is a solar cell including a semiconductor substrate, a conductive area including first and second conductive areas disposed on one surface of the semiconductor substrate, and an electrode including a first electrode connected to the first conductive area and a second electrode connected to the second conductive area. The electrode includes an adhesive layer disposed on the semiconductor substrate or the conductive area, an electrode layer disposed on the adhesive layer and including a metal as a main component, and a barrier layer disposed on the electrode layer and including a metal that is different from the metal of the electrode layer as a main component.
Lg Electronics Inc.


 Semiconductor device and  fabricating the same patent thumbnailSemiconductor device and fabricating the same
A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region.
Samsung Electronics Co., Ltd.


 Semiconductor device and  manufacturing the same patent thumbnailSemiconductor device and manufacturing the same
The present disclosure relates to a semiconductor device and method of manufacturing the same. The method of manufacturing the semiconductor device includes: providing a substrate, forming a patterned semiconductor layer on the substrate, forming a filter layer to cover the patterned semiconductor layer and forming a low concentration dopant buried layer within the semiconductor substrate, wherein one to forty percent of dopant are filtered out by the filter layer in the formation of the low concentration dopant buried layer..
Taiwan Semiconductor Manufacturing Company Ltd.


 Semiconductor device and fabrication method thereof patent thumbnailSemiconductor device and fabrication method thereof
The present disclosure provides a method for forming a semiconductor device, including: providing a semiconductor substrate; forming a well region and a drift region in the semiconductor substrate; and forming one or more counter-doped regions in the drift region, the one or more counter-doped regions being aligned along a direction vertical to the semiconductor substrate to divide the drift region into a plurality of parts. The semiconductor fabrication method also includes: forming a gate structure on the semiconductor substrate, the gate structure covering a portion of the well region and a portion of the drift region; and forming a source electrode in the well region on one side of the gate structure and a drain electrode in the drift region on another side of the gate structure..
Semiconductor Manufacturing International (shanghai) Corporation


 Mos transistor structure with hump-free effect patent thumbnailMos transistor structure with hump-free effect
A mos transistor structure is provided. The mos transistor structure includes a semiconductor substrate having an active area including a first edge and a second edge opposite thereto.
Mediatek Inc.


 Semiconductor substrate and semiconductor device patent thumbnailSemiconductor substrate and semiconductor device
A semiconductor substrate including a substrate, a buffer layer having a nitride-based semiconductor containing carbon provided on the substrate, a high-resistance layer having a nitride-based semiconductor containing carbon provided on the buffer layer, and a channel layer having a nitride-based semiconductor provided on the high-resistance layer, the high-resistance layer including a first region having carbon concentration lower than that of the buffer layer, and a second region which is provided between the first region and the channel layer, and has the carbon concentration higher than the first region. As a result, it is possible to provide the semiconductor substrate which can reduce a leak current by enhancing crystallinity of the high-resistance layer while maintaining a high resistance of the high-resistance layer, and suppress occurrence of a decrease in electron mobility or current collapse in the channel layer by likewise enhancing crystallinity of the channel layer formed on the high-resistance layer..
Shin-etsu Handotai Co. Ltd.


 Semiconductor device manufacturing method and semiconductor device patent thumbnailSemiconductor device manufacturing method and semiconductor device
Technique disclosed herein can suppress performance variation among semiconductor devices to be manufactured upon manufacturing each semiconductor device by forming diffusion layer by ion implantation to semiconductor substrate after etching. A semiconductor device includes a semiconductor substrate.
Toyota Jidosha Kabushiki Kaisha


Structure and formation semiconductor device structure with a dummy fin structure

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device and fabricating method thereof

In accordance with various embodiments of the disclosed subject matter, a semiconductor device, and a fabricating method thereof are provided. In some embodiments, the semiconductor device comprises: a semiconductor substrate, wherein a plurality of fins are projected on a surface of the semiconductor substrate; and an insulating layer on side walls of the plurality of fins, wherein the insulating layer is located on the surface of the semiconductor substrate, a surface of the insulating layer is lower than top surfaces of the plurality of fins, and a thermal conductivity of the insulating layer is larger than a thermal conductivity of silicon oxide..
Semiconductor Manufacturing International (shanghai) Corporation

Metal line connection for improved rram reliability, semiconductor arrangement comprising the same, and manufacture thereof

Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array.
Taiwan Semiconductor Manufacturing Co., Ltd.

Resistive switching random access memory with asymmetric source and drain

A resistive random access memory (rram) structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage. The resistive element includes a resistive material layer.
Taiwan Semiconductor Manufacturing Company., Ltd.

Method of manufacturing solid-state image sensor

A method of manufacturing a solid-state image sensor, including a first transistor for transferring charges from a charge accumulation region to a first charge holding region and a second transistor for transferring charges from the first charge holding region to a second charge holding region, the method comprising forming, on the semiconductor substrate, a resist pattern having a opening on the first charge holding region, and injecting a impurity via the opening so as to make the first charge holding region be a buried type, wherein the impurity is injected such that an impurity region, which makes the first charge holding region be a buried type, is formed at a position away from an end of the gate electrode of the second transistor.. .
Canon Kabushiki Kaisha

Solid-state imaging device, manufacturing same, and electronic device

The present disclosure relates to a solid-state imaging device, a method for manufacturing the same, and an electronic device capable of increasing utilization efficiency of a substrate. The solid-state imaging device includes a first semiconductor substrate provided with a sensor circuit having a photoelectric conversion part, and a second semiconductor substrate and a third semiconductor substrate provided with respective circuits different from the sensor circuit.
Sony Corporation

Crosstalk improvement through p on n structure for image sensor

The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate having a first type of dopant; a semiconductor layer having a second type of dopant different from the first type of dopant and disposed on the semiconductor substrate; a photo-sensitive structure formed in the semiconductor layer; a multi-layer interconnect (mli) structure disposed on the semiconductor layer; a color filter disposed on the mli structure and disposed above the photo-sensitive structure; and a microlens disposed over the color filter and disposed above the photo-sensitive structure..
Taiwan Semiconductor Manufacturing Company., Ltd.

Integrated passive device on soi substrate

A method for fabricating dual-tier radio-frequency devices involves providing a silicon-on-insulator integrated circuit wafer having a semiconductor substrate and a plurality of integrated circuit devices formed thereon, at least partially removing the semiconductor substrate from a backside of the integrated circuit wafer, adding a low-loss replacement substrate to the backside of the integrated circuit wafer, and forming an integrated passive device over each of the plurality of integrated circuit devices after the adding of the low-loss replacement substrate to form a dual-tier wafer.. .
Skyworks Solutions, Inc.

Three-dimensional semiconductor device with co-fabricated adjacent capacitor

A three-dimensional semiconductor device includes a semiconductor substrate, fin(s) coupled to the substrate and surrounded at a bottom portion thereof by isolation material, each fin including a source region, a drain region and a channel region therebetween, a first gate and spacers over a portion of each fin, and a second gate and spacers, the second gate encompassing a common end portion of each fin. The first gate and corresponding source and drain regions act as an access transistor, and the second gate and common end portion(s) of the fin(s) act as a storage capacitor, and a top surface of the second gate acts as a plate for the storage capacitor, when multiple cells are arranged in an array..
Globalfoundries Inc.

Semiconductor device, circuit board, and electronic device

A novel semiconductor device or memory device is provided. Alternatively, a semiconductor device or memory device in which storage capacity per unit area is large is provided.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device

A semiconductor device includes a plurality of active regions including channel regions extending in a first direction on a semiconductor substrate and source/drain regions connected to the channel regions, a plurality of gate electrodes extending in a second direction different from the first direction to intersect the channel regions, a plurality of conductive lines electrically connected to at least one of the source/drain regions and the plurality of gate electrodes through a plurality of vias, and a power line disposed between the semiconductor substrate and the plurality of conductive lines and configured to supply a power supply voltage.. .
Samsung Electronics Co., Ltd.

Semiconductor device and a manufacturing the same

To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an lcd driver, a mark is formed in an alignment mark formation region over a semiconductor substrate.
Renesas Electronics Corporation

Three-dimensional integrated circuit laminate, and interlayer filler for three-dimensional integrated circuit laminate

A three-dimensional integrated circuit laminate, which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated, and has a first interlayer filler layer containing a resin (a) and an organic filler (b) and having a thermal conductivity of at least 0.8 w/(m·k) between the semiconductor substrate.. .

Contact structure for high aspect ratio and fabricating the same

A method of fabricating semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. A fist inter layer dielectric layer is deposited on the gate structures.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device having a multi-level interconnection structure

A semiconductor device includes a semiconductor substrate, and a multi-level interconnection structure that is provided on the semiconductor substrate and that has a plurality of interconnection layers stacked one on another. Each interconnection layer includes a real interconnection and a dummy interconnection covered with an insulative film.
Rohm Co., Ltd.

Semiconductor device

A semiconductor device includes: a semiconductor element which includes semiconductor substrate, an insulating film formed on a front surface of the semiconductor substrate and having an opening, and an electrode formed in the opening on the front surface of the semiconductor substrate; and a first protective film disposed to cover the semiconductor element. The insulating film has a thickness of not less than 1/500 of a thickness of the semiconductor substrate and not more than 4 μm.
Mitsubishi Electric Corporation

Method of forming interconnects for semiconductor devices

A method of forming interconnects for semiconductor devices includes forming a lower insulating layer and a lower interconnect on a semiconductor substrate, forming an insulating pattern layer on the lower interconnect through self-assembly, forming an interlayer insulating layer and a trench mask on the insulating pattern layer, forming a preparatory via hole allowing the insulating pattern layer to be exposed by removing a portion of the interlayer insulating layer, forming a trench by etching the interlayer insulating layer using the trench mask, forming a via hole allowing the lower interconnect to be exposed by selectively etching the insulating pattern layer within the preparatory via hole, and filling the trench and the via hole with an conductive material.. .
Samsung Electronics Co., Ltd.

Semiconductor device

Provided is a semiconductor device including an active region defined by a separation region on a main surface of a semiconductor substrate, and a field effect transistor formed in the active region. A boundary portion, over which a gate electrode pattern strides, is disposed in a boundary between the active region and the separation region and is configured such that a length of one side, in a direction of a gate length of the field effect transistor formed in the active region, becomes larger than the gate length and does not come into contact with at least one of a pair of source and drain regions of the field effect transistor..
Synaptics Japan Gk

Semiconductor device having vertical channels and manufacturing the same

A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions.
Samsung Electronics Co., Ltd.

Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device

A method of manufacturing a silicon carbide semiconductor device is provided. The method suppresses the increase in the number of manufacturing steps and is capable of suppressing the degradation of ohmic characteristics of an alloy layer with respect to a semiconductor substrate.
Mitsubishi Electric Corporation

Methods and cleaning semiconductor wafers

A method for cleaning semiconductor substrate using ultra/mega sonic device comprising holding a semiconductor substrate by using a chuck, positioning a ultra/mega sonic device adjacent to the semiconductor substrate, injecting chemical liquid on the semiconductor substrate and gap between the semiconductor substrate and the ultra/mega sonic device, changing gap between the semiconductor substrate and the ultra/mega sonic device for each rotation of the chuck during the cleaning process by turn the semiconductor substrate or the ultra/mega sonic device clockwise or counter clockwise.. .
Acm Research (shanghai) Inc.

Integrated vacuum microelectronic structure and manufacturing method thereof

An integrated vacuum microelectronic structure is described as having a highly doped semiconductor substrate, a first insulating layer placed above said doped semiconductor substrate, a first conductive layer placed above said first insulating layer, a second insulating layer placed above said first conductive layer, a vacuum trench formed within said first and second insulating layers and extending to the highly doped semiconductor substrate, a second conductive layer placed above said vacuum trench and acting as a cathode, a third metal layer placed under said highly doped semiconductor substrate and acting as an anode, said second conductive layer is placed adjacent to the upper edge of said vacuum trench, the first conductive layer is separated from said vacuum trench by portions of said second insulating layer and is in electrical contact with said second conductive layer.. .
Stmicroelectronics S.r.l.

Split gate nand flash memory structure and array, programming, erasing and reading thereof, and manufacturing

A split gate nand flash memory structure is formed on a semiconductor substrate of a first conductivity type. The nand structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region.
Silicon Storage Technology, Inc.

Sense amplifier layout for finfet technology

A sense amplifier (sa) comprises a semiconductor substrate having an oxide definition (od) region, a pair of sa sensing devices, a sa enabling device, and a sense amplifier enabling signal (sae) line for carrying an sae signal. The pair of sa sensing devices have the same poly gate length lg as the sa enabling device, and they all share the same od region.
Taiwan Semiconductor Manufacturing Co., Ltd.

Optical scanner, optical scanning method and non-transient recording medium

An optical scanner comprises a light source, an mems mirror and a position detector. The light source emits a light beam.
Toshiba Tec Kabushiki Kaisha

Optical module having multi-mode coupler formed on semiconductor substrate

An optical module that implements an mmi device including an optical hybrid primarily made of semiconductor material is disclosed. The mmi device, which has a rectangular plane shape and includes multi-mode couplers, is mounted on a carrier.
Sumitomo Electric Industries, Ltd.

Methods and compensation and current spreading correction in shared drain multi-channel load switch

Described example embodiments include an integrated circuit having a first channel area with a first fet formed in a semiconductor substrate, the substrate providing a contact to the drain. A second channel area includes a second fet formed in the semiconductor substrate.
Texas Instruments Incorporated

Surface emitting laser, surface emitting laser element and atomic oscillator

A surface emitting laser for emitting light with a wavelength λ includes a first reflection mirror provided on a semiconductor substrate; a resonator region including an active layer provided on the first reflection mirror; a second reflection mirror, including plural low refraction index layers and plural high refraction index layers, provided on the resonator region; a contact layer provided on the second reflection mirror; a third reflection mirror provided on the contact layer; and an electric current narrowing layer provided between the active layer and the second reflection mirror or in the second reflection mirror. Optical lengths of at least one of thicknesses of the low refraction index layers and the high refraction index layers formed between the electric current narrowing layer and the contact layer are (2n+1)×λ/4 (n=1, 2, .
Ricoh Company, Ltd.

Vcsel structure with embedded heat sink

An optoelectronic device includes a semiconductor substrate, having front and back sides and having at least one cavity extending from the back side through the semiconductor substrate into proximity with the front side. At least one optoelectronic emitter is formed on the front side of the semiconductor substrate in proximity with the at least one cavity.
Apple Inc.

Manufacturing high-voltage metal-oxide-semiconductor transistor

A manufacturing method of a high-voltage metal-oxide-semiconductor (hv mos) transistor device is provided. The manufacturing method includes the following steps.
United Microelectronics Corp.

Semiconductor device and manufacturing semiconductor device

A semiconductor device, including a semiconductor substrate, a semiconductor layer disposed on a surface of the semiconductor substrate, a first semiconductor region disposed in the semiconductor layer at a surface thereof, a source region and a second semiconductor region disposed in the first semiconductor region at a surface thereof, a source electrode contacting the source region and the second semiconductor region, a gate insulating film disposed on the surface of the semiconductor layer and covering a portion of the first semiconductor region between the source region and the semiconductor layer, a gate electrode disposed on a surface of the gate insulating film, a drain electrode disposed on another surface of the semiconductor substrate, and a third semiconductor region, which has an impurity concentration higher than that of the first semiconductor region, formed in the semiconductor layer at the surface thereof and being electrically connected to the source electrode.. .
Fuji Electric Co., Ltd.

Semiconductor device

A semiconductor device includes a semiconductor substrate, a base region formed in the semiconductor substrate on a front surface side thereof, a gate trench extending from a front surface side of the base region and penetrating thorough the base region, and a dummy trench extending from the front surface side of the base region and penetrating thorough the base region, where a portion of the dummy trench that extends beyond a back surface of the base region is longer than a portion of the gate trench that extends beyond the back surface of the base region.. .
Fuji Electric Co., Ltd.

Semiconductor device

The semiconductor device includes: a plurality of interlayer insulation films, each interlayer insulation film covering a front surface of a corresponding one of the gate electrodes and protruding from the front surface of the semiconductor substrate; the first metal film covering the front surface of the semiconductor substrate and plurality of the interlayer insulation films; and the protective insulation film covering a part of the first metal film. In a cross-section traversing the plurality of trenches, the end of the protective insulation film is above one of the interlayer insulation films, and a width of the one of the interlayer insulation films that is below the end of the protective insulation film is wider than widths of other interlayer insulation films..
Toyota Jidosha Kabushiki Kaisha

Source/drain regions for high electron mobility transistors (hemt) and methods of forming same

An embodiment high electron mobility transistor (hemt) includes a gate electrode over a semiconductor substrate and a multi-layer semiconductor cap over the semiconductor substrate and adjacent the gate electrode. The multi-layer semiconductor cap includes a first semiconductor layer and a second semiconductor layer comprising a different material than the first semiconductor layer.
Taiwan Semiconductor Manufacturing Company, Ltd.

Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates

Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate.

Photosensitive capacitor pixel for image sensor

A method of fabricating a pixel array includes forming a transistor network along a frontside of a semiconductor substrate. A contact element is formed for every pixel in the pixel array that is electrically coupled to a transistor within the transistor network.
Omnivision Technologies, Inc.

Process module for increasing the response of backside illuminated photosensitive imagers and associated methods

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation where the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light, and a dielectric region positioned between the textured region and the at least one junction.
Sionyx, Llc

Method and systems for coupling semiconductor substrates

Systems and methods may be provided for coupling together semiconductor devices. One or more of the semiconductor devices may be provided with an array of bump contacts formed in an etch back process.
Flir Systems, Inc.

Method including a formation of a transistor and semiconductor structure including a first transistor and a second transistor

A method includes providing a semiconductor-on-insulator structure including a semiconductor substrate, a layer of electrically insulating material over the semiconductor substrate and a layer of semiconductor material over the layer of electrically insulating material. A first transistor is formed.
Globalfoundries Inc

Independent vertical-gate 3-d nand memory circuit

A memory array provided on a semiconductor substrate includes: (a) channel structures arranged in multiple layers above the semiconductor substrate, each channel structure extending along a first direction substantially parallel a surface of the semiconductor substrate; (b) gate structures each extending along a second direction substantially transverse to the first direction and each being adjacent one of the channel structures, separated therefrom by a layer of memory material; and (c) conductors provided to connect the gate structures with circuitry fabricated in the semiconductor substrate, wherein at each location where one of the gate structure adjacent one of the channel structures, a portion of the gate structure, a portion of the channel structure and the layer of memory material constitute a memory cell of the memory array. Two or more memory cells sharing a channel structure are connected in series to form a nand string..
Schiltron Corporation

Memory device and fabricating the same

A memory device includes a semiconductor substrate, an isolation layer disposed on the semiconductor substrate, a first conductive layer disposed on the isolation layer, at least one contact plug passing through the isolation layer and electrically contacting the semiconductor substrate with the first conductive layer, a plurality of insulating layers disposed on the first conductive layer, a plurality of second conductive layers alternatively stacked with the insulating layers and insulated from the first conductive layer, a channel layer disposed on at least one sidewall of a first through opening and electrically contacting to the contact plug, wherein the first through opening passes through the insulating layers and the second conductive layers to expose the contact plug, and a memory layer disposed between the channel layer and the second conductive layers.. .
Macronix International Co., Ltd.

Die-die stacking

A semiconductor die is provided with an optical transmitter configured to transmit an optical signal to another die and an optical receiver configured to receive an optical signal from another die. Furthermore, a method of forming a semiconductor device is provided including forming a first semiconductor die with the steps of providing a semiconductor substrate, forming a transistor device at least partially over the semiconductor substrate, forming an optical receiver one of at least partially over and at least partially in the semiconductor substrate, forming a metallization layer over the transistor device, and forming an optical transmitter one of at least partially over the metallization layer and at least partially in the metallization layer..
Globalfoundries Inc.

Packages with stress-reducing structures and methods of forming same

A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor chip and semiconductor package having the same

Provided are a semiconductor chip and a semiconductor package capable of obtaining stability and reliability through a connection structure using a through-silicon-via (tsv). The semiconductor chip includes a semiconductor substrate and a through-silicon-via (tsv) structure penetrating through the semiconductor substrate.
Samsung Electronics Co., Ltd.

Multichip module, on board computer, sensor interface substrate, and the multichip module manufacturing method

A multichip module includes a plurality of semiconductor substrates and a plurality of surface mounting parts. The plurality of semiconductor substrates each have a wiring line region which contains a wiring line to pierce from one of the surfaces to the other surface.
Mitsubishi Heavy Industries, Ltd

Electronic device with multi-layer contact

An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier.
Infineon Technologies Ag

Semiconductor device with through-substrate via covered by a solder ball

The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate.
Ams Ag

Semiconductor wafers with through substrate vias and back metal, and methods of fabrication thereof

An embodiment of a semiconductor wafer includes a semiconductor substrate, a plurality of through substrate vias (tsvs), and a conductive layer. The tsvs extend between first and second substrate surfaces.
Freescale Semiconductor, Inc.

Semiconductor component and manufacture

In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a iii-n semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces.
Semiconductor Components Industries, Llc

Semiconductor component and manufacture

In accordance with an embodiment, a semiconductor component is provided that includes a leadframe having a device receiving area, one or more leadframe leads and at least one insulated metal substrate bonded to a first portion of the device receiving area. A first semiconductor device is mounted to a first insulated metal substrate, the first semiconductor device configured from a iii-n semiconductor material.
Semiconductor Components Industries, Llc

Semiconductor component and manufacture

In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a iii-n semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces.
Semiconductor Components Industries, Llc

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device is provided. The method includes forming of an interlayer insulating film on a semiconductor substrate; etching the interlayer insulating film to form a contact hole and an alignment hole wider than the contact hole; depositing a first metal layer having a thickness thicker than a half of the width of the contact hole and thinner than a half of the width of the alignment hole; etching the first metal layer so that a bottom surface of the alignment hole are exposed and the first metal layer remains covering a bottom surface of the contact hole; treating the semiconductor substrate based on the position of the alignment hole; and cutting a part of the semiconductor substrate including the alignment hole to divide a semiconductor device having the contact hole from the semiconductor substrate..
Toyota Jidosha Kabushiki Kaisha

Shallow trench isolation regions made from crystalline oxides

A method of manufacturing a semiconductor device that involves etching a trench in a semiconductor substrate, epitaxially growing a crystalline structure in the trench and forming semiconductor structures on either side of the crystalline structure. Crystalline oxides may include rare earth oxides, aluminum oxides or perovskites..
International Business Machines Corporation

Polishing apparatus and semiconductor manufacturing method

A polishing apparatus according to an embodiment includes a first polishing part, a second polishing part, and an annular part. The second polishing part includes a mounting surface for a semiconductor substrate, and rubs the semiconductor substrate mounted on the mounting surface while pressing the semiconductor substrate against the first polishing part.
Kabushiki Kaisha Toshiba

Neutral hard mask and its application to graphoepitaxy-based directed self-assembly (dsa) patterning

A material stack is formed on the surface of a semiconductor substrate. The top layer of the material stack comprises at least an organic planarization layer.
International Business Machines Corporation



Semiconductor Substrate topics:
  • Semiconductor Substrate
  • Semiconductor
  • Semiconductor Device
  • Gallium Nitride
  • Memory Cell
  • Phase Change Memory
  • Phase Change Material
  • Memory Device
  • Semiconductor Memory
  • Integrated Circuit
  • Transistors
  • Field Effect Transistor
  • Planarization
  • Conductive Layer
  • Semiconductor Devices


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