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Semiconductor Substrate patents



      
           
This page is updated frequently with new Semiconductor Substrate-related patents. Subscribe to the Semiconductor Substrate RSS feed to automatically get the update: related Semiconductor RSS feeds.

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Date/App# patent app List of recent Semiconductor Substrate-related patents
04/10/14
20140099798
 Uv-curing apparatus provided with wavelength-tuned excimer lamp and method of processing semiconductor substrate using same patent thumbnailnew patent Uv-curing apparatus provided with wavelength-tuned excimer lamp and method of processing semiconductor substrate using same
A uv irradiation apparatus for processing a semiconductor substrate includes: a uv lamp unit having at least one dielectric barrier discharge excimer lamp which is constituted by a luminous tube containing a rare gas wherein an inner surface of the luminous tube is coated with a fluorescent substance having a peak emission spectrum in a wavelength range of 190 nm to 350 nm; and a reaction chamber disposed under the uv lamp unit and connected thereto via a transmission window.. .
04/10/14
20140099786
 Methods of forming through substrate interconnects patent thumbnailnew patent Methods of forming through substrate interconnects
A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate.
04/10/14
20140099775
 Method for fabricating semiconductor device with mini sonos cell patent thumbnailnew patent Method for fabricating semiconductor device with mini sonos cell
A method for fabricating a semiconductor device with mini-sonos cell is disclosed. The method includes: providing a semiconductor substrate having a first mos region and a second mos region; forming a first trench in the semiconductor substrate between the first mos region and the second mos region; depositing a oxide liner and a nitride liner in the first trench; forming a sti in the first trench; removing a portion of the nitride liner for forming a second trench between the first mos region of the semiconductor substrate and the sti and a third trench between the sti and the second mos region of the semiconductor substrate; and forming a first conductive type nitride layer in the second trench..
04/10/14
20140099767
 Manufacturing method of semiconductor device patent thumbnailnew patent Manufacturing method of semiconductor device
An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film.
04/10/14
20140099763
 Forming silicon-carbon embedded source/drain junctions with high substitutional carbon level patent thumbnailnew patent Forming silicon-carbon embedded source/drain junctions with high substitutional carbon level
Embodiment of the present invention provides a method of forming a semiconductor device. The method includes providing a semiconductor substrate; epitaxially growing a silicon-carbon layer on top of the semiconductor substrate; amorphizing the silicon-carbon layer; covering the amorphized silicon-carbon layer with a stress liner; and subjecting the amorphized silicon-carbon layer to a solid phase epitaxy (spe) process to form a highly substitutional silicon-carbon film.
04/10/14
20140099758
 Sram devices utilizing strained-channel transistors and methods of manufacture patent thumbnailnew patent Sram devices utilizing strained-channel transistors and methods of manufacture
A novel sram memory cell structure and method of making the same are provided. The sram memory cell structure comprises strained pmos transistors formed in a semiconductor substrate.
04/10/14
20140097866
 Method of evaluating metal contamination in semiconductor sample and method of manufacturing semiconductor substrate patent thumbnailnew patent Method of evaluating metal contamination in semiconductor sample and method of manufacturing semiconductor substrate
An aspect of the present invention relates to a method of evaluating metal contamination in a semiconductor sample by dlts method, which includes obtaining a first dlts spectrum by measuring a dlts signal while varying a temperature, the dlts signal being generated by alternatively and cyclically applying to a semiconductor junction on a semiconductor sample a reverse voltage vr to form a depletion layer and a weak voltage v1 to trap carriers in the depletion layer; obtaining a second dlts spectrum by measuring a dlts signal while varying a temperature, the dlts signal is being generated by cyclically applying the vr to the semiconductor junction; obtaining a differential spectrum of the first dlts spectrum with a correction-use spectrum in the form of the second dlts spectrum or a spectrum that is obtained by approximating the second dlts spectrum as a straight line or as a curve.. .
04/10/14
20140097861
 Semiconductor device and test method patent thumbnailnew patent Semiconductor device and test method
A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion.. .
04/10/14
20140097832
 Integrated automatic compass for vehicle patent thumbnailnew patent Integrated automatic compass for vehicle
An integrated automotive compass suitable for use in a vehicle includes an application specific integrated circuit that includes at least first and second magnetoresponsive sensing elements. The first and second magnetoresponsive sensing elements and at least a portion of associated circuitry are established on a common semiconductor substrate using cmos technology.
04/10/14
20140097522
 Methods and apparatus for identifying and reducing semiconductor failures patent thumbnailnew patent Methods and apparatus for identifying and reducing semiconductor failures
The present disclosure provides multi-junction solar cell structures and fabrication methods thereof that improve electrical testing capability and reduce chip failure rates. In the present invention a special masking pattern is used in the layout such that all or some of the epitaxial layers are etched away in the corner areas of each solar cell.
04/10/14
20140097519
new patent Semiconductor device and method for fabricating the same
A method for fabricating a semiconductor device includes forming a first semiconductor wafer, in which a circuit part and a first bonding layer are stacked, on a first semiconductor substrate, forming a second semiconductor wafer, which includes structures and an insulating layer for gap-filling between the structures, on a second semiconductor substrate, the structures including a pillar and bit lines stacked therein, bonding the first semiconductor wafer with the second semiconductor wafer so that the first bonding layer faces the insulating layer, and separating the second semiconductor substrate from the bonded second semiconductor wafer.. .
04/10/14
20140097517
new patent Semiconductor device having localized charge balance structure and method
In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein.
04/10/14
20140097496
new patent Guard rings on fin structures
A device includes a semiconductor substrate, isolation regions extending into the semiconductor substrate, a plurality of semiconductor fins higher than top surfaces of the isolation regions, and a plurality of gate stacks. Each of the gate stacks includes a gate dielectric on a top surface and sidewalls of one of the plurality of semiconductor fin, and a gate electrode over the gate dielectric.
04/10/14
20140097492
new patent Semiconductor structure
A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a dielectric layer, a dielectric structure and an electrode structure.
04/10/14
20140097490
new patent Semiconductor device
A semiconductor substrate of a semiconductor device includes a body region of a first conductivity type, a drift region of a second conductivity type coming into contact with a lower surface of the body region, a gate electrode that is provided in a gate trench passing through the body region and extending to the drift region and faces the body region, and a gate insulator that is provided between the gate electrode and a wall surface of the gate trench. An inverted u-shaped section is formed in a lower surface of the gate insulator, and a floating region of the first conductivity type is formed in the inverted u-shaped section.
04/10/14
20140097477
new patent Magnetic random access memory and a method of fabricating the same
An aspect of the present embodiment, there is provided magnetic random access memory device including a semiconductor substrate, a selection transistor on the semiconductor substrate, the selection transistor including a diffusion layer, a contact plug on diffusion layer, an amorphous film on the contact plug, a lower electrode provided on the amorphous film, a first magnetic layer, a nonmagnetic layer, a second magnetic layer, an upper electrode stacked in an order and a sidewall contact film on the contact plug, the sidewall contact film being in contact with a sidewall of the upper electrode.. .
04/10/14
20140097465
new patent Silicon controlled rectifier (scr) device for bulk finfet technology
Some aspects relate to a semiconductor device disposed on a semiconductor substrate. The device includes an sti region that laterally surrounds a base portion of a semiconductor fin.
04/10/14
20140097451
new patent Proximity sensor and circuit layout method thereof
A proximity sensor and a circuit layout method thereof are disclosed. The proximity sensor includes a light sensor and a light emitting unit.
04/10/14
20140097448
new patent Semiconductor device and method of manufacturing the same
A semiconductor device includes a drift layer including a trench formed on a semiconductor substrate. A well in the drift layer overlaps an edge of the trench, and at least one gate electrode is formed at this overlapping edge region.
04/10/14
20140096909
new patent Heating plate with planar heater zones for semiconductor processing
A heating plate of a semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a first layer with an array of heater zones operable to tune a spatial temperature profile on the semiconductor substrate, and a second layer with one or more primary heaters to provide mean temperature control of the semiconductor substrate. The heating plate can be incorporated in a substrate support wherein a switching device independently supplies power to each one of the heater zones to provide time-averaged power to each of the heater zones by time divisional multiplexing of the switches..
04/10/14
20140096821
new patent Solar cell and method for making thereof
A solar cell includes a doped layer disposed on a first surface of a semiconductor substrate, a doped polysilicon layer disposed in a first region of a second surface of the semiconductor substrate, a doped area disposed in a second region of the second surface, and an insulating layer covering the doped polysilicon layer and the doped area. The insulating layer has openings exposing portions of the doped polysilicon layer and the doped layer, and the doped polysilicon layer and doped layer are respectively connected to a first electrode and a second electrode through the openings.
04/10/14
20140096606
new patent Detector of gravitational waves and method of detecting gravitational waves
A semiconductor detector of gravitational waves of a first frequency may include an oscillator having a metal coated oscillating member over a metal coated semiconductor substrate to be subjected to a casimir attraction force towards the semiconductor substrate. The oscillator may be configured to exert a force to counterbalance the casimir attraction force causing the oscillating member oscillates with a main harmonic resonance frequency equal to the first frequency.
04/03/14
20140096101
Semiconductor device and designing method of semiconductor device
A semiconductor device has: a first signal line formed in a first wiring layer formed on a semiconductor substrate, and disposed in a first direction; first and second shield lines formed in the first wiring layer, disposed on both sides of the first signal line in the first direction, and given a first fixed potential; and a plurality of third shield lines formed in a second wiring layer formed on the semiconductor substrate, disposed with a first wiring width and at a first wiring interval in a second direction almost orthogonal to the first direction in a manner to partially overlap with each of the first signal line and the first and second shield lines, and given the first fixed potential.. .
04/03/14
20140094014
Contact structures for semiconductor transistors
Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ild) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ild layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ild layer on top of the first ild layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region..
04/03/14
20140094008
Cmos devices with schottky source and drain regions
A semiconductor structure includes a semiconductor substrate, and an nmos device at a surface of the semiconductor substrate, wherein the nmos device comprises a schottky source/drain extension region. The semiconductor structure further includes a pmos device at the surface of the semiconductor substrate, wherein the pmos device comprises a source/drain extension region comprising only non-metal materials.
04/03/14
20140092680
Multiple well bias memory
A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a sense amplifier configured to sense and amplify data from the memory cell. The first and second wells have different doping concentrations and are biased to first and second voltages, respectively.
04/03/14
20140091477
System and method for chemical-mechanical planarization of a metal layer
A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a semiconductor substrate, depositing a porogen-containing low-k layer over the low-k inter-metal layer, and etching a space for the via through the low-k inter-metal layer and the porogen-containing low-k layer.
04/03/14
20140091464
Semiconductor device
The semiconductor device of the present invention includes a semiconductor substrate provided with semiconductor elements, a lower layer wiring pattern which includes first wiring and second wiring, the first wiring and the second wiring disposed separately so as to be flush with each other, and the first wiring and the second wiring being fixed at a mutually different potential, an uppermost interlayer film disposed on the lower layer wiring pattern, a titanium nitride layer disposed on the uppermost interlayer film so as to cover the first wiring and the second wiring, and the titanium nitride having the thickness of 800 Å or more, and a pad metal disposed on the titanium nitride layer.. .
04/03/14
20140091459
Chip-size, double side connection package and method for manufacturing the same
A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an lsi chip.
04/03/14
20140091430
Semiconductor device including operative capacitors and dummy capacitors
The semiconductor device according to the present invention comprises a plurality of actually operative capacitors formed, arranged in an actually operative capacitor part over a semiconductor substrate and each including a lower electrode, a ferroelectric film and an upper electrode; a plurality of dummy capacitors formed, arranged in a dummy capacitor part provided outside of the actually operative capacitor part over the semiconductor substrate and each including the lower electrode, the ferroelectric film and the upper electrode; a plurality of interconnections respectively formed on said plurality of the actually operative capacitors and respectively connected to the upper electrodes of said plurality of the actually operative capacitors; and the interconnections respectively formed on said plurality of the dummy capacitors.. .
04/03/14
20140091423
Infrared photosensor
A thermal diode for a photosensor of a thermal imaging camera includes a semiconductor substrate having a surface and two doped structures set apart from each other on the surface. Furthermore, a device is provided for influencing a current between the first and the second structure, in order to reduce a current density in an area near to the surface and to increase it in an area far from the surface.
04/03/14
20140091421
Solid-state image pickup element and solid-state image pickup element mounting structure
A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a principal face of the semiconductor substrate, a plurality of second electrode pads arrayed in a direction along a direction in which the plurality of first electrode pads are arrayed, on the principal face of the semiconductor substrate, and a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence. The plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line perpendicular to the array directions of the plurality of first and second electrode pads..
04/03/14
20140091416
Photoelectric conversion apparatus and manufacturing method for a photoelectric conversion apparatus
A photoelectric conversion apparatus has multiple photoelectric converting units disposed in a semiconductor substrate, and isolation portions disposed in the semiconductor substrate. Each photoelectric converting unit includes a second semiconductor region, a third semiconductor region, disposed below the second semiconductor region and a fourth semiconductor region disposed below the third semiconductor region.
04/03/14
20140091415
Solid-state imaging apparatus, manufacturing method for the same, and electronic apparatus
A solid-state imaging apparatus includes a semiconductor substrate, an upper layer film, and on-chip lenses. On the semiconductor substrate, a plurality of pixels are formed.
04/03/14
20140091395
Transistor
A method for fabricating a transistor device including the following processes. First, a semiconductor substrate having a first transistor region is provided.
04/03/14
20140091388
Semiconductor device and method of fabricating the same
Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer..
04/03/14
20140091380
Split gate flash cell
In one aspect, a disclosed method of fabricating a split gate memory device includes forming a gate dielectric layer overlying an channel region of a semiconductor substrate and forming an electrically conductive select gate overlying the gate dielectric layer. The method further includes forming a counter doping region in an upper region of the substrate.
04/03/14
20140091377
Implant isolated devices and method for forming the same
A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the implant isolation region.
04/03/14
20140091375
Implant isolated devices and method for forming the same
A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate and extends over the implant isolation region.
04/03/14
20140091368
Solid-state imaging device
A solid-state imaging device including: a semiconductor substrate of a first conductivity type, having a fixed electric potential; a dark-current drain region of a second conductivity type, formed on a portion of the semiconductor substrate; a connection region of the first conductivity type, formed on another portion of the semiconductor substrate where the dark-current drain region is not formed; a well region of the first conductivity type, covering the dark-current drain region and the connection region; and a first region and a second region, formed within the well region and constituting a part of a read transistor that reads signal charge generated by photoelectric conversion. The well region is maintained at a fixed electric potential by being connected to the semiconductor substrate via the connection region..
04/03/14
20140091362
Integrated circuit transistor structure with high germanium concentration sige stressor
An integrated circuit transistor structure includes a semiconductor substrate, a first sige layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first sige layer has a ge concentration of 50 percent or more..
04/03/14
20140091359
Semiconductor device
A semiconductor device includes a semiconductor substrate having one main surface in which an anode of a diode is formed. At a distance from the outer periphery of the anode, a guard ring is formed to surround the anode.
04/03/14
20140090596
Methods of combinatorial processing for screening multiple samples on a semiconductor substrate
In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes.
03/27/14
20140088401
Method for radiation monitoring
A radiation dosimeter includes a semiconductor substrate and a buried insulator layer disposed on the semiconductor substrate. The buried insulator layer has a plurality of charge traps.
03/27/14
20140087555
Method of forming semiconductor device
A semiconductor device includes a semiconductor substrate including a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions.. .
03/27/14
20140087543
Method for manufacturing soi substrate and semiconductor device
It is an object of the present invention to provide a method for manufacturing an soi substrate having an soi layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an soi substrate with high yield.
03/27/14
20140087541
Method for manufacturing a semiconductor substrate, and method for manufacturing semiconductor devices integrated in a semiconductor substrate
A method of manufacturing a semiconductor substrate includes providing a semiconductor wafer having a first surface and a second surface opposite the first surface, and forming, when seen in a cross-section perpendicular to the first surface, cavities in the semiconductor wafer at a first distance from the first surface. The cavities are laterally spaced from each other by partition walls formed by semiconductor material of the wafer.
03/27/14
20140087515
Method for the contact separation of electrically-conducting layers on the back contacts of solar cells and corresponding solar cell
A method for fabricating a solar cell including a semiconductor substrate is proposed where electrical contacting is made on the back side of the semiconductor substrate. The back side of the semiconductor substrate has locally doped regions.
03/27/14
20140087504
Oled display with spalled semiconductor driving circuitry and other integrated functions
Spalling is employed to generate a single crystalline semiconductor layer. Complementary metal oxide semiconductor (cmos) logic and memory devices are formed on a single crystalline semiconductor substrate prior to spalling.
03/27/14
20140087493
Method of manufacturing optical modulator, and optical modulator
A method for manufacturing an optical modulator having a laser diode section and an eam section. Ld growth layers which are semiconductor layers for manufacturing the laser diode section, are formed on a semiconductor substrate.
03/27/14
20140085624
Coaxial gyro accelerometer in a semiconductor substrate
A coaxial gyro accelerometer device in a semiconductor substrate for simultaneously sensing coaxial linear and rotational forces. An exemplary device includes a resonating cantilever beam within a substrate and a package having a resonating cavity.
03/27/14
20140085517
Backside illuminated image sensor pixels with dark field microlenses
A backside illuminated image sensor with an array of image sensor pixels is provided. Each image pixel may include a photodiode and associated pixel circuits formed in a front surface of a semiconductor substrate.
03/27/14
20140084476
Thermal dissipation through seal rings in 3dic structure
A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.. .
03/27/14
20140084458
Chip package and method for forming the same
An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; a sensing layer disposed on the first surface of the substrate, wherein the sensing layer has a sensing region; a conducting pad structure disposed on the substrate and electrically connected to the sensing region; a spacer layer disposed on the first surface of the substrate; a semiconductor substrate placed on the spacer layer, wherein the semiconductor substrate, the spacer layer, and the substrate together surround a cavity on the sensing region; and a through-hole extending from a surface of the semiconductor substrate toward the substrate, wherein the through-hole connects to the cavity.. .
03/27/14
20140084455
Semiconductor package and fabrication method thereof
A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability.. .
03/27/14
20140084445
Thermal dissipation through seal rings in 3dic structure
A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die.
03/27/14
20140084444
Thermal dissipation through seal rings in 3dic structure
A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die.
03/27/14
20140084419
Capacitor structure
A dram capacitor structure is disposed on the interior surface of a vertical hollow cylinder of a support structure overlying a semiconductor substrate. The support structure further includes a horizontal supporting layer that is integrally connected with the vertical hollow cylinder.
03/27/14
20140084408
Semiconductor device and production method for a semiconductor device
A semiconductor device includes a carrier substrate having at least one conductor track, at least one converter element structured at least partly from a further semiconductor substrate, and conductive structures formed on a respective converter element. The at least one converter element is electrically linked to the at least one conductor track via at least one at least partly conductive supporting element arranged between a contact side of the carrier substrate and an inner side of the converter element.
03/27/14
20140084406
Method of manufacturing solid state imaging device, and solid state imaging device
Disclosed herein is a method of manufacturing a solid state imaging device, including the steps of: forming a light receiving portion in a light receiving area of a semiconductor substrate; forming a pad portion in a pad area of the semiconductor substrate; forming a microlens material layer over the light receiving portion and the pad portion; providing the microlens material layer with a microlens corresponding to the light receiving portion; forming a low-reflection material layer on the microlens material layer; etching the microlens material layer and the low-reflection material layer over the pad portion to form an opening; and imparting hydrophilicity to a surface of the low-reflection material layer and an inside portion of the opening by a normal temperature oxygen radical treatment.. .
03/27/14
20140084370
Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates
Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate.
03/27/14
20140084364
Semiconductor device and method for manufacturing semiconductor device
A semiconductor device according to one embodiment includes a semiconductor substrate, a back-gate layer formed above the semiconductor substrate, and a stacked body formed above the back-gate layer and comprising a plurality of insulating layers alternately formed between a plurality of electrode layers. The lowermost electrode layer of the plurality of electrode layers contains metal, and remaining electrode layers of the plurality of electrode layers other than the lowermost electrode layer do not contain the metal.
03/27/14
20140084362
Semiconductor device and method for manufacturing a semiconductor device
A semiconductor device includes a transistor including a source region, a drain region, and a gate electrode. The gate electrode is disposed in a first trench arranged in a top surface of the semiconductor substrate.
03/27/14
20140084350
Semiconductor device including transistor and method of manufacturing the same
A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface..
03/27/14
20140084349
Microelectronic component and corresponding production process
A microelectronic component includes a semiconductor substrate having a top side and a reverse side, an elastically movable mass device on the top side of the substrate, at least one source region provided in or on the mass device, at least one drain region provided in or on the mass device, and a gate region suspended on a conductor track arrangement above the at least one source region and at least one drain region and spaced apart from the mass device by a gap. The conductor track arrangement is anchored on the top side of the substrate in a periphery of the mass device such that the gate region remains fixed when the mass device has been moved..
03/27/14
20140084342
Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates
Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate.
03/27/14
20140084335
Semiconductor device and method for fabricating semiconductor device
A method for fabricating a semiconductor device in which a lifetime control region can be formed within a predetermined range with high positioning accuracy is provided. In a semiconductor device, an igbt element region and a diode element region may be formed in one semiconductor substrate.
03/27/14
20140084301
Lateral silicon-on-insulator bipolar junction transistor radiation dosimeter
A radiation dosimeter includes a semiconductor substrate and a buried insulator layer disposed on the semiconductor substrate. The buried insulator layer has a plurality of charge traps.
03/27/14
20140084299
Vertical microelectronic component and corresponding production method
A vertical microelectronic component includes a semiconductor substrate having a front side and a back side, and a multiplicity of fins formed on the front side. Each fin has a side wall and an upper side and is separated from other fins by trenches.
03/27/14
20140084254
Oled display with spalled semiconductor driving circuitry and other integrated functions
Spalling is employed to generate a single crystalline semiconductor layer. Complementary metal oxide semiconductor (cmos) logic and memory devices are formed on a single crystalline semiconductor substrate prior to spalling.
03/27/14
20140084173
Semiconductor photo-detection device and radiation detection apparatus
On the front side of an n-type semiconductor substrate, p-type regions are two-dimensionally arranged in an array. A high-concentration n-type region and a p-type region are disposed between the p-type regions adjacent each other.
03/27/14
20140084172
Semiconductor photo-detection device and radiation detection apparatus
On the front side of an n-type semiconductor substrate, p-type regions are two-dimensionally arranged in an array. A high-concentration n-type region and a p-type region are disposed between the p-type regions adjacent each other.


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Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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