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This page is updated frequently with new Semiconductor Substrate-related patent applications.




 Semiconductor device patent thumbnailSemiconductor device
In a semiconductor device having a magnetic sensor configured to detect a direction of magnetism, stress applied by a magnetic flux concentrator that is a magnetic material is small. The magnetic sensor includes, in combination, hall elements arranged on a surface of a semiconductor substrate, and a magnetic flux concentrator formed of a magnetic material having the function of amplifying magnetism, the magnetic flux concentrator being arranged on the semiconductor substrate, for at least partly covering each of the hall elements.
Sii Semiconductor Corporation


 Solar cell patent thumbnailSolar cell
Disclosed is a solar cell including a semiconductor substrate, a first conductive area disposed on one surface of the semiconductor substrate, the first conductive area being of a first conductive type, a second conductive area of a second conductive type opposite to the first conductive type, a first electrode connected to the first conductive area, and a second electrode connected to the second conductive area. At least one of the first conductive area and the second conductive area is formed of a metal compound layer..
Lg Electronics Inc.


 Solar cell patent thumbnailSolar cell
A solar cell including a first conductive type semiconductor substrate; a first intrinsic semiconductor layer on a front surface of the semiconductor substrate; a first conductive type first semiconductor layer on at least one surface of the first intrinsic semiconductor layer; a second conductive type second semiconductor layer on a back surface of the semiconductor substrate; a second intrinsic semiconductor layer between the second semiconductor layer and the semiconductor substrate; a first conductive type third semiconductor layer on the back surface of the semiconductor substrate, the third semiconductor layer being spaced apart from the second semiconductor layer; and a third intrinsic semiconductor layer between the third semiconductor layer and the semiconductor substrate.. .
Intellectual Keystone Technology Llc


 Solar cell patent thumbnailSolar cell
Solar cell including a semiconductor substrate with a first and second side, a first contact structure disposed in the region of the first side of the semiconductor substrate and contacting the semiconductor substrate, a passivation layer with openings disposed on the second side of the semiconductor substrate, and a second contact structure disposed on the passivation layer, which locally contacts the semiconductor substrate through the openings of the passivation layer, wherein the first contact structure has a strip-shaped connection element and contact fingers connected to the connection element, and wherein the passivation layer has an openings-free region extending along the connection element in a region under the strip-shaped connection element of the first contact structure.. .
Solarworld Innovations Gmbh


 Zener diode having an adjustable low breakdown voltage patent thumbnailZener diode having an adjustable low breakdown voltage
The present disclosure relates to a zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The zener diode includes an anode region having the second conductivity type, formed beneath the cathode region.
Stmicroelectronics (rousset) Sas


 Semiconductor device and  manufacturing the semiconductor device patent thumbnailSemiconductor device and manufacturing the semiconductor device
A semiconductor device includes at least one first gate structure and at least one second gate structure on a semiconductor substrate. The at least one first gate structure has a flat upper surface extending in a first direction and a first width in a second direction perpendicular to the first direction.

 Semiconductor device structure with raised source/drain having cap element patent thumbnailSemiconductor device structure with raised source/drain having cap element
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a source/drain structure adjacent to the gate stack.
Taiwan Semiconductor Manufacturing Co., Ltd


 Ldmos device and fabrication method thereof patent thumbnailLdmos device and fabrication method thereof
The disclosed subject matter provides an ldmos device and fabrication method thereof. In an ldmos device, a drift region and a body region are formed in a substrate.
Semiconductor Manufacturing International (shanghai) Corporation


 Methods of manufacturing trench semiconductor devices with edge termination structures patent thumbnailMethods of manufacturing trench semiconductor devices with edge termination structures
Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate.
Freescale Semiconductor, Inc.


 Insulated gate bipolar transistor and  manufacturing same patent thumbnailInsulated gate bipolar transistor and manufacturing same
An insulated gate bipolar transistor includes: a drift layer having a semiconductor substrate with n-type conductivity; a collector layer having p-type conductivity at a surface layer of the semiconductor substrate at a back surface side; and a field stop layer between the drift layer and the collector layer that has a higher impurity concentration than the drift layer. In a thickness direction of the semiconductor substrate, a lifetime control layer is arranged with a predetermined half value width by helium ion implantation; and the field stop layer is arranged with a predetermined half value width by hydrogen ion implantation.
Denso Corporation


Method for manufacturing a semiconductor device having a schottky contact


A semiconductor device includes an n-doped monocrystalline semiconductor substrate having a substrate surface, an amorphous n-doped semiconductor surface layer at the substrate surface of the n-doped monocrystalline semiconductor substrate, and a schottky-junction forming material in contact with the amorphous n-doped semiconductor surface layer. The schottky-junction forming material forms at least one schottky contact with the amorphous n-doped semiconductor surface layer..
Infineon Technologies Austria Ag


Semiconductor device


A semiconductor device according to an embodiment includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes an element region and a termination region provided around the element region.
Kabushiki Kaisha Toshiba


Zener diode having an adjustable breakdown voltage


The present disclosure relates to a zener diode including a zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the zener diode junction upon application of a second voltage to the second conducting region..
Stmicroelectronics (rousset) Sas


Semiconductor device, and manufacturing semiconductor device


A semiconductor device comprises: an n-type semiconductor substrate; a p-type anode region formed in the semiconductor substrate on its front surface side; an n-type field stop region formed in the semiconductor substrate on its rear surface side with protons as a donor; and an n-type cathode region formed in the semiconductor substrate to be closer to its rear surface than the field stop region is, wherein a concentration distribution of the donor in the field stop region in its depth direction has a first peak, and a second peak that is closer to the rear surface of the semiconductor substrate than the first peak is, and has a concentration lower than that of the first peak, and a carrier lifetime in at least a partial region between the anode region and the cathode region is longer than carrier lifetimes in the anode region.. .
Fuji Electric Co., Ltd.


Semiconductor-substrate manufacturing method and semiconductor-device manufacturing method in which germanium layer is heat-treated


A method of manufacturing a semiconductor substrate includes: heat-treating a germanium layer 30 with an oxygen concentration of 1×1016 cm−3 or greater in a reducing gas atmosphere at 700° c. Or greater.
Japan Science And Technology Agency


Wire-last gate-all-around nanowire fet


A nanowire field effect transistor (fet) device includes a first source/drain region and a second source/drain region. Each of the first and second source/drain regions are formed on an upper surface of a bulk semiconductor substrate.
International Business Machines Corporation


Semiconductor device


A semiconductor device includes: a semiconductor substrate; and a thin film resistor formed over an upper surface of the semiconductor substrate, the thin film resistor including first thin film resistor units and second thin film resistor units alternately connected in series, each of the first thin film resistor units having an elongated main portion and end portions that are connected to the elongated main portion, the end portions each forming a u-shape together with the elongated main portion in a plan view, and respectively overlapping with two of the second thin film resistor units that are adjacent to and connected to the first thin film resistor unit in series.. .
Fuji Electric Co., Ltd.


Composite grid structure to reduce cross talk in back side illumination image sensors


A semiconductor structure for back side illumination (bsi) pixel sensors is provided. Photodiodes are arranged within a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


Composite grid structure to reduce crosstalk in back side illumination image sensors


A semiconductor structure for back side illumination (bsi) pixel sensors is provided. Photodiodes are arranged within a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


Solid-state imaging device, manufacturing solid-state imaging device, and imaging apparatus


A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of amos transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of amos transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion.. .
Sony Corporation


Solid-state image sensor and electronic device


There is provided a solid-state image sensor including a semiconductor substrate in which a plurality of pixels are arranged, and a wiring layer stacked on the semiconductor substrate and formed in such a manner that a plurality of conductor layers having a plurality of wirings are buried in an insulation film. In the wiring layer, wirings connected to the pixels are formed of two conductor layers..
Sony Corporation


Semiconductor device and manufacturing the same


A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.. .
Sony Corporation


Image sensor and manufacturing the same


Image sensor and method of manufacturing the same are provided. The image sensor includes a semiconductor substrate including a pixel area, a voltage connection area, and a pad area, a plurality of photoelectric conversion devices in the pixel area, an anti-reflective layer on a back side of the semiconductor substrate and on the plurality of photoelectric conversion devices, a device isolation structure between the plurality of photoelectric conversion devices, at least one voltage connection structure in the voltage connection area, and electrically connected to the device isolation structure, at least one voltage applying device electrically connected to the at least one voltage connection structure, an internal circuit including at least one conductive inner wire and at least one conductive inner via in an insulating layer, and a through via structure in the pad area..
Samsung Electronics Co., Ltd.


Semiconductor memory device


A semiconductor memory device according to an embodiment comprises: a memory cell array, the memory cell array including: a conductive layer, an inter-layer insulating layer, and a conductive line stacked on a semiconductor substrate in a stacking direction; first and second connecting lines that contact the semiconductor substrate and are electrically connected to the conductive line and that extend in the stacking direction; and a columnar body that penetrates the conductive layer and the inter-layer insulating layer in the stacking direction between the first and second connecting lines and that includes a first semiconductor layer, the semiconductor substrate having: a first impurity region to which a first impurity is added at a place of contact with the first connecting line; and a second impurity region to which a second impurity different from the first impurity is added at a place of contact with the second connecting line.. .
Kabushiki Kaisha Toshiba


Semiconductor memory device with first and second semicondutor films in first and second columnar bodies


A semiconductor memory device according to an embodiment comprises: conductive layers stacked in a vertical direction on a semiconductor substrate; and first and columnar bodies that extend in the vertical direction, the first and second columnar bodies each comprising: a first film; a second film disposed on the first film; and a semiconductor film, and the first film of the second columnar body having an upper end positioned higher than a first position lower than a first conductive layer and lower than a second position higher than the first conductive layer and a lower end positioned at or lower than the first position, and the second film of the second columnar body having an upper end positioned higher than the second position and a lower end positioned lower than the first position.. .
Kabushiki Kaisha Toshiba


Split gate non-volatile memory cell with 3d finfet structure, and making same


A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between.
Silicon Storage Technology, Inc.


Salicided structure to integrate a flash memory device with a high k, metal gate logic device


An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region.
Taiwan Semiconductor Manufacturing Co., Ltd.


Nonvolatile semiconductor memory device


A stacked body is disposed so as cover a periphery of a semiconductor columnar portion and includes a conductive layer and an inter-layer insulating layer stacked alternately in a stacking direction on a semiconductor substrate. An epitaxial layer is disposed on a surface of the semiconductor substrate and is electrically connected to a lower end of the semiconductor columnar portion.
Kabushiki Kaisha Toshiba


Merged n/p type transistor


A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region intersect at a common area, and a shared gate structure over each common area.. .
Globalfoundries Inc.


Finfet including tunable fin height and tunable fin width ratio


A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer.
Stmicroelectronics, Inc.


Semiconductor device and testing the semiconductor device


A semiconductor device and a method for testing the semiconductor device are provided. The semiconductor device includes a diode (protection element) and a semiconductor element having a withstand voltage that is higher than that of the diode provided on one and the same first-conductive-type semiconductor substrate, the diode having a second-conductive-type first semiconductor region selectively provided in a front surface layer of the semiconductor substrate.
Fuji Electric Co., Ltd.


Cooling channels in 3dic stacks


An integrated circuit structure includes a die including a semiconductor substrate, dielectric layers over the semiconductor substrate, an interconnect structure including metal lines and vias in the dielectric layers, a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers, and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through..
Taiwan Semiconductor Manufacturing Company, Ltd.


Semiconductor device and manufacturing method thereof


A semiconductor device according to the present embodiment includes a semiconductor substrate, an insulating film and a conductive film. The insulating film is disposed on a first surface of the semiconductor substrate.
Kabushiki Kaisha Toshiba


Semiconductor device and manufacturing method thereof


A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer.
Kabushiki Kaisha Toshiba


Jog design in integrated circuits


A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip.
Taiwan Semiconductor Manufacturing Company, Ltd.


Semiconductor device and manufacturing semiconductor device


According to one embodiment, a semiconductor device includes: a semiconductor substrate; and an insulating film provided above the semiconductor substrate. The insulating film includes: a plurality of first particles having a periodic structure; a plurality of second particles provided between the plurality of first particles and having an average particle outline size smaller than an average particle outline size of the plurality of first particles; and a filler provided between at least one of the plurality of first particles and the plurality of second particles..
Kabushiki Kaisha Toshiba


Semiconductor structure and fabrication method thereof


The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers are formed on a semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


Power and ground routing of integrated circuit devices with improved ir drop and chip performance


An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (imd) layers and a plurality of first conductive layers embedded in respective said plurality of imd layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of imd layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.. .
Mediatek Inc.


Semiconductor memory device


A semiconductor memory device according to an embodiment comprises: when three directions intersecting each other are assumed to be first through third directions, and two directions intersecting each other in a plane extending in the first and second directions are assumed to be fourth and fifth directions, a memory cell array including: a conductive layer stacked in the third direction above a semiconductor substrate and having a first region; and a first columnar body penetrating the first region of the conductive layer in the third direction and including a semiconductor film, the first columnar body having a cross-section along the first and second directions in which, at a first position which is a certain position in the third direction, a length in the fourth direction is shorter than a length in the fifth direction.. .
Kabushiki Kaisha Toshiba


Semiconductor device and manufacturing semiconductor device


According to one embodiment, a semiconductor device includes an insulating layer provided on a semiconductor substrate, an opening provided on the insulating layer, a spacer film provided in a side wall of the opening in a stepped shape, and configured to have an etching resistance lower than that of the insulating layer, and a conductive body provided in the opening to be configured to cover the spacer film.. .
Kabushiki Kaisha Toshiba


Structure and formation damascene structure


A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first conductive feature over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


Method of manufacturing semiconductor device and semiconductor manufacturing apparatus


A method of manufacturing a semiconductor device uses a semiconductor manufacturing apparatus including a turn table allowing placement of at least first and second semiconductor substrates and being capable of moving positions of the first and the second semiconductor substrates by turning, a first film forming chamber, and a second film forming chamber. The first and the second film forming chambers are provided with an opening capable of loading and unloading the first and the second semiconductor substrates by lifting and lowering the first and the second semiconductor substrates placed on the turn table.
Kabushiki Kaisha Toshiba


Semiconductor manufacturing method and laminated body


A semiconductor manufacturing method according to a present embodiment includes forming a supporter on a second surface of a semiconductor substrate opposite to a first surface to be ground of the semiconductor substrate. The semiconductor manufacturing method includes thinning the thickness of the semiconductor substrate by grinding the first surface.
Kabushiki Kaisha Toshiba


Semiconductor manufacturing method and semiconductor manufacturing device


According to one embodiment, a semiconductor manufacturing method for a stacked body that includes a semiconductor substrate, a supporting substrate containing silicon, and a joining layer arranged between the semiconductor substrate and the supporting substrate to joint the semiconductor substrate and the supporting substrate, in which a surface of the semiconductor substrate opposite to the joining layer is to be ground, includes irradiating the stacked body with electromagnetic wave having energy of 0.11 to 0.14 ev from a side of the supporting substrate, and separating the semiconductor substrate from the supporting substrate.. .
Kabushiki Kaisha Toshiba


Semiconductor manufacturing method


A semiconductor manufacturing method in accordance with an embodiment includes feeding a first gas, which contains a component of a first film, to a reaction chamber, and forming a first film over a semiconductor substrate, which is accommodated in the reaction chamber, through plasma cvd. The semiconductor manufacturing method includes feeding a second gas to the reaction chamber after forming the first film, allowing the first gas in the reaction chamber to react on the second gas, and forming a second film, which has a composition different from that of the first film, over the surface of the first film.
Kabushiki Kaisha Toshiba


Atomic layer process chamber for 3d conformal processing


Embodiments described herein relate to methods for forming or treating material layers on semiconductor substrates. In one embodiment, a method for performing an atomic layer process includes delivering a species to a surface of a substrate at a first temperature, followed by spike annealing the surface of the substrate to a second temperature to cause a reaction between the species and the molecules on the surface of the substrate.
Applied Materials, Inc.


Substrate carrier for a reduced transmission of thermal energy


According to the present disclosure, a semiconductor substrate handling systems and substrate carrier is provided. The substrate carrier for holding a substrate to be processed and for transporting the substrate in or through a processing area with a transport device includes a main portion for holding the substrate; a first end portion adapted to be supported by the transport device; and at least one first intermediate portion connecting the main portion with the first end portion.
Applied Materials, Inc.


Sensor integrated metal dielectric filters for solar-blind silicon ultraviolet detectors


A filter for electromagnetic radiation including one or more dielectric spacer regions and one or more reflective regions integrated on a semiconductor substrate, the semiconductor substrate including a semiconductor photodetector, such that the filter transmits ultraviolet radiation to the semiconductor photodetector, the ultraviolet radiation having a range of wavelengths, and the filter suppresses transmission of electromagnetic radiation, having wavelengths outside the range of wavelengths, to the semiconductor photodetector.. .
California Institute Of Technology


Cleaning agent for semiconductor substrates and processing semiconductor substrate surface


The present invention relates to a cleaning agent for a semiconductor substrate having a copper wiring film or a copper alloy wiring film, and a cobalt-containing film to be used in a post-process of a chemical mechanical polishing process, comprising (a) an organic acid represented by general formula described in the present specification, (b) amines selected from the group consisting of (b-1) diamines, (b-2) amidines, (b-3) azoles, and (b-4) pyrazines or pyrimidines, represented by general formulae described in the present specification, (c) a hydroxylamine derivative, and (d) an oxygen scavenger represented by general formula described in the present specification, and being an aqueous solution having a ph of 10 or higher; and a processing method for the surface of a semiconductor substrate, having a copper wiring film or a copper alloy wiring film, and a cobalt-containing film, which comprises using the cleaning agent.. .
Wako Pure Chemical Industries, Ltd.


Semiconductor pressure sensor and fabricating same


In a semiconductor pressure sensor, a fixed electrode is formed as the same layer as a diffusion layer formed to extend from a surface of a semiconductor substrate to inside of the semiconductor substrate. A void is formed by removing a sacrifice film, which is a region constituted of the same film as a floating gate electrode.
Mitsubishi Electric Corporation


Cleaning semiconductor substrate storage articles


Provided are methods and systems for cleaning various semiconductor substrate storage articles, in particular, foup doors. The foup doors and other similar articles often have openings that may get contaminated with cleaning liquids if not covered.
Brooks Ccs Gmbh


Solid-state image capturing element, manufacturing method therefor, and electronic device


The present disclosure relates to a solid-state image capturing element, a manufacturing method therefor, and an electronic device, which are capable of controlling a thickness of a depletion layer. The solid-state image capturing element includes pixels each in which a photoelectric conversion film configured to perform photoelectric conversion on incident light and a fixed charge film configured to have a predetermined fixed charge are stacked on a semiconductor substrate.
Sony Corporation


Method for doping an active hall effect region of a hall effect device and hall effect device having a doped active hall effect region


Methods for doping an active hall effect region of a hall effect device in a semiconductor substrate, and hall effect devices having a doped active hall effect region are provided. A method includes forming a first doping profile of a first doping type in a first depth region of the active hall effect region by means of a first implantation with a first implantation energy level, forming a second doping profile of the first doping type in a second depth region of the active hall effect region by means of a second implantation with a second implantation energy level, and forming an overall doping profile of the active hall effect region by annealing the semiconductor substrate with the active hall effect region having the first and the second doping profile..
Infineon Technologies Ag


Embedded gallium-nitride in silicon


A method and structure for integrating gallium nitride into a semiconductor substrate. The method may also include means for isolating the gallium nitride from the semiconductor substrate..
International Business Machines Corporation


Solar cell manufacturing method


A solar cell manufacturing method includes: forming a first amorphous semiconductor layer of one conductivity type on a main surface of a semiconductor substrate; forming an insulation layer on the first amorphous semiconductor layer; etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region; forming a second amorphous semiconductor layer of an other conductivity type on the insulation layer after the etching, the other conductivity type being different from the one conductivity type; and etching to remove the second amorphous semiconductor layer in a predetermined second region, wherein the etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region includes: applying an etching paste to the insulation layer in the predetermined first region; and etching to remove the insulation layer and the first amorphous semiconductor layer in the predetermined first region using the etching paste.. .
Panasonic Intellectual Property Management Co., Ltd.


Photoelectric conversion element, photoelectric conversion module, and solar photovoltaic power generation system


There is provided a photoelectric conversion element which can prevent the contact resistance between a non-crystalline semiconductor layer containing impurities and an electrode formed on the non-crystalline semiconductor layer from increasing, and can improve the element characteristics. A photoelectric conversion element (10) includes a semiconductor substrate (12), a first semiconductor layer (20n), a second semiconductor layer (20p), a first electrode (22n), and a second electrode (22p).
Sharp Kabushiki Kaisha


Semiconductor device and a manufacturing method thereof


In a semiconductor device including a split gate type monos memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the monos memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches..
Renesas Electronics Corporation


Source/drain regions for fin field effect transistors and methods of forming same


A method for forming a semiconductor device includes forming a fin extending upwards from a semiconductor substrate and forming a sacrificial layer on sidewalls of a portion of the fin. The method further includes forming a spacer layer over the sacrificial layer and recessing the portion of the fin past a bottom surface of the sacrificial layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


Semiconductor device


According to one embodiment, a semiconductor device includes a semiconductor substrate having a trench and including an active area including a channel area formed along an inner surface of the trench and source/drain areas formed at both ends of the channel area and sandwiching the trench, a gate insulating film formed on the inner surface of the trench, and a gate electrode formed in the trench in which the gate insulating film is provided. A main surface of the semiconductor substrate has {100} plane orientation, a portion of the channel area parallel to a side surface of the trench has {110} channel plane orientation and has <100> channel orientation in a channel length direction, and tensile stress in the channel length direction and compressive stress in a channel width direction are applied to the portion of the channel area parallel to the side surface of the trench..

Fully depleted device with buried insulating layer in channel region


A semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and a buried insulating material region disposed in the active region under the gate structure. The buried insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth of the active region.
Globalfoundries Inc.


Semiconductor structure including backgate regions and the formation thereof


A semiconductor structure includes a semiconductor substrate, a plurality of transistors and an electrically insulating layer provided between the substrate and the plurality of transistors, and a trench isolation structure including a portion between a first and a second island of the semiconductor structure and extending into the substrate to a first depth. The substrate includes a bottom region having a first type of doping and extending at least to a second depth greater than the first depth, and a deep well region having a second type of doping and extending to a third depth greater than the first depth and smaller than the second depth.
Globalfoundries Inc.


Semiconductor device, integrated circuit and manufacturing a semiconductor device


A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to at least two sides of the channel region.
Infineon Technologies Ag


Method of manufacturing a semiconductor device


A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate of a first conductivity type having a continuous first area and a second area, introducing dopants of the first conductivity type in the continuous first area of the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer, and forming trenches in the second semiconductor layer in the continuous first area.. .
Infineon Technologies Ag


Semiconductor device


A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first region of a first conductivity type provided along the first surface selectively on a second region of a second conductivity type formed along the first surface, and a third region of a first conductivity type between the second region and the second surface. The semiconductor device also includes a gate electrode adjacent to the second region.
Kabushiki Kaisha Toshiba


Diamond shaped source drain epitaxy with underlying buffer layer


A semiconductor structure includes a fin upon a semiconductor substrate. A clean epitaxial growth surface is provided by forming a buffer layer upon fin sidewalls and an upper surface of the fin.
Globalfoundries Inc.


Method for manufacturing a transistor


A method comprises arranging a stack, on a semiconductor substrate, comprising a sacrificial layer and an insulating layer. The insulator layer is at least partially arranged between the semiconductor substrate and the sacrificial layer.
Infineon Technologies Dresden Gmbh


Method of manufacturing a semiconductor device


A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region.
Infineon Technologies Ag


Semiconductor arrangement and manufacturing the same


A semiconductor arrangement and a method for manufacturing the same. An arrangement may include a bulk semiconductor substrate; a fin formed on the substrate; a first finfet and a second finfet formed on the substrate.
Institute Of Microelectronics, Chinese Academy Of Sciences


Field effect power transistor metalization having a comb structure with contact fingers


A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically conducting or doped semiconductor substrate is provided. A metalization of source electrode contact areas, a metalization of drain electrode contact areas and a metalization of gate electrode contact areas are on a semiconductor surface of the semiconductor layers and have a plurality of metalization layers, between which insulation layers are arranged in a lateral direction.
Infineon Technologies Austria Ag


Closed cell configuration to increase channel density for sub-micron planar semiconductor power device


A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions.
Alpha And Omega Semiconductor Incorporated


Double aspect ratio trapping


A semiconductor structure is provided by a process in which two aspect ratio trapping processes are employed. The structure includes a semiconductor substrate portion of a first semiconductor material having a first lattice constant.
International Business Machines Corporation


Semiconductor substrate, semiconductor device and manufacturing semiconductor device


A semiconductor substrate of an embodiment includes a sic layer having a surface inclined in a <11-20> direction plus or minus 5° from a {0001} face at an off angle of 0° to 10°. Area density of threading edge dislocation clusters in the sic layer is 18.8 cm−2 or less, each of the threading edge dislocation clusters includes a plurality of threading edge dislocations on the surface, the threading edge dislocations included in each of the threading edge dislocation clusters exist in a region that extends in a [1-100] direction plus or minus 5° and has a width of 30 μm or less, each of the threading edge dislocation clusters includes at least three threading edge dislocations adjacent at an interval of 30 μm or less, and an interval of adjacent threading edge dislocations in each of the threading edge dislocation clusters is 70 μm or less..
Kabushiki Kaisha Toshiba


Integrated strained fin and relaxed fin


A relaxed fin and a strained fin are formed upon a semiconductor substrate. The strained fin is more highly strained relative to relaxed fin.
Globalfoundries Inc.


Semiconductor device and manufacturing semiconductor device


According to one embodiment, a semiconductor device includes a semiconductor substrate made of a first semiconductor material, an element isolation insulating film, a gate electrode film, source/drain regions, a channel region, and a diffusion preventing film. The channel region is provided near a surface of the semiconductor substrate below the gate electrode film, and containing a second impurity of a predetermined conductivity type diffused therein.
Kabushiki Kaisha Toshiba


Semiconductor device and producing semiconductor device


Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n− drift layer, forming an n-type fs layer having lower resistance than the n-type semiconductor substrate in the rear surface of the n− drift layer. When the proton irradiation is performed a plurality of times, the next proton irradiation is performed to as to compensate for a reduction in mobility due to disorder which remains after the previous proton irradiation.
Fuji Electric Co., Ltd.


Method of fabricating multi-wafer image sensor


A method of fabricating an image system includes forming a first wafer that includes a first semiconductor substrate and a first interconnect layer. A pixel array is formed in an imaging region of the first semiconductor substrate and a first insulation-filled trench is formed in a peripheral circuit region of the first semiconductor substrate.
Omnivision Technologies, Inc.


Imaging package with removable transparent cover


An imaging package includes an image sensor package formed with a semiconductor substrate. A removable transparent cover is bonded over the image sensor package to cover a first side the image sensor package.
Omnivision Technologies, Inc.


Solid-state imaging device and manufacturing method therefor, and electronic apparatus


There is provided a solid state imaging device including a pixel including a photoelectric conversion unit that generates and accumulates a charge according to a received light amount, a charge accumulation unit that accumulates the generated charge, a first transfer transistor that transfers the charge of the photoelectric conversion unit to the charge accumulation unit, a charge holding unit that holds the charge to read out as a signal, and a second transfer transistor that transfers the charge of the charge accumulation unit to the charge holding unit, in which a gate electrode of the first transfer transistor is formed to be buried up to a predetermined depth from a semiconductor substrate interface, and the charge accumulation unit is formed in a longitudinally long shape to be extended in a depth direction along a side wall of the gate electrode of the first transfer transistor to be buried therein.. .
Sony Corporation


Semiconductor device and manufacturing semiconductor device


According to one embodiment, a stacked body of n layers is stacked on a semiconductor substrate, steps are provided in the stacked body such that upper layers are retracted behind lower layers, n lower openings are provided in correspondence with the individual layers of the stacked body and are equal in depth, one to n upper openings are provided on one to n lower openings and are different in depth, n lower-layer contact electrodes are provided in the lower openings, and one to n upper-layer contact electrodes are provided in the upper openings.. .
Kabushiki Kaisha Toshiba


Method of manufacturing semiconductor device and semiconductor device


In a method of manufacturing a semiconductor device of an embodiment, first and second mask patterns are formed on a stacked body formed on a semiconductor substrate. Then, a first step-like pattern and a first dummy pattern are formed from the stacked body.
Kabushiki Kaisha Toshiba


Method of manufacturing semiconductor device and semiconductor device


According to one embodiment of a method of manufacturing a semiconductor device, a film stack in which a first film and a second film are alternately and repeatedly stacked is formed on a semiconductor substrate. Further, silicon oxide which is a first interlayer insulation film is formed at a non-stack area where the film stack is not disposed up to a predetermined height.
Kabushiki Kaisha Toshiba


Embedded memory and methods of forming the same


A method for forming an embedded flash memory device includes a gate stack, and source and drain regions in the semiconductor substrate is disclosed. The first source and drain regions are on opposite sides of the gate stack.
Taiwan Semiconductor Manufacturing Company, Ltd.


Method of forming a device including a floating gate electrode and a layer of ferroelectric material


A method disclosed herein includes providing a semiconductor structure, the semiconductor structure comprising a semiconductor substrate and a gate stack, the gate stack comprising a gate insulation material over the substrate, a floating gate electrode material over the gate insulation material, a ferroelectric transistor dielectric over the floating gate electrode material and a top electrode material over the ferroelectric transistor dielectric, performing a first patterning process to remove portions of the top electrode material and the ferroelectric transistor dielectric and performing a second patterning process after the first patterning process to remove portions of the floating gate electrode material and the gate insulation material, wherein a projected area of an upper portion of the gate structure onto a plane that is perpendicular to a thickness direction of the substrate is smaller than a projected area of the lower portion of the gate structure onto the plane.. .
Namlab Ggmbh


Semiconductor memory device


Three directions intersecting each other are referred to as first to third directions. A semiconductor memory device according to embodiments includes a semiconductor substrate having a top surface spread in the first and second directions, and a plurality of conductive layers laminated at predetermined intervals in the third direction on the semiconductor substrate.
Kabushiki Kaisha Toshiba


Semiconductor memory device and manufacturing the same


According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a first electrode film formed on the semiconductor substrate, a second electrode film formed on the first electrode film, a first semiconductor member going through the first electrode film, a second semiconductor member going through the second electrode film and connected to the first semiconductor member, a first insulating layer provided between the first electrode film and the first semiconductor member, and a memory film provided between the second electrode film and the second semiconductor member and capable of storing charge. The first electrode film includes a silicon layer, and a metal layer provided on the silicon layer..
Kabushiki Kaisha Toshiba


Semiconductor device and forming the same


A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film; a gate electrode filled in the active region; a bit line contact structure coupled to an active region between the gate electrodes; and a line-type bit line electrode formed over the bitline contact structure. The bit line contact structure includes a bit line contact formed over the active region; and an ohmic contact layer formed over the bit line contact..
Sk Hynix Inc.


Methods for forming pillar bumps on semiconductor wafers


The subject matter contained herein discloses methods for forming a vertical metallic pillar overlying an under bump metal pad further overlying a semiconductor substrate, and applying a discrete solder cap on a top surface of the pillar, wherein the metallic pillar is defined by at least one photoresist layer. The method includes heating a multi-element metallic paste containing a variable amount of metallic powder, a melting point depressant and a flux such that the metal powder sinters to form the metallic pillar and simultaneously adheres the metallic pillar to the underbump metal pad..
Flipchip International Llc


Protection ring for image sensors


Some embodiments of the present disclosure provide an image sensor. The image sensor includes a pixel sensor array including a plurality of photosensors arranged in a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


Semiconductor device with transistor local interconnects


A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate.
Globalfoundries Inc.


Semiconductor device and manufacturing the same


Provided is a corrosion resistant semiconductor device including a fuse element that can be cut by laser light. A silicon nitride film is formed above the fuse element via a metal lattice and an interlayer film left therein so that, when laser light radiated from a rear surface of a semiconductor substrate is collected at the fuse element, the fuse element may generate heat, expand, and rupture.
Sii Semiconductor Corporation


Semiconductor device and manufacturing the same


Provided is a corrosion resistant semiconductor device including a fuse element that can be cut by laser light. In the semiconductor device, an upper portion of the fuse element is covered with a porous insulating film so that, when laser light radiated from a rear surface of a semiconductor substrate is collected at the fuse element, the fuse element may generate heat, expand, and rupture.
Sii Semiconductor Corporation


Semiconductor device


A semiconductor device includes a first insulating film, a first wiring, a second insulating film, and a second wiring. The first insulating film is formed on a semiconductor substrate.
Panasonic Intellectual Property Management Co., Ltd.


Semiconductor structure with through-silicon via


A semiconductor structure includes a semiconductor substrate and a conductive element formed in a portion of the semiconductor substrate. The semiconductor structure further includes a plurality of insulating elements formed in portions of the semiconductor substrate at a first region surrounding the conductive element and a semiconductor device formed over a portion of the semiconductor substrate at a second region adjacent to the first region.
Mediatek Inc.


Semiconductor devices having through electrodes and methods of fabricating the same


A semiconductor device includes a semiconductor substrate, a circuit layer including an interlayer insulating layer on an upper surface of the substrate, and a conductive via penetrating through the interlayer insulating layer and the substrate, and electrically connected to the circuit layer. The device further includes an insulating layer surrounding the conductive via, and located between the conductive via and the substrate and between the conductive via and interlayer insulating layer, and a buffer layer located between the insulating layer and the conductive via, and overlapping at least a portion of the interlayer insulating layer in a depth direction of the conductive via..

Method of manufacturing a semiconductor device


A method of manufacturing a semiconductor device includes irradiating a first photoresist layer via a light source, measuring a first exposure intensity of the first photoresist layer, irradiating a second photoresist layer via the light source, measuring a second exposure intensity of the second photoresist layer, subtracting the second exposure intensity from the first exposure intensity, and subsequent to the subtracting, exposing a third photoresist layer formed on a semiconductor substrate by using the light source, wherein an out-of-band (oob) extreme ultraviolet (euv) light eliminating layer is formed on the second photoresist layer.. .
Samsung Electronics Co., Ltd.


Cap layer for spacer-constrained epitaxially grown material on fins of a finfet device


A method includes forming at least one fin in a semiconductor substrate. A fin spacer is formed on at least a first portion of the at least one fin.
Globalfoundries Inc.


Method for manufacturing semiconductor device


According to one embodiment, a method for manufacturing a semiconductor device, includes: selectively forming a plurality of electrode layers on a first surface of a semiconductor substrate, the semiconductor substrate having the first surface and a second surface; and dividing the semiconductor substrate by forming a gap piercing from the first surface to the second surface of the semiconductor substrate, the gap being formed by dry etching the first surface of the semiconductor substrate exposed between the plurality of electrode layers, the plurality of electrode layers being used as masks.. .
Kabushiki Kaisha Toshiba


Method for manufacturing semiconductor device


According to an embodiment, a method for manufacturing a semiconductor device includes: selectively forming a plurality of mask layers on a first surface of a semiconductor substrate, and the semiconductor substrate having the first surface and a second surface; dividing the semiconductor substrate by forming a gap piercing from the first surface to the second surface of the semiconductor substrate, the gap being formed by dry-etching the first surface of the semiconductor substrate exposed between the plurality of mask layers, and a width of the gap on the second surface side being larger than a width of the gap on the first surface side; and forming a first electrode under a reduced-pressure atmosphere on the first surface of the semiconductor substrate after the semiconductor substrate being divided.. .
Kabushiki Kaisha Toshiba


Technique to deposit sidewall passivation for high aspect ratio cylinder etch


Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner.
Lam Research Corporation


Method of fabricating electrostatic discharge protection structure


A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided.
United Microelectronics Corporation


Double aspect ratio trapping


A semiconductor structure is provided by a process in which two aspect ratio trapping processes are employed. The structure includes a semiconductor substrate portion of a first semiconductor material having a first lattice constant.
International Business Machines Corporation




Semiconductor Substrate topics:
  • Semiconductor Substrate
  • Semiconductor
  • Semiconductor Device
  • Gallium Nitride
  • Memory Cell
  • Phase Change Memory
  • Phase Change Material
  • Memory Device
  • Semiconductor Memory
  • Integrated Circuit
  • Transistors
  • Field Effect Transistor
  • Planarization
  • Conductive Layer
  • Semiconductor Devices


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