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Semiconductor Substrate patents



      

This page is updated frequently with new Semiconductor Substrate-related patent applications.




Date/App# patent app List of recent Semiconductor Substrate-related patents
04/07/16
20160099361 
 Element and photovoltaic cell patent thumbnailElement and photovoltaic cell
The invention provides an element including a semiconductor substrate and an electrode disposed on the semiconductor substrate, the electrode being a sintered product of a composition for an electrode that includes phosphorus-containing copper alloy particles, glass particles and a dispersing medium, and the electrode includes a line-shaped electrode having an aspect ratio, which is defined as electrode short length : electrode height, of from 2:1 to 250:1.. .
Hitachi Chemical Company, Ltd.


04/07/16
20160099358 
 Method of manufacturing semiconductor device patent thumbnailMethod of manufacturing semiconductor device
A semiconductor device including a nonvolatile memory cell and a field effect transistor together is improved in performance. In a method of manufacturing a semiconductor device, a hydrogen-containing insulating film is formed before heat treatment of a semiconductor wafer, the hydrogen-containing insulating film covering a gate electrode and agate insulating film in a region that will have a memory cell therein, and exposing a region that will have therein a misfet configuring a peripheral circuit.
Renesas Electronics Corporation


04/07/16
20160099351 
 Self-aligned slotted accumulation-mode field effect transistor (accufet) structure and method patent thumbnailSelf-aligned slotted accumulation-mode field effect transistor (accufet) structure and method
This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers.

04/07/16
20160099350 
 Semiconductor device patent thumbnailSemiconductor device
A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and extends in a first direction with a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped semiconductor layer resides on the fin-shaped semiconductor layer.
Unisantis Electronics Singapore Pte. Ltd.


04/07/16
20160099334 
 Bipolar transistor manufacturing method patent thumbnailBipolar transistor manufacturing method
A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.. .
Stmicroelectronics Sa


04/07/16
20160099324 
 Structure and formation  semiconductor device with gate stack patent thumbnailStructure and formation semiconductor device with gate stack
A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


04/07/16
20160099320 
 Semiconductor composite film with heterojunction and manufacturing method thereof patent thumbnailSemiconductor composite film with heterojunction and manufacturing method thereof
The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface.
Richtek Technology Corporation


04/07/16
20160099310 
 Semiconductor device integrating high and low voltage devices patent thumbnailSemiconductor device integrating high and low voltage devices
The present invention is directed to a method for forming multiple active components, such as bipolar transistors. Mosfets, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components.
Alpha & Omega Semiconductor Incorporated


04/07/16
20160099309 
 Method for growing iii-v epitaxial layers patent thumbnailMethod for growing iii-v epitaxial layers
Disclosed are methods of growing iii-v epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer.
Epigan Nv


04/07/16
20160099307 
 Termination design by metal strapping guard ring trenches shorted to a body region to shrink termination area patent thumbnailTermination design by metal strapping guard ring trenches shorted to a body region to shrink termination area
This invention discloses a semiconductor power device formed in a semiconductor substrate of a first conductivity type comprises an active cell area and a termination area surrounding the active cell area and disposed near edges of the semiconductor substrate. The termination area includes a plurality of trenches filled with a conductivity material forming a shield electrode and insulated by a dielectric layer along trench sidewalls and trench bottom surface wherein the trenches extending vertically through a body region of a second conductivity type near a top surface of the semiconductor substrate and further extending through a surface shield region of the first conductivity type.
Alpha And Omega Semiconductor Incorporated


04/07/16
20160099302 

Embedded metal-insulator-metal capacitor


A method of manufacturing a semiconductor device comprising a capacitor structure is provided, including the steps of forming a first metallization layer comprising a first dielectric layer and a first conductive layer functioning as a lower electrode for the capacitor structure over a semiconductor substrate, forming a barrier layer functioning as a capacitor insulator for the capacitor structure on the first metallization layer, forming a metal layer on the barrier layer and etching the metal layer to form an upper electrode of the capacitor structure.. .
Globalfoundries Inc.


04/07/16
20160099291 

Metal line connection for improved rram reliability, semiconductor arrangement comprising the same, and manufacture thereof


Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array.
Taiwan Semiconductor Manufacturing Co., Ltd.


04/07/16
20160099283 

Photosensor with channel region having center contact


A pixel cell includes a charge accumulation region having a second doping polarity buried completely in a semiconductor substrate having a first doping polarity beneath a first surface. The charge accumulation region accumulates image charge in response to light directed through a second surface.
Omnivision Technologies, Inc.


04/07/16
20160099278 

Back-illuminated integrated imaging device with simplified interconnect routing


A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels.
Stmicroelectronics (crolles 2) Sas


04/07/16
20160099267 

Cmos image sensor for reducing dead zone


An image sensor such as a complementary metal-oxide-semiconductor (cmos) image sensor and a method of manufacturing the same are provided. The cmos image sensor includes: a semiconductor substrate including a first surface and a third surface formed by removing a part of the semiconductor substrate from a second surface opposite to the first surface; a plurality of active regions which are formed between the first surface and the third surface and each of which includes a photoelectric conversion element generating charges in response to light input through the third surface; and an isolation region vertically formed from either of the first and third surfaces to isolate the active regions from one another.
Samsung Electronics Co., Ltd.


04/07/16
20160099216 

Semiconductor device structure and forming the same


A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


04/07/16
20160099193 

Semiconductor device


A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor substrate; an electrode pad provided on the main plane of the semiconductor substrate and connected to the semiconductor element; a guard ring surrounding the semiconductor element and the electrode pad, and provided on the main plane of the semiconductor substrate; and an insulating film covering all region of a semiconductor of the main plane of the semiconductor substrate exposed inside the guard ring, wherein the insulating film is made of a water impermeable material.. .
Mitsubishi Electric Corporation


04/07/16
20160099182 

Backside contacts for integrated circuit devices


A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor substrate. A source/drain region of the transistor is disposed in the well region.
Taiwan Semiconductor Manufacturing Co., Ltd.


04/07/16
20160099180 

Method for manufacturing a semiconductor switching device with different local cell geometry


A method for manufacturing a semiconductor device includes providing a semiconductor substrate having an outer rim, an active area, and an edge termination region arranged between the active area and the outer rim, and forming a plurality of switchable cells in the active area. Each of the switchable cells includes a body region, a gate electrode structure, and a source region.
Infineon Technologies Austria Ag


04/07/16
20160099157 

Barc-assisted process for planar recessing or removing of variable-height layers


The present disclosure provides a method of manufacturing an integrated circuit device in some embodiments. In the method, a semiconductor substrate is processed through a series of operations to form a topographically variable surface over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


04/07/16
20160099153 

Split-gate non-volatile memory (nvm) cell and method therefor


A split gate memory device includes a semiconductor substrate and a select gate over the substrate. The select gate has a bottom portion and a top portion over the bottom portion, wherein the top portion has a top sidewall and the bottom portion has a bottom sidewall, and wherein the bottom sidewall extends beyond the top sidewall.
Freescale Semiconductor, Inc.


04/07/16
20160099151 

Etching process


A method includes providing a semiconductor substrate; forming a doping oxide layer on the semiconductor substrate; forming a patterning layer on the doping oxide layer, the patterning layer leaving exposed regions of the doping oxide layer; performing a sputtering process to the substrate; and after the sputtering process, performing a wet etching process to the semiconductor substrate to remove the doping oxide layer from the exposed regions.. .
Taiwan Semiconductor Manufacturing Compnay, Ltd.


04/07/16
20160099149 

Method for manufacturing semiconductor substrate


A method for manufacturing a semiconductor substrate. An impurity diffusion ingredient can be diffused well and uniformly from a coating film into a semiconductor substrate by forming a coating film having a thickness of not more than 30 nm on a surface of a semiconductor substrate with a diffusion agent composition containing an impurity diffusion ingredient and a silicon compound that can be hydrolyzed to produce a silanol group..
Tokyo Ohka Kogyo Co., Ltd.


04/07/16
20160099067 

Non-volatile split gate memory device and a operating same


A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns.
Silicon Storage Technology, Inc.


04/07/16
20160098321 

Efficient memory architecture for low density parity check decoding


A low density parity check (ldpc) decoder integrated on a single semiconductor substrate may comprise one or more arrays of first-type memory cells and one or more arrays of second-type memory cells. The ldpc decoder may be configured to store intrinsic messages in the array of first-type cells and to store extrinsic messages in the array of second-type cells.
Maxlinear, Inc.


04/07/16
20160096978 

Composition for forming a coating type bpsg film, substrate, and patterning process


A composition for forming a coating type bpsg film, containing one or more silicic acid skeletal structures represented by formula (1), one or more phosphoric acid skeletal structures represented by formula (2), one or more boric acid skeletal structures represented by formula (3), and one or more silicon skeletal structures represented by formula (4), wherein the composition contains a coupling between units in formula (4). The composition is capable of forming a bpsg film that has excellent adhesiveness in fine patterning, can be easily wet etched by a removing liquid which does not cause damage to a semiconductor substrate and a coating type organic film or a cvd film mainly consisting of carbon which is required in the patterning process, can maintain the peelability even after dry etching, and can suppress generation of particles by forming it in the coating process..
Shin-etsu Chemical Co., Ltd.


04/07/16
20160096977 

Composition for forming a coating type silicon-containing film, substrate, and patterning process


A composition for forming a coating type silicon-containing film, containing one or more silicic acid skeletal structures represented by the formula (1) and one or more silicon skeletal structures represented by the formula (2), wherein the composition contains a coupling between units shown in the formula (2). There can be provided a composition capable of forming a silicon-containing film that has excellent adhesiveness in fine patterning, and can be easily wet etched by a removing liquid which does not cause damage to a semiconductor substrate and a coating type organic film or a cvd film mainly of carbon which is required in the patterning process..
Shin-etsu Chemical Co., Ltd.


03/31/16
20160094182 

Semiconductor circuit, oscillator, electronic apparatus, and moving object


A semiconductor circuit includes an oscillation circuit; an output circuit that receives a first oscillation signal from the oscillation circuit and outputs a second oscillation signal; a dc circuit that receives a voltage based on a power supply voltage and outputs at least one of a dc voltage and a dc current; and a semiconductor substrate on which the oscillation circuit, the output circuit, and the dc circuit are formed. In a plan view of the semiconductor substrate, the dc circuit is disposed between the oscillation circuit and the output circuit..
Seiko Epson Corporation


03/31/16
20160093835 

Semiconductor device and manufacturing same


A fet is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction..
Semiconductor Energy Laboratory Co., Ltd.


03/31/16
20160093819 

Fringing field assisted dielectrophoresis assembly of carbon nanotubes


A method of arranging at least one carbon nanotube on a semiconductor substrate includes depositing the at least one carbon nanotube on a dielectric layer of the semiconductor device. The method further includes arranging the at least one carbon nanotube on the dielectric layer in response to applying a voltage potential to an electrically conductive electrode of the semiconductor device, and applying a ground potential to an electrically conductive semiconductor layer of the semiconductor device..
International Business Machines Corporation


03/31/16
20160093763 

Damage free laser patterning of transparent layers for forming doped regions on a solar cell substrate


The laser patterning methods utilizing a laser absorbent hard mask in combination with wet etching to form patterned solar cell doped regions which may further improve cell efficiency by completely avoiding laser ablation of an underlying semiconductor substrate associated with ablation of an overlying transparent passivation layer.. .
Solexel, Inc.


03/31/16
20160093758 

Solar cell


A solar cell includes a photoelectric conversion unit, where a first conductive-type layer and a second conductive-type layer are arranged alternately on a main surface of the semiconductor substrate, and an electrode layer provided on the first conductive-type layer and the second conductive-type layer. The photoelectric conversion unit has a plurality of sub-cells.
Panasonic Intellectual Property Management Co., Ltd.


03/31/16
20160093754 

Solar cell


A solar cell includes: a semiconductor substrate of one conductivity type; a first semiconductor layer of the one conductivity type on the semiconductor substrate; a second semiconductor layer of the other conductivity type on the semiconductor substrate; an insulation layer between the first and second semiconductor layers in an area where the first and second semiconductor layers layer overlap each other; a first region where the first semiconductor layer is joined to the semiconductor substrate; a second region where the second semiconductor layer is joined to the semiconductor substrate; and a third region, which is a part of the first region, where the insulation layer is provided. The first region includes first finger sections and a first busbar section.
Panasonic Intellectual Property Management Co., Ltd.


03/31/16
20160093752 

Solar cell and solar cell panel including the same


A solar cell is disclosed. The disclosed solar cell includes a semiconductor substrate, a conductive region disposed in or on the semiconductor substrate, and an electrode including a plurality of finger lines connected to the conductive region, and formed to extend in a first direction while being parallel, and 6 or more bus bar lines formed to extend in a second direction crossing the first direction.
Lg Electronics Inc.


03/31/16
20160093739 

Finfet semiconductor device with isolated channel regions


A finfet device includes a fin structure positioned in the channel region of the device and a gate structure positioned above the fin structure, wherein the fin structure includes a portion of a semiconductor substrate and an epi semiconductor material positioned vertically above the portion of the semiconductor substrate. Sidewall spacers are positioned adjacent the gate structure and a fin cavity is positioned in source/drain regions of the device, wherein the fin structure has edges in a gate width direction that are substantially self-aligned with the sidewall spacers and the semiconductor substrate defines the bottom of the fin cavity.
Globalfoundries Inc.


03/31/16
20160093736 

Semiconductor device structure and forming the same


A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


03/31/16
20160093731 

Method of manufacturing a semiconductor device and semiconductor device


A method of manufacturing a semiconductor device including a transistor comprises forming field plate trenches in a main surface of a semiconductor substrate, a drift zone being defined between adjacent field plate trenches, forming a field dielectric layer in the field plate trenches, thereafter, forming gate trenches in the main surface of the semiconductor substrate, a channel region being defined between adjacent gate trenches, and forming a conductive material in at least some of the field plate trenches and in at least some of the gate trenches. The method further comprising forming a source region and forming a drain region in the main surface of the semiconductor substrate..
Infineon Technologies Ag


03/31/16
20160093727 

Finfet with reduced capacitance


A structure including a plurality of fins etched from a semiconductor substrate, a gate electrode above and perpendicular to the plurality of fins, a pair of sidewall spacers disposed on opposing sides of the gate electrode, a gap fill material above the semiconductor substrate and between the plurality of fins, the gap fill material is directly below the gate electrode and directly below the pair of sidewall spacers, wherein the gate electrode separates the gap fill material from each of the plurality of fins, and an epitaxially grown region above a portion of the plurality of fins not covered by the gate electrode, the epi region separates the gap fill material from each of the plurality of fins.. .
International Business Machines Corporation


03/31/16
20160093718 

Semiconductor structures and fabrication method thereof


A method is provided for fabricating transistors. The method includes providing a semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


03/31/16
20160093713 

Semiconductor devices with replacement gate structures


A transistor device includes a semiconductor substrate and a gate structure positioned above a surface of the semiconductor substrate. The gate structure includes a high-k gate insulation layer positioned above the surface of the semiconductor substrate and at least one work-function adjusting layer of material positioned above the high-k gate insulation layer, wherein an upper surface of the at least one work-function adjusting layer of material has a stepped profile when viewed in cross-section taken in a gate-width direction of the transistor device.
Globalfoundries Inc.


03/31/16
20160093710 

Semiconductor device and forming the same


A semiconductor device includes a junction region on both sides of a trench in a semiconductor substrate, a first gate electrode with a first workfunction buried in the trench, and a second gate electrode formed of a polycide layer having a second workfunction overlapping with the junction region at an upper part of the first gate electrode.. .
Sk Hynix Inc.


03/31/16
20160093707 

Method of manufacturing non volatile memory device


A non-volatile memory device includes a semiconductor substrate, a well region situated on the semiconductor substrate, a floating gate situated on the well region, a floating gate channel region, a control gate situated on both sides of the floating gate, a control gate channel region, and an ion implantation area for regulating a program threshold voltage integrally formed between an area underneath of the floating gate and the control gate and a foreside of the well region, wherein a doping concentration of the ion implantation area for regulating a program threshold voltage is greater than a doping concentration of the well region. Therefore, the non-volatile memory device of examples integrally forms an ion implantation area for regulating a program threshold voltage irrespective of a channel region of a floating gate and a control gate so as to guarantee durability of a non-volatile memory device..
Magnachip Semiconductor, Ltd.


03/31/16
20160093706 

Method of forming a transistor, patterning a substrate, and transistor


A method of forming a transistor having a gate electrode includes forming a sacrificial layer over a semiconductor substrate, forming a patterning layer over the sacrificial layer, patterning the patterning layer to form patterned structures, forming spacers adjacent to sidewalls of the patterned structures, removing the patterned structures, etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate, thereby forming trenches in the semiconductor substrate, and filling a conductive material in the trenches in the semiconductor substrate to form the gate electrode.. .
Infineon Technologies Ag


03/31/16
20160093700 

Double aspect ratio trapping


A semiconductor structure is provided by a process in which two aspect ratio trapping processes are employed. The structure includes a semiconductor substrate portion of a first semiconductor material having a first lattice constant.
International Business Machines Corporation


03/31/16
20160093693 

Methods for forming vertical semiconductor pillars


A method for forming a semiconductor device includes providing a semiconductor structure, which includes a semiconductor substrate and a first mask layer on the substrate. The first mask layer is used to form a plurality of first trenches that extends into the substrate and extends laterally in a first direction and do not intersect each other.
Semiconductor Manufacturing International (shanghai) Corporation


03/31/16
20160093692 

Finfet semiconductor devices with replacement gate structures


A device includes first and second fins defined in a semiconductor substrate and a raised isolation post structure positioned between the first and second fins, wherein an upper surface of the raised isolation post structure is at a level that is approximately equal to or greater than a level corresponding to an upper surface of each of the first and second fins. A first space is defined by a sidewall of the first fin and a first sidewall of the raised isolation post structure, a second space is defined by a sidewall of the second fin and a second sidewall of the raised isolation post structure, and a gate structure is positioned around a portion of each of the first and second fins and around a portion of the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces..
Globalfoundries Inc.


03/31/16
20160093675 

Image sensor and electronic device including the same


An image sensor including a semiconductor substrate integrated with a plurality of photo-sensing devices and a nanopattern layer on the semiconductor substrate, the nanopattern layer having a plurality of nanopatterns, wherein a single nanopattern of the plurality of nanopatterns corresponds to a single photo-sensing device in the plurality of photo-sensing devices.. .
Samsung Electronics Co., Ltd.


03/31/16
20160093666 

Optoelectronic device and manufacturing same


The invention relates to an optoelectronic device (50) including: a semiconductor substrate (14) doped with a first conductivity type; semiconductor contact pads (54) or a semiconductor layer, in contact with a surface of the substrate, doped with a second conductivity type opposite to the first type; conical or frusto-conical wired semiconductor elements (26), doped with the first conductivity type, each element being in contact with one of the contact pads or with the layer; light-emitting semiconductor portions (30), each portion at least partially covering one of the semiconductor elements; and a circuit (s) for polarising the contact pads (54) or the layer. The contact pads or the layer are selected among: aluminium nitride, boron nitride, silicon carbide, magnesium nitride, gallium and magnesium nitride, or a combination of same and the nitride compounds thereof..
Commissariat A L'energie Atomique Et Aux Energies Alternatives


03/31/16
20160093660 

Semiconductor apparatus and manufacturing semiconductor apparatus


A semiconductor apparatus includes: an mos type field effect transistor formed on a semiconductor substrate and having a first gate electrode set at a predetermined impurity concentration; and a charge modulation device formed on the semiconductor substrate and having a second gate electrode set at a predetermined impurity concentration lower than the impurity concentration of the first gate electrode.. .
C/o Sony Corporation


03/31/16
20160093659 

Solid-state image pickup device, manufacturing solid-state image pickup device, and electronic apparatus


There is provided a solid-state image pickup device including: a semiconductor substrate (21); a photodiode (11a, 11b) formed in the semiconductor substrate; a transistor (10) having a gate electrode (14) part or all of which is embedded in the semiconductor substrate, the transistor being configured to read a signal electric charge from the photodiode via the gate electrode; and an electric charge transfer layer (13) provided between the gate electrode and the photodiode.. .
Sony Corporation


03/31/16
20160093633 

Semiconductor memory device and manufacturing method thereof


A semiconductor memory device includes a plurality of memory cell transistors that are formed above a semiconductor substrate and are connected to each other in series, first and second selection transistors formed respectively on either side of the memory cell transistors above the semiconductor substrate, a source line contact formed adjacent the first selection transistor and having a bottom thereof in contact with the semiconductor substrate, and a bit line contact formed adjacent the second selection transistor and having a bottom thereof in contact with the semiconductor substrate at a position higher than the bottom of the source line contact.. .
Kabushiki Kaisha Toshiba


03/31/16
20160093627 

Semiconductor device and manufacturing the same


A semiconductor device includes: a semiconductor substrate; a ferroelectric capacitor above the semiconductor substrate; a first guard ring around the ferroelectric capacitor above the semiconductor substrate. The ferroelectric capacitor includes a bottom electrode, a capacitor insulating film and a top electrode.
Fujitsu Semiconductor Limited


03/31/16
20160093623 

Two-transistor sram semiconductor structure and methods of fabrication


A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


03/31/16
20160093622 

Cross-coupled thyristor sram semiconductor structures and methods of fabrication


A memory cell based upon thyristors for an sram integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


03/31/16
20160093621 

Memory devices including one-time programmable memory cells


A memory device including one-time programmable memory cells has a semiconductor substrate with a write region and a read region, a write gate provided on the write region, a read gate provided on the read region, first and second junction patterns provided at both sides of the read gate, and insulating dielectric patterns interposed between the write and read gates and the semiconductor substrate. The read region may have a different conductivity type from the first and second junction patterns, and the write region may have the same conductivity type as the first and second junction patterns..

03/31/16
20160093618 

Single source/drain epitaxy for co-integrating nfet semiconductor fins and pfet semiconductor fins


A plurality of gate structures are formed straddling nfet semiconductor fins and pfet semiconductor fins which extend upwards from a surface of a semiconductor substrate. A boron-doped silicon germanium alloy material is epitaxially grown from exposed surfaces of both the nfet semiconductor fins and the pfet semiconductor fins not protected by the gate structures.
International Business Machines Corporation


03/31/16
20160093609 

Method of making an integrated switchable capacitive device


A method is provided for forming an integrated circuit chip with a variable capacitor disposed in a metallization. A back end of line metallization is formed over the semiconductor substrate.
Stmicroelectronics (rousset) Sas


03/31/16
20160093607 

Six-transistor sram semiconductor structures and methods of fabrication


A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


03/31/16
20160093597 

Package and making the same


A package structure includes a substrate having a first bond pad layer. A silicon bridge layer having one or more redistribution layers therein.
Taiwan Semiconductor Manufacturing Company, Ltd.


03/31/16
20160093592 

Wafer level integration of passive devices


A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate.
Apple Inc.


03/31/16
20160093583 

Bond pad with micro-protrusions for direct metallic bonding


A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (tsv) extending through the semiconductor substrate, and a copper pad electrically connected to the tsv and having a coupling side.
Micron Technology, Inc.


03/31/16
20160093567 

System, apparatus, and interconnection in a substrate


A semiconductor substrate according to some examples of the disclosure may include a substrate with a cavity in a top surface of the substrate, a plurality of cavity interconnections embedded below a bottom surface of the cavity and extending to a bottom surface of the substrate, and a plurality of side interconnections to either side of the cavity extending from the top surface of the substrate to the bottom surface of the substrate. Each of the plurality of side interconnections may include an electrically conductive stop etch layer in the same horizontal plane as the bottom of the cavity..
Qualcomm Incorporated


03/31/16
20160093555 

Method of manufacturing a semiconductor integrated circuit device


The tsv technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when tsv is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process.
Renesas Electronics Corporation


03/31/16
20160093542 

Method of manufacturing semiconductor device and semiconductor manufacturing apparatus


A method of manufacturing a semiconductor device includes forming a film along a surface of a semiconductor substrate in a first state having a first surface area by supplying a reaction gas at a first flow rate. The method further includes detecting a transition from the first state to a second state having a second surface area different from the first surface area.
Kabushiki Kaisha Toshiba


03/31/16
20160093539 

Modification processing device, modification monitoring device and modification processing method


There is provided a technique for easily inspecting the modification state of a film in a semiconductor substrate. A modification processing device modifies a film by irradiating a semiconductor substrate with pulsed light emitted from a light irradiation part.
Osaka University


03/31/16
20160093529 

Method of manufacturing a semiconductor device having a cell field portion and a contact area


A semiconductor device is manufactured at least partially in a semiconductor substrate. The substrate has first and second opposing main surfaces.
Infineon Technologies Austria Ag


03/31/16
20160093509 

Semiconductor device and forming the same


A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate..
Sk Hynix Inc.


03/31/16
20160093499 

Method of manufacturing semiconductor device


To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate.
Renesas Electronics Corporation


03/31/16
20160093484 

Methods of forming and using materials containing silicon and nitrogen


Some embodiments include methods utilizing atomic layer deposition to form material containing silicon and nitrogen (e.g., silicon nitride). The atomic layer deposition uses sii4 as one precursor and uses a nitrogen-containing material as another precursor.
Micron Technology, Inc.


03/31/16
20160093369 

Write assist sram circuits and methods of operation


A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


03/31/16
20160093368 

Six-transistor sram circuits and methods of operation


A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


03/31/16
20160093367 

Cross-coupled thyristor sram circuits and methods of operation


A memory cell based upon thyristors for an sram integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


03/31/16
20160093362 

Two-transistor sram circuit and methods of fabrication


A two-transistor memory cell based upon a thyristor for an sram integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of mos and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation.
Kilopass Technology, Inc.


03/31/16
20160090292 

Method to improve cantilever process performance


A method of manufacturing a cantilever structure includes providing a semiconductor substrate, forming a recess in the semiconductor substrate, forming a sacrificial layer in the recess, forming a cantilever structure layer on the semiconductor substrate and the sacrificial layer, performing an etching process to remove a portion of the cantilever structure layer until a surface of the sacrificial layer is exposed to form a cantilever structure and an opening, and removing a portion of the sacrificial layer to form a void below the cantilever structure so that the cantilever structure is suspended in the void. The cantilever structure thus formed has good morphological properties to ensure that the cantilever structure is free of residues at the bottom and has excellent suspension even if the width of the cantilever structure is relatively large..
Semiconductor Manufacturing International (shanghai) Corporation


03/24/16
20160088253 

Image sensor device, image processing device and manufacturing image sensor device


According to one embodiment, an image sensor device includes a sensor array on a semiconductor substrate, the sensor array including blocks, each of the blocks including a pixel and outputting a signal of the pixel; a first insulating layer on the sensor array; semiconductor layers on the first insulating layer; analog-digital converting circuits on the semiconductor layers, the analog-digital converting circuits corresponding to the blocks and processing the signal; a second insulating layer on the first insulating layer and the analog-digital converting circuits; and interconnect portions electrically connecting the analog-digital converting circuits to the blocks via a region between the semiconductor layers, the interconnect portions extending across the first insulating layer and the second insulating layer.. .
Kabushiki Kaisha Toshiba


03/24/16
20160088245 

Solid-state imaging device, electronic apparatus, lens control method, and imaging module


There is provided a solid-state imaging device including: a pixel region that includes a plurality of pixels arranged in a two-dimensional matrix pattern. Some of the plurality of pixels are configured to be phase difference detection pixels that include a photoelectric conversion section disposed on a semiconductor substrate and a light blocking film disposed above a portion of the photoelectric conversion section.
Sony Corporation


03/24/16
20160087588 

Packaged rf amplifier devices with grounded isolation structures and methods of manufacture thereof


An embodiment of a packaged rf amplifier device includes a device substrate, a transistor die coupled to the device substrate, and an isolation structure coupled to the transistor die. The transistor die has a top die surface, a bottom die surface, a semiconductor substrate, first and second transistors formed in the semiconductor substrate, a conductive structure at the top die surface and positioned between the first and second transistors, and a low resistance path that extends vertically through the semiconductor substrate between the conductive structure and the bottom die surface.
Freescale Semiconductor, Inc.


03/24/16
20160087577 

Flexible solar cells comprising thick and thin absorber regions


A solar cell includes a p-type semiconductor substrate including a plurality of thin absorption regions and a plurality of thick absorption regions. The plurality of thin absorption regions and the plurality of thick absorption regions are coplanar on a bottom side thereof.
King Abdulaziz City For Science And Technology


03/24/16
20160087529 

Bootstrap circuit


A bootstrap circuit includes an n-channel mos transistor including: a first n-type semiconductor layer formed on a surface of a p-type semiconductor substrate and electrically connected to a bootstrap capacitor; a p-type semiconductor layer formed on a surface of the first n-type semiconductor layer; a second n-type semiconductor layer formed on a surface of the p-type semiconductor layer; a first electrode electrically connected to the p-type semiconductor layer; a second electrode electrically connected to the second n-type semiconductor layer; and a power-source terminal connected to each of the first electrode and the second electrode for supplying a power-source voltage thereto, the n-channel mos transistor supplying power to the bootstrap capacitor, and a current limiting element connected between the power-source terminal and the first electrode.. .
Sanken Electric Co., Ltd.


03/24/16
20160087408 

Quantum-cascade laser


A quantum cascade laser is configured with a semiconductor substrate and first and second active layers provided in series on the substrate. A unit laminate structure of the first active layer has a subband level structure having an emission upper level and an emission lower level, and is configured so as to be able to generate light of a first frequency ω1, a unit laminate structure of the second active layer has a subband level structure having a first emission upper level, a second emission upper level, and a plurality of emission lower levels, and is configured so as to be able to generate light of a second frequency ω2, and light of a difference frequency ω is generated by difference frequency generation from the light of the first frequency ω1 and the light of the second frequency ω2..
Hamamatsu Photonics K.k.


03/24/16
20160087123 

Solar cell and manufacturing the same


A solar cell and a method for manufacturing the same are discussed. The solar cell includes a semiconductor substrate, a first doped region of a first conductive type, a second doped region of a second conductive type opposite the first conductive type, a back passivation layer having contact holes exposing a portion of each of the first and second doped regions, a first electrode formed on the first doped region exposed through the contact holes, a second electrode formed on the second doped region exposed through the contact holes, an alignment mark formed at one surface of the semiconductor substrate, and a textured surface that is formed at a light receiving surface of the semiconductor substrate opposite the one surface of the semiconductor substrate in which the first and second doped regions are formed..
Lg Electronics Inc.


03/24/16
20160087110 

Semiconductor device


An n−-type semiconductor substrate (1) includes an active region and a terminal region disposed outside the active region. A p+-type anode layer (2) is formed in a portion of an upper surface of the n−-type semiconductor substrate (1) in the active region.
Miitsubishi Electric Corporation


03/24/16
20160087094 

Semiconductor device


A semiconductor device includes a semiconductor substrate having a main cell region and a sense cell region. A separation trench separating a main second semiconductor region from a sense second semiconductor region is provided in an upper surface of the semiconductor substrate.
Toyota Jidosha Kabushiki Kaisha


03/24/16
20160087093 

Mos device with island region


A semiconductor device formed on a semiconductor substrate, comprising: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; an active region; and an island region under the contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer. The active region comprises: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body; and an active region contact electrode disposed within the active region contact trench..
Alpha And Omega Semiconductor Limited


03/24/16
20160087078 

Mos devices having epitaxy regions with reduced facets


An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage.
Taiwan Semiconductor Manufacturing Company, Ltd.


03/24/16
20160087077 

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device includes preparing a semiconductor substrate, forming a gate electrode on the semiconductor substrate via a gate insulating film, forming a laminated film on the semiconductor substrate so as to cover the gate electrode, the laminated film including a first insulating film and a second insulating film on the first insulating film, forming a first side wall insulating film, formed of the laminated film, on a side wall of the gate electrode by etching back the laminated film, epitaxially growing an epitaxial semiconductor layer on a portion of the semiconductor substrate which is not covered with the gate electrode and the first side wall insulating film but is exposed, forming an oxide film on a surface of the epitaxial semiconductor layer by oxidizing the surface of the epitaxial semiconductor layer, and removing the second insulating film forming the first side wall insulating film.. .
Renesas Electronics Corporation


03/24/16
20160087074 

Metalization of a field effect power transistor


A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically conducting semiconductor substrate is described. The lateral semiconductor layers have different band gaps such that a two-dimensional electron gas can form in their semiconductor depletion layer.
Infineon Technologies Austria Ag


03/24/16
20160087072 

Dummy bit line mos capacitor and device using the same


A mos capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The mos capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure.
Sk Hynix Inc.


03/24/16
20160087050 

Power semiconductor devices having a semi-insulating field plate


A power semiconductor device comprising a first metal electrode and a second metal electrode formed on a first substrate surface of a semiconductor substrate, a semi-insulating field plate interconnecting said first and second metal electrodes, and an insulating oxide layer extending between said first and second metal electrodes and between said field plate and said semiconductor substrate, wherein said semi-insulating field plate is a titanium nitride (tin) field plate.. .
Hkg Technologies Limited


03/24/16
20160087048 

Gallium nitride semiconductor substrate with semiconductor film formed therein


A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more signal crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis.
Sumitomo Electric Industries, Ltd.


03/24/16
20160087040 

Methods for high-k metal gate cmos with sic and sige source/drain regions


A method of manufacturing a semiconductor device includes forming a pmos region and an nmos region in a semiconductor substrate, forming dummy gate structures in the pmos and nmos regions, and forming a gate hard mask layer overlying top portions and sidewalls of the dummy gate structures. The method includes forming silicon carbon regions embedded in the semiconductor substrate on both sides of the dummy gate structure in the nmos region, removing the hard mask layer on top of the dummy gate in the nmos region, and forming silicon germanium regions embedded in the semiconductor substrate on both sides of the dummy gate structure in the pmos region.
Semiconductor Manufacturing International (shanghai) Corporation


03/24/16
20160087035 

Semiconductor device and fabricating the same


A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer..

03/24/16
20160087031 

Semiconductor device and manufacturing same


A semiconductor device including a terminal region that can suppress a resist collapse in manufacturing and effectively relieve a concentration of electric fields and a method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor element formed in a semiconductor substrate made of a silicon carbide semiconductor of a first conductivity type and a plurality of ring-shaped regions of a second conductivity type formed in the semiconductor substrate while surrounding the semiconductor element in plan view.
Mitsubishi Electric Corporation


03/24/16
20160087028 

Semiconductor device and manufacturing same


One semiconductor device includes a capacitor having a lower electrode which is arranged on a semiconductor substrate, a second protective film, a dielectric film which has a defect that extends in the film thickness direction from an upper surface that faces the second protective film, a third protective film which has at least a defect filling film that is formed of an insulating body filling the defect, a first protective film which covers the dielectric film and the third protective film, and an upper electrode which covers the first protective film.. .
Ps4 Luxco S.a.r.l.


03/24/16
20160087025 

Semiconductor device and manufacturing the same


A semiconductor device includes a semiconductor substrate having a main surface; a first coil formed on the main surface; a first insulating film formed over the first coil and having a first main surface; a second insulating film formed on the first main surface of the first insulating film and having a second main surface; and a second coil formed on the second main surface of the second insulating film, wherein the first main surface of the first insulating film has a first area on which the second insulating film is formed, and has a second area without the first area in a plan view, and wherein the second insulating film is surrounded with the second area in the plane view.. .
Renesas Electronics Corporation


03/24/16
20160087012 

Image sensor and electronic device including the same


An image sensor includes a semiconductor substrate integrated with at least a photo-sensing device, a plurality of first electrodes disposed on the semiconductor substrate, an organic photoelectric conversion layer disposed on the first electrodes, and a second electrode disposed on the organic photoelectric conversion layer. The first electrodes include a light-transmitting electrode and a metal layer interposed between the semiconductor substrate and the light-transmitting electrode.
Samsung Electronics Co., Ltd.


03/24/16
20160087008 

Method for producing semiconductor device


A method for producing a semiconductor device includes forming a fin-shaped semiconductor layer on a semiconductor substrate and a first pillar-shaped semiconductor layer, a first dummy gate layer and a second pillar-shaped semiconductor layer, and a second dummy gate layer. Third and fourth dummy gate layers are formed on sidewalls of the first dummy layer gate, the first pillar-shaped semiconductor layer, the second dummy gate layer and the second pillar-shaped semiconductor layer.
Unisantis Electronics Singapore Pte. Ltd.


03/24/16
20160087006 

3-dimensional stack memory device


A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides of the gate electrode in each of the plurality of active regions, a bit line formed on one side of the drain to be connected to the drain, a resistive device layer formed on one side of the source to be connected to the source, and a source line connected to the resistive device layer. The source is configured of an impurity region having a first conductivity type, and the drain is configured of an impurity region having a second conductivity type different from the first conductivity type..
Sk Hynix Inc.


03/24/16
20160087002 

Solid state imaging device and fabricating the same


According to one embodiment, a semiconductor substrate has a first region in which a photoelectric conversion device is provided, a second region which is provided around the first region, and in which a device is provided, and a third region which is provided between the first region and the second region, and in which the photoelectric conversion device is provided. A first interlayer insulating film is provided on the first region and the third region.
Kabushiki Kaisha Toshiba


03/24/16
20160086993 

Solid-state image pickup apparatus, and image pickup system using solid-state image pickup apparatus


A solid-state image pickup apparatus includes a photoelectric conversion unit, a charge storage unit, and a floating diffusion unit, all disposed on a semiconductor substrate. The solid-state image pickup apparatus further includes a first gate electrode disposed on the semiconductor substrate and extending between the photoelectric conversion unit and charge storage unit, and a second gate electrode disposed on the semiconductor substrate and extending between the charge storage unit and the floating diffusion unit.
Canon Kabushiki Kaisha


03/24/16
20160086985 

Pixel for cmos image sensor and image sensor including the same


A pixel of a complementary metal-oxide-semiconductor (cmos) image sensor includes a semiconductor substrate having a first surface and a third surface formed by removing part of the semiconductor substrate from a second surface, an active region which is formed between the first surface and the third surface and which contains a photoelectric conversion element generating charges in response to light incident on the substrate at the third surface, and a trench-type isolation region formed from either of the first and third surfaces to isolate the active region from an adjacent active region. The trench-type isolation region is filled with first material in a process that leaves a void in the material, the void is filled or partially filled with second material, and then a layer of third material is formed over the resulting structure composed of the first and second materials..
Samsung Electronics Co., Ltd.


03/24/16
20160086984 

Approach for reducing pixel pitch using vertical transfer gates and implant isolation regions


An active pixel sensor (aps) with a vertical transfer gate and a pixel transistor (e.g., a transfer transistor, a source follower transistor, a reset transistor, or a row select transistor) electrically isolated by an implant isolation region is provided. A semiconductor substrate has a photodetector buried therein.
Taiwan Semiconductor Manufacturing Co., Ltd.


03/24/16
20160086961 

Method of manufacturing a semiconductor device


An improvement is achieved in the performance of a semiconductor device. Over a first insulating film formed over a main surface of a semiconductor substrate located in a memory formation region and having an internal charge storage portion and over a second insulating film formed over the main surface of the semiconductor substrate located in a main circuit formation region, a conductive film is formed.
Renesas Electronics Corporation


03/24/16
20160086957 

Semiconductor device with buried bit line and fabricating the same


A method for fabricating a semiconductor device includes etching semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.. .
Sk Hynix Inc.


03/24/16
20160086956 

Semiconductor device and manufacturing semiconductor device


One semiconductor device has a groove formed on one surface of a semiconductor substrate, a gate electrode formed on the lower part of the groove with a gate insulation film interposed there between, a side wall insulation film made of a nitride film formed on the inner wall of the groove above the gate electrode, and an embedded insulation film formed in the groove enclosed by the side wall insulation film above the gate electrode. The side wall insulation film is shaped so that the width increases closer the bottom part of the groove..
Ps5 Luxco S.a.r.l.


03/24/16
20160086944 

Replacement metal gate


A semiconductor structure which includes: a fin on a semiconductor substrate; and a gate structure wrapped around the fin. The gate structure includes: spaced apart spacers to form an opening, the spacers being perpendicular to the fin, the spacers having a height with respect to the fin; a high-k dielectric material in the opening and over the fin, the high-k dielectric material in contact with the spacers and a bottom of the opening; a work function metal in contact with the high-k dielectric material that is over the fin, the spacers and the bottom of the opening, the work function metal that is in contact with the high-k dielectric material having a height in the opening that is less than the height of the spacers, the high-k dielectric material and the work function metal only partially filling the opening; and a metal completely filling the opening..
International Business Machines Corporation


03/24/16
20160086941 

Semiconductor device


A semiconductor device includes: an fet structure that is formed next to a looped trench on a semiconductor substrate and that has an n+ emitter region and an n− drain region facing each other in the depth direction of the looped trench across a p-type base region; a p-type floating region formed on the side of the looped trench opposite to the fet structure; and an emitter connecting part that is electrically connected to the n+ emitter region and a trench gate provided in the same trench, the emitter connecting part and the trench gate being insulated from each other by the looped trench. The trench gate faces the fet structure, and the emitter connecting part faces the p-type floating region, across an insulating film..
Rohm Co., Ltd.


03/24/16
20160086940 

Stack mom capacitor structure for cis


A semiconductor device includes a semiconductor substrate, an interlayer dielectric layer on the semiconductor substrate, a capacitor on the interlayer dielectric layer, and a pn-junction diode in the semiconductor substrate and below the capacitor. The pn-junction diode includes a p-type ion implanted region and an n-well located below the p-type ion implanted region and completely surrounding the p-type ion implanted region.
Semiconductor Manufacturing International (shanghai) Corporation


03/24/16
20160086926 

Pass-through interconnect structure for microelectronic dies and associated systems and methods


Pass-through interconnect structures for microelectronic dies and associated systems and methods are disclosed herein. In one embodiment, a microelectronic die assembly includes a support substrate, a first microelectronic die positioned at least partially over the support substrate, and a second microelectronic die positioned at least partially over the first die.
Micron Technology, Inc.


03/24/16
20160086902 

Semiconductor package structure and manufacturing method thereof


A semiconductor package structure includes a semiconductor substrate including a plurality of through substrate vias (tsv) extending from a first surface to a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface; a plurality of conductive bumps on the second surface and connected to a corresponding tsv; a polymeric layer on the second surface and surrounding a lower portion of a corresponding conductive bump. The polymeric layer includes a first portion configured as a blanket covering a periphery region of the semiconductor substrate; and a second portion in a core region of the semiconductor substrate and configured as a plurality of isolated belts, wherein each of the isolated belts surrounds a corresponding conductive bump..
Taiwan Semiconductor Manufacturing Company Ltd.


03/24/16
20160086896 

Chip package and forming the same


An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface.
Xintec Inc.


03/24/16
20160086886 

Nanowire compatible e-fuse


An e-fuse is provided in one area of a semiconductor substrate. The e-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion..
Globalfoundries Inc.


03/24/16
20160086880 

Copper wire through silicon via connection


A semiconductor device includes a semiconductor substrate having opposing first and second main surfaces, a via (tsv) extending from the first main surface of the substrate to the second main surface of the substrate, first electrical connectors formed near the first main surface and second electrical connectors formed near the second main surface. There are insulated bond wires, each extending through the via and having a first end bonded to a respective one of the first electrical connectors and a second end bonded to a respective one of the second electrical connectors.
Freescale Semiconductor, Inc.


03/24/16
20160086847 

Method of electrodepositing gold on a copper seed layer to form a gold metallization structure


An electrically conductive barrier layer is formed on a semiconductor substrate such that the barrier layer covers a first device terminal. A seed layer is formed on the barrier layer.
Infineon Technologies Austria Ag


03/24/16
20160086813 

Method of fabricating semiconductor device


A method of fabricating a semiconductor device includes forming an active region in a semiconductor substrate, forming a plurality of dummy gates on the active region, the plurality of dummy gates having a gate mask disposed thereon, forming an interlayer insulating layer on the gate mask, and performing a one-time chemical mechanical polishing (cmp) process by using a slurry composition capable of polishing the interlayer insulating layer and the gate mask until top surfaces of the dummy gates are exposed.. .
Samsung Electronics Co., Ltd.


03/24/16
20160086804 

Method of manufacturing semiconductor device


First, a first resist mask for forming an n+ emitter region is formed on the front surface of an n− semiconductor substrate. The first resist mask is left on the surface of the gate electrode.
Fuji Electric Co., Ltd.


03/24/16
20160086795 

Internal plasma grid applications for semiconductor fabrication


The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers.
Lam Research Corporation


03/24/16
20160086660 

Electromechanical nonvolatile memory


A semiconductor device includes an insulating layer on a semiconductor substrate, a bit line including tial and disposed on the insulating layer, a sidewall layer disposed on opposite sides of the bit line, a word line including tin and disposed on the sidewall layer intersecting the bit line, and an air gap in an intersection region of the bit line and the word line. The thickness of the sidewall layer is larger than the thickness of the bit line.
Semiconductor Manufacturing International (shanghai) Corporation




Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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