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Semiconductor Substrate patents



      
           
This page is updated frequently with new Semiconductor Substrate-related patent applications. Subscribe to the Semiconductor Substrate RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Substrate RSS RSS


Diode circuit and dc to dc converter

Toshiba

Diode circuit and dc to dc converter

Method of inspecting semiconductor device, method of fabricating semiconductor device, and inspection tool

Toshiba

Method of inspecting semiconductor device, method of fabricating semiconductor device, and inspection tool

Method of inspecting semiconductor device, method of fabricating semiconductor device, and inspection tool

Globalfoundries

Gate length independent silicon-on-nothing (son) scheme for bulk finfets

Date/App# patent app List of recent Semiconductor Substrate-related patents
02/26/15
20150056813
 Self-assembled monolayer for pattern formation patent thumbnailnew patent Self-assembled monolayer for pattern formation
The present disclosure relates to a method of forming a pattern on a semiconductor substrate. One or more layers are formed over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.
02/26/15
20150056807
 Semiconductor device and manufacturing method thereof patent thumbnailnew patent Semiconductor device and manufacturing method thereof
According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires.. .
Kabushiki Kaisha Toshiba
02/26/15
20150056795
 Method of manufacturing semiconductor device patent thumbnailnew patent Method of manufacturing semiconductor device
A method of manufacturing a semiconductor devices includes providing a semiconductor substrate that includes a channel region. The method includes forming a gate electrode material film including a stepped portion on the channel region.
Samsung Electronics Co., Ltd
02/26/15
20150056791
 Depression filling method and processing apparatus patent thumbnailnew patent Depression filling method and processing apparatus
A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor substrate is provided. The depression penetrating the insulating film is configured so as to extend to the semiconductor substrate.
Tokyo Electron Limited
02/26/15
20150056785
 Substrate dividing method patent thumbnailnew patent Substrate dividing method
A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness..
Hamamatsu Photonics K.k.
02/26/15
20150056781
 Gate length independent silicon-on-nothing (son) scheme for bulk finfets patent thumbnailnew patent Gate length independent silicon-on-nothing (son) scheme for bulk finfets
Methods for fabricating integrated circuits and finfet transistors on bulk substrates with active channel regions isolated from the substrate with an insulator are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material and extends in a longitudinal direction from a first end to a second end.
Globalfoundries, Inc.
02/26/15
20150056779
 Semiconductor device and  manufacturing the same patent thumbnailnew patent Semiconductor device and manufacturing the same
A semiconductor device includes a semiconductor substrate divided into a cell region and a peripheral circuit region defined in a first direction, wherein the peripheral circuit region is divided into a first region and a second region defined in a second direction substantially orthogonal to the first direction; gate lines formed over the semiconductor substrate in the cell region and arranged in the second direction; and a capacitor including lower electrodes over the semiconductor substrate, a dielectric layer and an upper electrode, wherein the lower electrodes in the first and second regions, separated from each other in the first direction and coupled to each other in the first region, the dielectric layer is formed along surfaces of the lower electrodes in the second region, and the upper electrode is formed over the dielectric layer.. .
Sk Hynix Inc.
02/26/15
20150056776
 Method of manufacturing mos-type semiconductor device patent thumbnailnew patent Method of manufacturing mos-type semiconductor device
A method of manufacturing a mos-type semiconductor device capable of increasing the thickness of a gate oxide film and obtaining high gate withstanding power and reduced switching loss without increasing a gate threshold voltage vth is provided. A p-type well region is selectively formed on one principle surface of a semiconductor substrate having an n-type low impurity concentration layer by using an oxide film as a mask.
Fuji Electric Co., Ltd.
02/26/15
20150056771
 Method for fabricating semiconductor device with super junction structure patent thumbnailnew patent Method for fabricating semiconductor device with super junction structure
A semiconductor device with a super-junction structure is provided, including: a semiconductor substrate having a first conductivity type; an epitaxial layer having the first conductivity type formed over the semiconductor substrate; a first doping region having the first conductive type formed in a portion of the epitaxial layer; a second doping region having a second conductivity type formed in a portion of the of the epitaxial layer; a third doping region having the second conductivity type formed in a portion of the of the epitaxial layer, wherein the doping region partially comprises doped polysilicon materials having the second conductivity type; a gate dielectric layer formed over the epitaxial layer, partially overlying the well region; and a gate electrode formed over a portion of the gate dielectric layer.. .
Vanguard International Semiconductor Corporation
02/26/15
20150056768
 Method for fabricating semiconductor device patent thumbnailnew patent Method for fabricating semiconductor device
A method of fabricating a semiconductor device is disclosed. The method includes the steps of: sequentially forming agate dielectric layer and a first gate layer on a semiconductor substrate, wherein the gate dielectric layer is between the first gate layer and the semiconductor substrate; forming at least an opening in the first gate layer; forming a first dielectric layer conformally on the semiconductor substrate wherein the first dielectric layer covers the first gate layer; and forming a second gate layer filling the opening and overlapping the first gate layer..
United Microelectronics Corp.
02/26/15
20150056765
new patent

Semiconductor device and manufacturing the same


A semiconductor device which provides compactness and enhanced drain withstand voltage. The semiconductor device includes: a gate electrode; a source electrode spaced from the gate electrode; a drain electrode located opposite to the source electrode with respect to the gate electrode in a plan view and spaced from the gate electrode; at least one field plate electrode located between the gate and drain electrodes in a plan view, provided over the semiconductor substrate through an insulating film and spaced from the gate electrode, source electrode and drain electrode; and at least one field plate contact provided in the insulating film, coupling the field plate electrode to the semiconductor substrate.
Renesas Electronics Corporation
02/26/15
20150056763
new patent

Selective deposition of diamond in thermal vias


A method for fabricating a semiconductor device, such as a gan high electron mobility transistor (hemt) device, including etching a thermal via into a back-side of a semiconductor substrate and depositing a diamond nucleation seed layer across the back-side of the substrate. The method further includes coating the diamond nucleation with a mask layer and removing mask material outside of the thermal via on the planar portions of the back-side of the substrate.
02/26/15
20150056760
new patent

Semiconductor device having diffusion barrier to reduce back channel leakage


A semiconductor-on-insulator (soi) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer.
International Business Machines Corporation
02/26/15
20150056751
new patent

Die edge sealing structures and related fabrication methods


Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region.
02/26/15
20150056743
new patent

Manufacturing solar cell


A manufacturing method of a solar cell includes a protection-film forming step of forming a protection film on one surface side of a semiconductor substrate, a first processing step of forming a plurality of first openings having a shape close to a desired opening shape and a size smaller than a target opening size in the protection film by a method having relatively high processing efficiency, a second processing step of forming second openings in the protection film by expanding the first openings up to the target opening size by a method having relatively high processing accuracy, and an etching step of forming an asperity structure having the a concave portion in an inverted pyramid shape on the one surface side of the semiconductor substrate by performing anisotropic wet etching on the semiconductor substrate in a region under the second openings via the second openings.. .
Mitsubishi Electric Corporation
02/26/15
20150056742
new patent

Annealing for damage free laser processing for high efficiency solar cells


Annealing solutions providing damage-free laser patterning utilizing auxiliary heating to anneal laser damaged ablation regions are provided herein. Ablation spots on an underlying semiconductor substrate are annealed during or after pulsed laser ablation patterning of overlying transparent passivation layers..
Solexel, Inc.
02/26/15
20150056727
new patent

Method of inspecting semiconductor device, fabricating semiconductor device, and inspection tool


A method of inspecting a semiconductor device includes attaching an inspection tool on a back surface of a semiconductor substrate including the semiconductor device, the inspection tool including a sheet and a holding frame, the sheet being larger than the semiconductor substrate and being provided with an opening in a center portion of the sheet, the opening being smaller than the semiconductor substrate, the holding frame holding an outer periphery of the sheet, and a supporting substrate being attached on a front surface of the semiconductor substrate, removing the supporting substrate attached on the front surface of the semiconductor substrate, and measuring electrical characteristics of the semiconductor device.. .
Kabushiki Kaisha Toshiba
02/26/15
20150055401
new patent

Semiconductor devices including dual gate electrode structures and related methods


A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region.
Samsung Electronics Co., Ltd.
02/26/15
20150055394
new patent

Semiconductor device


A semiconductor device comprises a semiconductor substrate including first and second regions that have different conductivity types from each other; an isolation region extending continuously over the first and second regions and having a shallow trench covered by a field insulator; first and second active regions placed in respective first and second regions and being each surrounded by the isolation region; a gate electrode disposed in a lower portion of a gate groove that extends continuously from the first active region to the second active region via the isolation region, the gate groove being shallower than the shallow trench; a cap insulating film disposed in an upper portion of the gate groove so as to cover an upper surface of the gate electrode; first and second transistors placed in respective first and second active regions and sharing the gate electrode; and a logic circuit including the first and second transistors connected in series.. .
Micron Technology, Inc.
02/26/15
20150054995
new patent

Organic pixels including organic photodiode, manufacturing methods thereof, and apparatuses including the same


Provided is an organic pixel, which includes a semiconductor substrate including a pixel circuit, an interconnection layer having a first contact and a first electrode formed on a semiconductor substrate, and an organic photo-diode formed on the interconnection layer. For example, the organic photo-diode includes an insulation layer formed on the first electrode, a second electrode and a photo-electric conversion region formed between the first contact, the insulation layer and the second electrode.
02/26/15
20150054142
new patent

Wafer surface conditioning for stability in fab environment


Hydroxyl moieties are formed on a surface over a semiconductor substrate. The surfaces are silylized to replace the hydroxyl groups with silyl ether groups, the silyl ether groups being of the form: —osir1r2r3, where r1, r2, and r3 are each hydrocarbyl groups comprising at least one carbon atom.
Taiwan Semiconductor Manufacturing Co., Ltd.
02/26/15
20150054141
new patent

Method for forming integrated circuits on a strained semiconductor substrate


An electronic circuit on a strained semiconductor substrate, includes: electronic components on a first surface of a semiconductor substrate; and at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.. .
Stmicroelectronics (crolles 2) Sas
02/26/15
20150054137
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes a semiconductor substrate having opposed main and back surfaces; first and second electrodes in a device region of the substrate, and spaced apart from each other; a metal film on the main surface and joined to the second electrode; an air gap between part of the main surface and the metal film, enveloping the first electrode, and having an opening; a cured resin closing the opening; a liquid repellent film increasing contact angle of the resin, relative to contact angles on the substrate and the metal film; a first metal film joined to the metal film, covering the metal film and the cured resin, and joined to an outer peripheral region of the substrate, at a periphery of the device region; and a second metal film on the back surface and connected to the first electrode through a via hole penetrating the substrate.. .
Mitsubishi Electric Corporation
02/26/15
20150054129
new patent

Semiconductor device with pads of enhanced moisture blocking ability


A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film..
Fujitsu Semiconductor Limited
02/26/15
20150054123
new patent

Self-aligned emitter-base region


Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor.
International Business Machines Corporation
02/26/15
20150054121
new patent

Finfet formed over dielectric


A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels.
International Business Machines Corporation
02/26/15
20150054118
new patent

Semiconductor device


A semiconductor device includes a semiconductor substrate, and a field plate portion formed on a front surface of a non-cell region. The non-cell region includes a plurality of flr layers.
Toyota Jidosha Kabushiki Kaisha
02/26/15
20150054116
new patent

High voltage device having schottky diode


A high voltage device having schottky diode includes a semiconductor substrate, a schottky diode formed on the semiconductor substrate, at least a first doped region having a first conductive type formed in the semiconductor substrate and under the schottky diode, and a control gate positioned on the semiconductor substrate. The control gate covers a portion of the schottky diode and the first doped region positioned on the semiconductor substrate..
United Microelectronics Corp.
02/26/15
20150054105
new patent

Solid-state imaging device and electronic apparatus


A solid-state imaging device which includes, a photoelectric conversion film provided on a second surface side which is the opposite side to a first surface on which a wiring layer of a semiconductor substrate is formed, performs photoelectric conversion with respect to light in a predetermined wavelength region, and transmits light in other wavelength regions; and a photoelectric conversion layer which is provided in the semiconductor substrate, and performs the photoelectric conversion with respect to light in other wavelength regions which has transmitted the photoelectric conversion film, in which input light is incident from the second surface side with respect to the photoelectric conversion film and the photoelectric conversion layer.. .
Sony Corporation
02/26/15
20150054086
new patent

Semiconductor device and manufacturing same


A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.. .
Micron Technology, Inc.
02/26/15
20150054077
new patent

Finfet formed over dielectric


A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels.
International Business Machines Corporation
02/26/15
20150054071
new patent

High voltage semiconductor device and fabricating the same


A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein.
Vanguard International Semiconductor Corporation
02/26/15
20150054069
new patent

Semiconductor device including a mosfet


A semiconductor device for use in a power supply circuit has first and second mosfets. The source-drain path of one of the mosfets are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths.
Renesas Electronics Corporation
02/26/15
20150054066
new patent

Semiconductor devices including vertical transistors, electronic systems including the same and methods of manufacturing the same


The semiconductor device includes word lines on a semiconductor substrate, common gates connected to each of the word lines and vertically disposed in the semiconductor substrate, buried bit lines intersecting the word lines at a non-right angle in a plan view, and a pair of vertical transistors sharing each of the common gates. The pair of vertical transistors is disposed on both sides of one of the word lines.
Sk Hynix Inc.
02/26/15
20150054062
new patent

Power semiconductor device and fabrication method thereof


A power semiconductor device includes a cell region on a semiconductor substrate, at least a transistor device in the cell region, a peripheral termination region encompassing the cell region, a plurality of epitaxial islands arranged around the cell region, and a grid type epitaxial layer in the peripheral termination region. The grid type epitaxial layer separates the plurality of epitaxial islands from one another..
Anpec Electronics Corporation
02/26/15
20150054061
new patent

Protection diode


A protection diode includes a semiconductor substrate; a gate side well region of a first conductivity type in the semiconductor substrate; a grounding side well region of the first conductivity type in the semiconductor substrate and joined to the gate side well region; a gate side diffusion region of a second conductivity type in the semiconductor substrate and joined to the gate side well region; a grounding side diffusion region of the second conductivity type in the semiconductor substrate, separated from the gate side diffusion region, and joined to the grounding side well region; a gate side electrode connected between a gate of a transistor and the gate side diffusion region; and a grounding electrode connected to the grounding side diffusion region. Dopant impurity concentration in the grounding side well region is lower than dopant impurity concentration in the gate side well region..
Mitsubishi Electric Corporation
02/26/15
20150054060
new patent

Protection diode


A protection diode includes: a semiconductor substrate; a well region of a first conductivity type in the semiconductor substrate; a gate side diffusion region of a second conductivity type in the semiconductor substrate and joined to the well region; a grounding side diffusion region of the second conductivity type in the semiconductor substrate, separated from the gate side diffusion region, and joined to the well region; a gate side electrode connected between a gate of a transistor and the gate side diffusion region; a grounding electrode connected to the grounding side diffusion region; and an insulating film on the well region. The grounding electrode extends to the well region on the insulating film..
Mitsubishi Electric Corporation
02/26/15
20150054051
new patent

Semiconductor device and fabrication method


Semiconductor devices and fabrication methods are provided. A semiconductor substrate includes a first region and a second region.
Semiconductor Manufacturing International (beijing) Corporation
02/26/15
20150054047
new patent

Semiconductor memory device and manufacturing the same


According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a silicon film provided on the first insulating film, a metal silicide film provided on the silicon film, a second insulating film provided on the metal silicide film, and an electrode provided on the second insulating film.. .
Kabushiki Kaisha Toshiba
02/26/15
20150054045
new patent

Semiconductor device and manufacturing the same


Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a cg shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the cg shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region..
Renesas Electronics Corporation
02/26/15
20150054042
new patent

Photodiode of high quantum efficiency


A photodiode includes at least one central pad arranged on a light-receiving surface of a photodiode semiconductor substrate. The pad is made of a first material and includes lateral sidewalls surrounded by a spacer made of a second material having a different optical index than the first material.
Commissariat A L'energie Atomique Et Aux Energies Alternatives
02/26/15
20150054039
new patent

Finfet device with channel epitaxial region


The present disclosure relates to a fin field effect transistor (finfet) device having epitaxial enhancement structures, and an associated method of fabrication. In some embodiments, the finfet device has a semiconductor substrate having a plurality of isolation regions overlying the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.
02/26/15
20150054029
new patent

Metal gate stack having taalcn layer


An integrated circuit device includes a semiconductor substrate; and a gate stack disposed over the semiconductor substrate. The gate stack further includes a gate dielectric layer disposed over the semiconductor substrate; a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer comprises tantalum aluminum carbon nitride (taalcn); a work function layer disposed over the multi-function blocking/wetting layer; and a conductive layer disposed over the work function layer..
Taiwan Semiconductor Manufacturing Company, Ltd.
02/26/15
20150054024
new patent

Semiconductor device


A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.. .
Mitsubishi Electric Corporation
02/26/15
20150053999
new patent

Wide bandgap insulated gate semiconductor device


A wide bandgap insulated gate semiconductor device includes a semiconductor substrate made of semiconductor having a bandgap wider than silicon; n− drift layer over the semiconductor substrate; p-channel regions selectively disposed over the drift layer; n+ semiconductor regions selectively disposed in respective surfaces in the channel regions; a plurality of p+ base regions in contact with bottoms of the respective channel regions; a protruding drift layer portion that is n-type region interposed between the p-channel regions and the p+ base regions thereunder; a gate electrode formed, through a gate insulating film, on the protruding drift layer portion and on respective surfaces of the p-channel regions; a source electrode in contact with the n+ semiconductor regions in the channel regions; and a p+ floating region inside the protruding drift layer portion, having side faces respectively facing side faces of the second conductivity type base regions, wherein respective gaps between the p+ base regions and the p+ floating region defined by the respective side faces have a wide portion and a narrow portion.. .
Fuji Electric Co., Ltd.
02/26/15
20150053994
new patent

Diode circuit and dc to dc converter


A diode circuit includes a switching element having a first terminal and a second terminal. The switching element includes a control electrode for controlling electrical conductance between the first and second terminals.
Kabushiki Kaisha Toshiba
02/26/15
20150053982
new patent

Heterojunction bipolar transistors with reduced parasitic capacitance


Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate.
International Business Machines Corporation
02/26/15
20150053924
new patent

Spad photodiode of high quantum efficiency


A spad-type photodiode has a semiconductor substrate with a light-receiving surface. A lattice formed of interlaced strips made of a first material covers the light receiving surface.
Commissariat A L'energie Atomique Et Aux Energies Alternatives
02/26/15
20150053256
new patent

Solar cells and methods of making thereof


A method of making a solar cell may include depositing in a first pattern a first ink comprising a first dopant on a back surface of a substrate that is doped with a second dopant being of the same type as the first dopant; then, depositing a second ink comprising a set of undoped semiconductor nanoparticles over the first ink on the back surface of the substrate in a second pattern matching the first pattern; then, heating the semiconductor substrate so that the first dopant diffuses into the substrate and thereby, forms a third pattern of localized doped regions; then, exposing the substrate to a doping ambient comprising a third dopant being of the opposite type to the second dopant, thereby forming a doped semiconductor layer on the front surface and a portion of the back surface not covered by the second ink, and then, removing the deposited ink.. .
E I Du Pont De Nemours And Company
02/26/15
20150053003
new patent

Method and fabricating electrostatic capacitance-type acceleration sensor and electrostatic capacitance-type acceleration sensor


In a method for fabricating an electrostatic capacitance-type acceleration sensor having a capacitor which electrostatic capacitance between a movable electrode and a fixed electrode changes according to the displacement of the movable electrode, the method includes: a step of forming a groove on at least one of the surface of an insulative substrate and the surface of a semiconductor substrate; a step of forming a hole in the semiconductor substrate so as to penetrate the semiconductor substrate at a position communicating with a passage formed by the groove; and a step of forming an electrode extraction hole in the insulative substrate so as to penetrate the insulative substrate, at a position communicating with the passage formed by the groove.. .
Japan Oil, Gas And Metals National Corporation
02/19/15
20150050862

Polishing composition and method using said polishing composition to manufacture compound semiconductor substrate


A polishing composition contains abrasive grains and water. 50% by mass or more of the abrasive grains consists of particles a having particle sizes between 40 nm and 80 nm inclusive, and 10% by mass or more of the abrasive grains consists of particles b having particle sizes between 150 nm and 300 nm inclusive.
Fujimi Incorporated
02/19/15
20150050817

Method of preventing voltage breakdown at a surface of a semiconductor substrate of a superjunction semiconductor device


A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main surface. The at least one column of the second conductivity type has a first sidewall surface proximate the at least one column of the first conductivity type and a second sidewall surface opposed to the first sidewall surface.
Icemos Technology Ltd.
02/19/15
20150050802

Method of manufacturing a nonvolatile memory device


A method of manufacturing a nonvolatile memory device comprises forming a gate insulating layer and a first conductive layer over a semiconductor substrate that defines a first area in which selection lines will be formed and a second area in which word lines will be formed, performing an etch process to lower a height of the first conductive layer in the first area, forming a dielectric layer and a second conductive layer over the first conductive layer with a height that is different from the height of the first conductive layer, and performing a gate patterning process to form the selection lines and the word lines.. .
Sk Hynix Inc.
02/19/15
20150050798

Production a semiconductor device


A method for producing a semiconductor device includes providing a semiconductor substrate having a first conductivity type; implanting protons through a rear surface of the semiconductor substrate of the first conductivity type; and forming a first semiconductor region of the first conductivity type in the semiconductor substrate by performing an annealing process in an annealing furnace in a hydrogen atmosphere having a volume concentration of hydrogen that is equal to or greater than 0.5% and less than 4.65%, the first semiconductor region having a higher impurity concentration than that of the semiconductor substrate after the implantation step. The method reduces crystal defects in the generation of donors during proton implantation and improves the rate of change into a donor..
Fuji Electric Co., Ltd.
02/19/15
20150050792

Extra narrow diffusion break for 3d finfet technologies


Methods for forming a narrow isolation region are disclosed. The narrow isolation region may serve as an extra narrow diffusion break, suitable for use in 3d finfet technologies.
Globalfoundries Inc.
02/19/15
20150050791

Method for manufacturing rectifier with vertical mos structure


A method for manufacturing a rectifier with a vertical mos structure is provided. A first multi-trench structure and a first mask layer are formed at a first side of the semiconductor substrate.
Pfc Device Corp.
02/19/15
20150050768

Laser diode device and manufacturing laser diode device


A laser diode device includes: a semiconductor substrate including a semi-polar surface, the semiconductor substrate being formed of a hexagonal iii-nitride semiconductor; an epitaxial layer including a light emitting layer, the epitaxial layer being formed on the semi-polar surface of the semiconductor substrate, and the epitaxial layer including a ridge section; a first electrode formed on a top surface of the ridge section; an insulating layer covering the epitaxial layer in an adjacent region of the ridge section and a side surface of the ridge section, the insulating layer covering part or all of side surfaces of the first electrode continuously from the epitaxial layer; a pad electrode formed to cover a top surface of the first electrode and the insulating layer, the pad electrode being electrically connected to the first electrode; and a second electrode formed on a surface, of the semiconductor substrate, opposite to the semi-polar surface.. .
Sumitomo Electric Industries, Ltd.
02/19/15
20150049982

Passive optical diode on semiconductor substrate


An optical device includes a first optical cavity, a second optical cavity, a first light guide and a second light guide. Each of the first and second optical cavities is formed on a semiconductor substrate, and is configured to store light.
Purdue Research Foundation
02/19/15
20150048510

Semiconductor device


A semiconductor device includes a semiconductor substrate and a metal film formed on the semiconductor substrate. The metal film includes a ni base and a material having condensation energy higher than that of ni.
Denso Corporation
02/19/15
20150048507

Conductive diffusion barrier structure for ohmic contacts


An integrated circuit includes a p-type region formed beneath a surface of a semiconductor substrate, and an n-type region formed beneath the surface of the semiconductor substrate. The n-type region meets the p-type region at a p-n junction.
Taiwan Semiconductor Manufacturing Co. Ltd.
02/19/15
20150048503

Packages with interposers and methods for forming the same


A package structure includes an interposer, a die over and bonded to the interposer, and a printed circuit board (pcb) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.
02/19/15
20150048486

Spatial semiconductor structure and fabricating the same


A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided.
United Microelectronics Corporation
02/19/15
20150048484

Passivation for group iii-v semiconductor devices having a plated metal layer over an interlayer dielectric layer


A semiconductor device that includes a group iii-v semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ild) layer. The ild layer defines a via that extends through it to the first metal layer.
Avago Technologies General Ip (singapore) Pte. Ltd.
02/19/15
20150048475

Semiconductor structures with shallow trench isolations


A method is disclosed that includes the operations outlined below. An insulating material is disposed within a plurality of trenches on a semiconductor substrate and over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.
02/19/15
20150048473

Image pickup element and image pickup device


An image pickup element includes: a photoelectric conversion film provided on a semiconductor substrate and including a chalcopyrite-based compound; an insulating film provided on a light incident surface side of the photoelectric conversion film; and a conductive film provided on the insulating film.. .
Sony Corporation
02/19/15
20150048468

Solid-state imaging device


According to one embodiment, a solid-state imaging device includes a first light-receiving portion and a first light guide layer. The first light-receiving portion is formed in the surface of a semiconductor substrate.
Kabushiki Kaisha Toshiba
02/19/15
20150048459

Device for detecting a laser attack in an integrated circuit chip


A device for detecting a laser attack made on an integrated circuit chip comprises a bipolar transistor of a first type formed in a semiconductor substrate, that bipolar transistor comprising a parasitic bipolar transistor of a second type. A buried region, forming the base of the parasitic bipolar transistor, operates as a detector of the variations in current flowing caused by impingement of laser light on the substrate..
Stmicroelectronics (rousset) Sas
02/19/15
20150048458

Semiconductor device and manufacturing method thereof


Provided are a semiconductor device and a method for manufacturing the same. The method may include: forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high k gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high k gate dielectric layer; implanting dopant to the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack comprising the first metal gate layer, the high k gate dielectric layer, and the interfacial oxide layer..
Institute Of Microelectronics, Chinese Academy Of Sciences
02/19/15
20150048451

Semiconductor device and manufacturing the same


A semiconductor device and a manufacturing method for the same are provided. The semiconductor substrate includes a gate structure, a first doped contact region, a second doped contact region and a well doped region.
Macronix International Co., Ltd.
02/19/15
20150048449

High voltage semiconductor device and forming the same


A high voltage semiconductor device includes a semiconductor substrate having a first conductivity type and including a low voltage part and a high voltage part, a semiconductor layer having a second conductivity type on the semiconductor substrate, a body region having the first conductivity type on the semiconductor layer, a first buried layer having the second conductivity type between the high voltage part of the semiconductor substrate and the semiconductor layer, and a second buried layer having the first conductivity type and having sidewalls inside sidewalls of the first buried layer and extending deeper into the substrate than the first buried layer. A surface of the body region adjacent the substrate is spaced apart from a surface of the second buried layer remote from the substrate such that a portion of the semiconductor layer is disposed therebetween..
Samsung Electronics Co., Ltd.
02/19/15
20150048447

Lateral diffusion metal oxide semiconductor (ldmos) device with tapered drift electrode


A lateral diffusion metal oxide semiconductor (ldmos) comprises a semiconductor substrate having an sti structure in a top surface of the substrate, a drift region below the sti structure, and a source region and a drain region on opposite sides of the sti structure. A gate conductor is on the substrate over a gap between the sti structure and the source region, and partially overlaps the drift region.
International Business Machines Corporation
02/19/15
20150048444

Semiconductor devices including bit line contact plug and peripheral transistor


A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode..
02/19/15
20150048436

Nonvolatile semiconductor memory device and production the same


According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate; an element isolation insulating film buried in the semiconductor substrate so as to isolate adjacent element; a memory cell having a first insulating film and a charge accumulation film; a second insulating film formed on the charge accumulation films of the memory cells and the element isolation insulating film; and a control electrode film formed on the second insulating film. An upper surface of the element isolation insulating film is lower than an upper surface of the charge accumulation film, the second insulating film is provided with a cell upper portion on the charge accumulation film and an inter-cell portion on the element isolation insulating film, and a dielectric constant of the cell upper portion is lower than a dielectric constant of the inter-cell portion..
Kabushiki Kaisha Toshiba
02/19/15
20150048431

Method for forming a contact on a semiconductor substrate and semiconductor device


A method for forming a contact on a semiconductor substrate includes: applying a metal to an exposed partial area of an outer side of the semiconductor substrate and/or of a layer applied to the semiconductor substrate, the partial area being surrounded by at least one edge region of an insulating layer, and the at least one edge region of the insulating layer being at least partially covered by the metal; heating the semiconductor substrate, whereby the metal which is applied to the exposed partial area reacts with at least one semiconductor material of the partial area to form a semiconductor-metal material as the end material or a further processing material of the at least one contact; and etching using an etching material having a higher etching rate for the metal than for the semiconductor-metal material.. .
Robert Bosch Gmbh
02/19/15
20150048417

Germanium barrier embedded in mos devices


An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is in the opening, wherein the first silicon germanium region has a first germanium percentage.
Taiwan Semiconductor Manufacturing Company, Ltd.
02/19/15
20150048378

Image pickup element and image pickup device


Provided is an image pickup element that includes a photoelectric conversion section provided on a semiconductor substrate and including a chalcopyrite-based compound. The photoelectric conversion section has a band gap that is relatively wide on a light incident surface side..
Sony Corporation
02/19/15
20150048317

Solid state imaging device


According to one embodiment, solid state imaging device includes, a semiconductor substrate and a photoelectric conversion unit formed in the semiconductor substrate or above the semiconductor substrate. Further, the photoelectric conversion unit is provided with a first photoelectric conversion unit and a second photoelectric conversion unit.
Kabushiki Kaisha Toshiba
02/19/15
20150048313

Strip-shaped gate tunneling field effect transistor with double-diffusion and a preparation method thereof


The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor with double-diffusion and a preparation method thereof, belonging to a field of cmos field effect transistor logic device and the circuit. The tunneling field effect transistor includes a semiconductor substrate, a highly-doped source region, a highly-doped drain region, a double-diffusion source region, a gate dielectric layer, and a control gate, wherein the control gate has a strip-shaped structure with a gate length greater than a gate width, and at one side thereof is connected to the highly-doped drain region and at the other side thereof extends laterally into the highly-doped source region; a region located below the control gate is a channel region; the gate width of the control gate is less than twice width of a source depletion layer; the double-diffusion region has the same doping region as the highly-doped source region and the double-diffusion region has the same doping type as the highly-doped drain region; and the channel region located below a portion of the control gate portion in the highly-doped source region has double-diffusion source doped impurities.
Peking University
02/19/15
20150048296

Semiconductor device having fin gate, resistive memory device including the same, and manufacturing the same


A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same. The semiconductor device includes an active pillar formed on a semiconductor substrate, the active pillar including an inner region and an outer region surrounding the inner region, and a fin gate overlapping an upper surface and a lateral surface of the active pillar.
Sk Hynix Inc.
02/19/15
20150048295

Semiconductor device having fin gate, resistive memory device including the same, and manufacturing the same


A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same are provided. The semiconductor device includes an active pillar formed on a semiconductor substrate, and including a first region and a second region surrounding at least one surface of the first region, and a fin gate extending to overlap an upper surface and a lateral surface of the active pillar.
Sk Hynix Inc.
02/19/15
20150048294

Variable resistive memory device including vertical channel pmos transistor and manufacturing the same


A semiconductor device having a vertical channel, a variable resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device having a vertical channel includes a vertical pillar formed on a semiconductor substrate and including an inner portion and an outer portion surrounding the inner portion, junction regions formed in the outer portion of the vertical pillar, and a gate formed to surround the vertical pillar.
Sk Hynix Inc.
02/19/15
20150048292

Semiconductor device having vertical channel, resistive memory device including the same, and manufacturing the same


A semiconductor device, a resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device includes a pillar extending substantially perpendicular from a semiconductor substrate, the pillar including an inner portion and an outer portion surrounding the inner portion.
Sk Hynix Inc.


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Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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