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Semiconductor Substrate patents



      

This page is updated frequently with new Semiconductor Substrate-related patent applications.




Date/App# patent app List of recent Semiconductor Substrate-related patents
05/19/16
20160143156 
 Reflow treating unit and substrate treating apparatus patent thumbnailReflow treating unit and substrate treating apparatus
Provided are a semiconductor substrate manufacturing apparatus and a substrate treating method, and more particularly, an apparatus and method for performing a reflow treating process on a semiconductor wafer. The apparatus treating apparatus includes a load port on which a carrier accommodating a substrate is seated, a substrate treating module including one reflow treating unit or a plurality of reflow treating units for performing a reflow process on the substrate, and a substrate transfer module including a transfer robot transferring the substrate between the load port and the substrate treating module, the substrate transfer module being disposed between the load port and the substrate treating module.
Semigear, Inc


05/19/16
20160143155 
 Reflow treating unit and substrate treating apparatus patent thumbnailReflow treating unit and substrate treating apparatus
Provided are a semiconductor substrate manufacturing apparatus and a substrate treating method, and more particularly, an apparatus and method for performing a reflow treating process on a semiconductor wafer. The apparatus treating apparatus includes a load port on which a carrier accommodating a substrate is seated, a substrate treating module including one reflow treating unit or a plurality of reflow treating units for performing a reflow process on the substrate, and a substrate transfer module including a transfer robot transferring the substrate between the load port and the substrate treating module, the substrate transfer module being disposed between the load port and the substrate treating module.
Semigear, Inc.


05/19/16
20160142630 
 Image sensor,  manufacturing the same, and image processing device having the image sensor patent thumbnailImage sensor, manufacturing the same, and image processing device having the image sensor
An image sensor comprising: a first layer having a plurality of groups of photodiodes formed in a semiconductor substrate, each group representing a 2×2 array of photodiodes, with 2 first pixels configured to detect light of a first wavelength and 2 second pixels configured to detect light of a second wavelength, each first pixel positioned adjacent to the second pixels; and a second layer overlapping the first layer, the second layer is organic, having a plurality of organic photodiodes configured to detect light of a third wavelength, each organic photodiode positioned to partially overlap 2 first photodiodes and 2 second photodiodes of the first layer.. .
Samsung Electronics Co., Ltd.


05/19/16
20160141890 
 Wireless power transfer - near field communication enabled communication device patent thumbnailWireless power transfer - near field communication enabled communication device
Various configurations and arrangements of various communication devices are disclosed. Various integrated circuits that form these communication devices can be fabricated onto one or more semiconductor substrates, chips, and/or dies using a high voltage semiconductor process, a low voltage semiconductor process, or any combination thereof.
Broadcom Corporation


05/19/16
20160141836 
 Monolithic nano-cavity light source on lattice mismatched semiconductor substrate patent thumbnailMonolithic nano-cavity light source on lattice mismatched semiconductor substrate
An optoelectronic light emission device is provided that includes a gain region of at least one type iii-v semiconductor layer that is present on a lattice mismatched semiconductor substrate. The gain region of the type iii-v semiconductor layer has a nanoscale area using nano-cavities.
International Business Machines Corporation


05/19/16
20160141448 
 Monolithic nano-cavity light source on lattice mismatched semiconductor substrate patent thumbnailMonolithic nano-cavity light source on lattice mismatched semiconductor substrate
An optoelectronic light emission device is provided that includes a gain region of at least one type iii-v semiconductor layer that is present on a lattice mismatched semiconductor substrate. The gain region of the type iii-v semiconductor layer has a nanoscale area using nano-cavities.
International Business Machines Corporation


05/19/16
20160141439 
 Light detection device patent thumbnailLight detection device
A semiconductor light detection element includes a plurality of avalanche photodiodes operating in geiger mode and formed in a semiconductor substrate, quenching resistors connected in series to the respective avalanche photodiodes and arranged on a first principal surface side of the semiconductor substrate, and a plurality of through-hole electrodes electrically connected to the quenching resistors and formed so as to penetrate the semiconductor substrate from the first principal surface side to a second principal surface side. A mounting substrate includes a plurality of electrodes arranged corresponding to the respective through-hole electrodes on a third principal surface side.
Hamamatsu Photonics K.k.


05/19/16
20160141427 
 Multi-channel field effect transistors using 2d-material patent thumbnailMulti-channel field effect transistors using 2d-material
A device includes a semiconductor substrate, a buried oxide over the substrate, a first transition metal dichalcogenide layer over the buried oxide, an insulator over the first transition metal dichalcogenide layer, and a second transition metal dichalcogenide layer over the insulator. A gate dielectric is over the second transition metal dichalcogenide layer, and a gate is over the gate dielectric..
National Taiwan University


05/19/16
20160141407 
 Semiconductor device and  manufacturing semiconductor device patent thumbnailSemiconductor device and manufacturing semiconductor device
A method of manufacturing a semiconductor device is provided, the method including forming a first gate member on a semiconductor substrate through a gate insulating film, forming a spacer on the first gate member, flattening a surface of the spacer, forming a first gate by partially etching the first gate member using the spacer as a mask, forming a second gate member so as to cover the first gate and the spacer having the flattened surface, forming a first insulating film on a surface of the second gate member, and forming a second gate by causing the second gate member to retreat while removing the first insulating film by etching.. .
Lapis Semiconductor Co., Ltd.


05/19/16
20160141402 
 Semiconductor device patent thumbnailSemiconductor device
A semiconductor substrate is provided with a first cell region, the first cell region including: an n-type emitter region; a p-type first top body region; an n-type first barrier region; an n-type first pillar region; and a p-type first bottom body region, the semiconductor substrate may further comprise: an n-type drift region; a p-type collector region; an n-type cathode region, the n-type first barrier region may include a first peak position where a peak of the n-type impurity density is present within a part linked to the n-type first pillar region, and a second peak position where a peak of the n-type impurity density is present within a part in contact with the gate insulating layer, and a depth of the first peak position from a front surface of the semiconductor substrate is different from a depth of the second peak position from the front surface of the semiconductor substrate.. .
Toyota Jidosha Kabushiki Kaisha


05/19/16
20160141399 

Method for forming a semiconductor device and a semiconductor device


A method for forming a semiconductor device comprises implanting a defined dose of protons into a semiconductor substrate and tempering the semiconductor substrate according to a defined temperature profile. At least one of the defined dose of protons and the defined temperature profile is selected depending on a carbon-related parameter indicating information on a carbon concentration within at least a part of the semiconductor substrate..
Infineon Technologies Ag


05/19/16
20160141393 

Meander resistor


A method includes forming a plurality of fins in a semiconductor substrate using a common patterning process. A conductive layer is formed above the plurality of fins.
Globalfoundries Inc.


05/19/16
20160141380 

Method for manufacturing a semiconductor device, and semiconductor device


A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a main surface and a gate electrode which is within a trench between neighboring semiconductor mesas. The gate electrode is electrically insulated from the neighboring semiconductor mesas by respective dielectric layers.
Infineon Technologies Austria Ag


05/19/16
20160141367 

Semiconductor devices including channel dopant layer


A semiconductor device includes a semiconductor substrate including a well dopant layer having a first conductivity type, a gate electrode on the well dopant layer, a channel dopant layer in the well dopant layer and spaced apart from a top surface of the semiconductor substrate, a channel region between the gate electrode and the channel dopant layer, and source/drain regions in the well dopant layer at both sides of the gate electrode. The channel dopant layer and the channel region have the first conductivity type.
Samsung Electronics Co., Ltd.


05/19/16
20160141361 

Nanowire mosfet with support structures for source and drain


Transistor devices and methods for forming transistor devices are provided. A transistor device includes a semiconductor substrate and a device layer.
Taiwan Semiconductor Manufacturing Company Limited


05/19/16
20160141360 

Iii-v semiconductor devices with selective oxidation


Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer..
International Business Machines Corporation


05/19/16
20160141358 

Apparatus and methods for transceiver interface overvoltage clamping


Apparatus and methods for transceiver interface overvoltage clamping are provided. In certain configurations, an interface device includes a first p-type well region and a second p-type well region in an n-type isolation structure.
Analog Devices, Inc.


05/19/16
20160141357 

Semiconductor device and method


A semiconductor device and a method of making the same. The device includes a semiconductor substrate including a body region having a first conductivity type.
Nxp B.v.


05/19/16
20160141356 

Semiconductor device


A semiconductor device includes: a first conductivity type semiconductor substrate; and a plurality of second conductivity type semiconductor regions, the respective second conductivity type semiconductor regions being embedded in a plurality of stripe shaped trenches formed in the semiconductor substrate so that the respective second conductivity type semiconductor regions are extended in the row direction or the column direction in parallel with a first principal surface of the semiconductor substrate and are spaced in a fixed gap mutually. The semiconductor substrate and the plurality of the semiconductor regions are depleted by a depletion layer extended in the direction in parallel to the first principal surface from a plurality of pn junction interfaces, and the respective pn junction interfaces are formed between the semiconductor substrate and the plurality of the semiconductor regions..
Rohm Co., Ltd.


05/19/16
20160141324 

Semiconductor image sensor module, manufacturing the same as well as camera and manufacturing the same


A semiconductor image sensor module 1 at least includes a semiconductor image sensor chip 2 having a transistor forming region on a first main surface of a semiconductor substrate and having a photoelectric conversion region with a light incident surface formed on a second main surface on the side opposite to the first main surface and an image signal processing chip 3 for processing image signals formed in the semiconductor image sensor chip 2, wherein a plurality of bump electrodes 15a are formed on a first main surface, a plurality of bump electrodes 15b are formed on the image signal processing chip 3, both the chips 2 and 3 are formed to be laminated through heat dissipating means 4 and the plurality of bump electrodes 15a of the semiconductor image sensor chip 2 and the plurality of bump electrodes 15b on the image signal processing chip 3 are electrically connected.. .
Sony Corporation


05/19/16
20160141316 

Low full-well capacity image sensor with high sensitivity


Image sensor pixels having low full-well capacity and high sensitivity for applications such as dis, qdis, single/multi bit qis. Some embodiments provide an image sensor pixel architecture, comprises a transfer gate, a floating diffusion region both formed on a first surface of a semiconductor substrate and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially or entirely beneath the transfer gate.
Dartmouth College


05/19/16
20160141303 

Semiconductor memory device


According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit..
Kabushiki Kaisha Toshiba


05/19/16
20160141298 

Sti recess method to embed nvm memory in hkmg replacement gate technology


The present disclosure relates to a structure and method for reducing contact over-etching and high contact resistance (rc) on an embedded flash memory hkmg integrated circuit. In one embodiment, an sti region underlying a memory contact pad region is recessed to make the sti surface substantially co-planar with the rest of the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


05/19/16
20160141289 

Semiconductor device and manufacturing same


To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate.
Renesas Electronics Corporation


05/19/16
20160141285 

Electrostatic discharge (esd) protection device


An electrostatic discharge (esd) protection device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. In addition, the esd protection device further includes a first doping region formed in a portion of the at least one portion of the semiconductor substrate separating the pair of first well regions, having a second conductivity type opposite to the first conductivity type.
Mediatek Inc.


05/19/16
20160141284 

Semiconductor device


A transistor (2) is provided on a semiconductor substrate (8). A temperature detection diode (4) for monitoring temperature of an upper surface of the semiconductor substrate (8) is provided on the semiconductor substrate (8).
Mitsubishi Electric Corporation


05/19/16
20160141280 

Device-embedded image sensor, and wafer-level fabricating same


A device-embedded image sensor includes an image sensor formed in a first semiconductor substrate; a top conductive pad formed on a top surface of the first semiconductor substrate; and a semiconductor device formed in a second semiconductor substrate bonded to a bottom surface of the first semiconductor substrate, the semiconductor device electrically connected to the top conductive pad. A method for fabricating a device-embedded image sensor from a cmos image sensor wafer assembly that includes an image sensor and a conductive pad.
Omnivision Technologies, Inc.


05/19/16
20160141267 

Semiconductor device, manufacturing semiconductor device, and electronic apparatus


There is provided a semiconductor device, including a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a bonding electrode formed on a surface of the interlayer insulating layer, and a metal film which covers an entire surface of a bonding surface including the interlayer insulating layer and the bonding electrode.. .
Sony Corporation


05/19/16
20160141261 

Ball amount process in the manufacturing of integrated circuit


An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a post-passivation interconnect (ppi) over the polymer layer. The ppi is electrically connected to the metal pad.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/19/16
20160141254 

Chip package and forming the same


An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.. .
Xintec Inc.


05/19/16
20160141252 

Methods of forming alignment marks and overlay marks on integrated circuit products employing finfet devices and the resulting alignment/overlay mark


A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to define an alignment/overlay mark trench. An alignment/overlay mark includes at least one insulating material positioned within the alignment/overlay mark trench.
Globalfoundries Inc.


05/19/16
20160141228 

Device connection through a buried oxide layer in a silicon on insulator wafer


An approach to forming a semiconductor structure for a semiconductor device with connections through a buried oxide layer in a silicon on insulator wafer. A buried oxide layer is formed on a semiconductor substrate and at least one semiconductor device is formed on the buried oxide layer.
International Business Machines Corporation


05/19/16
20160141226 

Device connection through a buried oxide layer in a silicon on insulator wafer


An approach to forming a semiconductor structure for a semiconductor device with connections through a buried oxide layer in a silicon on insulator wafer. A buried oxide layer is formed on a semiconductor substrate and at least one semiconductor device is formed on the buried oxide layer.
International Business Machines Corporation


05/19/16
20160141211 

Semiconductor device including power and logic devices and related fabrication methods


Semiconductor device structures and related fabrication methods are provided. An exemplary fabrication method involves forming a layer of gate electrode material overlying a semiconductor substrate, forming a layer of masking material overlying the gate electrode material, and patterning the layer of masking material to define a channel region within a well region in the semiconductor substrate that underlies the gate electrode material.

05/19/16
20160141208 

Method for processing a semiconductor substrate and a processing a semiconductor wafer


According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies.. .
Infineon Technologies Ag


05/19/16
20160141204 

Trench having thick dielectric selectively on bottom portion


A method of fabricating a semiconductor device includes etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from the top surface into the semiconductor substrate. A dielectric liner of a first dielectric material is formed on the bottom surface and sidewalls of the trench to line the trench.
Texas Instruments Incorporated


05/19/16
20160141188 

Internal plasma grid for semiconductor fabrication


The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers.
Lam Research Corporation


05/19/16
20160141171 

Photoresist pattern trimming methods


Provided are methods of trimming photoresist patterns. The methods involve coating a photoresist trimming composition over a photoresist pattern, wherein the trimming composition includes a matrix polymer, a thermal acid generator and a solvent, the trimming composition being free of cross-linking agents.
Rohm And Haas Electronic Materials Llc


05/19/16
20160141169 

Substrate backside texturing


Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized.
Tokyo Electron Limited


05/19/16
20160141003 

Semiconductor memory device


According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array disposed on the semiconductor substrate, a capacitor and a control circuit. The memory cell array includes a plurality of memory cells.
Kabushiki Kaisha Toshiba


05/19/16
20160139338 

Optical connector having waveguide and manufacturing same


An optical connector includes a semiconductor substrate, an epitaxial layer of photoelectric element, and a waveguide. The semiconductor substrate has a surface that includes a photoelectric element zone, a waveguide zone, and an optical fiber zone, and defines a receiving groove in the optical fiber zone extending through the optical fiber zone and connecting with the waveguide zone and configured for receiving an optical fiber.
Hon Hai Precision Industry Co., Ltd.


05/19/16
20160139335 

Semiconductor structure


A semiconductor structure is provided, the semiconductor structure comprising: a semiconductor substrate processed to comprise at least an optical aspect comprising at least a silicon photonics device and at least an electronic aspect comprising at least an electronic device; at least an interlayer dielectric layer provided on the semiconductor substrate, and at least an electrically interconnecting layer provided on the interlayer dielectric layer, wherein: the semiconductor structure further comprises at least a functional-oxide crystalline layer provided in relation to the interlayer dielectric layer before the interconnecting layer is provided on the interlayer dielectric layer, the functional-oxide crystalline layer comprising at least a functional-oxide material and is processed to comprise at least an active optical device, and the interlayer dielectric layer comprises a first surface and a second surface, the first surface being in common to at least a respective part of the optical aspect and the electronic aspect.. .
International Business Machines Corporation


05/19/16
20160138188 

Multizone control of lamps in a conical lamphead using pyrometers


A method and apparatus for processing a semiconductor substrate is described. The apparatus is a process chamber having an optically transparent upper dome and lower dome.
Applied Materials, Inc.


05/19/16
20160138160 

Reactive ultraviolet thermal processing of low dielectric constant materials


Various embodiments herein relate to methods and apparatus for preparing a low-k dielectric material on a semiconductor substrate. The dielectric material may include porogens distributed throughout a structural matrix.
Lam Research Corporation


05/12/16
20160133865 

Solid-state imaging element, production method thereof, and electronic device


A solid-state imaging element including a phase difference detection pixel pair that includes first (2pa) and second (2pb) phase difference detection pixels is provided. In particular, each phase difference detection pixel of the first and second phase difference detection pixels includes a first photoelectric conversion unit (52, 53b, 53c) arranged at an upper side of a semiconductor substrate (12) and a second photoelectric conversion unit (42, 43) arranged within the semiconductor substrate.
Sony Corporation


05/12/16
20160133792 

Semiconductor substrate and fabricating the same


A semiconductor substrate includes a substrate including a plurality of semispherical protrusions disposed at an interval on a first plane of the substrate, and a first semiconductor layer disposed on the first plane of the substrate.. .
Seoul Viosys Co., Ltd


05/12/16
20160133763 

Semiconductor device, manufacturing method thereof and imaging apparatus


A semiconductor device for converting incident light into an electric current includes a semiconductor substrate; an electrode embedded in the semiconductor substrate; an insulation film contacting the electrode in the semiconductor substrate; a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and a third semiconductor region of the first conductivity type, formed sequentially in a depth direction from a side of a front face of the semiconductor substrate; and a fourth semiconductor region of the second conductivity type contacting the insulation film and the second semiconductor region. An impurity concentration of the fourth semiconductor region is greater than an impurity concentration of the second semiconductor region..
Ricoh Company, Ltd


05/12/16
20160133753 

Semiconductor devices containing an epitaxial perovskite/doped strontium titanate structure


Semiconductor devices are provided such as, ferroelectric transistors and floating gate transistors, that include an epitaxial perovskite/doped strontium titanate structure formed above a surface of a semiconductor substrate. The epitaxial perovskite/doped strontium titanate structure includes a stack of, in any order, a doped strontium titanate and a perovskite type oxide..
International Business Machines Corporation


05/12/16
20160133748 

Semiconductor devices including silicide regions and methods of fabricating the same


A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween.
Samsung Electronics Co., Ltd.


05/12/16
20160133746 

High mobility devices and methods of forming same


An embodiment method includes forming a first fin and a second fin over a semiconductor substrate. The first fin includes a first semiconductor strip of a first type, and the second fin includes a second semiconductor strip of the first type.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/12/16
20160133733 

Power semiconductor component and manufacturing method thereof


A power semiconductor component includes a semiconductor substrate, a mos layer, a n-type buffer layer, a p-type injection layer, a backside trench layer and a collector metal layer. The mos layer is formed on a first surface of the semiconductor substrate for defining a n-type high-resistance layer.
Mosel Vitelic Inc.


05/12/16
20160133716 

Alternative gate dielectric films for silicon germanium and germanium channel materials


Embodiments of the present invention provide a high-k dielectric film for use with silicon germanium (sige) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (il) is formed on the semiconductor substrate providing reduced interface trap density.
Globalfoundries Inc.


05/12/16
20160133703 

Finfets having dielectric punch-through stoppers


A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/12/16
20160133690 

Methods and high voltage integrated circuit capacitors


High voltage integrated circuit capacitors are disclosed. In an example arrangement, a capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region.
Texas Instruments Incorporated


05/12/16
20160133667 

Solid state image pickup manufacturing the same


When forming a hollow portion between each color filter, in order to realize the formation of the hollow portions with a narrower width, a plurality of light receiving portions are formed on the upper surface of a semiconductor substrate, a plurality of color filters corresponding to each of the light receiving portions are formed above the semiconductor substrate, a photoresist is formed on each color filter, side walls are formed on the side surfaces of the photoresist, and a hollow portion is formed between each color filter by performing etching using at least the side walls as a mask.. .
Canon Kabushiki Kaisha


05/12/16
20160133663 

Solid-state image sensor and camera


An image sensor includes a semiconductor substrate having first and second faces. The sensor includes a plurality of pixel groups each including pixels, each pixel having a photoelectric converter and a wiring pattern, the converter including a region whose major carriers are the same with charges to be accumulated in the photoelectric converter.
Canon Kabushiki Kaisha


05/12/16
20160133658 

Solid-state imaging device and manufacturing the same


According to one embodiment, a method of manufacturing a back-illuminated solid-state imaging device including forming a mask with apertures corresponding to a pixel pattern on the surface of a semiconductor layer, implanting second-conductivity-type impurity ions into the semiconductor layer from the front side of the layer to form second-conductivity-type photoelectric conversion parts and forming a part where no ion has been implanted into a pixel separation region, forming at the surface of the semiconductor layer a signal scanning circuit for reading light signals obtained at the photoelectric conversion parts after removing the mask, and removing the semiconductor substrate and a buried insulating layer from the semiconductor layer after causing a support substrate to adhere to the front side of the semiconductor layer.. .
Kabushiki Kaisha Toshiba


05/12/16
20160133644 

Semiconductor memory devices including asymmetric word line pads


Semiconductor memory devices may include a semiconductor substrate, a first stack disposed on the semiconductor substrate and a second stack disposed on the first stack. The first stack may include a plurality of first word lines with a plurality of first line pads stacked in a stair form, and the second stack may include a plurality of second word lines with a plurality of second line pads stacked in a stair form.

05/12/16
20160133642 

Semiconductor device and fabricating the same


A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes: a memory cell structure formed over a semiconductor substrate; a channel portion formed in the semiconductor substrate; a through-hole formed to pass through the memory cell structure; a first channel region formed over sidewalls of the through-hole; and a second channel region formed at a center part of the through-hole, and spaced apart from the first channel region, wherein each of the first channel region and the second channel region is coupled to the channel portion..
Sk Hynix Inc.


05/12/16
20160133641 

Semiconductor device and manufacturing semiconductor device


A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film.
Renesas Electronics Corporation


05/12/16
20160133636 

Embedded flash memory device with floating gate embedded in a substrate


An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess.
Taiwan Semiconductor Manufacturing Co., Ltd.


05/12/16
20160133618 

Semiconductor device and forming the same


A semiconductor device having a semiconductor substrate is provided. The semiconductor substrate includes an integrated circuit, which includes multi-layer structured metallization and inter-metal dielectric.
Taiwan Semiconductor Manufacturing Company Ltd.


05/12/16
20160133592 

Semiconductor device and manufacturing the same


A semiconductor device according to the present invention includes a semiconductor substrate, a pad formed on the semiconductor substrate, a rewiring that is electrically connected to the pad and led to a region outside the pad, a resin layer formed on the rewiring, and an external terminal electrically connected to the rewiring via the resin layer, and the resin layer is formed so as to enter the inside of a slit formed in a region along the periphery of the external terminal in the rewiring.. .
Rohm Co., Ltd.


05/12/16
20160133582 

Device for detecting a laser attack in an integrated circuit chip


A device for detecting a laser attack made on an integrated circuit chip comprises a bipolar transistor of a first type formed in a semiconductor substrate, that bipolar transistor comprising a parasitic bipolar transistor of a second type. A buried region, forming the base of the parasitic bipolar transistor, operates as a detector of the variations in current flowing caused by impingement of laser light on the substrate..
Stmicroelectronics (rousset) Sas


05/12/16
20160133575 

Air gap structure with bilayer selective cap


A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors.
International Business Machines Corporation


05/12/16
20160133574 

Though-substrate vias (tsvs) and method therefor


A semiconductor device includes a semiconductor substrate having a first major surface and a second major surface opposite the first major surface. A via extends through the substrate.
Freescale Semiconductor, Inc.


05/12/16
20160133524 

Methods for fabricating integrated circuits with improved active regions


Methods for fabricating integrated circuits having improved active regions are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area.
Globalfoundries Singapore Pte. Ltd.


05/12/16
20160133508 

Air gap structure with bilayer selective cap


A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors.
International Business Machines Corporation


05/12/16
20160133505 

Semiconductor device


A method for manufacturing a semiconductor device including a cell region and a peripheral region formed outside the cell region, comprising the steps of (a) providing a semiconductor substrate including a first epitaxial layer of a first conductivity type formed over a main surface thereof, (b) doping a lower band gap impurity for making the band gap smaller than the band gap of the first epitaxial layer before doping into the first epitaxial layer in the cell region, and thereby forming a lower band gap region, (c) after the step (b), forming a plurality of first column regions of a second conductivity type which is the opposite conductivity type to the first conductivity type in such a manner as to be separated from one another in the first epitaxial layer extending from the cell region to the peripheral region, and (d) after the step (c), forming a second epitaxial layer.. .
Renesas Electronics Corporation


05/12/16
20160133504 

Susceptor design to reduce edge thermal peak


Implementations of the present disclosure generally relate to a susceptor for thermal processing of semiconductor substrates. In one implementation, the susceptor includes a first rim surrounding and coupled to an inner region, and a second rim disposed between the inner rim and the first rim.
Applied Materials, Inc.


05/12/16
20160133477 

Methods of forming relief images


In a preferred aspect, methods are provided that comprise a) providing a semiconductor substrate comprising a patterned mask over a layer to be patterned; b) applying a layer of a first composition over the mask, wherein the composition comprises a polymer and the layer is coated on a sidewall of the mask; c) applying a layer of a second composition over the semiconductor substrate in a volume adjacent the coated sidewall of the mask; and d) removing the first composition from the sidewall of the mask, thereby exposing the layer to be patterned and forming a gap between the mask sidewall and the second composition layer to provide a relief image. The methods find particular applicability in semiconductor device manufacture..
Dow Global Technologies Llc


05/12/16
20160133471 

Electroless plating process and tin-silver plating solution therein


An electroless plating process includes providing a semiconductor substrate which has a substrate and a copper pillar disposed on the substrate; providing a tin-silver plating solution includes 0.1-50 wt % tin and 1×105-2 wt % silver; and performing a reduction reaction, wherein the semiconductor substrate is disposed in the tin-silver plating solution for making tin and silver of the tin-silver plating solution deposit jointly on the copper pillar surface to form a tin-silver co-deposition layer. The tin-silver co-deposition layer is able to enhance the coupling strength between the copper pillar of the semiconductor substrate and the other semiconductor substrate and is also able to reduce the time and cost of the process performing tin-plating and silver-plating separately..
National Pingtung University Of Science & Technology


05/05/16
20160126701 

Semiconductor laser and manufacturing method thereof


In a semiconductor laser, a block layer is provided on both sides of a mesa-type semiconductor part having an n-type cladding layer, an active layer, and a p-type cladding layer. The block layer has: a p-type block layer formed on the side surface of the mesa-type semiconductor part and over a p-type semiconductor substrate; a high-resistance layer formed over the p-type block layer; and an n-type block layer formed over the high-resistance layer, which has a higher resistance than that of the p-type block layer.
Renesas Electronics Corporation


05/05/16
20160126587 

Semiconductor structures having a micro-battery and methods for making the same


The present disclosure provides an embodiment of an integrated structure that includes a first electrode of a first conductive material embedded in a first semiconductor substrate; a second electrode of a second conductive material embedded in a second semiconductor substrate; and a electrolyte disposed between the first and second electrodes. The first and second semiconductor substrates are bonded together through bonding pads such that the first and second electrodes are enclosed between the first and second semiconductor substrates.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/05/16
20160126416 

Optoelectronic device and manufacturing same


The invention relates to an optoelectronic device and to the method for manufacturing same. The optoelectronic device (45), according to the invention includes, in particular: a semiconductor substrate (46) doped with a first type of conductivity; semiconductor contact pads (18) or a semiconductor layer on a surface (16) of the substrate which are/is respectively doped with a second type of conductivity that is the opposite of the first type; and semiconductor elements (24), each semiconductor element being in contact with a contact pad or with the layer..
Aledia


05/05/16
20160126400 

Solar cell and manufacturing the same


A solar cell and a method for manufacturing the same are disclosed. The solar cell includes a semiconductor substrate containing impurities of a first conductive type, a tunnel layer positioned on the semiconductor substrate, an emitter region positioned on the tunnel layer and containing impurities of a second conductive type opposite the first conductive type, a dopant layer positioned on the emitter region and formed of a dielectric material containing impurities of the second conductive type, a first electrode connected to the semiconductor substrate, and a second electrode configured to pass through the dopant layer and connected to the emitter region..
Lg Electronics Inc.


05/05/16
20160126394 

Photovoltaic cell and manufacturing such a photovoltaic cell


A photovoltaic cell includes a semiconductor substrate of a first conductivity type, with a first surface arranged with a highly doped surface field layer of the first conductivity type. The substrate has on the highly doped surface field layer at least one contacting area for contacting the surface field layer with a respective contact.
Stichting Energieonderzoek Centrum Nederland


05/05/16
20160126375 

Solar cell, manufacturing the same, and solar cell module


A solar cell includes: a first-conductivity-type semiconductor substrate including an impurity diffusion layer, in which a second-conductivity-type impurity element is diffused, on one surface side; a light-receiving surface-side electrode including a grid electrode and a bus electrode having a wider width than the grid electrode and in electrical communication with the grid electrode, and formed on the one surface side and electrically connected to the impurity diffusion layer; and a rear surface side electrode formed on a rear surface and electrically connected to the impurity diffusion layer, wherein the light-receiving surface-side electrode includes a first metal electrode layer directly bonded to the one surface side, and a second metal electrode layer that is formed of a metal material different from the first metal electrode layer and having electrical resistivity substantially equivalent to the first metal electrode layer and is formed to cover the first metal electrode layer.. .
Mitsubishi Electric Corporation


05/05/16
20160126369 

Semiconductor device and patterning plated electrode thereof


The present invention discloses in detail a semiconductor device and a patterning method for the plated electrode thereof. By using the laser ablation method according to the prior art, the semiconductor substrate below the arc is damaged by direct destructive burning.
Atomic-energy Council-institute Of Nuclear Engergy Research


05/05/16
20160126368 

Solar cell


A solar cell is discussed. The solar cell according to an embodiment includes a semiconductor substrate containing impurities of a first conductive type, a metal oxide layer positioned on the semiconductor substrate, an emitter region positioned on the metal oxide layer and having a second conductive type opposite the first conductive type, a first electrode connected to the emitter region, and a second electrode connected to the semiconductor substrate..
Lg Electronics Inc.


05/05/16
20160126353 

Finfet device including a uniform silicon alloy fin


A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses.
Globalfoundries Inc.


05/05/16
20160126343 

Finfets with source/drain cladding


A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/05/16
20160126319 

Method for manufacturing a semiconductor device


A method for manufacturing a semiconductor device having a mos gate structure includes forming a device structure on a semiconductor substrate; forming an interlayer dielectric to cover the device structure; forming a contact hole through the interlayer dielectric; forming a transition metal film (e.g., ni) on a portion of the semiconductor substrate exposed by the contact hole; (e) forming a metal film (e.g., ti) on the entire surface of the semiconductor substrate; forming an oxide film in the surface of the metal film; selectively removing the metal film in which the oxide film has been formed, to thereby expose the transition metal film; and (h) exposing, to a hydrogen plasma atmosphere, the semiconductor substrate in which the transition metal film and the oxide film have been exposed, to thereby cause the transition metal film to generate heat and react with the semiconductor substrate and form an ohmic contact there between.. .
Fuji Electric Co., Ltd.


05/05/16
20160126314 

Semiconductor device


A gate pad electrode and a source electrode are disposed, separately from one another, on the front surface of a super junction semiconductor substrate. A mos gate structure formed of n source regions, p channel regions, p contact regions, a gate oxide film, and polysilicon gate electrodes is formed immediately below the source electrode.
Fuji Electric Co., Ltd.


05/05/16
20160126309 

Semiconductor device structure and forming the same


A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


05/05/16
20160126285 

Solid-state imaging device and imaging system


A solid-state imaging device includes: a first semiconductor substrate including a photoelectric conversion element; and a second semiconductor substrate including at least a part of a peripheral circuit arranged in a main face of the second semiconductor substrate, the peripheral circuit generating a signal based on the charge of the photoelectric conversion element, a main face of the first semiconductor substrate and the main face of the second semiconductor substrate being opposed to each other with sandwiching a wiring structure therebetween; a pad to be connected to an external terminal; and a protection circuit electrically connected to the pad and to the peripheral circuit, wherein the protection circuit is arranged in the main face of the second semiconductor substrate.. .
Canon Kabushiki Kaisha


05/05/16
20160126282 

Cmos image sensor with enhanced dynamic range


An image sensor includes a semiconductor substrate having a main surface, a transfer transistor having a transfer gate disposed on the main surface, a light-sensing structure on one side of the transfer gate, a floating diffusion node on the other side of the transfer gate, a reset transistor serially connected to the transfer transistor via the floating diffusion node, a source-follower transistor having a source-follower gate, and a vertical capacitor having a first vertical electrode plate and a second vertical electrode plate. The first vertical electrode plate is electrically connected to the source-follower gate and the floating diffusion node..
Powerchip Technology Corporation


05/05/16
20160126274 

Image pickup apparatus


To provide an image pickup apparatus that can increase capacitance value of an input node in a connection state without decreasing amplification transistor gain when capacitance is in a non-connection state. In an image pickup apparatus according to an aspect of the present disclosure, a gate electrode of an amplification transistor is arranged on a main surface of the semiconductor substrate, a third semiconductor region having a second conductivity type is arranged in a lower part of the gate electrode, and an added impurity concentration of impurity having the second conductivity type on a pn junction surface of a capacitance is higher than a highest value of an added impurity concentration having the second conductivity type in a region from the main surface up to a depth at which a source and a drain of the amplification transistor are arranged in the third semiconductor region..
Canon Kabushiki Kaisha


05/05/16
20160126273 

Solid-state imaging device, manufacturing a solid-state imaging device, and electronic apparatus


Disclosed is a solid-state imaging device including a plurality of pixels and a plurality of on-chip lenses. The plurality of pixels are arranged in a matrix pattern.
Sony Corporation


05/05/16
20160126268 

Semiconductor device, solid-state imaging device and camera module


Certain embodiments provide a solid-state imaging device including: a semiconductor substrate having a top surface on which a light receiving section that receives light is provided, the semiconductor substrate having a through hole which is provided in a part of the semiconductor substrate; an electrode pad provided on the top surface side of the semiconductor substrate including an area right above the through hole to be in contact with the first wiring, the electrode pad having a slit between the area right above the through hole and the first wiring; an insulating film provided on a side surface of the through hole; and a second wiring provided on the insulating film to be in contact with the electrode pad.. .
Kabushiki Kaisha Toshiba


05/05/16
20160126267 

Imaging systems with backside isolation trenches


An image sensor such as a backside illumination image sensor may be provided with analog circuitry, digital circuitry, and an image pixel array on a semiconductor substrate. Trench isolation structures may separate the analog circuitry from the digital circuitry on the substrate.
Semiconductor Components Industries, Llc


05/05/16
20160126250 

Charge-trapping memory device


A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (fet) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed.
Spansion Llc


05/05/16
20160126239 

Integrated circuits with resistor structures formed from mim capacitor material and methods for fabricating same


Integrated circuits having resistor structures formed from a mim capacitor material and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a capacitor area.
Globalfoundries, Inc.


05/05/16
20160126235 

Semiconductor device and producing the same


A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad.
Fuji Electric Co., Ltd.


05/05/16
20160126141 

Methods for forming finfets having a capping layer for reducing punch through leakage


A method for forming finfets having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer.
Globalfoundries Inc.


05/05/16
20160126132 

Methods for fabricating integrated circuits with isolation regions having uniform step heights


Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including an isolation region between a first device region and a second device region.
Globalfoundries, Inc.


05/05/16
20160126120 

Work-in-progress substrate processing methods and systems for use in the fabrication of integrated circuits


Disclosed herein are methods and systems for semiconductor fabrication. In one embodiment, a method for fabricating semiconductors utilizing a semiconductor fabrication system includes performing a semiconductor fabrication process on a first lot of unprocessed semiconductor substrates with a semiconductor fabrication equipment unit to form a first lot of processed substrates and communicating processing data regarding the first lot of processed substrates from the semiconductor fabrication equipment unit to a just-in-time (jit) module of the semiconductor fabrication system.
Globalfoundries, Inc.


05/05/16
20160126116 

Singulation apparatus and method


A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon.
Taiwan Semiconductor Manufacturing Company Ltd.


05/05/16
20160126103 

Recess filling method and processing apparatus


There is provided a method of filling a recess of a workpiece, which includes: forming a first thin film made of a semiconductor material along a wall surface defining a recess in a semiconductor substrate; annealing the workpiece within a vessel whose internal process is set to a first pressure, and forming an epitaxial region which is generated by crystallizing the semiconductor material of the first thin film, along a surface defining the recess, without moving the first thin film; forming a second thin film made of the semiconductor material along the wall surface defining the recess; and annealing the workpiece within the vessel whose internal pressure is set to a second pressure lower than the first pressure, and forming a further epitaxial region which is generated by crystallizing the semiconductor material of the second thin film which is moved toward a bottom of the recess.. .
Tokyo Electron Limited


05/05/16
20160126092 

Silicon carbide semiconductor device and manufacturing silicon carbide semiconductor device


On a silicon carbide semiconductor substrate, heat treatment is performed after one layer or two or more layers of an oxide film, a nitride film, or an oxynitride film are formed as a gate insulating film. The heat treatment after the gate insulating film is formed is performed for a given period in an atmosphere that includes h2 and h2o without including o2.
National Institute Of Advanced Industrial Science And Technology




Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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