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Semiconductor Substrate patents



      
           
This page is updated frequently with new Semiconductor Substrate-related patent applications. Subscribe to the Semiconductor Substrate RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Substrate RSS RSS


Apparatus and method for detecting position drift in a machine operation using a robot arm

Apparatus and method for detecting position drift in a machine operation using a robot arm

Internal plasma grid for semiconductor fabrication

Internal plasma grid for semiconductor fabrication

Internal plasma grid for semiconductor fabrication

Internal plasma grid for semiconductor fabrication

Date/App# patent app List of recent Semiconductor Substrate-related patents
10/09/14
20140303919
 Photoinduced carrier lifetime measurement device and photoinduced carrier lifetime measurement method patent thumbnailPhotoinduced carrier lifetime measurement device and photoinduced carrier lifetime measurement method
A photoinduced carrier lifetime measurement device includes light sources that respectively apply light that differs in wavelength and generates photoinduced carriers to a semiconductor substrate, a microwave generation section that generates microwaves that are applied to the semiconductor substrate, a detection section that detects the intensity of the microwaves that have passed through the semiconductor substrate, and a calculation section that calculates the effective carrier lifetime corresponding to the wavelength of each light based on the intensity of the microwaves detected when applying each light, and calculates the bulk carrier lifetime and a surface recombination velocity of the semiconductor substrate based on the effective carrier lifetime calculated corresponding to the wavelength of each light.. .
10/09/14
20140303776
 Apparatus and method for detecting position drift in a machine operation using a robot arm patent thumbnailApparatus and method for detecting position drift in a machine operation using a robot arm
In an example embodiment, apparatus for detecting position drift in a machine operation using a robot arm, the robot arm being for operation on a semiconductor substrate, the robot arm and the semiconductor substrate being configured for relative movement therebetween, the apparatus includes an input for receiving an input signal from a sensor mounted on the robot arm; a detector for detecting, from the input signal, a detection of there being a predefined distance between the robot arm and the semiconductor substrate; wherein the apparatus is configured to determine, from the detection, whether there has been position drift.. .
10/09/14
20140302681
 Internal plasma grid for semiconductor fabrication patent thumbnailInternal plasma grid for semiconductor fabrication
The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers.
10/09/14
20140302680
 Internal plasma grid for semiconductor fabrication patent thumbnailInternal plasma grid for semiconductor fabrication
The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers.
10/09/14
20140302678
 Internal plasma grid applications for semiconductor fabrication patent thumbnailInternal plasma grid applications for semiconductor fabrication
The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers.
10/09/14
20140302668
 Semiconductor device and manufacturing method thereof patent thumbnailSemiconductor device and manufacturing method thereof
An improvement is achieved in the performance of semiconductor device including a nonvolatile memory. In a split-gate nonvolatile memory, between a memory gate electrode and a p-type well and between a control gate electrode and the memory gate electrode, an insulating film is formed.
10/09/14
20140302655
 Non-volatile memory device with vertical memory cells and method for fabricating the same patent thumbnailNon-volatile memory device with vertical memory cells and method for fabricating the same
A non-volatile memory device includes a plurality of gate electrodes stacked over a semiconductor substrate and stretched in a first direction along the semiconductor substrate and a plurality of junction layers having a first region protruding from the semiconductor substrate and crossing the gate electrodes and a second region formed between the gate electrodes.. .
10/09/14
20140302651
 Method for manufacturing semiconductor device with first and second gates over buried bit line patent thumbnailMethod for manufacturing semiconductor device with first and second gates over buried bit line
A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device.
10/09/14
20140302646
 Method of manufacturing semiconductor device patent thumbnailMethod of manufacturing semiconductor device
A performance and reliability of a semiconductor device are improved. On a semiconductor substrate, a gate electrode for a first misfet and a dummy gate electrode for a second misfet are formed, and then, an insulating film is partially formed on the gate electrode.
10/09/14
20140302628
 Optical semiconductor device and method of manufacturing optical semiconductor device patent thumbnailOptical semiconductor device and method of manufacturing optical semiconductor device
A method of manufacturing an optical semiconductor device including: forming a mesa structure including a first conductivity type cladding layer, an active layer and a second conductivity type cladding layer in this order on a first conductivity type semiconductor substrate, an upper most surface of the mesa structure being constituted of an upper face of the second conductivity type cladding layer; growing a first burying layer burying both sides of the mesa structure at higher position than the active layer; forming an depressed face by etching both edges of the upper face of the second conductivity type cladding layer; and growing a second burying layer of the first conductivity type on the depressed face of the second conductivity type cladding layer and the first burying layer.. .
10/09/14
20140302620
Method for manufacturing solar cell
A method for manufacturing a solar cell capable of significantly reducing the amount of wastewater generated during a wet-etching process and improving the efficiency of the solar cell. A method comprising: texturing to form an uneven structure on one semiconductor substrate surface by etching the semiconductor substrate surface with a texturing device; forming a temporary layer at an upper portion of the semiconductor substrate surface to surround a first byproduct layer formed at a predetermined region of the semiconductor substrate surface during the texturing; and doping the semiconductor substrate surface with a predetermined dopant using a doping device to form a first semiconductor layer and a second semiconductor layer disposed above the first semiconductor layer and having a different polarity than the first semiconductor layer.
10/09/14
20140301128
3d variable resistance memory device having junction fet and driving method thereof
A 3d variable resistance memory device having a junction fet and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate.
10/09/14
20140300667
Liquid discharge head and method for manufacturing the same
A liquid discharge head includes a recording element substrate comprising a semiconductor substrate having an energy generating element configured to generate energy for discharging liquid, on a first surface, a flow path forming member disposed on the first surface, and in which a discharge port configured to discharge the liquid and a liquid flow path in communication with the discharge port are formed, and a connection terminal disposed in a vicinity of an end portion of the first surface, and an electric wiring substrate electrically connected to the connection terminal. The recording element substrate includes an insulating resin layer disposed in a vicinity of the end portion of the first surface and outward from the connection terminal, and an adhesiveness improving layer disposed between the insulating resin layer and the semiconductor substrate, and configured to improve adhesiveness between the insulating resin layer and the semiconductor substrate..
10/09/14
20140300340
High-k metal gate device structure for human blood gas sensing
A device structure for detecting partial pressure of oxygen in blood includes a semiconductor substrate including a source region and a drain region. A multi-layer gate structure is formed on the semiconductor substrate.
10/09/14
20140300003
Semiconductor device and interconnect substrate
A semiconductor substrate includes a semiconductor chip and an interconnect substrate. The interconnect substrate has an interconnect region between a first main surface formed with plural orderly arranged first and second signal electrodes connected to the semiconductor chip, and a second main surface.
10/09/14
20140299986
Semiconductor device manufacturing method and semiconductor device
A plurality of protruding electrodes of a semiconductor chip are in contact with a plurality of electrodes formed on a semiconductor substrate, via a plurality of solder sections. In this state, the solder sections are melted so as to form a plurality of solder bonding sections joined to the protruding electrodes of the semiconductor chip and the electrodes of the semiconductor substrate.
10/09/14
20140299972
Semiconductor device having a through contact
A semiconductor device includes a semiconductor substrate having a first side and a second side opposite the first side, an active area and a through contact area, the active area including a transistor structure having a control electrode, the through contact area including a semiconductor mesa having insulated sidewalls. The semiconductor device further includes a first metallization on the first side in the active area and a recess extending from the first side into the semiconductor substrate and between the active area and the through contact area and including in the through contact area a horizontally widening portion, the recess being at least partly filled with a conductive material forming a first conductive region in ohmic contact with the semiconductor mesa and the transistor structure.
10/09/14
20140299970
Semiconductor integrated circuit device
A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate.
10/09/14
20140299958
Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device, includes forming a trench in a semiconductor substrate having a first face and a second face by processing the first face of the semiconductor substrate, the trench including a first portion and a second portion located between the first portion and a plane including a first face, filling an insulator in the second portion such that a space remains in the first portion and the trench is closed, and forming a plurality of elements between the first face and the second face, wherein the space and the insulator form element isolation.. .
10/09/14
20140299956
Layers for increasing performance in image sensors
An imaging device includes a semiconductor substrate having a photosensitive element for accumulating charge in response to incident image light. The semiconductor substrate includes a light-receiving surface positioned to receive the image light.
10/09/14
20140299944
Graphene devices and methods of fabricating the same
A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable schottky barrier formed by junction of the first electrode, the graphene layer, and the semiconductor substrate..
10/09/14
20140299928
Semiconductor device and method of forming the same
A semiconductor device may include, but is not limited to, a semiconductor substrate having a first gate groove; a first fin structure underneath the first gate groove; a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of a first side of the first gate groove; and a second diffusion region in the semiconductor substrate. The second diffusion region covers a second side of the first gate groove.
10/09/14
20140299926
Semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device comprises forming a first layer on an impurity diffusion region in a semiconductor substrate by a selective epitaxial growth method, forming a second layer on the first layer by the selective epitaxial growth method, forming a contact hole penetrating an interlayer insulating film in a thickness direction thereof and reaching the second layer, and filling a conductive material into the contact hole to form a contact plug including the first and second layers and the conductive material.. .
10/09/14
20140299923
Field effect transistor
A field effect transistor includes a semiconductor substrate having a protrusion with at least one inclined surface, a gate insulator disposed at least on a portion of the inclined surface, and a gate conductor disposed on the gate insulator, wherein the semiconductor substrate comprises doped regions sandwiching a channel region, wherein the at least one inclined surface has a first crystal orientation in the channel region, and the inclined surface has an included angle to a vertical plane with a second crystal orientation. The hole mobility and the electron mobility are substantially the same in the channel region having a crystalline orientation off from the (110) crystal orientation..
10/09/14
20140299922
High-k metal gate device structure for human blood gas sensing
A device structure for detecting partial pressure of oxygen in blood includes a semiconductor substrate including a source region and a drain region. A multi-layer gate structure is formed on the semiconductor substrate.
10/09/14
20140299921
Solid-state imaging device with channel stop region with multiple impurity regions in depth direction and method for manufacturing the same
Channel stop sections formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a p-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented.
10/09/14
20140299918
Semiconductor substrate and fabrication method thereof, and semiconductor apparatus using the same and fabrication method thereof
A semiconductor substrate and a fabrication method thereof, and a semiconductor apparatus using the same and a fabrication method thereof are provided. The semiconductor substrate includes a semiconductor wafer, a silicon germanium (sige)-based impurity doping region formed on the semiconductor wafer, and a protection layer formed on the sige-based impurity doping region..
10/09/14
20140299917
Semiconductor device
A semiconductor device includes a first conductive type semiconductor substrate, a second conductive type active region formed on a top surface side of the semiconductor substrate, a second conductive type inside vld region formed to contact the active region on the top surface side in a plan view, and a second conductive type well region formed to contact a portion opposite to the portion contacting the active region of the inside vld region on the top surface side in a plan view. The well region is formed to be deeper than the active region.
10/09/14
20140299916
Monolithic cell for an integrated circuit and especially a monolithic switching cell
A cell includes at least two semiconductor structures of the same nature, these two structures both employing voltages and currents that are unidirectional, each structure having an anode (10), a cathode (14) and optionally a gate (16). The structures are integrated into the volume of one and the same semiconductor substrate (4).
10/09/14
20140299915
Semiconductor device
In a semiconductor device having a vertical semiconductor element configured to pass an electric current between an upper electrode and a lower electrode, a field stop layer includes a phosphorus/arsenic layer doped with phosphorus or arsenic and a proton layer doped with proton. The phosphorus/arsenic layer is formed from a back side of a semiconductor substrate to a predetermined depth.
10/09/14
20140299891
Semiconductor device
A semiconductor device that can improve reliability while suppressing increase of a conduction loss or a switching loss. In the semiconductor device, when a two-dimensional shape on a main surface of the semiconductor substrate is an unit cell, the shape being a repeating unit of a plurality of well regions periodically disposed in a surface layer of a drift layer, one unit cell and another unit cell adjacent in an x-axis direction are disposed misaligned in a y-axis direction, and one unit cell and another unit cell adjacent in the y-axis direction are disposed misaligned in the x-axis direction..
10/09/14
20140299888
Silicon carbide semiconductor device
A sic semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a sic-mosfet including an n-type semiconductor substrate formed of sic, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad.
10/09/14
20140299886
Silicon carbide semiconductor device and manufacturing method of the same
A silicon carbide semiconductor device includes: a semiconductor substrate made of silicon carbide single crystal and having a principal surface and a backside; and an ohmic electrode contacting one of the principal surface and the backside of the semiconductor substrate in an ohmic manner. A boundary between the ohmic electrode and the one of the principal surface and the backside of the semiconductor substrate is terminated with an element, which has a pauling electronegativity larger than silicon and a binding energy with silicon larger than a binding energy of si—h..
10/09/14
20140299831
3d variable resistance memory device and method of manufacturing the same
A 3d variable resistance memory device and a method of manufacturing the same are provided. A semiconductor substrate includes a peripheral area, having a top surface, wherein a peripheral circuit is formed in the peripheral area.
10/09/14
20140299747
Solid-state imaging device and method for driving the same
A solid-state imaging device includes: multiple pixels. Each pixel is arranged at a surface layer portion of a semiconductor substrate, and includes: a photoelectric conversion portion that converts light incident into an electric charge; a charge holding portion that stores the electric charge, and is arranged in the semiconductor substrate; a multiplication gate electrode that is capacitively coupled with the charge holding portion, and is arranged on the semiconductor substrate via an insulation film; and a charge barrier portion that is arranged between the charge holding portion and the insulation film, and has a higher impurity concentration than the semiconductor substrate..
10/09/14
20140299187
Solar cell
Discussed is a solar cell including a semiconductor substrate, a first tunneling layer entirely formed over a surface of the semiconductor substrate, a first conductive type area disposed on the surface of the semiconductor substrate, and an electrode including a first electrode connected to the first conductive type area.. .
10/09/14
20140299186
Interdigitated back contact photovoltaic cell with floating front surface emitter regions
A photo-voltaic cell with semiconductor substrate having a first conductivity type has a first pattern of base and emitter surface regions on the back surface, the base and emitter surface regions being coupled to first and second output terminals respectively. A second pattern of first and second further surface regions on the front surface, electrically floating with respect to the first and second output terminals.
10/02/14
20140295676
Method of operating vertical heat treatment apparatus, vertical heat treatment apparatus and non-transitory recording medium
A method of operating vertical heat treatment apparatus includes: cleaning interior of vertical reaction chamber by supplying cleaning gas; pre-coating the interior of the reaction chamber by performing, a plurality of times, a cycle including alternately supplying the first gas and supplying the second gas while generating plasma from the second gas; eliminating charges by loading substrate holding unit holding a dummy semiconductor substrate or a conductive substrate into the reaction chamber and supplying the second gas while generating plasma from the second gas without supplying the first gas; loading the substrate holding unit holding a plurality of product semiconductor substrates into the reaction chamber; and forming thin film in the reaction chamber by performing, a plurality of times, a cycle including alternately supplying the first gas and supplying the second gas while generating plasma from the second gas.. .
10/02/14
20140295658
Semiconductor device comprising trench gate and buried source electrodes
A semiconductor device includes a semiconductor substrate, a trench, a buried insulated source electrode arranged in a bottom portion of the trench, a first gate electrode and a second gate electrode arranged in an upper portion of the trench and spaced apart from one another. A surface gate contact extends into the upper portion of the trench and is in physical and electrical contact with the first gate electrode and second gate electrode..
10/02/14
20140295651
Backside stress compensation for gallium nitride or other nitride-based semiconductor devices
A method includes forming a stress compensation layer over a first side of a semiconductor substrate and forming a group iii-nitride layer over a second side of the substrate. Stress created on the substrate by the group iii-nitride layer is at least partially reduced by stress created on the substrate by the stress compensation layer.
10/02/14
20140295647
Bulk fin-field effect transistors with well defined isolation
A computer program storage product includes instructions for forming a fin field-effect-transistor. The instructions are configured to perform a method.
10/02/14
20140295641
Semiconductor memory device and method of manufacturing the same
A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.. .
10/02/14
20140295633
Manufacturing method of semiconductor device
A manufacturing method of a semiconductor device includes: a semiconductor substrate including a drain, a drift making contact with a front face of the drain, a body contacting with a front face of the drift, a source provided in part of a front face of the body, and a floating surrounded by the drift; and a gate including an insulator formed on an inner wall of a trench and a electrode disposed inside the insulator and which has a bottom portion contacting with the floating, the manufacturing method includes: forming the trench in a semiconductor wafer so as to have a bottom portion in which an end portion in a short direction perpendicular to a longitudinal direction thereof is deeper than a central portion; injecting an impurity ions into the bottom portion of the trench; and forming the central portion of the trench in the short direction to be deepened.. .
10/02/14
20140295614
Solar cell and method of manufacturing the same
A solar cell and a method of manufacturing a solar cell are disclosed. The solar cell includes forming a first doped region of a first conductive type and a second doped region of a second conductive type opposite the first conductive type on a semiconductor substrate of the first conductive type; forming a passivation layer on the semiconductor substrate to expose a portion of each of the first and second doped regions; and forming a first electrode electrically connected to the first doped region and a second electrode electrically connected to the second doped region, wherein the forming of the first and second electrodes includes forming a metal seed layer directly contacting the first doped region and a metal seed layer directly contacting the second doped region, and forming a conductive layer on the metal seed layer of each of the first and second electrodes..
10/02/14
20140295612
Solar cell and manufacturing method thereof
A solar cell and a manufacturing method thereof are provided. A laser doping process is adopted to form positive and negative doping regions for an accurate control of the doping regions.
10/02/14
20140295610
Spectroscopic sensor and method for manufacturing same
A method for manufacturing a spectroscopic sensor includes: (a) forming a light receiving element on a semiconductor substrate; (b) forming an angle restricting filter on the semiconductor substrate; and (c) forming a spectroscopic filter on the angle restricting filter. The step (c) of forming a spectroscopic filter includes: (c1) forming a first light transmitting film having a peripheral edge that overlaps a light blocking portion in plan view ox the semiconductor substrate by a lift-off method; and (c2) forming a second light transmitting film at a position spaced apart from the first light transmitting film in plan view of the semiconductor substrate by the lift-off method, the second light transmitting film having a peripheral edge that overlaps the light blocking portion in plan view of the semiconductor substrate..
10/02/14
20140295582
Controlling the device performance by forming a stressed backside dielectric layer
A device includes a p-type metal-oxide-semiconductor (pmos) device and an n-type metal-oxide-semiconductor (nmos) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate.
10/02/14
20140295580
Method for manufacturing semiconductor device and manufacturing apparatus
A method for manufacturing a semiconductor device includes accommodating in a processing chamber a semiconductor structural body having a semiconductor substrate and a laminated structure formed on the semiconductor substrate and having multiple metal films including a noble-metal film, and generating a bias voltage on the semiconductor substrate while generating an oxygen plasma in the processing chamber such that a plasma treatment removes at least part of the noble-metal film in the laminated structure of the semiconductor structural body.. .
10/02/14
20140294031
Optical device and optical module
An optical device includes an active layer disposed over a semiconductor substrate, a diffraction grating disposed over the active layer, a clad layer partly disposed over the diffraction grating, at least one first burying material layer disposed beside side surfaces of end portions of the clad layer over the diffraction grating, and at least one second burying material layer disposed beside side surfaces of a center portion of the clad layer over the diffraction grating. A refractive index of the at least one first burying material layer is different from a refractive index of the at least are second burying material layer..
10/02/14
20140294028
Semiconductor laser device
A semiconductor laser device includes an n-type semiconductor substrate, an n-type cladding layer laminated on the semiconductor substrate, an n-side light guiding layer laminated on the n-type cladding layer, an active layer laminated on the n-side light guiding layer, a p-side light guiding layer laminated on the active layer, and a p-type cladding layer laminated on the p-side light guiding layer. The sum of the thicknesses of the n-side and p-side light guiding layers is such that the first and higher order modes of oscillation can occur in the crystal growth direction.
10/02/14
20140293716
Switching circuit and semiconductor memory device
A switching circuit includes a first well and a second well formed in a semiconductor substrate; a first transistor being connected with a first node at one end, and the first transistor being formed in the first well; a second transistor being connected with another end of the first node at one end, and connected with a second node at another end, and the second transistor being formed in the second well; and a potential control circuit that connects the second well with the first node during a predetermined period including a period for the first transistor and the second transistor to transition from off to on in a state where potential of the second node is lower than potential of the first node, and connects the second well with the second node after the predetermined period.. .
10/02/14
20140293700
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array including a plurality of stacked memory cells, a plurality of first wirings electrically connected to the plurality of memory cells, a plurality of first contacts electrically connected to part of the plurality of first wirings and arranged in a first direction parallel to the semiconductor substrate, a plurality of second contacts electrically connected to part of the plurality of first wirings and arranged in the first direction alternately with the first contacts, a plurality of third contacts electrically connected to the first contacts and displaced from the first contacts in the first direction, and a plurality of fourth contacts electrically connected to the second contacts and displaced from the second contacts in a second direction perpendicular to the first direction.. .
10/02/14
20140293695
Semiconductor memory device
According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit..
10/02/14
20140293250
Focus control apparatus for photolithography
A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material the sound wave is detected using a sensor.
10/02/14
20140292317
Durable miniature gas composition detector having fast response time
A miniature oxygen sensor makes use of paramagnetic properties of oxygen gas to provide a fast response time, low power consumption, improved accuracy and sensitivity, and superior durability. The miniature oxygen sensor disclosed maintains a sample of ambient air within a micro-channel formed in a semiconductor substrate.
10/02/14
20140291942
Chuck structure for substrate cleansing equipment
The present invention provides a chuck structure for substrate cleansing equipment, which comprises a base and at least a pair of clipping members. The pair of clipping members is disposed on both corresponding sides of the base, respectively.
10/02/14
20140291856
Tsv layout structure and tsv interconnect structure, and fabrication methods thereof
Tsv layout structure and tsv interconnect structure, and their fabrication methods are provided. An exemplary tsv interconnect structure includes a semiconductor substrate having a first region and a second region; and a plurality of through-holes disposed in the first region and the second region of the semiconductor substrate.
10/02/14
20140291809
Semiconductor substrate and a method of manufacturing the same
The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 mev from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm−3.. .
10/02/14
20140291799
Semiconductor device including sti structure and fabrication method
Semiconductor devices including sti structures and their fabrication methods are provided. A mask layer is provided on a semiconductor substrate and patterned to form an opening in the mask layer to expose a surface portion of the semiconductor substrate.
10/02/14
20140291798
Semiconductor memory device
A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.. .
10/02/14
20140291793
Solid-state imaging apparatus, solid-state imaging apparatus manufacturing method, and electronic apparatus
There is provided a solid-state imaging apparatus including a plurality of photoelectric conversion regions which photoelectrically convert light incident from a rear surface side of a semiconductor substrate, element isolation regions formed between the plurality of photoelectric conversion regions arranged in a matrix shape, and shielding members formed on upper surfaces of the element isolation regions. The element isolation regions have high impurity concentration regions of a high impurity concentration connected to at least a part of the shielding members..
10/02/14
20140291786
Component having a micromechanical microphone structure
Substrate-side overload protection for the diaphragm structure of a microphone component having a micromechanical microphone structure which impairs the damping properties of the microphone structure as little as possible, in which the microphone structure includes a diaphragm structure having at least one acoustically active diaphragm which is formed in a diaphragm layer above a semiconductor substrate. The diaphragm structure spans at least one sound opening in the rear side of the substrate.
10/02/14
20140291773
Power semiconductor device and fabrication method thereof
A power semiconductor device includes a cell region on a semiconductor substrate, at least a transistor device in the cell region, a peripheral termination region encompassing the cell region, a plurality of epitaxial islands arranged around the cell region, and a grid type epitaxial layer in the peripheral termination region. The grid type epitaxial layer separates the plurality of epitaxial islands from one another..
10/02/14
20140291770
Method of making a finfet device
The present disclosure provides many different embodiments of fabricating a finfet device that provide one or more improvements over the prior art. In one embodiment, a method of fabricating a finfet includes providing a semiconductor substrate and a plurality of dummy fins and active fins on the semiconductor substrate.
10/02/14
20140291768
Spacer elements for semiconductor device
The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack.
10/02/14
20140291765
Esd protection structure and esd protection circuit
An electrostatic discharge (esd) protection structure and an esd protection circuit are provided. A pmos transistor is located in a first region of a first n-type well region of a semiconductor substrate.
10/02/14
20140291764
Esd protection structure and esd protection circuit
An electrostatic discharge (esd) protection structure and an esd protection circuit are provided. A pmos transistor is located in a first region of a first n-type well region of a semiconductor substrate.
10/02/14
20140291759
Mos transistor and fabrication method
Mos transistors and fabrication methods are provided. An exemplary mos transistor includes a gate structure formed on a semiconductor substrate.
10/02/14
20140291755
Semiconductor device and semiconductor module
A semiconductor device includes a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate, and a gate structure crossing the active region and disposed between the first and second source/drain regions, the gate structure including a gate electrode having a first part and a second part on the first part, the gate electrode being at a lower level than an upper surface of the active region, an insulating capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an empty space between the active region and the second part of the gate electrode.. .
10/02/14
20140291754
Semiconductor structure having buried word line and method of manufacturing the same
A semiconductor structure having buried word line formed in a trench in a semiconductor substrate includes a gate oxide layer, a gate conductor, a gate cap layer, a blocking layer, and an isolation structure. The gate oxide layer is formed on the inner surface of the trench, the gate conductor is formed in the trench, and the gate cap layer is formed on the gate conductor.
10/02/14
20140291750
Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods
A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer.
10/02/14
20140291749
Memory device having multiple dielectric gate stacks and related methods
A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack.
10/02/14
20140291748
Semiconductor memory device
A semiconductor memory device includes a bit line, an active region formed in a semiconductor substrate, a plug formed on the active region and connecting the bit line to the active region, a memory cell which includes a first gate insulating film on the active region, a charge storage layer on the first gate insulating film, a first insulating film on the charge storage layer, and a control gate electrode on the first insulating film, a select transistor formed between the plug and the memory cell on the active region and including a second gate insulating film on the active region, a first electrode layer on the second gate insulating film, a second insulating film on the first electrode layer, and a second electrode layer on the second insulating film, and a wiring formed above the active region between the plug and the second electrode layer of the select transistor.. .
10/02/14
20140291736
Semiconductor device and method of manufacturing the same
In one embodiment, a first main terminal region of a first conductivity type and a second main terminal region of a second conductivity type, which is an opposite conductivity type of the first conductivity type, formed in the semiconductor substrate so as to sandwich a gate electrode, a diffusion layer of the second conductivity type coming in contact with the first and second element isolation insulator films and having an upper surface in a position deeper than lower surfaces of the first and second main terminal regions, a first well region of the first conductivity type formed between the first main terminal region and the diffusion layer, and a second well region of the first conductivity type formed between the second main terminal region and the diffusion layer. The second well region has a impurity concentration higher than that of the first well region..
10/02/14
20140291735
Double patterning via triangular shaped sidewall spacers
An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (sin) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers for mandrels of a filler material substantially different in composition from the sidewall spacers, such as a flowable oxide.
10/02/14
20140291734
Thin channel mosfet with silicide local interconnect
A semiconductor structure and method of manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate having an isolated area comprising a first region and a second region.
10/02/14
20140291732
Photoelectric conversion apparatus and imaging system using the photoelectric conversion apparatus
In a photoelectric conversion apparatus including a charge holding portion, a part of an element isolation region contacting with a semiconductor region constituting the charge holding portion extends from a reference surface including the light receiving surface of a photoelectric conversion element into a semiconductor substrate at a level equal to or deeper than the depth of the semiconductor region in comparison with the semiconductor region.. .
10/02/14
20140291486
Light detection device
A light detection device 1 has a semiconductor light detection element having a semiconductor substrate, and a mounting substrate arranged as opposed to the semiconductor light detection element. The semiconductor light detection element includes a plurality of avalanche photodiodes operating in geiger mode and formed in the semiconductor substrate, and electrodes electrically connected to the respective avalanche photodiodes and arranged on a second principal surface side of the semiconductor substrate.


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Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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