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Semiconductor Substrate patents

      

This page is updated frequently with new Semiconductor Substrate-related patent applications.




new patent Semiconductor substrate, semiconductor module and manufacturing the same
The present disclosure relates to a semiconductor substrate, a semiconductor module and a method for manufacturing the same. The semiconductor substrate includes a first dielectric structure, a second dielectric structure, a first patterned conductive layer and a second patterned conductive layer.
Advanced Semiconductor Engineering, Inc.


new patent Monolithic nanophotonic device on a semiconductor substrate
A photonic light generating device is provided on a portion of a first semiconductor material. The photonic light generating device includes a second semiconductor material that has a different lattice constant than the lattice constant of the first semiconductor material and that is capable of generating and emitting light.
International Business Machines Corporation


new patent Method of manufacturing a battery, battery and integrated circuit
A method of manufacturing a battery includes defining an active region and a bonding area in a first main surface of a first semiconductor substrate, forming a first ditch in the bonding area, forming an anode at the first semiconductor substrate in the active region, and forming a cathode at a carrier comprising an insulating material. The method further includes stacking the first semiconductor substrate and the carrier so that the first main surface of the first semiconductor substrate is disposed on a side adjacent to a first main surface of the carrier, a cavity being formed between the first semiconductor substrate and the carrier, and forming an electrolyte in the cavity..
Infineon Technologies Ag


new patent Method for manufacturing a photovoltaic cell with selective doping
A method for creating a photovoltaic cell, includes forming a first doped region in a semiconductor substrate having a first concentration of doping elements; forming, by ion implantation, alignment units, the largest size of which is smaller than one millimeter, and a second doped region, adjacent to the first region with a second concentration of doping elements; heat-treating the substrate to activate the doping elements and to form an oxide layer at the surface of the substrate, the second concentration and the heat treatment conditions being selected such that the oxide layer has a thickness above the alignment units that is larger, by at least 10 nm, than the thickness of the oxide layer above an area of the substrate adjacent to the alignment units; depositing an antireflection layer onto the oxide layer; and depositing an electrode onto the antireflection coating, through a screen, opposite the second region.. .
Commissariat A L'energie Atomique Et Aux Energies Alternatives


new patent Method for producing solar cells having simultaneously etched-back doped regions
A method for producing a solar cell is described, in which a plurality of doped regions are to be etched-back selectively or over their entire surface. Once a semiconductor substrate (1) has been provided, various doped regions (3, 5) are formed in partial regions of a surface of the semiconductor substrate, the various doped regions (3, 5) differing as regards their doping concentration and/or their doping polarity.
UniversitÄt Konstanz


new patent Solar cell and solar cell module
A solar cell and a solar cell module are disclosed. The solar cell includes a semiconductor substrate, an emitter region extending in a first direction, a back surface field region extending in the first direction in parallel with the emitter region, a first electrode connected to the emitter region and extending in the first direction, and a second electrode connected to the back surface field region and extending in the first direction.
Lg Electronics Inc.


new patent Photoactive semiconductor component and producing a photoactive semiconductor component
The invention relates to a photoactive semiconductor component, especially a photovoltaic solar cell, having a semiconductor substrate, a carbon-containing sic layer disposed indirectly upon a surface of the semiconductor substrate, and a passivating intermediate layer disposed indirectly or directly between the sic layer and semiconductor substrate, and a metallic contact connection disposed indirectly or directly upon a side of the sic layer facing away from the passivating intermediate layer and in electrically conductive connection with the sic layer, where the sic layer has p-type or n-type doping, which is characterized in that the sic layer partly has a partly amorphous structure and partly has a crystalline structure.. .
Fraunhofer-gesellschaft Zur Forderung Der Angewandten Forschung E.v.


new patent Semiconductor device
A semiconductor device is provided comprising a semiconductor substrate of a first conductivity type and a dummy trench portion having a main body portion and one or more branch portions, the main body portion formed in a front surface of the semiconductor substrate and extending in a predetermined extending direction, the branch portions extending from the main body portion in directions different from the extending direction. The semiconductor substrate has an emitter region of first conductivity type and a base region of a second conductivity type which are provided sequentially from the front surface side of the semiconductor substrate, and the dummy trench portion has a dummy trench which penetrates the emitter region and the base region from the front surface of the semiconductor substrate, and a dummy insulating portion which is provided within the dummy trench..
Fuji Electric Co., Ltd.


new patent Semiconductor device
An improvement is achieved in the reliability of a semiconductor device having an igbt. In an active cell region, in a portion of a semiconductor substrate which is interposed between first and second trenches in which first and second trench gate electrodes are embedded, an n+-type emitter region, a p-type body region located thereunder, and a first n-type hole barrier region located thereunder are formed.
Renesas Electronics Corporation


new patent Field-plate structures for semiconductor devices
Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor structure includes a semiconductor substrate, a source ohmic contact, a drain ohmic contact, and a gate contact disposed over a gate region between the source ohmic contact and the drain ohmic contact, and a source field plate connected to the source ohmic contact.
Cambridge Electronics, Inc.


new patent

Semiconductor device and a forming a semiconductor device

A method for forming a semiconductor device includes forming at least one graphene layer on a surface of a semiconductor substrate. The method further includes forming a silicon carbide layer on the at least one graphene layer..
Infineon Technologies Ag

new patent

Semiconductor device and manufacturing the same

A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the soi substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed.

new patent

Semiconductor device

A semiconductor device including a semiconductor substrate of a first conductivity type, a plurality of base regions of a second conductivity type formed on a first principal surface of the semiconductor substrate via a semiconductor layer of the first conductivity type, and a plurality of source regions of the first conductivity type formed in the base regions. Each base region, in a top-down view from an angle perpendicular to the first principle surface, is of a polygonal shape.
Fuji Electric Co., Ltd.

new patent

Cmos image sensor with pump gate and extremely high conversion gain

Some embodiments relate to an image sensor pixel comprising a transfer gate formed on a first surface of a semiconductor substrate, a floating diffusion formed in the first surface of the semiconductor substrate, and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially beneath the transfer gate. The transfer gate is spaced away from the floating diffusion such that an intervening semiconductor region provides a potential barrier to charge flow from beneath the transfer gate to the floating diffusion.
Dartmouth College

new patent

Soi-based semiconductor device with dynamic threshold voltage

A semiconductor device includes a semiconductor substrate, an insulating layer on a top surface of the substrate, and a first semiconductor transistor on the insulating layer, the transistor including an active region with a source region, a drain region, a channel region between the source and drain regions and a gate structure over the channel region, the gate structure extending beyond the transistor to an adjacent area. An outer well is included in the substrate, an inner well of an opposite type as the outer well situated within the outer well and under the active region and adjacent area, and a contact for the inner well in the adjacent area, the contact surrounding the gate structure.
Globalfoundries Inc.

new patent

Semiconductor device

Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film.
Renesas Electronics Corporation

new patent

Transistor

A transistor includes: a semiconductor substrate; a plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes on the semiconductor substrate; a drain pad on the semiconductor substrate and connected to the plurality of drain electrodes; a metal wiring on the semiconductor substrate and arranged spaced apart from, adjacent to and parallel to the drain pad; and a ground pad on the semiconductor substrate and connected to both ends of the metal wiring.. .
Mitsubishi Electric Corporation

new patent

Semiconductor device with a switchable and a non-switchable diode region

A semiconductor device includes at least one igbt cell region, at least one switchable free-wheeling diode region, and at least one non-switchable free-wheeling diode region integrated in the same semiconductor substrate as the at least one igbt cell region and the at least one switchable free-wheeling diode region.. .
Infineon Technologies Ag

new patent

Semiconductor device

In order to reduce electric field concentration in a semiconductor device including a main transistor section and a sense transistor section, the semiconductor device is provided, the semiconductor device including a semiconductor substrate of a first conductivity type, a main transistor section in an active region on the semiconductor substrate, and a sense transistor section outside the active region on the semiconductor substrate, wherein the active region is provided with a main well region of a second conductivity type, and wherein the sense transistor section has a sense gate trench section formed extending from the outside of the active region to the main well region on the front surface of the semiconductor substrate.. .
Fuji Electric Co., Ltd.

new patent

Method of producing a semiconductor device with through-substrate via covered by a solder ball

A semiconductor substrate is provided with a through-substrate via comprising a metallization and an opening. A solder ball is placed on the opening.
Ams Ag

new patent

Transmission line for 3d integrated circuit

A semiconductor transmission line substructure and methods of transmitting rf signals are described. The semiconductor transmission line substructure can include a substrate; a first signal line over the substrate; a first ground line over the substrate; and a second semiconductor substrate over the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Through-body via liner deposition

Techniques are disclosed for through-body via liner structures and processes of forming such liner structures in an integrated circuit. In an embodiment, an integrated circuit includes a silicon semiconductor substrate having one or more through-silicon vias (tsvs), although other through-body vias can be used as will be appreciated in light of this disclosure.
Intel Corporation

new patent

Semiconductor device having structure for improving voltage drop and device including the same

A semiconductor device includes a semiconductor substrate and a plurality of metal layers above the semiconductor substrate. A first of the metal layers includes a plurality of first power rails which extend in a first direction and provide a first voltage, a plurality of second power rails which extend in the first direction and provide a second voltage, and a first conductor which is integral with one end of each of the first power rails and extends in a second direction.
Samsung Electronics Co., Ltd.

new patent

Interconnect structure including middle of line (mol) metal layer local interconnect on etch stop layer

An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer.
Globalfoundries, Inc.

new patent

Method for preparing low-warpage semiconductor substrate

Disclosed is a method for preparing a low-warpage semiconductor substrate. The method includes: providing a first substrate and a second substrate, the first substrate including a first surface and a second surface which are opposite to each other, a first insulating layer is disposed on the first surface.
Shanghai Simgui Tehcnology Co., Ltd.

new patent

Methods of manufacturing semiconductor devices including isolation layers

A method of manufacturing a semiconductor device comprising the steps of: forming a trench at an upper portion of a semiconductor substrate forming a preliminary filling insulation layer by coating a siloxane composition on the semiconductor substrate to fill the trench performing a low temperature curing process at a temperature in a range from about 50° c. To about 150° c.
Samsung Electronics Co., Ltd.

new patent

3d ic bump height metrology apc

The present disclosure relates to a method of bump metrology that relies upon advanced process control (apc) to provide substrate warpage parameters describing a warpage of a substrate to a bump metrology module to improve focus of the bump metrology module. In some embodiments, the method measures one or more substrate warpage parameters of a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

new patent

Semiconductor device and semiconductor device manufacturing method

Protons are injected from a back surface side of a semiconductor substrate to repair both defects within the semiconductor substrate and also defects in a channel forming region on a front surface side of the semiconductor substrate. As a result, variation in gate threshold voltage is reduced and leak current when a reverse voltage is applied is reduced.
Fuji Electric Co., Ltd.

new patent

Semiconductor structure and manufacture method thereof

A method of making a semiconductor structure can include: (i) forming a plurality of oxide layers on a semiconductor substrate; (ii) forming a plurality of conductor layers on the plurality of oxide layers; (iii) forming plurality of thickening layers on the plurality of conductor layers; (iv) patterning the plurality of conductor layers and the plurality of thickening layers to form a hard mask; and (v) implanting ion using the hard mask to form a plurality of doped regions.. .
Silergy Semiconductor Technology (hangzhou) Ltd

new patent

Method for manufacturing semiconductor device

There are prepared a semiconductor substrate having a first main surface and a second main surface, and an adhesive tape having a third main surface and a fourth main surface, the first main surface having a maximum diameter of not less than 100 mm. The semiconductor substrate fixed to the third main surface of the adhesive tape is placed in an accommodation chamber.
Sumitomo Electric Industries, Ltd.

new patent

Semiconductor substrates and methods for processing semiconductor substrates

Semiconductor substrates and methods for fabricating integrated circuits are provided. A method for fabricating an integrated circuit includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region.
Globalfoundries, Inc.

new patent

Pressure sensor with built in stress buffer

A semiconductor pressure sensor comprising: a semiconductor substrate having a through-opening extending from a top surface to a bottom surface of the substrate, the through-opening forming a space between an inner part and an outer part of said substrate; a pressure responsive structure arranged on said inner part; a number of flexible elements extending from said inner part to said outer part for suspending the inner part within said through-opening; the through-opening being at least partly filled with an anelastic material. A method of producing such a semiconductor pressure sensor..
Melexis Technologies Nv

new patent

Integrated semiconductor device and manufacturing method

The present disclosure relates to an integrated semiconductor device, comprising a semiconductor substrate; a cavity formed into the semiconductor substrate; a sensor portion of the semiconductor substrate deflectably suspended in the cavity at one side of the cavity via a suspension portion of the semiconductor substrate interconnecting the semiconductor substrate and the sensor portion thereof, wherein an extension of the suspension portion along the side of the cavity is smaller than an extension of said side of the cavity.. .
Infineon Technologies Dresden Gmbh

Solid-state imaging device and imaging apparatus

The solid-state imaging device includes a semiconductor layer 11 in which a surface side becomes a circuit formation surface, photoelectric conversion units pd1 and pd2 of two layers or more that are stacked and formed in the semiconductor layer 11, and a longitudinal transistor tr1 in which a gate electrode 21 is formed to be embedded in the semiconductor layer 11 from a surface 15 of the semiconductor layer 11. The photoelectric conversion unit pd1 of one layer in the photoelectric conversion units of the two layers or more is formed over a portion 21a of the gate electrode 21 of the longitudinal transistor tr1 embedded in the semiconductor substrate 11 and is connected to a channel formed by the longitudinal transistor tr1..

Solid-state imaging device, production the same, and imaging apparatus

A solid-state imaging device in which a pixel circuit formed on the first surface side of a semiconductor substrate is shared by a plurality of light reception regions and second surface side of the semiconductor substrate is the light incident side of the light reception regions. The second surface side regions of the light reception regions are arranged at approximately even intervals and the first surface side regions of the light reception regions e are arranged at uneven intervals.
Sony Corporation

Algainp-based semiconductor laser

An aluminium gallium indium phosphide (algainp)-based semiconductor laser device is provided. On a main surface of a semiconductor substrate formed of n-type gaas (gallium arsenide), from the bottom layer, an n-type buffer layer, an n-type cladding layer formed of an algainp-based semiconductor containing silicon (si) as a dopant, an active layer, a p-type cladding layer formed of an algainp-based semiconductor containing magnesium (mg) or zinc (zn) as a dopant, an etching stopper layer, and a p-type contact layer are formed.
Ushio Opto Semiconductors, Inc.

Structured silicon-based thermal emitter

An optical radiation source produced from a disordered semiconductor material, such as black silicon, is provided. The optical radiation source includes a semiconductor substrate, a disordered semiconductor structure etched in the semiconductor substrate and a heating element disposed proximal to the disordered semiconductor structure and configured to heat the disordered semiconductor structure to a temperature at which the disordered semiconductor structure emits thermal infrared radiation..
Si-ware Systems

Solar cell module

A solar cell module includes a plurality of solar cells, each solar cell including a semiconductor substrate, an emitter region, a back surface field region a first electrode connected to the emitter region, a second electrode connected to the back surface field region, and a conductive line connected to one electrode of the first and second electrodes using a conductive adhesive and insulated from the other electrode of the first and second electrodes through an insulating layer, the conductive line being used to connect a plurality of solar cells in series. A thickness of the conductive adhesive between the one electrode and the conductive line is greater than a thickness of the insulating layer between the other electrode and the conductive line..
Lg Electronics Inc.

Solar cell and manufacturing the same

Disclosed is method of manufacturing a solar cell including forming a barrier film over at least one surface of a semiconductor substrate or a semiconductor layer, forming a first conductive area on the at least one surface of the semiconductor substrate or the semiconductor layer via ion implantation of a first conductive dopant through the barrier film, and removing the barrier film.. .
Lg Electronics Inc.

Solar cell module

A solar cell module includes a plurality of solar cells each including a semiconductor substrate, an emitter region forming a p-n junction along with the semiconductor substrate, a first electrode connected to the emitter region, and a second electrode connected to a back surface of the semiconductor substrate; and a plurality of wiring members connected to the first electrode or the second electrode and configured to electrically connect the plurality of solar cells in series, wherein a number of wiring members connected to the first electrode or the second electrode of each solar cell is 6 to 30, and the wiring members have a circular cross-section.. .
Lg Electronics Inc.

Solar cell and solar cell module

A solar cell is provided with: a semiconductor substrate having a main surface; a plurality of first electrodes disposed so as to be aligned in one direction on the main surface of the semiconductor substrate, the first electrodes having obverse and side surfaces; a passivation layer disposed on the main surface of the semiconductor substrate and positioned in the gaps between the first electrodes; a conductive adhesive disposed on the obverse surfaces of the first electrodes; and lead members connected to adjacent first electrodes by the conductive adhesive so as to straddle the passivation layer. The solar cell is further provided with contact members, the contact members being positioned in gaps, being disposed on the obverse surface of the passivation layer or the main surface of the semiconductor substrate in alignment with the passivation layer in one direction, and being in contact with parts of the lead members from underneath..
Kyocera Corporation

Semiconductor device and manufacturing method thereof

A terminal structure includes: a first trench extending along a depth direction from an upper surface of a semiconductor substrate; a plurality of second trenches, each of which extends along the depth direction from a bottom surface of the first trench and which are arranged at intervals in a direction away from an element portion; a plurality of first floating regions having a floating potential, each of which is exposed at the bottom surface of the first trench, is disposed between the second trenches, and forms a pn-junction with a surrounding region thereof; and a plurality of second floating regions having a floating potential, each of which is exposed at a bottom surface of the second trench and forms a pn-junction with a surrounding region thereof. The plurality of second floating regions is arranged to be separated from each other in the direction away from the element portion..
Denso Corporation

Trench mosfet with depleted gate shield and manufacture

A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type.
Great Wall Semiconductor Corporation

Semiconductor device and manufacturing semiconductor device

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first main surface side of the first semiconductor substrate and a first main surface side of the second semiconductor substrate being bonded to each other; and a warpage correction layer which is formed on at least one or more selected from the first main surface side of the first semiconductor substrate, the first main surface side of the second semiconductor substrate, a second main surface side of the first semiconductor substrate, and a second main surface side of the second semiconductor substrate.. .
Sony Corporation

Image sensor pixels with light guides and light shield structures

A front-side illuminated image sensor with an array of image sensor pixels is provided. Each image pixel may include a photodiode, transistor gate structures, shallow trench isolation structures, and other associated pixel circuits formed in a semiconductor substrate.
Semiconductor Components Industries, Llc

Solid-state image pickup device

A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2.
Sony Corporation

Bridging local semiconductor interconnects

A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. Cmos/pmos areas, source/drain regions, etc.) and one or more inner active areas.
Stmicroelectronics, Inc.

Split gate non-volatile memory cell having a floating gate, word line, erase gate, and manufacturing

A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate.
Silicon Storage Technology, Inc.

Semiconductor device

A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the x direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the x direction; first and second active regions arranged on the opposite sides of the reference potential wire in the y direction; and a gate electrode layer extending in the y direction in such a manner as to cross with the first and second active regions.
Renesas Electronics Corporation

Method and design of low sheet resistance meol resistors

An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (sti) region in the semiconductor substrate; one or more active devices formed on the semiconductor substrate; and a resistor array having a plurality of resistors disposed above the sti region; wherein the resistor array comprises a portion of one or more interconnect contact layers that are for interconnection to the one or more active devices.. .
Xilinx, Inc.

Semiconductor device and manufacturing semiconductor device

A semiconductor device, in which, in a density distribution of first conductivity type impurities in the first conductivity type region measured along a thickness direction of the semiconductor substrate, a local maximum value n1, a local minimum value n2, a local maximum value n3, and a density n4 are formed in this order from front surface side, a relationship of n1>n3>n2>n4 is satisfied, a relationship of n3/10>n2 is satisfied, and a distance “a” from the surface to the depth having the local maximum value n1 is larger than twice a distance “b” from the depth having the local maximum value n1 to the depth having the local minimum n2.. .
Toyota Jidosha Kabushiki Kaisha

Silicon controlled rectifier

A silicon controlled rectifier, an electrostatic discharge (esd) protection circuit including the silicon controlled rectifier and an integrated circuit including the silicon controlled rectifier or esd protection circuit. The silicon controlled rectifier includes a first region having a first conductivity type and a second region having a second conductivity type located adjacent the first region in a semiconductor substrate.
Nxp B.v.

Electrostatic discharge protection device comprising a silicon controlled rectifier

An electrostatic discharge protection device including a silicon controlled rectifier. In one example, the silicon controlled rectifier includes a first n-type region located in a semiconductor substrate.
Nxp B.v.

Semiconductor device processing material removal

A method of removing at least a portion of a layer of material from over a semiconductor substrate that can include dispensing an etching solution over the semiconductor substrate to form a pool of etching solution on the layer of material, wherein a footprint of the pool of etching solution is less than a footprint of the semiconductor substrate. The pool of etching solution and the semiconductor substrate can be moved with respect to each other.
Deca Technologies Inc.

Semiconductor integrated circuit

A high-resistance region is formed right under a seal ring by irradiating a semiconductor substrate with hydrogen ions or helium ions. The high-resistance region has a greater thickness than an isolation insulating layer formed as a shallow trench isolation (sti) region on the surface of the semiconductor substrate.
Socionext Inc.

Semiconductor device and producing semiconductor device

A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.. .
Socionext Inc.

Methods of manufacturing a semiconductor device by forming a separation trench

A method of manufacturing a semiconductor device includes forming a separation trench into a first main surface of a semiconductor substrate and removing substrate material from a second main surface of the semiconductor substrate, so as to thin the substrate to a thickness of less than 100 μm, the second main surface being opposite to the first main surface, so as to uncover a bottom side of the trench. Additional methods of manufacturing semiconductor devices are provided..
Infineon Technologies Austria Ag



Semiconductor Substrate topics:
  • Semiconductor Substrate
  • Semiconductor
  • Semiconductor Device
  • Gallium Nitride
  • Memory Cell
  • Phase Change Memory
  • Phase Change Material
  • Memory Device
  • Semiconductor Memory
  • Integrated Circuit
  • Transistors
  • Field Effect Transistor
  • Planarization
  • Conductive Layer
  • Semiconductor Devices


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