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Semiconductor Substrate patents



      

This page is updated frequently with new Semiconductor Substrate-related patent applications.




Date/App# patent app List of recent Semiconductor Substrate-related patents
07/14/16
20160205725 
 System and  monitoring temperatures of and controlling multiplexed heater array patent thumbnailSystem and monitoring temperatures of and controlling multiplexed heater array
A system for measuring temperatures of and controlling a multi-zone heating plate in a substrate support assembly used to support a semiconductor substrate in a semiconductor processing includes a current measurement device and switching arrangements. A first switching arrangement connects power return lines selectively to an electrical ground, a voltage supply or an electrically isolated terminal, independent of the other power return lines.
Lam Research Corporation


07/14/16
20160204344 
 Structure and formation  memory device patent thumbnailStructure and formation memory device
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first electrode over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


07/14/16
20160204303 
 Using an active solder to couple a metallic article to a photovoltaic cell patent thumbnailUsing an active solder to couple a metallic article to a photovoltaic cell
Methods include providing a metallic article that is configured to serve as an electrical conduit within a photovoltaic cell. The processes further include providing a semiconductor substrate that includes a coating at a top surface of the semiconductor substrate, where the coating is a dielectric anti-reflective coating, a transparent conductive oxide or an amorphous silicon.
Gtat Corporation


07/14/16
20160204260 
 Structure and formation  finfet device patent thumbnailStructure and formation finfet device
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a fin channel structure over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


07/14/16
20160204258 
 Semiconductor device and  manufacturing the same patent thumbnailSemiconductor device and manufacturing the same
To improve performance of a semiconductor device. Over a semiconductor substrate, a gate electrode is formed via a first insulating film for a gate insulating film, and a second insulating film extends from over a side wall of the gate electrode to over the semiconductor substrate.
Renesas Electronics Corporation


07/14/16
20160204255 
 Method of making a finfet, and finfet formed by the method patent thumbnailMethod of making a finfet, and finfet formed by the method
A method includes forming first and second fins of a finfet extending above a semiconductor substrate, with a shallow trench isolation (sti) region in between, and a distance between a top surface of the sti region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the sti region.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/14/16
20160204253 
 Iii-v mosfet with strained channel and semi-insulating bottom barrier patent thumbnailIii-v mosfet with strained channel and semi-insulating bottom barrier
Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a semiconductor substrate. A channel is formed on the bottom barrier.
International Business Machines Corporation


07/14/16
20160204252 
 Semiconductor device patent thumbnailSemiconductor device
A plurality of unit misfet elements connected in parallel with each other to make up a power misfet are formed in an ldmosfet forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power misfet is formed in a driver circuit region on the main surface of the semiconductor substrate.
Renesas Electronics Corporation


07/14/16
20160204246 
 Ge and iii-v channel semiconductor devices having maximized compliance and free surface relaxation patent thumbnailGe and iii-v channel semiconductor devices having maximized compliance and free surface relaxation
Ge and iii-v channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such ge and iii-v channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate.
Intel Corporation


07/14/16
20160204238 
 Igbt having deep gate trench patent thumbnailIgbt having deep gate trench
There are disclosed herein various implementations of an insulated-gate bipolar transistor (igbt) with buried depletion electrode. Such an igbt may include a collector at a bottom surface of a semiconductor substrate, a drift region having a first conductivity type situated over the collector, and a base layer having a second conductivity type opposite the first conductivity type situated over the drift region.
Infineon Technologies Americas Corp.


07/14/16
20160204237 

Semiconductor device


A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth p layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth p layers respectively have surface concentrations p(1) to p(4) that decrease in this order, bottom-end distances d(1) to d(4) that increase in this order, and distances b(1) to b(4) to the edge of the semiconductor substrate that increase in this order.
Mitsubishi Electric Corporation


07/14/16
20160204224 

Tunnel field-effect transistor, manufacturing same, and switch element


A tunnel field-effect transistor (tfet) is configured by disposing a iii-v compound semiconductor nano wire on a (111) plane of a iv semiconductor substrate exhibiting p-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate. Alternatively, the tunnel field-effect transistor is configured by disposing a iii-v compound semiconductor nano wire on a (111) plane of a iv semiconductor substrate exhibiting n-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate.
Japan Science And Technology Agency


07/14/16
20160204223 

High voltage device fabricated using low-voltage processes


A method for fabricating a high-voltage transistor on a semiconductor substrate includes defining and forming shallow trench isolation regions for all of the transistors, defining and forming well regions for all of the transistors, forming a gate oxide layer in the well regions for all of the transistor, forming gates for all of the transistors over the gate oxide layer, implanting a dopant to form lightly-doped drain regions for all of the transistors, the lightly-doped drain regions for at least drains of the high-voltage transistors being spaced apart from an inner edge of the shallow trench isolation regions, forming gate spacers at sides of the gates of all of the transistors, and implanting a dopant to form sources and drains for all of the transistors, the drains of the high-voltage transistors being formed completely surrounded by the lightly-doped drain regions of the high-voltage transistors.. .
Microsemi Soc Corporation


07/14/16
20160204210 

Semiconductor device having field plate structures and gate electrode structures between the field plate structures


A semiconductor device includes a field effect transistor in a semiconductor substrate having a first surface. The field effect transistor includes a first field plate structure and a second field plate structure, each extending in a first direction parallel to the first surface, and gate electrode structures disposed over the first surface and extending in a second direction parallel to the first surface, the gate electrode structures being disposed between the first and the second field plate structures..
Infineon Technologies Austria Ag


07/14/16
20160204179 

Light emitting device and electronic apparatus


On a semiconductor substrate, a plurality of transistors that includes a drive transistor which controls a drive current according to a potential of a gate, a light emitting element that emits a light having a brightness corresponding to the drive current, and an element isolation portion that electrically isolates each transistor are formed. The element isolation portion has a structure in which an insulator fills inside of a groove formed on the semiconductor substrate..
Seiko Epson Corporation


07/14/16
20160204163 

Variable resistance memory device and manufacturing the same


A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.. .
Sk Hynix Inc.


07/14/16
20160204156 

Solid-state imaging device and electronic apparatus


There is provided a solid-state imaging device including: one or more photoelectric conversion elements provided on side of a first surface of a semiconductor substrate; a through electrode coupled to the one or more photoelectric conversion elements, and provided between the first surface and a second surface of the semiconductor substrate; and an amplifier transistor and a floating diffusion provided on the second surface of the semiconductor substrate, in which the one or more photoelectric conversion elements are coupled to a gate of the amplifier transistor and the floating diffusion via the through electrode.. .
Sony Corporation


07/14/16
20160204153 

Solid-state imaging apparatus, manufacturing method therefor, and electronic apparatus


A charge accumulation section that is formed on a first semiconductor substrate and accumulates photoelectrically converted charges, a charge-retaining section that is formed on a second semiconductor substrate and retains charges accumulated in the charge accumulation section, and a transfer transistor that is formed on the first semiconductor substrate and the second semiconductor substrate and transfers charges accumulated in the charge accumulation section to the charge-retaining section are provided. A bonding interface between the first semiconductor substrate and the second semiconductor substrate is formed in a channel of the transfer transistor..

07/14/16
20160204149 

Semiconductor switching device separated by device isolation


A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


07/14/16
20160204145 

Image pickup element, manufacturing image pickup element, and electronic apparatus


An image pickup element includes: a semiconductor substrate including a photoelectric conversion section for each pixel; a pixel separation groove provided in the semiconductor substrate; and a fixed charge film provided on a light-receiving surface side of the semiconductor substrate, wherein the fixed charge film includes a first insulating film and a second insulating film, the first insulating film being provided contiguously from the light-receiving surface to a wall surface and a bottom surface of the pixel separation groove, and the second insulating film being provided on a part of the first insulating film, the part corresponding to at least the light-receiving surface.. .
Sony Corporation


07/14/16
20160204140 

Solid-state imaging element and electronic device


The solid-state imaging element includes a high-concentration diffusion layer configured to serve as a connection portion by which a wiring is connected to a semiconductor substrate, and a junction leak control film formed to cover a surface of the diffusion layer. Also, to connect the wiring to the diffusion layer, a width of an opening formed in an insulation film stacked on the semiconductor substrate is greater than a width of the diffusion layer.

07/14/16
20160204132 

Finfet with reduced capacitance


A structure including a gate electrode above and perpendicular to a plurality of semiconductor fins, a pair of spacers disposed on opposing sides of the gate electrode, and a gap fill material above a semiconductor substrate, directly below the gate electrode, and between the plurality of fins, the gate electrode separates the gap fill material from each of the plurality of fins.. .
International Business Machines Corporation


07/14/16
20160204129 

Fdsoi - capacitor


A method of manufacturing a semiconductor device including a capacitor structure is provided, including the steps of providing an soi wafer comprising a substrate, a buried oxide (box) layer formed over the substrate and a semiconductor layer formed over the box layer, removing the semiconductor layer in a first region of the wafer to expose the box layer, forming a dielectric layer over the exposed box layer in the first region, and forming a conductive layer over the dielectric layer. Moreover, a semiconductor device including a capacitor formed on a wafer is provided, wherein the capacitor comprises a first capacitor electrode comprising a doped semiconductor substrate of the wafer, a capacitor insulator comprising an ultra-thin box layer of the wafer and a high-k dielectric layer formed on the ultra-thin box layer, and a second capacitor electrode comprising a conductive layer formed over the high-k dielectric layer..
Globalfoundries Inc.


07/14/16
20160204118 

Techniques to avoid or limit implant punch through in split gate flash memory devices


Some embodiments of the present disclosure relate to a flash memory device. The flash memory device includes first and second individual source/drain (s/d) regions spaced apart within a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/14/16
20160204116 

Method for manufacturing a semiconductor device


The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate.
Renesas Electronics Corporation


07/14/16
20160204108 

Cmos transistor, semiconductor device including the transistor, and semiconductor module including the device


Provided are a cmos transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The cmos transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate.

07/14/16
20160204105 

Method and device for a finfet


A method of forming a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of fins formed thereon, a stress layer formed on the top surface of each of the fins, and a plurality of strip-shaped gate structures formed above the stress layers.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204100 

Semiconductor device and formation method thereof


The present disclosure provides a semiconductor device and formation method thereof. A shallow trench isolation structure is formed in a semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204095 

Semiconductor device


A first impurity diffusion region is provided within a semiconductor substrate, a second impurity diffusion region is provided within the first impurity diffusion region, a third impurity diffusion region is provided within the second impurity diffusion region, a first portion of a fourth impurity diffusion region is provided within the second impurity diffusion region so as to be spaced from the third impurity diffusion region, and a second portion of the fourth impurity diffusion region is provided in a third portion of the first impurity diffusion region on a side of a surface of the semiconductor substrate, a first contact is provided so as to be in contact with the second portion, the first contact and the third portion overlap in plan view, and a first power supply is connected to the third impurity diffusion region.. .
Seiko Epson Corporation


07/14/16
20160204086 

Methods of manufacturing wide band gap semiconductor device and semiconductor module, and wide band gap semiconductor device and semiconductor module


A method of manufacturing a wide band gap semiconductor device includes the steps of preparing a wide band gap semiconductor substrate, separating the wide band gap semiconductor substrate into a plurality of first semiconductor chips (80), fixing the plurality of first semiconductor chips (80) on a fixation member (70), measuring a breakdown voltage of each of the first semiconductor chips (80) while immersing at least the first semiconductor chips (80) in inert liquid (91), and after the step of measuring a breakdown voltage of each of the first semiconductor chips (80), providing a plurality of second semiconductor chips each having each of the first semiconductor chips (80) fixed on the fixation member (70), by cutting the fixation member (70).. .
Sumitomo Electric Industries, Ltd.


07/14/16
20160204071 

Semiconductor die and die cutting method


The present disclosure provides die cutting methods and semiconductor dies. A semiconductor substrate has a test region, isolation regions, and core regions.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204066 

Semiconductor device and fabrication method thereof


The present disclosure provides a semiconductor device and fabrication method thereof. A dielectric layer is formed on a first surface of a semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204040 

Manufacturing apparatus of semiconductor device and management manufacturing apparatus of semiconductor device


According to one embodiment, a management method of a manufacturing apparatus of a semiconductor device, the method includes measuring a weight of a pre-exposure substrate including a semiconductor substrate and a resist film provided on the semiconductor substrate, performing an exposure process for the resist film, measuring a weight of a post-exposure substrate including the semiconductor substrate and the resist film after the exposure process is performed, and acquiring a weight difference between the weight of the pre-exposure substrate and the weight of the post-exposure substrate.. .
Kabushiki Kaisha Toshiba


07/14/16
20160204038 

Methods for fabricating integrated circuits with improved implantation processes


Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate.
Globalfoundries, Inc.


07/14/16
20160204031 

Shielded coplanar line


In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.. .
Stmicroelectronics Sa


07/14/16
20160204023 

Manufacturing semiconductor substrate


A technique disclosed herein relates to a manufacturing method for a semiconductor substrate having the bonded interface with high bonding strength without forming an oxide layer at the bonded interface also for the substrate having surface that is hardly planarized. The manufacturing method for the semiconductor substrate may include an amorphous layer formation process in which a first amorphous layer is formed by modifying a surface of a support substrate and a second amorphous layer is formed by modifying a surface of a single-crystalline layer of a semiconductor.
National Institute Of Advanced Industrial Science And Technology


07/14/16
20160204000 

Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device in accordance with the present invention includes the steps of preparing a semiconductor substrate, placing the semiconductor substrate on an electrostatic chuck, chucking the semiconductor substrate after raising a temperature of the electrostatic chuck to a first temperature, raising a temperature of the electrostatic chuck to a second temperature which is higher than the above-described first temperature in a state where the semiconductor substrate is chucked, and performing a treatment to the semiconductor substrate in a state where a temperature of the electrostatic chuck is maintained at the above-described second temperature.. .
Sumitomo Electric Industries, Ltd.


07/14/16
20160203995 

Integrating atomic scale processes: ald (atomic layer deposition) and ale (atomic layer etch)


Methods are provided for integrating atomic layer etch and atomic layer deposition by performing both processes in the same chamber or reactor. Methods involve sequentially alternating between atomic layer etch and atomic layer deposition processes to protect feature degradation during etch, improve selectivity, and encapsulate sensitive layers of a semiconductor substrate..
Lam Research Corporation


07/14/16
20160203990 

Internal plasma grid for semiconductor fabrication


The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers.
Lam Research Corporation


07/14/16
20160203988 

Semiconductor device and fabrication method thereof


The present disclosure provides semiconductor devices and fabrication methods thereof. A work function layer is formed on the semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160203980 

Device isolation for iii-v substrates


Techniques for device isolation for iii-v semiconductor substrates are provided. In one aspect, a method of fabricating a iii-v semiconductor device is provided.
International Business Machines Corporation


07/14/16
20160203973 

Method for the surface treatment of a semiconductor substrate


To apply an anti-wetting coating to a substrate of a semiconductor material, a method includes applying to a support a solution of a hydrocarbon comprising at least one unsaturated bond and, optionally, at least one hetero-atom for obtaining a layer of hydrocarbons. The method also includes treating at least one surface of the substrate of the semiconductor material with an acid.
Stmicroelectronics S.r.l.


07/14/16
20160203971 

Gate stack materials for semiconductor applications for lithographic overlay improvement


Embodiments of the disclosure provide methods and system for manufacturing film layers with minimum lithographic overlay errors on a semiconductor substrate. In one embodiment, a method for forming a film layer on a substrate includes supplying a deposition gas mixture including a silicon containing gas and a reacting gas onto a substrate disposed on a substrate support in a processing chamber, forming a plasma in the presence of the depositing gas mixture in the processing chamber, applying current to a plasma profile modulator disposed in the processing chamber while supplying the depositing gas mixture into the processing chamber, and rotating the substrate while depositing a film layer on the substrate..
Applied Materials, Inc.


07/14/16
20160202349 

Monolithic ultrasonic imaging devices, systems and methods


To implement a single-chip ultrasonic imaging solution, on-chip signal processing may be employed in the receive signal path to reduce data bandwidth and a high-speed serial data module may be used to move data for all received channels off-chip as digital data stream. The digitization of received signals on-chip allows advanced digital signal processing to be performed on-chip, and thus permits the full integration of an entire ultrasonic imaging system on a single semiconductor substrate.
Butterfly Network, Inc.


07/14/16
20160201212 

Multi-contact lipseals and associated electroplating methods


Disclosed herein are lipseal assemblies for use in an electroplating clamshell for engaging and supplying electrical current to a semiconductor substrate during electroplating, which include an elastomeric lipseal for engaging the semiconductor substrate during electroplating, and wherein upon engagement the elastomeric lipseal forms multiple radially-separated sealing contact surfaces with the substrate which substantially exclude plating solution from a peripheral region of the substrate. Said lipseal assemblies may also include one or more electrical contact elements for supplying electrical current to the semiconductor substrate during electroplating..
Lam Research Corporation


07/14/16
20160201123 

Integrated on chip detector and zero waveguide module structure for use in dna sequencing


A semiconductor structure for use in single molecule real time dna sequencing technology is provided. The structure includes a semiconductor substrate including a first region and an adjoining second region.
International Business Machines Corporation


07/07/16
20160198111 

Image capturing apparatus and control method thereof


An image capturing apparatus comprises an image sensor including a first semiconductor substrate on which a photodiode is arranged, a second semiconductor substrate on which a storage element is arranged, and a connection unit configured to electrically connect the photodiode and the storage element, a first transfer unit configured to transfer pixel signals of a first pixel group to the storage element, a first readout unit configured to read out the pixel signals of the first pixel group, a second transfer unit configured to transfer pixel signals of a second pixel group to the storage element, and a second readout unit configured to read out some of the pixel signals of the second pixel group, wherein an image of one frame is generated by composing the pixel signals of the second pixel group and the first pixel group.. .
Canon Kabushiki Kaisha


07/07/16
20160197259 

Thermoelectric devices and systems


The present disclosure provides a thermoelectric element comprising a flexible semiconductor substrate having exposed surfaces with a metal content that is less than about 1% as measured by x-ray photoelectron spectroscopy (xps) and a figure of merit (zt) that is at least about 0.25, wherein the flexible semiconductor substrate has a young's modulus that is less than or equal to about 1×106 pounds per square inch (psi) at 25° c.. .
Silicium Energy, Inc.


07/07/16
20160197216 

Photodiodes including seed layer


A photodiode includes a semiconductor substrate, a crystalline layer on the semiconductor substrate, an insulating pattern layer on the crystalline layer to define a plurality of holes exposing a top surface of the crystalline layer, a seed layer in the plurality of holes and directly on the crystalline layer, and a light absorption layer on the seed layer and the insulating pattern layer.. .
Samsung Electronics Co., Ltd.


07/07/16
20160197209 

Solar cell and manufacturing the same


A method for manufacturing a solar cell according to an embodiment of the invention includes forming an emitter layer having an emitter dopant of a second conductive type opposite to a first conductive type on a first surface on a semiconductor substrate; forming a passivation layer including a first dopant of the first conductive type on a second surface of the semiconductor substrate; forming a back surface field layer including a first portion on the second surface by locally heating a portion of the passivation layer using a laser; and forming an electrode electrically connected to the first portion of the back surface field layer through an opening of the passivation layer after the first portion of the back surface field layer is formed on the second surface, wherein the back surface field layer is locally formed between the electrode and the second surface.. .
Lg Electronics Inc.


07/07/16
20160197208 

Use of metal phosphorus in metallization of photovoltaic devices and fabricating same


A photovoltaic device, such as a solar cell, including a copper-containing-grid metallization structure that contains a metal phosphorus layer as a diffusion barrier is provided. The copper-containing-grid metallization structure includes, from bottom to top, an electroplated metal phosphorus layer that does not include copper or a copper alloy located within a grid pattern formed on a front side surface of a semiconductor substrate, and an electroplated copper-containing layer.
International Business Machines Corporation


07/07/16
20160197204 

Solar cell and manufacturing the same


A solar cell and a method for manufacturing the same are discussed. The solar cell includes a crystalline semiconductor substrate containing impurities of a first conductive type, a tunnel layer positioned on the crystalline semiconductor substrate, a semiconductor layer which is formed on the tunnel layer, has a crystallinity less than the crystalline semiconductor substrate, and includes a first doped region of a second conductive type opposite the first conductive type and a second doped region containing impurities of the first conductive type at a higher concentration than that of the crystalline semiconductor substrate, a first electrode connected to the first doped region, and a second electrode connected to the second doped region..
Lg Electronics Inc.


07/07/16
20160197202 

Oxide semiconductor substrate and schottky barrier diode


A schottky barrier diode element having a silicon (si) substrate, an oxide semiconductor layer and a schottky electrode layer, wherein the oxide semiconductor layer includes a polycrystalline and/or amorphous oxide semiconductor having a band gap of 3.0 ev or more and 5.6 ev or less.. .
Idemitsu Kosan Co., Ltd.


07/07/16
20160197184 

Tunnel field effect transistors having low turn-on voltage


Tunnel field effect transistors include a semiconductor substrate; a source region in the semiconductor substrate; a drain region in the semiconductor substrate; a channel region in the semiconductor substrate between the source region and the drain region; and a gate electrode on the semiconductor substrate above the channel region. The source region comprises a first region having a first conductivity type, a third region having a second conductivity type that is different from the first conductivity type, and a second region having an intrinsic conductivity type that is between the first region and the third region..
Samsung Electronics Co., Ltd.


07/07/16
20160197175 

Semiconductor device structure and forming same


An embodiment is a semiconductor device comprising a first gate structure over a semiconductor substrate, a first etch stop layer (esl) over the semiconductor substrate and the first gate, the first esl having a curved top surface, and a first inter-layer dielectric (ild) on the first esl, the first ild having a curved top surface. The semiconductor device further comprises a second esl on the first ild, the second esl having a curved top surface, and a second ild on the second esl..
Taiwan Semiconductor Manufacturing Company, Ltd.


07/07/16
20160197169 

Injection control in semiconductor power devices


Semiconductor power devices can be formed on substrate structure having a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type. A semiconductive first buffer layer of the first conductivity type formed above the substrate.
Alpha And Omega Semiconductor Incorporated


07/07/16
20160197163 

Manufacturing semiconductor apparatus and semiconductor apparatus


A screen oxide film is formed on an n− drift layer (2) that is disposed on an anterior side of an n-type low-resistance layer (1), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film (61) is formed.
Fuji Electric Co., Ltd.


07/07/16
20160197158 

Low end parasitic capacitance finfet


Embodiments of the present invention provide methods for fabricating a semiconductor device. One method may include providing a semiconductor substrate with fins etched into the semiconductor substrate; forming a gate structure and depositing an insulating material around the gate structure; selectively etching an active device area; forming a set of spacers on the sides of the gate structure; growing a doped source and drain region; depositing an insulator over an upper surface of a deposited etch stop layer; and depositing a metal into a contact opening to form one or more contacts..
International Business Machines Corporation


07/07/16
20160197154 

Iii-v nanowire fet with compositionally-graded channel and wide-bandgap core


A method for fabricating a iii-v nanowire. The method may include providing a semiconductor substrate, which includes an insulator, with a wide-bandgap layer on the top surface of the semiconductor substrate; etching the insulator to suspend the wide-bandgap layer; growing a compositionally-graded channel shell over the wide-bandgap layer; forming a gate structure forming spacers on the sidewalls of the gate structure; and forming a doped raised source drain region adjacent to the spacers..
International Business Machines Corporation


07/07/16
20160197149 

Silicon carbide semiconductor device and manufacturing same


A first electrode being in contact with the first main surface of the silicon carbide semiconductor substrate and in ohmic junction with the silicon carbide semiconductor substrate is formed. At least a portion of the silicon carbide semiconductor substrate on a side of the second main surface is removed.
Sumitomo Electric Industries, Ltd.


07/07/16
20160197120 

Semiconductor storage device


A semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.. .

07/07/16
20160197109 

Solid-state imaging device, production method thereof, and electronic device


Disclosed is a solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a sti structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the sti structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region.
Sony Corporation


07/07/16
20160197095 

Semiconductor device


Disclosed herein is a technique for reducing, in an analog circuit that needs trimming adjustment in a semiconductor device, a variation to be caused in the characteristic of the analog circuit while the circuit is kept in stock for a long time after having been packaged or subjected to a reflow process. An analog circuit including a trimming mechanism for output adjustment is formed on a buried oxide film in a semiconductor substrate.
Panasonic Intellectual Property Management Co., Ltd.


07/07/16
20160197091 

Fabrication method and structure of semiconductor non-volatile memory device


A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film.
Renesas Electronics Corporation


07/07/16
20160197089 

Non-volatile memory cell structure, non-volatile memory array structure and fabricating non-volatile memory cell structure


A nvm cell structure includes a semiconductor substrate having a first conductivity type, a first well region having a second conductivity type, a floating gate transistor and an erase gate region. The first well region is disposed on a first od region of the semiconductor substrate.
Ememory Technology Inc.


07/07/16
20160197085 

Semiconductor structure and fabrication method thereof, and static random access memory cell


A method for forming a semiconductor having a plurality of finfets. The method includes providing a semiconductor substrate having a surface; and forming a plurality of first fins and a plurality of second fins on the surface of the semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/07/16
20160197081 

Semiconductor devices and methods of fabricating the same


Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate.

07/07/16
20160197075 

Fin field effect transistors and fabrication method thereof


A method for forming finfets includes providing a semiconductor substrate having at least a first fin in a first region and at least a second fin in a second region, and a first gate structure over the first fin and a second gate structure over the second fin; forming a first stress layer on the first fin and a first cover layer on the first stress layer; forming a second stress layer on the second fin and a second cover layer on the second stress layer; performing a first potential barrier reducing ion implantation process on the first cover layer; performing a second potential barrier reducing ion implantation process on the second cover layer; forming a first metal layer and a second metal layer; and forming a first contact layer on the first cover layer and a second contact layer on the second cover layer.. .
Semiconductor Manufacturing International (shanghai) Corporation


07/07/16
20160197071 

Integrated circuit device and forming the same


The invention provides an integrated circuit device. The integrated circuit device includes a semiconductor substrate.
Mediatek Inc.


07/07/16
20160197064 

Optoelectronic device comprising light-emitting diodes


An optoelectronic device including a semiconductor substrate that is optionally doped with a first type of conductivity; a first semiconductor region that is electrically connected to the substrate, doped with the first type of conductivity or a second opposite type of conductivity and more strongly doped than the substrate; a first set of first light-emitting diodes resting on the first semiconductor region, the first light-emitting diodes comprising wire-like, conical or frustoconical semiconductor elements; and a conductive portion in contact with the first semiconductor region.. .
Aledia


07/07/16
20160197021 

Semiconductor device and manufacturing method thereof


When vc inspection for a teg is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an sram is formed on an soi substrate in a chip region.
Renesas Electronics Corporation


07/07/16
20160197016 

Method of manufacturing semiconductor device


A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with an insulating layer formed thereon.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/07/16
20160196979 

Self-aligned insulated film for high-k metal gate device


An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ild) on either side of the metal gate structure.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


07/07/16
20160196976 

Method for tuning the effective work function of a metal


The disclosed technology generally relates to integrated circuit devices and methods of forming the same, and more particularly to metal electrodes whose effective work function can be tuned. In one aspect, a method of forming a metal electrode of a semiconductor structure includes providing a semiconductor substrate having at least a region covered with a dielectric.
Imec Vzw


07/07/16
20160195678 

Through-substrate optical coupling to photonics chips


An optoelectronic integrated circuit for coupling light to or from an optical waveguide formed in an optical device layer in a near-normal angle to that layer. In an embodiment, the integrated circuit comprises a semiconductor body including a metal-dielectric stack, an optical device layer, a buried oxide layer and a semiconductor substrate arranged in series between first and second opposite sides of the semiconductor body.
International Business Machines Corporation


06/30/16
20160192082 

Acoustic sensor and manufacturing the same


An acoustic sensor is provided for improving shock resistance performance, along with a method for manufacturing the acoustic sensor. In the acoustic sensor, a fixing plate is provided by a semiconductor manufacturing process, a frame wall has a curved shape in at least a portion of the periphery of the fixing plate, the frame wall being coupled to the semiconductor substrate.

06/30/16
20160191825 

Imaging device including unit pixel cell


An imaging device of the present disclosure includes: a unit pixel cell comprising a photoelectric converter converting incident light into signal charge, a semiconductor substrate, a charge storage region located in the semiconductor substrate and storing the signal charge, and a signal detection circuit detecting the signal charge; a feedback circuit negatively feeding back output of the signal detection circuit and comprising a signal line; and at least one wiring layer located between the semiconductor substrate and the photoelectric converter. The at least one wiring layer includes a portion of the signal line, the portion overlapping the unit pixel cell in a plan view.

06/30/16
20160191058 

Integrated circuit layout wiring for multi-core chips


An integrated circuit system-on-chip (soc) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip.

06/30/16
20160190930 

Semiconductor device


Provided is a semiconductor device including: a dc/dc converter circuit, wherein the dc/dc converter circuit includes a transistor of a normally-off type, having a first drain electrode connected town input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.. .

06/30/16
20160190375 

Hetero-junction solar cell and manufacturing method thereof


A hetero junction solar cell includes a semiconductor substrate, a first n-type buffer layer, a second n-type buffer layer, a first amorphous silicon layer, a second amorphous silicon layer, a first tco layer and a second tco layer. The first n-type buffer layer and the second n-type buffer layer are formed respectively on a first surface and a second surface of the semiconductor substrate.

06/30/16
20160190374 

Thin film type solar cell and fabrication method thereof


A method of fabricating a solar cell includes forming a doped portion having a first conductive type on a semiconductor substrate, growing an oxide layer on the semiconductor substrate, forming a plurality of recess portions in the oxide layer, further growing the oxide layer on the semiconductor substrate, forming a doped portion having a second conductive type on areas of the semiconductor substrate corresponding to the recess portions, forming a first conductive electrode electrically coupled to the doped portion having the first conductive type, and forming a second conductive electrode on the semiconductor substrate and electrically coupled to the doped portion having the second conductive type, wherein a gap between the doped portions having the first and second conductive types corresponds to a width of the oxide layer formed by further growing the oxide layer.. .

06/30/16
20160190349 

E-flash si dot nitrogen passivation for trap reduction


The present disclosure relates to a structure and method for reducing dangling bonds around quantum dots in a memory cell. In some embodiments, the structure has a semiconductor substrate having a tunnel dielectric layer disposed over it and a plurality of quantum dots disposed over the tunnel dielectric layer.

06/30/16
20160190335 

Split-gate flash memory having mirror structure and forming the same


Split-gate flash memory and forming method thereof are provided. The method includes: forming a first dielectric layer on a semiconductor substrate; forming a floating gate layer on the first dielectric layer; forming a mask layer on the floating gate layer; etching the mask layer until first groove exposing the floating gate layer is formed; forming a protective sidewall on sidewall of the first groove; forming a gate dielectric layer on bottom and the sidewall of the first groove; forming two control gates on the gate dielectric layer, the remained first groove serving as second groove; etching the gate dielectric layer and the floating gate layer at bottom of the second groove until third groove exposing the first dielectric layer is formed; forming a source in the semiconductor substrate under the third groove; and forming a second dielectric layer in the third groove.

06/30/16
20160190323 

Finfet device including a uniform silicon alloy fin


A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate.

06/30/16
20160190320 

Surface tension modification using silane with hydrophobic functional group for thin film deposition


A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces.

06/30/16
20160190319 

Non-planar semiconductor devices having multi-layered compliant substrates


Non-planar semiconductor devices having multi-layered compliant substrates and methods of fabricating such non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate.

06/30/16
20160190314 

Vertical slit transistor with optimized ac performance


A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent respective sidewalls of the semiconductor substrate.

06/30/16
20160190308 

Silicon-carbide trench gate mosfets


In a general aspect, an apparatus can include a semiconductor substrate, a drift region disposed in the semiconductor substrate; a body region disposed in the drift region and a source region disposed in the body region. The apparatus can also include a gate trench disposed in the semiconductor substrate.

06/30/16
20160190306 

Finfet device with a substantially self-aligned isolation region positioned under the channel region


One illustrative device disclosed herein includes, among other things, a semiconductor substrate, a fin structure, a gate structure positioned around a portion of the fin structure in the channel region of the device, spaced-apart portions of a second semiconductor material positioned vertically between the fin structure and the substrate, wherein the second semiconductor material is a different semiconductor material than that of the fin, and a local channel isolation material positioned laterally between the spaced-apart portions of the second semiconductor material and vertically below the fin structure and the gate structure, wherein the local channel isolation material is positioned under at least a portion of the channel region of the device.. .

06/30/16
20160190305 

Structure and 3d finfet metal gate


The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate; wherein the gate stack includes a high k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer, wherein the gate stack has a convex top surface..

06/30/16
20160190283 

Fabrication of mosfet device with reduced breakdown voltage


Fabricating a semiconductor device comprises: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer; forming a source embedded in the body; forming a contact trench that extends through the source and at least part of the body; disposing an implant at least along a contact trench wall; and disposing an epitaxial enhancement portion below the contact trench and in contact with the implant.. .

06/30/16
20160190280 

Structure and formation semiconductor device structure with gate stack


Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate.

06/30/16
20160190265 

Split-gate trench power mosfet with protected shield oxide


A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region.

06/30/16
20160190262 

Confined early epitaxy with local interconnect capability


A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate and surrounded at a lower portion thereof by a layer of isolation material, gate structure(s) and confined epitaxial material above active regions of the raised structures, the confined epitaxial material having recessed portion(s) therein. Dummy gate structures surrounding a portion of each of the raised structures are initially used, and the confined epitaxial material is created before replacing the dummy gate structures with final gate structures.

06/30/16
20160190256 

Semiconductor device including a transistor with a gate dielectric having a variable thickness


A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode.

06/30/16
20160190255 

Methods for forming finfets having a capping layer for reducing punch through leakage


A method for forming finfets having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer.

06/30/16
20160190250 

V-shaped epitaxially formed semiconductor layer


The present disclosure provides a method in accordance with some embodiments. The method includes forming a recess in a source/drain region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material.

06/30/16
20160190243 

Structure and formation finfet device


Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and a fin structure over the semiconductor substrate.

06/30/16
20160190242 

Fin recess last process for finfet fabrication


A method includes forming isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a hard mask strip over the isolation regions and a semiconductor strip, wherein the semiconductor strip is between two neighboring ones of the isolation regions. A dummy gate strip is formed over the hard mask strip, wherein a lengthwise direction of the dummy gate strip is perpendicular to a lengthwise direction of the semiconductor strip, and wherein a portion of the dummy gate strip is aligned to a portion of the semiconductor strip.

06/30/16
20160190240 

Semiconductor structure and manufacturing method thereof


A semiconductor structure includes a semiconductor substrate, a first active area, a second active area, a first trench, at least one raised portion, and a first dielectric. The first active area is in the semiconductor substrate.

06/30/16
20160190236 

Finfet and manufacturing the same


There is provided a method of manufacturing a fin field effect transistor (finfet). The method may include: forming a fin on a semiconductor substrate; forming a dummy device including a dummy gate on the fin; forming an interlayer dielectric layer to cover regions except for the dummy gate; removing the dummy gate to form an opening; implanting ions to form a punch-though-stop layer (ptsl) in a portion of the fin directly under the opening, while forming reflection doped layers in portions of the fin on inner sides of source/drain regions; and forming a replacement gate in the opening..

06/30/16
20160190231 

Semiconductor switch


According to an embodiment, a semiconductor switch includes a first insulating film on a semiconductor substrate, a first semiconductor layer on the first insulating film, a semiconductor switch circuit on the first semiconductor layer, and a wiring on the first insulating film. The first insulating film being between the wiring and the substrate.

06/30/16
20160190230 

Unknown


In a method for producing a capacitor, a dielectric structure is generated in a trench of a semiconductor substrate. The dielectric structure includes a plurality of adjacent dielectric layers having opposing material tensions..

06/30/16
20160190207 

Integrated circuits including magnetic tunnel junctions for magnetoresistive random-access memory and methods for fabricating the same


Integrated circuits that include a magnetic tunnel junction (mtj) for a magnetoresistive random-access memory (mram) and methods for fabricating such integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a lower electrode on a metal interconnect.

06/30/16
20160190206 

Acoustic wave device structure, integrated structure of power amplifier and acoustic wave device, and fabrication methods thereof


An integrated structure of power amplifier and acoustic wave device comprises: a compound semiconductor epitaxial substrate, a power amplifier upper structure formed on a first side of said compound semiconductor epitaxial substrate, and a film bulk acoustic resonator formed on a second side of said compound semiconductor epitaxial substrate; wherein forming an epitaxial structure on a compound semiconductor substrate to form said compound semiconductor epitaxial substrate; wherein said first side of said compound semiconductor epitaxial substrate and said power amplifier upper structure form a power amplifier; said second side of said compound semiconductor epitaxial substrate and said film bulk acoustic resonator form an acoustic wave device; the integrated structure of power amplifier and acoustic wave device on the same compound semiconductor epitaxial substrate is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between power amplifier and acoustic wave device.. .

06/30/16
20160190201 

Image sensors employing sensitized semiconductor diodes


In various example embodiments, the inventive subject matter is an image sensor and methods of formation of image sensors. In an embodiment, the image sensor comprises a semiconductor substrate and a plurality of pixel regions.

06/30/16
20160190200 

Solid-state imaging device, manufacturing method thereof, and electronic apparatus


A solid-state imaging device having a backside illuminated structure, includes: a pixel region in which pixels each having a photoelectric conversion portion and a plurality of pixel transistors are arranged in a two-dimensional matrix; an element isolation region isolating the pixels which is provided in the pixel region and which includes a semiconductor layer provided in a trench by an epitaxial growth; and a light receiving surface at a rear surface side of a semiconductor substrate which is opposite to a multilayer wiring layer.. .

06/30/16
20160190146 

Integrated circuits and methods for fabricating memory cells and integrated circuits


Integrated circuits and methods fabricating memory cells and integrated circuits are provided. In one embodiment, a method for fabricating a memory cell includes doping a semiconductor substrate to define a conductive region.

06/30/16
20160190144 

Method of manufacturing semiconductor device


Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a misfet is formed.

06/30/16
20160190143 

Interdigitated capacitor to integrate with flash memory


Some embodiments relate to an integrated circuit (ic). The ic includes a semiconductor substrate including a flash memory region and a capacitor region.

06/30/16
20160190134 

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.. .

06/30/16
20160190130 

Method for forming single diffusion breaks between finfet devices and the resulting devices


A method includes forming a fin in a semiconductor substrate. A plurality of sacrificial gate structures are formed above the fin.

06/30/16
20160190125 

Semiconductor device having switchable regions with different transconductances


A semiconductor device includes a semiconductor substrate having an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells and the outer rim. Each of the switchable cells includes a gate electrode structure.

06/30/16
20160190122 

Method for finfet integrated with capacitor


A semiconductor structure comprises a semiconductor substrate and a shallow trench isolation (sti) feature over the substrate. The sti feature includes first and second portions.

06/30/16
20160190102 

Semiconductor device and manufacturing same


In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a first semiconductor substrate having a first surface and a second surface opposite the first surface, a first insulating film formed on the first surface, a first hole formed in the first insulating film and partially extending into the first semiconductor substrate, a second hole formed in the second surface, a first electrode entirely filling the first hole, and a conductive film conformally formed in the second hole.

06/30/16
20160190079 

Semiconductor substrate and semiconductor package structure having the same


The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump.

06/30/16
20160190051 

Electronic device


An electronic device, suitable for achieving a smaller size, includes a semiconductor substrate having a main surface and a back surface opposite to the main surface, a main electronic element arranged on the substrate, and a conducting layer electrically connected to the main electronic element. The substrate is formed with an element arrangement recessed portion that is recessed from the main surface and in which the main electronic element is arranged.

06/30/16
20160190042 

Devices, manufacturing through-substrate vias and front-side structures


Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (tsvs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening.

06/30/16
20160190021 

Integrated circuits, methods of forming the same, and methods of determining gate dielectric layer electrical thickness in integrated circuits


Integrated circuits, methods of forming integrated circuits, and methods of determining gate dielectric layer electrical thickness in integrated circuits are provided. An exemplary integrated circuit includes a semiconductor substrate including an active region and an sti structure disposed therein, adjacent to the active region.

06/30/16
20160190018 

Device and methods for high-k and metal gate slacks


A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate.

06/30/16
20160190006 

Mechanisms for forming semiconductor device structure with feature opening


A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming a hard mask layer over the dielectric layer.



Semiconductor Substrate topics: Semiconductor Substrate, Semiconductor, Semiconductor Device, Gallium Nitride, Memory Cell, Phase Change Memory, Phase Change Material, Memory Device, Semiconductor Memory, Integrated Circuit, Transistors, Field Effect Transistor, Planarization, Conductive Layer, Semiconductor Devices

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