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Semiconductor Memory patents



      
           
This page is updated frequently with new Semiconductor Memory-related patents. Subscribe to the Semiconductor Memory RSS feed to automatically get the update: related Semiconductor RSS feeds.

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Date/App# patent app List of recent Semiconductor Memory-related patents
04/17/14
20140108808
 Host device, semiconductor memory device, and authentication method patent thumbnailHost device, semiconductor memory device, and authentication method
According to one embodiment, encrypted secret identification information (e-secretid) and the key management information (fkb) are read from a memory device. Encrypted management key (e-fkey) is obtained using the key management information (fkb) and index information (k).
04/17/14
20140108725
 Semiconductor memory device patent thumbnailSemiconductor memory device
A semiconductor memory device includes a memory cell array configured to include sub memory blocks and a redundancy memory block, data line groups configured to deliver data to be programmed into the sub memory blocks and data read from the sub memory blocks, a redundancy data line group configured to deliver data to be programmed into the redundancy memory block and data read from the redundancy memory block, and switching circuits configured to couple selectively the data line groups to the redundancy data line group.. .
04/17/14
20140108714
 Apparatus and method for generating descriptors to transfer data to and from non-volatile semiconductor memory of a storage drive patent thumbnailApparatus and method for generating descriptors to transfer data to and from non-volatile semiconductor memory of a storage drive
A storage drive including first, second, third, fourth and fifth modules. The first module is configured to control transfer of blocks of data between a host device and the storage drive.
04/17/14
20140104971
 Semiconductor memory device patent thumbnailSemiconductor memory device
Disclosed is a semiconductor memory device that includes a sense amplifier section. The sense amplifier section includes first n-type diffusion layers, second n-type diffusion layers, first to fifth gates, and first to eighth contacts.
04/17/14
20140104966
 Data loading circuit and semiconductor memory device comprising same patent thumbnailData loading circuit and semiconductor memory device comprising same
A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.. .
04/17/14
20140104954
 Non-volatile semiconductor memory having multiple external power supplies patent thumbnailNon-volatile semiconductor memory having multiple external power supplies
A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory.
04/17/14
20140104950
 Non-volatile semiconductor memory patent thumbnailNon-volatile semiconductor memory
A non-volatile semiconductor memory includes a memory array. In a programming operation, programming pulses are applied to a page of the memory array to program data to the page.
04/17/14
20140104947
 Non-volatile semiconductor memory data reading method thereof patent thumbnailNon-volatile semiconductor memory data reading method thereof
A non-volatile semiconductor memory includes a memory array, a selecting device selecting a page according to addresses, a data storage device, storing page data, and an output device outputting the stored data. The data storage device includes a first data storage device receiving data from a selected page of the memory array, a second data storage device receiving data from the first data storage device, and a data transmission device configured between the first and the second data storage device.
04/17/14
20140104935
 Semiconductor memory systems with on-die data buffering patent thumbnailSemiconductor memory systems with on-die data buffering
A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams.
04/17/14
20140104933
 Semiconductor memory patent thumbnailSemiconductor memory
Provided is a semiconductor memory in which it is easier to read a read margin when an ambient temperature changes. The semiconductor memory includes: a memory cell including a first variable resistance element having variable electric resistance; a first reference cell including a second variable resistance element having variable electric resistance, and serving as a point of reference for a magnitude of electric resistance of the memory cell; and a second reference cell serving as a point of reference for a magnitude of electric resistance of the first reference cell, in which a first temperature coefficient of the first variable resistance element and a second temperature coefficient of the second variable resistance element have the same polarity..
04/17/14
20140104930
Semiconductor memory device
A semiconductor memory device comprises a memory cell array including plural memory cells provided at the intersections of plural first lines and plural second lines; and a write circuit. The write circuit, on execution of a write operation, executes a first step of applying a voltage across the first and second lines connected to a data-write-targeted, selected memory cell, and a different voltage across the first and second lines connected to a data-write-untargeted, unselected memory cell of the plural memory cells and, after execution of the first step, executes a second step of applying a voltage, required for data write, across the first and second lines connected to the selected memory cell, and bringing at least one of the first and second lines connected to the unselected memory cell into the floating state..
04/17/14
20140104921
Semiconductor memory device having otp cell array
Provided is a semiconductor memory device. The semiconductor includes a one time programmable (otp) cell array, a converging circuit and a sense amplifier circuit.
04/17/14
20140104917
Semiconductor memory device including plurality of memory chips
A semiconductor memory device includes a plurality of memory chips each including a chip identification (id) generation circuit. The chip id generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip id generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip id numbers of the plurality of device chips.
04/17/14
20140104915
Semiconductor memory device
A semiconductor memory device includes a memory cell, a pair of local bit lines connected to the memory cell, first and second transistors, one end of the current channel of each connected to a power supply and the other end of the current channel of each connected to one of the local bit lines, third and fourth transistors, one end of the current channel of each connected to one of the local bit lines, the other end of the current channel of each connected to one of the global bit lines, fifth and sixth transistors, one end of the current channel of each connected to one of the global bit lines and the other end of the current channel of which connected to the power supply. The device further includes a control unit configured to control the transistors..
04/10/14
20140101395
Semiconductor memory devices including a discharge circuit
Semiconductor memory devices are provided. Each of the semiconductor memory devices may include first and second memory cells.
04/10/14
20140099761
Three dimensional semiconductor memory devices and methods of forming the same
Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate.
04/10/14
20140098621
Semiconductor memory device and driving method thereof
A semiconductor memory device includes: a variable delay for delaying a delay locked loop (dll) clock by a predetermined delay time to output a delayed dll clock; an output driver for outputting data and data strobe signal in response to the delayed dll clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output ac parameters.. .
04/10/14
20140098620
Semiconductor memory device
A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the compressed data which are sequentially outputted from the read circuit to an outside of the semiconductor memory device.. .
04/10/14
20140098613
Multi-port semiconductor memory device with multi-interface
A semiconductor memory device is provided which includes a first port configured to connect to a first processor and including a first interface circuit; a second port configured to connect to a second processor and including a second interface circuit; and a memory cell array including a first memory area connected to the first and second ports in common. The first memory area includes a plurality of magneto-resistive random access memory cells.
04/10/14
20140098612
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device comprises multiple memory strings each including a plurality of first and second groups of serially connected memory cells, and a back gate transistor serially connected between the first and second groups of memory cells, a plurality of word lines, each word line being connected to a control gate of a different memory cell in each of the memory strings, a voltage generating circuit configured to generate control voltages of different voltage levels, and a control circuit configured to control application of control voltages to the word lines and the back gate line. A control voltage applied to the back gate line may be varied depending on how far a selected word line is from the back gate line, and a control voltage applied to unselected word lines may be varied depending on how far the unselected word line is from the selected word line..
04/10/14
20140098609
Nonvolatile semiconductor memory apparatus
According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings.
04/10/14
20140098600
Semiconductor memory device having discriminary read and write operations according to temperature
A semiconductor memory device is provided which includes a memory cell array including magnetic memory cells arranged in a matrix form of rows and columns and connected with bit lines and a source line; and a temperature sensing unit configured to generate a temperature sensing signal by sensing a temperature of the memory cell array. A memory controller, constituting a memory system together with the semiconductor memory device, may control read and write operations of the semiconductor memory device differently according to the temperature sensing signal of the temperature sensing unit..
04/10/14
20140098599
Semiconductor memory device with data path option function
A semiconductor memory device may include a memory cell, a bit line connected to the memory cell, a bit line data latch circuit configured to sense-amplify data stored in the memory cell connected to the bit line and to store write data in the memory cell via the bit line; an input/output driver configured to output read data on the bit line to an external device or to drive the write data provided from the external device; and a selection unit configured to select whether the read data and the write data are communicated between the input/output driver and the memory cell with or without use of the bit line data latch circuit.. .
04/10/14
20140097485
Nonvolatile semiconductor memory device and method for manufacturing same
According to one embodiment, a nonvolatile semiconductor memory device includes a first stacked structure body, a first semiconductor layer, a first organic film, a first semiconductor-side insulating film, and a first electrode-side insulating film. The first stacked structure body includes a plurality of first electrode films stacked along a first direction and a first inter-electrode insulating film provided between the first electrode films.
04/03/14
20140095962
Semiconductor device and operating method thereof
An operating method of a semiconductor device may comprise monitoring error handling information for a data read from a semiconductor memory device; and generating a refresh request for one or more memory cells of the semiconductor memory device according to the error handling information.. .
04/03/14
20140095824
Semiconductor device and operating method thereof
A semiconductor device comprises: a read queue configured to store one or more read requests to a semiconductor memory device; a write queue configured to store one or more write requests to the semiconductor memory device; and a dispatch block configured to determine a scheduling order of the one or more read requests and the one or more write requests and switch to the read queue or to the write queue if a request exists in a row hit state in the read queue or in the write queue.. .
04/03/14
20140094012
Three-dimensional semiconductor memory devices
Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate..
04/03/14
20140094011
Self-aligned method of forming a semiconductor memory array of floating gate memory cells with single poly layer
A method of forming a semiconductor memory cell that includes forming the floating and control gates from the same poly layer. Layers of insulation, conductive and second insulation material are formed over a substrate.
04/03/14
20140092698
Semiconductor device and operating method thereof
An operating method of a semiconductor device may comprise monitoring error handling information corresponding to an address of a semiconductor memory device, setting a refresh period for the address considering the error handling information and requesting a refresh request for the address.. .
04/03/14
20140092693
Semiconductor device and operating method thereof
A semiconductor device may test a semiconductor memory device by storing a data sample that is sampled from among data requested to be written into a semiconductor memory device and by comparing the data sample with data read from the semiconductor memory device which corresponds to the data sample.. .
04/03/14
20140092684
Nonvolatile semiconductor memory device
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block.
04/03/14
20140092665
Semiconductor memory device
A memory cell array includes a plurality of word lines each connected to gates of cell transistors in corresponding ones of a plurality of memory cells, a plurality of first control lines, a plurality of second control lines, a first ground circuit configured to ground the first control lines together in accordance with a first signal, and the first ground circuit includes a plurality of first transistors provided in a one-to-one correspondence with the first control lines, and each including a drain connected to a corresponding one of the first control lines, a first ground line configured to ground sources of the first transistors together, and a first signal line connected to gates of the first transistors to feed the first signal to the gates.. .
04/03/14
20140091396
Pass gate, semiconductor memory, and semiconductor device
According to one embodiment, a pass gate provided between a data holding unit of an sram cell and a bit line, includes a first tunnel transistor and a first diode connected in series between the data holding unit and the bit line, and a second tunnel transistor and a second diode connected in series between the data holding unit and the bit line and connected in parallel to the first tunnel transistor and the first diode. Gate electrodes of the first tunnel transistor and the second tunnel transistor are connected to a word line.
03/27/14
20140089575
Semiconductor memory asynchronous pipeline
An asynchronously pipelined sdram has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage.
03/27/14
20140089574
Semiconductor memory device storing memory characteristic information, memory module and memory system having the same, and operating method of the same
A semiconductor memory device storing memory characteristic information, a memory module including the semiconductor memory device, a memory system, and an operating method of the semiconductor memory device. The semiconductor memory device may include a cell array including a plurality of areas; a command decoder configured to decode a command and generate an internal command; and an information storage unit configured to store characteristic information of at least one of the plurality of areas.
03/27/14
20140089570
Semiconductor memory
A memory block area in a semiconductor memory includes program segments. Each program segment includes a group of memory cells arranged at positions where word lines and bit lines intersect and connected to a common source line.
03/27/14
20140086002
Semiconductor memory device and detection clock pattern generating method thereof
A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state..
03/27/14
20140086001
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors.
03/27/14
20140085999
Semiconductor memory device having adjustable refresh period, memory system comprising same, and method of operating same
A semiconductor memory device comprises a cell array comprising a plurality of cell regions, a row decoder configured to drive rows corresponding to cell regions in which a refresh operation is to be performed, based on a counting address, and a refresh address generator configured to generate the counting address and a modified address in response to a control signal, wherein the modified address is generated by inverting at least one bit of the counting address, and wherein the semiconductor memory device performs concurrent refresh operations on a first cell region corresponding to the counting address and a second cell region corresponding to the modified address where the second cell region is determined to have weak cells.. .
03/27/14
20140085993
Multiple bitcells tracking scheme semiconductor memory array
A read tracking system and method for advanced memory devices are provided. The read tracking system and method include tracking multiple tracking bit cells in multiple segments and columns to incorporate device performance variation of bit cells in the memory array.
03/27/14
20140085991
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode.
03/27/14
20140085990
Volatile semiconductor memory device and memory system
A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level.
03/27/14
20140085989
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes memory units each of which includes first and second select transistors and memory cells connected in series between the first and second select transistors. A control circuit applies a first potential difference between a source and a drain of either the first or second select transistor in a first memory unit, thereby programming either the first or second select transistor.
03/27/14
20140085988
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation.
03/27/14
20140085987
Semiconductor memory circuit
Provided is a semiconductor memory circuit excellent in long-term reliability and reading characteristics and having low current consumption. The semiconductor memory circuit includes: a first inverter; a first non-volatile memory, which is electrically writable; a second inverter; and a second non-volatile memory, the first inverter having an output connected to a source of the first non-volatile memory, the first non-volatile memory having a drain connected to an input of the second inverter, the second inverter having an output connected to a source of the second non-volatile memory, the second non-volatile memory having a drain connected to an input of the first inverter, the drain of the second non-volatile memory serving as an output of the semiconductor memory circuit..
03/27/14
20140085983
Nonvolatile semiconductor memory device and control method thereof
A nonvolatile semiconductor memory device includes a memory cell array having first and second groups of memory strings, each memory string including first and second memory cells connected between select transistors. The nonvolatile semiconductor memory device further includes a first word line connected to the first memory cells of the memory strings, a second word line connected to the second memory cells of the memory strings, and a control unit configured to control application of control voltages to the select transistors and the word lines, such that a select line voltage is applied to the first word line and a non-select line voltage is applied to the second word line and not discharged while select transistors of the first group of memory strings are turned off and select transistors of the second group of memory strings are turned on..
03/27/14
20140085982
Semiconductor memory device
A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor..
03/27/14
20140085981
Semiconductor memory device
A semiconductor memory device includes a memory block as a code storage memory area which has a large memory capacity and in which the number of bits to be written at once is large, and a memory block as a work memory area which has a small memory capacity and in which the number of bits to be written at once is small, in which in writing to the code storage memory area a first voltage is supplied to a source line of this memory block, and in writing to the work memory area a second voltage higher than the first voltage is supplied to a source line of this memory block.. .
03/27/14
20140085979
Nonvolatile semiconductor memory device
A memory cell array according to an embodiment includes a plurality of nand strings with a plurality of memory cells stacked, and a bit line is connected to the nand string. A word line is connected to a gate of the memory cell.
03/27/14
20140085977
Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate
A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to n-th memory cells.
03/27/14
20140085976
Nonvolatile semiconductor memory device
This nonvolatile semiconductor memory device comprises a transistor string formed on a substrate and including a plurality of first transistors connected in series with each other. A first bit line is connected to a first end of the transistor string.
03/27/14
20140085972
Semiconductor memory device, memory system and access method to semiconductor memory device
A semiconductor memory device includes a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more), a page selection circuit configured to select a row in the block array as a page to be selected, and a page buffer configured to store data to be written in a page selected by the page selection circuit or data read from the page. Each of the memory blocks includes a memory cell array having a plurality of memory cells, a row selection circuit configured to select a row of the memory cell array, and a column selection circuit configured to select a column of the memory cell array..
03/27/14
20140085961
Semiconductor memory device
According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines..
03/27/14
20140085960
Semiconductor memory device and electronic device
A semiconductor memory device including a plurality of memory blocks mba0, mba1, mbb0, mbb1; a plurality of bus lines 26 provided respectively associated with the plurality of memory blocks; a plurality of input/output ports 22a, 22b; a selector 28a, 28b selectively connecting each of the plurality of bus lines to one of the plurality of input/output ports; and a setting unit 38a, 38b setting a connection of the selector.. .
03/27/14
20140084353
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device with a first region including a memory cell array of a plurality of memory cells arrayed in three dimensions and a second region with a peripheral circuit for controlling the memory cell array is described. The peripheral circuit includes an insulating film and a template region.
03/20/14
20140082306
Semiconductor memory device and information data processing apparatus including the same
A semiconductor memory device includes a plural number of data input/output pins, a plural number of banks, in each of which a plural number of the information data is stored, a selector and a control circuit. In a first access mode, the control circuit simultaneously accesses the multiple banks in response to a single read-out command or to a single write-in command from outside.
03/20/14
20140082266
Nonvolatile semiconductor memory device
A semiconductor memory device includes a plurality of memory strings each of which includes a series of memory cells that each store data having n bits (n≧3), word lines, each connected in common to memory cells of different memory strings, and a control circuit which controls a first write operation and a second write operation. The first write operation includes a first step where a middle threshold voltage distribution is formed in memory cells and a second step following the first step where threshold voltages of some of the memory cells are increased, and the second write operation includes a step where threshold voltage distributions which correspond to the data having n bits is formed in the memory cells, wherein a write verify operation is performed after the first step but not after the second step of the first write operation..
03/20/14
20140081439
Recording apparatus, reproducing apparatus, and recording and/or reproducing apparatus
An apparatus has a microphone, an analog to digital converting circuit, a semiconductor memory, an input device, and a controller. The analog to digital converting circuit converts an output signal from the microphone into a digital signal.
03/20/14
20140080297
Nonvolatile semiconductor memory device and method of fabricating the same
According to one embodiment, a semiconductor device, including a substrate, a stacked layer body provided above the substrate, the stacked layer body alternately stacking an insulator and an electrode film one on another, silicon pillars contained with fluorine, the silicon pillar penetrating through and provided in the stacked layer body, a tunnel insulator provided on a surface of the silicon pillar facing to the stacked layer body, a charge storage layer provided on a surface of the tunnel insulator facing to the stacked layer body, a block insulator provided on a surface of the charge storage layer facing to the stacked layer body, the block insulator being in contact with the electrode film, and an embedded portion provided in the silicon pillars.. .
03/20/14
20140078848
Semiconductor memory device, memory controller, and data processing system including these
In one embodiment, a semiconductor memory device receives a refresh command and address information, and supplies a refresh control signal and the address information in common to core chips. Each of the core chips includes a layer-address comparison circuit that determines whether the address information assigns an own core chip, and a refresh control circuit that refreshes an own memory cell based on the refresh control signal when the address information assigns the own core chip.
03/20/14
20140078846
Semiconductor memory device capable of performing refresh operation without auto refresh command
A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The semiconductor memory device is configured such that when a read command or a write command is input, if a first portion of a plurality of memory banks of a first memory bank group from among one or more memory bank groups of the memory cell array performs a read operation or a write operation, a second portion of the plurality of memory banks of the first memory bank group performs a refresh operation..
03/20/14
20140078842
Post package repairing method, method of preventing multiple activation of spare word lines, and semiconductor memory device including fuse programming circuit
Provided is a method of preventing simultaneous activation of redundancy memory line or spare word lines, the method including: programming a fail address of a memory line determined to be defective; reprogramming the fail address if a first spare line for the memory line is determined to be defective; storing additional information with respect to the reprogrammed fail address; and activating a second spare line and inactivating the first spare line, referring to the additional information.. .
03/20/14
20140078834
Semiconductor memory device and information processing apparatus
A semiconductor memory device includes an address decoder to decode an address specifying pseudo-multiport cells in memory blocks, a first word line driver to output a word line selection signal selecting one of word lines of one of the pseudo-multiport cells based on a row address in the address, and a second word line driver having an output part to output the word line selection signal into one of a pair of the word lines of the pseudo-multiport cell, and a nor logic part to output nor of the word line selection signal and a read/write selection signal into the other one of the pair of the word lines, the read/write selection signal selecting writing or reading operations. The second word line driver activates the pair of the word lines for writing data, and activates one of the pair of the word lines for reading data..
03/20/14
20140078813
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes a memory cell array including memory cells having a variable resistance element provided at intersections of crossing first and second lines, the memory cell array including third lines, fourth and fifth lines, and first and second diodes; and a control circuit which, when the memory cells include a selected memory cell, a selected first line connected to the selected memory cell and an unselected first line, and a selected second line connected to the selected memory cell and an unselected second line, supplies a first voltage to the selected first line, and supplies a second voltage to the unselected first line, and when the third lines include a selected third line electrically connected to the selected second line via one of the fourth line and a first diode, supplies a third voltage to the selected fourth line.. .
03/20/14
20140078805
Semiconductor memory device having vertical transistors
A device includes first and second regions including first and second amplifiers, respectively and a memory cell array region formed between the first and second regions and includes first and second conductive layers each extending in a first direction, and a plurality of first pillar elements arranged in line in the first direction on the first conductive layer, each of the first pillar elements being coupled to the first conductive layer at one end thereof, and the first pillar elements comprising a plurality of first elements and a second element, and a plurality of second pillar elements arranged in line in the first direction on the second conductive layer, each of the second pillar elements being coupled to the second conductive layer at one end thereof, and the second pillar elements comprising a plurality of third elements and a fourth element.. .
03/20/14
20140077285
Non-volatile semiconductor memory device and method for manufacturing non-volatile semiconductor memory device
An embodiment includes: a stacked body having an impurity doped silicon layer and an interlayer insulating film alternately stacked on each other in which one layer of the impurity doped silicon layers is replaced with a conductive film enabling forming a metal oxide; a hole penetrating the stacked body in a stacking direction; a channel layer formed in the hole along the stacking direction of the stacked body; a tunnel insulating film formed between an inner surface of the hole and the channel layer; a charge trapping layer formed between the inner surface of the hole and the tunnel insulating film; and a block insulating film formed between the inner surface of the hole and the charge trapping layer.. .
03/20/14
20140077150
Semiconductor memory storage array device and method for fabricating the same
A semiconductor memory storage array device comprises a first electrode layer, an oxide layer, a second electrode layer, a memory material layer and a first insulator layer. The oxide layer is disposed on the first electrode layer.
03/13/14
20140075266
Error check and correction circuit and semiconductor memory
An error check and correction circuit includes a chien search unit. The chien search unit includes a calculation circuit and a plurality of chien search circuits.
03/13/14
20140075135
Semiconductor memory device with operation functions
A semiconductor memory device performs a modified read operation or a modified write operation. The semiconductor memory device includes a memory cell array, a read circuit, and a write circuit.
03/13/14
20140075099
Control method and memory system of non-volatile semiconductor memory
A method and a device for controlling a non-volatile semiconductor memory device having a plurality of physical memory blocks are described. The control method includes forming a logical block including normal physical blocks and a defective physical block.
03/13/14
20140075097
Semiconductor storage device and method for controlling nonvolatile semiconductor memory
According to embodiments, a controller comprises a write control unit that performs writing in a nonvolatile semiconductor memory, and an area management unit that causes the write control unit to perform write processing until a spare area not storing valid data is not present in the nonvolatile semiconductor memory, and transmits an error to a host when the spare area is not present.. .


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Semiconductor Memory topics: Semiconductor, Semiconductor Memory, Memory Device, Memory Cell, Transistors, Memory Cells, Work Function, Free Energy, Volatile Memory

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