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Semiconductor Memory patents



      
           
This page is updated frequently with new Semiconductor Memory-related patent applications. Subscribe to the Semiconductor Memory RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Memory RSS RSS


Semiconductor memory card access apparatus, a computer-readable recording medium, an initialization method, and a…

Sense amplifier circuit and semiconductor memory device

Semiconductor memory system

Date/App# patent app List of recent Semiconductor Memory-related patents
08/21/14
20140237263
 Nonvolatile semiconductor memory device and memory system using the same patent thumbnailNonvolatile semiconductor memory device and memory system using the same
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and an encryption arithmetic module. The memory cell array includes a first storage area and a second storage area.
08/21/14
20140237203
 Semiconductor memory card access apparatus, a computer-readable recording medium, an initialization method, and a semiconductor memory card patent thumbnailSemiconductor memory card access apparatus, a computer-readable recording medium, an initialization method, and a semiconductor memory card
A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters.
08/21/14
20140233336
 Sense amplifier circuit and semiconductor memory device patent thumbnailSense amplifier circuit and semiconductor memory device
A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell.
08/21/14
20140233332
 Semiconductor memory system patent thumbnailSemiconductor memory system
A semiconductor memory system includes a semiconductor memory configured to provide an external circuit with a plurality of refresh characteristic information and perform an auto-refresh operation in response to a plurality of auto-refresh commands, and a memory controller configured to provide the semiconductor memory with the plurality of auto-refresh commands generated according to the plurality of refresh characteristic information.. .
08/21/14
20140233323
 Nonvolatile semiconductor memory device patent thumbnailNonvolatile semiconductor memory device
A control circuit is configured to, during an erase operation, set a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage. The control circuit is configured to, during the erase operation, set a voltage difference between a voltage of a first line connected to an unselected cell unit and a voltage of a gate of a first transistor included in the unselected cell unit to a second voltage, the second voltage differing from the first voltage.
08/21/14
20140233320
 Nonvolatile semiconductor memory device patent thumbnailNonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes a memory cell, a bit line electrically connected to the memory cell, a sense amplifier that includes a first transistor having a first end electrically connected to the bit line, a second transistor electrically connected between a second end of the first transistor and ground, a third transistor electrically connected between a second end of the first transistor and a source line, and a controller configured to control the first, second, and third transistors after performing a program operation. After the program operation, the first and second transistors are turned on and then while the first transistor remains turned on, the second transistor is turned off and the third transistor is turned on..
08/21/14
20140233312
 Semiconductor memory device for storing multivalued data patent thumbnailSemiconductor memory device for storing multivalued data
Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line.
08/21/14
20140233311
 Nonvolatile semiconductor memory patent thumbnailNonvolatile semiconductor memory
A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.. .
08/21/14
20140233309
 Semiconductor memory device patent thumbnailSemiconductor memory device
According to one embodiment, a semiconductor includes a memory cell, a bit line, a word line, a sense amplifier, and a control circuit. The memory cell stores n levels (where n is a natural number of two or greater).
08/21/14
20140233308
 Semiconductor memory device and writing method thereof patent thumbnailSemiconductor memory device and writing method thereof
A writing method of a semiconductor memory device includes applying a plurality of program voltages sequentially generated to a selected word line, and applying any one of a plurality of source selection line voltages to a source selection line when each of the plurality of program voltages is applied.. .
08/21/14
20140231898
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a block insulating film; an organic molecular layer, which is formed between the semiconductor layer and the block insulating film, and provided with a first organic molecular film on the semiconductor layer side containing first organic molecules and a second organic molecular film on the block insulating film side containing second organic molecules, and in which the first organic molecule has a charge storing unit and the second organic molecule is an amphiphilic organic molecule; and a control gate electrode formed on the block insulating film.. .
08/21/14
20140231897
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a block insulating layer; an organic molecular layer, which is formed between the semiconductor layer and the block insulating layer, and contains first organic molecules and second organic molecules, and in which the first organic molecule has a first alkyl chain or a first alkyl halide chain on the semiconductor layer side and a charge trapping unit on the block insulating layer side, and the second organic molecule has a second alkyl chain or a second alkyl halide chain on the semiconductor layer side and a hydroxy group, an ether group, a carboxyl group or an ester group on the block insulating layer side; and a control gate electrode formed on the block insulating layer.. .
08/21/14
20140231801
Semiconductor memory device and manufacturing method thereof
A memory cell therein includes a first transistor and a capacitor and stores data corresponding to a potential held in the capacitor. The first transistor includes a pair of electrodes, an insulating film in contact with side surfaces of the electrodes, a first gate electrode provided between the electrodes with the insulating film provided between the first gate electrode and each electrode and whose top surface is at a lower level than top surfaces of the electrodes, a first gate insulating film over the first gate electrode, an oxide semiconductor film in contact with the first gate insulating film and the electrodes, a second gate insulating film at least over the oxide semiconductor film, and a second gate electrode over the oxide semiconductor film with the second gate insulating film provided therebetween.
08/14/14
20140229662
Memory system and method for controlling a nonvolatile semiconductor memory
A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management table, the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated.. .
08/14/14
20140227842
3d structured memory devices and methods for manufacturing thereof
A 3d structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region.
08/14/14
20140227841
Three-dimensional semiconductor memory devices and methods of fabricating the same
Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate.
08/14/14
20140226422
Semiconductor memory device and method of testing the same
A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous to the first mat, a first sense amplifier coupled to a first bit line of the first mat, a second sense amplifier coupled to a second bit line of the first mat and a third bit line of the second mat, a third sense amplifier coupled to a fourth bit line of the second mat, and a plurality of bit line precharge voltage providers for varying a level of a bit line precharge voltage provided to the first, second, and third sense amplifiers, selectively providing the resultant bit line precharge voltage level, and providing the same voltage as that of data of a selected cell to a non-selected sense amplifier during a read operation..
08/14/14
20140226421
Clock signal generation apparatus for use in semiconductor memory device and its method
A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.. .
08/14/14
20140226417
Load and short current measurement by current summation technique
Methods for monitoring one or more load currents corresponding with one or more voltage regulators used during operation of a semiconductor memory are described. The one or more load currents may be due to the biasing of memory cells within a memory array or due to the presence of shorts between lines in the memory array.
08/14/14
20140226407
Nonvolatile semiconductor memory device
An erase verify operation is executed divided into at least a first erase verify operation and a second erase verify operation. The first erase verify operation is an operation that applies a verify read voltage only to a first group of memory cells among the plurality of memory cells included in the nand cell unit, and applies a first read pass voltage to memory cells other than the first group of memory cells.
08/14/14
20140226393
Temperature compensation of conductive bridge memory arrays
Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array.
08/14/14
20140225183
Three-dimensional semiconductor memory device
A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.. .
08/14/14
20140225179
Nonvolatile semiconductor memory device
According to one embodiment, a memory cell includes a gate insulating layer on the active area, a floating gate electrode on the gate insulating layer, the floating gate electrode having a lower portion with a first width and a higher portion with a second width narrower than the first width, an intermediate insulating layer covering an end of the higher portion of the floating gate electrode, a charge storage layer being adjacent to the intermediate layer, an inter-electrode insulating layer covering the floating gate electrode and the charge storage layer, and a control gate electrode on the inter-electrode insulating layer.. .
08/14/14
20140225171
Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device are disclosed. The techniques may be realized as a semiconductor memory device.
08/07/14
20140223399
Circuit analysis device and circuit analysis method
A circuit analysis device includes: a processor configured to execute a procedure by: calculating, for power supply noise included in a power supply voltage supplied to a semiconductor memory device, variation characteristics of an electric potential relative to the power supply voltage in a specific memory cell included in a memory cell array; calculating power supply noise of a power supply system that occurs when a current is supplied to an equivalent circuit of the power supply system under a predetermined condition, the power supply system including a power supply line and an element for supplying a power supply voltage from a voltage source to a semiconductor device; calculating, from the variation characteristics, the electric potential obtained when the power supply noise is equal to a specific magnitude; and determining, by comparing the calculated electric potential with a threshold, whether memory latch-up will occur in the specific memory cell.. .
08/07/14
20140223257
Semiconducotr memory device including non-volatile memory cell array
A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a dram cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit.
08/07/14
20140220750
Semiconductor memory device and method of fabricating the same
Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate.
08/07/14
20140219044
Memory module and memory system comprising same
A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (mrs) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an mrs command received from a command decoder, and an address buffer configured to store a predetermined address signal, to receive an address signal and corresponding data from an external device, and to compare the address signal received with the predetermined address signal in response to the enable signal. As a consequence of determining that the address signal received from the external device is the same as the predetermined address signal stored in the address buffer, data different from the corresponding data received from the external device is written to a memory cell corresponding to the predetermined address signal..
08/07/14
20140219040
Semiconductor memory device including bulk voltage generation circuit
A semiconductor memory device includes a bulk voltage generation circuit configured to interrupt driving of a bulk voltage in response to an exit signal which is generated in synchronization with a time at which a power-down mode is ended, and discharge charges of a first node from which the bulk voltage is outputted, in response to the exit signal; and an internal circuit including a mos transistor which is supplied with the bulk voltage.. .
08/07/14
20140219037
Non-volatile semiconductor memory device and semiconductor device
Provided is a semiconductor non-volatile memory device capable of improving the accuracy of trimming by creating a written state before data is written into a non-volatile memory element. The semiconductor non-volatile memory device includes: a written data transmission circuit for transmitting written data to a non-volatile memory element; a first switch connected between the non-volatile memory element and a data output terminal; a third switch connected to an output terminal of the written data transmission circuit; and a control circuit for controlling the respective switches.
08/07/14
20140219036
Equalizer and semiconductor memory device including the same
Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit.
08/07/14
20140219035
Semiconductor memory device
Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data erase operation in all of the non-volatile memory circuits has been completed, the shift circuit outputs a continuous erase completion signal. Thereby, the data erase operation in all of the non-volatile memory circuits built in one chip can be continuously executed by one continuous erase command as is also the case where a single non-volatile memory circuit is built in..
08/07/14
20140219029
Programming method for nonvolatile semiconductor memory device
A method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprises the steps of: dividing the plurality of memory cells into m number of groups (m is an integer); successively selecting each of the m number of groups; generating m number of successive overlapping pulse signals; and programming the memory cells of the m number of groups in response to the respective m number of successive overlapping pulse signals.. .
08/07/14
20140219024
Nonvolatile semiconductor memory device
Word lines extend in a first direction and are commonly connected to memory cells in a plurality of nand cell units. Bit lines extend in a second direction crossing to the first direction and connected to one ends of the nand cell units.
08/07/14
20140219008
Semiconductor memory device with hierarchical bitlines
A dynamic random access memory (dram) device has a hierarchical bitline structure with local bitlines and global bitlines formed on different metal layers. The local bitlines are separated into a plurality of local bitline sections, and bitline isolation switches are configured to connect or disconnect the local bitline sections to or from the global bitlines.
08/07/14
20140219005
Semiconductor memory device and method of controlling data thereof
A control circuit is configured to perform a state determination operation to sense voltages of a plurality of first wiring lines, the voltages changing based on current flowing from the first wiring lines to a plurality of second wiring lines via a plurality of variable resistive elements. Then, the control circuit is configured to adjust voltages to be applied to the first and second wiring lines in a reset operation or a set operation based on the voltages of the first wiring lines sensed in the state determination operation..
08/07/14
20140219004
Nonvolatile semiconductor memory device
A length of a wiring line between the set operation-dedicated first driver circuit and the memory cell array is longer compared to a length of a wiring line between the reset operation-dedicated first driver circuit and the memory cell array.. .
08/07/14
20140219000
Otp cell array including protected area, semiconductor memory device including the same, and method of programming the same
A method of programming a memory device including a one-time programmable (otp) cell array configured to include at least one of a protected area and a programmable area are disclosed. The method includes receiving a fuse-program command to initiate a fuse-programming operation; checking whether the programmable area exists in the otp cell array, terminating the fuse-programming operation when the otp cell array does not include the programmable area, performing a fuse-programming operation on the programmable area when the otp cell array includes the programmable area thereby programming fuses to create a fuse-programmed area; setting the fuse-programmed area of the otp cell array as the protected area..
08/07/14
20140218999
Semiconductor storage device
With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (ma) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically.
08/07/14
20140218767
Image forming apparatus, memory management method for image forming apparatus, and program
An image forming apparatus that performs image processing using information stored in a semiconductor memory includes an obtaining unit configured to obtain from the semiconductor memory a block size used for data reading and writing, and a management unit configured to discretely arrange and manage, with respect to a specific region set in the semiconductor memory, use-based information to be updated along with execution of the image processing, included in the stored information, according to the obtained block size.. .
08/07/14
20140217598
Semiconductor memory device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes a plurality of interconnects of an nth layer, a plurality of interconnects of a (n+1)th layer, a plurality of stacked films of the nth layer, each of the plurality of stacked films of the nth layer including a memory element, an inter-layer insulating film of the nth layer, a plurality of interconnects of a (n+2)th layer, a plurality of stacked films of the (n+1)th layer, each of the plurality of stacked films of the (n+1)th layer including a memory element, and an inter-layer insulating film of the (n+1)th layer. The inter-layer insulating film of the (n+1)th layer is provided also at a side surface of an end portion in the first direction of the interconnects of the nth layer..
08/07/14
20140217494
Nonvolatile semiconductor memory device and manufacturing method thereof
First and second memory cells have first and second channels, first and second tunnel insulating films, first and second charge storage layers formed of an insulating film, first and second block insulating films, and first and second gate electrodes. A first select transistor has a third channel, a first gate insulating film, and a first gate electrode.
07/31/14
20140215288
Semiconductor memory device and method of controlling the same
A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.. .
07/31/14
20140215168
Semiconductor memory device
A semiconductor memory device includes a first semiconductor chip which includes a first data input-output circuit connected to a plurality of output lines including first and second output lines and configured to output a status signal onto the first output line, and a second semiconductor chip which includes a second data input-output circuit connected to the plurality of output lines including the first and second output lines and configured to output a status signal onto the second output line.. .
07/31/14
20140211577
Semiconductor memory device and method of operating the same
A method of operating a semiconductor memory device is disclosed. The method may include receiving an access command, applying a first voltage to a selected word line of the semiconductor memory device for a period of time in response to receiving the access command, applying a second voltage to word lines adjacent to the selected word line before and after the period of time, and applying a third voltage to the word lines adjacent to the selected word line for the period of time, a voltage level of the third voltage greater than the second voltage.
07/31/14
20140211566
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a first sense amplifier that is located in a first region and amplifies signals from a memory cell in the first region. A second sense amplifier is located in a second region and amplifies signals from a memory cell in the second region.
07/31/14
20140211557
Voltage assisted stt-mram writing scheme
An embodiment includes a three terminal magnetic element for a semiconductor memory device. The magnetic element includes a reference layer; a free layer; a barrier layer disposed between the reference layer and the free layer; a first electrode; an insulating layer disposed between the electrode and the free layer; and a second electrode coupled to sidewalls of the free layer..
07/31/14
20140211553
Load and short current measurement by current summation technique
Methods for monitoring one or more load currents corresponding with one or more voltage regulators used during operation of a semiconductor memory are described. The one or more load currents may be due to the biasing of memory cells within a memory array or due to the presence of shorts between lines in the memory array.
07/31/14
20140211539
Semiconductor memory device
A control circuit is configured to perform, when a plurality of variable resistance elements connected to a selected first wiring line are selected, a read operation to sense a voltage of the selected first wiring line. The control circuit is configured to adjust, according to the voltage of the selected first wiring line sensed in the read operation, a voltage to be applied to the selected first wiring line in a reset operation or a set operation.
07/31/14
20140210055
Method of forming micropattern, method of forming damascene metallization, and semiconductor device and semiconductor memory device fabricated using the same
According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths.
07/31/14
20140209853
Semiconductor memory device
A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells.
07/31/14
20140208554
Semiconductor device and control method of the same
The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened..
07/24/14
20140204692
Semiconductor memory device and method with auxiliary i/o line assist circuit and functionality
A semiconductor memory device includes an i/o line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the i/o line on the basis of the read data, a read circuit for receiving the read data transmitted through the i/o line, and an assist circuit for amplifying the read data transmitted through the i/o line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit.
07/24/14
20140204681
Semiconductor memory device and method of operating the same
A semiconductor memory device includes strings each configured to include a drain select transistor, memory cells, and a source select transistor coupled in series between a bit line and a common source line and peripheral circuits configured to perform an operation of precharging a bit line so that the precharge level of the bit line varies depending on whether an adjacent unselected memory cell, which is adjacent to a selected memory cell, is in the program state or the erase state, by supplying a first voltage to the adjacent unselected memory cell arranged toward the drain select transistor, a second voltage to the remaining memory cells in order to turn on the remaining memory cells, and a third voltage higher than a bit line precharge voltage to the common source line and perform a read operation of supplying a read voltage lower than the second voltage to the selected memory cell, the second voltage to the remaining memory cells including the adjacent unselected memory cell, and a ground voltage to the common source line.. .
07/24/14
20140204670
Semiconductor memory device using only single-channel transistor to apply voltage to selected word line
A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines.
07/24/14
20140204653
Semiconductor memory device
A semiconductor memory device includes: a plurality of word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements each having a first terminal connected to either one of the first and third bit lines; a plurality of active areas extending in a direction oblique to the first direction while intersecting with the first to third bit lines; a plurality of select transistors provided on the active areas and each having a gate connected to a corresponding one of the word lines, and a current path whose one end is connected to a second terminal of a corresponding one of the variable resistance elements; and a plurality of contact plugs each connecting the other end of the current path of a corresponding one of the select transistors to the second bit line, wherein each of the active areas includes two select transistors sharing a diffusion region, the variable resistance elements includes a first variable resistance element group and a second variable resistance element group, the first variable resistance element group including variable resistance elements aligned in the second direction below the first bit line, and each disposed between adjacent two of the word lines, the second variable resistance element group including variable resistance elements aligned in the second direction below the third bit line, and each disposed between adjacent two of the word lines, and the contact plugs are aligned in the second direction below the second bit line, and are each disposed between adjacent two of the word lines.. .
07/24/14
20140203345
Non-volatile semiconductor memory device
A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device (1), when a selected memory cell transistor (115) is caused to accumulate electric charges, high voltage as writing prevention voltage is applied from a pmos transistor (9b) while low voltage as writing voltage is applied from an nmos transistor (15a).
07/17/14
20140198596
Circuit for controlling sense amplifier source node in semiconductor memory device and controlling method thereof
Provided is a bit line sense amplifier source node control circuit of a semiconductor memory device. The sense amplifier source node control circuit may include a source driver connected between a source node of a sense amplifier and a sense amplifier driving signal line, for driving the source node of the sense amplifier to a set voltage level.
07/17/14
20140198593
Redundancy circuit and semiconductor memory device including the same
A redundancy circuit includes a redundancy decoder, a fuse array, and a decoder. The redundancy decoder decodes a redundancy enable signal generated when an address of a defective cell matches an input address.
07/17/14
20140198589
Memory core and semiconductor memory device including the same
A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages..
07/17/14
20140198585
Semiconductor memory apparatus
A semiconductor memory apparatus includes: a data output signal transmitter configured to receive a data signal and a data mask signal and transmit a data output signal through a global data line, the data output signal being outputted by determining whether the data signal is masked or not; and a write driver configured to receive the data output signal through the global data line and input the received data output signal to a local data line corresponding to the data output signal.. .
07/10/14
20140195727
Apparatus and method for generating descriptors to reaccess a non-volatile semiconductor memory of a storage drive due to an error
A storage drive including a first module and a second module. The first module is configured to, based on an instruction signal of a first descriptor, transfer a block of data to or from a non-volatile semiconductor memory in the storage drive.
07/10/14
20140195726
Controller, data storage device and data storage system having the controller, and data processing method
A controller, a data storage device and a data storage system including the controller, and a data processing method are provided. The controller may process a plurality of instructions in parallel by including a plurality of address translation central processing units (cpus) in a multi-channel parallel array structure, thereby improving the performance of a semiconductor memory system..
07/10/14
20140192598
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes first hookup transistors connected to word lines, a first dummy hookup transistor connected to first dummy word line, and a second dummy hookup transistor connected to second dummy word line. A group of hookup transistors formed by the first hookup transistors, the first dummy hookup transistor, and the second dummy hookup transistor is aligned on either of one row and rows.
07/10/14
20140191328
Semiconductor memory device
A semiconductor memory device has a memory cell array having memory cells, each including first and second conduction type transistors, a peripheral circuit having the first and second conduction type transistors, a first conduction type memory cell array well region within the memory cell array region, a second conduction type memory cell array well region within the first conduction type memory cell array well region, a first conduction type peripheral circuit well region within the peripheral circuit region, a second conduction type peripheral circuit well region within the first conduction type peripheral circuit well region, and a second conduction type isolation region between the first conduction type memory cell array well region and the first conduction type peripheral circuit well region. At least a portion of first conduction type transistors of first conduction type transistors of the peripheral circuit is formed in the second conduction type isolation region..
07/10/14
20140191327
Semiconductor memory device
A semiconductor memory device has a memory cell array with memory cells, each including first and second conduction type transistors, column-side peripheral circuits disposed with the same row-direction interval as the memory cells, a first conduction type well region formed within the memory cell array, a second conduction type well region formed within the first conduction type well region and is disposed separately in the row direction, a second conduction type well contact region disposed extending in the row direction among the memory cells, a first conduction type well contact region disposed extending in the column direction among the memory cells, a column-side peripheral contact region, a first conduction type back gate voltage line connecting to the first conduction type well region; and a second conduction type back gate voltage line connecting to the second conduction type well.. .
07/03/14
20140189283
Semiconductor memory device and operating method for the same
Provided is a semiconductor memory device that may efficiently map an internal address used inside the semiconductor memory device in response to an external address that is applied from the outside of the semiconductor memory device. The semiconductor memory device may include a memory cell array configured to include a first main cell array, a first spare cell array, a second main cell array, and a second spare cell array each of which has internal cells that are selected in response to an internal address, and an address mapping unit configured to map external address as the internal address when the external address designates the first main and spare cell arrays, and to operate calculation with a given value and the external address and to map the calculation result value as the internal address when the external address designates the second main and spare cell arrays..
07/03/14
20140189258
Semiconductor memory device
A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers over a substrate, first lines coupling word lines of memory blocks arranged in even-numbered layers, and second lines coupling word lines of memory blocks arranged in odd-numbered layers.. .
07/03/14
20140189257
Semiconductor memory device
A semiconductor memory device includes stacked memory strings in which at least some adjacent memory strings share a common source line. During a read operation for a selected memory string, a first current path is formed from a bit line of the selected memory string to the common source line through the selected memory string.
07/03/14
20140185396
Semiconductor memory, memory system, and operation method thereof
A memory system includes a semiconductor memory including a storage unit configured to store parameter information in response to a test mode signal and to output the stored parameter information in response to a parameter request signal, and a memory controller configured to provide the parameter request signal to the semiconductor memory and receive the parameter information from the semiconductor memory device.. .
07/03/14
20140185387
Semiconductor memory device and method of operating the same
A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.. .
07/03/14
20140185383
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a first nand string and a second nand string are connected to a bit line. One of the first and second nand strings is selected by first to fourth select memory cells.
07/03/14
20140185380
Semiconductor memory device having faulty cells
In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories..
07/03/14
20140185370
Nonvolatile memory apparatus having magnetoresistive memory elements and method for driving the same
A semiconductor memory apparatus includes a source line, a first bit line disposed over the source line, a second bit line disposed under the source line, a first memory cell between the source line and the first bit line, and a second memory cell between the source line and the second bit line.. .


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Semiconductor Memory topics: Semiconductor, Semiconductor Memory, Memory Device, Memory Cell, Transistors, Memory Cells, Work Function, Free Energy, Volatile Memory

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