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Semiconductor Memory patents



      
           
This page is updated frequently with new Semiconductor Memory-related patent applications. Subscribe to the Semiconductor Memory RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Memory RSS RSS


Redundancy circuit and semiconductor memory device including the same

Memory core and semiconductor memory device including the same

Semiconductor memory apparatus

Date/App# patent app List of recent Semiconductor Memory-related patents
07/17/14
20140198596
 Circuit for controlling sense amplifier source node in semiconductor memory device and controlling method thereof patent thumbnailCircuit for controlling sense amplifier source node in semiconductor memory device and controlling method thereof
Provided is a bit line sense amplifier source node control circuit of a semiconductor memory device. The sense amplifier source node control circuit may include a source driver connected between a source node of a sense amplifier and a sense amplifier driving signal line, for driving the source node of the sense amplifier to a set voltage level.
07/17/14
20140198593
 Redundancy circuit and semiconductor memory device including the same patent thumbnailRedundancy circuit and semiconductor memory device including the same
A redundancy circuit includes a redundancy decoder, a fuse array, and a decoder. The redundancy decoder decodes a redundancy enable signal generated when an address of a defective cell matches an input address.
07/17/14
20140198589
 Memory core and semiconductor memory device including the same patent thumbnailMemory core and semiconductor memory device including the same
A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages..
07/17/14
20140198585
 Semiconductor memory apparatus patent thumbnailSemiconductor memory apparatus
A semiconductor memory apparatus includes: a data output signal transmitter configured to receive a data signal and a data mask signal and transmit a data output signal through a global data line, the data output signal being outputted by determining whether the data signal is masked or not; and a write driver configured to receive the data output signal through the global data line and input the received data output signal to a local data line corresponding to the data output signal.. .
07/10/14
20140195727
 Apparatus and method for generating descriptors to reaccess a non-volatile semiconductor memory of a storage drive due to an error patent thumbnailApparatus and method for generating descriptors to reaccess a non-volatile semiconductor memory of a storage drive due to an error
A storage drive including a first module and a second module. The first module is configured to, based on an instruction signal of a first descriptor, transfer a block of data to or from a non-volatile semiconductor memory in the storage drive.
07/10/14
20140195726
 Controller, data storage device and data storage system having the controller, and data processing method patent thumbnailController, data storage device and data storage system having the controller, and data processing method
A controller, a data storage device and a data storage system including the controller, and a data processing method are provided. The controller may process a plurality of instructions in parallel by including a plurality of address translation central processing units (cpus) in a multi-channel parallel array structure, thereby improving the performance of a semiconductor memory system..
07/10/14
20140192598
 Semiconductor memory device patent thumbnailSemiconductor memory device
According to one embodiment, a semiconductor memory device includes first hookup transistors connected to word lines, a first dummy hookup transistor connected to first dummy word line, and a second dummy hookup transistor connected to second dummy word line. A group of hookup transistors formed by the first hookup transistors, the first dummy hookup transistor, and the second dummy hookup transistor is aligned on either of one row and rows.
07/10/14
20140191328
 Semiconductor memory device patent thumbnailSemiconductor memory device
A semiconductor memory device has a memory cell array having memory cells, each including first and second conduction type transistors, a peripheral circuit having the first and second conduction type transistors, a first conduction type memory cell array well region within the memory cell array region, a second conduction type memory cell array well region within the first conduction type memory cell array well region, a first conduction type peripheral circuit well region within the peripheral circuit region, a second conduction type peripheral circuit well region within the first conduction type peripheral circuit well region, and a second conduction type isolation region between the first conduction type memory cell array well region and the first conduction type peripheral circuit well region. At least a portion of first conduction type transistors of first conduction type transistors of the peripheral circuit is formed in the second conduction type isolation region..
07/10/14
20140191327
 Semiconductor memory device patent thumbnailSemiconductor memory device
A semiconductor memory device has a memory cell array with memory cells, each including first and second conduction type transistors, column-side peripheral circuits disposed with the same row-direction interval as the memory cells, a first conduction type well region formed within the memory cell array, a second conduction type well region formed within the first conduction type well region and is disposed separately in the row direction, a second conduction type well contact region disposed extending in the row direction among the memory cells, a first conduction type well contact region disposed extending in the column direction among the memory cells, a column-side peripheral contact region, a first conduction type back gate voltage line connecting to the first conduction type well region; and a second conduction type back gate voltage line connecting to the second conduction type well.. .
07/03/14
20140189283
 Semiconductor memory device and operating method for the same patent thumbnailSemiconductor memory device and operating method for the same
Provided is a semiconductor memory device that may efficiently map an internal address used inside the semiconductor memory device in response to an external address that is applied from the outside of the semiconductor memory device. The semiconductor memory device may include a memory cell array configured to include a first main cell array, a first spare cell array, a second main cell array, and a second spare cell array each of which has internal cells that are selected in response to an internal address, and an address mapping unit configured to map external address as the internal address when the external address designates the first main and spare cell arrays, and to operate calculation with a given value and the external address and to map the calculation result value as the internal address when the external address designates the second main and spare cell arrays..
07/03/14
20140189258
Semiconductor memory device
A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers over a substrate, first lines coupling word lines of memory blocks arranged in even-numbered layers, and second lines coupling word lines of memory blocks arranged in odd-numbered layers.. .
07/03/14
20140189257
Semiconductor memory device
A semiconductor memory device includes stacked memory strings in which at least some adjacent memory strings share a common source line. During a read operation for a selected memory string, a first current path is formed from a bit line of the selected memory string to the common source line through the selected memory string.
07/03/14
20140185396
Semiconductor memory, memory system, and operation method thereof
A memory system includes a semiconductor memory including a storage unit configured to store parameter information in response to a test mode signal and to output the stored parameter information in response to a parameter request signal, and a memory controller configured to provide the parameter request signal to the semiconductor memory and receive the parameter information from the semiconductor memory device.. .
07/03/14
20140185387
Semiconductor memory device and method of operating the same
A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.. .
07/03/14
20140185383
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a first nand string and a second nand string are connected to a bit line. One of the first and second nand strings is selected by first to fourth select memory cells.
07/03/14
20140185380
Semiconductor memory device having faulty cells
In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories..
07/03/14
20140185370
Nonvolatile memory apparatus having magnetoresistive memory elements and method for driving the same
A semiconductor memory apparatus includes a source line, a first bit line disposed over the source line, a second bit line disposed under the source line, a first memory cell between the source line and the first bit line, and a second memory cell between the source line and the second bit line.. .
07/03/14
20140183617
Non-volatile semiconductor memory device and its manufacturing method
In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select tr have the same gate insulating film as a vcc tr. Further, the gate electrodes of a vpp tr and vcc tr are realized by the use of a first polysilicon layer.
07/03/14
20140183433
Semiconductor memory device
A semiconductor memory device according to an embodiment comprises a semiconductor layer, a variable resistance layer, a sidewall layer, and a buried layer. The semiconductor layer functions as a rectifying device.
06/26/14
20140181588
Semiconductor memory apparatus and operating method thereof
A semiconductor memory apparatus includes: a user setting unit configured to generate test data and a delay control signal in response to an external command and an external address; a delay locked loop (dll) clock generation unit including a replica configured to have a delay time controlled in response to the delay control signal; and a data output unit configured to output the test data in response to a dll clock signal outputted from the dll clock generation unit.. .
06/26/14
20140181424
Semiconductor memory system and operation method thereof
A semiconductor memory system may include a plurality of memory devices each configured to have multiple planes, and an access controller configured to access each of the multiple planes corresponding to each of the plurality of memory devices as a unit memory.. .
06/26/14
20140177374
Driver of semiconductor memory device and driving method thereof
A driver of a semiconductor memory device and driving method thereof is disclosed, which relates to a technology for reducing consumption of a leakage current not required for a driver circuit of a semiconductor memory device. The driver of the semiconductor memory device includes a drive controller configured to selectively provide a first voltage and a second voltage, that have different levels in response to a power-down signal, to a first node; an input driver configured to selectively output a voltage received from the first node in response to a decoding signal; and an output driver configured to be driven in response to an output voltage of the input driver..
06/26/14
20140177366
Data input/output circuit and semiconductor memory device including the same
A data input/output circuit includes a precharge voltage supply unit configured to supply a precharge voltage driven by a first internal voltage in a standby state, and supply the precharge voltage driven by a second internal voltage when an active operation is performed; and a precharge unit configured to receive the precharge voltage, precharge a first input/output line and a first inverted input/output line to a level of the first internal voltage in the standby state, and precharge the first input/output line and the first inverted input/output line by the second internal voltage when the active operation is performed.. .
06/26/14
20140177356
Programmable resistance-modulated write assist for a memory device
Providing for improved write processes of a semiconductor memory are disclosed herein. By way of example, a programmable write assist can be provided that includes partially discharging a supply voltage applied to a memory cell.
06/26/14
20140177340
Determining memory page status
The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status of a page of memory cells without using input/output (i/o) circuitry, and outputting the status through the i/o circuitry..
06/26/14
20140177339
Nonvolatile semiconductor memory device and memory system having the same
A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.. .
06/26/14
20140177337
Three dimensional stacked nonvolatile semiconductor memory
A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential.
06/26/14
20140177332
Operating circuit controlling device, semiconductor memory device and method of operating the same
A semiconductor memory device is kept in a busy state by controlling a ready/busy pad when a detection signal is output since an external voltage is less than a reference voltage, prevents generation of an operating voltage by a pump circuit by preventing generation of a pump clock, and resets a microcontroller by preventing generation of micro clock. Accordingly, the semiconductor memory device may be prevented from malfunctioning through a series of operations when the external voltage is less than the reference voltage..
06/26/14
20140177322
Semiconductor memory apparatus, verify read method and system
Disclosed are a semiconductor memory apparatus, and verify read method and system. The semiconductor memory apparatus includes a memory cell array including a plurality of resistive memory cells; and a control block controlling a resistance state of the memory cell to be discriminated based on a digital code value of at least 2 bits or more reflecting the resistance states of the plurality of resistive memory cells.
06/26/14
20140177314
Semiconductor memory devices and semiconductor system having parameters, and methods of testing the same
A semiconductor memory device may be effectively evaluated by a test that compares the phase of an internally generated control signal with the phase of an internally generated clock signal. Specifically, if the phase of the internal data strobe signal idqs is synchronized with the phase of the internal clock signal iclk through the test, the data strobe signal dqs may also be synchronized with the external clock signal clk.
06/26/14
20140177313
Semiconductor device and method of operation
A semiconductor device and method of operation having reduced read time of fuse array information during boot-up operation. When fuse array information is read, only repaired fuse-set information is read such that a read time of the semiconductor memory device is reduced, resulting in an increased read margin..
06/19/14
20140173234
Semiconductor memory device and memory system
A semiconductor memory system or device includes a memory cell array and an address converter. The memory cell array includes a plurality of memory blocks, and there is at least one block that serves as a buffer.
06/19/14
20140173231
Semiconductor memory device and system operating method
Disclosed is a semiconductor memory device for controlling a memory block. The semiconductor memory device includes a plurality of memory blocks to store data, and controller.
06/19/14
20140173191
Semiconductor memory system having a snapshot function
In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request.
06/19/14
20140173182
Nonvolatile semiconductor memory
According to one embodiment, a memory includes a temporary storage area which temporary stores data in a read/write operation to an array. The temporary storage area comprises a clamp fet connected between a first data bus and a second data bus, a first precharge fet connected between the first data bus and first potential, a second precharge fet connected between the second data bus and the first potential, a first storage area connected to the first data bus, and a second storage area connected to the second data bus.
06/19/14
20140169112
Semiconductor memory system and operating method thereof
A semiconductor memory system configured to exchange signals through channels may include a memory control device configured to have a plurality of channels, a plurality of memory devices configured to be connected to each of the plurality of channels, wherein the plurality of channels share at least one of the plurality of memory devices.. .
06/19/14
20140169097
Semiconductor memory device, system having the same and program method thereof
The present invention relates to a semiconductor memory device and a program method thereof. The program method according to an embodiment of the present invention includes: precharging a plurality of cell strings by providing a positive voltage to the plurality of cell strings through a common source line; and performing a program operation on selected memory cells by applying a program pulse to the selected memory cells..
06/19/14
20140169096
Semiconductor memory device and operating method thereof
A semiconductor memory device includes: a memory array including a plurality of memory cells; and a peripheral circuit configured to change a voltage level of a bit line connected to a program target cell according to a threshold voltage of the program target cell among the memory cells during a program operation.. .
06/19/14
20140169092
Semiconductor memory device
A semiconductor memory device includes a first data bus having a first width, and a second data bus which is separate from the first data bus and which has a second width which is different from the first width. The semiconductor memory device further includes a data transfer unit configured for transferring data from memory cells connected to a plurality of bit lines.
06/19/14
20140169086
Common source semiconductor memory device
A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively.
06/19/14
20140169071
Semiconductor memory device
A semiconductor memory device including a plurality of memory blocks each including a first command generating circuit which generates a first command; a control circuit which controls the memory core based on the first command or based on a second command inputted via the input/output port; and an arbitration circuit which outputs a first delay signal to the control circuit of one memory block of the plurality of memory blocks, the first delay signal which delays a start of an execution of the first command, in a first case when the first command generated by the first command generating circuit of the one memory block and the second command inputted via the input/output port of another memory block of the plurality of memory blocks are overlapped.. .
06/19/14
20140169064
Regulator, voltage generator and semiconductor memory device
A regulator includes a variable resistance unit coupled between an input node to which a pumping voltage is inputted and a control node and configured to adjust resistance of the variable resistance unit in response to a control signal varied depending on a target voltage, a voltage output unit configured to adjust the pumping voltage according to potential of the control node and output the adjusted pumping voltage, and a regulation unit configured to control the potential of the control node according to the adjusted pumping voltage, to output the target voltage. The regulator adjusts the resistance of an internal resistor according to the target voltage, thereby reducing current consumption..
06/19/14
20140167134
Self-aligned vertical nonvolatile semiconductor memory device
The present invention belongs to the technical field of semiconductor memory devices and specifically relates to a self-aligned vertical nonvolatile semiconductor memory device, including: a semiconductor substrate, a drain region of a first doping type, two source regions of a second doping type, a stacked gate used to capture electrons; wherein the drain region, the two source regions and the stacked gate form two tunneling field effect transistors (tfets) sharing one gate and one drain, the drain region current of each of the tfet is affected by the quantity and distribution of the charges in the stacked gate used to capture electrons, the drain is buried in the semiconductor substrate, the source regions above the drain region are separated from the drain through a channel and separated form each other through a region of the first doping type. The semiconductor memory device of the present invention features small unit area and simple manufacturing process.
06/19/14
20140167133
Nonvolatile semiconductor memory
A nonvolatile semiconductor memory according to an embodiment includes: a semiconductor region; a first insulating film formed on the semiconductor region; a charge storage film formed on the first insulating film; a hydrogen diffusion preventing film formed on the charge storage film; a second insulating film formed on the hydrogen diffusion preventing film; a control gate electrode formed on the second insulating film; a hydrogen discharge film formed on the control gate electrode; and a sidewall formed on a side surface of a multilayer structure including the first insulating film, the charge storage film, the hydrogen diffusion preventing film, the second insulating film, and the control gate electrode, the sidewall containing a material for preventing hydrogen from diffusing.. .
06/12/14
20140162440
Semiconductor memory devices and methods of forming the same
Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate.
06/12/14
20140160874
Power management in semiconductor memory system
A method for operating a memory module device. The method can include transferring a chip select, command, and address information from a host memory controller.
06/12/14
20140160872
Voltage generation circuit, and write driver and semiconductor memory apparatus including the same
A voltage generation circuit includes a charge unit and a discharge unit. The charge unit is configured for raising a level of a ramp voltage to a predetermined level in response to a control signal.
06/12/14
20140160868
Method of maintaining the state of semiconductor memory having electrically floating body transistor
Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell, and accessing the cell.. .
06/12/14
20140160863
Semiconductor device having transistor and semiconductor memory device using the same
Semiconductor device capable of preventing off-leakage of the transistor may include a pulse voltage generator configured to generate a pulse voltage, and a transistor configured to have a gate provided with the pulse voltage. The transistor is in an off state in response to the pulse voltage..
06/12/14
20140160856
Semiconductor memory device and program method thereof
A program method of a semiconductor memory device includes performing a verify operation on selected memory cells by applying a selected word line voltage to a selected word line, continuously increasing the selected word line voltage without discharging the selected word line after the verify operation, and performing a program operation on the selected memory cells when the selected word line voltage reaches a program voltage level.. .
06/12/14
20140160846
Semiconductor memory device and method of operating the same
A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory blocks, a voltage generator configured to generate a precharge voltage; and a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed.
06/12/14
20140160833
Semiconductor memory device
A semiconductor memory device includes a memory cell array, a plurality of reference cell arrays, a plurality of word lines, a plurality of bit lines, a plurality of reference word lines, a plurality of reference bit lines each being provided for an associated one of the reference cell arrays, and equalizing transistors each of which is provided between the plurality of reference bit lines and receives an associated one of independent control signals, and a potential of one of the plurality of reference bit lines and a plurality of one of the plurality of bit lines are input to a sense amplifier.. .
06/12/14
20140159156
Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making
An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link..
06/05/14
20140156924
Semiconductor memory device with improved operating speed and data storage device including the same
A semiconductor memory device includes a power block configured to generate an internal voltage based on an external voltage which is applied through a power pad; a circuit block configured to operate according to the internal voltage and drive memory cells; and a cam (content addressed memory) block configured to operate according to the external voltage and store setting information necessary for driving of the memory cells.. .
06/05/14
20140156213
Semiconductor memory devices and methods of testing open failures thereof
Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (i/o) drive controller, a data i/o unit and a data transmitter.
06/05/14
20140154866
Method of forming a semiconductor memory device
A semiconductor memory device includes a semiconductor substrate defining active regions partitioned by an isolation region, conductive lines spaced apart from each other and crossing the active regions over the semiconductor substrate, a thin film pattern formed on a top portion of the conductive lines having opening portions exposing part of the conductive lines in a width wider than a width of the conductive lines, an insulating layer filling the opening portions and formed over the thin film pattern, and an air gap formed between the conductive lines below the insulating layer and the thin film pattern.. .
06/05/14
20140153344
Semiconductor memory device, system having the same and method for generating reference voltage for operating the same
A semiconductor memory device and a method for generating a reference voltage needed for operating the same are disclosed. The semiconductor memory device includes a first decoder configured to generate a default set signal in response to a reset signal and a clock enable signal, a second decoder configured to generate a reference voltage set signal in response, and a reference voltage provider configured to generate an internal reference voltage..
06/05/14
20140153337
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The memory cells are stacked above a semiconductor substrate, and each includes a charge accumulation layer and control gate.
06/05/14
20140153336
Semiconductor memory device having a plurality of chips and capability of outputting a busy signal
One package contains a plurality of memory chips. Each memory chip has an i/o terminal which generates a busy signal.
06/05/14
20140153319
Semiconductor memory device
A semiconductor memory device includes a bit line; two or more word lines; and a memory cell including two or more sub memory cells that each include a transistor and a capacitor. One of a source and a drain of the transistor is connected to the bit line, the other of the source and the drain of the transistor is connected to the capacitor, a gate of the transistor is connected to one of the word lines, and each of the sub memory cells has a different capacitance of the capacitor..
06/05/14
20140153315
Semiconductor memory apparatus, refresh method and system
Disclosed are a semiconductor memory apparatus, and refresh method and system. The semiconductor memory apparatus includes: a memory cell array including a plurality of resistive memory cells; and a control block configured to control at least one of a mode and a schedule of a refresh operation for the plurality of memory cells to be variable based on digital code values reflecting resistance states of the plurality of resistive memory cells.
06/05/14
20140151784
Semiconductor memory device and method of manufacturing the same
The present technology includes a semiconductor memory device, including a channel layer and interlayer insulation layers surrounding the channel layer. The interlayer insulation layers are stacked with a trench interposed therebetween.
06/05/14
20140151779
Semiconductor memory device and method of manufacturing the same
A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.. .
06/05/14
20140151777
Semiconductor memory devices and methods of fabricating the same
Provided are a semiconductor memory device and a method of fabricating the same, the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.. .
05/29/14
20140149827
Semiconductor memory device including non-volatile memory, cache memory, and computer system
In one embodiment, the memory device includes a data storage region and an error correction (ecc) region. The data storage region configured to store a first number of data blocks.
05/29/14
20140149667
Card and host apparatus
A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus..
05/29/14
20140149639
Coding techniques for reducing write cycles for memory
Structures and methods for encoding data to reduce write cycles in a semiconductor memory device are disclosed herein. In one embodiment, a method of writing data to a semiconductor memory device can include: (i) determining a number of significant bits for data to be written in the semiconductor memory device; (ii) determining a tag associated with the data to be written in the semiconductor memory device, where the tag is determined based on the determined number of significant bits; (iii) encoding the data when the tag has a first state, where the tag is configured to indicate data encoding that comprises using n bits of the encoded data to store m bits of the data, where m and n are both positive integers and n is greater than m; and (iv) writing the encoded data and the tag in the semiconductor memory device..
05/29/14
20140146617
Nonvolatile semiconductor memory
A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision.
05/29/14
20140146608
Oscillator circuit with location-based charge pump enable and semiconductor memory including the same
A semiconductor memory includes a plurality of memory blocks each comprising a plurality of memory cells, and a plurality of charge pumps each located near one of the plurality of memory blocks. In an access to the semiconductor memory, depending on the selected memory block, a subset or all of the plurality of charge pumps are activated in one of a predetermined number of sequences..
05/29/14
20140146607
Semiconductor memory device for pseudo-random number generation
According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a random number generation circuit configured to generate a random number, and a controller configured to control the memory cell array and the random number generation circuit. The random number generation circuit includes a random number control circuit configured to generate a random number parameter based on data which is read out from the memory cell by a generated control parameter, and a pseudo-random number generation circuit configured to generate the random number by using the random number parameter as a seed value..
05/29/14
20140146598
Reduced leakage memory cells
Methods and structures are described for reducing leakage currents in semiconductor memory storage cells. Vertically oriented nanorods may be used in the channel region of an access transistor.
05/29/14
20140146589
Semiconductor memory device with cache function in dram
A semiconductor memory device is provided which includes a dynamic random access memory including a memory cell array formed of dynamic random access memory cells; a cache memory formed at the same chip as the dynamic random access memory and configured to communicate with a processor or an external device; and a controller connected with the dynamic random access memory and the cache memory in the same chip and configured to control a dynamic random access function and a cache function.. .


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Semiconductor Memory topics: Semiconductor, Semiconductor Memory, Memory Device, Memory Cell, Transistors, Memory Cells, Work Function, Free Energy, Volatile Memory

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This listing is a sample listing of patent applications related to Semiconductor Memory for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Semiconductor Memory with additional patents listed. Browse our RSS directory or Search for other possible listings.
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