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Semiconductor Material patents



      

This page is updated frequently with new Semiconductor Material-related patent applications.




Date/App# patent app List of recent Semiconductor Material-related patents
06/23/16
20160181463 
 Methods of treating a semiconductor layer patent thumbnailnew patent Methods of treating a semiconductor layer
Methods for treating a semiconductor layer including a semiconductor material are presented. A method includes contacting at least a portion of the semiconductor material with a passivating agent.

06/23/16
20160181441 
 Semiconductor device and  manufacturing a semiconductor device patent thumbnailnew patent Semiconductor device and manufacturing a semiconductor device
A semiconductor device includes a semiconductor material having a bandgap larger than 2 ev and less than 10 ev, and a contact layer in contact with the semiconductor material. The contact layer includes a metal nitride.

06/23/16
20160181426 
 Methods of forming epi semiconductor material in a trench formed above a semiconductor device and the resulting devices patent thumbnailnew patent Methods of forming epi semiconductor material in a trench formed above a semiconductor device and the resulting devices
A device includes a gate structure having an axial length that is positioned above an active region of a semiconductor substrate and includes a first gate structure portion positioned above the active region and second gate structure portions positioned above an isolation region formed in the semiconductor substrate. An etch stop layer is positioned on the gate structure and covers sidewall surfaces of the second gate structure portions but does not cover any sidewall surfaces of the first gate structure portion.

06/23/16
20160181421 
 Semiconductor devices and related fabrication methods patent thumbnailnew patent Semiconductor devices and related fabrication methods
Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body region of semiconductor material having a first conductivity type, a source region of semiconductor material having a second conductivity type within the body region, a junction isolation region of semiconductor material having the second conductivity type, a drain region of semiconductor material having the second conductivity type, and first and second drift regions of semiconductor material having the second conductivity type.

06/23/16
20160181398 
 Composite dummy gate with conformal polysilicon layer for finfet device patent thumbnailnew patent Composite dummy gate with conformal polysilicon layer for finfet device
A method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure.

06/23/16
20160181388 
 Method for manufacturing a semiconductor device comprising a metal nitride layer and semiconductor device patent thumbnailnew patent Method for manufacturing a semiconductor device comprising a metal nitride layer and semiconductor device
A method of manufacturing a semiconductor device includes introducing nitrogen into a metal layer or into a metal nitride layer, the metal layer or metal nitride layer being formed in contact with a semiconductor material. A semiconductor device includes a semiconductor material and a metal nitride layer in contact with the semiconductor material.

06/23/16
20160181352 
 Capacitor structure compatible with nanowire cmos patent thumbnailnew patent Capacitor structure compatible with nanowire cmos
A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure.

06/23/16
20160181296 
 Image sensor pixel for high dynamic range image sensor patent thumbnailnew patent Image sensor pixel for high dynamic range image sensor
An image sensor pixel includes a first photodiode and a second photodiode disposed in a semiconductor material. The first photodiode has a first doped region, a first lightly doped region, and a first highly doped region.

06/23/16
20160181271 
 Methods of fabricating memory device with spaced-apart semiconductor charge storage regions patent thumbnailnew patent Methods of fabricating memory device with spaced-apart semiconductor charge storage regions
Methods of fabricating semiconductor devices, such as monolithic three-dimensional nand memory string devices, include selectively forming semiconductor material charge storage regions over first material layers exposed on a sidewall of a front side opening extending through a stack comprising an alternating plurality of first and second material layers using a difference in incubation time for the semiconductor material on the first material relative to an incubation time for the semiconductor material on the second material of the stack. In other embodiments, a silicon layer is selectively deposited on silicon nitride on a surface having at least one first portion including silicon oxide and at least one second portion including silicon nitride using a difference in an incubation time for the silicon on silicon nitride relative to an incubation time for the silicon on silicon oxide..

06/23/16
20160181253 
 Semiconductor structures with deep trench capacitor and methods of manufacture patent thumbnailnew patent Semiconductor structures with deep trench capacitor and methods of manufacture
An integrated finfet and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (soi) wafer.

06/23/16
20160181250 
new patent

Finfet based zram with convex channel region


Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less dram devices, sometimes referred to as zram devices. A channel is formed in a fin-type field effect transistor (finfet) that is comprised of a finned channel portion and a convex channel portion.

06/23/16
20160181248 
new patent

Cmos transistors including gate spacers of the same thickness


A dielectric material layer is deposited on gate structures of first and second semiconductor material portions. The dielectric material layer is anisotropically etched to form a first gate spacer on a first semiconductor material portion, while being protected above the second semiconductor material portion.

06/23/16
20160181174 
new patent

Integrated circuit cooling apparatus


A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a structure to remove heat from the active devices to the chip back side. The structure may include thermally conductive partial vias (tcpvs), which may include a recess with a depth, from the chip back side towards the active devices less than the first depth.

06/23/16
20160181164 
new patent

Fin formation on an insulating layer


An approach to forming fins for a semiconductor device on a silicon-on-insulator wafer. The approach includes depositing a layer of mandrel material and etching the layer of mandrel material to form a mandrel.

06/23/16
20160181117 
new patent

Integrated etch/clean for dielectric etch applications


The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations.

06/23/16
20160177158 
new patent

Suspensions for protecting semiconductor materials and methods of producing semiconductor bodies


A suspension for protecting a semiconductor material includes a polymeric matrix as carrier medium, inorganic particles, and at least one of an absorber dye or a plasticizer.. .

06/23/16
20160176702 
new patent

Integrated micro-electromechanical device of semiconductor material having a diaphragm, such as a pressure sensor and an actuator


An integrated micro-electromechanical device includes a first body of semiconductor material having a first face and a second face opposite the first surface, with the first body including a buried cavity forming a diaphragm delimited between the buried cavity and the first face. The diaphragm is monolithic with the first body.

06/16/16
20160172758 

Coupled multiband antennas


An antenna includes at least two radiating arm structures made of or limited by a conductor, superconductor or semiconductor material. The two arms are coupled through a region on first and second superconducting arms such that the combined structure forms a small antenna with broadband behavior, multiband behavior or a combination thereof.
Fractus, S.a.


06/16/16
20160172611 

Photodetectors and photovoltaics based on semiconductor nanocrystals


A composite material is described. The composite material comprises semiconductor nanocrystals, and organic molecules that passivate the surfaces of the semiconductor nanocrystals.
Invisage Technologies, Inc.


06/16/16
20160172609 

Electronic device and manufacturing semiconductor device


There is provided an electronic device including at least a first electrode, a second electrode disposed to be spaced apart from the first electrode, and an active layer disposed over the second electrode from above the first electrode and formed of an organic semiconductor material. A charge injection layer is formed between the first electrode and the active layer and between the second electrode and the active layer, and the charge injection layer is formed of an organic material having an increased electric conductivity when the charge injection layer is oxidized..
Sony Corporation


06/16/16
20160172526 

Illumination sensitive current control device


A semiconductor device that includes a layer of highly crystalline semiconductor material positioned on an insulating substrate. The semiconductor device also includes a source structure and a drain structure positioned on the layer of highly crystalline semiconductor material.
International Business Machines Corporation


06/16/16
20160172523 

High speed photodetector


A photodetector is disclosed. A first layer of the photodetector has a first semiconductor material having a first band gap energy, a first electric field, and a first doping concentration.
Tyco Electronics Svenska Holdings Ab


06/16/16
20160172498 

Finfet with epitaxial source and drain regions and dielectric isolated channel region


A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure.
International Business Machines Corporation


06/16/16
20160172479 

Methods and systems for ultra-high quality gated hybrid devices and sensors


High electron mobility leads to better device performance and today is achieved by fabricating “gated devices” within a high-mobility two-dimensional electron gas (2deg. However, the fabrication techniques used to form these devices lead to rapid degradation of the 2deg quality which then can limits the mobility of the electronic devices.

06/16/16
20160172476 

Semiconductor device and manufacturing semiconductor device


A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer and a third semiconductor layer formed on the first semiconductor layer; a fourth semiconductor layer formed on the third semiconductor layer; a gate electrode formed on the fourth semiconductor layer; and a source electrode and a drain electrode formed in contact with the second semiconductor layer. The third semiconductor layer and the fourth semiconductor layer are formed in an area immediately below the gate electrode, the fourth semiconductor layer is formed with a p-type semiconductor material, and the second semiconductor layer and the third semiconductor layer are formed with algan, and the third semiconductor layer has a lower composition ratio of al than that of the second semiconductor layer..
Transphorm Japan, Inc.


06/16/16
20160172475 

Method of forming a semiconductor structure


A semiconductor structure comprises a first layer. The first layer comprises a first iii-v semiconductor material.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/16/16
20160172472 

Techniques for forming non-planar germanium quantum well devices


Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group iv or iii-v semiconductor materials and includes a germanium fin structure.
Intel Corporation


06/16/16
20160172470 

Isolation structure of fin field effect transistor


A representative fin field effect transistor (finfet) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/16/16
20160172467 

Replacement metal gate including dielectric gate material


A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin.
Globalfoundries Inc.


06/16/16
20160172465 

Planar iii-v field effect transistor (fet) on dielectric layer


A method of forming a semiconductor substrate including a type iii-v semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A iii-v semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench..
International Business Machines Corporation


06/16/16
20160172462 

Fin replacement in a field-effect transistor


In a method for fabricating a field-effect transistor (fet) structure, forming a fin on a semiconductor substrate. The method further includes forming a gate on a portion of the fin and the semiconductor substrate.
International Business Machines Corporation


06/16/16
20160172459 

Active regions with compatible dielectric layers


A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material.

06/16/16
20160172458 

Schottky device and manufacture


A schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the schottky device is formed from a semiconductor material of a first conductivity type which has a barrier height adjustment layer of a second conductivity type that extends from a first major surface of the semiconductor material into the semiconductor material a distance that is less than a zero bias depletion boundary.
Semiconductor Components Industries, Llc


06/16/16
20160172369 

Forming memory using doped oxide


A method is provided for manufacturing a memory device. A strip of semiconductor material is formed having a memory region, a contact landing area region and a switch region between the memory region and the contact landing area region.
Macronix International Co., Ltd.


06/16/16
20160172362 

Cmos transistors with identical active semiconductor region shapes


A disposable semiconductor material is deposited to form disposable semiconductor material portions on semiconductor fins. A first dielectric liner is deposited and patterned to form openings above a first set of disposable semiconductor material portions on a first semiconductor fin.
International Business Machines Corporation


06/16/16
20160172275 

Package for a surface-mount semiconductor device and manufacturing method thereof


A surface-mount electronic device includes a body of semiconductor material, a lead frame, which forms a plurality of contact terminals, and a package dielectric region, which overlies the semiconductor body. Each contact terminal includes an inner portion that is overlaid by the package dielectric region and an outer portion, which projects laterally beyond the package dielectric region and is delimited by a first lateral surface.
Stmicroelectronics S.r.l.


06/16/16
20160172202 

Integrated circuits with backside metalization and production method thereof


An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated device includes a set of contact terminals for contacting the integrated circuit. At least one contact terminal of said set of contact terminals includes a contact layer of metal material being suitable to be directly coupled mechanically to an element external to the chip, and a coupling element for improving an electrical and/or mechanical coupling between the contact layer and the chip.
Stmicroelectronics S.r.l.


06/16/16
20160172199 

Nanocrystal memory and methods for forming same


A charge-storing device includes a charge-storing layer including nanocrystals. The nanocrystals are formed by a deposition technique incorporating deuterated hydrides.
Freescale Semiconductor, Inc.


06/16/16
20160172153 

Microscopy support structures


Electron microscope support structures and methods of making and using same. The support structures are generally constructed using semiconductor materials and semiconductor manufacturing processes.
Protochips, Inc.


06/09/16
20160163920 

Electronic devices comprising n-type and p-type superlattices


A superlattice and method for forming that superlattice are disclosed. In particular, an engineered layered single crystal structure forming a superlattice is disclosed.
The Silanna Group Pty Ltd.


06/09/16
20160163850 

Ldmos finfet device and manufacture using a trench confined epitaxial growth process


A finfet transistor includes a fin of semiconductor material with a transistor gate electrode extending over a channel region. Raised source and drain regions of first epitaxial growth material extending from the fin on either side of the transistor gate electrode.
Globalfoundries Inc


06/09/16
20160163844 

Method and structure for iii-v finfet


A method for fabricating a semiconductor device comprises forming a fin in a layer of iii-v compound semiconductor material on a silicon-on-insulator substrate; forming a semiconductor extension on the fin, the semiconductor extension comprising a iii-v compound semiconductor material that is different from a material forming the fin in the ill-v compound semiconductor layer; forming a dummy gate structure and a spacer across and perpendicular to the fin; forming a source/drain layer on a top surface of the substrate adjacent to the dummy gate structure; planarizing the source/drain layer; removing the dummy gate structure to expose a portion of the semiconductor extension on the fin; removing the exposed portion of the semiconductor extension; etching the semiconductor extension to undercut the spacer; and forming a replacement gate structure in place of the removed dummy gate structure and removed exposed portion of the semiconductor extension.. .
International Business Machines Corporation


06/09/16
20160163843 

Quantum well fin-like field effect transistor (qwfinfet) having a two-section combo qw structure


The present disclosure provides a quantum well fin field effect transistor (qwfinfet). The qwfinfet includes a semiconductor fin over a substrate and a combo quantum well (qw) structure over the semiconductor fin.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/09/16
20160163827 

Selective etching in the formation of epitaxy regions in mos devices


A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. After the step of performing the selective epitaxial growth, a selective etch-back is performed to the epitaxy region.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/09/16
20160163809 

Low resistance replacement metal gate structure


A first sacrificial gate structure of a first width and a second sacrificial gate structure of a second width greater than the first width are provided on a semiconductor material portion. A dielectric spacer and a planarizing dielectric material are provided surrounding each sacrificial gate structure.
International Business Machines Corporation


06/09/16
20160163796 

Semiconductor devices with structures for suppression of parasitic bipolar effect in stacked nanosheet fets and methods of fabricating the same


A device may include a nanosheet field effect transistor (fet) that may include a substrate, a well that is doped with impurities at a surface of the substrate, a channel including a plurality of stacked nanosheets, a gate, a conductive material, and an isolation layer. Ones of the plurality of stacked nanosheets may include a semiconductor material that may be doped with impurities of the same conductivity type as the impurities of the well.

06/09/16
20160163728 

Uniform thickness blocking dielectric portions in a three-dimensional memory structure


A memory opening is formed through a stack of alternating layers comprising first material layers and second material layers. Sidewall surfaces of the second material layers are laterally recessed with respect to sidewall surfaces of the first material layers within the memory opening.
Sandisk Technologies, Inc.


06/09/16
20160163727 

Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate


Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material.
Micron Technology, Inc.


06/09/16
20160163725 

Selective floating gate semiconductor material deposition in a three-dimensional memory structure


A method of forming a three-dimensional memory device includes forming a stack of alternating first and second material layers over a substrate, forming a memory opening through the stack, forming a memory film and a semiconductor channel in the memory opening, and forming backside recesses by removing the second material layers selective to the first material layers and the memory film, where an outer sidewall of the memory film is physically exposed within each backside recess. The method also includes forming at least one set of surfaces selected from silicon deposition inhibiting surfaces on the first material layers and silicon deposition promoting surfaces over the memory film in the back side recesses, selectively growing a silicon-containing semiconductor portion laterally within each backside recess, forming at least one blocking dielectric within the backside recesses, and forming conductive material layers by depositing a conductive material within the backside recesses..
Sandisk Technologies, Inc.


06/09/16
20160163659 

Radio frequency device protected against overvoltages


A device includes passive radio frequency components formed of portions of metal layers separated by insulating layers and crossed by vias. The insulating layers are positioned on an upper surface of an insulating substrate.
Stmicroelectronics (tours) Sas


06/09/16
20160163648 

Method for forming an electrical contact


A method for forming an electrical contact to a semiconductor structure is provided. The method includes providing a semiconductor structure, providing a metal on an area of said semiconductor structure, wherein said area exposes a semiconductor material and is at least a part of a contact region, converting said metal to a si-comprising or a ge-comprising alloy, thereby forming said electrical contact on said area, wherein said converting is done by performing a vapor-solid reaction, whereby said semiconductor structure including said metal is subjected to a silicon-comprising precursor gas or a germanium-comprising precursor gas..
Imec Vzw


06/09/16
20160160364 

Photocatalytic metamaterial based on plasmonic near perfect optical absorbers


The present disclosure provides a photocatalyst that can utilize plasmon resonance based, near-perfect optical absorption for performing and enhancing photocatalytic reactions. The photocatalyst comprises a substrate and a reflective layer adjacent to the substrate.
Pacific Integrated Energy, Inc.


06/02/16
20160156156 

Semiconductor interband cascade lasers with enhanced optical confinement


A semiconductor interband cascade laser having an outer cladding layer formed from a material selected from the group consisting of a high-doped semiconductor material, a dielectric material and/or a metal, having an outer cladding layer refractive index and/or permittivity; an intermediate cladding layer formed from a semiconductor material having an intermediate cladding layer refractive index and/or permittivity which is greater than the outer cladding layer refractive index and/or permittivity; and a waveguide core having an active region having an active region refractive index and/or permittivity, the active region configured to generate light based on interband transitions, the light defining a lasing wavelength, wherein the intermediate cladding layer is positioned between the outer cladding layer and the waveguide core; and wherein the active region refractive index and/or permittivity is greater than the intermediate cladding layer refractive index and/or permittivity. The waveguide core may further include at least one separate confinement layer (scl) positioned between the active region and the intermediate cladding layer..
The Board Of Regents Of The University Of Oklahoma


06/02/16
20160155964 

Organic semiconductor composition, organic thin film transistor, electronic paper and display device


The present invention provides an organic semiconductor composition, which improves the insulation reliability of an organic thin film transistor without greatly reducing the mobility of the organic thin film transistor, and an organic thin film transistor, electronic paper, and a display device which are prepared by using the organic semiconductor composition. The organic semiconductor composition of the present invention contains an organic semiconductor material and an anti-migration agent containing at least either a compound x, which contains at least two or more groups selected from the group consisting of a group represented by formula (a) and a group represented by formula (b), or a compound y which is represented by formula (c)..
Fujifilm Corporation


06/02/16
20160155897 

Nanostructure semiconductor light emitting device


A nanostructure semiconductor light emitting device includes a base layer, an insulating layer, a plurality of light emitting nanostructures, and a contact electrode. The base layer is formed of a first conductivity-type semiconductor material.
Samsung Electronic Co., Ltd.


06/02/16
20160155893 

Engineered substrates for semiconductor devices and associated systems and methods


Engineered substrates for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a transducer structure having a plurality of semiconductor materials including a radiation-emitting active region.
Micron Technology, Inc.


06/02/16
20160155870 

A solar cell structure and a its fabrication


A solar cell structure (1) and a method of its fabrication, the structure comprising an array of elongated nanowires (2) made in a semiconductor material having a direct band gap. Each nanowire (2) has at least a first (3) and a second (4) sections.
Sol Voltaics Ab


06/02/16
20160155844 

Asymmetric ultrathin soi mos transistor structure and manufacturing same


A method for manufacturing an asymmetric super-thin soimos transistor is disclosed. The method comprises: a.
Institute Of Microelectronics, Chinese Academy Of Sciences


06/02/16
20160155834 

Iii-nitride device having a buried insulating region


A semiconductor device includes a compound semiconductor material on a semiconductor substrate, the compound semiconductor material having a channel region, a source region, a drain region spaced apart from the source region, the channel region extending between the source region and the drain region, and an insulating region positioned under the channel region in an active region of the semiconductor device so that the insulating region is separated from the channel region by a portion of the compound semiconductor material in the active region. The active region includes the source, the drain and the channel region.
Infineon Technologies Austria Ag


06/02/16
20160155805 

Secondary use of aspect ratio trapping holes as edram structure


A semiconductor structure is provided according to a method in which an aspect ratio trapping process is employed. The structure includes a semiconductor substrate comprising a first semiconductor material having a first lattice constant.
International Business Machines Corporation


06/02/16
20160155798 

Method for manufacturing a semiconductor structure, semiconductor structure, and electronic device


A method for manufacturing a semiconductor structure comprises the steps of: providing a substrate including a first semiconductor material; forming a dielectric layer on a surface of the substrate; forming an opening in the dielectric layer having a bottom reaching the substrate; providing a second semiconductor material in the opening and on the substrate, the second semiconductor material being en-capsulated by a further dielectric material thereby forming a filled cavity; melting the second semiconductor material in the cavity; recrystallizing the second semi-conductor material in the cavity; laterally removing the second semiconductor material at least partially for forming a lateral surface at the second semiconductor material; and forming a third semiconductor material on the lateral surface of the second semiconductor material, wherein the third semiconductor material is different from the second semiconductor material.. .
International Business Machines Corporation


06/02/16
20160155735 

Semiconductor component including a short-circuit structure


A semiconductor component including a short-circuit structure. One embodiment provides a semiconductor component having a semiconductor body composed of doped semiconductor material.
Infineon Technologies Ag


06/02/16
20160153898 

Decomposition detecting unit, concentration measuring unit, and concentration control apparatus


Provided is a decomposition detecting unit that despite a simple configuration, can detect whether or not decomposition occurs in material gas resulting from the vaporization of a semiconductor material. The decomposition detecting unit includes: an ndir type or laser absorption spectroscopy type absorbance measuring mechanism that measures first absorbance, which is absorbance at a wavelength at which a semiconductor material absorbs light, and second absorbance, which is absorbance at a wavelength at which a material produced when the semiconductor material decomposes absorbs light, of mixed gas containing material gas resulting from the vaporization of the semiconductor material; and a decomposition detection part that detects the decomposition in the material gas on the basis of the ratio between first concentration calculated on the basis of the first absorbance and the second absorbance and second concentration calculated on the basis of the second absorbance..
Horiba Stec, Co., Ltd.


05/26/16
20160149083 

Semiconductor material including different crystalline orientation zones and related production process


The intermediate layer being intended to be vaporised spontaneously during the step consisting of growing the layer of element iii nitride via epitaxy.. .

05/26/16
20160149025 

Semiconductor device and manufacturing the same


Provided is a technique of securing reliability of a gate insulating film, as much as in a si power mosfet, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an sic power mosfet. In order to achieve this object, in the in the sic power mosfet, the gate electrode ge is formed in contact with the gate insulating film gox, and is formed of the polycrystalline silicon film pf1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film pf2 formed in contact with the polycrystalline silicon film pf1, and having any thickness..
Hitachi Ltd.


05/26/16
20160149024 

High-electron mobility transistor and process to form the same


An electron device formed by primarily nitrides semiconductor materials and a method to form the electron device are disclosed. The electron device includes, on the sic substrate, a buffer layer of aln, a channel layer of gan, and an electron supplying layer of algan.
Sumitomo Electric Industries, Ltd.


05/26/16
20160149022 

Heterojunction field effect transistor (hfet) variable gain amplifier having variable transconductance


A heterojunction semiconductor field effect transistor hfet having a pair of layers of different semiconductor materials forming a quantum well within the structure to support the 2deg. Source, drain and gate electrodes are disposed above the channel.
Raytheon Company


05/26/16
20160148870 

Low-k dielectric pore sealant and metal-diffusion barrier formed by doping and forming the same


A diffusion barrier and a method to form the diffusion bather are disclosed. A trench structure is formed in an inter layer dielectric (ild).
Samsung Electronics Co., Ltd.


05/26/16
20160148846 

Semiconductor structure containing low-resistance source and drain contacts


Semiconductor structures having a source contact and a drain contact that exhibit reduced contact resistance and methods of forming the same are disclosed. In one embodiment of the present application, the reduced contact resistance is provided by forming a layer of a dipole metal or metal-insulator-semiconductor (mis) oxide between an epitaxial semiconductor material (providing the source region and the drain region of the device) and an overlying metal semiconductor alloy.
International Business Machines Corporation


05/26/16
20160148807 

Polycrystalline semiconductor nanostructured material


A method for producing a network of nanostructures from at least one semiconductor material, including a step of forming nanostructures on the surface of a substrate, at least a part of the nanostructures having areas of contact between each other, comprising, in sequence and after the step of forming: a step of deoxidising the surface of the nanostructures and a step of reinforcing the bond between the nanostructures at the contact areas.. .
Institut Polytechnique De Grenoble


05/26/16
20160146752 

Device for detecting at least one gaseous analyte and the production thereof


A device for detecting at least one gaseous analyte comprises a detection section including a semiconductor substrate and at least one sensor element, which is arranged on the semiconductor substrate. The at least one sensor element includes two electrodes and a solid electrolyte layer arranged between the electrodes.
Robert Bosch Gmbh


05/26/16
20160146692 

Package for semiconductor devices sensitive to mechanical and thermo-mechanical stresses, such as mems pressure sensors


A surface mounting device has one body of semiconductor material such as an asic, and a package surrounding the body. The package has a base region carrying the body, a cap and contact terminals.
Stmicroelectronics, Inc.


05/26/16
20160145767 

Deposition systems having access gates at desirable locations, and related methods


Deposition systems include a reaction chamber, and a substrate support structure disposed at least partially within the reaction chamber. The systems further include at least one gas injection device and at least one vacuum device, which together are used to flow process gases through the reaction chamber.
Soitec


05/19/16
20160141529 

Method for producing an organic cmos circuit and organic cmos circuit protected against uv radiation


An organic cmos circuit including a substrate having an n-type organic transistor and a p-type organic transistor formed thereon, the transistors respectively including a layer of n-type semiconductor material and a layer of p-type semiconductor material. A surface of each of the semiconductor material layers, opposite to the substrate, is covered with an anti-ultraviolet layer made of electrically-insulating material absorbing and/or reflecting ultra-violet rays..
Commissariat A L'energie Atomique Et Aux Energies Alternatives


05/19/16
20160141463 

Composite having semiconductor structures embedded in a matrix


Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot.

05/19/16
20160141408 

Super junction field effect transistor with internal floating ring


A super junction field effect transistor (fet) device includes a charge compensation region disposed on a substrate of semiconductor material. The charge compensation region includes a set of strip-shaped p− type columns, a floating ring-shaped p− type column that surrounds the set of strip-shaped p− type columns, and a set of ring-shaped p− type columns that surrounds the floating ring-shaped p− type column.
Ixys Corporation


05/19/16
20160141294 

Three-dimensional memory structure with multi-component contact via structure and making thereof


A contact via structure can include a ruthenium portion formed by selective deposition of ruthenium on a semiconductor surface at the bottom of a contact trench. The ruthenium-containing portion can reduce contact resistance at the interface with an underlying doped semiconductor region.
Sandisk Technologies Inc.


05/19/16
20160141220 

Hetero-bipolar transistor and producing the same


A semiconductor device provided with a substrate made of material except for semiconductors and having thermal conductivity greater than that of the semiconductor material. The semiconductor device provides, on the support, a metal layer, a primary mesa, and electrodes formed on the primary mesa.
Sumitomo Electric Industries, Ltd.


05/19/16
20160141205 

Finfets with different fin height and epi height setting


An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/19/16
20160140450 

Atomistic quantum dots


A quantum device is provided that includes controllably quantum mechanically coupled dangling bonds extending from a surface of a semiconductor material. Each of the controllably quantum mechanically coupled dangling bonds has a separation of at least one atom of the semiconductor material.
The Governors Of The University Of Alberta


05/12/16
20160133794 

Optoelectronic semiconductor chip


An optoelectronic semiconductor chip includes a multiplicity of active regions arranged at a distance from one another, and a continuous current spreading layer, wherein at least one of the active regions has a main extension direction, one of the active regions has a core region formed with a first semiconductor material, the active region has an active layer covering the core region at least in directions transversely with respect to the main extension direction of the active region, the active region has a cover layer formed with a second semiconductor material and covers the active layer at least in directions transversely with respect to the main extension direction of the active region, and the current spreading layer covers all cover layers of the active region.. .
Osram Opto Semiconductors Gmbh


05/12/16
20160133787 

Diode-based devices and methods for making the same


In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


05/12/16
20160133751 

Hydrogenated p-channel metal oxide semiconductor thin film transistors


This disclosure provides p-type metal oxide semiconductor materials that display good thin film transistor (tft) characteristics. Also provided are tfts including channels that include p-type oxide semiconductors, and methods of fabrication.
Qualcomm Incorporated


05/12/16
20160133750 

Fabrication process for mitigating external resistance of a multigate device


A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench.. .
International Business Machines Corporation


05/12/16
20160133740 

Semiconductor device comprising a multi-layer channel region


One illustrative device disclosed herein includes, among other things, a substrate made of a first semiconductor material, at least one layer of insulating material positioned above the substrate, a fin structure positioned above the layer of insulating material and the substrate, the fin structure comprising first, second and third layers of semiconductor material, wherein the semiconductor materials of the first, second and third layers are different than the first semiconductor material, and a gate structure around a portion of the fin structure comprised of the first, second and third layers of semiconductor material.. .
Globalfoundries Inc.


05/12/16
20160133735 

Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition


Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate.

05/12/16
20160133715 

Semiconductor device


The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other.
Renesas Electronics Corporation


05/12/16
20160133709 

Monolithic integrated semiconductor structure


A monolithic integrated semiconductor structure includes: a) an si carrier layer, b) a layer having the composition bxalygazntpv, wherein x=0-0.1, y=0-1, z=0-1, t=0-0.1 and v=0.9-1, c) a relaxation layer having the composition bxalygazinupvsbw, wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1 and w=0-1, wherein w and/or u is on the side facing toward layer a) or b) smaller than, equal to, or bigger than on the side facing away from layer a) or b) and wherein v=1−w and/or y=1−u−x−z, and d) a group iii/v, semiconductor material. The sum of the above stoichiometric indices for all group iii elements and for all group v elements are each equal to one..
Nasp Iii/v Gmbh


05/12/16
20160133694 

Structures and methods with reduced sensitivity to surface charge


The present application provides (in addition to more broadly applicable inventions) improvements which are particularly applicable to two-sided power semiconductor devices which use bipolar conduction. In this class of devices, the inventor has realized that two or three of the four (or more) semiconductor doping components which form the carrier-emission structures and control structures in the active device (array) portion of a two-sided power device can also be used, with surprising advantages, to form field-limiting rings around the active arrays on both surfaces.
Ideal Power Inc.


05/12/16
20160133525 

Semiconductor devices and methods of manufacturing the same


In a method of manufacturing a semiconductor device, a first gate structure and a second gate structure are formed on a substrate in a first region and a second region, respectively. A first semiconductor pattern including germanium is formed in the first region on the substrate.

05/12/16
20160133517 

Self-limited, anisotropic wet etching of transverse vias in microfluidic chips


The present invention is notably directed to a method of fabrication of a microfluidic chip (1). Comprising: providing (s10-s20) a wafer (10, 12) of semiconductor material having a diamond cubic crystal structure, exhibiting two opposite main surfaces (s1, s2), one on each side of the wafer, and having, each, a normal in the <100> or <110> direction; and performing (s30) self-limited, anisotropic wet etching steps on each of the two main surfaces on each side of the wafer, to create a via (20, 20a) extending transversely through the thickness of the wafer, at a location such that the resulting via connects an in-plane microchannel (31) on a first one (51) of the two main surfaces to a second one (s2) of the two main surfaces, the via exhibiting slanted sidewalls (20s) as a result of the self-limited wet etching.
International Business Machines Corporation


05/12/16
20160133506 

Method of fabricating semiconductor device isolation structure


A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components.
Taiwan Semiconductor Manufacturing Company, Ltd.




Semiconductor Material topics: Semiconductor, Semiconductor Material, Semiconductor Device, Transistors, Surfactant, Electric Conversion, Transparent Conductive Oxide, Semiconductor Substrate, Heating Devices, Semiconductor Devices, Organic Electroluminescence, Buffer Layer, Integrated Circuit, Crystallin, Electronic Device

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