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Semiconductor Material patents



      

This page is updated frequently with new Semiconductor Material-related patent applications.




Date/App# patent app List of recent Semiconductor Material-related patents
04/07/16
20160099390 
 Optoelectronic semiconductor component patent thumbnailOptoelectronic semiconductor component
An optoelectronic semiconductor component includes a luminescent diode chip including a radiation passage face through which primary electromagnetic radiation leaves the luminescent diode chip when in operation, and a filter element that covers the radiation passage face of the luminescent diode chip at least in places, wherein the filter element prevents passage of some of the primary electromagnetic radiation in the uv range, and the filter element consists of a ii-vi compound semiconductor material.. .
Osram Opto Semiconductors Gmbh


04/07/16
20160099376 
 Method of manufacturing nanostructure semiconductor light-emitting device patent thumbnailMethod of manufacturing nanostructure semiconductor light-emitting device
According to an example embodiment, a method of manufacturing a nanostructure semiconductor light-emitting device includes forming nanocores of a first-conductivity type nitride semiconductor material on abase layer to be spaced apart from each other, and forming a multilayer shell including an active layer and a second-conductivity type nitride semiconductor layers on surfaces of each of the nanocores. At least a portion the multilayer shell is formed by controlling at least one process parameter of a flux of source gas, a flow rate of source gas, a chamber pressure, a growth temperature, and a growth rate so as to have a higher film thickness uniformity..
Samsung Electronics Co., Ltd.


04/07/16
20160099368 
 Nanostructured units formed inside a silicon material and the manufacturing process to perform them therein patent thumbnailNanostructured units formed inside a silicon material and the manufacturing process to perform them therein
The invention bears on elementary nanoscale units nanostructured-formed inside a silicon material and the manufacturing process to implement them. Each elementary nanoscale unit is created by means of a limited displacement of two si atoms outside a crystal elementary unit.
Segton Advanced Technology Sas


04/07/16
20160099343 
 Tunneling field effect transistor and methods of making such a transistor patent thumbnailTunneling field effect transistor and methods of making such a transistor
One illustrative method of forming a tfet device includes forming a first semiconductor material that extends for a full length of a drain region, a gate region and a source region of the device, masking the drain region while exposing at least a portion of the gate region and exposing the source region, forming a second semiconductor material above the gate region and above the source region, forming a third semiconductor material above the second semiconductor material and above the gate region and above the source region, the third semiconductor material being doped with an opposite type of dopant material than in the first semiconductor material, masking the drain region, and forming a gate structure above at least a portion of the exposed gate region.. .
Globalfoundries Inc.


04/07/16
20160099329 
 Suspended body field effect transistor patent thumbnailSuspended body field effect transistor
A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed.
Globalfoundries Inc.


04/07/16
20160099318 
 Structure and  transient voltage suppression devices with a two-region base patent thumbnailStructure and transient voltage suppression devices with a two-region base
A transient voltage suppression (tvs) device and a method of forming the device are provided. The tvs device includes a first layer of wide band-gap semiconductor material formed of a first conductivity type material, a second layer of wide band-gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, the second layer including a first concentration of dopant.
General Electric Company


04/07/16
20160099249 
 Integrated fin and strap structure for an access transistor of a trench capacitor patent thumbnailIntegrated fin and strap structure for an access transistor of a trench capacitor
At least one dielectric pad layer is formed on a semiconductor-on-insulator (soi) substrate. A deep trench is formed in the soi substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the soi substrate.
International Business Machines Corporation


04/07/16
20160099200 
 Aluminum alloy lead frame for a semiconductor device and corresponding manufacturing process patent thumbnailAluminum alloy lead frame for a semiconductor device and corresponding manufacturing process
Described herein is a semiconductor device provided with: a die of semiconductor material; a lead frame, defining a support plate, which is designed to carry the die, and leads, which are designed to be electrically coupled to the die; and a package, of encapsulating material, which is designed to encapsulate the die and partially coming out of which are the leads. The lead frame has as constituent material an aluminum alloy comprising a percentage of silicon ranging between 1% and 1.5%..
Stmicroelectronics S.r.l.


04/07/16
20160096993 
 Semiconductor structure having nanocrystalline core and nanocrystalline shell pairing with compositional transition layer patent thumbnailSemiconductor structure having nanocrystalline core and nanocrystalline shell pairing with compositional transition layer
Semiconductor structures having a nanocrystalline core and nanocrystalline shell pairing with compositional transition layers are described. In an example, a semiconductor structure includes a nanocrystalline core composed of a first semiconductor material.
Pacific Light Technologies Corp.


03/31/16
20160094015 
 Quantum cascade laser patent thumbnailQuantum cascade laser
A quantum cascade laser includes a substrate having a principal surface including first and second regions arranged along a first axis; a laser structure disposed on the principal surface in the second region, the laser structure having an end facet intersecting the first axis, the laser structure including a stripe-shaped stacked semiconductor layer extending along the first axis; and a distributed bragg reflection structure disposed on the principal surface in the first region, the distributed bragg reflection structure including a semiconductor wall made of a single semiconductor material, the distributed bragg reflection structure being optically coupled to the end facet of the laser structure. The semiconductor wall has first and second side surfaces that intersect the first axis and extend along a second axis intersecting the principal surface.
Sumitomo Electric Industries, Ltd


03/31/16
20160093807 

Fullerene derivative and n-type semiconductor material


Ring a represents a fullerene ring.. .

03/31/16
20160093762 

Anneal techniques for chalcogenide semiconductors


Techniques for precisely controlling the composition of volatile components (such as sulfur (s), selenium (se), and tin (sn)) of chalcogenide semiconductors in real-time—during production of the material are provided. In one aspect, a method for forming a chalcogenide semiconductor material includes providing a s source(s) and a se source(s); heating the s source(s) to form a s-containing vapor; heating the se source(s) to form a se-containing vapor; passing a carrier gas first through the s-containing vapor and then through the se-containing vapor, wherein the s-containing vapor and the se-containing vapor are transported via the carrier gas to a sample; and contacting the s-containing vapor and the se-containing vapor with the sample under conditions sufficient to form the chalcogenide semiconductor material.
International Business Machines Corporation


03/31/16
20160093743 

Thin film transistor substrate and fabricating the same


A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer partially overlapping the gate electrode, the semiconductor layer including an oxide semiconductor material; a source electrode and a drain electrode disposed on the semiconductor layer, the source electrode and the drain electrode including a barrier layer, a main wiring layer disposed on the barrier layer, and a first capping layer disposed on the main wiring layer and being spaced apart from each other; and second capping layers covering lateral surfaces of the main wiring layers of the source and drain electrodes.. .
Samsung Display Co., Ltd.


03/31/16
20160093739 

Finfet semiconductor device with isolated channel regions


A finfet device includes a fin structure positioned in the channel region of the device and a gate structure positioned above the fin structure, wherein the fin structure includes a portion of a semiconductor substrate and an epi semiconductor material positioned vertically above the portion of the semiconductor substrate. Sidewall spacers are positioned adjacent the gate structure and a fin cavity is positioned in source/drain regions of the device, wherein the fin structure has edges in a gate width direction that are substantially self-aligned with the sidewall spacers and the semiconductor substrate defines the bottom of the fin cavity.
Globalfoundries Inc.


03/31/16
20160093738 

Methods for finfet source/drain formation and finfet devices


A semiconductor device includes a fin structure of a first semiconductor material on a substrate. The fin structure has a source region, a drain region, and a channel region between the source region and the drain region.
Semiconductor Manufacturing International (shanghai) Corporation


03/31/16
20160093734 

Semiconductor device and manufacturing method thereof


A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.


03/31/16
20160093720 

Epitaxial growth of material on source/drain regions of finfet structure


A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer.. .
International Business Machines Corporation


03/31/16
20160093709 

Transistor-containing constructions and memory arrays


Some embodiments include transistor-containing constructions having gate material within an opening in a semiconductor material and spaced from the semiconductor material by gate dielectric material. The opening has a wide lower region beneath a narrow upper region.
Micron Technology, Inc.


03/31/16
20160093700 

Double aspect ratio trapping


A semiconductor structure is provided by a process in which two aspect ratio trapping processes are employed. The structure includes a semiconductor substrate portion of a first semiconductor material having a first lattice constant.
International Business Machines Corporation


03/31/16
20160093698 

Method for doping a gan-base semiconductor


The method for doping a gan-base semiconductor to fabricate a p-n junction includes a first step consisting in providing a substrate including a gan-base semiconductor material layer covered by a silicon-base mask. The method includes a second step of performing implantation of impurities in the mask so as to transfer additional dopant impurities of si type by diffusion from the mask to the semiconductor material layer to form an n-type area adjacent to a p-type area.
Commissariat Á L'energie Atomique Et Aux Energies Alternatives


03/31/16
20160093662 

Back side illumination photodiode of high quantum efficiency


A back side illumination photodiode includes a light-receiving back side surface of a semiconductor material substrate. An area of the light-receiving back side surface includes a recess.
Commissariat A L'energie Atomique Et Aux Energies Alternatives


03/31/16
20160093639 

Semiconductor-on-insulator (soi) device and related methods for making same using non-oxidizing thermal treatment


A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (soi) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer..
Stmicroelectronics, Inc.


03/31/16
20160093619 

Iii-v finfet cmos with iii-v and germanium-containing channel closely spaced


Closely spaced iii-v compound semiconductor fins and germanium-containing semiconductor fins are provided by utilizing mandrel structures for iii-v compound semiconductor material epitaxial growth and subsequent fin formation. Mandrel structures are formed on a semiconductor material stack that includes an uppermost layer of a relaxed germanium-containing material layer.
International Business Machines Corporation


03/31/16
20160093614 

Method and structure for improving finfet with epitaxy source/drain


Isolation structures are formed to laterally surround a gate material block such that each sidewall of the gate material block abuts a corresponding sidewall of the isolation structures. Sidewalls of the gate material bock define ends of gate structures to be subsequently formed.
International Business Machines Corporation


03/31/16
20160093510 

Method for performing activation of dopants in a gan-base semiconductor layer


The method for performing activation of p-type dopants in a gan-base semiconductor comprises a first step consisting in providing a substrate comprising (i) a gan-base semiconductor material layer comprising p-type electric dopant impurities, (ii) a cap block devoid of any silicon-base compound, in contact with the semiconductor material layer, and (iii) a silicon-base covering layer covering the cap block. The method comprises a second heat treatment step at a temperature of more than 900° c.
Commissariat A L'energie Atomique Et Aux Energies Alternatives


03/31/16
20160093496 

Method for fabricating an improved gan-based semiconductor layer


The invention relates to a post-activation method of dopants in a doped and activated gan-base semiconductor layer, including the following successive steps: providing said doped and activated substrate, eliminating a part of the semiconductor material layer.. .
Commissariat À L' Énergie Atomique Et Aux Énergies Alternatives


03/31/16
20160093495 

Method for performing activation of dopants in a gan-base semiconductor layer by successive implantations and heat treatments


The method for performing activation of n-type or p-type dopants in a gan-base semiconductor includes the following steps: providing a substrate including a gan-base semiconductor material layer, performing the following successive steps at least twice: implanting electric dopant impurities in the semiconductor material layer, performing heat treatment so as to activate the electric dopant impurities in the semiconductor material layer, a cap layer covering the semiconductor material layer when the heat treatment is performed, two implantation steps of electric dopant impurities being separated by a heat treatment step.. .
Commissariat Á L' Énergie Atomique Et Aux Énergies Alternatives


03/24/16
20160087160 

Iii-v photonic integrated circuits on silicon substrate


A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a iii-v optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure.
International Business Machines Corporation


03/24/16
20160087144 

Solid state lighting devices without converter materials and associated methods of manufacturing


Solid state lighting devices that can produce white light without a phosphor are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials.
Micron Technology, Inc.


03/24/16
20160087103 

Finfet with buried insulator layer and forming


A fin structure suitable for a finfet and having a buried insulator layer is disclosed. In an exemplary embodiment, a semiconductor device comprises a substrate with a first semiconductor material and having a fin structure formed thereupon.
Taiwan Semiconductor Manufacturing Company, Ltd.


03/24/16
20160087099 

Finfet with heterojunction and improved channel control


Roughly described, a computer program product describes a transistor with a fin, a fin support, a gate, and a gate dielectric. The fin includes a first crystalline semiconductor material which includes a channel region of the transistor between a source region of the first transistor and a drain region of the transistor.
Synopsys, Inc.


03/24/16
20160087096 

Semiconductor device and related fabrication methods


Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first region of semiconductor material having a first conductivity type and a first dopant concentration, a second region of semiconductor material having a second conductivity type overlying the first region, a drift region of semiconductor material having the first conductivity type overlying the second region, and a drain region of semiconductor material having the first conductivity type.

03/24/16
20160087080 

Integrated vertical trench mos transistor


A vtmos transistor in semiconductor material of a first type of conductivity includes a body region of a second type of conductivity and a source region of the first type of conductivity. A gate region extends into the main surface through the body region and is insulated from the semiconductor material.
Stmicroelectronics S.r.l.


03/24/16
20160086979 

Semiconductor device


One object is to provide a new semiconductor device whose standby power is sufficiently reduced. The semiconductor device includes a first power supply terminal, a second power supply terminal, a switching transistor using an oxide semiconductor material and an integrated circuit.
Semiconductor Energy Laboratory Co., Ltd.


03/24/16
20160086974 

Method for fabricating semiconductor structures including transistor channels having different strain states, and related semiconductor structures


Methods of fabricating a semiconductor structure include implanting ion into a second region of a strained semiconductor layer on a multi-layer substrate to amorphize a portion of crystalline semiconductor material in the second region of the strained semiconductor layer without amorphizing a first region of the strained semiconductor layer. The amorphous region is recrystallized, and elements are diffused within the semiconductor layer to enrich a concentration of the diffused elements in a portion of the second region of the strained semiconductor layer and alter a strain state therein relative to a strain state of the first region of the strained semiconductor layer.
Soitec


03/24/16
20160086858 

Structure and advanced bulk fin isolation


A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant..
International Business Machines Corporation


03/24/16
20160086803 

Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers


Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (soi) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer.
Soitec


03/24/16
20160084764 

Separation of doping density and minority carrier lifetime in photoluminescence measurements on semiconductor materials


Methods are presented for separating the effects of background doping density and effective minority carrier lifetime on photoluminescence (pl) generated from semiconductor materials. In one embodiment the background doping density is measured by another technique, enabling pl measurements to be analysed in terms of effective minority carrier lifetime.
Bt Imaging Pty Ltd


03/17/16
20160079810 

Photovoltaics optimized for laser remote power applications at eye-safer wavelengths


A system for transmitting power to a remote equipment, the system including a first laser source that generates a first laser beam; a first tracking device operatively connected to the first laser source, wherein the first tracking device controls a direction of the first laser beam; and a first photovoltaic device operatively connected to the remote equipment located remotely from the first laser source and the first tracking device, wherein the first photovoltaic device includes a semiconductor material that generates an electric current in response to absorbing the first laser beam, and wherein a first wavelength of the first laser beam is within an eye-safer range.. .
The Government Of The United States Of America, As Represented By The Secretary Of The Navy


03/17/16
20160079428 

Finfet structure and manufacture method


A method for forming a finfet transistor structure includes providing a substrate with a buried oxide layer and a layer of first semiconductor material. One or more fin structures are formed on the first layer of semiconductor material using a hard mask layer.
Semiconductor Manufacturing International (shanghai) Corporation


03/17/16
20160079425 

Device having epi film in substrate trench


The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component.
Taiwan Semiconductor Manufacturing Company, Ltd.


03/17/16
20160079421 

Fin field effect transistor including self-aligned raised active regions


Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask structures.
International Business Machines Corporation


03/17/16
20160079397 

Partial fin on oxide for improved electrical isolation of raised active regions


A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure.
Globalfoundries Inc.


03/17/16
20160079391 

Method of fabricating a vertical mos transistor


The disclosure relates to a method of fabricating a vertical mos transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.. .
Stmicroelectronics (rousset) Sas


03/17/16
20160079388 

Production of spacers at flanks of a transistor gate


The production of spacers at flanks of a transistor gate, including a step of forming a dielectric layer covering the gate and a peripheral region of a layer of semiconductor material surrounding the gate, including forming a superficial layer covering the gate and the peripheral region; partially removing the superficial layer configured so as to completely remove the superficial layer at the peripheral region while preserving a residual part of the superficial layer at the flanks; and selective etching of the dielectric layer vis-à-vis the material of the residual part of the superficial layer and vis-à-vis the semiconductor material.. .
Stmicroelectronics (crolles 2) Sas


03/17/16
20160079372 

Device contact structures including heterojunctions for low contact resistance


A semiconductor device can include a channel region with a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device and a metal contact. A source/drain region can include a semiconductor material alloy including a second semiconductor material and at least one heterojunction located between the metal contact and the channel region, wherein the heterojunction forms a band-edge offset for the majority carrier that is less than or equal to about 0.2 ev..

03/17/16
20160079362 

Method of forming an epitaxial semiconductor layer in a recess and a semiconductor device having the same


A method of manufacturing a semiconductor device may include: etching a recess in a semiconductor substrate, where the etching produces a metal residue over a surface of the recess. The recess may thereafter be exposed to a cleaning process that causes the metal residue to etch at least one fissure in the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


03/17/16
20160079359 

High voltage field effect transistors


Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate.
Intel Corporation


03/17/16
20160079356 

Electronic device of vertical mos type with termination trenches having variable depth


An electronic device is integrated on a chip of semiconductor material having a main surface and a substrate region with a first type of conductivity. The electronic device has a vertical mos transistor, formed in an active area having a body region with a second conductivity type.
Stmicroelectronics S.r.l.


03/17/16
20160079316 

Light emitting device including tandem structure


A light emitting device comprising: a pair of electrodes; two or more light emitting elements disposed between the electrodes in a stacked arrangement, wherein a light emitting element comprises a layer comprising an emissive material; and a charge generation element disposed between adjacent light emitting elements in the stacked arrangement, the charge generation element comprising a first layer comprising an inorganic n-type semiconductor material, and a second layer comprising a hole injection material. A charge generation element is also disclosed..
Qd Vision, Inc.


03/17/16
20160079274 

Transistors, semiconductor constructions, and methods of forming semiconductor constructions


Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion.
Micron Technology, Inc.


03/17/16
20160079245 

Semiconductor device


The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor.
Semiconductor Energy Laboratory Co., Ltd.


03/17/16
20160079233 

Iii-v semiconductor material based ac switch


A power circuit is described that includes a semiconductor die and a coupling structure. The semiconductor die includes a common substrate and a iii-v semiconductor layer formed atop the common substrate.
Infineon Technologies Austria Ag


03/17/16
20160079218 

Electrostatic protection device and light-emitting module


An electrostatic protection device includes a base member formed of a high-resistance semiconductor material. External connecting lands are formed on a first principal surface of the base member along a first direction with a space therebetween.
Murata Manufacturing Co., Ltd.


03/17/16
20160079181 

Traceable integrated circuits and production method thereof


An embodiment of a method for producing traceable integrated circuits includes forming on a wafer of semiconductor material functional regions for implementing specific functionalities of corresponding integrated circuits, forming at least one seal ring around each functional region of the corresponding integrated circuit, and forming on each integrated circuit at least one marker indicative of information of the integrated circuit. Forming on each integrated circuit at least one marker may include forming the at least one marker on at least a portion of the respective seal ring that is visible..
Stmicroelectronics S.r.l.


03/17/16
20160079166 

Programmable electrical fuse in keep out zone


An method including forming a back end of the line (beol) wiring portion directly on top of a semiconductor base portion, the beol wiring portion including a plurality of layers of a metallic material and a dielectric material and excluding a semiconductor material, forming a through-substrate via through the beol wiring portion and the semiconductor base portion, forming an electronic fuse in the beol wiring portion adjacent to the through-substrate via, and forming a guard ring in the beol wiring portion surrounding the through-substrate via and the electronic fuse in the beol wiring portion, the through-substrate via in the semiconductor base portion being free from the guard ring.. .
International Business Machines Corporation


03/17/16
20160079094 

Methods of protecting peripheries of in-process semiconductor wafers and related in-process wafers and systems


Methods of processing semiconductor wafers may involve, for example, encapsulating an active surface and each side surface of a wafer of semiconductor material, a plurality of semiconductor devices located on the active surface of the wafer, an exposed side surface of an adhesive material located on a back side surface of the wafer, and at least a portion of a side surface of a carrier substrate secured to the wafer by the adhesive material in an encapsulation material. At least a portion of the side surface of the adhesive material may be exposed by removing at least a portion of the encapsulation material.
Micron Technology, Inc.


03/17/16
20160077218 

Integrated detection device, in particular detector of particles such as particulates or alpha particles


A detection device is formed in a body of semiconductor material having a first face, a second face, and a cavity. A detection area formed in the cavity, and a gas pump is integrated in the body and configured to force movement of gas towards the detection area.
Stmicroelectronics S.r.i.


03/17/16
20160076962 

Integrated transducer provided with a temperature sensor and sensing a temperature of the transducer


A pressure sensor includes a body made of semiconductor material having a first type of conductivity and a pressure-sensitive structure having the first type of conductivity defining a suspended membrane. One or more piezoresistive elements having a second type of conductivity (p) are formed in the suspended membrane.
Stmicroelectronics S.r.l.


03/17/16
20160075808 

Semiconductor materials prepared from dithienylvinylene copolymers


Disclosed herein are new semiconductor materials prepared from dithienylvinylene copolymers with aromatic or heteroaromatic π-conjugated systems. Such copolymers, with little or no post-deposition heat treatment, can exhibit high charge carrier mobility and/or good current modulation characteristics.

03/10/16
20160072084 

Semiconductor structure and its production


The present invention relates to a semiconductor structure and a method for its production, the semiconductor structure comprising at least one conductor region and at least two semiconductor regions, which semiconductor regions are partly separated by the at least one conductor region. The at least one conductor region comprises openings extending between the semiconductor regions which are partly separated by the respective conductor region.
Basf Se


03/10/16
20160072057 

Integrated magnetoresistive sensor, in particular three-axis magnetoresistive sensor and manufacturing method thereof


An integrated magnetoresistive device includes a substrate of semiconductor material that is covered, on a first surface, by an insulating layer. A magnetoresistor of ferromagnetic material extends within the insulating layer and defines a sensitivity plane of the sensor.
Stmicroelectronics S.r.l.


03/10/16
20160072034 

Metals-semiconductor nanowire composites


When fabricating thermoelectric devices using bulk semiconductor materials and single crystal substrates, the performance of the thermoelectric device can be limited by the interdependence between electrical conductivity, seebeck coefficient, and thermal conductivity in the bulk semiconductor material. Additionally, the properties of bulk semiconductor materials can lead to expensive, bulky, and complex power generation systems.
The Regents Of The University Of California


03/10/16
20160071996 

Solar cell having an emitter region with wide bandgap semiconductor material


Solar cells having emitter regions composed of wide bandgap semiconductor material are described. In an example, a method includes forming, in a process tool having a controlled atmosphere, a thin dielectric layer on a surface of a semiconductor substrate of the solar cell.

03/10/16
20160071985 

Solar cell


An solar cell is provided comprising a photoelectric conversion layer formed on a substrate formed of a semiconductor material, and a first finger electrode formed of printed conductive paste to a main surface side of the photoelectric conversion layer, wherein an average of standard deviations of heights of uneveness on a surface of the first finger electrode is 5.0 μm or less. The first finger electrode may be formed on a back surface side of the solar cell opposite to a light-receiving surface side.
Panasonic Intellectual Property Management Co., Ltd.


03/10/16
20160071979 

Fin device with blocking layer in channel region


A method includes forming an ion implant layer in a fin defined on a semiconductor substrate. The semiconductor substrate is annealed to convert the ion implant layer to a dielectric layer.
Globalfoundries Inc.


03/10/16
20160071978 

Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer


A semiconductor device includes drain and source regions positioned in an active region of a transistor and a channel region positioned laterally between the drain and source regions that includes a semiconductor base material and a threshold voltage adjusting semiconductor material positioned on the semiconductor base material. A gate electrode structure is positioned on the threshold voltage adjusting semiconductor material, and a strain-inducing semiconductor alloy including a first semiconductor material and a second semiconductor material positioned above the first semiconductor material is embedded in the semiconductor base material of the active region.
Globalfoundries Inc.


03/10/16
20160071968 

Low external resistance channels in iii-v semiconductor devices


The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a replacement channel composed of a iii-v compound semiconductor material in a doped layer of a iii-v compound semiconductor substrate. The replacement channel may be formed by removing a portion of the doped layer located directly below a dummy gate stack that has been removed.
International Business Machines Corporation


03/10/16
20160071967 

High-electron-mobility transistor having a buried field plate


A high-electron-mobility field effect transistor is formed with a buffer region having a stepped lateral profile, the stepped lateral profile having first, second and third cross-sections of the buffer region, the first cross-section being thicker than the third cross-section and including a buried field plate, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections. A barrier region is formed along the stepped lateral profile.
Infineon Technologies Austria Ag


03/10/16
20160071961 

Method for fabricating thin film transistor and apparatus thereof


A method for fabricating a thin film transistor (tft) is provided, and the method includes following steps. A gate and an insulation layer are sequentially formed on a substrate.
Au Optronics Corporation


03/10/16
20160071947 

Method including a replacement of a dummy gate structure with a gate structure including a ferroelectric material


A method disclosed herein includes providing a substrate including a semiconductor material. A first area of the substrate is recessed relative to a second area of the substrate, and an active region of a first transistor is formed in the recessed area.
Globalfoundries Inc.


03/10/16
20160071912 

Drive circuit, organic light-emitting diode display, and methods for fabricating the same


A drive circuit, an organic light-emitting diode display, and methods for fabricating the same are provided. The drive circuit includes: a driving transistor, including a first gate, a first semiconductor layer disposed above the first gate, an etch stopping layer disposed on the first semiconductor layer, and a first source and a first drain which are disposed on the two sides of the first semiconductor layer, the first semiconductor layer being made of oxide semiconductor material; and a switching transistor, including a second gate, a second semiconductor layer disposed above the second gate, and a second source and a second drain which are disposed on two sides of the second semiconductor layer, the second semiconductor layer being made of oxide semiconductor material.
Tianma Micro-electronics Co., Ltd.


03/10/16
20160071886 

Highly conformal extension doping in advanced multi-gate devices


A semiconductor device includes a semiconductor material positioned above a substrate and a gate structure positioned above a surface of the semiconductor material, the gate structure covering a non-planar surface portion of the surface. A sidewall spacer is positioned adjacent to the gate structure and includes first dopants having one of an n-type and a p-type conductivity, wherein the sidewall spacer covers an entire sidewall surface of the gate structure and partially covers the surface of the semiconductor material.

03/10/16
20160071819 

Method of producing a semiconductor device and a semiconductor device


A method of producing a semiconductor device is provided. The method includes: providing a semiconductor wafer, the wafer including an upper layer of a semiconductor material, an inner etch stop layer and a lower layer; forming a plurality of functional areas in the upper layer; performing a selective first etch process on the upper layer so as to separate the plurality of functional areas from each other by trenches etched through the upper layer, the first etch process being substantially stopped by the inner etch stop layer; and removing the lower layer by a second etch process, the second etch process being substantially stopped by the inner etch stop layer..
Infineon Technologies Austria Ag


03/10/16
20160071772 

Method for the formation of a finfet device with epitaxially grown source-drain regions having a reduced leakage path


Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either soi or bulk type). Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers.
Stmicroelectronics (crolles 2) Sas


03/10/16
20160071624 

Organic semiconductor composition, organic thin-film transistor, electronic paper, and display device


The present invention provides an organic semiconductor composition, which improves the insulation reliability of an organic thin-film transistor without greatly reducing the mobility of the organic thin-film transistor, an organic thin-film transistor which is formed by using the organic semiconductor composition, and electronic paper and a display device which use the organic thin-film transistor. The organic semiconductor composition of the present invention contains an organic semiconductor material and an f-containing migration inhibitor selected from the group consisting of a compound represented by any of formulae (1) to (8), a polymer compound (x) containing a repeating unit represented by formula (a), and a polymer compound (y) containing a repeating unit represented by formula (b) and a repeating unit represented by formula (c)..
Fujifilm Corporation


03/10/16
20160070060 

Method for the formation of nano-scale on-chip optical waveguide structures


A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material.
Stmicroelectronics, Inc.


03/10/16
20160069740 

Radiation detector having a bandgap engineered absorber


A radiation detector is provided that includes a photodiode having a radiation absorber with a graded multilayer structure. Each layer of the absorber is formed from a semiconductor material, such as hgcdte.
Drs Network & Imaging Systems, Inc.


03/10/16
20160068750 

Nanocrystals including a group iiia element and a group va element, method, composition, device and other products


A nanocrystal comprising a semiconductor material comprising one or more elements of group iiia of the periodic table of elements and one or more elements of group va of the periodic table of elements, wherein the nanocrystal is capable of emitting light having a photoluminescence quantum efficiency of at least about 30% upon excitation. Also disclosed is a nanocrystal including a core comprising a first semiconductor material comprising one or more elements of group iiia of the periodic table of elements and one or more elements of group va of the periodic table of elements, and a shell disposed over at least a portion of the core, the shell comprising a second semiconductor material, wherein the nanocrystal is capable of emitting light having a photoluminescence quantum efficiency of at least about 30% upon excitation.
Qd Vision, Inc.


03/03/16
20160065118 

Multi-functional photovoltaic skylight and/or methods of making the same


Certain examples relate to improved solar photovoltaic systems, and/or methods of making the same. Certain improved building-integrated photovoltaic systems may include concentrated photovoltaic skylights having a cylindrical lens array.
Guardian Industries Corp.


03/03/16
20160064674 

Organic semiconductor comosition, organic thin-film transistor, electronic paper, and display device


An object of the present invention is to provide an organic semiconductor composition, which improves the insulation reliability of an organic thin-film transistor without greatly reducing the mobility of the organic thin-film transistor, an organic thin-film transistor which is prepared by using the organic semiconductor composition, and electronic paper and a display device which use the organic thin-film transistor. The organic semiconductor composition of the present invention contains an organic semiconductor material (a) and a polymer compound (b) containing a repeating unit represented by the following formula (b)..
Fujifilm Corporation


03/03/16
20160064609 

Nanostructure semiconductor light emitting device


A nanostructure semiconductor light emitting device may include a base layer having first and second regions and formed of a first conductivity-type semiconductor material; a plurality of light emitting nanostructures disposed on the base layer, each of which including a nanocore formed of a first conductivity-type semiconductor material, and an active layer and a second conductivity-type semiconductor layer sequentially disposed on the nanocore; a contact electrode disposed on the light emitting nanostructures to be connected to the second conductivity-type semiconductor layer; a first electrode connected to the base layer; and a second electrode covering a portion of the contact electrode disposed on at least one of light emitting nanostructures disposed in the second region among the plurality of light emitting nanostructures, wherein light emitting nanostructures disposed in the second region and light emitting nanostructures disposed in the first region among the plurality of light emitting nanostructures have different shapes.. .
Samsung Electronics Co., Ltd.


03/03/16
20160064607 

Nanostructure semiconductor light emitting device


A nanostructure semiconductor light emitting device may include: a base layer formed of a first conductivity-type semiconductor material; an insulating layer disposed on the base layer and having a plurality of openings exposing portions of the base layer; a plurality of nanocores disposed on the exposed portions of the base layer and formed of a first conductivity-type semiconductor material, each of which including a tip portion having a crystal plane different from that of a side surface thereof; a first high resistance layer disposed on the tip portion of the nanocore and formed of an oxide containing an element which is the same as at least one of elements constituting the nanocore; an active layer disposed on the first high resistance layer and the side surface of the nanocore; and a second conductivity-type semiconductor layer disposed on the active layer.. .
Samsung Electronics Co., Ltd.


03/03/16
20160064590 

Fabrication of solar cells with electrically conductive polyimide adhesive


The present disclosure provides a method of manufacturing a solar cell including: providing a first substrate and a second substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell including a top subcell and a bottom subcell; forming a back metal contact over the bottom subcell; applying a conductive polyimide adhesive to the second substrate; attaching the second substrate on top of the back metal contact; and removing the first substrate to expose the surface of the top subcell.. .
Solaero Technologies Corp.


03/03/16
20160064566 

Method of making a semiconductor device using spacers for source/drain confinement


A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto.
Stmicroelectronics, Inc.


03/03/16
20160064539 

Semiconductor structure and recess formation etch technique


A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process.
Massachusetts Institute Of Technology


03/03/16
20160064526 

Methods of forming alternative channel materials on finfet semiconductor devices


One illustrative method disclosed herein includes forming a recessed fin structure and a replacement fin cavity in a layer of insulating material above the recessed fin structure, forming at least first and second individual layers of epi semiconductor material in the replacement fin cavity, wherein each of the first and second layers have different concentrations of germanium, performing an anneal process on the first and second layers so as to form a substantially homogeneous sige replacement fin in the fin cavity, and forming a gate structure around at least a portion of the replacement fin.. .
Globalfoundries Inc.


03/03/16
20160064492 

Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication


A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening.. .
Taiwan Semiconductor Manufacturing Co., Ltd.


03/03/16
20160064465 

Thin film transistor substrate and display using the same


The present invention relates to a thin film transistor substrate having two different types of semiconductor materials on the same substrate, and a display using the same. A disclosed display may include a substrate, a first thin film transistor having a polycrystalline semiconductor material on the substrate and a second thin film transistor having an oxide semiconductor material on the substrate..
Lg Display Co., Ltd.


03/03/16
20160064381 

Fin-like field effect transistor (finfet) device and manufacturing same


A finfet device and method for fabricating a finfet device is disclosed. An exemplary device includes a fin structure formed over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


03/03/16
20160064284 

Method for fabricating a semiconductor structure


Method for fabricating a semiconductor structure. The method includes: providing a crystalline silicon substrate; defining an opening in a dielectric layer on the crystalline silicon substrate, the opening having sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; providing a confinement structure above the dielectric layer, thereby forming a confinement region between the confinement structure and the dielectric layer; and growing a crystalline compound semiconductor material in the confinement region thereby at least partially filling the confinement region.
International Business Machines Corporation


03/03/16
20160063924 

Thin film transistor substrate and display using the same


The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate and a display using the same. A disclosed display device may include a substrate, a first thin film transistor including a first semiconductor layer having a polycrystalline semiconductor material on the substrate, and a second thin film transistor including a second semiconductor layer including an oxide semiconductor material on the substrate.
Lg Display Co., Ltd.


03/03/16
20160060105 

Mems device and manufacturing a mems device


A method for producing a mems device comprises forming a semiconductor layer stack, the semiconductor layer stack comprising at least a first monocrystalline semiconductor layer, a second monocrystalline semiconductor layer and a third monocrystalline semiconductor layer, the second monocrystalline semiconductor layer formed between the first and third monocrystalline semiconductor layers. A semiconductor material of the second monocrystalline semiconductor layer is different from semiconductor materials of the first and third monocrystalline semiconductor layers.
Infineon Technologies Ag


02/25/16
20160056611 

Semiconductor laser resonator and semiconductor laser device including the same


A semiconductor laser resonator configured to generate a laser beam includes a gain medium layer including a semiconductor material and comprising: a central portion; and protrusions periodically arranged around the central portion, one of the protrusions being configured to confine the laser beam as a standing wave in the one protrusion.. .
Samsung Electronics Co., Ltd.


02/25/16
20160056390 

Aromatic heterocyclic compound, manufacturing method thereof, organic semiconductor material, and organic semiconductor device


Provided are an organic semiconductor material having a high charge mobility, oxidation stability, and solvent solubility, an organic semiconductor device using the same, and a novel aromatic heterocyclic compound to be used for the same and a production method therefor. The aromatic heterocyclic compound is represented by the following general formula (1), has two heteroatoms, and has a structure in which six rings are fused.
Nippon Steel & Sumikin Chemical Co., Ltd.


02/25/16
20160056336 

Semiconductor light-emitting device


A semiconductor light-emitting device includes a substrate, a first reflective layer disposed on the substrate and including first openings, a first conductivity-type semiconductor layer grown in and extending from the first openings and connected on the first reflective layer, a second reflective layer disposed on the first conductivity-type semiconductor layer and including second openings having lower surfaces disposed to be spaced apart from upper surfaces of the first openings, and a plurality of light-emitting nanostructures including nanocores extending from the second openings and formed of a first conductivity-type semiconductor material, and active layers and second conductivity-type semiconductor layers sequentially disposed on the nanocores.. .
Samsung Electronics Co., Ltd.


02/25/16
20160056331 

Nanostructure semiconductor light emitting device


A nanostructure semiconductor light emitting device includes: a base layer formed of a first-conductivity type nitride semiconductor material; and a plurality of light emitting nanostructures disposed on the base layer to be spaced apart from each other, wherein each of the plurality of light emitting nanostructures includes: a nanocore formed of a first conductivity-type nitride semiconductor material, an active layer disposed on a surface of the nanocore and including a quantum well which is divided into first and second regions having different indium (in) composition ratios in a thickness direction thereof; and a second conductivity-type semiconductor layer disposed on the active layer, and an in composition ratio in the first region is higher than an in composition ratio in the second region.. .

02/25/16
20160056298 

Semiconductor device


A semiconductor device with significantly low off-state current is provided. An oxide semiconductor material in which holes have a larger effective mass than electrons is used.
Semiconductor Energy Laboratory Co., Ltd.


02/25/16
20160056297 

Metal oxide tft with improved source/drain contacts and reliability


A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level.

02/25/16
20160056290 

Metal-insensitive epitaxy formation


The present disclosure provides a method forming a field effect transistor (fet) in accordance with some embodiments. The method includes performing an etching process to a semiconductor substrate, thereby forming recesses in source and drain (s/d) regions of the semiconductor substrate; forming a passivation material layer of a first semiconductor in the recesses; and epitaxially growing a second semiconductor material, thereby forming s/d features in the recesses, wherein the s/d features are separated from the semiconductor substrate by the passivation material layer..
Taiwan Semiconductor Manufacturing Company, Ltd.


02/25/16
20160056277 

Structure and method and finfet device


The present disclosure provides an embodiment of a fin-like field-effect transistor (finfet) device. The device includes the device includes a strain-relaxed buffer (srb) stack over a substrate, a first fin structure disposed over the srb stack and a liner layer extending along the portion of the second srb layer and the first semiconductor material layer of the first fin structure..
Taiwan Semiconductor Manufacturing Company, Ltd.


02/25/16
20160056270 

Structure and defect passivation to reduce junction leakage for finfet device


The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (sti) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


02/25/16
20160056253 

Integrated circuits with diffusion barrier layers and processes for preparing integrated circuits including diffusion barrier layers


Integrated circuits with a diffusion barrier layers, and processes for preparing integrated circuits including diffusion barrier layers are provided herein. An exemplary integrated circuit includes a semiconductor substrate comprising a semiconductor material, a compound gate dielectric overlying the semiconductor substrate, and a gate electrode overlying the compound gate dielectric.
Globalfoundries, Inc.


02/25/16
20160056180 

Heterogeneous semiconductor material integration techniques


Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface.
Intel Corporation


02/25/16
20160056175 

Circuit structures, memory circuitry, and methods


A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material.
Micron Technology, Inc.


02/25/16
20160056069 

Methods of forming memory arrays


Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level.
Micron Technology, Inc.




Semiconductor Material topics: Semiconductor, Semiconductor Material, Semiconductor Device, Transistors, Surfactant, Electric Conversion, Transparent Conductive Oxide, Semiconductor Substrate, Heating Devices, Semiconductor Devices, Organic Electroluminescence, Buffer Layer, Integrated Circuit, Crystallin, Electronic Device

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