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Semiconductor Material patents



      
           
This page is updated frequently with new Semiconductor Material-related patent applications. Subscribe to the Semiconductor Material RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Material RSS RSS


Methods of forming semiconductor structures including bodies of semiconductor material

Method of forming a semiconductor structure including a vertical nanowire

Methods and arrangements relating to semiconductor packages including multi-memory dies

Date/App# patent app List of recent Semiconductor Material-related patents
07/24/14
20140206261
 Method for polishing a semiconductor wafer patent thumbnailMethod for polishing a semiconductor wafer
A method for polishing at least one wafer composed of semiconductor material that has a front side and the rear side includes performing at least one first polishing step including simultaneously polishing both front and rear sides of the at least one wafer at a process temperature between an upper polishing plate and a lower polishing plate. Each of the upper polishing and lower polishing plates is covered with a polishing pad having an inner edge and an outer edge, a hardness of at least 80° shore a, a compressibility of less than 2.5%, and respective upper and lower surfaces that come into contact with the wafer being polished.
07/24/14
20140206175
 Methods of forming semiconductor structures including bodies of semiconductor material patent thumbnailMethods of forming semiconductor structures including bodies of semiconductor material
Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material.
07/24/14
20140206157
 Method of forming a semiconductor structure including a vertical nanowire patent thumbnailMethod of forming a semiconductor structure including a vertical nanowire
A method comprises providing a semiconductor structure comprising a substrate and a nanowire above the substrate. The nanowire comprises a first semiconductor material and extends in a vertical direction of the substrate.
07/24/14
20140206141
 Methods and arrangements relating to semiconductor packages including multi-memory dies patent thumbnailMethods and arrangements relating to semiconductor packages including multi-memory dies
Embodiments provide a method comprising providing a multi-memory die that comprises multiple individual memory dies. Each of the individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies.
07/24/14
20140203452
 Active chip on carrier or laminated chip having microelectronic element embedded therein patent thumbnailActive chip on carrier or laminated chip having microelectronic element embedded therein
A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity.
07/24/14
20140203410
 Die edge sealing structures and related fabrication methods patent thumbnailDie edge sealing structures and related fabrication methods
Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region.
07/24/14
20140203409
 Integrated circuit structures, semiconductor structures, and semiconductor die patent thumbnailIntegrated circuit structures, semiconductor structures, and semiconductor die
Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level.
07/24/14
20140203371
 Finfet device formation patent thumbnailFinfet device formation
A method includes patterning a fin on a semiconductor substrate, depositing a local trench isolation (lti) layer on the semiconductor substrate, patterning a gate stack over a channel region of the fin and over a portion of the lti layer, depositing a first capping layer over exposed portions of the lti layer, performing an etching process to remove oxide material from exposed portions of the fin, and epitaxially growing a semiconductor material from exposed portions of the fin to define active regions.. .
07/24/14
20140203349
 Method of producing a high-voltage-resistant semiconductor component having vertically conductive semiconductor body areas and a trench structure patent thumbnailMethod of producing a high-voltage-resistant semiconductor component having vertically conductive semiconductor body areas and a trench structure
A high-voltage-resistant semiconductor component (1) has vertically conductive semiconductor areas (17) and a trench structure (5). These vertically conductive semiconductor areas are formed from semiconductor body areas (10) of a first conductivity type and are surrounded by a trench structure (5) on the upper face (6) of the semiconductor component.
07/24/14
20140203338
 Finfet device with epitaxial structure patent thumbnailFinfet device with epitaxial structure
A finfet device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure.
07/24/14
20140203334
Method for fabricating a finfet device including a stem region of a fin element
A method includes providing a substrate having a fin extending from a first (e.g., top) surface of the substrate. The fin has first region (a stem region) and a second region (an active region) each having a different composition.
07/24/14
20140203290
Wire-last integration method and structure for iii-v nanowire devices
In one aspect, a method of fabricating a nanowire fet device includes the following steps. A layer of iii-v semiconductor material is formed on an soi layer of an soi wafer.
07/24/14
20140203263
Switchable memory diodes based on ferroelectric/conuugated polymer heterostructures and/or their composites
An embodiment of the present memory cell a first layer of a chosen conductivity type, and a second layer which includes ferroelectric semiconductor material of the opposite conductivity type, the layers forming a pn junction. The first layer may be a conjugated semiconductor polymer, or may also be of ferroelectric semiconductor material.
07/24/14
20140203238
Wire-last integration method and structure for iii-v nanowire devices
In one aspect, a method of fabricating a nanowire fet device includes the following steps. A layer of iii-v semiconductor material is formed on an soi layer of an soi wafer.
07/24/14
20140203237
Self-rectified device, method for manufacturing the same, and applications of the same
A self-rectified device is provided, comprising a bottom electrode, a patterned dielectric layer with a contact hole formed on the bottom electrode, a memory formed at the bottom electrode and substantially aligned with the contact hole, and a top electrode formed on the bottom electrode and filling into the contact hole to contact with the memory, wherein the top electrode comprises a n+ type semiconductor material or a p+ type semiconductor material, and the memory and the top electrode produce a self-rectified property.. .
07/17/14
20140199807
Thin film transistors formed by organic semiconductors using a hybrid patterning regime
The present disclosure describes a process strategy for forming bottom gate/bottom contact organic tfts in cmos technology by using a hybrid deposition/patterning regime. To this end, gate electrodes, gate dielectric materials and drain and source electrodes are formed on the basis of lithography processes, while the organic semiconductor materials are provided as the last layers by using a spatially selective printing process..
07/17/14
20140199539
Composite plated film and laminated film
It is provided a steel with composite plating film providing rust prevention over a long time period and a method of manufacturing thereof. A composite plating film 24 is formed on a metal material 21.
07/17/14
20140197862
Methods for characterizing shallow semiconductor junctions
The disclosed technology generally relates to methods of characterizing semiconductor materials, and more particularly to methods of characterizing shallow semiconductor junctions. In one aspect, the method of characterizing shallow semiconductor junctions comprises providing a substrate comprising a shallow junction formed at a first main surface, where the shallow junction is formed substantially parallel to the first main surface.
07/17/14
20140197855
Multifunctional nanoscopy for imaging cells
Disclosed herein is an apparatus comprising a metal shunt and a semiconductor material in electrical contact with the metal shunt, thereby defining a semiconductor/metal interface for passing a flow of current between the semiconductor material and the metal shunt in response to an application of an electrical bias to the apparatus, wherein the semiconductor material and the metal shunt lie in different planes that are substantially parallel planes, the semiconductor/metal interface thereby being parallel to planes in which the semiconductor material and the metal shunt lie, and wherein, when under the electrical bias, the semiconductor/metal interface is configured to exhibit a change in resistance thereof in response to a perturbation. Such an apparatus can be used as a sensor and deployed as an array of sensors..
07/17/14
20140197470
Methods for forming etch stop layers, semiconductor devices having the same, and methods for fabricating semiconductor devices
A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration.
07/17/14
20140197457
Finfet device and method of fabricating same
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having isolation regions, a gate region, source and drain regions separated by the gate region, a first fin structure in a gate region.
07/17/14
20140197456
Semiconductor device and fabricating the same
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (s/d) regions separated by the gate region and a first fin structure in a gate region in the n-fet region.
07/17/14
20140197435
Optoelectronic semiconductor chip
An optoelectronic semiconductor chip includes a semiconductor body of semiconductor material, a p-contact layer and an n-contact layer. The semiconductor body includes an active layer intended for generating radiation.
07/17/14
20140197419
Techniques for forming optoelectronic devices
Embodiments relate to use of a particle accelerator beam to form thin films of material from a bulk substrate. In particular embodiments, a bulk substrate (e.g.
07/17/14
20140197410
Semiconductor structure and method for manufacturing the same
The present invention provides a method for manufacturing a semiconductor structure. The method comprises: providing an soi substrate and forming a gate structure on said soi substrate; etching a soi layer and a box layer of the soi substrate on both sides of the gate structure to form a trench exposing the box layer, said trench partially entering into the box layer; forming a stressed layer that fills up a part of said trench; forming a semiconductor layer covering the stressed layer in the trench.
07/17/14
20140197407
Semiconductor device and method for manufacturing the same
Objects are to provide a semiconductor device for high power application in which a novel semiconductor material having high productivity is used and to provide a semiconductor device having a novel structure in which a novel semiconductor material is used. The present invention is a vertical transistor and a vertical diode each of which has a stacked body of an oxide semiconductor in which a first oxide semiconductor film having crystallinity and a second oxide semiconductor film having crystallinity are stacked.
07/17/14
20140196787
Organic photovoltaic cell, organic semiconductor polymer and composition for organic semiconductor material used therefor
Wherein x represents s, nr2, o, se or te; y represents nr2, o, te, so, so2 or co; and r1 and r2 represent a hydrogen atom or a substituent.. .
07/17/14
20140196775
Synthesis method of cu(in,ga)se2 nanorod or nanowire and materials including the same
A method of fabricating cigs nanorod or nanowire according to one exemplary embodiment of the present disclosure comprises a deposition preparation step of placing a raw material including copper, indium, gallium and selenium and a substrate, and a deposition step of growing cigs nanorod or nanowire on the substrate by maintaining an internal temperature of a reactor, in which carrier gas flows at a constant flow rate, at a temperature in the range of 850 to 1000° c. According to the method, cu(in,ga)se2 nanorod or nanowire as a direct transition type semiconductor material having substantially uniform composition, high crystallinity and high light absorption ratio can be fabricated..
07/17/14
20140196774
Multi-junction iii-v solar cell
A multi junction solar cell structure includes a top photovoltaic cell including iii-v semiconductor materials and a silicon-based bottom photovoltaic cell. A thin, germanium-rich silicon germanium buffer layer is provided between the top and bottom cells.
07/17/14
20140196773
Multi-junction iii-v solar cell
A multi junction solar cell structure includes a top photovoltaic cell including iii-v semiconductor materials and a silicon-based bottom photovoltaic cell. A thin, germanium-rich silicon germanium buffer layer is provided between the top and bottom cells.
07/10/14
20140191779
Crosstalk suppression in wireless testing of semiconductor devices
An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.. .
07/10/14
20140191354
Laser system with polarized oblique incidence angle and associated methods
Novel laser processed semiconductor materials, systems, and methods associated with the manufacture and use of such materials are provided. In one aspect, for example, a method of processing a semiconductor material can include providing a semiconductor material and irradiating a target region of the semiconductor material with a beam of laser radiation to form a laser treated region.
07/10/14
20140191340
Transistors, semiconductor constructions, and methods of forming semiconductor constructions
Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion.
07/10/14
20140191332
Pfet devices with different structures and performance characteristics
Disclosed herein is a device that includes a first pfet transistor formed in and above a first active region of a semiconducting substrate, a second pfet transistor formed in and above a second active region of the semiconducting substrate, wherein at least one of a thickness of the first and second channel semiconductor materials or a concentration of germanium in the first and second channel semiconductor materials are different.. .
07/10/14
20140191297
Strained finfet with an electrically isolated channel
A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities.
07/10/14
20140191285
Semiconductor device having epitaxial structures
A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant.
07/10/14
20140191228
Thin film transistor, method of fabricating the same, and display apparatus having the same
A thin film transistor includes a semiconductor layer disposed on a base substrate and including an oxide semiconductor material, a source electrode and a drain electrode, which respectively extend from opposing ends of the semiconductor layer, a plurality of low carrier concentration areas respectively disposed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer, a gate insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating layer.. .
07/10/14
20140191178
Method of fabricating a vertical mos transistor
The disclosure relates to a method of fabricating a vertical mos transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.. .
07/10/14
20140190837
Electrochemical liquid-liquid-solid deposition processes for production of group iv semiconductor materials
An electrochemical liquid-liquid-solid (lls) process that produces unlimited amounts of crystalline semiconductor, such as ge or si, from aqueous or polar solutions with tunable nanostructured shapes without any physical or chemical templating agent is presented. Dissolution into, saturation within, and precipitation of the semiconductor from a liquid electrode (e.g., hg pool) or near an electrode comprising metallic nanoparticles (e.g., in nanoparticles) yields a polycrystalline semiconductor material, as deposited.
07/10/14
20140190566
Organic photoelectric conversion element and organic solar cell using the same
An organic photoelectric conversion element having: a transparent first electrode; a power generation layer having a p-type organic semiconductor material and an n-type organic semiconductor material; and a second electrode, on a transparent substrate, in which the power generation layer is a bulk heterojunction power generation layer including the p-type organic semiconductor material and the n-type organic semiconductor material, and additionally includes a compound represented by either the following general formula (i) or general formula (ii).. .
07/10/14
20140190401
Method, system, and apparatus for doping and for multi-chamber high-throughput solid-phase epitaxy deposition process
A doping and multi-chamber method and apparatus for the growth of material, directed toward solid phase epitaxy (spe) process, is disclosed. Different variations and features of this method and process are examined.
07/03/14
20140187797
Leaving substituent-containing compound, organic semiconductor material, organic semiconductor film containing the material, organic electronic device containing the film, method for producing film-like product, pi-electron conjugated compound and method for producing the pi-electron conjugated compound
Where a pair of x1 and x2 or a pair of y1 and y2 each represent a hydrogen atom; the other pair each represent a group selected from the group consisting of a halogen atom and a substituted or unsubstituted acyloxy group having one or more carbon atoms; a pair of the acyloxy groups represented by the pair of x1 and x2 or the pair of y1 and y2 may be identical or different, or may be bonded together to form a ring; r1 to r4 each represent a hydrogen atom or a substituent; and q1 and q2 each represent a hydrogen atom, a halogen atom or a monovalent organic group, and may be bonded together to form a ring.. .
07/03/14
20140187046
Method for forming spacers for a transitor gate
At least one step of removing the modified layer of nitride by means of a selective etching of the modified layer of nitride vis-à-vis said semiconductor material and vis-à-vis the non-modified layer of nitride. .
07/03/14
20140187007
Mosfet including asymmetric source and drain regions
At least one drain-side surfaces of a field effect transistor (fet) structure, which can be a structure for a planar fet or a fin fet, is structurally damaged by an angled ion implantation of inert or electrically active dopants, while at least one source-side surface of the transistor is protected from implantation by a gate stack and a gate spacer. Epitaxial growth of a semiconductor material is retarded on the at least one structurally damaged drain-side surface, while epitaxial growth proceeds without retardation on the at least one source-side surface.
07/03/14
20140187002
Method of forming a semiconductor structure
A method of forming a semiconductor structure having a substrate is disclosed. The semiconductor structure includes a first layer formed in contact with the substrate.
07/03/14
20140185346
Hybrid power devices and switching circuits for high power load sourcing applications
A hybrid switching circuit includes first and second switching devices containing first and second unequal bandgap semiconductor materials. These switching devices, which support parallel conduction in response to first and second control signals, are three or more terminal switching devices of different type.
07/03/14
20140183761
Semiconductor device and method of forming embedded wafer level chip scale packages
A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material.
07/03/14
20140183718
Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material.
07/03/14
20140183700
High quality devices growth on pixelated patterned templates
A method of producing a template material for growing semiconductor materials and/or devices, comprises the steps of: (a) providing a substrate with a dielectric layer on the substrate; and (b) forming a pixelated pattern on the dielectric layer, the pattern comprising a plurality of discrete groups of structures.. .
07/03/14
20140183662
Deep trench isolation with tank contact grounding
An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type.
07/03/14
20140183636
Method for manufacturing semiconductor substrate, substrate for forming semiconductor substrate, stacked substrate, semiconductor substrate, and electronic device
Film thickness variations are prevented in a plurality of single crystal semiconductor films separated at a fragile layer reliably and transferred to a base substrate. A method for manufacturing a soi substrate (33) in which a plurality of soi layers (15) are disposed on a base substrate (30) includes the steps of bonding a plurality of soi wafers (10), in which an oxide film (14), a soi layer (15), a box layer (12), and a si support substrate (13) having a fragile layer (17) formed by ion irradiation in the inside and being made from a single crystal semiconductor material are stacked sequentially, to a base substrate (30) in such a way that the oxide film (14) is located on the side close to the base substrate (30), applying heat to the plurality of soi wafers (10) to separate part of the si support substrate (13) at the fragile layer (17) and transfer the oxide film (14), the soi layer (15), the box layer (12), and a single crystal si layer (18) which is part of the si support substrate (13) to the base substrate (30), and subjecting the base substrate (30) to an etch back treatment to expose the box layer (12) by etching the transferred single crystal si layer (18)..
07/03/14
20140183601
Method for transferring a layer of a semiconductor and substrate comprising a confinement structure
A method for transferring a layer of semiconductor by providing a donor substrate that includes a useful layer of a semiconductor material, a confinement structure that includes a confinement layer of a semiconductor material having a chemical composition that is different than that of the useful layer, and two protective layers of semiconductor material that is distinct from the confinement layer with the protective layers being arranged on both sides of the confinement layer; introducing ions into the donor substrate, bonding the donor substrate to a receiver substrate, subjecting the donor and receiver substrates to a heat treatment that provides an increase in temperature during which the confinement layer attracts the ions in order to concentrate them in the confinement layer, and detaching the donor substrate from the receiver substrate by breaking the confinement layer.. .
07/03/14
20140183600
Novel fin structure of finfet
A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa.
07/03/14
20140183597
Metal alloy with an abrupt interface to iii-v semiconductor
Semiconductor structures having a first layer including an n-type iii-v semiconductor material and a second layer including an m(inp)(ingaas) alloy, wherein m is selected from ni, pt, pd, co, ti, zr, y, mo, ru, ir, sb, in, dy, tb, er, yb, and te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers.
07/03/14
20140183594
Radiation-emitting semiconductor chip having integrated esd protection
A radiation-emitting semiconductor chip having a semiconductor layer sequence based on a nitride compound semiconductor material and having a pn junction includes a first protective layer having deliberately introduced crystal defects, a second protective layer having a higher doping than the first protective layer, wherein the first protective layer protects the semiconductor chip against electrostatic discharge pulses, an active zone that generates radiation disposed downstream of the first protective layer in a growth direction, wherein during operation of the semiconductor chip, a breakdown behavior of the semiconductor layer sequence in a reverse direction in regions having crystal defects differs from regions without crystal defects, and wherein in the event of electrostatic discharge pulses, electrical charge is dissipated in a homogeneously distributed manner via the regions having crystal defects.. .
07/03/14
20140183507
Organic field-effect transistor
An organic transistor including at least one lower substrate made of plastic material, two electrodes, respectively a source electrode and a drain electrode, deposited on the plastic substrate, a semiconductor layer made of an organic semiconductor material and deposited on the electrodes and the plastic substrate, a dielectric layer deposited on the semiconductor layer, and a gate electrode formed on said dielectric layer. It further includes a porous layer extending between the plastic substrate and the semiconductor layer, said porous layer extending at least between the source and drain electrodes, to decrease the dielectric constant of the surface of said plastic substrate..
07/03/14
20140183457
Transistor with organic semiconductor interface
A method is provided for preparing an interface surface for the deposition of an organic semiconductor material, in the fabrication of an organic thin film transistor (otft). A substrate is provided and a gate electrode is formed overlying the substrate.
07/03/14
20140183451
Field effect transistor with channel core modified to reduce leakage current and method of fabrication
A semiconductor device includes a channel structure formed on a substrate, the channel structure being formed of a semiconductor material. A gate structure covers at least a portion of the surface of the channel structure and is formed of a film of insulation material and a gate electrode.
07/03/14
20140183442
Engineered substrate assemblies with epitaxial templates and related systems, methods, and devices
Engineered substrates having epitaxial templates for forming epitaxial semiconductor materials and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming a first semiconductor material at a front surface of a donor substrate.
06/26/14
20140179512
Photocatalyst for the production of hydrogen
A method and composition for making photocatalytic capped colloidal nanocrystals include semiconductor nanocrystals and inorganic capping agents as photocatalysts. The photocatalytic capped colloidal nanocrystals may be deposited on a substrate and treated to form a photoactive material that may be used in a plurality of photocatalytic energy conversion applications such as water splitting.
06/26/14
20140179077
Method of forming semiconductor device including silicide layers
A method includes forming a gate structure on a semiconductor material region, wherein the gate structure includes spacer elements abutting a gate electrode layer. The gate electrode layer is etched to provide a recess.
06/26/14
20140175556
Semiconductor device having v-shaped region
Among other things, a semiconductor device or transistor and a method for forming the semiconductor device are provided for herein. The semiconductor device comprises one or more v-shaped recesses in which stressed monocrystalline semiconductor material, such as silicon germanium, is grown, to form at least one of a source or a drain of the semiconductor device.
06/26/14
20140175550
Device structures compatible with fin-type field-effect transistor technologies
Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material.
06/26/14
20140175541
Manufacturing of electronic devices in a wafer of semiconductor material having trenches with different directions
A method for integrating a set of electronic devices on a wafer (100; 200a; 200b) of semiconductor material having a main surface includes forming a plurality of trenches extending into the wafer from the main surface. At least one layer of electrically insulating material is formed within each trench.
06/26/14
20140175513
Structure and method for integrated devices on different substartes with interfacial engineering
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first semiconductor material and a first reactivity; and a low reactivity capping layer of disposed on the semiconductor substrate, wherein the low reactivity capping layer includes a second semiconductor material and a second reactivity less than the first reactivity, the low reactivity capping layer includes silicon germanium si1−xgex and x is less than about 30%..
06/26/14
20140175441
Thin film transistor array panel and manufacturing method thereof
A thin film transistor array panel includes a substrate, an insulation layer, a first semiconductor, and a second semiconductor. The insulation layer is disposed on the substrate and includes a stepped portion.
06/26/14
20140175416
Leaving substituent-containing compound, organic semiconductor material, organic semiconductor film containing the material, organic electronic device containing the film, method for producing film-like product, pi-electron conjugated compound and method for producing the pi-electron conjugated compound
Where a pair of x1 and x2 or a pair of y1 and y2 each represent a hydrogen atom; the other pair each represent a group selected from the group consisting of a halogen atom and a substituted or unsubstituted acyloxy group having one or more carbon atoms; a pair of the acyloxy groups represented by the pair of x1 and x2 or the pair of y1 and y2 may be identical or different, or may be bonded together to form a ring; r1 to r4 each represent a hydrogen atom or a substituent; and q1 and q2 each represent a hydrogen atom, a halogen atom or a monovalent organic group, and may be bonded together to form a ring.. .
06/26/14
20140175372
Recessed contact to semiconductor nanowires
A semiconductor nanowire device includes at least one semiconductor nanowire having a bottom surface and a top surface, an insulating material which surrounds the semiconductor nanowire, and an electrode ohmically contacting the top surface of the semiconductor nanowire. A contact of the electrode to the semiconductor material of the semiconductor nanowire is dominated by the contact to the top surface of the semiconductor nanowire..
06/26/14
20140174349
Apparatus and methods of mixing and depositing thin film photovoltaic compositions
Improved methods and apparatus for forming thin-film layers of semiconductor material absorber layers on a substrate web. According to the present teachings, a semiconductor layer may be formed in a multi-zone process whereby various layers are deposited sequentially onto a moving substrate web.
06/19/14
20140171822
Wafer-scale package including power source
A medical device includes a first substrate, a second substrate, a control module, and an energy storage device. The first substrate includes at least one of a first semiconductor material and a first insulating material.
06/19/14
20140170834
Method for manufacturing a hybrid soi/bulk semiconductor wafer
A method for manufacturing a hybrid soi/bulk substrate, including the steps of starting from an soi wafer comprising a single-crystal semiconductor layer called soi layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the soi layer at least one masking layer and forming openings crossing the masking layer, the soi layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.. .
06/19/14
20140170822
Cross-point diode arrays and methods of manufacturing cross-point diode arrays
Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post.
06/19/14
20140170794
Thermoelectric semiconductor material, thermoelectric semiconductor element using thermoelectric semiconductor material, thermoelectric module using thermoelectric semiconductor element and manufacturing method for same
A metal mixture is prepared, in which an excess amount of te is added to a (bi—sb)2te3 based composition. After melting the metal mixture, the molten metal is solidified on a surface of a cooling roll of which the circumferential velocity is no higher than 5 m/sec, so as to have a thickness of no less than 30 μm.


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Semiconductor Material topics: Semiconductor, Semiconductor Material, Semiconductor Device, Transistors, Surfactant, Electric Conversion, Transparent Conductive Oxide, Semiconductor Substrate, Heating Devices, Semiconductor Devices, Organic Electroluminescence, Buffer Layer, Integrated Circuit, Crystallin, Electronic Device

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