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Semiconductor Material patents



      

This page is updated frequently with new Semiconductor Material-related patent applications.




Date/App# patent app List of recent Semiconductor Material-related patents
02/04/16
20160037098 
 Image sensors including semiconductor channel patterns patent thumbnailImage sensors including semiconductor channel patterns
The inventive concepts relate to image sensors. The image sensor includes a substrate including a floating diffusion region and a pixel circuit, an interlayer insulating layer on the substrate, a contact node and a first electrode on the interlayer insulating layer, a dielectric layer on a top surface of the first electrode, a channel semiconductor pattern on the dielectric layer and connected to the contact node, and a photoelectric conversion layer on the channel semiconductor pattern.
Samsung Electronics Co., Ltd.


02/04/16
20160035984 
 Organic thin film transistor, organic semiconductor thin film, and organic semiconductor material patent thumbnailOrganic thin film transistor, organic semiconductor thin film, and organic semiconductor material
An organic thin film transistor containing a compound represented by the following formula in a semiconductor active layer has a high carrier mobility and a small change in the threshold voltage after repeated driving. Z represents a substituent having a length of 3.7 Å or less, and at least one of r1 to r8 represents -l-r wherein l represents alkylene, etc., and r represents alkyl, etc..
Fujifilm Corporation


02/04/16
20160035929 
 Lateral single-photon avalanche diode and  producing a lateral single-photon avalanche diode patent thumbnailLateral single-photon avalanche diode and producing a lateral single-photon avalanche diode
The lateral single-photon avalanche diode comprises a semiconductor body comprising a semiconductor material of a first type of electric conductivity, a trench in the semiconductor body, and anode and cathode terminals. A junction region of the first type of electric conductivity is located near the sidewall of the trench, and the electric conductivity is higher in the junction region than at a farther distance from the sidewall.
Ams Ag


02/04/16
20160035878 
 Finfet with dielectric isolation after gate module for improved source and drain region epitaxial growth patent thumbnailFinfet with dielectric isolation after gate module for improved source and drain region epitaxial growth
A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures.
International Business Machines Corporation


02/04/16
20160035877 
 Finfet having highly doped source and drain regions patent thumbnailFinfet having highly doped source and drain regions
A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain.
International Business Machines Corporation


02/04/16
20160035876 
 Fin end spacer for preventing merger of raised active regions patent thumbnailFin end spacer for preventing merger of raised active regions
After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins.
International Business Machines Corporation


02/04/16
20160035875 
 Fin end spacer for preventing merger of raised active regions patent thumbnailFin end spacer for preventing merger of raised active regions
After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins.
International Business Machines Corporation


02/04/16
20160035872 
 Method for the formation of silicon and silicon-germanium fin structures for finfet devices patent thumbnailMethod for the formation of silicon and silicon-germanium fin structures for finfet devices
A substrate layer formed of a first semiconductor material includes adjacent first and second regions. Fin structures are formed from the substrate layer in both the first and second regions.
International Business Machines Corporation


02/04/16
20160035864 
 Fin end spacer for preventing merger of raised active regions patent thumbnailFin end spacer for preventing merger of raised active regions
After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins.
International Business Machines Corporation


02/04/16
20160035863 
 Methods of forming stressed channel regions for a finfet semiconductor device and the resulting device patent thumbnailMethods of forming stressed channel regions for a finfet semiconductor device and the resulting device
An illustrative method includes forming a finfet device above structure comprising a semiconductor substrate, a first epi semiconductor material and a second epi semiconductor material that includes forming an initial fin structure that comprises portions of the semiconductor substrate, the first epi material and the second epi material, recessing a layer of insulating material such that a portion, but not all, of the second epi material portion of the initial fin structure is exposed so as to define a final fin structure, forming a gate structure above and around the final fin structure, removing the first epi material of the initial fin structure and thereby define an under-fin cavity under the final fin structure and substantially filling the under-fin cavity with a stressed material.. .
International Business Machines Corporation


02/04/16
20160035858 

Finfet having highly doped source and drain regions


A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain.
International Business Machines Corporation


02/04/16
20160035851 

Epitaxial metallic transition metal nitride layers for compound semiconductor devices


A method for integrating epitaxial, metallic transition metal nitride (tmn) layers within a compound semiconductor device structure. The tmn layers have a similar crystal structure to relevant semiconductors of interest such as silicon carbide (sic) and the group iii-nitrides (iii-ns) such as gallium nitride (gan), aluminum nitride (aln), indium nitride (inn), and their various alloys.

02/04/16
20160035849 

Strained channel of gate-all-around transistor


The disclosure relates to a semiconductor device. An exemplary structure for a nanowire structure comprises a first semiconductor material having a first lattice constant and a first linear thermal expansion constant; and a second semiconductor material having a second lattice constant and a second linear thermal expansion constant surrounding the first semiconductor material, wherein a ratio of the first lattice constant to the second lattice constant is from 0.98 to 1.02, wherein a ratio of the first linear thermal expansion constant to the second linear thermal expansion constant is greater than 1.2 or less than 0.8..
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160035841 

Multi-composition gate dielectric field effect transistors


A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion.
International Business Machines Corporation


02/04/16
20160035726 

Fin sidewall removal to enlarge epitaxial source/drain volume


A finfet device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer.
Taiwan Semiconductor Manufacturing Co., Ltd.


02/04/16
20160035718 

Electrostatic discharge devices and methods of manufacture


Electrostatic discharge (esd) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material.
International Business Machines Corporation


02/04/16
20160035662 

Semiconductor devices with close-packed via structures having in-plane routing and making same


The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (fs) and an opposite second side (bs). There is at least one conductive wafer-through via (v) comprising metal, and at least one recess (rdl) provided in the first side of the substrate and in the semiconductor material of the substrate.
Silex Microsystems Ab


02/04/16
20160035630 

Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures


One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the n-active region while masking the p-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the p-active region while masking the n-active region, forming an n-type transistor in and above the n-active region and forming a p-type transistor in and above the p-active region.. .
Globalfoundries Inc.


02/04/16
20160033658 

Semiconductor radiation detector array


A radiation detector with improved performance includes a probe and a first detector element constructed from planar semiconductor material in the probe. The detector further includes a second detector element constructed from planar semiconductor material in the probe.
Hitachi High-tech Science Corporation


02/04/16
20160032183 

Alloyed rod structure in a nanocrystalline quantum dot


A quantum dot includes a nanocrystalline core and an alloyed nanocrystalline shell made of a semiconductor material composition different from the nanocrystalline core. The alloyed nanocrystalline shell is bonded to and completely surrounds the nanocrystalline core..

02/04/16
20160031700 

Microelectromechanical microphone


This disclosure provides systems, methods and apparatus including microelectromechanical system microphones. In one aspect, the systems include a substrate made of a low dielectric material, such as glass.
Pixtronix, Inc.


02/04/16
20160029935 

Analyte sensors, systems, testing apparatus and manufacturing methods


In some aspects, an analyte sensor is provided for detecting an analyte concentration level in a bio-fluid sample. The analyte sensor may include one or more conductors received in a hollow portion of a hollow member.
Bayer Healthcare Llc


01/28/16
20160028079 

Oxide shell formation on inorganic substrate via oxidative polyoxoanion salt deposition


The present invention provides a process for depositing an oxide coating on an inorganic substrate, including providing an aqueous composition containing a tetraalkylammonium polyoxoanion and hydrogen peroxide; contacting the aqueous composition with an inorganic substrate for a time sufficient to deposit a hydroxide derived from the polyoxoanion on surfaces of the inorganic substrate to form an initially coated inorganic substrate; and heating the initially coated inorganic substrate for a time sufficient to convert the hydroxide to an oxide to form on the inorganic substrate an oxide coating derived from the polyoxoanion. The inorganic substrate may be a ceramic material or a semiconductor material, a glass or other dielectric material, and the ceramic material may be a lithium ion battery cathode material..
Sachem, Inc.


01/28/16
20160027976 

Optoelectronic semiconductor device and producing an optoelectronic semiconductor device


An optoelectronic semiconductor component has at least one semiconductor chip for emitting electromagnetic radiation. The semiconductor chip has at least one side surface and wherein a part of the electromagnetic radiation exits through the side surface during operation of the semiconductor chip.
Osram Opto Semiconductors Gmbh


01/28/16
20160027958 

Group i-iii-vi material nano-crystalline core and group i-iii-vi material nano-crystalline shell pairing


Nano-crystalline core and nano-crystalline shell pairings having group i-iii-vi material nano-crystalline cores, and methods of fabricating nano-crystalline core and nano-crystalline shell pairings having group i-iii-vi material nano-crystalline cores, are described. In an example, a semiconductor structure includes a nano-crystalline core composed of a group i-iii-vi semiconductor material.
Pacific Light Technologies Corp.


01/28/16
20160027957 

Light emitting devices with built-in chromaticity conversion and methods of manufacturing


Various embodiments of light emitting devices with built-in chromaticity conversion and associated methods of manufacturing are described herein. In one embodiment, a method for manufacturing a light emitting device includes forming a first semiconductor material, an active region, and a second semiconductor material on a substrate material in sequence, the active region being configured to produce a first emission.
Micron Technology, Inc.


01/28/16
20160027947 

Free-standing metallic article for semiconductors


A free-standing metallic article, and method of making, is disclosed in which the metallic article is electroformed on an electrically conductive mandrel. The mandrel has an outer surface with a preformed pattern, wherein at least a portion of the metallic article is formed in the preformed pattern.
Gtat Corpotation


01/28/16
20160027937 

Semiconductor materials and making and using such materials


Novel compounds having a formula m1dm2em3fchg where m1 is a transition metal, a group iii, group iv, or group v element, m2 is a group 13, group 14, or group 15 element, and m3 and ch independently are group 15 or group 16 elements, and a method for making the same are disclosed. The compounds may have a tetrahedrite crystal structure.
Oregon State University


01/28/16
20160027920 

Thin film transistor substrate and fabricating the same


A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the gate electrode and includes an oxide semiconductor material; and a source electrode and a drain electrode disposed on the semiconductor layer, where the drain electrode is spaced apart from the source electrode. The source electrode and the drain electrode each include a barrier layer and a main wiring layer, the a main wiring layer is disposed on the barrier layer, and the barrier layer includes a first metal layer disposed on the semiconductor layer, and a second metal layer disposed on the first metal layer..
Samsung Display Co., Ltd.


01/28/16
20160027894 

Thin oxide formation by wet chemical oxidation of semiconductor surface when the one component of the oxide is water soluble


A semiconductor device is provided, which comprises a semiconductor structure having a surface, the semiconductor structure comprising a material whose oxide is water soluble; and an oxide layer formed on the surface of the semiconductor structure by a wet chemical oxidation treatment utilizing a solvent mixture that comprises a water soluble substance and an aprotic solvent. The layer of oxide may be as thin as approximately 0.7 nanometers in width or less.
Taiwan Semiconductor Manufacturing Company Limited


01/28/16
20160027888 

Silicide formation due to improved sige faceting


An integrated circuit includes a pmos gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in pmos source/drain region.
Texas Instruments Incorporated


01/28/16
20160027877 

Source/drain structures and methods of forming same


The present disclosure provides a semiconductor device including a gate stack disposed over a substrate, a source/drain (s/d) feature at least partially embedded within the substrate adjacent the gate stack. The s/d feature includes a first semiconductor material layer, a second semiconductor material layer disposed over the first semiconductor material layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


01/28/16
20160027806 

Finfet device with abrupt junctions


A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin.
International Business Machines Corporation


01/28/16
20160027788 

Dynamic random access memory cell with self-aligned strap


After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures.
International Business Machines Corporation


01/28/16
20160027784 

Semiconductor device


The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor.
Semiconductor Energy Laboratory Co., Ltd.


01/28/16
20160027781 

Iii-v layers for n-type and p-type mos source-drain contacts


Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of mos transistors of a cmos device, where an intermediate iii-v semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance.
Intel Corporation


01/28/16
20160027774 

Bidirectional switch


A bidirectional switch formed in a substrate includes first and second main vertical thyristors in antiparallel connection. A third auxiliary vertical thyristor has a rear surface layer in common with the rear surface layer of the first thyristor.
Stmicroelectronics (tours) Sas


01/28/16
20160027756 

Semiconductor device


A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost.
Rohm Co., Ltd.


01/28/16
20160027700 

Gate structure cut after formation of epitaxial active regions


A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed.
Globalfoundries Inc.


01/21/16
20160020360 

Engineered substrate assemblies with epitaxial templates and related systems, methods, and devices


Engineered substrates having epitaxial templates for forming epitaxial semiconductor materials and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming a first semiconductor material at a front surface of a donor substrate.

01/21/16
20160020356 

Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated systems and methods


Solid-state transducers (“ssts”) and vertical high voltage ssts having buried contacts are disclosed herein. An sst die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure.
Micron Technology, Inc.


01/21/16
20160020317 

Non-planar quantum well device having interfacial layer and forming same


Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group iv or iii-v semiconductor materials and includes a fin structure.
Intel Corporation


01/21/16
20160020299 

Electronic devices


A method of manufacturing an electronic device comprising a first terminal (e.g. A source terminal), a second terminal (e.g.
Pragmatic Printing Ltd


01/21/16
20160020274 

Semiconductor device and manufacturing the same


A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.. .
Institute Of Microelectronics, Chinese Academy Of Sciences


01/21/16
20160020238 

Semiconductor device for detection of radiation and producing a semiconductor device for detection of radiation


The semiconductor device for detection of radiation comprises a semiconductor substrate (1) with a main surface (11), a dielectric layer (6) comprising at least one compound of a semiconductor material, an integrated circuit (2) including at least one component sensitive to radiation (3), a wiring (4) of the integrated circuit embedded in an intermetal layer (8) of the dielectric layer (6), an electrically conductive through-substrate via (5) contacting the wiring, and an optical filter element (7) arranged immediately on the dielectric layer above the component sensitive to radiation. The dielectric layer comprises a passivation layer (9) at least above the through-substrate via, the passivation layer comprises a dielectric material that is different from the intermetal layer (8), and the wiring is arranged between the main surface and the passivation layer..
Ams Ag


01/21/16
20160020201 

Optoelectronic semiconductor chip and fabrication thereof


An optoelectronic semiconductor chip has a first semiconductor layer sequence which comprises a multiplicity of microdiodes, and a second semiconductor layer sequence which comprises an active region. The first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material, the first semiconductor layer sequence is before the first semiconductor layer sequence in the direction of growth, and the microdiodes form an esd protection for the active region..
Osram Opto Semiconductors Gmbh


01/14/16
20160013619 

Semiconductor interband lasers and forming


A semiconductor interband laser that includes a first cladding layer formed using a first high-doped semiconductor material having a first refractive index/permittivity and a second cladding layer formed using a second high-doped semiconductor material having a second refractive index/permittivity. The laser also includes a waveguide core having a waveguide core refractive index/permittivity, the waveguide core is positioned between the first and the second cladding layers.
The Board Of Regents Of The University Of Oklahoma


01/14/16
20160013434 

Semiconducting layer production process


The invention provides a process for producing a layer of a semiconductor material, wherein the process comprises: a) disposing on a substrate: i) a plurality of particles of a semiconductor material, ii) a binder, wherein the binder is a molecular compound comprising at least one metal atom or metalloid atom, and iii) a solvent; and b) removing the solvent. The invention also provides a layer of semiconductor material obtainable by this process.
Isis Innovation Limited


01/14/16
20160013415 

Organic electroluminescent display device, manufacturing the same and display apparatus


Disclosed is an organic electroluminescent display device, a method for manufacturing the same and a display apparatus. The organic electroluminescent display device comprises: a substrate; a thin film transistor disposed on the substrate and including a gate electrode and an active layer insulated with each other, and a source electrode and a drain electrode connected with the active layer; and an organic electroluminescent structure disposed on the substrate and including an anode, a luminescent layer and a cathode stacked sequentially, the anode and the drain electrode being electrically connected with each other.
Boe Technology Group Co., Ltd.


01/14/16
20160013391 

Thermoelectric conversion material, producing same, and thermoelectric conversion module


The invention provides a thermoelectric conversion material having a low thermal conductivity and an improved figure of merit and a production method for the material, and also provides a thermoelectric conversion module. The thermoelectric conversion material has, on a porous substrate having microscopic pores, a thermoelectric semiconductor layer formed of a thermoelectric semiconductor material, wherein the porous substrate has a polymer layer (b) on a plastic film (a) and the microscopic pores are formed in the polymer layer (b) and in a part of the plastic film (a).
Kyushu Institute Of Technology


01/14/16
20160013336 

Compound-semiconductor photovoltaic cell and manufacturing compound-semiconductor photovoltaic cell


A compound-semiconductor photovoltaic cell includes a first photoelectric conversion cell, which includes an absorption layer made of a first compound-semiconductor material which lattice matches with gallium arsenide (gaas) or germanium (ge); and a window layer made of aluminum indium phosphide (alx1in1-x1p (0<x1≦1)), arranged on an incident side of the absorption layer in a light incident direction, having a lattice constant less than a lattice constant of the absorption layer, and having a band gap greater than a band gap of the absorption layer.. .
Ricoh Company, Ltd.


01/14/16
20160013296 

Methods of forming low defect replacement fins for a finfet semiconductor device and the resulting devices


One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a <100> crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the substrate fin, wherein the replacement fin structure is comprised of a semiconductor material that is different from the first semiconductor material, and a gate structure positioned around at least a portion of the replacement fin structure.. .
Globalfoundries Inc.


01/14/16
20160013291 

Methods of forming isolated channel regions for a finfet semiconductor device and the resulting device


A fin structure is formed in and above a substrate and includes a portion of a substrate semiconductor material, a first epi semiconductor material formed above the substrate semiconductor material portion, and a second epi semiconductor material formed above the first epi semiconductor material. A sacrificial gate structure is formed above the fin structure, a sidewall spacer is formed adjacent the sacrificial gate structure, and at least one etching process is performed to remove portions of the fin structure positioned laterally outside of the sidewall spacer so as to define a fin cavity source/drain regions and to expose edges of the fin structure positioned under the spacer.
Stmicroelectronics, Inc.


01/14/16
20160013270 

Semiconductor device and manufacturing method thereof


A si-on-half-insulator device and its manufacturing method are disclosed in this invention. In one embodiment, a horizontal insulating layer located below at least one of the source and drain regions is realized to reduce junction capacitance.
Semiconductor Manufacturing International (beijing) Corporation


01/14/16
20160013216 

Array substrate and fabricating the same, and liquid crystal display device


An array substrate, a method of fabricating the same, and a liquid crystal display device are disclosed. The method comprises: sequentially forming a first transparent conductive material layer, an insulation material layer, a semiconductor material layer and a photoresist layer on a substrate base and forming patterns including a gate line, a gate, a gate insulation layer, a semiconductor layer and a first transparent electrode by patterning process; forming a passivation layer and forming a source via and a drain via connected to the semiconductor layer in the passivation layer; sequentially forming a second transparent conductive material layer and a source-drain metal layer and forming patterns including a source, a drain and a second transparent electrode by patterning process, the gate insulation layer is formed only on the gate and the gate line, the source and the drain include stacked second transparent conductive material layer and source-drain metal layer..
Boe Technology Group Co., Ltd.


01/14/16
20160013189 

Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin structures


A method of forming a semiconductor device that includes forming an at least partially relaxed semiconductor material, and forming a plurality of fin trenches in the partially relaxed semiconductor material. At least a portion of the plurality of fin trenches is filled with a first strained semiconductor material that is formed using epitaxial deposition.
International Business Machines Corporation


01/14/16
20160013095 

Uniform shallow trench isolation regions and the forming the same


A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the first material is different from the second material. A third material is formed on treated first surface of the first material and on treated second surface of the second material.
Taiwan Semiconductor Manufacturing Company, Ltd.


01/14/16
20160011722 

Electrostatic and piezoelectric touch panel


An electrostatic and piezoelectric touch panel includes a first switching circuit, a second switching circuit, at least one first sensing device, and at least one second sensing device. The first sensing device includes a first transistor and a piezoelectric-transistor.
Chung Hua University


01/07/16
20160006214 

Surface emitting semiconductor laser, surface emitting semiconductor laser device, optical transmission device, and information processing apparatus


A surface emitting semiconductor laser includes: a substrate; a first semiconductor multilayer reflector on the substrate including laminated pairs of a high refractive index layer relatively high in refractive index and a low refractive index layer relatively low in refractive index; an active region on or above the first reflector; a second semiconductor multilayer reflector on or above the active region including laminated pairs of a high refractive index layer relatively high in refractive index and a low refractive index layer relatively low in refractive index; and a cavity extending region formed between the first reflector and the active region or between the second reflector and the active region, having an optical film thickness greater than an oscillation wavelength, extending a cavity length, including a conductive semiconductor material, and including an optical loss causing layer at at least one node of a standing wave of a selected longitudinal mode.. .
Fuji Xerox Co., Ltd.


01/07/16
20160005909 

Photoactive devices having low bandgap active layers configured for improved efficiency and related methods


Photoactive devices include an active region disposed between first and second electrodes and is configured to absorb radiation and generate a voltage between the electrodes. The active region includes an active layer comprising a semiconductor material exhibiting a relatively low bandgap.
Soitec


01/07/16
20160005895 

Interband cascade devices


Photovoltaic (pv) and photodetector (pd) devices, comprising a plurality of interband cascade (ic) stages, wherein the ic stages comprise an absorption region with a type-i superlattice and/or a bulk semiconductor material having a band gap, the absorption region configured to absorb photons, an intraband transport region configured to act as a hole barrier, and an interband tunneling region configured to act as an electron barrier, wherein the absorption region, the intraband transport region, and the interband tunneling region are positioned such that electrons will flow from the absorption region to the intraband transport region to the interband tunneling region.. .
Board Of Regents University Of Oklahoma


01/07/16
20160005892 

Vertical pillar structure photovoltaic devices and making the same


Thin substrate photovoltaic and methods for making them are disclosed herein. In an embodiment, a photovoltaic device may include a substrate comprising a semiconductor material, one or more core structures, each extending essentially perpendicularly from a first surface of the substrate such that the core structures and the substrate form a single crystal, a shell layer disposed at least on a portion of a sidewall of the core structures and on the first surface, and a conductive layer disposed between adjacent core structures.
Zena Technologies, Inc.


01/07/16
20160005887 

Highly efficient optical to electrical conversion devices and methods


Methods, systems, and devices are disclosed for implementing high conversion efficiency solar cells. In one aspect, an optical-to-electrical energy conversion device includes a substrate formed of a doped semiconductor material and having a first region and a second region, an array of multilayered nanoscale structures protruding from the first region of the substrate, in which the nanoscale structures are formed of a first co-doped semiconductor material covered by a layer of a second co-doped semiconductor material forming a core-shell structure, the layer covering at least a portion of the doped semiconductor material of the substrate in the second region, and an electrode formed on the layer-covered portion of the substrate in the second region, in which the multilayered nanoscale structures provide an optical active region capable of absorbing photons from light at one or more wavelengths to generate an electrical signal presented at the electrode..
The Regents Of The University Of California


01/07/16
20160005834 

Methods of forming a channel region for a semiconductor device by performing a triple cladding process


One illustrative method disclosed herein includes, among other things, forming a plurality of trenches that define a fin, performing a plurality of epitaxial deposition processes to form first, second and third layers of epi semiconductor material around an exposed portion of the fin, removing the first, second and third layers of epi semiconductor material from above an upper surface of the fin so as to thereby expose the fin, selectively removing the fin relative to the first, second and third layers of epi semiconductor material so as to thereby define two fin structures comprised of the first, second and third layers of epi semiconductor material, and forming a gate structure around a portion of at least one of the fin structures comprised of the first, second and third layers of epi semiconductor material.. .
Globalfoundries Inc.


01/07/16
20160005815 

Semiconductor constructions


Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of x and the mesas have widths along the cross-section of at least 3x.
Micron Technology, Inc.


01/07/16
20160005813 

Fin structures and methods of manfacturing the fin structures, and fin transistors having the fin structures and methods of manufacturing the fin transistors


Fin structures and methods of forming the fin structure are provided. Fin structures may include a semiconductor fin that is on a silicon layer and includes a group iv semiconductor material that includes germanium, an isolation insulation layer at two lower sides of the semiconductor fin and a bottom insulation layer under the semiconductor fin and the isolation insulation layer.

01/07/16
20160005807 

Semiconductor structure with dielectric-sealed doped region


Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material.
Taiwan Semiconductor Manufacturing Company, Ltd.


01/07/16
20160005758 

Three-dimensional vertical gate nand flash memory including dual-polarity source pads


A memory includes a three-dimensional array including a plurality of levels is described. Each level includes a bit line pad, a source line pad, and a plurality of strips of semiconductor material extending between the bit line pad and the source line pad.
Macronix International Co., Ltd.


01/07/16
20160005746 

Memory architecture of 3d array with interleaved control structures


A 3d memory device includes a first plurality and a second plurality of stacks of semiconductor material strips on a substrate. The second plurality of stacks of gate material strips on the substrate is interleaved with, and coplanar with, the first plurality of stacks.
Macronix International Co., Ltd.


01/07/16
20160005628 

Wafer level packaging method and integrated electronic package


A wafer level packaging method entails providing electronic devices and providing a platform structure having cavities extending through the platform structure. The platform structure is mounted to a temporary support.
Freescal Semiconductor, Inc.


01/07/16
20160002750 

Hydrometallurgical process for recovery of metals and/or semimetals from waste materials containing compound semiconductor materials and/or back contact materials and/or transparent electrically conducting oxides (tcos)


The present invention relates to a hydrometallurgical process for recovery of metals and/or semimetals from waste materials, such as high-tech or green-tech wastes, and/or electrical and electronic waste containing compound semiconductor materials and/or back contact materials and/or transparent electrically conducting oxides (tcos), wherein the waste materials according to the invention are mixed thoroughly with a reaction solution of water, 1 to 5% by mass sodium bisulphate and 1-5% by mass sodium chlorite or with a reaction solution of water, 1 to 50% by mass organosulphonic acid and in the stoichiometric ratio to the organosulphonic acid 1-5% by mass of an oxidizing agent, and the metals and/or semimetals that are to be recovered are dissolved.. .

01/07/16
20160002164 

Compound with branching alkyl chains, preparing the same, and use thereof in photoelectric device


The invention discloses a compound having branching alkyl chains, the method for preparing the same and use thereof in photoelectric devices. By applying the branching alkyl chains as the solubilizing group to the preparation of organic conjugated molecules (for example, organic conjugated polymers), the number of methylenes between the resultant alky side chains and the backbone, i.e., m>1, which can effectively reduce the effect of the alkyl chains on the backbone π-π stacking, thereby ensuring the solubility of the organic conjugated molecule while greatly increasing the mobility of their carriers.
Peking University


12/31/15
20150380727 

Oxide shell formation on inorganic substrates via lithium polyoxoanion salt deposition


The present invention provides a process for depositing an oxide coating on an inorganic substrate, including providing an aqueous composition containing a tetraalkylammonium polyoxoanion and lithium hydroxide; contacting the aqueous composition with an inorganic substrate for a time sufficient to deposit a lithium polyoxoanion on surfaces of the inorganic substrate to form an initially coated inorganic substrate; and heating the initially coated inorganic substrate for a time sufficient to convert the lithium polyoxoanion to an oxide to form on the inorganic substrate an oxide coating derived from the polyoxoanion. The inorganic substrate may be a ceramic material or a semiconductor material, a glass or other dielectric material, and the ceramic material may be a lithium ion battery cathode material..
Sachem, Inc.


12/31/15
20150380590 

Energy harvester


In one or more disclosed embodiments a circuit is configured and arranged to harvest photonic energy. The circuit includes a quantum stack having a plurality of quantum confinement regions.
Nxp B.v.


12/31/15
20150380525 

Structure and finfet device


A method for fabricating a fin-type field-effect transistor (finfet) device includes forming a first fin structure over a substrate, forming a dielectric layer over the first fin structures, forming a trench with a vertical profile in the dielectric layer, depositing conformably a first semiconductor material layer over sidewalls and bottom of the trench, depositing a second semiconductor material layer over the first semiconductor material layer to filling in the remaining trench, recessing the dielectric layer to laterally expose the first semiconductor material layer and etching the exposed first semiconductor material layer to reveal the second semiconductor material layer.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


12/31/15
20150380489 

Low resistance and defect free epitaxial semiconductor material for providing merged finfets


A gate structure is formed straddling a first portion of a plurality of semiconductor fins that extend upwards from a topmost surface of an insulator layer. A dielectric spacer is formed on sidewalls of the gate structure and straddling a second portion of the plurality of semiconductor fins.
International Business Machines Corporation


12/31/15
20150380450 

Imaging device and electronic device


An imaging device with high productivity and improved dynamic range is provided. The imaging device includes a pixel driver circuit and a photoelectric conversion element including a p-type semiconductor, an n-type semiconductor, and an i-type semiconductor.
Semiconductor Energy Laboratory Co., Ltd.


12/31/15
20150380441 

Array substrate and manufacturing method thereof, liquid crystal display panel and display device


An array substrate and a manufacturing method thereof, a liquid crystal display panel and a display device are provided, the array substrate comprises a base substrate, and thin film transistors and pixel electrodes provided on the base substrate, the pixel electrode and the active layer in the thin film transistor are provided in the same layer. The active layer is formed of transparent oxide semiconductor material, and the concentration of carriers in the oxide semiconductor material may be increased by performing a plasma process on the oxide semiconductor material, thus the pixel electrode may be manufactured by using the oxide semiconductor material used for manufacturing the active layer, thereby the pixel electrode and the active layer can be provided in the same layer, the number of the masks can be reduced, the manufacturing process is simplified, production cost is saved, the productivity is increased, and the manufacturing time is shortened..
Boe Technology Group Co., Ltd.


12/31/15
20150380432 

Methods of forming a charge-retaining transistor


A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes first semiconductor material alongside the inter-gate dielectric.
Micron Technology, Inc.


12/31/15
20150380430 

Junction formation for vertical gate 3d nand memory


A method is provided for manufacturing a memory device. A plurality of layers of a first semiconductor material is formed, and a plurality of holes is formed through the layers.
Macronix International Co., Ltd.


12/31/15
20150380405 

Removal of semiconductor growth defects


After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces.
International Business Machines Corporation


12/31/15
20150380399 

Devices and methodologies related to structures having hbt and fet


A semiconductor structure includes a heterojunction bipolar transistor (hbt) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (fet) located over the substrate, the fet having a channel formed in the semiconductor material that forms the collector layer of the hbt. In some implementations, a second fet can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the hbt.
Skyworks Solutions, Inc.


12/31/15
20150380363 

Methods and apparatus to reduce semiconductor wafer warpage in the presence of deep cavities


Methods and apparatus for forming structures to reduce wafer warpage. A method includes providing a semiconductor wafer having a plurality of integrated circuits; providing a photomask defining a plurality of cavities to be formed by an etch on a backside surface of the semiconductor wafer; defining structural support areas for the backside surface, the structural support areas being contiguous areas; providing areas on the photomask that correspond to the structural support areas, the structural support areas being areas that are not to be etched; using the photomask, performing an etch on the backside surface of the semiconductor wafer to form the cavities by removing semiconductor material from the backside surface of the semiconductor wafer; and the structural supports on the backside of the semiconductor wafer formed as areas that are not subjected to the etch.
Texas Instruments Incorporated


12/31/15
20150380314 

Low resistance and defect free epitaxial semiconductor material for providing merged finfets


A gate structure is formed straddling a first portion of a plurality of semiconductor fins that extend upwards from a topmost surface of an insulator layer. A dielectric spacer is formed on sidewalls of the gate structure and straddling a second portion of the plurality of semiconductor fins.
International Business Machines Corporation


12/31/15
20150380313 

Method of forming semiconductor structure with horizontal gate all around structure


A method of forming a semiconductor device having a horizontal gate all around structure on a bulk substrate is provided. The method comprises forming a plurality of fins on a bulk substrate wherein each fin comprises a vertical slice of substrate material and a plurality of channel layers above the vertical slice of substrate material.
Taiwan Semiconductor Manufacturing Company Limited


12/31/15
20150380251 

Block mask litho on high aspect ratio topography with minimal semiconductor material damage


A trilayer stack that can be used as a block mask for forming patterning features in semiconductor structures with high aspect ratio topography is provided. The trilayer stack includes an organic planarization (opl) layer, a titanium-containing antireflective coating (tiarc) layer on the opl layer and a photoresist layer on the tiarc layer.
International Business Machines Corporation


12/31/15
20150377624 

Micro-electro-mechanical device with compensation of errors due to disturbance forces, such as quadrature components


Mems device having a support region elastically carrying a suspended mass through first elastic elements. A tuned dynamic absorber is elastically coupled to the suspended mass and configured to dampen quadrature forces acting on the suspended mass at the natural oscillation frequency of the dynamic absorber.
Stmicroelectronics, S.r.l.


12/24/15
20150372634 

Lateral photovoltaic device for near field use


A device, method and process of fabricating an interdigitated multicell thermo-photo-voltaic component that is particularly efficient for generating electrical energy from photons in the red and near-infrared spectrum received from a heat source in the near field. Where the absorbing region is germanium, the device is capable of generating electrical energy by absorbing photon energy in the greater than 0.67 electron volt range corresponding to radiation in the infrared and near-infrared spectrum.
Mtpv Power Corporation


12/24/15
20150372393 

Micro assembled high frequency devices and arrays


Phased-array antenna systems can be constructed using transfer printed active components. Phased-array antenna systems benefit from a large number of radiating elements (e.g., more radiating elements can form sharper, narrower beams (higher gain)).
X-celeprint Limited


12/24/15
20150372192 

Method and creating a porus reflective contact


A light emitting device includes a semiconductor structure having a light emitting region (102) disposed between an n-type region (103) and a p-type region (101). A porous region (103a) is disposed between the light emitting region (102) and a contact (n-contact 131) electrically connected to one of the n-type region (103) and the p-type regions (101).
Koninklijke Philips N.v.


12/24/15
20150372176 

Optoelectronic device and producing the same


An optoelectronic device comprising a substrate having a first and a second series of grooves and a channel therebetween. Each groove of the first and second series of grooves has a first and a second face and a cavity therebetween.
Big Solar Limited


12/24/15
20150372145 

High density vertical nanowire stack for field effect transistor


An alternating stack of layers of a first epitaxial semiconductor material and a second epitaxial semiconductor material is formed on a substrate. A fin stack is formed by patterning the alternating stack into a shape of a fin having a parallel pair of vertical sidewalls.
International Business Machines Corporation


12/24/15
20150372120 

Fin structure of semiconductor device


A fin structure of a semiconductor device, such as a fin field effect transistor (finfet), and a method of manufacture, is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/24/15
20150372116 

Apparatus and multiple gate transistors


A method comprises etching away an upper portion of a substrate to form a trench between two adjacent isolation regions, wherein the substrate has a first crystal orientation and is formed of a first semiconductor material, growing a first semiconductor region in the trench over the substrate, wherein the first semiconductor region is formed of a second semiconductor material and an upper portion of the first semiconductor region has a second crystal orientation and growing a second semiconductor region over the first semiconductor region, wherein the second semiconductor region is formed of a third semiconductor material.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


12/24/15
20150372115 

Methods of forming nanowire devices with doped extension regions and the resulting devices


A method of forming a nanowire device includes patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces. The method further includes forming doped extension regions in the first and second exposed end surfaces of the semiconductor material layers.
Globalfoundries Inc.


12/24/15
20150372112 

Replacement gate structure for enhancing conductivity


After formation of a gate cavity straddling at least one semiconductor material portion, a gate dielectric layer and at least one work function material layer is formed over the gate dielectric layer. The at least one work function material layer and the gate dielectric layer are patterned such that remaining portions of the at least one work function material layer are present only in proximity to the at least one semiconductor material portion.
International Business Machines Corporation


12/24/15
20150372111 

Methods of forming nanowire devices with spacers and the resulting devices


A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces.
Globalfoundries Inc.


12/24/15
20150372109 

Replacement gate structure for enhancing conductivity


After formation of a gate cavity straddling at least one semiconductor material portion, a gate dielectric layer and at least one work function material layer is formed over the gate dielectric layer. The at least one work function material layer and the gate dielectric layer are patterned such that remaining portions of the at least one work function material layer are present only in proximity to the at least one semiconductor material portion.
International Business Machines Corporation


12/24/15
20150372093 

Wide bandgap high-density semiconductor switching device and manufacturing process thereof


A switching device, such as a barrier junction schottky diode, has a body of silicon carbide of a first conductivity type housing switching regions of a second conductivity type. The switching regions extend from a top surface of the body and delimit body surface portions between them.
Stmicroelectronics S.r.l.


12/24/15
20150372091 

Semiconductor chip carriers with monolithically integrated quantum dot devices and manufacture thereof


A three-dimensional polycrystalline semiconductor material provides a major ingredient forming individual crystalline grains having a nominal maximum grain diameter less than or equal to 50 nm, and a minor ingredient forming boundaries between the individual crystalline grains.. .

12/24/15
20150372075 

Edge termination structure for a power integrated device and corresponding manufacturing process


An integrated device has: a structural layer of semiconductor material doped with a first conductivity type and having a top surface defining a plane; a functional region, doped with a second conductivity type, arranged in an active area of the structural layer at the top surface, in the proximity of an edge area of the integrated device, which externally surrounds the active area; and an edge termination region, doped with the second conductivity type, joined to the functional region and arranged in the edge area. The edge termination region has a doping profile and a junction depth that vary in a first direction parallel to the plane..
Stmicroelectronics S.r.l.




Semiconductor Material topics: Semiconductor, Semiconductor Material, Semiconductor Device, Transistors, Surfactant, Electric Conversion, Transparent Conductive Oxide, Semiconductor Substrate, Heating Devices, Semiconductor Devices, Organic Electroluminescence, Buffer Layer, Integrated Circuit, Crystallin, Electronic Device

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