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Semiconductor Material patents



      

This page is updated frequently with new Semiconductor Material-related patent applications.




Date/App# patent app List of recent Semiconductor Material-related patents
07/21/16
20160212834 
 Cyclic accelerator for accelerating charge carriers and  manufacturing a cyclic accelerator patent thumbnailCyclic accelerator for accelerating charge carriers and manufacturing a cyclic accelerator
What is shown is a cyclic accelerator for accelerating charge carriers. The cyclic accelerator includes a charge carrier source configured to generate free charge carriers, a vacuum chamber configured to receive the free charge carriers, wherein the vacuum chamber is produced by means of mems technology, and wherein at least a main surface region of the vacuum chamber has a semiconductor material.
Fraunhofer-gesellschaft Zur Foerderung Der Angewandten Forschung E.v.


07/21/16
20160211411 
 High efficiency ultraviolet light emitting diode with band structure potential fluctuations patent thumbnailHigh efficiency ultraviolet light emitting diode with band structure potential fluctuations
A method of growing an algan semiconductor material utilizes an excess of ga above the stoichiometric amount typically used. The excess ga results in the formation of band structure potential fluctuations that improve the efficiency of radiative recombination and increase light generation of optoelectronic devices, in particular ultraviolet light emitting diodes, made using the method.
Trustees Of Boston University


07/21/16
20160211295 
 Blue enhanced image sensor patent thumbnailBlue enhanced image sensor
A back side illuminated image sensor includes a semiconductor material having a front side and a back side. The semiconductor material is disposed between image sensor circuitry and a light filter array.
Omnivision Technologies, Inc.


07/21/16
20160211267 
 Semiconductor storage device patent thumbnailSemiconductor storage device
Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked.
Semiconductor Energy Laboratory Co., Ltd.


07/21/16
20160211261 
 Method and structure for finfet devices patent thumbnailMethod and structure for finfet devices
A semiconductor device and a method of forming the same are disclosed. The device comprises a semiconductor substrate comprised of a first semiconductor material and having a plurality of isolation features, thereby defining a first active region and a second active region; a first fin semiconductor feature comprised of a second semiconductor material and formed in the first active region; and a second fin semiconductor feature comprised of a second semiconductor material and formed in the second active region.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/21/16
20160211258 
 Reverse-conducting gated-base bipolar-conduction devices and methods with reduced risk of warping patent thumbnailReverse-conducting gated-base bipolar-conduction devices and methods with reduced risk of warping
Reverse-conducting igbts where the collector side includes diode terminal regions, and the semiconductor material is much thicker through the diode terminal regions than it is through the collector regions. This exploits the area fraction which is taken up by the diode terminal regions to provide increased rigidity for the wafer, and thus avoid warping..
Maxpower Semiconductor Inc.


07/21/16
20160211227 
 Semiconductor device including a protection structure patent thumbnailSemiconductor device including a protection structure
A device includes a semiconductor chip including a dicing edge. The device further includes an active structure arranged in a semiconductor material of the semiconductor chip, and a protection structure arranged between the dicing edge and the active structure..
Infineon Technologies Ag


07/21/16
20160211043 
 Systems and methods for regulating electrical power generated from a decay of radiation-emitting isotopes patent thumbnailSystems and methods for regulating electrical power generated from a decay of radiation-emitting isotopes
Systems and methods are presented for regulating electrical power generated from a decay of radiation-emitting isotopes. The systems include a diode formed of a semiconductor material capable of mitigating radiation damage by operating at temperatures greater than 300° c.
Idaho State University


07/21/16
20160211042 
 Devices and methods for converting energy from radiation into electrical power patent thumbnailDevices and methods for converting energy from radiation into electrical power
Devices and methods are presented for converting energy from radiation into electrical power. In one illustrative embodiment, a device for converting energy from radiation into electrical power includes a diode formed of a semiconductor material capable of mitigating radiation damage by operating at temperatures greater than 300° c.
Idaho State University


07/21/16
20160207757 
 Mems device and corresponding micromechanical structure with integrated compensation of thermo-mechanical stress patent thumbnailMems device and corresponding micromechanical structure with integrated compensation of thermo-mechanical stress
A micromechanical structure of a mems device, integrated in a die of semiconductor material provided with a substrate and having at least a first axis of symmetry lying in a horizontal plane, has a stator structure, which is fixed with respect to the substrate, and a rotor structure, having a suspended mass, mobile with respect to the substrate and to the stator structure as a result of an external action, the stator structure having fixed sensing electrodes capacitively coupled to the rotor structure; a compensation structure is integrated in the die for compensation of thermo-mechanical strains. The compensation structure has stator compensation electrodes, which are fixed with respect to the substrate, are capacitively coupled to the rotor structure, and are arranged symmetrically to the fixed sensing electrodes with respect to the first axis of symmetry..
Stmicroelectronics S.r.l.


07/14/16
20160204327 

Compound semiconductors and their applications


Disclosed is a new compound semiconductor material which may be used for thermoelectric material or the like, and its applications. The compound semiconductor may be represented by chemical formula 1 below: chemical formula 1 bi1-xmxcu1-wtwoa-yq1ytebsez where, in chemical formula 1, m is at least one selected from the group consisting of ba, sr, ca, mg, cs, k, na, cd, hg, sn, pb, mn, ga, in, tl, as and sb, q1 is at least one selected from the group consisting of s, se, as and sb, t is at least one selected from the group consisting of transition metal elements, 0≦x<1, 0<w<1, 0.2<a<1.5, 0≦y<1.5, 0≦b<1.5 and 0≦z<1.5..
Lg Chem, Ltd.


07/14/16
20160204278 

Self-aligned metal oxide tft with reduced number of masks and with reduced power consumption


A method of fabricating mo tfts includes positioning opaque gate metal on a transparent substrate to define a gate area. Depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon.

07/14/16
20160204231 

Semiconductor device and manufacturing method thereof


A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204211 

Self-limiting silicide in highly scaled fin technology


A method of forming a metal semiconductor alloy on a fin structure that includes forming a semiconductor material layer of a polycrystalline crystal structure material or amorphous crystal structure material on a fin structure of a single crystal semiconductor material, and forming a metal including layer on the semiconductor material layer. Metal elements from the metal including layer may then b intermixed metal elements with the semiconductor material layer to provide a metal semiconductor alloy contact on the fin structure.
International Business Machines Corporation


07/14/16
20160204205 

Source material for electronic device applications


Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material.
Micron Technology, Inc.


07/14/16
20160204198 

High mobility transistors


An integrated circuit containing an n-channel finfet and a p-channel finfet has a dielectric layer over a silicon substrate. The fins of the finfets have semiconductor materials with higher mobilities than silicon.
Texas Instruments Incorporated


07/14/16
20160204194 

Method and structure for improving finfet with epitaxy source/drain


Isolation structures are formed to laterally surround a gate material block such that each sidewall of the gate material block abuts a corresponding sidewall of the isolation structures. Sidewalls of the gate material bock define ends of gate structures to be subsequently formed.
International Business Machines Corporation


07/14/16
20160204131 

Strain release in pfet regions


A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (ssoi) structure, the ssoi structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the ssoi structure, forming a gate structure over a portion of at least one fin in a nfet region, forming a gate structure over a portion of at least one fin in a pfet region, removing the gate structure over the portion of the at least one fin in the pfet region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pfet region, such that the new gate structure surrounds the portion on all four sides.. .
International Business Machines Corporation


07/14/16
20160204039 

Temperature-controlled implanting of a diffusion-suppressing dopant in a semiconductor structure


Semiconductor structures and methods of fabrication are provided for, for instance, inhibiting diffusion of active dopant within a semiconductor material. A diffusion-suppressing dopant is implanted via, an implanting process under controlled temperature, into a semiconductor material of a semiconductor structure to define a diffusion-suppressed region within the semiconductor material.
Globalfoundries Inc.


07/14/16
20160204004 

Wafer-scale package including power source


A medical device includes a first substrate, a second substrate, a control module, and an energy storage device. The first substrate includes at least one of a first semiconductor material and a first insulating material.
Medtronic, Inc.


07/14/16
20160203980 

Device isolation for iii-v substrates


Techniques for device isolation for iii-v semiconductor substrates are provided. In one aspect, a method of fabricating a iii-v semiconductor device is provided.
International Business Machines Corporation


07/14/16
20160203973 

Method for the surface treatment of a semiconductor substrate


To apply an anti-wetting coating to a substrate of a semiconductor material, a method includes applying to a support a solution of a hydrocarbon comprising at least one unsaturated bond and, optionally, at least one hetero-atom for obtaining a layer of hydrocarbons. The method also includes treating at least one surface of the substrate of the semiconductor material with an acid.
Stmicroelectronics S.r.l.


07/14/16
20160202329 

Amr-type integrated magnetoresistive sensor for detecting magnetic fields perpendicular to the chip


An amr-type integrated magnetoresistive sensor sensitive to perpendicular magnetic fields is formed on a body of semiconductor material covered by an insulating region. The insulating region houses a set/reset coil and a magnetoresistor arranged on the set/reset coil.
Stmicroelectronics S.r.l.


07/07/16
20160197454 

Passive waveguide structure with alternating gainas/alinas layers for mid-infrared optoelectronic devices


Disclosed is a semiconductor optical emitter having an optical mode and a gain section, the emitter comprising a low loss waveguide structure made of two alternating layers of semiconductor materials a and b, having refractive indexes of na and nb, respectively, with an effective index no of the optical mode in the low loss waveguide between na and nb, wherein no is within a 5% error margin of identical to a refractive index of the gain section and wherein the gain section is butt-jointed with the low loss waveguide, and wherein the size and shape of the optical mode(s) in the low loss waveguide and gain section are within a 10% error margin of equal. Desirably, at least one of the semiconductor materials a and b has a sufficiently large band gap that the passive waveguide structure blocks current under a voltage bias of 15 v..
Thorlabs Quantum Electronics, Inc.


07/07/16
20160197281 

Photoelectric conversion device and fabrication method therefor


In order to form a photoelectric conversion layer of a photoelectric conversion element, mixed liquid including poly-[n-9′-heptadecanyl-2,7-carbazole-alt-5,5-(4′,7′-di-2-thienyl2′,1′,3′-benzothiadiazle)] as a p-type organic semiconductor material and a fullerene derivative as an n-type organic semiconductor material, which configure a bulk heterojunction are applied and dried. The dried substance is exposed in an atmosphere including vapor of a solvent that dissolves the p-type organic semiconductor material preferentially to the n-type organic semiconductor material..
Fujitsu Limited


07/07/16
20160197260 

Thermoelectric generator


A thermoelectric generator for powering a load includes a first mounting plate, a second mounting plate, and a plurality of semiconductors positioned between the first and the second mounting plates. The plurality of semiconductors includes one of positive-type or negative-type semiconductor material..
The Boeing Company


07/07/16
20160197256 

New compound semiconductors and their application


Disclosed is a new compound semiconductor material which may be used for thermoelectric material or the like, and its applications. The compound semiconductor may be represented by chemical formula 1 below: chemical formula 1 <chemical formula 1> bi2texsen−xinymz where in chemical formula 1, m is at least one selected from the group consisting of cu, fe, co, ag and ni, 2.5<x<3.0, 3.0≦a<3.5, 0<y and 0≦z..
Lg Chem, Ltd.


07/07/16
20160197231 

Solid state lighting devices with dielectric insulation and methods of manufacturing


Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials.
Micron Technology, Inc.


07/07/16
20160197223 

High-frequency optoelectronic detector, system and method


An optoelectronic device for detecting electromagnetic radiation includes a body of semiconductor material. A first region and a second region that form a junction are provided within the body.
Stmicroelectronics S.r.l.


07/07/16
20160197186 

Finfet with dielectric isolation after gate module for improved source and drain region epitaxial growth


A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures.
International Business Machines Corporation


07/07/16
20160197182 

Finfet and forming the same


The present disclosure provides a method for forming a field-effect fin transistor (finfet) structure. The method includes providing a substrate with fin structures; forming a gate structures across the fin structures; and forming ion implantation regions in the fin structures at both sides of the gate structure.
Semiconductor Manufacturing International (shanghai) Corporation


07/07/16
20160197093 

Semiconductor memory device and manufacturing same


According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body.
Kabushiki Kaisha Toshiba


07/07/16
20160197078 

Structure and advanced bulk fin isolation


A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant..
International Business Machines Corporation


07/07/16
20160197077 

Structure and advanced bulk fin isolation


A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant..
International Business Machines Corporation


07/07/16
20160197072 

Semiconductor device with different fin sets


A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench..
Globalfoundries Inc.


07/07/16
20160195489 

Electrical devices with enhanced electrochemical activity and manufacturing methods thereof


In some aspects, a device is provided having a member with a region of enhanced electrochemical activity. In one aspect, a sensor of enhanced electrochemical activity is provided for detecting an analyte concentration level in a bio-fluid sample.
Ascensia Diabetes Care Holding Ag


07/07/16
20160195479 

Multiple beam transmission interferometric testing methods for the development and evaluation of subwavelength sized features within semiconductor and anisotropic devices


Improved methods and systems for inspection imaging for holographic or interferometric semiconductor test and evaluation through all phases of device development and manufacture. Specifically, systems and methods are disclosed for extending the range of optical holographic interferometric inspection for testing and evaluating microelectronic devices and determining the interplay of electromagnetic signals and dynamic stresses to the semiconductor material are provided in which an enhanced imaging method provides continuous and varying the magnification of the optical holographic interferometric images over a plurality of interleaved optical pathways and imaging devices.
Attofemto, Inc.


06/30/16
20160191017 

Co-integrated bulk acoustic wave resonators


An electrical circuit assembly can include a semiconductor integrated circuit, such as fabricated including cmos devices. A first lateral-mode resonator can be fabricated upon a surface of the semiconductor integrated circuit, such as including a deposited acoustic energy storage layer including a semiconductor material, a deposited piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer, and a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to the semiconductor integrated circuit.

06/30/16
20160190556 

Anode material having a uniform metal-semiconductor alloy layer


The present invention relates to methods for producing anode materials for use in nonaqueous electrolyte secondary batteries. In the present invention, a metal-semiconductor alloy layer is formed on an anode material by contacting a portion of the anode material with a solution containing metals ions and a dissolution component.

06/30/16
20160190376 

Photovoltaic cell with variable band gap


A monolithic photovoltaic cell is proposed. Said cell comprises at least one junction.

06/30/16
20160190339 

Semiconductor devices with conductive contact structures having a larger metal silicide contact area


A semiconductor device includes a source/drain region, a gate structure, a gate cap layer positioned above the gate structure and a sidewall spacer positioned adjacent to opposite sides of the gate structure. A first epi semiconductor material is positioned in the source/drain region, the first epi semiconductor material having a first lateral width at an upper surface thereof.

06/30/16
20160190336 

Complementary high mobility nanowire neuron device


A method for forming a semiconductor device includes providing a substrate structure, which includes a nanowire structure supported by two isolation regions on a substrate. The nanowire structure includes a first nanowire and a second nanowire having different high mobility semiconductor materials and conductivity types.

06/30/16
20160190319 

Non-planar semiconductor devices having multi-layered compliant substrates


Non-planar semiconductor devices having multi-layered compliant substrates and methods of fabricating such non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate.

06/30/16
20160190315 

Method and structure of making enhanced utbb fdsoi devices


An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material.

06/30/16
20160190306 

Finfet device with a substantially self-aligned isolation region positioned under the channel region


One illustrative device disclosed herein includes, among other things, a semiconductor substrate, a fin structure, a gate structure positioned around a portion of the fin structure in the channel region of the device, spaced-apart portions of a second semiconductor material positioned vertically between the fin structure and the substrate, wherein the second semiconductor material is a different semiconductor material than that of the fin, and a local channel isolation material positioned laterally between the spaced-apart portions of the second semiconductor material and vertically below the fin structure and the gate structure, wherein the local channel isolation material is positioned under at least a portion of the channel region of the device.. .

06/30/16
20160190302 

Soi based finfet with strained source-drain regions


A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a sio2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (o2) throughout the layer as it is oxidized to form the insulator layer.

06/30/16
20160190299 

Semiconductor device having via hole coated in side surfaces with heat treated nitride metal and method to form the same


A semiconductor device having a via hole whose side surface is covered with nitride metals is disclosed. The via hole is formed within an insulating region that surrounds a conductive region, where both regions are made of nitride semiconductor materials.

06/30/16
20160190297 

High-electron-mobility transistors


High-electron-mobility transistors that include field plates are described. In a first implementation, a hemt includes a first and a second semiconductor material disposed to form a heterojunction at which a two-dimensional electron gas arises and source, a drain, and gate electrodes.

06/30/16
20160190286 

Surface passivation for germanium-based semiconductor structure


The present disclosure provides a method forming a semiconductor device in accordance with some embodiments. The method includes receiving a substrate having a fin protruding through the substrate, wherein the fin is formed of a first semiconductor material, exposing the substrate in an environment including hydrogen radicals, thereby passivating the protruded fin using the hydrogen radicals, and epitaxially growing a cap layer of a second semiconductor material to cover the protruded fin..

06/30/16
20160190279 

Unknown


A soi substrate is covered by a semiconductor material pattern which comprises a dividing pattern made from electrically insulating material. The dividing pattern is coated by one or more semiconductor materials.

06/30/16
20160190274 

Methods of forming contact structures for semiconductor devices and the resulting devices


A device includes a first epi semiconductor material positioned in a source/drain region of the device, the first epi semiconductor material having a first lateral width at an upper surface thereof. An extended-height epi contact structure having an upper surface and first and second side surfaces is positioned on the first epi semiconductor material, the upper surface and the first and second side surfaces collectively defining a contact length of the extended-height epi contact structure that is greater than the first lateral width.

06/30/16
20160190253 

Method and structure of making enhanced utbb fdsoi devices


An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material.

06/30/16
20160190250 

V-shaped epitaxially formed semiconductor layer


The present disclosure provides a method in accordance with some embodiments. The method includes forming a recess in a source/drain region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material.

06/30/16
20160190247 

Stressed nanowire stack for field effect transistor


A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires.

06/30/16
20160190246 

Stressed nanowire stack for field effect transistor


A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires.

06/30/16
20160190194 

Photodetector focal plane array systems and methods


A photodetector focal plane array system, comprising: a substrate comprising a plurality of photosensitive regions; and a microcomponent disposed adjacent to each of the plurality of photosensitive regions operable for receiving incident radiation and directing a photonic nanojet into the associated photosensitive region. Optionally, each of the microcomponents comprises one of a microsphere and a microcylinder.

06/30/16
20160190186 

Thin film transistor array panel and manufacturing method thereof


A thin film transistor array panel includes a substrate, an insulation layer, a first semiconductor, and a second semiconductor. The insulation layer is disposed on the substrate and includes a stepped portion.

06/30/16
20160190067 

Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method


A method of forming a semiconductor structure in a semiconductor-on-insulator (soi) substrate and semiconductor structure so formed are provided. The soi substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two.

06/30/16
20160190046 

Process for manufacturing a package for a surface-mount semiconductor device and semiconductor device


A surface-mount electronic device includes a body of semiconductor material, and a lead frame that includes a plurality of contact terminals. The plurality of contact terminals is electrically connected to the semiconductor body.

06/30/16
20160187433 

Magnetism detection device


Provided is a magnetism detection device by which it is possible to achieve a reduction in size and an increase in accuracy. A magnetism detection device includes: a magneto-impedance element; a magnetic field direction changing body; and a substrate that is formed of a semiconductor material and has an element arrangement recessed portion bottom surface and a back surface that face mutually opposite sides in a thickness direction, and a through-hole that reaches the element arrangement recessed portion bottom surface and the back surface and has a cross-sectional dimension that increases toward the main surface starting from the element arrangement recessed portion bottom surface.

06/30/16
20160187278 

Method for locating a wafer in the ingot of same


A method for determining the original position of a wafer in an ingot made from semiconductor material comprises the following steps: measuring the interstitial oxygen concentration in an area of the wafer; measuring the concentration of thermal donors formed in said area of the wafer during a previous solidification of the ingot; determining the effective time of a thermal donor formation anneal undergone by the wafer when solidification of the ingot took place, from the thermal donor concentration and the interstitial oxygen concentration; and determining the original position of the wafer in the ingot from the effective time.. .

06/30/16
20160186362 

Substrates for semiconductor devices


A method of fabricating a composite semiconductor component comprising: (i) providing a bowed substrate comprising a wafer of synthetic diamond material having a thickness td, the bowed substrate being bowed by an amount b and comprising a convex face and a concave face; (ii) growing a layer of compound semiconductor material on the convex face of the bowed substrate via a chemical vapour deposition technique at a growth temperature t to form a bowed composite semiconductor component comprising the layer of compound semiconductor material of thickness tsc on the convex face of the bowed substrate, the compound semiconductor material having a higher average thermal expansion coefficient than the synthetic diamond material between the growth temperature t and room temperature providing a thermal expansion mismatch Δtec; and (iii) cooling the bowed composite semiconductor component, wherein the layer of compound semiconductor material contracts more than the wafer of synthetic diamond material during cooling due to the thermal expansion mismatch Δtec, wherein b, td, tsc, and Δtec are selected such that the layer of compound semiconductor material contracts on cooling by an amount which off-sets bowing in the bowed substrate thus pulling the bowed composite semiconductor component into a flat configuration, the layer of compound semiconductor material having a tensile stress after cooling of less than 500 mpa.. .

06/23/16
20160181463 

Methods of treating a semiconductor layer


Methods for treating a semiconductor layer including a semiconductor material are presented. A method includes contacting at least a portion of the semiconductor material with a passivating agent.

06/23/16
20160181441 

Semiconductor device and manufacturing a semiconductor device


A semiconductor device includes a semiconductor material having a bandgap larger than 2 ev and less than 10 ev, and a contact layer in contact with the semiconductor material. The contact layer includes a metal nitride.

06/23/16
20160181426 

Methods of forming epi semiconductor material in a trench formed above a semiconductor device and the resulting devices


A device includes a gate structure having an axial length that is positioned above an active region of a semiconductor substrate and includes a first gate structure portion positioned above the active region and second gate structure portions positioned above an isolation region formed in the semiconductor substrate. An etch stop layer is positioned on the gate structure and covers sidewall surfaces of the second gate structure portions but does not cover any sidewall surfaces of the first gate structure portion.

06/23/16
20160181421 

Semiconductor devices and related fabrication methods


Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body region of semiconductor material having a first conductivity type, a source region of semiconductor material having a second conductivity type within the body region, a junction isolation region of semiconductor material having the second conductivity type, a drain region of semiconductor material having the second conductivity type, and first and second drift regions of semiconductor material having the second conductivity type.

06/23/16
20160181398 

Composite dummy gate with conformal polysilicon layer for finfet device


A method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure.

06/23/16
20160181388 

Method for manufacturing a semiconductor device comprising a metal nitride layer and semiconductor device


A method of manufacturing a semiconductor device includes introducing nitrogen into a metal layer or into a metal nitride layer, the metal layer or metal nitride layer being formed in contact with a semiconductor material. A semiconductor device includes a semiconductor material and a metal nitride layer in contact with the semiconductor material.

06/23/16
20160181352 

Capacitor structure compatible with nanowire cmos


A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure.

06/23/16
20160181296 

Image sensor pixel for high dynamic range image sensor


An image sensor pixel includes a first photodiode and a second photodiode disposed in a semiconductor material. The first photodiode has a first doped region, a first lightly doped region, and a first highly doped region.

06/23/16
20160181271 

Methods of fabricating memory device with spaced-apart semiconductor charge storage regions


Methods of fabricating semiconductor devices, such as monolithic three-dimensional nand memory string devices, include selectively forming semiconductor material charge storage regions over first material layers exposed on a sidewall of a front side opening extending through a stack comprising an alternating plurality of first and second material layers using a difference in incubation time for the semiconductor material on the first material relative to an incubation time for the semiconductor material on the second material of the stack. In other embodiments, a silicon layer is selectively deposited on silicon nitride on a surface having at least one first portion including silicon oxide and at least one second portion including silicon nitride using a difference in an incubation time for the silicon on silicon nitride relative to an incubation time for the silicon on silicon oxide..

06/23/16
20160181253 

Semiconductor structures with deep trench capacitor and methods of manufacture


An integrated finfet and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (soi) wafer.

06/23/16
20160181250 

Finfet based zram with convex channel region


Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less dram devices, sometimes referred to as zram devices. A channel is formed in a fin-type field effect transistor (finfet) that is comprised of a finned channel portion and a convex channel portion.

06/23/16
20160181248 

Cmos transistors including gate spacers of the same thickness


A dielectric material layer is deposited on gate structures of first and second semiconductor material portions. The dielectric material layer is anisotropically etched to form a first gate spacer on a first semiconductor material portion, while being protected above the second semiconductor material portion.

06/23/16
20160181174 

Integrated circuit cooling apparatus


A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a structure to remove heat from the active devices to the chip back side. The structure may include thermally conductive partial vias (tcpvs), which may include a recess with a depth, from the chip back side towards the active devices less than the first depth.

06/23/16
20160181164 

Fin formation on an insulating layer


An approach to forming fins for a semiconductor device on a silicon-on-insulator wafer. The approach includes depositing a layer of mandrel material and etching the layer of mandrel material to form a mandrel.

06/23/16
20160181117 

Integrated etch/clean for dielectric etch applications


The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations.

06/23/16
20160177158 

Suspensions for protecting semiconductor materials and methods of producing semiconductor bodies


A suspension for protecting a semiconductor material includes a polymeric matrix as carrier medium, inorganic particles, and at least one of an absorber dye or a plasticizer.. .

06/23/16
20160176702 

Integrated micro-electromechanical device of semiconductor material having a diaphragm, such as a pressure sensor and an actuator


An integrated micro-electromechanical device includes a first body of semiconductor material having a first face and a second face opposite the first surface, with the first body including a buried cavity forming a diaphragm delimited between the buried cavity and the first face. The diaphragm is monolithic with the first body.

06/16/16
20160172758 

Coupled multiband antennas


An antenna includes at least two radiating arm structures made of or limited by a conductor, superconductor or semiconductor material. The two arms are coupled through a region on first and second superconducting arms such that the combined structure forms a small antenna with broadband behavior, multiband behavior or a combination thereof.
Fractus, S.a.


06/16/16
20160172611 

Photodetectors and photovoltaics based on semiconductor nanocrystals


A composite material is described. The composite material comprises semiconductor nanocrystals, and organic molecules that passivate the surfaces of the semiconductor nanocrystals.
Invisage Technologies, Inc.


06/16/16
20160172609 

Electronic device and manufacturing semiconductor device


There is provided an electronic device including at least a first electrode, a second electrode disposed to be spaced apart from the first electrode, and an active layer disposed over the second electrode from above the first electrode and formed of an organic semiconductor material. A charge injection layer is formed between the first electrode and the active layer and between the second electrode and the active layer, and the charge injection layer is formed of an organic material having an increased electric conductivity when the charge injection layer is oxidized..
Sony Corporation


06/16/16
20160172526 

Illumination sensitive current control device


A semiconductor device that includes a layer of highly crystalline semiconductor material positioned on an insulating substrate. The semiconductor device also includes a source structure and a drain structure positioned on the layer of highly crystalline semiconductor material.
International Business Machines Corporation


06/16/16
20160172523 

High speed photodetector


A photodetector is disclosed. A first layer of the photodetector has a first semiconductor material having a first band gap energy, a first electric field, and a first doping concentration.
Tyco Electronics Svenska Holdings Ab


06/16/16
20160172498 

Finfet with epitaxial source and drain regions and dielectric isolated channel region


A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure.
International Business Machines Corporation


06/16/16
20160172479 

Methods and systems for ultra-high quality gated hybrid devices and sensors


High electron mobility leads to better device performance and today is achieved by fabricating “gated devices” within a high-mobility two-dimensional electron gas (2deg. However, the fabrication techniques used to form these devices lead to rapid degradation of the 2deg quality which then can limits the mobility of the electronic devices.

06/16/16
20160172476 

Semiconductor device and manufacturing semiconductor device


A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer and a third semiconductor layer formed on the first semiconductor layer; a fourth semiconductor layer formed on the third semiconductor layer; a gate electrode formed on the fourth semiconductor layer; and a source electrode and a drain electrode formed in contact with the second semiconductor layer. The third semiconductor layer and the fourth semiconductor layer are formed in an area immediately below the gate electrode, the fourth semiconductor layer is formed with a p-type semiconductor material, and the second semiconductor layer and the third semiconductor layer are formed with algan, and the third semiconductor layer has a lower composition ratio of al than that of the second semiconductor layer..
Transphorm Japan, Inc.


06/16/16
20160172475 

Method of forming a semiconductor structure


A semiconductor structure comprises a first layer. The first layer comprises a first iii-v semiconductor material.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/16/16
20160172472 

Techniques for forming non-planar germanium quantum well devices


Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group iv or iii-v semiconductor materials and includes a germanium fin structure.
Intel Corporation


06/16/16
20160172470 

Isolation structure of fin field effect transistor


A representative fin field effect transistor (finfet) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration.
Taiwan Semiconductor Manufacturing Company, Ltd.


06/16/16
20160172467 

Replacement metal gate including dielectric gate material


A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin.
Globalfoundries Inc.


06/16/16
20160172465 

Planar iii-v field effect transistor (fet) on dielectric layer


A method of forming a semiconductor substrate including a type iii-v semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A iii-v semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench..
International Business Machines Corporation


06/16/16
20160172462 

Fin replacement in a field-effect transistor


In a method for fabricating a field-effect transistor (fet) structure, forming a fin on a semiconductor substrate. The method further includes forming a gate on a portion of the fin and the semiconductor substrate.
International Business Machines Corporation


06/16/16
20160172459 

Active regions with compatible dielectric layers


A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material.

06/16/16
20160172458 

Schottky device and manufacture


A schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the schottky device is formed from a semiconductor material of a first conductivity type which has a barrier height adjustment layer of a second conductivity type that extends from a first major surface of the semiconductor material into the semiconductor material a distance that is less than a zero bias depletion boundary.
Semiconductor Components Industries, Llc


06/16/16
20160172369 

Forming memory using doped oxide


A method is provided for manufacturing a memory device. A strip of semiconductor material is formed having a memory region, a contact landing area region and a switch region between the memory region and the contact landing area region.
Macronix International Co., Ltd.


06/16/16
20160172362 

Cmos transistors with identical active semiconductor region shapes


A disposable semiconductor material is deposited to form disposable semiconductor material portions on semiconductor fins. A first dielectric liner is deposited and patterned to form openings above a first set of disposable semiconductor material portions on a first semiconductor fin.
International Business Machines Corporation


06/16/16
20160172275 

Package for a surface-mount semiconductor device and manufacturing method thereof


A surface-mount electronic device includes a body of semiconductor material, a lead frame, which forms a plurality of contact terminals, and a package dielectric region, which overlies the semiconductor body. Each contact terminal includes an inner portion that is overlaid by the package dielectric region and an outer portion, which projects laterally beyond the package dielectric region and is delimited by a first lateral surface.
Stmicroelectronics S.r.l.


06/16/16
20160172202 

Integrated circuits with backside metalization and production method thereof


An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated device includes a set of contact terminals for contacting the integrated circuit. At least one contact terminal of said set of contact terminals includes a contact layer of metal material being suitable to be directly coupled mechanically to an element external to the chip, and a coupling element for improving an electrical and/or mechanical coupling between the contact layer and the chip.
Stmicroelectronics S.r.l.


06/16/16
20160172199 

Nanocrystal memory and methods for forming same


A charge-storing device includes a charge-storing layer including nanocrystals. The nanocrystals are formed by a deposition technique incorporating deuterated hydrides.
Freescale Semiconductor, Inc.


06/16/16
20160172153 

Microscopy support structures


Electron microscope support structures and methods of making and using same. The support structures are generally constructed using semiconductor materials and semiconductor manufacturing processes.
Protochips, Inc.




Semiconductor Material topics: Semiconductor, Semiconductor Material, Semiconductor Device, Transistors, Surfactant, Electric Conversion, Transparent Conductive Oxide, Semiconductor Substrate, Heating Devices, Semiconductor Devices, Organic Electroluminescence, Buffer Layer, Integrated Circuit, Crystallin, Electronic Device

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