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Semiconductor Material patents



      
           
This page is updated frequently with new Semiconductor Material-related patent applications. Subscribe to the Semiconductor Material RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Material RSS RSS


Transistor with improved sigma-shaped embedded stressor and method of formation

Transistor with improved sigma-shaped embedded stressor and method of formation

Finlike structures and methods of making same

Finlike structures and methods of making same

Finlike structures and methods of making same

Charge storage apparatus and methods

Date/App# patent app List of recent Semiconductor Material-related patents
10/09/14
20140303043
 Reversible reaction sensors and assemblies patent thumbnailReversible reaction sensors and assemblies
A reversible reaction sensor provides for detecting medical, biologic or explosive airborne compounds. The sensor may be formed in semiconductor material and is activated by radiation from sources to provide sensing of particular airborne compounds optically detectable by detectors, and reversed by other radiation from a source (or removal of activating radiation) to take away such airborne compounds from the sensor.
10/09/14
20140302658
 Transistor with improved sigma-shaped embedded stressor and method of formation patent thumbnailTransistor with improved sigma-shaped embedded stressor and method of formation
A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers.
10/09/14
20140302653
 Finlike structures and methods of making same patent thumbnailFinlike structures and methods of making same
Semiconductor materials, particularly iii-v materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material.
10/09/14
20140302650
 Charge storage apparatus and methods patent thumbnailCharge storage apparatus and methods
Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric.
10/09/14
20140302649
 Semiconductor field-effect transistor, memory cell and memory device patent thumbnailSemiconductor field-effect transistor, memory cell and memory device
Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion..
10/09/14
20140301126
 Memory arrays and methods of forming electrical contacts patent thumbnailMemory arrays and methods of forming electrical contacts
Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material projections containing repeating components of an array, and with a terminal semiconductor projection of the row comprising a contact location.
10/09/14
20140299968
 Semiconductor devices and fabrication methods patent thumbnailSemiconductor devices and fabrication methods
A method of making a semiconductor device comprises : providing a semiconductor wafer having a semiconductor layer; forming a first mask layer over the semiconductor layer; forming a second mask layer over the first mask layer; annealing the second mask layer to form islands; etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars; and growing semiconductor material between the pillars and then over the tops of the pillars.. .
10/09/14
20140299885
 Substrate structures and semiconductor devices employing the same patent thumbnailSubstrate structures and semiconductor devices employing the same
A substrate structure includes a substrate, a nucleation layer on the substrate and including a group iii-v compound semiconductor material having a lattice constant that is different from that of the substrate by less than 1%, and a buffer layer on the nucleation layer and including first and second layers, wherein the first and second layers include group iii-v compound semiconductor materials having lattice constants that are greater than that of the nucleation layer by 4% or more.. .
10/09/14
20140299882
 Integrated fin and strap structure for an access transistor of a trench capacitor patent thumbnailIntegrated fin and strap structure for an access transistor of a trench capacitor
At least one dielectric pad layer is formed on a semiconductor-on-insulator (soi) substrate. A deep trench is formed in the soi substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the soi substrate.
10/09/14
20140299871
 Organic field effect transistor patent thumbnailOrganic field effect transistor
The present invention provides an electronic component or device comprising a gate electrode, a source electrode and a drain electrode, wherein said component or device further comprising an organic semiconducting (osc) material that is provided between the source and drain electrode, wherein the osc material comprises (a) a polymer represented by formula: (i), and (b) a compound of formula (ii). High quality ofets can be fabricated by the choice of a semiconductor material, which is comprised of a polymer represented by formula i and (b) a compound of formula ii..
10/09/14
20140299585
Laser cladding method
In a laser cladding method, a laser beam is emitted from a semiconductor laser to melt alloy powder for laser cladding on the surface of a hydraulic support column. The semiconductor laser is a laser functioning with semiconductor material as gain medium and lighting by means of semiconductor material transition among energy bands.
10/02/14
20140295606
Method for producing a device comprising cavities formed between a suspended element resting on insulating pads semi-buried in a substrate and this substrate
A method for producing a device including plural cavities defined between a substrate in at least one given semiconductor material and a membrane resting on a top of insulating posts projecting from the substrate, the method allowing a height of the cavity or cavities to be adapted independently of a height of the insulating posts and allowing cavities of different heights to be formed.. .
10/02/14
20140293724
Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features
Systems and methods are disclosed for providing selective threshold voltage characteristics via use of mos transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer.
10/02/14
20140291850
Method for manufacturing electronic devices
An embodiment for manufacturing electronic devices is proposed. The embodiment includes the following phases: a) forming a plurality of chips in a semiconductor material wafer including a main surface; each chip includes respective integrated electronic components and respective contact pads facing the main surface; said contact pads are electrically coupled to the integrated electronic components; b) attaching at least one conductive ribbon to at least one contact pad of each chip; c) covering the main surface of the semiconductor material wafer and the at least one conductive ribbon with a layer of plastic material; d) lapping an exposed surface of the layer of plastic material to remove a portion of the plastic material layer at least to uncover portions of the at least one conductive ribbon, and e) sectioning the semiconductor material wafer to separate the chips..
10/02/14
20140291810
Methods for growing iii-v materials on a non iii-v material substrate
The present invention relates to a method for manufacturing semiconductor materials comprising epitaxial growing of group iii-v materials, for example gallium arsenide (gaas), on for example a non iii-v group material like silicon (si) substrates (wafers), and especially to pre-processing steps providing a location stabilisation of dislocation faults in a surface layer of the non iii-v material wafer in an orientation relative to an epitaxial material growing direction during growing of the iii-v materials, wherein the location stabilised dislocation fault orientations provides a barrier against threading dislocations (stacking of faults) from being formed in the growing direction of the iii-v materials during the epitaxial growth process.. .
10/02/14
20140291809
Semiconductor substrate and a method of manufacturing the same
The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 mev from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm−3.. .
10/02/14
20140291794
Microchannel avalanche photodiode (variants)
The invention is directed to an avalanche photodiode containing a substrate and semiconductor layers with various electro-physical properties having common interfaces both between themselves and with the substrate. The avalanche photodiode may be characterized by the presence in the device of at least one matrix consisting of separate solid-state areas with enhanced conductivity surrounded by semiconductor material with the same type of conductivity.
10/02/14
20140291624
Organic light emitting device display and manufacturing method thereof
Provided is an organic light emitting display including a pixel circuit unit prepared over a substrate and comprising a plurality of thin film transistors (tfts), and an organic light emitting device or diode (oled) electrically connected to the pixel circuit unit. The pixel circuit unit and the oled are connected through a repair unit comprising a semiconductor material, in order to facilitate easy repair..
10/02/14
20140291602
Oxide memory resistor including semiconductor nanoparticles
This invention relates to memory resistors, arrays of memory resistors and a method of making memory resistors. In particular, this invention relates to memory resistors having an on state and an off state, comprising: (a) a first electrode; (b) a second electrode; (c) a dielectric layer disposed between the first and second electrodes; wherein the dielectric layer comprises nanoparticles of semiconductor material, and wherein in the on state nanoparticles form at least one conductive filament encapsulated by the dielectric layer, thereby providing a conductive pathway between the first electrode and the second electrode..
10/02/14
20140291481
Enhanced photon detection device with biased deep trench isolation
A photon detection device includes a photodiode having a planar junction disposed in a first region of semiconductor material. A deep trench isolation (dti) structure is disposed in the semiconductor material.
10/02/14
20140291152
Microreactor and method for loading a liquid
A microreactor includes: a substrate (2; 102; 202) made of semiconductor material; a plurality of wells (5; 105; 205) separated by walls (6; 106; 206) in the substrate (2; 102; 202); a dielectric structure (7; 107; 207a, 207b) coating at least the top of the walls (6; 106; 206); a cap (3; 103; 203), bonded to the substrate (2; 102; 202) and defining a chamber (10; 110; 210) above the wells (5; 105; 205); and a biasing structure (2, 8, 13; 102, 108, 113; 202, 208a, 208b, 213), configured for setting up a voltage (vb) between the substrate (2; 102; 202) and the chamber (10; 110; 210).. .
10/02/14
20140290857
Substrate processing apparatus
In a method for forming a stacked substrate of a mos (metal oxide semiconductor) structure including an oxide film serving as a gate insulating film formed on a semiconductor material layer having a film or substrate shape; and a conductive film serving as a gate electrode formed on the oxide film, a polysilane film on the semiconductor material layer is formed by coating a polysilane solution on a surface of a substrate to which the semiconductor material layer is exposed. A film containing metal ions is formed on the polysilane film by coating a metal salt solution thereon, and the polysilane film and the film containing metal ions are respectively modified into a polysiloxane film and a film containing fine metal particles to form the stacked substrate..
09/25/14
20140287656
Method for polishing a semiconductor material wafer
A method for polishing at least one semiconductor wafer while supplying a polishing agent includes performing a first simultaneous double-side polishing of the front side and the back side of the at least one semiconductor wafer with first upper and lower polishing pads, edge-notch polishing the surface of the at least one semiconductor wafer, performing a second simultaneous double-side polishing of the front side and the back side of the at least on semiconductor wafer with second upper and lower polishing pads, where the upper and lower polishing pads for the first simultaneous double-side polishing are harder and less compressible than the upper and lower polishing pads for the second simultaneous double-side polishing and performing single-side polishing of the front side of the at least one semiconductor wafer.. .
09/25/14
20140284816
Through silicon via wafer, contacts and design structures
Disclosed herein are through silicon vias (tsvs) and contacts formed on a semiconductor material, methods of manufacturing, and design structures. The method includes forming a contact hole in a dielectric material formed on a substrate.
09/25/14
20140284758
Self-aligned bipolar junction transistors
Device structures, fabrication methods, and design structures for a bipolar junction transistor. An intrinsic base is formed on the substrate, a terminal is formed on the intrinsic base, and an extrinsic base is formed that is arranged in juxtaposition with the intrinsic base on the substrate.
09/25/14
20140284731
Semiconductor device
A semiconductor device includes a substrate that is made of a semiconductor material and has a main surface formed with a recess. The semiconductor device also includes a wiring layer formed on the substrate, an electronic element housed in the recess, and a sealing resin covering at least a part of the electronic element..
09/25/14
20140284727
Integrated circuit on corrugated substrate
By forming mosfets on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production.
09/25/14
20140284723
Finfets with different fin height and epi height setting
An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions.
09/25/14
20140284721
Finfet device formation
A method includes patterning a fin on a semiconductor substrate, depositing a local trench isolation (lti) layer on the semiconductor substrate, patterning a gate stack over a channel region of the fin and over a portion of the lti layer, depositing a first capping layer over exposed portions of the lti layer, performing an etching process to remove oxide material from exposed portions of the fin, and epitaxially growing a semiconductor material from exposed portions of the fin to define active regions.. .
09/25/14
20140284669
Optoelectronic integrated device including a photodetector and a mosfet transistor, and manufacturing process thereof
An optoelectronic integrated device includes a body made of semiconductor material, which is delimited by a front surface and includes a substrate having a first type of conductivity, an epitaxial region, which has the first type of conductivity and forms the front surface, and a ring region having a second type of conductivity, which extends into the epitaxial region from the front surface, and delimiting an internal region. The optoelectronic integrated device moreover includes a mosfet including at least one body region having the second type of conductivity, which contacts the ring region and extends at least in part into the internal region from the front surface.
09/25/14
20140284538
Memory cells having storage elements that share material layers with steering elements and methods of forming the same
A memory cell is provided that includes a steering element, a metal-insulator-metal stack coupled in series with the steering element, and a conductor above the metal-insulator-metal stack. The steering element includes a diode having an n-region and a p-region.
09/25/14
20140284451
Reducing localized high electric fields in photoconductive wide bandgap semiconductors
Methods, systems, and devices are disclosed for implementing a high voltage variable resistor. In one aspect, an optical transconductance variable resistor includes a photoconductive wide bandgap semiconductor material (pwbsm) substrate, whose conduction response to changes in amplitude of incident radiation that is substantially linear throughout a non-saturation region thereof, whereby the material is operable in non-avalanche mode as a variable resistor, and first and second electrodes in contact with the material so that: a first triple junction boundary region is formed between the pwbsm substrate and the first electrode, and a second triple junction boundary region is formed between the pwbsm substrate and the second electrode, and the pwbsm substrate is located within an internal triple junction region formed between the first and second triple junction boundary regions..
09/25/14
20140283913
Molybdenum substrates for cigs photovoltaic devices
Photovoltaic (pv) devices and solution-based methods of making the same are described. The pv devices include a cigs-type absorber layer formed on a molybdenum substrate.
09/18/14
20140273519
Hydrogen-plasma process for surface preparation prior to insulator deposition on compound semiconductor materials
A method of making a semiconductor material by pretreating a semiconductor substrate having a native oxide on the substrate surface under vacuum with hydrogen plasma to remove and/or modify the native oxide. After plasma exposure, a high-k dielectric is deposited in-situ onto the substrate using atomic layer deposition.
09/18/14
20140273480
Method for producing a substrate provided with edge protection
The method for producing a substrate provided with protection of its edges has a first step which is providing a substrate having a semiconductor material base. The substrate has opposite first and second main surfaces connected by a lateral surface.
09/18/14
20140273412
Methods for wet clean of oxide layers over epitaxial layers
Methods for an oxide layer over an epitaxial layer. In an embodiment, a method includes forming an epitaxial layer of semiconductor material over a semiconductor substrate; forming an oxide layer over the epitaxial layer; applying a solution including an oxidizer to the oxide layer; and cleaning the oxide layer with a cleaning solution.
09/18/14
20140273398
Methods for forming semiconductor materials in sti trenches
A method includes annealing a silicon region in an environment including hydrogen (h2) and hydrogen chloride (hcl) as process gases. After the step of annealing, a semiconductor region is grown from a surface of the silicon region..
09/18/14
20140273390
Bipolar junction transistors, memory arrays, and methods of forming bipolar junction transistors and memory arrays
Some embodiments include methods of forming bjts. A first type doped region is formed within semiconductor material.
09/18/14
20140273380
Finfets with regrown source/drain and methods for forming the same
A method includes etching a semiconductor substrate to form a recess in the semiconductor substrate, and reacting a surface layer of the semiconductor substrate to generate a reacted layer. The surface layer of the semiconductor substrate is in the recess.
09/18/14
20140273378
Methods of fabricating integrated circuit device with fin transistors having different threshold voltages
Methods of fabricating integrated circuit device with fin transistors having different threshold voltages are provided. The methods may include forming first and second semiconductor fins including first and second semiconductor materials, respectively, and covering at least one among the first and second semiconductor fins with a mask.
09/18/14
20140273360
Faceted semiconductor nanowire
Selective epitaxy of a semiconductor material is performed on a semiconductor fin to form a semiconductor nanowire. Surfaces of the semiconductor nanowire include facets that are non-horizontal and non-vertical.
09/18/14
20140273358
Circuit structures, memory circuitry, and methods
A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material.
09/18/14
20140273342
Vth control method of multiple active layer metal oxide semiconductor tft
The present invention generally relates to tfts and methods for fabricating tfts. When multiple layers are used for the semiconductor material in a tft, a negative vth shift may result.
09/18/14
20140273340
High productivity combinatorial screening for stable metal oxide tfts
Methods for hpc techniques are applied to the processing of site-isolated regions (sir) on a substrate to form at least a portion of a tft device used in display applications. The processing may be applied to at least one of gate electrode deposition, gate electrode patterning, gate dielectric deposition, gate dielectric patterning, metal-based semiconductor material (e.g.
09/18/14
20140273186
Method and apparatus for sequencing molecules
The invention comprises a polymer sequencing chip. In one embodiment, an open nano channel is used in the surface of a semiconductor material or glass as a conduit for the polymer and the resulting monomers released from the polymer.
09/18/14
20140272459
Corrosion resistant aluminum coating on plasma chamber components
Components of semiconductor material processing chambers are disclosed, which may include a substrate and at least one corrosion-resistant coating formed on a surface thereof. The at least one corrosion-resistant coating is a high purity metal coating formed by a cold-spray technique.
09/18/14
20140272314
Coated article including broadband and omnidirectional anti-reflective transparent coating, and/or method of making the same
Certain example embodiments involve the production of a broadband and at least quasi-omnidirectional antireflective (ar) coating. The concept underlying certain example embodiments is based on well-established and applied mathematical tools, and involves the creation of nanostructures that facilitate these and/or other features.
09/18/14
20140270041
Actinide oxide structures for monitoring a radioactive environment wirelessly
Various embodiments enable wireless monitoring of a radioactive environment and related operating conditions. Structures of increasing complexity and formed at least in part from a semiconductor material based on crystalline actinide oxide-based material enable monitoring at least one operating conditions of the radioactive environment.
09/18/14
20140268895
Mixed semiconductor h-bridge power converters and methods related thereto
This disclosure provides systems, methods and apparatus for power converters and particularly power converters for wireless power transfer to remote systems such as electric vehicles. In one aspect, the disclosure provides an electronic power supply.
09/18/14
20140266291
Method, device and system for automatic detection of defects in tsv vias
A method for automatic detection of defects in tsv vias formed in a layer of semiconductor material, this detection taking place before stacking this layer with a plurality of other layers of semiconductor material for the design of a multilayer chip integrated circuit, comprising: measurement on each of said tsv vias of at least one parameter derived from an electrical characteristic of the tsv vias; detection of defects in said tsv vias according to a comparison of the parameters measured with at least one reference parameter, and calculation of said at least one reference parameter using the measured parameters. The parameter measured on each of the tsv vias comprises an oscillation frequency value derived from a capacitive characteristic of the tsv vias..
09/18/14
20140264897
Damascene conductor for a 3d device
A method of forming a conductor structure can result in vertical sidewalls. The method deposits a lining over a plurality of spaced-apart stacks of active layers.
09/18/14
20140264775
Method and system for transient voltage suppression
A transient voltage suppression (tvs) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (μm) and 22.0 μm thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer..
09/18/14
20140264763
Engineered substrates for semiconductor epitaxy and methods of fabricating the same
In a method for fabricating an engineered substrate for semiconductor epitaxy, an array of seed structures is assembled on a surface of the substrate. The seed structures in the array have substantially similar directional orientations of their crystal lattices, and are spatially separated from each other.
09/18/14
20140264613
Integrated circuits and methods for fabricating integrated circuits with active area protection
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein.
09/18/14
20140264612
Growth of epitaxial semiconductor regions with curved top surfaces
Embodiments include epitaxial source/drain regions having curved top surfaces and methods of forming the same. According to an exemplary embodiment, an epitaxial semiconductor region having a curved top surface may be formed by providing a region having a substantially planar bottom made of semiconductor material and sidewalls made of non-semiconductor material substantially perpendicular to the planar bottom, depositing a semiconductor layer having a crystalline portion on the flat bottom and amorphous portions on the sidewalls using a low pressure chemical vapor deposition process with a nitrogen carrier gas, and removing the amorphous portions from the sidewalls.
09/18/14
20140264607
Iii-v finfets on silicon substrate
A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins.
09/18/14
20140264565
Method of forming a transistor and structure therefor
In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of semiconductor material. The gate structure includes a conductor and also a gate insulator that has a first portion positioned between the gate conductor and a first portion of the semiconductor material that underlies the gate conductor.
09/18/14
20140264559
Super junction trench metal oxide semiconductor device and method of making the same
A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall.
09/18/14
20140264558
Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels
A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench.
09/18/14
20140264521
Semiconductor device
A semiconductor device in which stored data can be held even when power is not supplied and there is no limitation on the number of writing operations is provided. A semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, such as an oxide semiconductor material that is a wide-gap semiconductor.
09/18/14
20140264499
Semiconductor devices having dielectric caps on contacts and related fabrication methods
Semiconductor device structures are provided. An exemplary semiconductor device structure includes a substrate of a semiconductor material and a gate structure overlying the substrate.
09/18/14
20140264490
Replacement gate electrode with a self-aligned dielectric spacer
A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions.
09/18/14
20140264488
Methods of forming low defect replacement fins for a finfet semiconductor device and the resulting devices
One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a <100> crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the substrate fin, wherein the replacement fin structure is comprised of a semiconductor material that is different from the first semiconductor material, and a gate structure positioned around at least a portion of the replacement fin structure.. .
09/18/14
20140264482
Carbon-doped cap for a raised active semiconductor region
After formation of a disposable gate structure, a raised active semiconductor region includes a vertical stack, from bottom to top, of an electrical-dopant-doped semiconductor material portion and a carbon-doped semiconductor material portion. A planarization dielectric layer is deposited over the raised active semiconductor region, and the disposable gate structure is replaced with a replacement gate structure.
09/18/14
20140264456
Method of forming a high electron mobility semiconductor device
In an embodiment, a semiconductor device is formed by a method that includes, providing a base substrate of a first semiconductor material, and forming a layer that is one of sic or a iii-v series material on the base substrate. In a different embodiment, the base substrate may be one of silicon, porous silicon, or porous silicon with nucleation sites formed thereon, or silicon in a (111) plane..
09/18/14
20140264446
Iii-v finfets on silicon substrate
A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins.
09/18/14
20140264444
Stress-enhancing selective epitaxial deposition of embedded source and drain regions
Shallow trench isolation structures are formed within a semiconductor layer of a substrate to define an active area. The active area is recessed relative to a top surface of the shallow trench isolation structure.
09/18/14
20140264387
Fin field effect transistors having a nitride containing spacer to reduce lateral growth of epitaxially deposited semiconductor materials
A fin field effect transistor including a plurality of fin structures on a substrate, and a shared gate structure on a channel portion of the plurality of fin structures. The fin field effect transistor further includes an epitaxial semiconductor material having a first portion between adjacent fin structures in the plurality of fin structures and a second portion present on outermost sidewalls of end fin structures of the plurality of fin structures.
09/18/14
20140264385
Manufacture of wafers of wide energy gap semiconductor material for the integration of electronic and/or optical and/or optoelectronic devices
A method is provided for fabricating a wafer of semiconductor material intended for use for the integration of electronic and/or optical and/or optoelectronic devices. The method comprises: providing a starting wafer of crystalline silicon (205); on the starting wafer of crystalline silicon, epitaxially growing a buffer layer (210) consisting of a sub-stoichiometric alloy of silicon and germanium; epitaxially growing on the buffer layer a layer (225) of a semiconductor material having an energy gap greater than that of the crystalline silicon constituting the starting wafer, wherein the layer of semiconductor material having an energy gap greater than that of the crystalline silicon is grown so to have a thickness capable of constituting a substrate for the integration therein of electronic and/or optical and/or optoelectronic devices..
09/18/14
20140264376
Power switching module with reduced oscillation and method for manufacturing a power switching module circuit
A power switching module includes a three-terminal power semiconductor device designed for a rated current and a freewheeling unit. The freewheeling unit includes a pn-diode integrated in a first semiconductor material having a first band-gap, and a schottky-diode integrated in a second semiconductor material having a second band-gap that is larger than the first band-gap.
09/18/14
20140264375
Lattice mismatched heterojunction structures and devices made therefrom
Semiconductor heterojunction structures comprising lattice mismatched, single-crystalline semiconductor materials and methods of fabricating the heterojunction structures are provided. The heterojunction structures comprise at least one three-layer junction comprising two layers of single-crystalline semiconductor and a current tunneling layer sandwiched between and separating the two layers of single-crystalline semiconductor material.
09/18/14
20140264347
Transistor with embedded strain-inducing material formed in cavities based on an amorphization process and a heat treatment
When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility.
09/18/14
20140264342
Semiconductor device including a resistor and method for the formation thereof
A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure.
09/18/14
20140264341
Bipolar junction transistors with reduced epitaxial base facets effect for low parasitic collector-base capacitance
Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region.
09/18/14
20140264328
Semiconductor element
Provided is a semiconductor element including a p-type semiconductor layer that is used in combination with an n-type zno-based semiconductor layer, and that can be formed, even at relatively low temperature, to have a small thickness, high crystallinity, and surface smoothness. The semiconductor element is expected to achieve high performance when used for a large-screen display.
09/18/14
20140264279
Faceted semiconductor nanowire
Selective epitaxy of a semiconductor material is performed on a semiconductor fin to form a semiconductor nanowire. Surfaces of the semiconductor nanowire include facets that are non-horizontal and non-vertical.
09/18/14
20140264276
Non-replacement gate nanomesh field effect transistor with pad regions
A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions.
09/18/14
20140264272
Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
A photonic device comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region.
09/18/14
20140264257
Group i-iii-vi material nano-crystalline core and group i-iii-vi material nano-crystalline shell pairing
Nano-crystalline core and nano-crystalline shell pairings having group i-iii-vi material nano-crystalline cores, and methods of fabricating nano-crystalline core and nano-crystalline shell pairings having group i-iii-vi material nano-crystalline cores, are described. In an example, a semiconductor structure includes a nano-crystalline core composed of a group i-iii-vi semiconductor material.
09/18/14
20140264256
Three dimensional radioisotope battery and methods of making the same
According to one embodiment, a product includes an array of three dimensional structures, where each of the three dimensional structure includes a semiconductor material; a cavity region between each of the three dimensional structures; and a first material in contact with at least one surface of each of the three dimensional structures, where the first material is configured to provide high energy particle and/or ray emissions.. .
09/18/14
20140264184
Solution, organic semiconductor material, organic semiconductor film, electronic device and electronic equipment
Wherein r1 represents an aromatic group which may have a substituent or an alkyl group which may have a substituent; r2 and r3 independently represent an alkyl group which may have a substituent, an alkoxy group which may have a substituent, an alkylthio group which may have a substituent or a hydrogen atom, and may form a ring together; x represents an alkyl group having 4 to 6 carbon atoms, which may have a substituent; and n represents 1, 2 or 3.. .
09/18/14
20140264046
One-dimensional x-ray detector with curved readout strips
A detector for a small-angle x-ray diffraction system uses curved readout strips shaped to correspond to the expected intensity distribution of x-rays scattered by the system. This expected intensity distribution may be a series of concentric circles, and each of the strips has a shape that approximates a section of an annulus.


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Semiconductor Material topics: Semiconductor, Semiconductor Material, Semiconductor Device, Transistors, Surfactant, Electric Conversion, Transparent Conductive Oxide, Semiconductor Substrate, Heating Devices, Semiconductor Devices, Organic Electroluminescence, Buffer Layer, Integrated Circuit, Crystallin, Electronic Device

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