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Semiconductor Material patents



      
           
This page is updated frequently with new Semiconductor Material-related patent applications. Subscribe to the Semiconductor Material RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Material RSS RSS


Semiconductor device and related fabrication methods

Diamond particle mololayer heat spreaders and associated methods

Rolled-up, three-dimensional field-effect transistors and the use thereof in electronics, sensors and microfluidics

Date/App# patent app List of recent Semiconductor Material-related patents
08/21/14
20140235036
 Hot-wire method for depositing semiconductor material on a substrate and device for performing the method patent thumbnailHot-wire method for depositing semiconductor material on a substrate and device for performing the method
A hot wire device and method for depositing semiconductor material onto a substrate in a deposition chamber in which the ends of at least two filaments are clamped into a filament holder and heated by supplying current, wherein a voltage for generating an electrical current is applied in temporal succession to filaments made of differing materials so that a number of differing semiconductors corresponding to the number of consecutively heated filament materials can be consecutively deposited onto the substrate without opening the chamber.. .
08/21/14
20140235025
 Semiconductor device and related fabrication methods patent thumbnailSemiconductor device and related fabrication methods
Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first vertical drift region of semiconductor material, a second vertical drift region of semiconductor material, and a buried lateral drift region of semiconductor material that abuts the vertical drift regions.
08/21/14
20140235018
 Diamond particle mololayer heat spreaders and associated methods patent thumbnailDiamond particle mololayer heat spreaders and associated methods
Thermally regulated semiconductor devices having reduced thermally induced defects are provided, including associated methods. Such a device can include a heat spreader having a monolayer of diamond particles within a thin metal matrix and a semiconductor material thermally coupled to the heat spreader.
08/21/14
20140234977
 Rolled-up, three-dimensional field-effect transistors and the use thereof in electronics, sensors and microfluidics patent thumbnailRolled-up, three-dimensional field-effect transistors and the use thereof in electronics, sensors and microfluidics
Field-effect transistors include at least two thin layers of a semiconductor material and of an electrically conductive gate material that are rolled up together. These two layers are arranged separated from one another by one or multiple barrier layers and this rolled-up multi-layer structure is integratable as field-effect transistors in circuits and/or in microfluid systems as sensors for the detection of fluids..
08/21/14
20140231979
 Stacked assembly of a mems integrated device having a reduced thickness patent thumbnailStacked assembly of a mems integrated device having a reduced thickness
An assembly of a mems integrated device envisages: a package having a base substrate with a main surface in a horizontal plane, and a coating set on the base substrate; a first body including semiconductor material and integrating a micromechanical structure, housed within the package on the base substrate; at least one second body including semiconductor material and integrating at least one electronic component, designed to be functionally coupled to the micromechanical structure, the first body and the second body being arranged within the package stacked in a vertical direction transverse to the horizontal plane. In particular, at least one between the first body and the base substrate defines a first recess, in which the second body is housed, at least in part..
08/21/14
20140231961
 Semiconductor device and related fabrication methods patent thumbnailSemiconductor device and related fabrication methods
Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region.
08/21/14
20140231938
 Micro-electro-mechanical device with buried conductive regions, and manufacturing process thereof patent thumbnailMicro-electro-mechanical device with buried conductive regions, and manufacturing process thereof
A mems device formed by a body; a cavity, extending above the body; mobile and fixed structures extending above the cavity and physically connected to the body via anchoring regions; and electrical-connection regions, extending between the body and the anchoring regions and electrically connected to the mobile and fixed structures. The electrical-connection regions are formed by a conductive multilayer including a first semiconductor material layer, a composite layer of a binary compound of the semiconductor material and of a transition metal, and a second semiconductor material layer..
08/21/14
20140231929
 Transistors with isolation regions patent thumbnailTransistors with isolation regions
A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions.
08/21/14
20140231886
 Two-dimensional material stacked flexible photosensor patent thumbnailTwo-dimensional material stacked flexible photosensor
A flexible photosensor includes a flexible substrate, a gate on the flexible substrate, the gate including a conductive material having a planar structure, a gate insulating layer on the flexible substrate and the gate to at least cover the gate, the gate insulating layer including a non-conductive material having a planar structure, and a channel layer on the gate insulating layer, the channel layer including a semiconductor material having a planar structure.. .
08/21/14
20140231878
 Collector-up bipolar junction transistors in bicmos technology patent thumbnailCollector-up bipolar junction transistors in bicmos technology
Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate.
08/21/14
20140231877
Collector-up bipolar junction transistors in bicmos technology
Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate.
08/21/14
20140231750
Quantum well infrared photodetectors using ii-vi material systems
A quantum well infrared photodetector (qwip) and method of making is disclosed. The qwip includes a plurality of epi-layers formed into multiple periods of quantum wells, each of the quantum wells being separated by a barrier, the quantum wells and barriers being formed of ii-vi semiconductor materials.
08/21/14
20140231678
Near infrared light source in bulk silicon
A light emitting device (10) comprises a body (12) of a semiconductor material having a first face (14) and at least one other face (16). At least one pn-junction (18) in the body is located towards the first face and is configured to be driven via contacts on the body into a light emitting mode.
08/14/14
20140227871
Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region
A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions.
08/14/14
20140227862
Semiconductor nanocrystals and methods
In one embodiment, a method for forming a coating comprising a semiconductor material on at least a portion of a population of semiconductor nanocrystals comprises providing a first mixture including semiconductor nanocrystals and an aromatic solvent, introducing one or more cation precursors and one or more anion precursors into the first mixture to form a reaction mixture for forming the semiconductor material, reacting the precursors in the reaction mixture, without the addition of an acid compound, under conditions sufficient to grow a coating comprising the semiconductor material on at least a portion of an outer surface of at least a portion of the semiconductor nanocrystals, and wherein an amide compound is formed in situ in the reaction mixture prior to isolating the coated semiconductor nanocrystals. In another embodiment, method for forming a coating comprising a semiconductor material on at least a portion of a population of semiconductor nanocrystals comprises providing a first mixture including semiconductor nanocrystals and a solvent, introducing an amide compound, one or more cation precursors and one or more anion precursors into the first mixture to form a reaction mixture for forming the semiconductor material, and reacting the precursors in the reaction mixture in the presence of the amide compound, under conditions sufficient to grow a coating comprising the semiconductor material on at least a portion of an outer surface of at least a portion of the semiconductor nanocrystals.
08/14/14
20140227826
Method for treating a semiconductor
Methods for treating a semiconductor material, and for making devices containing a semiconducting material, are presented. One embodiment is a method for treating a semiconductor material that includes a chalcogenide.
08/14/14
20140226427
Memory device word line drivers and methods
Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors.
08/14/14
20140226022
Optical output photodetector
An optical output photodetector includes a substrate having a semiconductor surface and at least one optical photodetector element on the semiconductor surface. The optical photodetector element includes a plurality of integrated sensing regions which collectively provide a plurality of different absorbance spectra.
08/14/14
20140225250
Methods and systems for fabrication of low-profile mems cmos devices
A mems integrated circuit including a plurality of layers where a portion includes one or more electronic elements on a semiconductor material substrate. The circuit includes a structure of interconnection layers having a bottom layer of conductor material and a top layer of conductor material where the layers are separated by at least one layer of dielectric material.
08/14/14
20140225231
Modulating bow of thin wafers
Apparatus and methods modulate the bowing of thin wafers. According to a method, a wafer is formed of semiconductor material.
08/14/14
20140225184
Method for inducing strain in vertical semiconductor columns
A vertical metal-oxide-semiconductor (mos) transistor includes a substrate and a nano-wire over the substrate. The nano-wire comprises a semiconductor material.
08/14/14
20140225082
Organic light-emitting diode
An organic light-emitting diode including a substrate; a first electrode on the substrate; a second electrode disposed opposite to the first electrode; an emission layer disposed between the first electrode and second electrode; and a first interlayer, a first hole transport layer, a second interlayer and a second hole transport layer disposed between the first electrode and the emission layer, wherein the first interlayer, the first hole transport layer, the second interlayer, and the second hole transport layer are stacked from the first electrode in order, and wherein the first interlayer and the second interlayer each independently include an n-type semiconductor material.. .
08/14/14
20140224965
Separation of doping density and minority carrier lifetime in photoluminescence measurements on semiconductor materials
Methods are presented for separating the effects of background doping density and effective minority carrier lifetime on photoluminescence (pl) generated from semiconductor materials. In one embodiment the background doping density is measured by another technique, enabling pl measurements to be analysed in terms of effective minority carrier lifetime.
08/14/14
20140224665
Semiconductor material, optical hydrogen generating device using same, and method of producing hydrogen
A semiconductor material of the present invention is a semiconductor material including an oxynitride containing at least one element selected from the group 4 elements and group 5 elements. In the oxynitride, part of at least one selected from oxygen and nitrogen is substituted with carbon.
08/14/14
20140224312
Deposition of a high surface energy thin film layer for improved adhesion of group i-iii-vi2 solar cells
A thin film photovoltaic cell includes a light absorption layer of group i-iii-vi2 semiconductor materials and a high surface energy thin film layer that improves adhesion between the light absorption layer and an underlying electrode layer. The high surface energy thin film either replaces or is deposited on top of the back electrode to decrease the formation of voids at the back interface during absorber growth/deposition and thereby enabling a wider process window and improved cell efficiencies.
08/07/14
20140220763
Memory devices and formation methods
A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types.
08/07/14
20140220751
Methods for forming semiconductor regions in trenches
A method includes recessing a portion of a semiconductor substrate between opposite isolation regions to form a recess. After the step of recessing, the portion of the semiconductor substrate includes a top surface.
08/07/14
20140220301
Epitaxial substrate having nano-rugged surface and fabrication thereof
The invention provides an epitaxial substrate and fabrication thereof. The epitaxial substrate according to the invention includes a crystalline substrate.
08/07/14
20140217553
Template layers for heteroepitaxial deposition of iii nitride semiconductor materials using hvpe processes
Methods of depositing iii-nitride semiconductor materials on substrates include depositing a layer of iii-nitride semiconductor material on a surface of a substrate in a nucleation hvpe process stage to form a nucleation layer having a microstructure comprising at least some amorphous iii-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate.
08/07/14
20140217544
Methods of forming a transistor device on a bulk substrate and the resulting device
One illustrative method disclosed herein includes forming a trench within an isolated region of a bulk semiconductor substrate, forming a region of an insulating material in the trench and forming a semiconductor material within the trench and above the upper surface of the region of insulating material. A substrate disclosed herein includes an isolated substrate region in a bulk semiconductor substrate, a region of an insulating material that is positioned within a trench defined in the isolated substrate region and a semiconductor material positioned within the trench and above the upper surface of the region of insulating material..
08/07/14
20140217500
Semiconductor device with low on resistance and high breakdown voltage
A semiconductor device includes an epitaxial layer of semiconductor material of a first conductivity type, a body region of a second (opposite) conductivity type extending into the epitaxial layer from a main surface of the epitaxial layer, a source region of the first conductivity type disposed in the body region, and a channel region extending laterally in the body region from the source region along the main surface. A charge compensation region of the second conductivity type can be provided under the body region which extends in a direction parallel to the main surface and terminates prior to a pn-junction between the source and body regions at the main surface, and/or an additional region of the first conductivity type which has at least one peak doping concentration each of which occurs deeper in the epitaxial layer from the main surface than a peak doping concentration of the device channel region..
08/07/14
20140217499
Methods for forming semiconductor regions in trenches
A structure includes a semiconductor substrate including a first semiconductor material. A portion of the semiconductor substrate extends between insulation regions in the semiconductor substrate.
08/07/14
20140217480
Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer
Disclosed herein are various methods of forming a silicon/germanium protection layer above source/drain regions of a transistor. One method disclosed herein includes forming a plurality of recesses in a substrate proximate the gate structure, forming a semiconductor material in the recesses, forming at least one layer of silicon above the semiconductor material, and forming a cap layer comprised of silicon germanium on the layer of silicon.
08/07/14
20140217467
Methods of forming substrates comprised of different semiconductor materials and the resulting device
Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (srb) layer between the first and second layers, forming a sidewall spacer on the sidewalls of an opening in the second layer, and forming a third semiconductor material in the opening, wherein the first, second and third semiconductor materials are different. A device includes first and second layers of first and second semiconductor materials and an srb layer positioned above the first layer.
08/07/14
20140217398
Thin-film transistor device and thin-film transistor display apparatus
A thin-film transistor (tft) device comprises a gate, a source, a drain, an insulation layer and an active area. The insulation layer electrically separates the gate from the source and the drain.
08/07/14
20140217374
Organic semiconductor material
Novel compounds useful as organic semiconductor material are described. Semiconductor devices containing said organic semiconductor material are also described..
08/07/14
20140217350
Arrays of memory cells and methods of forming an array of memory cells
An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines.
08/07/14
20140217157
Removal of electronic chips and other components from printed wire boards using liquid heat media
Systems and methods for the removal of electronic chips and other components from pwbs using liquid heat media are generally described. The systems and methods described herein can be used to remove solder, electronic chips (including those in which an integrated circuit is positioned on a piece of semiconductor material, such as silicon), and/or other electronic components from pwbs.
08/07/14
20140216929
Doped zinc target
The present invention generally relates to a sputtering target comprised of zinc and a dopant. Zinc is utilized for metal oxide semiconductor materials, such as igzo, zinc oxide and zinc oxynitride.
08/07/14
20140216542
Semiconductor material surface treatment with laser
A photovoltaic device and its method of manufacture are disclosed. The device is formed by forming a window layer over a substrate, forming an absorber layer over the window layer, and annealing the absorber layer using a laser beam to remove contaminants from the surface of the absorber layer and/or to reduce the thickness of the absorber layer..
07/31/14
20140213928
Miniaturized thermal system formed with semiconductor material with medical applications
In a first embodiment, a portable, battery-operated, minimally invasive small fiber neuropathy testing and diagnostic device, microcontrolled and interfacing with wireless powering to a wireless communications device is being disclosed. Said device is constructed out of an intra-epidermal thermal stimulus consisting of an electronically heated temperature-controlled polymer covered semiconductor material 101 lowered inside the skin through a probe 108 configured with three miniaturized electrodes 109 while a nerve impulse response measurement system records and identifies nerve action potential pulses through a proprietary algorithm.
07/31/14
20140213427
Photocatalyst for the reduction of carbon dioxide
The present disclosure relates to a method and composition for forming photocatalytic capped colloidal nanocrystals which may include semiconductor nanocrystals and inorganic capping agents as photocatalysts. Photocatalytic capped colloidal nanocrystals may be deposited on a substrate and treated to form a photoactive material which may be employed in a plurality of photocatalytic energy conversion applications such as the photocatalytic reduction of carbon dioxide.
07/31/14
20140213037
Methods for fabricating integrated circuits having confined epitaxial growth regions
Methods are provided for fabricating integrated circuits. In accordance with one embodiment, the method includes forming a portion of a semiconductor substrate at least partially bounded by a confinement isolation material.
07/31/14
20140213032
Process for forming resistive switching memory cells using nano-particles
A process for forming reversible resistance-switching memory cells having resistance-switching nano-particles which provide a reduced contact area to top and bottom electrodes of the memory cells, thereby limiting a peak current. Recesses are formed in a layered semiconductor material above the bottom electrodes, and one or more coatings of nano-particles are applied.
07/31/14
20140213031
Finfets and methods for forming the same
A method includes recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin. A dummy gate is formed to cover a middle portion of the semiconductor fin.
07/31/14
20140210010
Method to form finfet/trigate devices on bulk semiconductor wafers
A method for fabricating a finfet device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate.
07/31/14
20140209978
Devices with strained source/drain structures
A device includes a substrate, a gate structure over the substrate, and source/drain (s/d) features in the substrate and interposed by the gate structure. At least one of the s/d features includes a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material over the second semiconductor material.
07/31/14
20140209977
Doped and strained flexible thin-film transistors
Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors.
07/31/14
20140209173
Photoelectric conversion device and method for producing the same
Provided is a photoelectric conversion device which includes a positive electrode, a negative electrode, a photoelectric conversion layer including poly-[n-9″-heptadecanyl-2,7-carbazole-alt-5,5-(4′,7′-di-2-thienyl-2′,1′,3′-benzothiadiazole)] as a p-type organic semiconductor material and fullerene or a fullerene derivative as an n-type organic semiconductor material; and a buffer layer, provided between the positive electrode and the photoelectric conversion layer, including moo3, in which device the proportion of the p-type organic semiconductor material in a first region being in contact with the buffer layer in the photoelectric conversion layer is higher than the proportion of the p-type organic semiconductor material in the entirety of the photoelectric conversion layer, and the proportion of the p-type organic semiconductor material in a second region on the negative electrode side than the first region in the photoelectric conversion layer is lower than the proportion of the p-type organic semiconductor material in the entirety of the photoelectric conversion layer.. .
07/31/14
20140209165
Solar cell and method of manufacturing the same
Provided is a solar cell with improved photoelectric conversion efficiency. The solar cell includes a photoelectric conversion body and first and second electrodes.
07/31/14
20140209158
Solar cell
A solar cell includes a crystalline silicon substrate, a plurality of p-type semiconductor material layers, a plurality of n-type semiconductor material layers, a plurality of first and second anode electric collection portions, at least one first electrode bus portion, a plurality of first and second cathode electric collection portions, at least one second electrode bus portion, and at least one third electrode bus portion. The first anode electric collection portions, the first electrode bus portion, the first cathode electric collection portions, the second electrode bus portion, the second anode electric collection portions, the second electrode bus portion, the second cathode electric collection portions, and the third electrode bus portion are arranged to form plural cell sub-units, such that an output voltage of the solar cell can be increased..
07/24/14
20140206261
Method for polishing a semiconductor wafer
A method for polishing at least one wafer composed of semiconductor material that has a front side and the rear side includes performing at least one first polishing step including simultaneously polishing both front and rear sides of the at least one wafer at a process temperature between an upper polishing plate and a lower polishing plate. Each of the upper polishing and lower polishing plates is covered with a polishing pad having an inner edge and an outer edge, a hardness of at least 80° shore a, a compressibility of less than 2.5%, and respective upper and lower surfaces that come into contact with the wafer being polished.
07/24/14
20140206175
Methods of forming semiconductor structures including bodies of semiconductor material
Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material.
07/24/14
20140206157
Method of forming a semiconductor structure including a vertical nanowire
A method comprises providing a semiconductor structure comprising a substrate and a nanowire above the substrate. The nanowire comprises a first semiconductor material and extends in a vertical direction of the substrate.
07/24/14
20140206141
Methods and arrangements relating to semiconductor packages including multi-memory dies
Embodiments provide a method comprising providing a multi-memory die that comprises multiple individual memory dies. Each of the individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies.
07/24/14
20140203452
Active chip on carrier or laminated chip having microelectronic element embedded therein
A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity.
07/24/14
20140203410
Die edge sealing structures and related fabrication methods
Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region.
07/24/14
20140203409
Integrated circuit structures, semiconductor structures, and semiconductor die
Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level.
07/24/14
20140203371
Finfet device formation
A method includes patterning a fin on a semiconductor substrate, depositing a local trench isolation (lti) layer on the semiconductor substrate, patterning a gate stack over a channel region of the fin and over a portion of the lti layer, depositing a first capping layer over exposed portions of the lti layer, performing an etching process to remove oxide material from exposed portions of the fin, and epitaxially growing a semiconductor material from exposed portions of the fin to define active regions.. .
07/24/14
20140203349
Method of producing a high-voltage-resistant semiconductor component having vertically conductive semiconductor body areas and a trench structure
A high-voltage-resistant semiconductor component (1) has vertically conductive semiconductor areas (17) and a trench structure (5). These vertically conductive semiconductor areas are formed from semiconductor body areas (10) of a first conductivity type and are surrounded by a trench structure (5) on the upper face (6) of the semiconductor component.
07/24/14
20140203338
Finfet device with epitaxial structure
A finfet device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure.
07/24/14
20140203334
Method for fabricating a finfet device including a stem region of a fin element
A method includes providing a substrate having a fin extending from a first (e.g., top) surface of the substrate. The fin has first region (a stem region) and a second region (an active region) each having a different composition.
07/24/14
20140203290
Wire-last integration method and structure for iii-v nanowire devices
In one aspect, a method of fabricating a nanowire fet device includes the following steps. A layer of iii-v semiconductor material is formed on an soi layer of an soi wafer.
07/24/14
20140203263
Switchable memory diodes based on ferroelectric/conuugated polymer heterostructures and/or their composites
An embodiment of the present memory cell a first layer of a chosen conductivity type, and a second layer which includes ferroelectric semiconductor material of the opposite conductivity type, the layers forming a pn junction. The first layer may be a conjugated semiconductor polymer, or may also be of ferroelectric semiconductor material.
07/24/14
20140203238
Wire-last integration method and structure for iii-v nanowire devices
In one aspect, a method of fabricating a nanowire fet device includes the following steps. A layer of iii-v semiconductor material is formed on an soi layer of an soi wafer.
07/24/14
20140203237
Self-rectified device, method for manufacturing the same, and applications of the same
A self-rectified device is provided, comprising a bottom electrode, a patterned dielectric layer with a contact hole formed on the bottom electrode, a memory formed at the bottom electrode and substantially aligned with the contact hole, and a top electrode formed on the bottom electrode and filling into the contact hole to contact with the memory, wherein the top electrode comprises a n+ type semiconductor material or a p+ type semiconductor material, and the memory and the top electrode produce a self-rectified property.. .
07/17/14
20140199807
Thin film transistors formed by organic semiconductors using a hybrid patterning regime
The present disclosure describes a process strategy for forming bottom gate/bottom contact organic tfts in cmos technology by using a hybrid deposition/patterning regime. To this end, gate electrodes, gate dielectric materials and drain and source electrodes are formed on the basis of lithography processes, while the organic semiconductor materials are provided as the last layers by using a spatially selective printing process..
07/17/14
20140199539
Composite plated film and laminated film
It is provided a steel with composite plating film providing rust prevention over a long time period and a method of manufacturing thereof. A composite plating film 24 is formed on a metal material 21.
07/17/14
20140197862
Methods for characterizing shallow semiconductor junctions
The disclosed technology generally relates to methods of characterizing semiconductor materials, and more particularly to methods of characterizing shallow semiconductor junctions. In one aspect, the method of characterizing shallow semiconductor junctions comprises providing a substrate comprising a shallow junction formed at a first main surface, where the shallow junction is formed substantially parallel to the first main surface.
07/17/14
20140197855
Multifunctional nanoscopy for imaging cells
Disclosed herein is an apparatus comprising a metal shunt and a semiconductor material in electrical contact with the metal shunt, thereby defining a semiconductor/metal interface for passing a flow of current between the semiconductor material and the metal shunt in response to an application of an electrical bias to the apparatus, wherein the semiconductor material and the metal shunt lie in different planes that are substantially parallel planes, the semiconductor/metal interface thereby being parallel to planes in which the semiconductor material and the metal shunt lie, and wherein, when under the electrical bias, the semiconductor/metal interface is configured to exhibit a change in resistance thereof in response to a perturbation. Such an apparatus can be used as a sensor and deployed as an array of sensors..
07/17/14
20140197470
Methods for forming etch stop layers, semiconductor devices having the same, and methods for fabricating semiconductor devices
A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration.
07/17/14
20140197457
Finfet device and method of fabricating same
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having isolation regions, a gate region, source and drain regions separated by the gate region, a first fin structure in a gate region.
07/17/14
20140197456
Semiconductor device and fabricating the same
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (s/d) regions separated by the gate region and a first fin structure in a gate region in the n-fet region.
07/17/14
20140197435
Optoelectronic semiconductor chip
An optoelectronic semiconductor chip includes a semiconductor body of semiconductor material, a p-contact layer and an n-contact layer. The semiconductor body includes an active layer intended for generating radiation.
07/17/14
20140197419
Techniques for forming optoelectronic devices
Embodiments relate to use of a particle accelerator beam to form thin films of material from a bulk substrate. In particular embodiments, a bulk substrate (e.g.
07/17/14
20140197410
Semiconductor structure and method for manufacturing the same
The present invention provides a method for manufacturing a semiconductor structure. The method comprises: providing an soi substrate and forming a gate structure on said soi substrate; etching a soi layer and a box layer of the soi substrate on both sides of the gate structure to form a trench exposing the box layer, said trench partially entering into the box layer; forming a stressed layer that fills up a part of said trench; forming a semiconductor layer covering the stressed layer in the trench.
07/17/14
20140197407
Semiconductor device and method for manufacturing the same
Objects are to provide a semiconductor device for high power application in which a novel semiconductor material having high productivity is used and to provide a semiconductor device having a novel structure in which a novel semiconductor material is used. The present invention is a vertical transistor and a vertical diode each of which has a stacked body of an oxide semiconductor in which a first oxide semiconductor film having crystallinity and a second oxide semiconductor film having crystallinity are stacked.


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Semiconductor Material topics: Semiconductor, Semiconductor Material, Semiconductor Device, Transistors, Surfactant, Electric Conversion, Transparent Conductive Oxide, Semiconductor Substrate, Heating Devices, Semiconductor Devices, Organic Electroluminescence, Buffer Layer, Integrated Circuit, Crystallin, Electronic Device

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