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Semiconductor Material patents

      

This page is updated frequently with new Semiconductor Material-related patent applications.




 Transmitarray unit cell for a reconfigurable antenna patent thumbnailTransmitarray unit cell for a reconfigurable antenna
Unit cell including a receive antenna, a transmit antenna, and including first and second radiation surfaces separated from each other by a separation area, a phase-shift circuit comprising switches, each having an on, respectively off, state, wherein the corresponding switch allows, respectively blocks, the flowing of a current between the first and second radiation surfaces; a ground plane; a first printed circuit board including a first surface provided with the receive antenna, and a second opposite surface provided with the ground plane; a wafer of a semiconductor material including a first surface provide with first and second radiation surfaces and wherein the switches are formed in the separation area, monolithically with the transmit antenna.. .
Commissariat À L'energie Atomique Et Aux Energies Alternatives


 Method to make a flexible thermoelectric generator device and related devices patent thumbnailMethod to make a flexible thermoelectric generator device and related devices
A method is for making a thermoelectric generator device. The method may include forming bottom contacts on a first substrate, and forming a polymer layer over the first substrate with recesses therein, the recesses being over the bottom contacts.
Stmicroelectronics S.r.l.


 Resonant cavity strained iii-v photodetector and led on silicon substrate patent thumbnailResonant cavity strained iii-v photodetector and led on silicon substrate
An optoelectronic device that includes a germanium containing buffer layer atop a silicon containing substrate, and a first distributed bragg reflector stack of iii-v semiconductor material layers on the buffer layer. The optoelectronic device further includes an active layer of iii-v semiconductor material present on the first distributed bragg reflector stack, wherein a difference in lattice dimension between the active layer and the first distributed brag reflector stack induces a strain in the active layer.
International Business Machines Corporation


 Layer system for thin-film solar cells patent thumbnailLayer system for thin-film solar cells
A layer system (1) for thin-film solar cells (100), comprising an absorber layer (4), which contains a chalcogenide compound semiconductor, and a buffer layer (5), which is arranged on the absorber layer (4), wherein the buffer layer (5) has a semiconductor material of the formula axinysz, where a is potassium (k) and/or cesium (cs), with 0.015≦x/(x+y+z)≦0.25 and 0.30≦y/(y+z)≦0.45.. .
Bengbu Design & Reserach Institute For Glass Industry


 Sensor package with cooling feature patent thumbnailSensor package with cooling feature
A sensor device includes a first substrate of semiconductor material having opposing first and second surfaces, photodetectors configured to receive light impinging on the first surface, and first contact pads each exposed at both the first and second surfaces and electrically coupled to at least one of the photodetectors. A second substrate comprises opposing first and second surfaces, electrical circuits, a second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits, and a plurality of cooling channels formed as first trenches extending into the second surface of the second substrate but not reaching the first surface of the second substrate.
Optiz, Inc.


 Metal oxide tft with improved source/drain contacts and reliability patent thumbnailMetal oxide tft with improved source/drain contacts and reliability
A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level.

 Air gap contact formation for reducing parasitic capacitance patent thumbnailAir gap contact formation for reducing parasitic capacitance
A functional gate structure is located on a surface of a semiconductor material portion and including a u-shaped gate dielectric portion and a gate conductor portion. A source region is located on one side of the functional gate structure, and a drain region is located on another side of the functional gate structure.
International Business Machines Corporation


 Semiconductor device including fin having condensed channel region patent thumbnailSemiconductor device including fin having condensed channel region
A finfet semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The semiconductor fin includes a channel region interposed between opposing source/drain regions.
International Business Machines Corporation


 Method for detecting presence and location of defects in a substrate patent thumbnailMethod for detecting presence and location of defects in a substrate
A method for detecting the presence and location of defects over a substrate is disclosed. In an embodiment, the method may include: forming a semiconductor material in a plurality of openings in a reference wafer using an epitaxial growth process; performing one or more measurements on the reference wafer to obtain a baseline signal; forming a plurality of gate stacks and stressor regions in a plurality of substrates; after forming the plurality of gate stacks, forming the semiconductor material in a plurality of openings in a batch wafer; performing the one or more measurements on the batch wafer to obtain a batch signal; comparing the batch signal to the baseline signal; and determining whether a defect in present in the plurality of substrates based on the comparison..
Taiwan Semiconductor Manufacturing Company, Ltd.


 Air gap contact formation for reducing parasitic capacitance patent thumbnailAir gap contact formation for reducing parasitic capacitance
A functional gate structure is located on a surface of a semiconductor material portion and including a u-shaped gate dielectric portion and a gate conductor portion. A source region is located on one side of the functional gate structure, and a drain region is located on another side of the functional gate structure.
International Business Machines Corporation


Semiconductor device including fin having condensed channel region

A finfet semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The semiconductor fin includes a channel region interposed between opposing source/drain regions.
International Business Machines Corporation

Methods of forming replacement fins comprised of multiple layers of different semiconductor materials

One illustrative method disclosed herein includes, among other things, individually forming alternating layers of different semiconductor materials in a substrate fin cavity so as to form a multi-layer fin above a recessed substrate fin, wherein each of the layers of different semiconductor materials is formed to a final thickness that is less than a critical thickness of the layer of different semiconductor material being formed, recessing the layer of insulating material so as to expose at least a portion of the multi-layer fin above a recessed upper surface of the layer of insulating material and forming a gate structure around at least a portion of the of exposed the multi-layer fin.. .
Globalfoundries Inc.

Method of making a sensor package with cooling feature

A sensor device includes a first substrate of semiconductor material having opposing first and second surfaces, photodetectors configured to receive light impinging on the first surface, and first contact pads each exposed at both the first and second surfaces and electrically coupled to at least one of the photodetectors. A second substrate comprises opposing first and second surfaces, electrical circuits, a second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits, and a plurality of cooling channels formed as first trenches extending into the second surface of the second substrate but not reaching the first surface of the second substrate.
Optiz, Inc.

Integrated circuit having strained fins on bulk substrate and method to fabricate same

A method includes forming a set of fins composed of a first semiconductor material. The method further heats the set of fins to condense the fins and cause growth of a layer of oxide on vertical sidewalls thereof, masking a first sub-set of the fins, forming a plurality of voids in the oxide by removing a second sub-set of fins, where each void has a three-dimensional shape and dimensions that correspond to a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set, and epitaxially growing in the voids a third sub-set of fins.
International Business Machines Corporation

Method for forming a semiconductor device and a semiconductor device

A method of forming a semiconductor device and a semiconductor device are provided. The method includes providing a wafer stack including a carrier wafer comprising graphite and a device wafer comprising a wide band-gap semiconductor material and having a first side and a second side opposite the first side, the second side being attached to the carrier wafer, defining device regions of the wafer stack, partly removing the carrier wafer so that openings are formed in the carrier wafer arranged within respective device regions and that the device wafer is supported by a residual of the carrier wafer; and further processing the device wafer while the device wafer remains supported by the residual of the carrier wafer..
Infineon Technologies Ag

Optical module having multi-mode coupler formed on semiconductor substrate

An optical module that implements an mmi device including an optical hybrid primarily made of semiconductor material is disclosed. The mmi device, which has a rectangular plane shape and includes multi-mode couplers, is mounted on a carrier.
Sumitomo Electric Industries, Ltd.

Probe card for testing integrated circuits

A probe card is adapted for testing at least one integrated circuit that integrated on a corresponding at least one die of a semiconductor material wafer. The probe card includes a board adapted for the coupling to a tester apparatus.
Stmicroelectronics S.r.l.

Combinational array gas sensor

Described is a combinational array gas sensor. In one aspect is described as an apparatus for measuring a concentration of at least one gas in air comprising an integrated semiconductor sensor unit, the semiconductor sensor unit comprising a common substrate; a plurality of semiconductor sensors disposed over the common substrate, wherein each of the plurality of semiconductor sensors senses at least one of a plurality of different gases, wherein at least one of the plurality of sensors senses the at least one gas, and wherein each of the plurality of the semiconductor sensors include two electrodes and a plurality of semiconductor ridges disposed between the two electrodes, each of the plurality of semiconductor ridges being made of a same composition of semiconductor material, thereby allowing the air with the gas disposed therein to be proximate to each of the plurality of semiconductor ridges unless inhibited by an inhibitor material; and a circuit that uses a source current to pass a measurement current through at least some of the plurality of semiconductor sensors and cause outputting of at least one measurement signal from the plurality of semiconductor sensors..
Odosodo, Inc.

Metal circuit structure

A metal circuit structure is provided. The metal circuit structure includes a substrate, a first trigger layer and a first metal circuit layer.
Industrial Technology Research Institute

Low-cadmium nanocrystalline quantum dot heterostructure

A semiconductor structure has a nano-crystalline core comprising a first semiconductor material and a nano-crystalline shell comprising a second, different semiconductor material at least partially surrounding the nano-crystalline core. Either one, but not both, of the core and shell are based on cadmium-containing semiconductor materials..
Pacific Light Technologies Corp.

Low cost magnetic resonance safe probe for temperature measurement

A temperature measurement probe (130) for use in a magnetic resonance environment, includes an elongated substrate (202), at least one highly resistive, electrically conductive traces (200, 200a, 200b, 200a′, 200b′) one printed at least one thermistor (204) disposed on the substrate and electrically connected with the trace. The thermistor is configured to be placed in thermal communication with a patient in the magnetic resonance environment.
Koninklijke Philips N.v.

Resistive random access memory device embedding tunnel insulating layer and memory array using the same and fabrication method thereof

A resistive random access memory device is provided with a tunneling insulator layer between a resistance change layer and a bottom electrode. Thus, it is possible: to raise the selection (on/off) ratio by the current of a direct tunneling induced by low voltage in the unselected cell and the current of an f-n tunneling induced by high voltage in the selected cell, to efficiently suppress the leakage current in the read operation, to make a low current operation less μa level by controlling the thickness of the tunneling insulator layer, and to be simultaneously fabricated together with circuit devices by forming the bottom electrodes (word lines) with a semiconductor material..
Gachon University Of Industry-academic Cooperation Foundation

Dual-material mandrel for epitaxial crystal growth on silicon

In one example, a method for fabricating a semiconductor device includes etching a layer of silicon to form a plurality of fins and growing layers of a semiconductor material directly on sidewalls of the plurality of fins, wherein the semiconductor material and surfaces of the sidewalls have different crystalline properties.. .
International Business Machines Corporation

Nanowire field effect transistor device having a replacement gate

A device includes a substrate, a buffer layer, a nanowire, a gate structure, and a remnant of a sacrificial layer. The buffer layer is above the substrate.
Taiwan Semiconductor Manufacturing Company Limited

Dual-material mandrel for epitaxial crystal growth on silicon

In one example, a method for fabricating a semiconductor device includes etching a layer of silicon to form a plurality of fins and growing layers of a semiconductor material directly on sidewalls of the plurality of fins, wherein the semiconductor material and surfaces of the sidewalls have different crystalline properties.. .
International Business Machines Corporation

Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates

Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate.

Methods and improving micro-led devices

A μled device comprising: a substrate and an epitaxial layer grown on the substrate and comprising a semiconductor material, wherein at least a portion of the substrate and the epitaxial layer define a mesa; an active layer within the mesa and configured, on application of an electrical current, to generate light for emission through a light emitting surface of the substrate opposite the mesa, wherein the crystal lattice structure of the substrate and the epitaxial layer is arranged such that a c-plane of the crystal lattice structure is misaligned with respect to the light emitting surface.. .
Oculus Vr, Llc

Photosensitive capacitor pixel for image sensor

A method of fabricating a pixel array includes forming a transistor network along a frontside of a semiconductor substrate. A contact element is formed for every pixel in the pixel array that is electrically coupled to a transistor within the transistor network.
Omnivision Technologies, Inc.

Method including a formation of a transistor and semiconductor structure including a first transistor and a second transistor

A method includes providing a semiconductor-on-insulator structure including a semiconductor substrate, a layer of electrically insulating material over the semiconductor substrate and a layer of semiconductor material over the layer of electrically insulating material. A first transistor is formed.
Globalfoundries Inc

Three-dimensional memory device with metal and silicide control gates

An alternating stack of insulating layers and sacrificial material layers is formed on a substrate. Separator insulator structures can be optionally formed through the alternating stack.
Sandisk Technologies, Inc.

Three-dimensional junction memory device and method reading thereof using hole current detection

Data stored in a plurality of charge storage elements in a three-dimensional memory device can be read with high speed by measuring a majority charge carrier current passing through a vertical semiconductor channel. A memory film is provided in a memory opening extending through an alternating stack of insulating layers and electrically conductive layers.
Sandisk Technologies Llc

Semiconductor device with a reduced band gap zone

A semiconductor device comprising a source region being electrically connected to a first load terminal (e) of the semiconductor device and a drift region comprising a first semiconductor material (m1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (e) and a second load terminal (c) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (e), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (e) and the second load terminal (c).the semiconductor body region isolates the source region from the drift region and includes a reduced band gap zone comprising a second semiconductor material (m2) having a second band gap that is smaller than the first band gap, wherein the reduced band gap zone is arranged in the semiconductor body region such that the reduced band gap zone and the source region exhibit, in a cross-section along a vertical direction (z), at least one of a common lateral extension range (lr) along a first lateral direction (x) and a common vertical extension range (vr) along the vertical direction (z)..
Infineon Technologies Ag

Cascode configured semiconductor component

In accordance with an embodiment, semiconductor component includes a compound semiconductor material based semiconductor device coupled to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor.
Semiconductor Components Industries, Llc

Cascode configured semiconductor component and method

In accordance with an embodiment, semiconductor component having a compound semiconductor material based semiconductor device connected to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor.
Semiconductor Components Industries, Llc

Semiconductor component and manufacture

In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead and a second lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure.
Semiconductor Components Industries, Llc

Semiconductor component and manufacture

In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a iii-n semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces.
Semiconductor Components Industries, Llc

Semiconductor component and manufacture

In accordance with an embodiment, a semiconductor component includes a support and a plurality of leads. An insulated metal substrate having a first portion and a second portion bonded to the support.
Semiconductor Components Industries, Llc

Semiconductor component and manufacture

In accordance with an embodiment, a semiconductor component is provided that includes a leadframe having a device receiving area, one or more leadframe leads and at least one insulated metal substrate bonded to a first portion of the device receiving area. A first semiconductor device is mounted to a first insulated metal substrate, the first semiconductor device configured from a iii-n semiconductor material.
Semiconductor Components Industries, Llc

Semiconductor component and manufacture

In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead, a second lead, and a third lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure.
Semiconductor Components Industries, Llc

Semiconductor component and manufacture

In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a iii-n semiconductor material is mounted to the device receiving structure.
Semiconductor Components Industries, Llc

Semiconductor component and manufacture

In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a iii-n semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces.
Semiconductor Components Industries, Llc

Compound semiconductor photonic integrated circuit with dielectric waveguide

A photonic integrated circuit (pic) is grown by epitaxy on a substrate. The pic includes at least one active element, at least one passive element, and a dielectric waveguide.
Bb Photonics Inc.

Monolithic nanophotonic device on a semiconductor substrate

A photonic light generating device is provided on a portion of a first semiconductor material. The photonic light generating device includes a second semiconductor material that has a different lattice constant than the lattice constant of the first semiconductor material and that is capable of generating and emitting light.
International Business Machines Corporation

Electronic device and manufacturing method thereof

A electronic device includes: a control electrode 11 formed on a base substrate 10; an insulation layer 21 adapted to cover the control electrode 11 and formed of an organic insulation material; an active layer 12 formed on the insulation layer 21, formed of an organic semiconductor material, and subjected to patterning; and a first electrode 13a and a second electrode 13b formed on the active layer 12, in which a chemical composition of a surface of a region a (21a) that is a region of the insulation layer 21 not formed with the active layer 12 differs from a chemical composition of a region b (21b) that is a region of the insulation layer 21 located under the active layer 12.. .
Sony Corporation

Organic transistor, compound, organic semiconductor material for non-light-emitting organic semiconductor device, material for organic transistor, coating solution for non-light-emitting organic semiconductor device, manufacturing organic transistor, manufacturing organic semiconductor film, organic semiconductor film for non-light-emitting organic semiconductor device, and synthesizing organic semiconductor material

(x represents an oxygen, sulfur, selenium, or tellurium atom or nr5; y and z each represents cr6, an oxygen, sulfur, selenium, or nitrogen atom, or nr7; a ring containing y and z is an aromatic heterocycle; any one of r1 and r2 and the aromatic heterocycle containing y and z or any one of r3 and r4 and a benzene ring may be bonded to each other through a specific divalent linking group; r1, r2, and r5 to r8 each represent a hydrogen atom, an alkyl group, an alkenyl group, an alkynyl group, an aryl group, or a heteroaryl group; r3 and r4 each represent an alkyl group, an alkenyl group, an alkynyl group, an aryl group, or heteroaryl group; and each of m and n is an integer of 0 to 2.). .

Fin structure of semiconductor device

The disclosure relates to a fin field effect transistor (finfet). An exemplary finfet comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising an upper portion comprising a first semiconductor material having a first lattice constant, wherein the upper portion comprises a first substantially vertical portion having a first width and a second substantially vertical portion having a second width less than the first width over the first substantially vertical portion; and a lower portion comprising a second semiconductor material having a second lattice constant less than the first lattice constant, wherein a top surface of the lower portion has a third width less than the first width; and a gate structure covering the second substantially vertical portion..
Taiwan Semiconductor Manufacturing Company, Ltd.

Isolated global shutter pixel storage structure

An imaging system includes a pixel array of pixel cells with each one of the pixel cells including a photodiode disposed in a semiconductor material, a global shutter gate transistor, disposed in the semiconductor material and coupled to the photodiode, a storage transistor disposed in the semiconductor material, an optical isolation structure disposed in the semiconductor material to isolate a sidewall of the storage transistor from stray light and stray charge. The optical isolation structure also includes a deep trench isolation structure that is filled with tungsten and a p+ passivation formed over an interior sidewall of the deep trench optical isolation structure.
Omnivision Technologies, Inc.

Emission source and forming the same

In various embodiments, an emission source may be provided. The emission source may also include a gain medium including a halide semiconductor material.
Nanyang Technological University

Coating solution for non-light-emitting organic semiconductor device, organic transistor, compound, organic semiconductor material for non-light-emitting organic semiconductor device, material for organic transistor, manufacturing organic transistor, and manufacturing organic semiconductor film

(in formula (2), r11 and r12 each independently represent a hydrogen atom, an alkyl group, an alkenyl group, an alkynyl group, or an alkoxy group and may have a substituent, and an aromatic portion in formula (2) may be substituted with a halogen atom.). .

Structured silicon-based thermal emitter

An optical radiation source produced from a disordered semiconductor material, such as black silicon, is provided. The optical radiation source includes a semiconductor substrate, a disordered semiconductor structure etched in the semiconductor substrate and a heating element disposed proximal to the disordered semiconductor structure and configured to heat the disordered semiconductor structure to a temperature at which the disordered semiconductor structure emits thermal infrared radiation..
Si-ware Systems

Dual mode iii-v superlattice avalanche photodiode

In one aspect, an avalanche photodiode, includes an absorber, a first superlattice structure directly connected to the absorber and configured to multiply holes and a second superlattice structure directly connected to the first superlattice structure and configured to multiply electrons. The first and second superlattice structures include iii-v semiconductor material.
Raytheon Company

Finfet structure

A finfet device includes a substrate and a fin structure having a semiconductor material layer over the substrate and recessed regions on side walls of the fin structure. The recessed regions have openings facing away from the fin structure.
Semiconductor Manufacturing International (shanghai) Corporation

Structure to enable titanium contact liner on pfet source/drain regions

A semiconductor structure is provided that includes non-metal semiconductor alloy containing contact structures for field effect transistors (fets), particularly p-type fets. Notably, each non-metal semiconductor alloy containing contact structure includes a highly doped epitaxial semiconductor material directly contacting a topmost surface of a source/drain region of the fet, a titanium liner located on the highly doped epitaxial semiconductor material, a diffusion barrier liner located on the titanium liner, and a contact metal portion located on the diffusion barrier liner..
International Business Machines Corporation

Method and structure of forming controllable unmerged epitaxial material

A method of forming a semiconductor device that includes forming a plurality of semiconductor pillars. A dielectric spacer is formed between at least one set of adjacent semiconductor pillars.
Globalfoundries Inc.



Semiconductor Material topics:
  • Semiconductor
  • Semiconductor Material
  • Semiconductor Device
  • Transistors
  • Surfactant
  • Electric Conversion
  • Transparent Conductive Oxide
  • Semiconductor Substrate
  • Heating Devices
  • Semiconductor Devices
  • Organic Electroluminescence
  • Buffer Layer
  • Integrated Circuit
  • Crystallin
  • Electronic Device


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