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Semiconductor Material patents



      
           
This page is updated frequently with new Semiconductor Material-related patent applications. Subscribe to the Semiconductor Material RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Material RSS RSS


Display device using semiconductor light emitting device

Lg Electronics

Display device using semiconductor light emitting device

Gas phase enhancement of emission color quality in solid state leds

Nanoco Technologies

Gas phase enhancement of emission color quality in solid state leds

Gas phase enhancement of emission color quality in solid state leds

Osram Opto Semiconductors

Optoelectronic semiconductor chip and method of producing an optoelectronic semiconductor chip

Date/App# patent app List of recent Semiconductor Material-related patents
02/26/15
20150056791
 Depression filling method and processing apparatus patent thumbnailnew patent Depression filling method and processing apparatus
A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor substrate is provided. The depression penetrating the insulating film is configured so as to extend to the semiconductor substrate.
Tokyo Electron Limited
02/26/15
20150056752
 Substrateless power device packages patent thumbnailnew patent Substrateless power device packages
A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer.. .
Alpha And Omega Semiconductor Incorporated
02/26/15
20150056751
 Die edge sealing structures and related fabrication methods patent thumbnailnew patent Die edge sealing structures and related fabrication methods
Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region.
02/26/15
20150055677
 Determination of the interstitial oxygen concentration in a semiconductor sample patent thumbnailnew patent Determination of the interstitial oxygen concentration in a semiconductor sample
A method for determining the oxygen concentration of a sample made from p-type semiconductor material includes a thermal treatment step to form the thermal donors, a measuring step of the charge carrier concentration of the sample at a temperature between 0 k and 100 k, a step of determining the thermal donor concentration of the sample from the charge carrier concentration and the temperature of the sample, and a step of determining the interstitial oxygen concentration from the thermal donor concentration.. .
Commissariat A L'energie Atomique Et Aux Energies Alternatives
02/26/15
20150055425
 Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory patent thumbnailnew patent Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory
Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology.
Unity Semiconductor Corporation
02/26/15
20150054538
 Electromagnetic shield for testing integrated circuits patent thumbnailnew patent Electromagnetic shield for testing integrated circuits
A probe card includes a number probes. Each probe is adapted to contact a corresponding terminal of a circuit integrated in at least one die of a semiconductor material wafer during a test phase of the wafer.
Stmicroelectronics S.r.i.
02/26/15
20150054141
 Method for forming integrated circuits on a strained semiconductor substrate patent thumbnailnew patent Method for forming integrated circuits on a strained semiconductor substrate
An electronic circuit on a strained semiconductor substrate, includes: electronic components on a first surface of a semiconductor substrate; and at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.. .
Stmicroelectronics (crolles 2) Sas
02/26/15
20150054117
 Semiconductor devices with guard rings patent thumbnailnew patent Semiconductor devices with guard rings
Semiconductor devices with guard rings are described. The semiconductor devices may be, e.g., transistors and diodes designed for high-voltage applications.
Transphorm Inc.
02/26/15
20150054084
 Silicide formation due to improved sige faceting patent thumbnailnew patent Silicide formation due to improved sige faceting
An integrated circuit includes a pmos gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in pmos source/drain region.
Texas Instruments Incorporated
02/26/15
20150054081
 Epitaxial semiconductor resistor with semiconductor  structures on same substrate patent thumbnailnew patent Epitaxial semiconductor resistor with semiconductor structures on same substrate
An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region.
International Business Machines Corporation
02/26/15
20150054057
new patent

3d memory array with improved ssl and bl contact layout


A 3d memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks.
Macronix International Co., Ltd.
02/26/15
20150054039
new patent

Finfet device with channel epitaxial region


The present disclosure relates to a fin field effect transistor (finfet) device having epitaxial enhancement structures, and an associated method of fabrication. In some embodiments, the finfet device has a semiconductor substrate having a plurality of isolation regions overlying the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.
02/26/15
20150054032
new patent

Methods for making a semiconductor device with shaped source and drain recesses and related devices


A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack..
International Business Machines Corporation
02/26/15
20150054027
new patent

Passive devices for finfet integrated circuit technologies


Device structures and design structures for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate.
International Business Machines Corporation
02/26/15
20150054008
new patent

Display device using semiconductor light emitting device


A display device according to an embodiment of the present disclosure may include a lower substrate disposed with a line electrode at an upper portion thereof, a plurality of semiconductor light emitting devices electrically connected to the line electrode to generate light and disposed to be separated from one another, and an adhesive portion including a body configured to fix the location of the lower substrate to that of the semiconductor light emitting device, and a conductor dispersed within the body to electrically connect the lower substrate to the semiconductor light emitting device, wherein the plurality of semiconductor light emitting devices form one pixel region (p) having red, green and blue semiconductor light emitting devices that emit red, green and blue light, and contain a material selected from inorganic semiconductor materials, and the adhesive portion blocks light generated from the plurality of semiconductor light emitting devices.. .
Lg Electronics Inc.
02/26/15
20150053954
new patent

Electronic device, image display apparatus, and substrate for configuring image display apparatus


An electronic device includes a first electrode and a second electrode which are separately formed on a base; a functional layer which includes an organic semiconductor material layer, and is formed on the base between the first electrode and the second electrode; a functional layer extension portion which includes the organic semiconductor material layer, and extends from the functional layer; a protective film which is formed at least on the functional layer; and an insulating layer which covers an entire surface, in which the protective film is patterned to include at least two sides which intersect with each other at an acute angle, and a vertex portion of the protective film in which the two sides intersect with each other, is chamfered.. .
Sony Corporation
02/26/15
20150053930
new patent

Atomic layer deposition of selected molecular clusters


Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance.
Stmicroelectronics, Inc.
02/26/15
20150053929
new patent

Vertical iii-v nanowire field-effect transistor using nanosphere lithography


A vertical iii-v nanowire field-effect transistor (fet). The fet includes multiple nanowires or nanopillars directly connected to a drain contact, where each of the nanopillars includes a channel of undoped iii-v semiconductor material.
Board Of Regents. The University Of Texas System
02/26/15
20150053923
new patent

Back side illumination photodiode of high quantum efficiency


A back side illumination photodiode includes a light-receiving back side surface of a semiconductor material substrate. An area of the light-receiving back side surface includes a recess.
Stmicroelectronics Sa
02/26/15
20150053921
new patent

Enhanced switch device and manufacturing method therefor


An enhanced switch device and a manufacturing method therefor. The method comprises: providing a substrate, and forming a nitride transistor structure on the substrate; fabricating and forming a dielectric layer on the nitride transistor structure, on which a gate region is defined; forming a groove structure on the gate region; depositing a p-type semiconductor material in the groove; removing the p-type semiconductor material outside the gate region on the dielectric layer; etching the dielectric layer in another position than the gate region on the dielectric layer to form two ohmic contact regions; and forming a source electrode and a drain electrode on the two ohmic contact regions, respectively..
Enkris Semiconductor, Inc.
02/26/15
20150053919
new patent

Optoelectronic semiconductor chip and producing an optoelectronic semiconductor chip


An optoelectronic semiconductor chip having a semiconductor layer sequence includes at least one active layer that generates primary radiation; a plurality of conversion layers that at least partially absorb the primary radiation and convert the primary radiation into secondary radiation of a longer wavelength than the primary radiation; and a roughened portion that extends at least into one of the conversion layers, wherein the roughened portion has a random structure, the semiconductor layer sequence is arranged on a carrier, a top side of the semiconductor layer sequence facing away from the carrier is formed by the roughened portion, the at least one active layer is located between the carrier and the conversion layers, and the roughened portion includes a plurality of recesses free of a semiconductor material.. .
Osram Opto Semiconductors Gmbh
02/26/15
20150053916
new patent

Gas phase enhancement of emission color quality in solid state leds


Light-emitting materials are made from a porous light-emitting semiconductor having quantum dots (qds) disposed within the pores. According to some embodiments, the qds have diameters that are essentially equal in size to the width of the pores.
Nanoco Technologies Ltd.
02/19/15
20150050797

Method of implantation for fragilization of substrates


The disclosure relates to a method for implantation of atomic or ionic species into a batch of substrates made of semiconductor material, in which: each substrate made of semiconductor material is positioned on a respective support of a batch implanter, each substrate comprising a thin layer of electrical insulator on its surface; and a dose of at least one ionic or atomic species is implanted over the whole surface of the substrates, through their layer of insulator, so as to form a fragilization region within each substrate and to bound there a thin layer of semiconductor material between the thin layer of insulator and the fragilization region of the substrate, the implantation method being characterized in that, during the method, each support on which a substrate is positioned has at least two separate inclinations with respect to the plane orthogonal to the direction of implantation of the species in order to improve the implantation depth of the species in the substrate. The disclosure also relates to structures of the semiconductor-on-insulator type obtained by the implementation of the implantation method..
Soitec
02/19/15
20150050787

Fully silicided gate formed according to the gate-first hkmg approach


When forming field-effect transistors, a common problem is the formation of a schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art, which may overcome this problem.
Globalfoundries Inc.
02/19/15
20150050770

Process for producing layered member and layered member


The object is to provide a photoelectric surface member which allows higher quantum efficiency. In order to achieve this object, a photoelectric surface member 1a is a crystalline layer formed by a nitride type semiconductor material, and comprises a nitride semiconductor crystal layer 10 where the direction from the first surface 101 to the second surface 102 is the negative c polar direction of the crystal, an adhesive layer 12 formed along the first surface 101 of the nitride semiconductor crystal layer 10, and a glass substrate 14 which is adhesively fixed to the adhesive layer 12 such that the adhesive layer 12 is located between the glass substrate 14 and the nitride semiconductor crystal layer 10..
Hamamatsu Photonics K.k.
02/19/15
20150049276

Thin film transistor array panel, manufacturing method thereof, and display device including the thin film transistor array panel


A thin film transistor array panel includes: gate lines; data lines insulated from and crossing the gate lines; and shorting bars disposed outside of a display area in which the gate lines cross the data lines. The shorting bars overlap portions of the data lines disposed outside of the display area.
Samsung Display Co., Ltd.
02/19/15
20150048431

Method for forming a contact on a semiconductor substrate and semiconductor device


A method for forming a contact on a semiconductor substrate includes: applying a metal to an exposed partial area of an outer side of the semiconductor substrate and/or of a layer applied to the semiconductor substrate, the partial area being surrounded by at least one edge region of an insulating layer, and the at least one edge region of the insulating layer being at least partially covered by the metal; heating the semiconductor substrate, whereby the metal which is applied to the exposed partial area reacts with at least one semiconductor material of the partial area to form a semiconductor-metal material as the end material or a further processing material of the at least one contact; and etching using an etching material having a higher etching rate for the metal than for the semiconductor-metal material.. .
Robert Bosch Gmbh
02/19/15
20150048427

Image sensor pixel cell with switched deep trench isolation structure


A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region.
Omnivision Technologies, Inc.
02/19/15
20150048414

Igbt device with buried emitter regions


An embodiment of an igbt device is integrated in a chip of semiconductor material including a substrate of a first type of conductivity, an active layer of a second type of conductivity formed on an inner surface of the substrate, a body region of the first type of conductivity extending within the active layer from a front surface thereof opposite the inner surface, a source region of the second type of conductivity extending within the body region from the front surface, a channel region being defined within the body region between the source region and the active layer, a gate element insulated from the front surface extending over the channel region, a collector terminal contacting the substrate on a rear surface thereof opposite the inner surface, an emitter terminal contacting the source region and the body region on the front surface, and a gate terminal contacting the gate element.. .
Stmicroelectronics S.r.l.
02/19/15
20150048317

Solid state imaging device


According to one embodiment, solid state imaging device includes, a semiconductor substrate and a photoelectric conversion unit formed in the semiconductor substrate or above the semiconductor substrate. Further, the photoelectric conversion unit is provided with a first photoelectric conversion unit and a second photoelectric conversion unit.
Kabushiki Kaisha Toshiba
02/19/15
20150048293

Three-dimensional semiconductor device, variable resistive memory device including the same, and manufacturing the same


A three-dimensional semiconductor device, a resistive variable memory device including the same, and a method of manufacturing the same are provided. The 3d semiconductor device includes a source formed of a first semiconductor material, a channel layer formed on the source and formed of the first semiconductor material, a lightly doped drain (ldd) region formed on the channel layer and formed of a second semiconductor material having a higher oxidation rate than that of the first semiconductor material, a drain formed on the ldd region and formed of the first semiconductor material, and a gate insulating layer formed on outer circumferences of the channel layer, the ldd region, and the drain..
Sk Hynix Inc.
02/12/15
20150044846

Source and drain doping profile control employing carbon-doped semiconductor material


Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces.
International Business Machines Corporation
02/12/15
20150044843

Semiconductor fin on local oxide


A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate.
International Business Machines Corporation
02/12/15
20150044834

Transistors, semiconductor constructions, and methods of forming semiconductor constructions


Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion.
Micron Technology, Inc.
02/12/15
20150044830

Hard mask for source/drain epitaxy control


An integrated circuit is formed to include a first polarity mos transistor and a second, opposite, polarity mos transistor. A hard mask of silicon-doped boron nitride (sixbn) with 1 atomic percent to 30 atomic percent silicon is formed over the first polarity mos transistor and the second polarity mos transistor.
Texas Instruments Incorporated
02/12/15
20150044816

Method of manufacturing resistance change layer using irradiation of electron beam and resistive random access memory device using the same


Methods of manufacturing a resistance change layer and a resistive random access memory device are provided. The method of manufacturing a resistance change layer includes forming a preliminary resistance change layer including an oxide semiconductor material on a substrate and irradiating the preliminary resistance change layer with an electron beam to a predetermined depth.
Industry-university Cooperation Foundation Hanyang University
02/12/15
20150044806

Method for preparing semiconductor nanocrystals


A method for preparing semiconductor nanocrystals including a core and an overcoating layer is disclosed. According to one aspect of the invention, the method comprises preparing more than one batch of cores comprising a first semiconductor material and having a maximum emission peak within a predetermined spectral region, wherein each batch of cores is characterized by a first excitonic absorption peak at an absorption wavelength and a maximum emission peak at an emission wavelength; selecting a batch of cores from the batches prepared wherein the selected batch is characterized by a difference between the absorption wavelength and the emission wavelength that is less than or equal to 13; and overcoating the cores of the selected batch with a layer comprising a second semiconductor material..
Qd Vision, Inc.
02/12/15
20150043607

Distributed feedback (dfb) laser with slab waveguide


A distributed feedback (dfb) laser includes a substrate of a compound semiconductor material, and quantum-well (qw) active layer(s) overlying the substrate. A p-doped cladding layer including the compound semiconductor material is on one side of the active layer and an n-doped cladding layer is on the other side.
Gooch And Housego Plc
02/12/15
20150041988

Ultra high performance interposer


An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer.
Invensas Corporation
02/12/15
20150041921

Increasing ion/ioff ratio in finfets and nano-wires


Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes.
Synopsys, Inc.
02/12/15
20150041897

Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet


After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin.
International Business Machines Corporation
02/12/15
20150041853

Bonded epitaxial oxide structures for compound semiconductor on silicon substrates


A structure including a compound semiconductor layer epitaxially grown on an epitaxial oxide layer is provided wherein the lattice constant of the epitaxial oxide layer may be different from the semiconductor substrate on which it is grown. Fabrication of one structure includes growing a graded semiconductor layer stack to engineer a desired lattice parameter on a semiconductor substrate or layer.
International Business Machines Corporation
02/12/15
20150041724

Substituent-eliminable diketopyrrolopyrrole derivative, organic semiconductor material precursor solution, organic semiconductor material, and organic semiconductor material film


In the formula (i), r represents a substituted or unsubstituted alkyl group; x represents a substituted or unsubstituted alkyl group; ar represents a substituted or unsubstituted aromatic group or a substituted or unsubstituted heteroaromatic group; and n represents an integer of from 1 to 4.. .
02/12/15
20150041657

Multiple beam transmission interferometric testing methods for the development and evaluation of subwavelength sized features within semiconductor and anisotropic devices


Improved methods and systems for inspection imaging for holographic or interferometric semiconductor test and evaluation through all phases of device development and manufacture. Specifically, systems and methods are disclosed for extending the range of optical holographic interferometric inspection for testing and evaluating microelectronic devices and determining the interplay of electromagnetic signals and dynamic stresses to the semiconductor material are provided in which an enhanced imaging method provides continuous and varying the magnification of the optical holographic interferometric images over a plurality of interleaved optical pathways and imaging devices.
Attofemto, Inc.
02/12/15
20150040971

Fabrication of solar cells with electrically conductive polyimide adhesive


The present disclosure provides a method of manufacturing a solar cell including: providing a first substrate and a second substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell including a top subcell and a bottom subcell; forming a back metal contact over the bottom subcell; applying a conductive polyimide adhesive to the second substrate; attaching the second substrate on top of the back metal contact; and removing the first substrate to expose the surface of the top subcell.. .
Emcore Solar Power, Inc.
02/12/15
20150040397

Process for manufacturing a nozzle plate and fluid-ejection device provided with the nozzle plate


A nozzle plate for a fluid-ejection device, comprising: a first substrate made of semiconductor material, having a first side and a second side; a structural layer extending on the first side of the first substrate, the structural layer having a first side and a second side, the second side of the structural layer facing the first side of the first substrate; at least one first through hole, having an inner surface, extending through the structural layer, the first through hole having an inlet section corresponding to the first side of the structural layer and an outlet section corresponding to the second side of the structural layer; a narrowing element adjacent to the surface of the first through hole, and including a tapered portion such that the inlet section of the first through hole has an area larger than a respective area of the outlet section of the first through hole.. .
Stmicroelectronics, Inc.
02/05/15
20150037964

Method for manufacturing a marked single-crystalline substrate and semiconductor device with marking


A method for manufacturing a marked single-crystalline substrate comprises providing a single-crystalline substrate comprising a first material, the single-crystalline substrate having a surface area; forming a marking structure on the surface area of the single-crystalline substrate, wherein the marking structure comprises a first semiconductor material; and depositing a semiconductor layer on the marking structure and at least partially on the surface area of the single-crystalline substrate, wherein the semiconductor layer comprises the second semiconductor material, and wherein the marking structure is buried under the second semiconductor material.. .
Infineon Technologies Ag
02/05/15
20150037939

Rare-earth oxide isolated semiconductor fin


A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer.
International Business Machines Corporation
02/05/15
20150037685

Battery cell and making battery cell


Embodiments provide a battery cell including a porous membrane, the porous membrane including transformed semiconductor material. The porous membrane separates a first half-cell from a second half-cell of the battery cell.
Infineon Technologies Ag
02/05/15
20150035085

Doped high-k dielectrics and methods for forming the same


Embodiments provided herein describe high-k dielectric layers and methods for forming high-k dielectric layers. A substrate is provided.
Intermolecular Inc.
02/05/15
20150035075

Gate strain induced work function engineering


A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion.
International Business Machines Corporation
02/05/15
20150035027

Semiconductor component with a window opening as an inerface for ambient coupling


A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material..
X-fab Semiconductor Foundries Ag
02/05/15
20150035012

Methods and bipolar junction transistors and resistors


Methods and apparatus for bipolar junction transistors (bjts) are disclosed. A bjt comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a sige layer on the p+ region.
Taiwan Semiconductor Manufacturing Company, Ltd.
02/05/15
20150035008

Finfet devices including high mobility channel materials with materials of graded composition in recessed source/drain regions and methods of forming the same


A finfet device can include a high mobility semiconductor material in a fin structure that can provide a channel region for the finfet device. A source/drain recess can be adjacent to the fin structure and a graded composition epi-grown semiconductor alloy material, that includes a component of the high mobility semiconductor material, can be located in the source/drain recess..
Samsung Electronics Co., Ltd.
02/05/15
20150034967

Semiconductor device


A semiconductor device including a high resistance layer formed on a substrate, the high resistance layer being formed with a semiconductor material doped with as impurity element that makes the semiconductor material highly resistant; a multilayer intermediate layer formed on the high resistance layer; an electron transit layer formed with a semiconductor material on the multilayer intermediate layer; and an electron supply layer formed with a semiconductor material on the electron transit layer, wherein the multilayer intermediate layer is formed with a multilayer film in which a gan layer and an aln layer are alternately laminated.. .
Fujitsu Limited
02/05/15
20150034958

Hemt-compatible lateral rectifier structure


The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal.
Taiwan Semiconductor Manufacturing Co., Ltd.
02/05/15
20150034957

Normally-off enhancement-mode misfet


The present disclosure relates to an enhancement mode misfet device. In some embodiments, the misfet device has an electron supply layer located on top of a layer of semiconductor material.
Taiwan Semiconductor Manufacturing Co., Ltd.
02/05/15
20150034951

Display device and manufacturing method thereof


Disclosed is a display device including a transistor showing extremely low off current. In order to reduce the off current, a semiconductor material whose band gap is greater than that of a silicon semiconductor is used for forming a transistor, and the concentration of an impurity which serves as a carrier donor of the semiconductor material is reduced.
Semiconductor Energy Laboratory Co., Ltd.
02/05/15
20150034943

Thin film transistor array substrate


The present invention discloses a thin film transistor array substrate comprising a plurality of thin film transistors, with each one thereof including a gate electrode, a gate insulation layer, an amorphous-oxide semiconductor layer and a pair of a source electrode and a drain electrode. The amorphous-oxide semiconductor layer comprises an amorphous-oxide semiconductor material having a-igzo.
Hannstar Display Corp.
02/05/15
20150034941

Integrated circuits having finfet semiconductor devices and methods of fabricating the same to resist sub-fin current leakage


Integrated circuits that have a finfet and methods of fabricating the integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit having a finfet includes providing a substrate comprising fins.
Globalfoundries, Inc.
02/05/15
20150034933

Organic light emitting diode display having thin film transistor substrate using oxide semiconductor and manufacturing the same


Provided is a thin film transistor having an oxide semiconductor material for an organic light emitting diode display and a method for manufacturing the same. The organic light emitting diode display comprises: a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; a semiconductor layer formed on the gate insulating layer to overlap with the gate electrode, and including a channel area and source and drain areas which extend from the channel area to both outsides, respectively and are conductorized; an etch stopper formed on the channel area and exposing the source area and the drain area; a source electrode contacting portions of the exposed source electrode; and a drain electrode contacting portions of the exposed drain electrode..
Lg Display Co., Ltd.
02/05/15
20150034153

Compound photovoltaic cell


A compound photovoltaic cell includes a substrate, a first cell made of a first semiconductor material and formed on the substrate, a tunnel layer, and a second cell made of a second semiconductor material lattice mismatched with a material of the substrate, connected to the first cell via the tunnel layer, and disposed on an incident side with respect to the first cell, wherein band gaps of the first and the second cells become smaller from an incident side to a back side, and wherein the tunnel layer includes a p-type layer disposed on the incident side and a n-type layer disposed on the back side, the p-type layer being a p+-type (al)gainas layer, the n-type layer being an n+-type inp layer, an n+-type gainp layer having a tensile strain with respect to inp or n+-type ga(in)psb layer having a tensile strain with respect to inp.. .
Ricoh Company, Ltd.
02/05/15
20150034140

Thermoelectric element


A thermoelectric element having high thermal resistance and requiring less semiconductor material than a conventional thermoelectric element with comparable performance comprises a substrate having a substrate front side and a substrate rear side opposite the substrate front side, a first contact, applied as a layer to the substrate front side, a second contact, applied as a layer to the substrate front side, a cut-off between the first and second contact which thermally and electrically separates the first and second contact from one another, and a thermoelectrically active layer having a top side and a bottom side, which are connected to one another by lateral delimiting surfaces, wherein the thermoelectrically active layer is arranged in the cut-off in such a way that the bottom side is on the substrate front side, and one of the lateral delimiting surfaces is against the first contact and one of the lateral delimiting surfaces is against the second contact. The invention further relates to a method for producing the thermoelectric element..
O-flexx Technologies Gmbh
01/29/15
20150033201

Systems and methods for fabricating semiconductor device structures


Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining raw measurement data for a wafer of semiconductor material from a metrology tool and adjusting a measurement model utilized by a metrology tool based at least in part on the raw measurement data and a value for a design parameter.
Globalfoundries, Inc.
01/29/15
20150031179

Method of forming a semiconductor structure including silicided and non-silicided circuit elements


A method includes providing a semiconductor structure including at least one first circuit element including a first semiconductor material and at least one second circuit element including a second semiconductor material. A dielectric layer having an intrinsic stress is formed that includes a first portion over the at least one first circuit element and a second portion over the at least one second circuit element.
Globalfoundries Inc.
01/29/15
20150028674

Four-terminal circuit element with photonic core


A four-terminal circuit element is described that includes a photonic core inside of the circuit element that uses a wide bandgap semiconductor material that exhibits photoconductivity and allows current flow through the material in response to the light that is incident on the wide bandgap material. The four-terminal circuit element can be configured based on various hardware structures using a single piece or multiple pieces or layers of a wide bandgap semiconductor material to achieve various designed electrical properties such as high switching voltages by using the photoconductive feature beyond the breakdown voltages of semiconductor devices or circuits operated based on electrical bias or control designs.
Lawrence Livermore National Security, Llc
01/29/15
20150028479

Semiconductor devices with close-packed via structures having in-plane routing and making same


The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (fs) and an opposite second side (bs). There is at least one conductive wafer-through via (v) comprising metal, and at least one recess (rdl) provided in the first side of the substrate and in the semiconductor material of the substrate.
Silex Microsystems Ab
01/29/15
20150028460

Semiconductor component and manufacture


A common mode filter monolithically integrated with a protection device. In accordance with an embodiment a semiconductor material having a resistivity of at least 5 ohm-centimeters is provided.
Semiconductor Components Industries, Llc
01/29/15
20150028441

Semiconductor element with solder resist layer


A semiconductor element includes a cdte-based semiconductor material and a number of connection points of the semiconductor element to connect to electronic components. In at least one embodiment, the connection points are provided with a special solder resist layer including a mixture ab of at least two metals with different coefficients of expansion.
Siemens Aktiengesellschaft
01/29/15
20150028426

Buried sige oxide finfet scheme for device enhancement


The present disclosure relates to a fin field effect transistor (finfet) device having a buried silicon germanium oxide structure configured to enhance performance of the finfet device. In some embodiments, the finfet device has a three-dimensional fin of semiconductor material protruding from a substrate at a position located between first and second isolation regions.
Taiwan Semiconductor Manufacturing Co., Ltd.
01/29/15
20150028419

Fin field effect transistor with dielectric isolation and anchored stressor elements


A first fin field effect transistor and a second fin field effect transistor are formed on an insulator layer overlying a semiconductor material layer. A first pair of trenches is formed through the insulator layer in regions in which a source region and a drain region of the first fin field effect transistor is to be formed.
International Business Machines Corporation
01/29/15
20150028414

Insulated gate semiconductor device structure


In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers.
Semiconductor Components Industries, Llc
01/29/15
20150028347

Light emitting diodes and associated methods of manufacturing


Light emitting diodes and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode (led) includes a substrate, a semiconductor material carried by the substrate, and an active region proximate to the semiconductor material.
Micron Technology, Inc.
01/29/15
20150028288

Synthesis of cdse/zns core/shell semiconductor nanowires


The present disclosure provides systems, processes, articles of manufacture, and compositions that relate to core/shell semiconductor nanowires. Specifically, the disclosure provides a novel semiconductor material, cdse/zns core/shell nanowires, as well as a method of preparation thereof.
Us Nano Llc


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Semiconductor Material topics: Semiconductor, Semiconductor Material, Semiconductor Device, Transistors, Surfactant, Electric Conversion, Transparent Conductive Oxide, Semiconductor Substrate, Heating Devices, Semiconductor Devices, Organic Electroluminescence, Buffer Layer, Integrated Circuit, Crystallin, Electronic Device

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