Popular terms

Semiconductor Material topics
Semiconductor
Semiconductor Material
Semiconductor Device
Transistors
Surfactant
Electric Conversion
Transparent Conductive Oxide
Semiconductor Substrate
Heating Devices
Semiconductor Devices
Organic Electroluminescence
Buffer Layer
Integrated Circuit
Crystallin
Electronic Device

Follow us on Twitter
twitter icon@FreshPatents

Web & Computing
Cloud Computing
Ecommerce
Search patents
Smartphone patents
Social Media patents
Video patents
Website patents
Web Server
Android patents
Copyright patents
Database patents
Programming patents
Wearable Computing
Webcam patents

Web Companies
Apple patents
Google patents
Adobe patents
Ebay patents
Oracle patents
Yahoo patents

[SEARCH]

Semiconductor Material patents

      

This page is updated frequently with new Semiconductor Material-related patent applications.




Date/App# patent app List of recent Semiconductor Material-related patents
08/18/16
20160242294 
 Electronic device patent thumbnailnew patent Electronic device
The present disclosure provides an electronic device suitable for miniaturization. The present electronic device includes: a substrate (1), having a main surface (111) and a back surface (112) facing opposite sides with each other in a thickness direction, wherein the substrate comprises a semiconductor material; an electronic component (8), which is disposed over the substrate (1); and a conductive layer (3), which is electrically connected with the electronic component (8); wherein a recess for disposing the component (14) and a through recess (17) are formed in the substrate, in which recess for disposing the component (14) is recessed from the main surface (111), and the through recess (17) penetrates from the recess for disposing the component (14) to the back surface (112); the electronic component (8) is disposed over the recess for disposing the component (14); a metal-filled portion (4) is formed in the through recess (17), wherein the metal-filled portion blocks at least the bottom of the through recess (17) and is filled with a metal material; and the conductive layer (3) is formed at least from the through recess (17) to the back surface (112)..
Rohm Co., Ltd.


08/18/16
20160240804 
 Coating material for forming semiconductors, semiconductor thin film, thin film solar cell and  manufacturing thin film solar cell patent thumbnailnew patent Coating material for forming semiconductors, semiconductor thin film, thin film solar cell and manufacturing thin film solar cell
The present invention aims to provide a coating liquid for forming a semiconductor which facilitates large-area production of a semiconductor that is useful as a semiconductor material of a solar cell with high conversion efficiency and small variation in the conversion efficiency, and enables control of the film thickness. The present invention also aims to provide a semiconductor thin film produced from the coating liquid for forming a semiconductor, a thin film solar cell, and a method for producing the thin film solar cell.
Sekisui Chemical Co., Ltd.


08/18/16
20160240789 
 Perylene-based semiconductors patent thumbnailnew patent Perylene-based semiconductors
The present invention relates to new semiconductor materials prepared from perylene-based compounds. Such compounds can exhibit high carrier mobility and/or good current modulation characteristics.
Polyera Corporation


08/18/16
20160240724 
 Method for producing a solar cell patent thumbnailnew patent Method for producing a solar cell
The invention relates to a method for producing a solar cell (1) from crystalline semiconductor material. In a first surface (3a) of a semiconductor substrate (3), a first doping area (5) is formed by thermally diffusing a first dopant and in the second surface (3b) of the semiconductor substrate, a second doping area (7) is formed by implanting ions and thermally implanting a second dopant..
Ion Beam Services


08/18/16
20160240723 
 Anneal techniques for chalcogenide semiconductors patent thumbnailnew patent Anneal techniques for chalcogenide semiconductors
Techniques for precisely controlling the composition of volatile components (such as sulfur (s), selenium (se), and tin (sn)) of chalcogenide semiconductors in real-time—during production of the material are provided. In one aspect, a method for forming a chalcogenide semiconductor material includes providing a s source(s) and a se source(s); heating the s source(s) to form a s-containing vapor; heating the se source(s) to form a se-containing vapor; passing a carrier gas first through the s-containing vapor and then through the se-containing vapor, wherein the s-containing vapor and the se-containing vapor are transported via the carrier gas to a sample; and contacting the s-containing vapor and the se-containing vapor with the sample under conditions sufficient to form the chalcogenide semiconductor material.
International Business Machines Corporation


08/18/16
20160240707 
 Photoconducting layered material arrangement,  fabricating the photoconducting layered material arrangement, and use of photoconducting layered material arrangement patent thumbnailnew patent Photoconducting layered material arrangement, fabricating the photoconducting layered material arrangement, and use of photoconducting layered material arrangement
A photoconducting layered material arrangement for producing or detecting high frequency radiation includes a semiconductor material including an alloy comprised of ingaas, ingaassb, or gasb, with an admixture of al, which material is applied to a suitable support substrate in a manner such that the lattices are suitably adjusted, wherewith the semiconductor material comprised of ingaalas, ingaalassb, or gaalsb has a band gap of more than 1 ev, as a consequence of the admixed proportion of al. The proportion x of al in the semiconductor material inyga1−y−xalxas is between x=0.2 and x=0.35, wherewith the proportion y of in may be between 0.5 and 0.55.
Technische Universität Darmstadt


08/18/16
20160240674 
 Method for manufacturing semiconductor device with recess, epitaxial growth and diffusion patent thumbnailnew patent Method for manufacturing semiconductor device with recess, epitaxial growth and diffusion
A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate..
Sony Corporation


08/18/16
20160240618 
 Depression filling method and processing apparatus patent thumbnailnew patent Depression filling method and processing apparatus
A method of filling a depression of a workpiece is provided. The depression passes through an insulating film and extends up to an inside of a semiconductor substrate.
Tokyo Electron Limited


08/18/16
20160240536 
 Structure and formation  finfet device patent thumbnailnew patent Structure and formation finfet device
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack and a second gate stack over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


08/18/16
20160240532 
 Gate-all-around semiconductor device and  fabricating the same patent thumbnailnew patent Gate-all-around semiconductor device and fabricating the same
The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between sti regions at least one suspended nanostructure anchored by a source region and a drain region.
Imec Vzw


08/18/16
20160240379 
new patent

Depression filling method and processing apparatus


A method of filling a depression of a workpiece is provided. The method includes forming a first thin film made of a semiconductor material substantially not containing an impurity along a wall surface which defines the depression, forming an epitaxial region conforming to crystals of the semiconductor substrate from the semiconductor material of the first thin film moved toward a bottom of the depression by annealing, etching the first thin film remaining on the wall surface, performing gas phase doping upon the epitaxial region, forming a second thin film made of a semiconductor material substantially not containing an impurity along the wall surface, further forming an epitaxial region from the semiconductor material of the second thin film moved toward the bottom of the depression by annealing, and performing gas phase doping upon the second thin film remaining on the wall surface and the epitaxial region..
Tokyo Electron Limited


08/18/16
20160238795 
new patent

Loss compensated optical switching


Loss compensated optical switching includes an optical crossbar switch and a wafer bonded semiconductor amplifier (soa). The optical crossbar switch has a plurality of input ports and a plurality of output ports and is on a substrate of a first semiconductor material.
Hewlett-packard Development Company, L.p.


08/18/16
20160237561 
new patent

Anneal techniques for chalcogenide semiconductors


Techniques for precisely controlling the composition of volatile components (such as sulfur (s), selenium (se), and tin (sn)) of chalcogenide semiconductors in real-time—during production of the material are provided. In one aspect, a method for forming a chalcogenide semiconductor material includes providing a s source(s) and a se source(s); heating the s source(s) to form a s-containing vapor; heating the se source(s) to form a se-containing vapor; passing a carrier gas first through the s-containing vapor and then through the se-containing vapor, wherein the s-containing vapor and the se-containing vapor are transported via the carrier gas to a sample; and contacting the s-containing vapor and the se-containing vapor with the sample under conditions sufficient to form the chalcogenide semiconductor material.
International Business Machines Corporation


08/11/16
20160233372 

Method for producing a solar cell involving doping by ion implantation and depositing an outdiffusion barrier


The invention relates to a method for producing a solar cell (1) from crystalline semiconductor material, wherein a first doping region (5) is formed by means of ion implantation (s2) of a first dopant in a first surface (3a) of a semiconductor substrate (3), and a second doping region (7) is formed by means of ion implantation (s3) or thermal indiffusion of a second dopant in the second surface (3b) of the semiconductor substrate. After the doping of the second surface, a cap (9b) acting as an outdiffusion barrier for the second dopant is applied and an annealing step (s4) is subsequently carried out..
International Solar Energy Research Center Konstan Z E.v.


08/11/16
20160233336 

Strained channel region transistors employing source and drain stressors and systems including the same


Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor.
Intel Corporation


08/11/16
20160233327 

Group iii-v semiconductor device with strain-relieving layers


According to one exemplary embodiment, a group iii-v semiconductor device includes at least one transition layer situated over a substrate. The group iii-v semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer.
Infineon Technologies Americas Corp.


08/11/16
20160233321 

Finfet device and fabricating same


Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (finfets). An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/11/16
20160233316 

Method of manufacturing a spacer supported lateral channel fet


A semiconductor device is manufactured by forming a plurality of trenches extending into a semiconductor material from a first main surface of the semiconductor material to form mesas of semiconductor material between the trenches. A trench fill material is disposed in the trenches, the trench fill material extending above the first main surface of the semiconductor material.
Infineon Technologies Austria Ag


08/11/16
20160233300 

System for glass sheet semiconductor coating and resultant product


A system (20) for coating semiconductor material on glass sheets is performed by conveying the glass sheets vertically suspended at upper extremities thereof through a system (20) having a housing (22) including a vacuum chamber (24). The glass sheets are conveyed on shuttles (42) through an entry load lock station (26) into the housing vacuum chamber (24), through a heating station (30) and at least one deposition station (32, 34) in the housing (22), and to a cooling station 36 prior to exiting of the system through an exit load lock station (28).
Willard & Kelsey Solar Group, Llc


08/11/16
20160233245 

Formation of strained fins in a finfet device


In an aspect of the present invention, a field-effect transistor (fet) structure is formed. The fet structure comprises a plurality of fins formed on a semiconductor substrate, wherein the plurality of fins includes a set of fins that include a base portion that is comprised of relaxed silicon-germanium (sige) and an upper portion that is comprised of semiconductor material.
International Business Machines Corporation


08/11/16
20160233242 

Cmos structure on ssoi wafer


A method of forming fins in a complimentary-metal-oxide-semiconductor (cmos) device that includes a p-type field effect transistor device (pfet) and an n-type field effect transistor (nfet) device and a cmos device are described. The method includes forming a strained silicon-on-insulator (ssoi) layer in both a pfet region and an nfet region, etching the strained silicon layer, the insulator, and a portion of the bulk substrate in only the pfet region to expose the bulk substrate, epitaxially growing silicon (si) from the bulk substrate in only the pfet region, and epitaxially growing additional semiconductor material on the si in only the pfet region.
International Business Machines Corporation


08/11/16
20160233240 

Cmos structure on ssoi wafer


A method of forming fins in a complimentary-metal-oxide-semiconductor (cmos) device that includes a p-type field effect transistor device (pfet) and an n-type field effect transistor (nfet) device and a cmos device are described. The method includes forming a strained silicon-on-insulator (ssoi) layer in both a pfet region and an nfet region, etching the strained silicon layer, the insulator, and a portion of the bulk substrate in only the pfet region to expose the bulk substrate, epitaxially growing silicon (si) from the bulk substrate in only the pfet region, and epitaxially growing additional semiconductor material on the si in only the pfet region.
International Business Machines Corporation


08/11/16
20160233227 

Enhanced channel mobility three-dimensional memory structure and making thereof


A stack including an alternating plurality of first material layers and second material layers is provided. A memory opening is formed and at least a contiguous semiconductor material portion including a semiconductor channel is formed therein.
Sandisk Technologies Inc.


08/11/16
20160233225 

Drain select gate formation methods and apparatus


Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (sgd) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the sgd transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the sgd transistor. Additional apparatus and methods are disclosed..
Micron Technology, Inc.


08/11/16
20160233165 

Active chip on carrier or laminated chip having microelectronic element embedded therein


A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity.
Tessera, Inc.


08/11/16
20160233108 

Defects annealing and impurities activation in semiconductors at thermodynamically non-stable conditions


A symmetric multicycle rapid thermal annealing (smrta) method for annealing a semiconductor material without the material decomposing. The smrta method includes a first long-time annealing at a first temperature at which the material is thermodynamically stable, followed by multicycle rapid thermal annealing (mrta) at temperatures at which the material is not thermodynamically stable, followed in turn by a second long-time annealing at a second temperature at which the material is thermodynamically stable.
The Government Of The United States Of America, As Represented By The Secretary Of The Navy


08/11/16
20160233096 

Floating body storage device employing a charge storage trench


A charge storage trench structure is provided underneath a body region of a field effect transistor to store electrical charges in a region spaced from the p-n junctions between the body region and the source and drain regions of a field effect transistor. The charge storage trench structure can be embedded in a dielectric material layer, and a semiconductor fin can be formed by attaching a semiconductor material layer to the top surface of the charge storage trench structure and by patterning the semiconductor material layer.
International Business Machines Corporation


08/11/16
20160231231 

Multi-functional fiber optic fuel sensor system having a photonic membrane


A fuel sensing system utilizes a fiber optic sensor comprising a membrane made of a direct band gap semiconductor material (such as gallium arsenide) that forms an optical cavity with an optical fiber inside a hermetically sealed sensor package located at the bottom of a fuel tank. The optical fiber inside the fuel tank is not exposed to the fuel.
The Boeing Company


08/11/16
20160230088 

Alloyed nanocrystals and quantum dots having alloyed nanocrystals


Alloyed nanocrystals and quantum dots having alloyed nanocrystals are described. In an example, a quantum dot includes an alloyed group ii-vi nanocrystalline core.
Pacific Light Technologies Corp.


08/11/16
20160229690 

Semiconductor device


A semiconductor device includes a substrate that is made of a semiconductor material and has a main surface formed with a recess. The semiconductor device also includes a wiring layer formed on the substrate, an electronic element housed in the recess, and a sealing resin covering at least a part of the electronic element..
Rohm Co., Ltd.


08/04/16
20160227147 

Image sensor with enhanced quantum efficiency


A back side illuminated image sensor includes a pixel array including semiconductor material, and image sensor circuitry disposed on a front side of the semiconductor material to control operation of the pixel array. A first pixel includes a first doped region disposed proximate to a back side of the semiconductor material and extends into the semiconductor material a first depth to reach the image sensor circuitry.
Omnivision Technologies, Inc.


08/04/16
20160226471 

Nonvolatile latch circuit and logic circuit, and semiconductor device using the same


To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element.
Semiconductor Energy Laboratory Co., Ltd.


08/04/16
20160226222 

Complementary metal oxide semiconductor device with iii-v optical interconnect having iii-v epitaxial semiconductor material formed using lateral overgrowth


An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate.
International Business Machines Corporation


08/04/16
20160225994 

Organic thin film transistor and manufacturing the same


Provided is a method for forming a pattern of an organic thin film semiconductor element. The method for forming a pattern of an organic thin film semiconductor element includes: preparing a mold structure having a groove; positioning the mold structure on an upper part of a substrate to enable the groove and the substrate to form a pipe; supplying an organic semiconductor material to a surface of the substrate; and hardening the organic semiconductor material..
Industry Academic Cooperation Foundation, Hallym University


08/04/16
20160225967 

Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated systems and methods


Solid-state transducers (“ssts”) and vertical high voltage ssts having buried contacts are disclosed herein. An sst die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure.
Micron Technology, Inc.


08/04/16
20160225948 

Solid state lighting devices with reduced crystal lattice dislocations and associated methods of manufacturing


Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and a plurality of hemispherical grained silicon (“hsg”) structures on the substrate surface of the substrate material.
Micron Technology, Inc.


08/04/16
20160225916 

Stacked nanowire device with variable number of nanowire channels


A method of forming a semiconductor structure including forming a stack of layers on a top surface of a substrate, the stack of layers including alternating layers of a semiconductor material and a sacrificial material, where a bottommost layer of the stack of layers is a top semiconductor layer of the substrate, patterning a plurality of material stacks from the stack of layers, each material stack including an alternating stack of a plurality of nanowire channels and a plurality of sacrificial spacers, the plurality of nanowire channels including the semiconductor material, and the plurality of sacrificial spacers including the sacrificial material, and removing at least one of the plurality of nanowire channels from at least one of the plurality of material stacks without removing one or more of the plurality of nanowire channels from an adjacent material stack.. .
Globalfoundries Inc.


08/04/16
20160225883 

Organic light emitting diode display having thin film transistor substrate using oxide semiconductor


A method for manufacturing an organic light emitting diode (oled) display can include forming a gate electrode on a substrate, forming a semiconductor layer by depositing a gate insulating layer and an oxide semiconductor material and patterning the oxide semiconductor material, forming an etch stopper on a central portion of the semiconductor layer, conducting a plasma treatment using the etch stopper as a mask to conductorize portions of the semiconductor layer exposed by the etch stopper for defining a channel area, a source area and a drain area, and forming a source electrode contacting portions of the conductorized source area and a drain electrode contacting portions of the conductorized drain area.. .
Lg Display Co., Ltd.


08/04/16
20160225853 

Graphene growth on a carbon-containing semiconductor layer


A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms.
Globalfoundries Inc.


08/04/16
20160225843 

Semiconductor component and manufacture


In accordance with an embodiment, a semiconductor component and a method for manufacturing a semiconductor component are provided. A first dielectric material is formed over a body of semiconductor material of the first conductivity type and a plurality of semiconductor fingers are formed over the first of dielectric material.
Semiconductor Components Industries, Llc


08/04/16
20160225699 

Integrated electronic device having a dissipative package, in particular dual side cooling package


Packaged semiconductor device having a frame, of conductive material; a body of semiconductor material, fixed to the frame through a first adhesive layer; a heat-sink element, fixed to the body through a second adhesive layer; and a packaging mass surrounding the body and, at least partially, the frame and the heat-sink element. The heat-sink element is formed by a heat-sink die facing, and coplanar to, a main face of the device and by a spacer structure, which includes a pair of pedestals projecting from the perimeter of the heat-sink die towards the body and rest on the body..
Stmicroelectronics S.r.l.


08/04/16
20160225676 

Methods of forming fin isolation regions under tensile-strained fins on finfet semiconductor devices


One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an nmos finfet device.. .
Globalfoundries Inc.


08/04/16
20160225674 

Methods of forming nmos and pmos finfet devices and the resulting product


One illustrative method disclosed herein includes, among other things, recessing first and second fins to define replacement fin cavities in a layer of insulating material, forming an initial strain relaxed buffer layer such that it only partially fills the replacement fin cavities, implanting carbon into the initial strain relaxed buffer layer in the nmos region, forming a channel semiconductor material on the initial strain relaxed buffer layer within the replacement fin cavities in both the nmos region and the pmos region to thereby define an nmos fin comprised of the channel semiconductor material and a carbon-doped strain relaxed buffer layer and a pmos fin comprised of the channel semiconductor material and the initial strain relaxed buffer layer and forming gate structures for the nmos and pmos devices.. .
Globalfoundries Inc.


08/04/16
20160225673 

High mobility transistors


An integrated circuit containing an n-channel finfet and a p-channel finfet has a dielectric layer over a silicon substrate. The fins of the finfets have semiconductor materials with higher mobilities than silicon.
Texas Instruments Incorporated


08/04/16
20160225657 

Localized region of isolated silicon over dielectric mesa


An integrated circuit is formed by forming an isolation mesa over a single crystal substrate which includes silicon, and forming a first epitaxial layer on the substrate by a selective epitaxial process so that a top surface of the first epitaxial layer is coplanar with the top surface of the isolation mesa. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on the first epitaxial layer and non-crystalline silicon-based material on the isolation mesa.
Texas Instruments Incorporated


07/28/16
20160218212 

Field effect transistor arrangement


A field effect transistor arrangement having as planar channel layer comprises semiconductor material, the whole surface of the underside of the layer being applied to an upper side of an electrically insulating substrate layer and the upper side of the planar channel layer being covered by an insulation layer. The arrangement has a source electrode on a first side edge of the channel layer and a drain electrode on a second side edge of the channel layer and a control electrode arranged above the channel layer.
Technische UniversitÄt Darmstadt


07/28/16
20160218198 

Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet


After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin.
Globalfoundries Inc.


07/28/16
20160218175 

Wafer substrate removal


A semiconductor device is formed on a semiconductor substrate, including a primary portion of the substrate. An active component of the semiconductor device is disposed in the primary portion of the substrate.
Texas Instruments Incorporated


07/28/16
20160218132 

Storage transistor with optical isolation


A storage transistor with a storage region is disposed in a semiconductor material. A gate electrode is disposed in a bottom side of an interlayer proximate to the storage region, and a dielectric layer is disposed between the storage region and the gate electrode.
Omnivision Technologies, Inc.


07/28/16
20160218128 

Active matrix light emitting diode array and projector display comprising it


A method of fabricating a pixelated imager and structure including a substrate with a bottom contact layer and active element blanket layers deposited on the bottom contact layer. The blanket layers are separated into an array of active elements with trenches isolating adjacent active elements in the array.

07/28/16
20160218043 

Fin field effect transistor including asymmetric raised active regions


Merged and unmerged raised active regions on semiconductor fins can be simultaneously formed on a same substrate by control of growth rates of a deposited semiconductor material on surfaces of the semiconductor fins. In one embodiment, a growth-rate-retarding dopant can be implanted by angled ion implantation onto sidewall surfaces of first semiconductor fins on which retardation of growth rates is desired, while second semiconductor fins are masked by a masking layer.
Globalfoundries Inc.


07/28/16
20160218005 

Methods and systems for improved uniformity of sige thickness


A process is used to form a protective layer to cover a divot between two regions of a semiconductor material. During etching processes, the protective layer protects the divot to be etched away and reduces material loss of a silicon (si)-shallow trench isolation (sti) substrate.
Shanghai Huali Microelectronics Corporation


07/28/16
20160217936 

Photoelectric conversion element


In a photoelectric conversion element, a conductive layer, a photoelectric conversion layer, and a counter electrode are disposed, and at least the photoelectric conversion layer is filled with an electrolyte. In the photoelectric conversion layer, at least one of a dye formed of a compound having one thiocyanate group and a dye formed of a compound not having a thiocyanate group is adsorbed onto a porous semiconductor layer formed of a semiconductor material.
Sharp Kabushiki Kaisha


07/21/16
20160212834 

Cyclic accelerator for accelerating charge carriers and manufacturing a cyclic accelerator


What is shown is a cyclic accelerator for accelerating charge carriers. The cyclic accelerator includes a charge carrier source configured to generate free charge carriers, a vacuum chamber configured to receive the free charge carriers, wherein the vacuum chamber is produced by means of mems technology, and wherein at least a main surface region of the vacuum chamber has a semiconductor material.
Fraunhofer-gesellschaft Zur Foerderung Der Angewandten Forschung E.v.


07/21/16
20160211411 

High efficiency ultraviolet light emitting diode with band structure potential fluctuations


A method of growing an algan semiconductor material utilizes an excess of ga above the stoichiometric amount typically used. The excess ga results in the formation of band structure potential fluctuations that improve the efficiency of radiative recombination and increase light generation of optoelectronic devices, in particular ultraviolet light emitting diodes, made using the method.
Trustees Of Boston University


07/21/16
20160211295 

Blue enhanced image sensor


A back side illuminated image sensor includes a semiconductor material having a front side and a back side. The semiconductor material is disposed between image sensor circuitry and a light filter array.
Omnivision Technologies, Inc.


07/21/16
20160211267 

Semiconductor storage device


Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked.
Semiconductor Energy Laboratory Co., Ltd.


07/21/16
20160211261 

Method and structure for finfet devices


A semiconductor device and a method of forming the same are disclosed. The device comprises a semiconductor substrate comprised of a first semiconductor material and having a plurality of isolation features, thereby defining a first active region and a second active region; a first fin semiconductor feature comprised of a second semiconductor material and formed in the first active region; and a second fin semiconductor feature comprised of a second semiconductor material and formed in the second active region.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/21/16
20160211258 

Reverse-conducting gated-base bipolar-conduction devices and methods with reduced risk of warping


Reverse-conducting igbts where the collector side includes diode terminal regions, and the semiconductor material is much thicker through the diode terminal regions than it is through the collector regions. This exploits the area fraction which is taken up by the diode terminal regions to provide increased rigidity for the wafer, and thus avoid warping..
Maxpower Semiconductor Inc.


07/21/16
20160211227 

Semiconductor device including a protection structure


A device includes a semiconductor chip including a dicing edge. The device further includes an active structure arranged in a semiconductor material of the semiconductor chip, and a protection structure arranged between the dicing edge and the active structure..
Infineon Technologies Ag


07/21/16
20160211043 

Systems and methods for regulating electrical power generated from a decay of radiation-emitting isotopes


Systems and methods are presented for regulating electrical power generated from a decay of radiation-emitting isotopes. The systems include a diode formed of a semiconductor material capable of mitigating radiation damage by operating at temperatures greater than 300° c.
Idaho State University


07/21/16
20160211042 

Devices and methods for converting energy from radiation into electrical power


Devices and methods are presented for converting energy from radiation into electrical power. In one illustrative embodiment, a device for converting energy from radiation into electrical power includes a diode formed of a semiconductor material capable of mitigating radiation damage by operating at temperatures greater than 300° c.
Idaho State University


07/21/16
20160207757 

Mems device and corresponding micromechanical structure with integrated compensation of thermo-mechanical stress


A micromechanical structure of a mems device, integrated in a die of semiconductor material provided with a substrate and having at least a first axis of symmetry lying in a horizontal plane, has a stator structure, which is fixed with respect to the substrate, and a rotor structure, having a suspended mass, mobile with respect to the substrate and to the stator structure as a result of an external action, the stator structure having fixed sensing electrodes capacitively coupled to the rotor structure; a compensation structure is integrated in the die for compensation of thermo-mechanical strains. The compensation structure has stator compensation electrodes, which are fixed with respect to the substrate, are capacitively coupled to the rotor structure, and are arranged symmetrically to the fixed sensing electrodes with respect to the first axis of symmetry..
Stmicroelectronics S.r.l.


07/14/16
20160204327 

Compound semiconductors and their applications


Disclosed is a new compound semiconductor material which may be used for thermoelectric material or the like, and its applications. The compound semiconductor may be represented by chemical formula 1 below: chemical formula 1 bi1-xmxcu1-wtwoa-yq1ytebsez where, in chemical formula 1, m is at least one selected from the group consisting of ba, sr, ca, mg, cs, k, na, cd, hg, sn, pb, mn, ga, in, tl, as and sb, q1 is at least one selected from the group consisting of s, se, as and sb, t is at least one selected from the group consisting of transition metal elements, 0≦x<1, 0<w<1, 0.2<a<1.5, 0≦y<1.5, 0≦b<1.5 and 0≦z<1.5..
Lg Chem, Ltd.


07/14/16
20160204278 

Self-aligned metal oxide tft with reduced number of masks and with reduced power consumption


A method of fabricating mo tfts includes positioning opaque gate metal on a transparent substrate to define a gate area. Depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon.

07/14/16
20160204231 

Semiconductor device and manufacturing method thereof


A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204211 

Self-limiting silicide in highly scaled fin technology


A method of forming a metal semiconductor alloy on a fin structure that includes forming a semiconductor material layer of a polycrystalline crystal structure material or amorphous crystal structure material on a fin structure of a single crystal semiconductor material, and forming a metal including layer on the semiconductor material layer. Metal elements from the metal including layer may then b intermixed metal elements with the semiconductor material layer to provide a metal semiconductor alloy contact on the fin structure.
International Business Machines Corporation


07/14/16
20160204205 

Source material for electronic device applications


Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material.
Micron Technology, Inc.


07/14/16
20160204198 

High mobility transistors


An integrated circuit containing an n-channel finfet and a p-channel finfet has a dielectric layer over a silicon substrate. The fins of the finfets have semiconductor materials with higher mobilities than silicon.
Texas Instruments Incorporated


07/14/16
20160204194 

Method and structure for improving finfet with epitaxy source/drain


Isolation structures are formed to laterally surround a gate material block such that each sidewall of the gate material block abuts a corresponding sidewall of the isolation structures. Sidewalls of the gate material bock define ends of gate structures to be subsequently formed.
International Business Machines Corporation


07/14/16
20160204131 

Strain release in pfet regions


A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (ssoi) structure, the ssoi structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the ssoi structure, forming a gate structure over a portion of at least one fin in a nfet region, forming a gate structure over a portion of at least one fin in a pfet region, removing the gate structure over the portion of the at least one fin in the pfet region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pfet region, such that the new gate structure surrounds the portion on all four sides.. .
International Business Machines Corporation


07/14/16
20160204039 

Temperature-controlled implanting of a diffusion-suppressing dopant in a semiconductor structure


Semiconductor structures and methods of fabrication are provided for, for instance, inhibiting diffusion of active dopant within a semiconductor material. A diffusion-suppressing dopant is implanted via, an implanting process under controlled temperature, into a semiconductor material of a semiconductor structure to define a diffusion-suppressed region within the semiconductor material.
Globalfoundries Inc.


07/14/16
20160204004 

Wafer-scale package including power source


A medical device includes a first substrate, a second substrate, a control module, and an energy storage device. The first substrate includes at least one of a first semiconductor material and a first insulating material.
Medtronic, Inc.


07/14/16
20160203980 

Device isolation for iii-v substrates


Techniques for device isolation for iii-v semiconductor substrates are provided. In one aspect, a method of fabricating a iii-v semiconductor device is provided.
International Business Machines Corporation


07/14/16
20160203973 

Method for the surface treatment of a semiconductor substrate


To apply an anti-wetting coating to a substrate of a semiconductor material, a method includes applying to a support a solution of a hydrocarbon comprising at least one unsaturated bond and, optionally, at least one hetero-atom for obtaining a layer of hydrocarbons. The method also includes treating at least one surface of the substrate of the semiconductor material with an acid.
Stmicroelectronics S.r.l.


07/14/16
20160202329 

Amr-type integrated magnetoresistive sensor for detecting magnetic fields perpendicular to the chip


An amr-type integrated magnetoresistive sensor sensitive to perpendicular magnetic fields is formed on a body of semiconductor material covered by an insulating region. The insulating region houses a set/reset coil and a magnetoresistor arranged on the set/reset coil.
Stmicroelectronics S.r.l.


07/07/16
20160197454 

Passive waveguide structure with alternating gainas/alinas layers for mid-infrared optoelectronic devices


Disclosed is a semiconductor optical emitter having an optical mode and a gain section, the emitter comprising a low loss waveguide structure made of two alternating layers of semiconductor materials a and b, having refractive indexes of na and nb, respectively, with an effective index no of the optical mode in the low loss waveguide between na and nb, wherein no is within a 5% error margin of identical to a refractive index of the gain section and wherein the gain section is butt-jointed with the low loss waveguide, and wherein the size and shape of the optical mode(s) in the low loss waveguide and gain section are within a 10% error margin of equal. Desirably, at least one of the semiconductor materials a and b has a sufficiently large band gap that the passive waveguide structure blocks current under a voltage bias of 15 v..
Thorlabs Quantum Electronics, Inc.


07/07/16
20160197281 

Photoelectric conversion device and fabrication method therefor


In order to form a photoelectric conversion layer of a photoelectric conversion element, mixed liquid including poly-[n-9′-heptadecanyl-2,7-carbazole-alt-5,5-(4′,7′-di-2-thienyl2′,1′,3′-benzothiadiazle)] as a p-type organic semiconductor material and a fullerene derivative as an n-type organic semiconductor material, which configure a bulk heterojunction are applied and dried. The dried substance is exposed in an atmosphere including vapor of a solvent that dissolves the p-type organic semiconductor material preferentially to the n-type organic semiconductor material..
Fujitsu Limited


07/07/16
20160197260 

Thermoelectric generator


A thermoelectric generator for powering a load includes a first mounting plate, a second mounting plate, and a plurality of semiconductors positioned between the first and the second mounting plates. The plurality of semiconductors includes one of positive-type or negative-type semiconductor material..
The Boeing Company


07/07/16
20160197256 

New compound semiconductors and their application


Disclosed is a new compound semiconductor material which may be used for thermoelectric material or the like, and its applications. The compound semiconductor may be represented by chemical formula 1 below: chemical formula 1 <chemical formula 1> bi2texsen−xinymz where in chemical formula 1, m is at least one selected from the group consisting of cu, fe, co, ag and ni, 2.5<x<3.0, 3.0≦a<3.5, 0<y and 0≦z..
Lg Chem, Ltd.


07/07/16
20160197231 

Solid state lighting devices with dielectric insulation and methods of manufacturing


Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials.
Micron Technology, Inc.


07/07/16
20160197223 

High-frequency optoelectronic detector, system and method


An optoelectronic device for detecting electromagnetic radiation includes a body of semiconductor material. A first region and a second region that form a junction are provided within the body.
Stmicroelectronics S.r.l.


07/07/16
20160197186 

Finfet with dielectric isolation after gate module for improved source and drain region epitaxial growth


A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures.
International Business Machines Corporation


07/07/16
20160197182 

Finfet and forming the same


The present disclosure provides a method for forming a field-effect fin transistor (finfet) structure. The method includes providing a substrate with fin structures; forming a gate structures across the fin structures; and forming ion implantation regions in the fin structures at both sides of the gate structure.
Semiconductor Manufacturing International (shanghai) Corporation


07/07/16
20160197093 

Semiconductor memory device and manufacturing same


According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body.
Kabushiki Kaisha Toshiba


07/07/16
20160197078 

Structure and advanced bulk fin isolation


A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant..
International Business Machines Corporation


07/07/16
20160197077 

Structure and advanced bulk fin isolation


A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant..
International Business Machines Corporation


07/07/16
20160197072 

Semiconductor device with different fin sets


A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench..
Globalfoundries Inc.


07/07/16
20160195489 

Electrical devices with enhanced electrochemical activity and manufacturing methods thereof


In some aspects, a device is provided having a member with a region of enhanced electrochemical activity. In one aspect, a sensor of enhanced electrochemical activity is provided for detecting an analyte concentration level in a bio-fluid sample.
Ascensia Diabetes Care Holding Ag


07/07/16
20160195479 

Multiple beam transmission interferometric testing methods for the development and evaluation of subwavelength sized features within semiconductor and anisotropic devices


Improved methods and systems for inspection imaging for holographic or interferometric semiconductor test and evaluation through all phases of device development and manufacture. Specifically, systems and methods are disclosed for extending the range of optical holographic interferometric inspection for testing and evaluating microelectronic devices and determining the interplay of electromagnetic signals and dynamic stresses to the semiconductor material are provided in which an enhanced imaging method provides continuous and varying the magnification of the optical holographic interferometric images over a plurality of interleaved optical pathways and imaging devices.
Attofemto, Inc.


06/30/16
20160191017 

Co-integrated bulk acoustic wave resonators


An electrical circuit assembly can include a semiconductor integrated circuit, such as fabricated including cmos devices. A first lateral-mode resonator can be fabricated upon a surface of the semiconductor integrated circuit, such as including a deposited acoustic energy storage layer including a semiconductor material, a deposited piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer, and a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to the semiconductor integrated circuit.

06/30/16
20160190556 

Anode material having a uniform metal-semiconductor alloy layer


The present invention relates to methods for producing anode materials for use in nonaqueous electrolyte secondary batteries. In the present invention, a metal-semiconductor alloy layer is formed on an anode material by contacting a portion of the anode material with a solution containing metals ions and a dissolution component.

06/30/16
20160190376 

Photovoltaic cell with variable band gap


A monolithic photovoltaic cell is proposed. Said cell comprises at least one junction.

06/30/16
20160190339 

Semiconductor devices with conductive contact structures having a larger metal silicide contact area


A semiconductor device includes a source/drain region, a gate structure, a gate cap layer positioned above the gate structure and a sidewall spacer positioned adjacent to opposite sides of the gate structure. A first epi semiconductor material is positioned in the source/drain region, the first epi semiconductor material having a first lateral width at an upper surface thereof.

06/30/16
20160190336 

Complementary high mobility nanowire neuron device


A method for forming a semiconductor device includes providing a substrate structure, which includes a nanowire structure supported by two isolation regions on a substrate. The nanowire structure includes a first nanowire and a second nanowire having different high mobility semiconductor materials and conductivity types.

06/30/16
20160190319 

Non-planar semiconductor devices having multi-layered compliant substrates


Non-planar semiconductor devices having multi-layered compliant substrates and methods of fabricating such non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate.

06/30/16
20160190315 

Method and structure of making enhanced utbb fdsoi devices


An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material.

06/30/16
20160190306 

Finfet device with a substantially self-aligned isolation region positioned under the channel region


One illustrative device disclosed herein includes, among other things, a semiconductor substrate, a fin structure, a gate structure positioned around a portion of the fin structure in the channel region of the device, spaced-apart portions of a second semiconductor material positioned vertically between the fin structure and the substrate, wherein the second semiconductor material is a different semiconductor material than that of the fin, and a local channel isolation material positioned laterally between the spaced-apart portions of the second semiconductor material and vertically below the fin structure and the gate structure, wherein the local channel isolation material is positioned under at least a portion of the channel region of the device.. .

06/30/16
20160190302 

Soi based finfet with strained source-drain regions


A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a sio2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (o2) throughout the layer as it is oxidized to form the insulator layer.

06/30/16
20160190299 

Semiconductor device having via hole coated in side surfaces with heat treated nitride metal and method to form the same


A semiconductor device having a via hole whose side surface is covered with nitride metals is disclosed. The via hole is formed within an insulating region that surrounds a conductive region, where both regions are made of nitride semiconductor materials.

06/30/16
20160190297 

High-electron-mobility transistors


High-electron-mobility transistors that include field plates are described. In a first implementation, a hemt includes a first and a second semiconductor material disposed to form a heterojunction at which a two-dimensional electron gas arises and source, a drain, and gate electrodes.

06/30/16
20160190286 

Surface passivation for germanium-based semiconductor structure


The present disclosure provides a method forming a semiconductor device in accordance with some embodiments. The method includes receiving a substrate having a fin protruding through the substrate, wherein the fin is formed of a first semiconductor material, exposing the substrate in an environment including hydrogen radicals, thereby passivating the protruded fin using the hydrogen radicals, and epitaxially growing a cap layer of a second semiconductor material to cover the protruded fin..

06/30/16
20160190279 

Unknown


A soi substrate is covered by a semiconductor material pattern which comprises a dividing pattern made from electrically insulating material. The dividing pattern is coated by one or more semiconductor materials.

06/30/16
20160190274 

Methods of forming contact structures for semiconductor devices and the resulting devices


A device includes a first epi semiconductor material positioned in a source/drain region of the device, the first epi semiconductor material having a first lateral width at an upper surface thereof. An extended-height epi contact structure having an upper surface and first and second side surfaces is positioned on the first epi semiconductor material, the upper surface and the first and second side surfaces collectively defining a contact length of the extended-height epi contact structure that is greater than the first lateral width.

06/30/16
20160190253 

Method and structure of making enhanced utbb fdsoi devices


An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material.

06/30/16
20160190250 

V-shaped epitaxially formed semiconductor layer


The present disclosure provides a method in accordance with some embodiments. The method includes forming a recess in a source/drain region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material.

06/30/16
20160190247 

Stressed nanowire stack for field effect transistor


A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires.

06/30/16
20160190246 

Stressed nanowire stack for field effect transistor


A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires.

06/30/16
20160190194 

Photodetector focal plane array systems and methods


A photodetector focal plane array system, comprising: a substrate comprising a plurality of photosensitive regions; and a microcomponent disposed adjacent to each of the plurality of photosensitive regions operable for receiving incident radiation and directing a photonic nanojet into the associated photosensitive region. Optionally, each of the microcomponents comprises one of a microsphere and a microcylinder.

06/30/16
20160190186 

Thin film transistor array panel and manufacturing method thereof


A thin film transistor array panel includes a substrate, an insulation layer, a first semiconductor, and a second semiconductor. The insulation layer is disposed on the substrate and includes a stepped portion.

06/30/16
20160190067 

Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method


A method of forming a semiconductor structure in a semiconductor-on-insulator (soi) substrate and semiconductor structure so formed are provided. The soi substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two.

06/30/16
20160190046 

Process for manufacturing a package for a surface-mount semiconductor device and semiconductor device


A surface-mount electronic device includes a body of semiconductor material, and a lead frame that includes a plurality of contact terminals. The plurality of contact terminals is electrically connected to the semiconductor body.



Semiconductor Material topics: Semiconductor, Semiconductor Material, Semiconductor Device, Transistors, Surfactant, Electric Conversion, Transparent Conductive Oxide, Semiconductor Substrate, Heating Devices, Semiconductor Devices, Organic Electroluminescence, Buffer Layer, Integrated Circuit, Crystallin, Electronic Device

Follow us on Twitter
twitter icon@FreshPatents

###

This listing is a sample listing of patent applications related to Semiconductor Material for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Semiconductor Material with additional patents listed. Browse our RSS directory or Search for other possible listings.


1.4704

6506

0 - 1 - 112