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Semiconductor Material

Semiconductor Material-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Waveguide embedded plasmon laser with multiplexing and electrical modulation
The Regents Of The University Of California
August 10, 2017 - N°20170229843

This disclosure provides systems, methods, and apparatus related to nanometer scale lasers. In one aspect, a device includes a substrate, a line of metal disposed on the substrate, an insulating material disposed on the line of metal, and a line of semiconductor material disposed on the substrate and the insulating material. The line of semiconductor material overlaying the line of ...
Semiconductor material doping
Sensor Electronic Technology, Inc.
August 10, 2017 - N°20170229610

A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such ...
Semiconductor element with a single photon avalanche diode and method for manufacturing such semiconductor element
Ams Ag
August 10, 2017 - N°20170229598

A method for manufacturing a semiconductor element comprising a single photon avalanche diode having a multiplication zone (ar) a guard ring structure with a second type of electrical conductivity comprises providing a semiconductor wafer with a first region (r) comprising a semiconductor material with the first type of conductivity. The method further comprises generating by a first doping process a ...
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Device with diffusion blocking layer in source/drain region
Globalfoundries Inc.
August 10, 2017 - N°20170229578

A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a source/drain region. A first material is epitaxially grown in the source/drain region. The first material includes a dopant species having a first concentration. A diffusion blocking layer is formed in the source/drain region ...
Finfet device and method for fabricating same
Taiwan Semiconductor Manufacturing Company, Ltd.
August 10, 2017 - N°20170229561

Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (finfets). An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer. ...
Finfet devices having a material formed on reduced source/drain region
Semiconductor Manufacturing International (shanghai) Corporation
August 10, 2017 - N°20170229559

A semiconductor device includes a fin structure of a first semiconductor material on a substrate. The fin structure has a source region, a drain region, and a channel region between the source region and the drain region. The device also has a gate structure overlying the fin structure. The source region includes an inner portion of the first semiconductor material ...
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Semiconductor Material Patent Applications
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inventor
  • 693+ full patent PDF documents of Semiconductor Material-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Vertical transistor device
International Business Machines Corporation
August 10, 2017 - N°20170229556

According to an embodiment of the present invention, a method for forming a semiconductor device includes pattering a first fin in a semiconductor substrate, and forming a liner layer over the first fin. The method further includes removing a first portion of the liner layer, and removing a portion of the exposed semiconductor substrate to form a first cavity. The ...
Stacked nanowire devices
International Business Machines Corporation
August 10, 2017 - N°20170229538

A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth ...
Monolithic visible-infrared focal plane array on silicon
International Business Machines Corporation
August 10, 2017 - N°20170229507

A structure includes a silicon substrate; silicon readout circuitry disposed on a first portion of a top surface of the substrate and a radiation detecting pixel disposed on a second portion of the top surface of the substrate. The pixel has a plurality of radiation detectors connected with the readout circuitry. The plurality of radiation detectors are composed of at ...
Single spacer for complementary metal oxide semiconductor process flow
International Business Machines Corporation
August 10, 2017 - N°20170229463

A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second ...
Fabricating a dual gate stack of a cmos structure
International Business Machines Corporation
August 10, 2017 - N°20170229460

A dual gate cmos structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including sixge1−x where x=0 to 1 and the second semiconductor material including a group iii-v compound material. A first gate stack on the first ...
Iii-v semiconductor cmos finfet device
International Business Machines Corporation
August 10, 2017 - N°20170229459

A method for forming a semiconductor device comprises forming an insulator layer on a semiconductor substrate, removing portions of the insulator layer to form a first cavity and a second cavity, the first cavity exposing a first portion of the semiconductor substrate an the second cavity exposing a second portion of the semiconductor substrate, growing a first semiconductor material in ...
Iii-v fins by aspect ratio trapping and self-aligned etch to remove rough epitaxy surface
International Business Machines Corporation
August 10, 2017 - N°20170229453

A semiconductor device that includes a fin structure of a type iii-v semiconductor material that is substantially free of defects, and has sidewalls that are substantially free of roughness caused by epitaxially growing the type iii-v semiconductor material abutting a dielectric material. The semiconductor device further includes a gate structure present on a channel portion of the fin structure; and ...
Semiconductor Material Patent Pack
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Semiconductor Material Patent Applications
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inventor
  • 693+ full patent PDF documents of Semiconductor Material-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
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Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture
Intel Corporation
August 10, 2017 - N°20170229354

Architectures and techniques for co-integration of heterogeneous materials, such as group iii-v semiconductor materials and group iv semiconductors (e. G., ge) on a same substrate (e. G. Silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region ...
Fabricating a dual gate stack of a cmos structure
International Business Machines Corporation
August 10, 2017 - N°20170229352

A dual gate cmos structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including sixge1-x where x=0 to 1 and the second semiconductor material including a group iii-v compound material. A first gate stack on the first channel ...
Single spacer for complementary metal oxide semiconductor process flow
International Business Machines Corporation
August 10, 2017 - N°20170229350

A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second ...
Method for forming a semiconductor structure containing high mobility semiconductor channel materials
International Business Machines Corporation
August 10, 2017 - N°20170229347

A method of forming a semiconductor structure is provided. The method includes providing a substrate comprising, from bottom to top, a handle substrate, an insulator layer and a germanium-containing layer. Next, hard mask material portions having an opening that exposes a portion of the germanium-containing layer are formed on the substrate. An etch is then performed through the opening to ...
Atomic layer etching 3d structures: si and sige and ge smoothness on horizontal and vertical ...
Lam Research Corporation
August 10, 2017 - N°20170229314

Methods and apparatuses for etching semiconductor material on substrates using atomic layer etching by chemisorption, by deposition, or by both chemisorption and deposition mechanisms in combination with oxide passivation are described herein. Methods involving atomic layer etching using a chemisorption mechanism involve exposing the semiconductor material to chlorine to chemisorb chlorine onto the substrate surface and exposing the modified surface ...
Strain relaxed buffer layers with virtually defect free regions
International Business Machines Corporation
August 10, 2017 - N°20170229304

A strain relaxed buffer layer of a second semiconductor material and of a second lattice constant and containing misfit dislocation defects and threading dislocation defects is formed atop a surface of a first semiconductor material of a first lattice constant that differs from the second lattice constant. The surface of the first semiconductor material includes at least one recessed region ...
Semiconductor chip carriers with monolithically integrated quantum dot devices and method of manufacture thereof
International Business Machines Corporation
August 10, 2017 - N°20170229302

A three-dimensional polycrystalline semiconductor material provides a major ingredient forming individual crystalline grains having a nominal maximum grain diameter less than or equal to 50 nm, and a minor ingredient forming boundaries between the individual crystalline grains.
Method for configuring an optical modulator
International Business Machines Corporation
August 10, 2017 - N°20170227829

A method for manufacturing an electro-optically coupled switch in accordance with the present invention requires a sequential reconfiguration of a layer of semiconductor material. To begin, a base member is created wherein the semiconductor layer is positioned on a layer of insulator material with the insulator material positioned between the semiconductor layer and a semiconductor substrate. In sequence, with a ...
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