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 Method and structure of making enhanced utbb fdsoi devices patent thumbnailnew patent Method and structure of making enhanced utbb fdsoi devices
An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material.
Stmicroelectronics (crolles 2) Sas


 Method and structure of making enhanced utbb fdsoi devices patent thumbnailnew patent Method and structure of making enhanced utbb fdsoi devices
An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material.
Stmicroelectronics (crolles 2) Sas


 Heterogeneous pocket for tunneling field effect transistors (tfets) patent thumbnailnew patent Heterogeneous pocket for tunneling field effect transistors (tfets)
Embodiments of the disclosure described herein comprise a tunneling field effect transistor (tfet) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to in crease a current through the tfet transistor when a voltage applied to the gate is above a threshold voltage..
Intel Corporation


 Method of fabricating semiconductor structures on dissimilar substrates patent thumbnailnew patent Method of fabricating semiconductor structures on dissimilar substrates
Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate.
Intel Corporation


 Photosensitive capacitor pixel for image sensor patent thumbnailnew patent Photosensitive capacitor pixel for image sensor
An image sensor pixel, and image sensor, and a method of fabricating the same is disclosed. The image pixel includes a photosensitive capacitor and a transistor network.
Omnivision Technologies, Inc.


 Method for the formation of a finfet device having a partially dielectric isolated fin structure patent thumbnailnew patent Method for the formation of a finfet device having a partially dielectric isolated fin structure
A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel.
Stmicroelectronics, Inc.


 Tunable composite interposer patent thumbnailnew patent Tunable composite interposer
A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a thickness of 200 microns or less, and can have a plurality of contacts exposed at the first surface and electrically conductive structure extending through the thickness.
Invensas Corporation


 Mis (metal-insulator-semiconductor) contact structures for semiconductor devices patent thumbnailnew patent Mis (metal-insulator-semiconductor) contact structures for semiconductor devices
An mis contact structure comprises a layer of semiconductor material, a layer of insulating material having a contact opening formed therein, a layer of contact insulating material having substantially vertically oriented portions and a substantially horizontally oriented portion, the vertically oriented portions of the layer of contact insulating material contacting a portion, but not all, of the sidewalls of the contact opening and the horizontally oriented portion of the layer of contact insulating material contacting the semiconductor layer. A conductive material is positioned on the layer of contact insulating material within the contact opening, the conductive material layer having vertically oriented portions and a horizontally oriented portion and a conductive contact positioned in the contact opening that contacts the uppermost surfaces of the conductive material layer and the layer of contact insulating material..
International Business Machines Corporation


 Non-destructive, wafer scale method to evaluate defect density in heterogeneous epitaxial layers patent thumbnailnew patent Non-destructive, wafer scale method to evaluate defect density in heterogeneous epitaxial layers
A semiconductor material stack of, from bottom to top, a first semiconductor material having a first lattice constant and a second semiconductor material having a second lattice constant that may or may not differ from the first lattice constant and is selected from an iii-v compound semiconductor and germanium is provided. The second semiconductor material of the semiconductor material stack is then scanned using an atomic force microscope (afm) operating in a tapping mode to provide an afm image of the second semiconductor material of the semiconductor material stack.
International Business Machines Corporation


 Photocathodes and dual photoelectrodes for nanowire photonic devices patent thumbnailnew patent Photocathodes and dual photoelectrodes for nanowire photonic devices
Important components of direct solar based nanowire enabled chemical processing and electrochemical systems are a high efficiency and highly stable photocathode and 2-photon dual electrodes. The former enables photo-excited electrons that lead to hydrogen generation whereas the later with complementary energy bandgap photoanode and photocathode enables high efficiency, unassisted solar-driven water splitting.

new patent

Mems isolation structures


A device may comprise a substrate formed of a first semiconductor material and a trench formed in the substrate. A second semiconductor material may be formed in the trench.
Digitaloptics Corporation Mems


Quantum dots with multiple insulator coatings


Fabricating a semiconductor structure including forming a nanocrystalline core from a first semiconductor material, forming a nanocrystalline shell from a second, different, semiconductor material that at least partially surrounds the nanocrystalline core, wherein the nanocrystalline core and the nanocrystalline shell form a quantum dot. Fabrication further involves forming an insulator layer encapsulating the quantum dot to create a coated quantum dot, and forming an additional insulator layer on the coated quantum dot using an atomic layer deposition (ald) process..

Metallic photovoltaics


According to some aspects, an apparatus for converting electromagnetic radiation into electric power is provided, comprising a first layer comprising a first semiconductor material, an absorber in contact with the first layer, a second layer comprising a second semiconductor material, the second layer being in contact with the absorber, and a reflector to reflect at least a portion of electromagnetic radiation passing through the second layer. According to some aspects, a method of forming an apparatus for converting electromagnetic radiation into electric power is provided, comprising forming a reflector on a substrate, forming a first layer in contact with the reflector, the first layer comprising a first semiconductor material, forming an absorber in contact with the first layer, and forming a second layer in contact with the absorber, the second layer comprising a second semiconductor material..
Massachusetts Institute Of Technology


Semiconductor apparatus having a trench schottky barrier schottky diode


A semiconductor apparatus having a trench schottky barrier schottky diode, which includes: a semiconductor volume of a first conductivity type, which semiconductor volume has a first side covered with a metal layer, and at least one trench extending in the first side and at least partly filled with metal. At least one wall segment of the trench, and/or at least one region, located next to the trench, of the first side covered with the metal layer, is separated by a layer, located between the metal layer and the semiconductor volume, made of a first semiconductor material of a second conductivity type..
Robert Bosch Gmbh


Self-aligned metal oxide thin film transistor and making same


A thin film transistor comprises a substrate, a gate electrode formed on the substrate, an electrically insulating layer covering the gate electrode, a channel layer made of a semiconductor material and formed on the electrically insulating layer, a source electrode formed on a first lateral side of the electrically insulating layer, and a drain electrode formed on an opposite second lateral side of the electrically insulating layer. The source electrode has an inner end covering a first outer end of the channel layer and electrically connecting therewith.
Ye Xin Technology Consulting Co., Ltd.


Method of making a cmos semiconductor device using a stressed silicon-on-insulator (soi) wafer


A method for forming a complementary metal oxide semiconductor (cmos) semiconductor device includes providing a stressed silicon-on-insulator (ssoi) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region.
Stmicroelectronics, Inc.


Method for inducing strain in vertical semiconductor columns


A vertical metal-oxide-semiconductor (mos) transistor includes a substrate and a nano-wire over the substrate. The nano-wire comprises a semiconductor material.
Taiwan Semiconductor Manufacturing Company, Ltd.


Three-dimensional transistor with improved channel mobility


A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure.
Globalfoundries Inc.


Methods of forming semiconductor devices, including forming a semiconductor material on a fin, and related semiconductor devices


Methods of forming a semiconductor device are provided. A method of forming a semiconductor device includes forming a semiconductor layer on a fin, where the fin and the semiconductor layer include first and second semiconductor materials, respectively.
Samsung Electronics Co., Ltd.


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High electron mobility transistor (hemt) and producing the same


A high electron mobility transistor (hemt) primarily made of nitride semiconductor materials is disclosed. The hemt includes, on a substrate, a buffer layer, a channel layer, and a barrier layer.
Sumitomo Electric Industries, Ltd.


Thin-substrate double-base high-voltage bipolar transistors


B-tran bipolar power transistor devices and methods, using a drift region which is much thinner than previously proposed double-base bipolar transistors of comparable voltage. This is implemented in a high-bandgap semiconductor material (preferably silicon carbide).
Ideal Power Inc.


Complementary tunneling fet devices and forming the same


Described is an apparatus forming complementary tunneling field effect transistors (tfets) using oxide and/or organic semiconductor material. One type of tfet comprises: a substrate; a doped first region, formed above the substrate, having p-type material selected from a group consisting of group iii-v, iv-iv, and iv of a periodic table; a doped second region, formed above the substrate, having transparent oxide n-type semiconductor material; and a gate stack coupled to the doped first and second regions.
Intel Corporation


Methods of forming embedded source/drain regions on finfet devices


One illustrative method disclosed herein includes, among other things, forming a layer of insulating material in the source/drain regions of the device, wherein the layer of insulating material has an upper surface that is substantially planar with an upper surface of a gate cap layer, recessing the layer of insulating material such that its recessed upper surface exposes a surface of the fin, performing another etching process to remove at least a portion of the fin and thereby define a recessed fin trench positioned above the recessed fin, and forming an epitaxial semiconductor material that is at least partially positioned in the recessed fin trench.. .
Globalfoundries Inc.


Double aspect ratio trapping


A semiconductor structure is provided by a process in which two aspect ratio trapping processes are employed. The structure includes a semiconductor substrate portion of a first semiconductor material having a first lattice constant.
International Business Machines Corporation


Devices having a semiconductor material that is semimetal in bulk and methods of forming the same


Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region.
Taiwan Semiconductor Manufacturing Company, Ltd.


Semiconductor device and manufacturing semiconductor device


According to one embodiment, a semiconductor device includes a semiconductor substrate made of a first semiconductor material, an element isolation insulating film, a gate electrode film, source/drain regions, a channel region, and a diffusion preventing film. The channel region is provided near a surface of the semiconductor substrate below the gate electrode film, and containing a second impurity of a predetermined conductivity type diffused therein.
Kabushiki Kaisha Toshiba


Reducing risk of punch-through in finfet semiconductor structure


Reducing a chance of punch-through in a finfet structure includes providing a substrate, creating a blanket layer of semiconductor material with impurities therein over the substrate, masking a portion of the blanket layer, creating epitaxial semiconductor material on an unmasked portion of the structure, removing the mask, and etching the structure to create n-type raised structure(s) and p-type raised structure(s), a bottom portion of the raised structure(s) being surrounded by isolation material. A middle portion of the raised structure(s) includes a semiconductor material with impurities therein, the middle portion extending across the raised structure(s), and a top portion including a semiconductor material lacking added impurities..
Globalfoundries Inc.


Semiconductor device having a trench mos barrier schottky diode


A semiconductor device having a trench mos barrier schottky diode includes a semiconductor volume of a first conductivity type, the semiconductor volume (i) having a first side which is covered with a metal layer, and (ii) including at least one trench which extends in the first side and is at least partially filled with metal and/or with a semiconductor material of a second conductivity type. The trench has at least one wall section which includes an oxide layer, at least in areas.
Robert Bosch Gmbh


Crystalline layer stack for forming conductive layers in a three-dimensional memory structure


A stack of alternating layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline substrate. The first and second epitaxial semiconductor layers are in epitaxial alignment with a crystal structure of the single crystalline substrate.
Sandisk Technologies, Inc.


Air gap contact formation for reducing parasitic capacitance


A functional gate structure is located on a surface of a semiconductor material portion and including a u-shaped gate dielectric portion and a gate conductor portion. A source region is located on one side of the functional gate structure, and a drain region is located on another side of the functional gate structure.
International Business Machines Corporation


Selective epitaxy using epitaxy-prevention layers


A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material..
International Business Machines Corporation


Double aspect ratio trapping


A semiconductor structure is provided by a process in which two aspect ratio trapping processes are employed. The structure includes a semiconductor substrate portion of a first semiconductor material having a first lattice constant.
International Business Machines Corporation


Surface passivation on indium-based materials


The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor feature, a passivation layer that includes indium sulfide formed over a surface of the semiconductor feature.
Taiwan Semiconductor Manufacturing Company, Ltd.


Optoelectronic semiconductor chip


An optoelectronic semiconductor chip is disclosed. In an embodiment the optoelectronic semiconductor chip includes a semiconductor body of semiconductor material, a p-contact layer and an n-contact layer.
Osram Opto Semiconductors Gmbh


Semiconductor material doping


A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier.
Sensor Electronic Technology, Inc.


Semiconductor device and manufacturing method thereof


It is an object to provide a semiconductor device having a new productive semiconductor material and a new structure. The semiconductor device includes a first conductive layer over a substrate, a first insulating layer which covers the first conductive layer, an oxide semiconductor layer over the first insulating layer that overlaps with part of the first conductive layer and has a crystal region in a surface part, second and third conductive layers formed in contact with the oxide semiconductor layer, an insulating layer which covers the oxide semiconductor layer and the second and third conductive layers, and a fourth conductive layer over the insulating layer that overlaps with part of the oxide semiconductor layer..
Semiconductor Energy Laboratory Co., Ltd.


Nitride semiconductor device having aluminum oxide film and a process for producing the same


A transistor primarily made of nitride semiconductor materials and a passivation film of al2o3, and a process for producing the same are disclosed. The transistor, which is the type of the high-electron mobility transistor (hemt), has a channel layer and a barrier layer sequentially grown on a semiconductor substrate.
Sumitomo Electric Industries, Ltd.


Parallel bit line three-dimensional resistive random access memory


Resistive random access memory (reram) array includes line stack structures located over a substrate. The line stack structures are laterally spaced apart along a first horizontal direction, and extend along a second horizontal direction that is different from the first horizontal direction.
Sandisk 3d Llc


Reversed flexible tft back-panel by glass substrate removal


The process of fabricating a flexible tft back-panel includes depositing etch stop material on a glass support. A matrix of contact pads, gate electrodes and gate dielectric are deposited overlying the etch stop material.

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Semiconductor device


An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor.
Semiconductor Energy Laboratory Co., Ltd.


Semiconductor structures including rails of dielectric material


Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings.
Micron Technology, Inc.


Heterojunction-based hemt transistor


A heterojunction structure of semiconductor material, for a high electron mobility transistor includes a substrate, a buffer layer, arranged on the substrate, of a large bandgap semiconductor material, based on a nitride from column iii, where the buffer layer is not intentionally doped with n-type carriers, a barrier layer arranged above the buffer layer, of a large bandgap semiconductor material based on a nitride from column iii, where the width of the bandgap of the barrier layer is less than the width of the bandgap of the buffer layer. The heterojunction structure additionally comprises an intentionally doped area, of a material based on a nitride from column iii identical to the material of the buffer layer, in a plane parallel to the plane of the substrate and a predefined thickness along a direction orthogonal to the plane of the substrate, where the area is comprised in the buffer layer..
Universite Libanaise


Method of making a finfet device


A device includes a first fin including a first semiconductor material. A first dielectric layer is disposed over a top surface of the first fin.
Taiwan Semiconductor Manufacturing Company, Ltd.


Ldd-free semiconductor structure and manufacturing the same


The present disclosure provides an ldd-free semiconductor structure including a semiconductor layer, a gate over the semiconductor layer and a regrowth region made of semiconductor material positioned in the semiconductor layer. The regrowth region forms a source region or a drain region of the ldd-free semiconductor structure.
Taiwan Semiconductor Manufacturing Company Ltd.


Three-dimensional devices having reduced contact length


Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate.
Micron Technology, Inc.


Iii-v finfet cmos with iii-v and germanium-containing channel closely spaced


Closely spaced iii-v compound semiconductor fins and germanium-containing semiconductor fins are provided by utilizing mandrel structures for iii-v compound semiconductor material epitaxial growth and subsequent fin formation. Mandrel structures are formed on a semiconductor material stack that includes an uppermost layer of a relaxed germanium-containing material layer.
International Business Machines Corporation


Integrated circuit structure with active and passive devices in different tiers


An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein.
Taiwan Semiconductor Manufacturing Company, Ltd.


Selective dopant junction for a group iii-v semiconductor device


An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer.
International Business Machines Corporation


Compound semiconductor structure


A method for fabricating semiconductor structure comprises the steps of providing a substrate including a first crystalline semiconductor material, patterning an opening in a dielectric layer above the substrate, the opening having a bottom, forming a crystalline interlayer on the substrate at least partially covering the bottom, and growing a second crystalline semiconductor material on the crystalline interlayer thereby at least partially filling the opening. The crystalline semiconductor materials are lattice mismatched, and the crystalline interlayer comprises an oxygen compound..
Globalfoundries Inc.


Complementary metal oxide semiconductor device with iii-v optical interconnect having iii-v epitaxially formed material


An electrical device that in one embodiment includes a first semiconductor device positioned on a first portion of a type iv semiconductor substrate, and an optoelectronic light emission device of type iii-v semiconductor materials that is in electrical communication with the first semiconductor device. The optoelectronic light emission device is positioned adjacent to the first semiconductor device on the first portion of the type iv semiconductor substrate.
International Business Machines Corporation


Hall sensor readout system with offset determination using the hall element itself


A method for providing offset compensation in a hall sensor comprising at least one hall element having a plate-shaped sensor element made of a doped semiconductor material, comprises using measurements on the hall element itself. The method comprises obtaining a first readout signal (vh) from the at least one hall element which is substantially dependent on the magnetic field, obtaining a second readout signal (vp) from the at least one hall element which is substantially independent of the magnetic field, and using the second readout signal (vp) for obtaining a prediction ({circumflex over (v)}o) of the offset (vo) on the first readout signal (vh)..
Melexis Technologies Nv


Tsv testing method and apparatus


An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between the top surface and the bottom surface. A through silicon via (tsv) has a conductive body in the opening, has a top contact point coupled to the body at the top surface, and has a bottom contact point coupled to the body at the bottom surface.
Texas Instruments Incorporated


Quantum dot light emitting diodes for multiplex gas sensing


A gas detection device comprising a light emitting source including a first plurality of quantum dots of substantially discrete size and made of a semiconductor material a gas cell to contain the gas to be detected and a light detector.. .
Board Of Supervisors Of Louisiana State University And Agricultural And Mechanical College


Method for manufacturing polysilicon thin film transistor


A method for manufacturing polysilicon thin film transistor is disclosed, and the method comprises the following steps: forming a semiconductor material layer on a prefabricated substrate; forming an intermediate layer on the semiconductor material layer; forming a photoresist layer on the intermediate layer, and exposing the photoresist layer with a photomask for a first time; moving the prefabricated substrate in a predetermined direction relative to the photomask, and exposing the photoresist layer with the photomask for a second time; forming a photoresist region which comprises a central part and a wing part and a hollowed-out region which contains no photoresist material in the photoresist layer; and forming an ion lightly doped region corresponding to the wing part and an ion heavily doped region corresponding to the hollowed-out region in the semiconductor material layer.. .
Shenzhen China Star Optoelectronics Technology Co., Ltd.


Field-effect transistor with aggressively strained fins


In a method for fabricating a field-effect transistor (fet) structure, forming a shallow trench isolation (sti) structure on a semiconductor substrate, wherein the sti structure includes dielectric structures that form one or more dielectric walled aspect ratio trapping (art) trenches. The method further includes epitaxially growing a first semiconductor material on the semiconductor substrate and substantially filling at least one of the one or more art trenches, and recessing the first semiconductor material down into the art trenches selective to the dielectric structures, such that the upper surface of the first semiconductor material is below the upper surface of the dielectric structures.
International Business Machines Corporation


Channel last replacement flow for bulk finfets


There is set forth herein a method including patterning a fin on a substrate of a semiconductor structure, forming dielectric material over the substrate, performing a process for removing material from a fin to define a cavity at a channel region of the fin, and forming a replacement semiconductor material formation at the channel region.. .
Globalfoundries Inc.


Epitaxial silicon germanium fin formation using sacrificial silicon fin templates


A method of forming semiconductor fins includes forming a plurality of sacrificial template fins from a first semiconductor material; epitaxially growing fins of a second semiconductor material on exposed sidewall surfaces of the sacrificial template fins; and removing the plurality of sacrificial template fins.. .
International Business Machines Corporation


Trench semiconductor device layout configurations


A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material..
Sanken Electric Co., Ltd.


Solid-state image sensing device


According to one embodiment, a solid-state image sensing device includes an organic photoelectric conversion layer. The organic photoelectric conversion layer includes an organic semiconductor material and an organic dye.
Kabushiki Kaisha Toshiba


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Memory devices including vertical pillars and methods of manufacturing and operating the same


A semiconductor device includes a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate.
Samsung Electronics Co., Ltd.


Semiconductor memory device


The memory capacity of a dram is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer.
Semiconductor Energy Laboratory Co., Ltd.


Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin structures


A method of forming a semiconductor device that includes forming an at least partially relaxed semiconductor material, and forming a plurality of fin trenches in the partially relaxed semiconductor material. At least a portion of the plurality of fin trenches is filled with a first strained semiconductor material that is formed using epitaxial deposition.
International Business Machines Corporation


Compound semiconductor transistor with gate overvoltage protection


A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region.
Infineon Technologies Austria Ag


Method for fabricating a quasi-soi source-drain multi-gate device


The present invention discloses a method for fabricating a quasi soi source-drain multi-gate device, belonging to a field of manufacturing ultra large scale integrated circuit, the method comprises in sequence the following steps of: forming a fin strip-shaped active region on a first semiconductor substrate; forming a sti isolation layer; depositing a gate dielectric layer and a gate material layer, forming a gate stack structure; forming a doped structure of a source-drain extension region; forming a recessed source-drain structure; forming a quasi soi source-drain isolation layer; in-situ doping an epitaxial source and drain of a second semiconductor material and performing annealing for activating; removing a dummy gate and performing a deposition of a high k metal gate again; and forming a contact and a metal interconnection.. .
Perking University


Epitaxial silicon germanium fin formation using sacrificial silicon fin templates


A method of forming semiconductor fins includes forming a plurality of sacrificial template fins from a first semiconductor material; epitaxially growing fins of a second semiconductor material on exposed sidewall surfaces of the sacrificial template fins; and removing the plurality of sacrificial template fins.. .
International Business Machines Corporation


Method of detecting conversion quality of green matrix composite material and system for same


A method of detecting conversion quality includes the steps of providing an article having a green material and a semiconductor material, processing the green material and the semiconductor material to produce a matrix composite, and detecting a matrix composite conversion quality with the semiconductor material.. .
United Technologies Corporation


Chip for biological analyses provided with wells having an improved shape, cartridge including the chip and manufacturing the chip


A chip for biological and/or biochemical analyses includes: a supporting body, including a substrate of semiconductor material and a structural layer of biocompatible material; and a plurality of wells, designed to contain a liquid solution for the biological and/or biochemical analyses. Each well is formed by: a bottom chamber, defining a first containment volume for containing the liquid solution, and a top chamber, extending at least partially vertically aligned to, and in fluid communication with, the bottom chamber and defining a second containment volume greater than the first containment volume.
Distretto Tecnologico Sicilia Micro E Nano Sistemi S.c.a.r.l.


Electronic device


The present disclosure provides an electronic device suitable for miniaturization. The present electronic device includes: a substrate (1), having a main surface (111) and a back surface (112) facing opposite sides with each other in a thickness direction, wherein the substrate comprises a semiconductor material; an electronic component (8), which is disposed over the substrate (1); and a conductive layer (3), which is electrically connected with the electronic component (8); wherein a recess for disposing the component (14) and a through recess (17) are formed in the substrate, in which recess for disposing the component (14) is recessed from the main surface (111), and the through recess (17) penetrates from the recess for disposing the component (14) to the back surface (112); the electronic component (8) is disposed over the recess for disposing the component (14); a metal-filled portion (4) is formed in the through recess (17), wherein the metal-filled portion blocks at least the bottom of the through recess (17) and is filled with a metal material; and the conductive layer (3) is formed at least from the through recess (17) to the back surface (112)..
Rohm Co., Ltd.


Coating material for forming semiconductors, semiconductor thin film, thin film solar cell and manufacturing thin film solar cell


The present invention aims to provide a coating liquid for forming a semiconductor which facilitates large-area production of a semiconductor that is useful as a semiconductor material of a solar cell with high conversion efficiency and small variation in the conversion efficiency, and enables control of the film thickness. The present invention also aims to provide a semiconductor thin film produced from the coating liquid for forming a semiconductor, a thin film solar cell, and a method for producing the thin film solar cell.
Sekisui Chemical Co., Ltd.


Perylene-based semiconductors


The present invention relates to new semiconductor materials prepared from perylene-based compounds. Such compounds can exhibit high carrier mobility and/or good current modulation characteristics.
Polyera Corporation


Method for producing a solar cell


The invention relates to a method for producing a solar cell (1) from crystalline semiconductor material. In a first surface (3a) of a semiconductor substrate (3), a first doping area (5) is formed by thermally diffusing a first dopant and in the second surface (3b) of the semiconductor substrate, a second doping area (7) is formed by implanting ions and thermally implanting a second dopant..
Ion Beam Services


Anneal techniques for chalcogenide semiconductors


Techniques for precisely controlling the composition of volatile components (such as sulfur (s), selenium (se), and tin (sn)) of chalcogenide semiconductors in real-time—during production of the material are provided. In one aspect, a method for forming a chalcogenide semiconductor material includes providing a s source(s) and a se source(s); heating the s source(s) to form a s-containing vapor; heating the se source(s) to form a se-containing vapor; passing a carrier gas first through the s-containing vapor and then through the se-containing vapor, wherein the s-containing vapor and the se-containing vapor are transported via the carrier gas to a sample; and contacting the s-containing vapor and the se-containing vapor with the sample under conditions sufficient to form the chalcogenide semiconductor material.
International Business Machines Corporation


Photoconducting layered material arrangement, fabricating the photoconducting layered material arrangement, and use of photoconducting layered material arrangement


A photoconducting layered material arrangement for producing or detecting high frequency radiation includes a semiconductor material including an alloy comprised of ingaas, ingaassb, or gasb, with an admixture of al, which material is applied to a suitable support substrate in a manner such that the lattices are suitably adjusted, wherewith the semiconductor material comprised of ingaalas, ingaalassb, or gaalsb has a band gap of more than 1 ev, as a consequence of the admixed proportion of al. The proportion x of al in the semiconductor material inyga1−y−xalxas is between x=0.2 and x=0.35, wherewith the proportion y of in may be between 0.5 and 0.55.
Technische Universität Darmstadt


Method for manufacturing semiconductor device with recess, epitaxial growth and diffusion


A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate..
Sony Corporation


Depression filling method and processing apparatus


A method of filling a depression of a workpiece is provided. The depression passes through an insulating film and extends up to an inside of a semiconductor substrate.
Tokyo Electron Limited


Structure and formation finfet device


Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack and a second gate stack over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


Gate-all-around semiconductor device and fabricating the same


The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between sti regions at least one suspended nanostructure anchored by a source region and a drain region.
Imec Vzw


Depression filling method and processing apparatus


A method of filling a depression of a workpiece is provided. The method includes forming a first thin film made of a semiconductor material substantially not containing an impurity along a wall surface which defines the depression, forming an epitaxial region conforming to crystals of the semiconductor substrate from the semiconductor material of the first thin film moved toward a bottom of the depression by annealing, etching the first thin film remaining on the wall surface, performing gas phase doping upon the epitaxial region, forming a second thin film made of a semiconductor material substantially not containing an impurity along the wall surface, further forming an epitaxial region from the semiconductor material of the second thin film moved toward the bottom of the depression by annealing, and performing gas phase doping upon the second thin film remaining on the wall surface and the epitaxial region..
Tokyo Electron Limited


Loss compensated optical switching


Loss compensated optical switching includes an optical crossbar switch and a wafer bonded semiconductor amplifier (soa). The optical crossbar switch has a plurality of input ports and a plurality of output ports and is on a substrate of a first semiconductor material.
Hewlett-packard Development Company, L.p.


Anneal techniques for chalcogenide semiconductors


Techniques for precisely controlling the composition of volatile components (such as sulfur (s), selenium (se), and tin (sn)) of chalcogenide semiconductors in real-time—during production of the material are provided. In one aspect, a method for forming a chalcogenide semiconductor material includes providing a s source(s) and a se source(s); heating the s source(s) to form a s-containing vapor; heating the se source(s) to form a se-containing vapor; passing a carrier gas first through the s-containing vapor and then through the se-containing vapor, wherein the s-containing vapor and the se-containing vapor are transported via the carrier gas to a sample; and contacting the s-containing vapor and the se-containing vapor with the sample under conditions sufficient to form the chalcogenide semiconductor material.
International Business Machines Corporation


Method for producing a solar cell involving doping by ion implantation and depositing an outdiffusion barrier


The invention relates to a method for producing a solar cell (1) from crystalline semiconductor material, wherein a first doping region (5) is formed by means of ion implantation (s2) of a first dopant in a first surface (3a) of a semiconductor substrate (3), and a second doping region (7) is formed by means of ion implantation (s3) or thermal indiffusion of a second dopant in the second surface (3b) of the semiconductor substrate. After the doping of the second surface, a cap (9b) acting as an outdiffusion barrier for the second dopant is applied and an annealing step (s4) is subsequently carried out..
International Solar Energy Research Center Konstan Z E.v.


Strained channel region transistors employing source and drain stressors and systems including the same


Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor.
Intel Corporation


Group iii-v semiconductor device with strain-relieving layers


According to one exemplary embodiment, a group iii-v semiconductor device includes at least one transition layer situated over a substrate. The group iii-v semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer.
Infineon Technologies Americas Corp.


Finfet device and fabricating same


Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (finfets). An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


Method of manufacturing a spacer supported lateral channel fet


A semiconductor device is manufactured by forming a plurality of trenches extending into a semiconductor material from a first main surface of the semiconductor material to form mesas of semiconductor material between the trenches. A trench fill material is disposed in the trenches, the trench fill material extending above the first main surface of the semiconductor material.
Infineon Technologies Austria Ag


System for glass sheet semiconductor coating and resultant product


A system (20) for coating semiconductor material on glass sheets is performed by conveying the glass sheets vertically suspended at upper extremities thereof through a system (20) having a housing (22) including a vacuum chamber (24). The glass sheets are conveyed on shuttles (42) through an entry load lock station (26) into the housing vacuum chamber (24), through a heating station (30) and at least one deposition station (32, 34) in the housing (22), and to a cooling station 36 prior to exiting of the system through an exit load lock station (28).
Willard & Kelsey Solar Group, Llc


Formation of strained fins in a finfet device


In an aspect of the present invention, a field-effect transistor (fet) structure is formed. The fet structure comprises a plurality of fins formed on a semiconductor substrate, wherein the plurality of fins includes a set of fins that include a base portion that is comprised of relaxed silicon-germanium (sige) and an upper portion that is comprised of semiconductor material.
International Business Machines Corporation


Cmos structure on ssoi wafer


A method of forming fins in a complimentary-metal-oxide-semiconductor (cmos) device that includes a p-type field effect transistor device (pfet) and an n-type field effect transistor (nfet) device and a cmos device are described. The method includes forming a strained silicon-on-insulator (ssoi) layer in both a pfet region and an nfet region, etching the strained silicon layer, the insulator, and a portion of the bulk substrate in only the pfet region to expose the bulk substrate, epitaxially growing silicon (si) from the bulk substrate in only the pfet region, and epitaxially growing additional semiconductor material on the si in only the pfet region.
International Business Machines Corporation


Cmos structure on ssoi wafer


A method of forming fins in a complimentary-metal-oxide-semiconductor (cmos) device that includes a p-type field effect transistor device (pfet) and an n-type field effect transistor (nfet) device and a cmos device are described. The method includes forming a strained silicon-on-insulator (ssoi) layer in both a pfet region and an nfet region, etching the strained silicon layer, the insulator, and a portion of the bulk substrate in only the pfet region to expose the bulk substrate, epitaxially growing silicon (si) from the bulk substrate in only the pfet region, and epitaxially growing additional semiconductor material on the si in only the pfet region.
International Business Machines Corporation


Enhanced channel mobility three-dimensional memory structure and making thereof


A stack including an alternating plurality of first material layers and second material layers is provided. A memory opening is formed and at least a contiguous semiconductor material portion including a semiconductor channel is formed therein.
Sandisk Technologies Inc.


Drain select gate formation methods and apparatus


Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (sgd) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the sgd transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the sgd transistor. Additional apparatus and methods are disclosed..
Micron Technology, Inc.


Active chip on carrier or laminated chip having microelectronic element embedded therein


A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity.
Tessera, Inc.


Defects annealing and impurities activation in semiconductors at thermodynamically non-stable conditions


A symmetric multicycle rapid thermal annealing (smrta) method for annealing a semiconductor material without the material decomposing. The smrta method includes a first long-time annealing at a first temperature at which the material is thermodynamically stable, followed by multicycle rapid thermal annealing (mrta) at temperatures at which the material is not thermodynamically stable, followed in turn by a second long-time annealing at a second temperature at which the material is thermodynamically stable.
The Government Of The United States Of America, As Represented By The Secretary Of The Navy


Floating body storage device employing a charge storage trench


A charge storage trench structure is provided underneath a body region of a field effect transistor to store electrical charges in a region spaced from the p-n junctions between the body region and the source and drain regions of a field effect transistor. The charge storage trench structure can be embedded in a dielectric material layer, and a semiconductor fin can be formed by attaching a semiconductor material layer to the top surface of the charge storage trench structure and by patterning the semiconductor material layer.
International Business Machines Corporation


Multi-functional fiber optic fuel sensor system having a photonic membrane


A fuel sensing system utilizes a fiber optic sensor comprising a membrane made of a direct band gap semiconductor material (such as gallium arsenide) that forms an optical cavity with an optical fiber inside a hermetically sealed sensor package located at the bottom of a fuel tank. The optical fiber inside the fuel tank is not exposed to the fuel.
The Boeing Company


Alloyed nanocrystals and quantum dots having alloyed nanocrystals


Alloyed nanocrystals and quantum dots having alloyed nanocrystals are described. In an example, a quantum dot includes an alloyed group ii-vi nanocrystalline core.
Pacific Light Technologies Corp.


Semiconductor device


A semiconductor device includes a substrate that is made of a semiconductor material and has a main surface formed with a recess. The semiconductor device also includes a wiring layer formed on the substrate, an electronic element housed in the recess, and a sealing resin covering at least a part of the electronic element..
Rohm Co., Ltd.


Image sensor with enhanced quantum efficiency


A back side illuminated image sensor includes a pixel array including semiconductor material, and image sensor circuitry disposed on a front side of the semiconductor material to control operation of the pixel array. A first pixel includes a first doped region disposed proximate to a back side of the semiconductor material and extends into the semiconductor material a first depth to reach the image sensor circuitry.
Omnivision Technologies, Inc.


Nonvolatile latch circuit and logic circuit, and semiconductor device using the same


To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element.
Semiconductor Energy Laboratory Co., Ltd.


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Complementary metal oxide semiconductor device with iii-v optical interconnect having iii-v epitaxial semiconductor material formed using lateral overgrowth


An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate.
International Business Machines Corporation


Organic thin film transistor and manufacturing the same


Provided is a method for forming a pattern of an organic thin film semiconductor element. The method for forming a pattern of an organic thin film semiconductor element includes: preparing a mold structure having a groove; positioning the mold structure on an upper part of a substrate to enable the groove and the substrate to form a pipe; supplying an organic semiconductor material to a surface of the substrate; and hardening the organic semiconductor material..
Industry Academic Cooperation Foundation, Hallym University


Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated systems and methods


Solid-state transducers (“ssts”) and vertical high voltage ssts having buried contacts are disclosed herein. An sst die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure.
Micron Technology, Inc.


Solid state lighting devices with reduced crystal lattice dislocations and associated methods of manufacturing


Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and a plurality of hemispherical grained silicon (“hsg”) structures on the substrate surface of the substrate material.
Micron Technology, Inc.


Stacked nanowire device with variable number of nanowire channels


A method of forming a semiconductor structure including forming a stack of layers on a top surface of a substrate, the stack of layers including alternating layers of a semiconductor material and a sacrificial material, where a bottommost layer of the stack of layers is a top semiconductor layer of the substrate, patterning a plurality of material stacks from the stack of layers, each material stack including an alternating stack of a plurality of nanowire channels and a plurality of sacrificial spacers, the plurality of nanowire channels including the semiconductor material, and the plurality of sacrificial spacers including the sacrificial material, and removing at least one of the plurality of nanowire channels from at least one of the plurality of material stacks without removing one or more of the plurality of nanowire channels from an adjacent material stack.. .
Globalfoundries Inc.


Organic light emitting diode display having thin film transistor substrate using oxide semiconductor


A method for manufacturing an organic light emitting diode (oled) display can include forming a gate electrode on a substrate, forming a semiconductor layer by depositing a gate insulating layer and an oxide semiconductor material and patterning the oxide semiconductor material, forming an etch stopper on a central portion of the semiconductor layer, conducting a plasma treatment using the etch stopper as a mask to conductorize portions of the semiconductor layer exposed by the etch stopper for defining a channel area, a source area and a drain area, and forming a source electrode contacting portions of the conductorized source area and a drain electrode contacting portions of the conductorized drain area.. .
Lg Display Co., Ltd.


Graphene growth on a carbon-containing semiconductor layer


A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms.
Globalfoundries Inc.


Semiconductor component and manufacture


In accordance with an embodiment, a semiconductor component and a method for manufacturing a semiconductor component are provided. A first dielectric material is formed over a body of semiconductor material of the first conductivity type and a plurality of semiconductor fingers are formed over the first of dielectric material.
Semiconductor Components Industries, Llc


Integrated electronic device having a dissipative package, in particular dual side cooling package


Packaged semiconductor device having a frame, of conductive material; a body of semiconductor material, fixed to the frame through a first adhesive layer; a heat-sink element, fixed to the body through a second adhesive layer; and a packaging mass surrounding the body and, at least partially, the frame and the heat-sink element. The heat-sink element is formed by a heat-sink die facing, and coplanar to, a main face of the device and by a spacer structure, which includes a pair of pedestals projecting from the perimeter of the heat-sink die towards the body and rest on the body..
Stmicroelectronics S.r.l.


Methods of forming fin isolation regions under tensile-strained fins on finfet semiconductor devices


One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an nmos finfet device.. .
Globalfoundries Inc.


Methods of forming nmos and pmos finfet devices and the resulting product


One illustrative method disclosed herein includes, among other things, recessing first and second fins to define replacement fin cavities in a layer of insulating material, forming an initial strain relaxed buffer layer such that it only partially fills the replacement fin cavities, implanting carbon into the initial strain relaxed buffer layer in the nmos region, forming a channel semiconductor material on the initial strain relaxed buffer layer within the replacement fin cavities in both the nmos region and the pmos region to thereby define an nmos fin comprised of the channel semiconductor material and a carbon-doped strain relaxed buffer layer and a pmos fin comprised of the channel semiconductor material and the initial strain relaxed buffer layer and forming gate structures for the nmos and pmos devices.. .
Globalfoundries Inc.


High mobility transistors


An integrated circuit containing an n-channel finfet and a p-channel finfet has a dielectric layer over a silicon substrate. The fins of the finfets have semiconductor materials with higher mobilities than silicon.
Texas Instruments Incorporated


Localized region of isolated silicon over dielectric mesa


An integrated circuit is formed by forming an isolation mesa over a single crystal substrate which includes silicon, and forming a first epitaxial layer on the substrate by a selective epitaxial process so that a top surface of the first epitaxial layer is coplanar with the top surface of the isolation mesa. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on the first epitaxial layer and non-crystalline silicon-based material on the isolation mesa.
Texas Instruments Incorporated




Semiconductor Material topics:
  • Semiconductor
  • Semiconductor Material
  • Semiconductor Device
  • Transistors
  • Surfactant
  • Electric Conversion
  • Transparent Conductive Oxide
  • Semiconductor Substrate
  • Heating Devices
  • Semiconductor Devices
  • Organic Electroluminescence
  • Buffer Layer
  • Integrated Circuit
  • Crystallin
  • Electronic Device


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