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This page is updated frequently with new Semiconductor Material-related patent applications. Subscribe to the Semiconductor Material RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Material RSS RSS


Semiconductor device pn junction fabrication using optical processing of amorphous semiconductor material

Apparatus and methods of measuring minority carrier lifetime using a liquid probe

Sacrificial replacement extension layer to obtain abrupt doping profile

Date/App# patent app List of recent Semiconductor Material-related patents
09/11/14
20140256894
 Difluoro benzotriazolyl organic semiconductor material, preparation method and use thereof patent thumbnailnew patent Difluoro benzotriazolyl organic semiconductor material, preparation method and use thereof
Wherein both r1 and r2 are c1 to c20 alkyl, and n is an integer from 10 to 50. In the difluoro benzotriazolyl organic semiconductor material, since the 1,2,3-benzotriazole organic semiconductor material contains two fluorine atoms, the homo energy level is reduced by 0.11 ev, while the fluorine-substituted 1,2,3-benzotriazole has two imido groups with electron-withdrawing ability; the fluorine-substituted 1,2,3-benzotriazole is a heterocyclic compound with strong electron-withdrawing ability, and an alkyl chain can be easily introduced to the n-position of the n—h bond of the benzotriazole.
09/11/14
20140256139
 Self-aligned trench over fin patent thumbnailnew patent Self-aligned trench over fin
A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch.
09/11/14
20140256080
 Semiconductor device pn junction fabrication using optical processing of amorphous semiconductor material patent thumbnailnew patent Semiconductor device pn junction fabrication using optical processing of amorphous semiconductor material
Systems and methods for semiconductor device pn junction fabrication are provided. In one embodiment, a method for fabricating an electrical device having a p-n junction comprises: depositing a layer of amorphous semiconductor material onto a crystalline semiconductor base, wherein the crystalline semiconductor base comprises a crystalline phase of a same semiconductor as the amorphous layer; and growing the layer of amorphous semiconductor material into a layer of crystalline semiconductor material that is epitaxially matched to the lattice structure of the crystalline semiconductor base by applying an optical energy that penetrates at least the amorphous semiconductor material..
09/11/14
20140254146
 Multi-sequenced leds on two or more wires patent thumbnailnew patent Multi-sequenced leds on two or more wires
The present invention is generally directed to sequencing two or more leds on two or more wires; if more than two wires are used, any two pairs of wires can be used as a pair of wires. Each pair of wires can be used to sequence two or more leds, and a sequencer can control sequencing of leds on multiple wires connected in a group, or in multiple groups of multiple wires.
09/11/14
20140253925
 Surface emitting laser and optical coherence tomography apparatus equipped with surface emitting laser patent thumbnailnew patent Surface emitting laser and optical coherence tomography apparatus equipped with surface emitting laser
A surface emitting laser according to the present invention includes a lower reflector, a first spacer layer, an active layer, a second spacer layer composed of a semiconductor material, a gap section formed of at least one of vacuum and gas, and an upper reflector in the written order, and also includes a control mechanism that changes a distance between an interface between the second spacer layer and the gap section and an interface between the upper reflector and the gap section. An optical path length neff×d extending from an interface between the lower reflector and the first spacer layer to an interface between the second spacer layer and the gap section satisfies a predetermined relationship..
09/11/14
20140253174
 Logic circuit patent thumbnailnew patent Logic circuit
A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a nand circuit and a nor circuit. Switching between a nand circuit and a nor circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor.
09/11/14
20140253161
 Apparatus and methods of measuring minority carrier lifetime using a liquid probe patent thumbnailnew patent Apparatus and methods of measuring minority carrier lifetime using a liquid probe
Methods and apparatus for measuring minority carrier lifetimes using liquid probes are provided. In one embodiment, a method of measuring the minority carrier lifetime of a semiconductor material comprises: providing a semiconductor material having a surface; forming a rectifying junction at a first location on the surface by temporarily contacting the surface with a conductive liquid probe; electrically coupling a second junction to the semiconductor material at a second location, wherein the first location and the second location are physically separated; applying a forward bias to the rectifying junction causing minority carrier injection in the semiconductor material; measuring a total capacitance as a function of frequency between the rectifying junction and the second junction; determining an inflection frequency of the total capacitance; and determining a minority lifetime of the semiconductor material from the inflection frequency..
09/11/14
20140252552
 Semiconductor dies having substrate shunts and related fabrication methods patent thumbnailnew patent Semiconductor dies having substrate shunts and related fabrication methods
Die structures for electronic device packages and related fabrication methods are provided. An exemplary die structure includes a substrate having a first layer of semiconductor material including a semiconductor device formed thereon, a handle layer of semiconductor material, and a buried layer of dielectric material between the handle layer and the first layer.
09/11/14
20140252524
 Array of mutually isolated, geiger-mode, avalanche photodiodes and manufacturing method thereof patent thumbnailnew patent Array of mutually isolated, geiger-mode, avalanche photodiodes and manufacturing method thereof
An embodiment of array of geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type and housing an anode region, of a second conductivity type, facing a top surface of the body, a cathode-contact region, having the first conductivity type and a higher doping level than the body, facing a bottom surface of the body, an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the anode region and the cathode-contact region. The insulation region is formed by a first mirror region of polycrystalline silicon, a second mirror region of metal material, and a channel-stopper region of dielectric material, surrounding the first and second mirror regions..
09/11/14
20140252509
 Mems device and corresponding micromechanical structure with integrated compensation of thermo-mechanical stress patent thumbnailnew patent Mems device and corresponding micromechanical structure with integrated compensation of thermo-mechanical stress
A micromechanical structure of a mems device, integrated in a die of semiconductor material provided with a substrate and having at least a first axis of symmetry lying in a horizontal plane, has a stator structure, which is fixed with respect to the substrate, and a rotor structure, having a suspended mass, mobile with respect to the substrate and to the stator structure as a result of an external action, the stator structure having fixed sensing electrodes capacitively coupled to the rotor structure; a compensation structure is integrated in the die for compensation of thermo-mechanical strains. The compensation structure has stator compensation electrodes, which are fixed with respect to the substrate, are capacitively coupled to the rotor structure, and are arranged symmetrically to the fixed sensing electrodes with respect to the first axis of symmetry..
09/11/14
20140252501
new patent Sacrificial replacement extension layer to obtain abrupt doping profile
At least one gate structure having a first spacer located on a vertical sidewall thereof is provided on an uppermost surface of a semiconductor substrate. Exposed portions of the semiconductor substrate are then removed utilizing the at least one gate structure and first spacer as an etch mask.
09/11/14
20140252500
new patent Sacrificial replacement extension layer to obtain abrupt doping profile
At least one gate structure having a first spacer located on a vertical sidewall thereof is provided on an uppermost surface of a semiconductor substrate. Exposed portions of the semiconductor substrate are then removed utilizing the at least one gate structure and first spacer as an etch mask.
09/11/14
20140252479
new patent Semiconductor fin isolation by a well trapping fin portion
A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate.
09/11/14
20140252426
new patent Semiconductor structure with dielectric-sealed doped region
Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material.
09/11/14
20140252407
new patent Tunnel effect transistor
A tunnel effect transistor includes a channel made of an intrinsic semiconductor material; source and drain extension regions on either side of the channel, the source extension region being made of a semiconductor material doped according to a first type of doping p or n and the drain extension region being made of a semiconductor material doped according to a second type of doping opposite to said first type of doping; source and drain conductive regions respectively in contact with the source and drain extension regions; a gate structure including a gate dielectric layer in contact with the channel and a gate area arranged such that the gate dielectric layer is arranged between the gate area and the channel; and an area doped according to the first type of doping inserted between the channel and the drain extension region.. .
09/11/14
20140252366
new patent Semiconductor structure including buffer with strain compensation layers
A semiconductor structure includes a substrate and a semiconductor buffer structure overlying the substrate. The semiconductor buffer structure includes a semiconductor body of a gallium nitride material, and a stack of strain compensation layers.
09/11/14
20140252363
new patent Three dimensional memory structure
A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (fet) using the portion of the pillar as the body of the fet.. .
09/11/14
20140252358
new patent Methods and apparatus for mems devices with increased sensitivity
Methods and apparatus for forming mems devices. An apparatus includes at least a portion of a semiconductor substrate having a first thickness and patterned to form a moveable mass; a moving sense electrode forming the first plate of a first capacitance; at least one anchor patterned from the semiconductor substrate and having a portion that forms the second plate of the first capacitance and spaced by a first gap from the first plate; a layer of semiconductor material of a second thickness patterned to form a first electrode forming a first plate of a second capacitance and further patterned to form a second electrode overlying the at least one anchor and forming a second plate spaced by a second gap that is less than the first gap; wherein a total capacitance is formed that is the sum of the first capacitance and the second capacitance.
09/11/14
20140252341
new patent Pyrrolo pyrroledione-thenequinone compound, and preparation process and use thereof
Disclosed are a pyrrolo-pyrroledione-thiophenequinone compound as shown by formula i, a preparation process thereof and the use thereof as an organic semiconductor material. The preparation process for the compound of formula i comprises reacting nah, an α-bromine substituted pyrrolo-pyrroledione-thiophene oligomer as shown by formula ii and malononitrile sodium salt, in the presence of catalytic pd(pph3)4, and then adding to the reaction system saturated bromine water to carry out an oxidation reaction, so as to obtain the compound of formula i.
09/04/14
20140248739
Heating a furnace for the growth of semiconductor material
A multi-ingot furnace for the growth of crystalline semiconductor material has one or more heating devices for heating a hot zone in which crucibles containing semiconductor material are received. At least one of the heating devices is arranged to apply a predetermined differential heat flux profile across a horizontal cross-section of the semiconductor material in one or more of the crucibles, the predetermined differential heat flux profile being selected in dependence the position of the one or more crucibles in an array.
09/04/14
20140248728
Optoelectronic device with light directing arrangement and method of forming the arrangement
An optoelectronic device comprises a body of an indirect bandgap semiconductor material having a surface and a photon active region on one side of the surface. A light directing arrangement is formed integrally with the body on an opposite side of the surface..
09/04/14
20140247093
Phase locked loop and semiconductor device using the same
It is an object of the present invention to provide a phase locked loop in which a voltage signal input to a voltage controlled oscillator after a return from a stand-by state becomes constant in a short time and power consumption is reduced. A transistor including a semiconductor layer formed using an oxide semiconductor material is provided between an input terminal of a voltage controlled oscillator and a capacitor of a loop filter.
09/04/14
20140246683
Solid state lighting devices with reduced crystal lattice dislocations and associated methods of manufacturing
Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and a plurality of hemispherical grained silicon (“hsg”) structures on the substrate surface of the substrate material.
09/04/14
20140246651
Grown nanofin transistors
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (spe) process is performed to crystallise the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth.
09/04/14
20140246561
High dynamic range pixel having a plurality of photodiodes with a single implant
A high dynamic range image sensor pixel includes a short integration photodiode and a long integration photodiode disposed in semiconductor material. The long integration photodiode has a light exposure area that is substantially larger than a light exposure area of the short integration photodiode.
08/28/14
20140242788
Method of forming a high quality interfacial layer for a semiconductor device by performing a low temperature ald process
One illustrative method disclosed herein includes performing an atomic layer deposition (ald) process at a temperature of less than 400° c. To deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide..
08/28/14
20140242771
Method for manufacturing a semiconductor device
A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer.
08/28/14
20140241031
Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same
In some aspects, a memory cell is provided that includes a steering element and a memory element. The memory element includes a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer.
08/28/14
20140239435
Super-junction schottky pin diode
A semiconductor chip has an n+-doped substrate, above which an n-doped epilayer having trenches is introduced, the trenches being filled with p-doped semiconductor material and in each case having a highly p-doped region at their top side, such that an alternating arrangement of n-doped regions having a first width and p-doped regions having a second width is present. A first metal layer functioning as an anode is provided on the front side of the chip and forms a schottky contact with the n-doped epilayer and forms an ohmic contact with the highly p-doped regions.
08/28/14
20140239399
Semiconductor device having compressively strained channel region and method of making same
A semiconductor device and method making it utilize a three-dimensional channel region comprising a core of a first semiconductor material and an epitaxial covering of a second semiconductor material. The first and second semiconductor materials have respectively different lattice constants, thereby to create a strain in the epitaxial covering.
08/28/14
20140239398
U-shaped semiconductor structure
A method for forming a u-shaped semiconductor device includes forming trenches in a crystalline layer and epitaxially growing a u-shaped semiconductor material along sidewalls and bottoms of the trenches. The u-shaped semiconductor material is anchored, and the crystalline layer is removed.
08/28/14
20140239394
U-shaped semiconductor structure
A method for forming a u-shaped semiconductor device includes forming trenches in a crystalline layer and epitaxially growing a u-shaped semiconductor material along sidewalls and bottoms of the trenches. The u-shaped semiconductor material is anchored, and the crystalline layer is removed.
08/28/14
20140239388
Termination trench for power mosfet applications
Aspects of the present disclosure describe a termination structure for a power mosfet device. A termination trench may be formed into a semiconductor material and may encircle an active area of the mosfet.
08/28/14
20140239347
Structure and method for defect passivation to reduce junction leakage for finfet device
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (sti) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate.
08/28/14
20140239302
Semiconductor device and method for manufacturing the same
An object is to realize a hermetically sealed package which ensures long-term airtightness inside the package by sealing using a substrate, or a sealing structure for reducing destruction caused by pressure from the outside. A frame of a semiconductor material is provided over a first substrate, which is bonded to a second substrate having a semiconductor element so that the semiconductor element is located inside the frame between the first substrate and the second substrate.
08/28/14
20140239244
Vertical mosfet transistor, in particular operating as a selector in nonvolatile memory devices
A vertical mosfet transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region of the first conductivity type, arranged on top of the channel region and the buried conductive region; a gate insulation region, extending at the sides of and contiguous to the channel region; and a gate region extending at the sides of and contiguous to the gate insulation region..
08/28/14
20140239154
High dynamic range pixel having a plurality of amplifier transistors
A pixel cell for use in a high dynamic range image sensor includes a photodiode disposed in semiconductor material to accumulate charge in response to light incident upon the photodiode. A transfer transistor is disposed in the semiconductor material and is coupled between a floating diffusion and the photodiode.
08/21/14
20140235036
Hot-wire method for depositing semiconductor material on a substrate and device for performing the method
A hot wire device and method for depositing semiconductor material onto a substrate in a deposition chamber in which the ends of at least two filaments are clamped into a filament holder and heated by supplying current, wherein a voltage for generating an electrical current is applied in temporal succession to filaments made of differing materials so that a number of differing semiconductors corresponding to the number of consecutively heated filament materials can be consecutively deposited onto the substrate without opening the chamber.. .
08/21/14
20140235025
Semiconductor device and related fabrication methods
Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first vertical drift region of semiconductor material, a second vertical drift region of semiconductor material, and a buried lateral drift region of semiconductor material that abuts the vertical drift regions.
08/21/14
20140235018
Diamond particle mololayer heat spreaders and associated methods
Thermally regulated semiconductor devices having reduced thermally induced defects are provided, including associated methods. Such a device can include a heat spreader having a monolayer of diamond particles within a thin metal matrix and a semiconductor material thermally coupled to the heat spreader.
08/21/14
20140234977
Rolled-up, three-dimensional field-effect transistors and the use thereof in electronics, sensors and microfluidics
Field-effect transistors include at least two thin layers of a semiconductor material and of an electrically conductive gate material that are rolled up together. These two layers are arranged separated from one another by one or multiple barrier layers and this rolled-up multi-layer structure is integratable as field-effect transistors in circuits and/or in microfluid systems as sensors for the detection of fluids..
08/21/14
20140231979
Stacked assembly of a mems integrated device having a reduced thickness
An assembly of a mems integrated device envisages: a package having a base substrate with a main surface in a horizontal plane, and a coating set on the base substrate; a first body including semiconductor material and integrating a micromechanical structure, housed within the package on the base substrate; at least one second body including semiconductor material and integrating at least one electronic component, designed to be functionally coupled to the micromechanical structure, the first body and the second body being arranged within the package stacked in a vertical direction transverse to the horizontal plane. In particular, at least one between the first body and the base substrate defines a first recess, in which the second body is housed, at least in part..
08/21/14
20140231961
Semiconductor device and related fabrication methods
Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region.
08/21/14
20140231938
Micro-electro-mechanical device with buried conductive regions, and manufacturing process thereof
A mems device formed by a body; a cavity, extending above the body; mobile and fixed structures extending above the cavity and physically connected to the body via anchoring regions; and electrical-connection regions, extending between the body and the anchoring regions and electrically connected to the mobile and fixed structures. The electrical-connection regions are formed by a conductive multilayer including a first semiconductor material layer, a composite layer of a binary compound of the semiconductor material and of a transition metal, and a second semiconductor material layer..
08/21/14
20140231929
Transistors with isolation regions
A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions.
08/21/14
20140231886
Two-dimensional material stacked flexible photosensor
A flexible photosensor includes a flexible substrate, a gate on the flexible substrate, the gate including a conductive material having a planar structure, a gate insulating layer on the flexible substrate and the gate to at least cover the gate, the gate insulating layer including a non-conductive material having a planar structure, and a channel layer on the gate insulating layer, the channel layer including a semiconductor material having a planar structure.. .
08/21/14
20140231878
Collector-up bipolar junction transistors in bicmos technology
Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate.
08/21/14
20140231877
Collector-up bipolar junction transistors in bicmos technology
Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate.
08/21/14
20140231750
Quantum well infrared photodetectors using ii-vi material systems
A quantum well infrared photodetector (qwip) and method of making is disclosed. The qwip includes a plurality of epi-layers formed into multiple periods of quantum wells, each of the quantum wells being separated by a barrier, the quantum wells and barriers being formed of ii-vi semiconductor materials.
08/21/14
20140231678
Near infrared light source in bulk silicon
A light emitting device (10) comprises a body (12) of a semiconductor material having a first face (14) and at least one other face (16). At least one pn-junction (18) in the body is located towards the first face and is configured to be driven via contacts on the body into a light emitting mode.
08/14/14
20140227871
Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region
A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions.
08/14/14
20140227862
Semiconductor nanocrystals and methods
In one embodiment, a method for forming a coating comprising a semiconductor material on at least a portion of a population of semiconductor nanocrystals comprises providing a first mixture including semiconductor nanocrystals and an aromatic solvent, introducing one or more cation precursors and one or more anion precursors into the first mixture to form a reaction mixture for forming the semiconductor material, reacting the precursors in the reaction mixture, without the addition of an acid compound, under conditions sufficient to grow a coating comprising the semiconductor material on at least a portion of an outer surface of at least a portion of the semiconductor nanocrystals, and wherein an amide compound is formed in situ in the reaction mixture prior to isolating the coated semiconductor nanocrystals. In another embodiment, method for forming a coating comprising a semiconductor material on at least a portion of a population of semiconductor nanocrystals comprises providing a first mixture including semiconductor nanocrystals and a solvent, introducing an amide compound, one or more cation precursors and one or more anion precursors into the first mixture to form a reaction mixture for forming the semiconductor material, and reacting the precursors in the reaction mixture in the presence of the amide compound, under conditions sufficient to grow a coating comprising the semiconductor material on at least a portion of an outer surface of at least a portion of the semiconductor nanocrystals.
08/14/14
20140227826
Method for treating a semiconductor
Methods for treating a semiconductor material, and for making devices containing a semiconducting material, are presented. One embodiment is a method for treating a semiconductor material that includes a chalcogenide.
08/14/14
20140226427
Memory device word line drivers and methods
Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors.
08/14/14
20140226022
Optical output photodetector
An optical output photodetector includes a substrate having a semiconductor surface and at least one optical photodetector element on the semiconductor surface. The optical photodetector element includes a plurality of integrated sensing regions which collectively provide a plurality of different absorbance spectra.
08/14/14
20140225250
Methods and systems for fabrication of low-profile mems cmos devices
A mems integrated circuit including a plurality of layers where a portion includes one or more electronic elements on a semiconductor material substrate. The circuit includes a structure of interconnection layers having a bottom layer of conductor material and a top layer of conductor material where the layers are separated by at least one layer of dielectric material.
08/14/14
20140225231
Modulating bow of thin wafers
Apparatus and methods modulate the bowing of thin wafers. According to a method, a wafer is formed of semiconductor material.
08/14/14
20140225184
Method for inducing strain in vertical semiconductor columns
A vertical metal-oxide-semiconductor (mos) transistor includes a substrate and a nano-wire over the substrate. The nano-wire comprises a semiconductor material.
08/14/14
20140225082
Organic light-emitting diode
An organic light-emitting diode including a substrate; a first electrode on the substrate; a second electrode disposed opposite to the first electrode; an emission layer disposed between the first electrode and second electrode; and a first interlayer, a first hole transport layer, a second interlayer and a second hole transport layer disposed between the first electrode and the emission layer, wherein the first interlayer, the first hole transport layer, the second interlayer, and the second hole transport layer are stacked from the first electrode in order, and wherein the first interlayer and the second interlayer each independently include an n-type semiconductor material.. .
08/14/14
20140224965
Separation of doping density and minority carrier lifetime in photoluminescence measurements on semiconductor materials
Methods are presented for separating the effects of background doping density and effective minority carrier lifetime on photoluminescence (pl) generated from semiconductor materials. In one embodiment the background doping density is measured by another technique, enabling pl measurements to be analysed in terms of effective minority carrier lifetime.
08/14/14
20140224665
Semiconductor material, optical hydrogen generating device using same, and method of producing hydrogen
A semiconductor material of the present invention is a semiconductor material including an oxynitride containing at least one element selected from the group 4 elements and group 5 elements. In the oxynitride, part of at least one selected from oxygen and nitrogen is substituted with carbon.
08/14/14
20140224312
Deposition of a high surface energy thin film layer for improved adhesion of group i-iii-vi2 solar cells
A thin film photovoltaic cell includes a light absorption layer of group i-iii-vi2 semiconductor materials and a high surface energy thin film layer that improves adhesion between the light absorption layer and an underlying electrode layer. The high surface energy thin film either replaces or is deposited on top of the back electrode to decrease the formation of voids at the back interface during absorber growth/deposition and thereby enabling a wider process window and improved cell efficiencies.
08/07/14
20140220763
Memory devices and formation methods
A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types.
08/07/14
20140220751
Methods for forming semiconductor regions in trenches
A method includes recessing a portion of a semiconductor substrate between opposite isolation regions to form a recess. After the step of recessing, the portion of the semiconductor substrate includes a top surface.
08/07/14
20140220301
Epitaxial substrate having nano-rugged surface and fabrication thereof
The invention provides an epitaxial substrate and fabrication thereof. The epitaxial substrate according to the invention includes a crystalline substrate.
08/07/14
20140217553
Template layers for heteroepitaxial deposition of iii nitride semiconductor materials using hvpe processes
Methods of depositing iii-nitride semiconductor materials on substrates include depositing a layer of iii-nitride semiconductor material on a surface of a substrate in a nucleation hvpe process stage to form a nucleation layer having a microstructure comprising at least some amorphous iii-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate.
08/07/14
20140217544
Methods of forming a transistor device on a bulk substrate and the resulting device
One illustrative method disclosed herein includes forming a trench within an isolated region of a bulk semiconductor substrate, forming a region of an insulating material in the trench and forming a semiconductor material within the trench and above the upper surface of the region of insulating material. A substrate disclosed herein includes an isolated substrate region in a bulk semiconductor substrate, a region of an insulating material that is positioned within a trench defined in the isolated substrate region and a semiconductor material positioned within the trench and above the upper surface of the region of insulating material..
08/07/14
20140217500
Semiconductor device with low on resistance and high breakdown voltage
A semiconductor device includes an epitaxial layer of semiconductor material of a first conductivity type, a body region of a second (opposite) conductivity type extending into the epitaxial layer from a main surface of the epitaxial layer, a source region of the first conductivity type disposed in the body region, and a channel region extending laterally in the body region from the source region along the main surface. A charge compensation region of the second conductivity type can be provided under the body region which extends in a direction parallel to the main surface and terminates prior to a pn-junction between the source and body regions at the main surface, and/or an additional region of the first conductivity type which has at least one peak doping concentration each of which occurs deeper in the epitaxial layer from the main surface than a peak doping concentration of the device channel region..
08/07/14
20140217499
Methods for forming semiconductor regions in trenches
A structure includes a semiconductor substrate including a first semiconductor material. A portion of the semiconductor substrate extends between insulation regions in the semiconductor substrate.
08/07/14
20140217480
Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer
Disclosed herein are various methods of forming a silicon/germanium protection layer above source/drain regions of a transistor. One method disclosed herein includes forming a plurality of recesses in a substrate proximate the gate structure, forming a semiconductor material in the recesses, forming at least one layer of silicon above the semiconductor material, and forming a cap layer comprised of silicon germanium on the layer of silicon.
08/07/14
20140217467
Methods of forming substrates comprised of different semiconductor materials and the resulting device
Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (srb) layer between the first and second layers, forming a sidewall spacer on the sidewalls of an opening in the second layer, and forming a third semiconductor material in the opening, wherein the first, second and third semiconductor materials are different. A device includes first and second layers of first and second semiconductor materials and an srb layer positioned above the first layer.
08/07/14
20140217398
Thin-film transistor device and thin-film transistor display apparatus
A thin-film transistor (tft) device comprises a gate, a source, a drain, an insulation layer and an active area. The insulation layer electrically separates the gate from the source and the drain.
08/07/14
20140217374
Organic semiconductor material
Novel compounds useful as organic semiconductor material are described. Semiconductor devices containing said organic semiconductor material are also described..
08/07/14
20140217350
Arrays of memory cells and methods of forming an array of memory cells
An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines.
08/07/14
20140217157
Removal of electronic chips and other components from printed wire boards using liquid heat media
Systems and methods for the removal of electronic chips and other components from pwbs using liquid heat media are generally described. The systems and methods described herein can be used to remove solder, electronic chips (including those in which an integrated circuit is positioned on a piece of semiconductor material, such as silicon), and/or other electronic components from pwbs.


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Semiconductor Material topics: Semiconductor, Semiconductor Material, Semiconductor Device, Transistors, Surfactant, Electric Conversion, Transparent Conductive Oxide, Semiconductor Substrate, Heating Devices, Semiconductor Devices, Organic Electroluminescence, Buffer Layer, Integrated Circuit, Crystallin, Electronic Device

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