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Semiconductor Material patents



      
           
This page is updated frequently with new Semiconductor Material-related patent applications. Subscribe to the Semiconductor Material RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Material RSS RSS


Fin structure of semiconductor device

Fin structure of semiconductor device

Device including a transistor having a stressed channel region and method for the formation thereof

Device including a transistor having a stressed channel region and method for the formation thereof

Device including a transistor having a stressed channel region and method for the formation thereof

Semiconductor alloy fin field effect transistor

Date/App# patent app List of recent Semiconductor Material-related patents
12/11/14
20140363941
 Replacement gate electrode with a self-aligned dielectric spacer patent thumbnailReplacement gate electrode with a self-aligned dielectric spacer
A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions.
12/11/14
20140361336
 Fin structure of semiconductor device patent thumbnailFin structure of semiconductor device
The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width..
12/11/14
20140361335
 Device including a transistor having a stressed channel region and method for the formation thereof patent thumbnailDevice including a transistor having a stressed channel region and method for the formation thereof
A device includes a substrate, a p-channel transistor and an n-channel transistor. The substrate includes a first layer of a first semiconductor material and a second layer of a second semiconductor material.
12/11/14
20140361314
 Semiconductor alloy fin field effect transistor patent thumbnailSemiconductor alloy fin field effect transistor
Semiconductor alloy fin structures can be formed by recessing a semiconductor material layer including a first semiconductor material to form a trench, and epitaxially depositing a semiconductor alloy material of the first semiconductor material and a second semiconductor material within the trench. The semiconductor alloy material is epitaxially aligned to the first semiconductor material in the semiconductor material layer.
12/11/14
20140361300
 Bipolar device having a monocrystalline semiconductor intrinsic base to extrinsic base link-up region patent thumbnailBipolar device having a monocrystalline semiconductor intrinsic base to extrinsic base link-up region
Disclosed are bipolar devices, which incorporate an entirely monocrystalline link-up region between the intrinsic and extrinsic base layers, and methods of forming the devices. In the methods, a selective epitaxial deposition process grows monocrystalline semiconductor material for the extrinsic base layer on an exposed edge portion of a monocrystalline section of an intrinsic base layer.
12/11/14
20140360427
 Method for producing the growth of a semiconductor material patent thumbnailMethod for producing the growth of a semiconductor material
A method for producing the growth of a semiconductor material, in particular of type ii-vi, uses a melt of the semiconductor placed in a sealed bulb under vacuum or under controlled atmosphere, the bulb being subjected to a sufficient temperature gradient for first maintaining the melt in the liquid state, then causing its progressive crystallization from the surface towards the bottom. The method further comprises an element capable of floating on the surface of the melt, and equipped with a substantially central bore, intended for receiving a seed crystal for permitting the nucleation leading to the preparation of a seed crystal, and also supporting the seed crystal above the melt while maintaining it in contact with the melt in order to permit the continued crystallization from the seed crystal by lowering the temperature gradient..
12/04/14
20140357060
 Method for the formation of fin structures for finfet devices patent thumbnailMethod for the formation of fin structures for finfet devices
A soi substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material.
12/04/14
20140357040
 Method of making a semiconductor device using spacers for source/drain confinement patent thumbnailMethod of making a semiconductor device using spacers for source/drain confinement
A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto.
12/04/14
20140355995
 Optoelectronic device having improved optical coupling patent thumbnailOptoelectronic device having improved optical coupling
An optoelectronic device may include a package having a component for sending/receiving optical signals along a first direction, and a chip of semiconductor material housed within the package. The chip may have a main surface and a portion exposed on the main surface for sending/receiving the optical signals along a second direction different from the first direction.
12/04/14
20140353786
 Semiconductor detector with radiation shield patent thumbnailSemiconductor detector with radiation shield
A semiconductor radiation detector includes a bulk layer of semiconductor material. On a first side of said bulk layer is an arrangement of field electrodes and a collection electrode for collecting radiation-induced signal charges from said bulk layer.
12/04/14
20140353780
Detection structure for a mems acoustic transducer with improved robustness to deformation
A micromechanical structure for a mems capacitive acoustic transducer, has: a substrate of semiconductor material; a rigid electrode, at least in part of conductive material, coupled to the substrate; a membrane, at least in part of conductive material, facing the rigid electrode and coupled to the substrate, which undergoes deformation in the presence of incident acoustic pressure waves and is arranged between the substrate and the rigid electrode and has a first surface and a second surface, in fluid communication, respectively, with a first chamber and a second chamber, the first chamber being delimited at least in part by a first wall portion and by a second wall portion formed by the substrate, and the second chamber being delimited at least in part by the rigid electrode; and a stopper element, connected between the first and second wall portions for limiting the deformations of the membrane. At least one electrode-anchorage element couples the rigid electrode to the stopper element..
12/04/14
20140353767
Method for the formation of fin structures for finfet devices
On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer.
12/04/14
20140353762
Multi-orientation semiconductor devices employing directed self-assembly
A template material layer is deposited over a substrate, and is patterned with at least two trenches having different lengthwise directions. An array of polymer lines are formed by directed self-assembly of a copolymer material and a selective removal of one type of polymer material relative to another type within each trench such that the lengthwise direction of the polymer lines are parallel to the lengthwise sidewalls of the trench.
12/04/14
20140353761
Multi-orientation semiconductor devices employing directed self-assembly
A template material layer is deposited over a substrate, and is patterned with at least two trenches having different lengthwise directions. An array of polymer lines are formed by directed self-assembly of a copolymer material and a selective removal of one type of polymer material relative to another type within each trench such that the lengthwise direction of the polymer lines are parallel to the lengthwise sidewalls of the trench.
12/04/14
20140353760
Method to co-integrate sige and si channels for finfet devices
A method for co-integrating finfets of two semiconductor material types, e.g., si and sige, on a bulk substrate is described. Fins for finfets may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator.
12/04/14
20140353730
Low gate-to-drain capacitance fully merged finfet
A low gate-to-drain capacitance merged finfet and methods of manufacture are disclosed. The method includes forming a plurality of fins on a substrate.
12/04/14
20140353721
Bulk finfet with controlled fin height and high-k liner
A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate.
12/04/14
20140353715
Finfet device and fabrication method thereof
A transistor device may include a substrate that has a well portion. The transistor device may further include a source member and a drain member.
12/04/14
20140353714
Methods for making a semiconductor device with shaped source and drain recesses and related devices
A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack..
12/04/14
20140353680
Gallium nitride semiconductor structures with compositionally-graded transition layer
The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer.
12/04/14
20140353574
Field effect transistor structure comprising a stack of vertically separated channel nanowires
A field effect transistor structure comprises a source and a drain on a substrate, and a stack of n vertically separated channel nanowires isolated from the substrate and connecting the source and the drain, where n is an integer and 2≦n≦20. The channel nanowires collectively comprise at least two different thicknesses and/or at least two different dopant concentrations and/or at least two different semiconductor materials..
12/04/14
20140352742
Substrate processing apparatus
A substrate processing apparatus has a cup part for receiving processing liquid such as pure water which is splashed from a substrate. The cup part is formed of electrical insulation material or semiconductor material.
11/27/14
20140350366
Photoelectric conversion device and manufacturing method thereof
According to one embodiment, a photoelectric conversion device including a substrate having opaque interconnection layers, an insulating film formed on the substrate, and having a plurality of openings, light-emitting elements formed of the openings, each light-emitting element having an upper electrode layer, and light-receiving elements formed of the openings, each light-receiving element having an upper electrode layer, wherein a semiconductor material is different in the light-emitting element and the light-receiving element, the upper electrode layer both of the light-emitting element and the light-receiving element are formed as common electrodes, and each interconnection layer is formed on a region outside a region specified by the opening.. .
11/27/14
20140349459
Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same
A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material.
11/27/14
20140349457
Floating body memory cell apparatus and methods
Some embodiments include apparatus and methods having a base; a memory cell including a body, a source, and a drain; and an insulation material electrically isolating the body, the source, and the drain from the base, where the body is configured to store information. The base and the body include bulk semiconductor material.
11/27/14
20140349454
Methods of forming charge storage structures including etching diffused regions to form recesses
Methods are disclosed that include selectively etching diffused regions to form recesses in semiconductor material, and forming charge storage structures in the recesses. Additional embodiments are disclosed..
11/27/14
20140349449
Elemental semiconductor material contact for high electron mobility transistor
Portions of a top compound semiconductor layer are recessed employing a gate electrode as an etch mask to form a source trench and a drain trench. A low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material in the source trench and the drain trench.
11/27/14
20140347771
Protection device and related fabrication methods
Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base region of semiconductor material having a first conductivity type, a second base region of semiconductor material having the first conductivity type and a dopant concentration that is less than the first base region, a third base region of semiconductor material having the first conductivity type and a dopant concentration that is greater than the second base region, an emitter region of semiconductor material having a second conductivity type opposite the first conductivity type within the first base region, and a collector region of semiconductor material having the second conductivity type.
11/27/14
20140346612
Bulk semiconductor fins with self-aligned shallow trench isolation structures
A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer.
11/27/14
20140346589
Semiconductor device with charge compensation
A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer.
11/27/14
20140346588
Superjunction power device and manufacturing method
A method for manufacturing a semiconductor power device, comprising the steps of: forming a trench in a semiconductor body having a first type of conductivity; partially filling the trench with semiconductor material via epitaxial growth so as to obtain a first column having a second type of conductivity and having an internal cavity. The epitaxial growth includes simultaneously supplying a gas containing dopant ions of the second type of conductivity, hydrochloric acid hcl in gaseous form and dichlorosilane dcs in gaseous form, so that the ratio between the amount of hcl and the amount of dcs has a value of from 3.5 to 5.5..
11/27/14
20140346567
Elemental semiconductor material contactfor high electron mobility transistor
Portions of a top compound semiconductor layer are recessed employing a gate electrode as an etch mask to form a source trench and a drain trench. A low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material in the source trench and the drain trench.
11/27/14
20140346566
Contact metallurgy for self-aligned high electron mobility transistor
A metallization scheme employing a first refractory metal barrier layer, a group iiia element layer, a second refractory metal barrier layer, and an oxidation-resistant metallic layer is employed to form a source region and a drain region that provide electrical contacts to a compound semiconductor material layer. The first and second refractory metal barrier layer are free of nitrogen, and thus, do not introduce additional nitrogen into the compound semiconductor layer, while allowing diffusion of the group iiia element to form locally doped regions underneath the source region and the drain region.
11/27/14
20140346564
Multi-threshold voltage fets
A multi-threshold voltage (vt) field-effect transistor (fet) formed through strain engineering is provided. An embodiment integrated circuit device includes a first transistor including a first channel region over a first buffer, the first channel region formed from a iii-v semiconductor material and a second transistor including a second channel region over a second buffer, the second channel region formed from the iii-v semiconductor material, the second buffer and the first buffer having a lattice mismatch.
11/27/14
20140345517
Method for the formation of nano-scale on-chip optical waveguide structures
A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material.
11/20/14
20140343870
Determination of acceptor and donor dopant concentrations
The concentrations of three acceptor and donor dopants of a semiconductor sample are determined by solving a system of three equations. A first equation is obtained by measuring the free charge carrier concentration of the sample at low temperature, and in then confronting these measurements with a mathematical model suitable for these temperatures.
11/20/14
20140342575
Method for forming an interfacial layer on a semiconductor using hydrogen plasma
Techniques include a method of forming an interfacial passivation layer between a first semiconductor material (such as germanium) and a high-k gate dielectric. Such techniques include using a hydrogen-based plasma formed using a slotted-plane antenna plasma processing system.
11/20/14
20140342533
Method of strain and defect control in thin semiconductor films
A method of managing strain and preventing defect formation in semiconductor materials is described. In structures featuring two or more semiconductor materials with different lattice constants, buffer layers may be used to form deposition surfaces that result in defect-free semiconductor devices.
11/20/14
20140342524
Integrated circuit comprising an isolating trench and corresponding method
An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.. .
11/20/14
20140342522
Reducing variation by using combination epitaxy growth
A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (e/g) ratio of process gases used in the first growth stage; and performing a second growth stage with a second e/g ratio of process gases used in the second growth stage different from the first e/g ratio..
11/20/14
20140342494
Ohmic n-contact formed at low temperature in inverted metamorphic multijunction solar cells
A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact composed of a sequence of layers over the first subcell at a temperature of 280° c. Or less and having a contact resistance of less than 5×10−4 ohms-cm2..
11/20/14
20140342493
Radiation detector having a bandgap engineered absorber
A radiation detector is provided that includes a photodiode having a radiation absorber with a graded multilayer structure. Each layer of the absorber is formed from a semiconductor material, such as hgcdte.
11/20/14
20140342486
Elemental semiconductor material contact for gan-based light emitting diodes
A vertical stack including a p-doped gan portion, a multi-quantum-well, and an n-doped gan portion is formed on an insulator substrate. The p-doped gan portion may be formed above, or below, the multi-quantum-well.
11/20/14
20140342485
Elemental semiconductor material contact for high indium content ingan light emitting diodes
A vertical stack including a p-doped gan portion, a multi-quantum-well including indium gallium nitride layers, and an n-doped transparent conductive material portion is formed on an insulator substrate. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a surface of the p-doped gan portion.
11/20/14
20140342254
Photo-catalytic systems for production of hydrogen
A system for splitting water and producing hydrogen for later use as an energy source may include the use of a photoactive material including pccn and plasmonic nanoparticles. A method for producing the pccn may include a semiconductor nanocrystal synthesis and an exchange of organic capping agents with inorganic capping agents.
11/20/14
20140340963
Apparatus and methods including source gates
Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described..
11/20/14
20140339706
Integrated circuit package with an interposer formed from a reusable carrier substrate
An integrated circuit package includes an interposer and an integrated circuit die. The interposer is formed from a layer of semiconductor material that is separated from a bulk portion of a semiconductor substrate, and the integrated circuit die is coupled to the interposer.
11/20/14
20140339677
Hybrid plasma-semiconductor transistors, logic devices and arrays
A hybrid plasma semiconductor device has a thin and flexible semiconductor base layer. An emitter region is diffused into the base layer forming a pn-junction.
11/20/14
20140339631
Innovative approach of 4f2 driver formation for high-density rram and mram
Some embodiments of the present disclosure relate to a memory array comprising memory cells having vertical gate-all-around (gaa) selection transistors. In some embodiments, the memory array has a source region disposed within an upper surface of a semiconductor body, and a semiconductor pillar of semiconductor material extending outward from the upper surface of the semiconductor body and having a channel region and an overlying drain region.
11/20/14
20140339624
Charge-retaining transistor, array of memory cells, and methods of forming a charge-retaining transistor
A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes first semiconductor material alongside the inter-gate dielectric.
11/20/14
20140339621
Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells including metal
Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells are disclosed. One such string of memory cells can be formed at least partially in a stack of materials comprising a plurality of alternating levels of control gate material and insulator material.
11/20/14
20140339611
Stacked semiconductor nanowires with tunnel spacers
A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material.
11/20/14
20140339591
Optoelectronic semiconductor chip and method of production thereof
An optoelectronic semiconductor chip includes a semiconductor layer stack including a nitride compound semiconductor material on a carrier substrate, wherein the semiconductor layer stack includes an active layer that emits an electromagnetic radiation, the semiconductor layer stack being arranged between a layer of a first conductivity and a layer of a second conductivity, the layer of the first conductivity is adjacent a front of the semiconductor layer stack, the layer of the first conductivity electrically connects to a first electrical connection layer covering at least a portion of a back of the semiconductor layer stack, and the layer of the second conductivity type electrically connects to a second electrical connection layer arranged at the back.. .
11/20/14
20140339577
Optoelectronic semiconductor chip
An optoelectronic semiconductor chip includes a multiplicity of active regions, arranged at a distance from one another, and a reflective layer arranged at an underside of the multiplicity of active regions, wherein at least one of the active regions has a main extension direction, one of the active regions has a core region formed with a first semiconductor material, the active region has an active layer, covering the core region at least in directions transversely with respect to the main extension direction of the active region, the active region has a cover layer formed with a second semiconductor material and covers the active layer at least in directions transversely with respect to the main extension direction of the active region, and the reflective layer reflects electromagnetic radiation generated during operation in the active layer.. .
11/20/14
20140339507
Stacked semiconductor nanowires with tunnel spacers
A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material.
11/20/14
20140339503
Elemental semiconductor material contact for gan-based light emitting diodes
A vertical stack including a p-doped gan portion, a multi-quantum-well, and an n-doped gan portion is formed on an insulator substrate. The p-doped gan portion may be formed above, or below, the multi-quantum-well.
11/20/14
20140339502
Elemental semiconductor material contact for high indium content ingan light emitting diodes
A vertical stack including a p-doped gan portion, a multi-quantum-well including indium gallium nitride layers, and an n-doped transparent conductive material portion is formed on an insulator substrate. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a surface of the p-doped gan portion.
11/20/14
20140339498
Radiation-emitting semiconductor chip
A radiation-emitting semiconductor chip includes a semiconductor body with a semiconductor layer sequence, wherein the semiconductor body with the semiconductor layer sequence extends in a vertical direction between a first major face and a second major face; the semiconductor layer sequence includes an active region that generates radiation, a first region of a first conduction type and a second region of a second conduction type differing from the first conduction type; the first region extends in a vertical direction between the first major face and the active region; the second region extends in a vertical direction between the second major face and the active region; at least one layer of the active region is based on an arsenide compound semiconductor material; and relative to its respective extent in the vertical direction, the first region or the second region is based in a proportion of at least half on a phosphide compound semiconductor material.. .
11/20/14
20140338728
Patterned organic semiconductor layers
A method of patterning organic semiconductor layers is disclosed. In one aspect, a method for forming a patterned organic semiconductor layer on a substrate includes providing a plurality of first electrodes on a substrate.
11/13/14
20140332903
Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same
A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material.
11/13/14
20140332892
Stringer-free gate electrode for a suspended semiconductor fin
At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin.
11/13/14
20140332890
Stringer-free gate electrode for a suspended semiconductor fin
At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin.
11/13/14
20140332854
Stress release structures for metal electrodes of semiconductor devices
This invention teaches stress release metal electrodes for gate, drain and source in a field effect transistor and stress release metal electrodes for emitter, base and collector in a bipolar transistor. Due to the large difference in the thermal expansion coefficients between semiconductor materials and metal electrodes, significant strain and stresses can be induced in the devices during the fabrication and operation.
11/13/14
20140332838
Light emitting devices having light coupling layers with recessed electrodes
A light emitting device comprises a first layer of an n-type semiconductor material, a second layer of a p-type semiconductor material, and an active layer between the first layer and the second layer. A light coupling structure is disposed adjacent to one of the first layer and the second layer.
11/13/14
20140332809
Semiconductor device
With a combination of a transistor including an oxide semiconductor material and a transistor including a semiconductor material other than an oxide semiconductor, a semiconductor device with a novel structure in which data can be retained for a long time and does not have a limitation on the number of writing can be obtained. When a connection electrode for connecting the transistor including a semiconductor material other than an oxide semiconductor to the transistor including an oxide semiconductor material is smaller than an electrode of the transistor including a semiconductor material other than an oxide semiconductor that is connected to the connection electrode, the semiconductor device with a novel structure can be highly integrated and the storage capacity per unit area can be increased..
11/13/14
20140332806
Semiconductor device
One object is to provide a new semiconductor device whose standby power is sufficiently reduced. The semiconductor device includes a first power supply terminal, a second power supply terminal, a switching transistor using an oxide semiconductor material and an integrated circuit.
11/13/14
20140332805
Semiconductor device
A semiconductor device having a novel structure is provided. The semiconductor device includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor.
11/13/14
20140332802
Semiconductor device
In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period..
11/13/14
20140332756
Nitride semiconductor light-emitting device and method of manufacturing the same
A nitride semiconductor light-emitting device is formed of an n-type nitride semiconductor layer, a trigger layer, a v-pit expanding layer, a light-emitting layer, and a p-type nitride semiconductor layer provided in this order. The light-emitting layer has a v-pit formed therein.
11/06/14
20140329380
Formation of semiconductor structures with variable gate lengths
A plurality of doped sacrificial semiconductor material portions of a first width and a plurality of doped sacrificial semiconductor material portions of a second width, which is different from the first width, are provided on a sacrificial gate dielectric material. Exposed portions of the sacrificial dielectric material are removed.
11/06/14
20140329370
Layer transfer of silicon onto iii-nitride material for heterogenous integration
An integrated silicon and iii-n semiconductor device may be formed by growing iii-n semiconductor material on a first silicon substrate having a first orientation. A second silicon substrate with a second, different, orientation has a release layer between a silicon device film and a carrier wafer.


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Semiconductor Material topics: Semiconductor, Semiconductor Material, Semiconductor Device, Transistors, Surfactant, Electric Conversion, Transparent Conductive Oxide, Semiconductor Substrate, Heating Devices, Semiconductor Devices, Organic Electroluminescence, Buffer Layer, Integrated Circuit, Crystallin, Electronic Device

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