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Semiconductor Material patents

      

This page is updated frequently with new Semiconductor Material-related patent applications.




 Multistep deposition of zinc oxide on gallium nitride patent thumbnailMultistep deposition of zinc oxide on gallium nitride
A method for fabricating a zinc oxide (zno) conductive film on a semiconductor material, including depositing a doped zno seed layer on a diode, wherein the zno seed layer forms an electrical contact to the diode; and depositing a zno layer on the zno seed layer, wherein the zno seed layer and the zno layer each have a thickness, a crystal quality, and a doping level such that (1) the diode comprising iii-nitride material is turned on with a turn on voltage of 2.75 volts or less applied across the zno layers and the diode, and (2) a contact resistance, of a structure comprising the zno layers and the diode, is lower as compared to a contact resistance of a structure comprising the zno layer directly on the diode without the zno seed layer.. .
The Regents Of The University Of California


 Compound-semiconductor photovoltaic cell and manufacturing  compound-semiconductor photovoltaic cell patent thumbnailCompound-semiconductor photovoltaic cell and manufacturing compound-semiconductor photovoltaic cell
A compound-semiconductor photovoltaic cell includes a first photoelectric conversion cell made of a first compound-semiconductor material which lattice matches with gaas or ge; a first tunnel junction layer arranged on a deep side farther than the first photoelectric conversion cell in a light incident direction, and including a first p-type (alx1ga1-x1)y1in1-y1as (0≦x1<1, 0<y1≦1) layer and a first n-type (alx2ga1-x2)y2in1-y2p (0≦x2<1, 0<y2<1) layer; and a second photoelectric conversion cell arranged on a deep side farther than the first tunnel junction layer in the light incident direction, and made of a second compound-semiconductor material which is a gaas-based semiconductor material. The first photoelectric conversion cell and the second photoelectric conversion cell are joined via the first tunnel junction layer, and a lattice constant of the first n-type (alx2ga1-x2)y2in1-y2p layer is greater than a lattice constant of the first photoelectric conversion cell..
Rich Company, Ltd.


 Methods of making source/drain regions positioned inside u-shaped semiconductor material using source/drain placeholder structures patent thumbnailMethods of making source/drain regions positioned inside u-shaped semiconductor material using source/drain placeholder structures
One illustrative method disclosed herein includes, among other things, forming a liner semiconductor material within a trench, the liner material defining a transistor cavity, and forming spaced-apart source/drain placeholder structures that are at least partially positioned within the transistor cavity, the spaced-apart source/drain placeholder structures defining a gate cavity therebetween where a portion of the liner semiconductor material is exposed within the gate cavity. The method further includes forming a gate structure within the gate cavity and, after forming the gate structure, removing at least a portion of the source/drain placeholder structures to define a plurality of source/drain cavities within the transistor cavity on opposite sides of the gate structure, and forming a source/drain structure in each of the source drain cavities..
Globalfoundries Inc.


 Semiconductor device with gate inside u-shaped channel and methods of making such a device patent thumbnailSemiconductor device with gate inside u-shaped channel and methods of making such a device
One illustrative method disclosed herein includes, among other things, forming a trench in a semiconductor substrate, forming a liner semiconductor material above the entire interior surface of the trench, the liner semiconductor material defining a transistor cavity, forming a gate structure that is at least partially positioned within the transistor cavity, and performing at least one epitaxial deposition process to form a source region structure and a drain region structure on opposite sides of the gate structure, wherein at least a portion of each of the source region structure and the drain region structure is positioned within the transistor cavity.. .
Globalfoundries Inc.


 High electron mobility transistor and  forming the same using atomic layer deposition technique patent thumbnailHigh electron mobility transistor and forming the same using atomic layer deposition technique
A hemt made of nitride semiconductor materials is disclosed. The hemt includes the gan channel layer, the inaln barrier layer, and the n-type gan regions formed beneath the source electrode and the drain electrode at a temperature such that the inaln barrier layer in the crystal quality thereof is not degraded, lower than 800° c.
Sumitomo Electric Industries, Ltd.


 Vertical junction finfet device and  manufacture patent thumbnailVertical junction finfet device and manufacture
A vertical junction field effect transistor (jfet) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends.
Stmicroelectronics, Inc.


 Punch through stopper in bulk finfet device patent thumbnailPunch through stopper in bulk finfet device
A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure.
International Business Machines Corporation


 Devices and methods of creating elastic relaxation of epitaxially grown lattice mismatched films patent thumbnailDevices and methods of creating elastic relaxation of epitaxially grown lattice mismatched films
Devices and methods of creating elastic relaxation of epitaxially grown lattice mismatched films for semiconductor devices are provided. One method includes, for instance: obtaining a wafer including a substrate; epitaxially growing at least one first silicon germanium (sige) layer over the wafer; and epitaxially growing at least one second sige layer over the at least one first sige layer.
Globalfoundries Inc.


 Dual-material mandrel for epitaxial crystal growth on silicon patent thumbnailDual-material mandrel for epitaxial crystal growth on silicon
In one example, a method for fabricating a semiconductor device includes etching a layer of silicon to form a plurality of fins and growing layers of a semiconductor material directly on sidewalls of the plurality of fins, wherein the semiconductor material and surfaces of the sidewalls have different crystalline properties.. .
International Business Machines Corporation


 Semiconductor device and driving method thereof patent thumbnailSemiconductor device and driving method thereof
A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node.
Semiconductor Energy Laboratory Co., Ltd.


Collars for under-bump metal structures and associated systems and methods

The present technology is directed to manufacturing collars for under-bump metal (ubm) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material.
Micron Technology, Inc.

Semiconductor device and manufacturing the same

An object is to realize a hermetically sealed package which ensures long-term airtightness inside the package by sealing using a substrate, or a sealing structure for reducing destruction caused by pressure from the outside. A frame of a semiconductor material is provided over a first substrate, which is bonded to a second substrate having a semiconductor element so that the semiconductor element is located inside the frame between the first substrate and the second substrate.
Semiconductor Energy Laboratory Co., Ltd.

Removal of semiconductor growth defects

After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces.
Globalfoundries Inc.

Semiconductor device and manufacturing method thereof

A number of variations may include a method that may include depositing a first layer on a first semiconductor layer in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer. The first layer may include a first metal and a second metal.
Semiconductor Components Industries, Llc

Cdzno/si tandem cell for photoelectrochemical water dissociation

Here we present an apparatus comprising a photoelectrochemical cell connected a photovoltaic device, comprised of a layer with a thick n-type absorber and a layer comprising a thin p-type hole emitter. The photoelectrochemical cell has binary, metal-oxide semiconductors with wide bandgaps comprising high electron affinities relative to other semiconductor materials allowing for n-type doping..

Complementary metal oxide semiconductor device with iii-v optical interconnect having iii-v epitaxial semiconductor material formed using lateral overgrowth

An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate.
International Business Machines Corporation

Pressure sensor, especially pressure difference sensor

The pressure sensor of the invention includes at least one platform, at least one measuring membrane 30, and a transducer, wherein the measuring membrane comprises a semiconductor material, wherein the measuring membrane, enclosing a pressure chamber, is secured on the platform, wherein the measuring membrane is contactable with at least one pressure and is elastically deformable in a pressure-dependent manner, wherein the transducer provides an electrical signal dependent on deformation of the measuring membrane, wherein the platform has a membrane bed, on which the measuring membrane lies in the case of overload, in order to support the measuring membrane, wherein the membrane bed 21 has a glass layer 20, whose surface faces the measuring membrane and forms a wall of the pressure chamber, wherein the surface of the glass layer has a contour, which is suitable for supporting the measuring membrane 30 in the case of overload, characterized in that the contour of the membrane bed 21 is obtainable by a sagging of an unsupported region of a glass plate at increased temperature, due to the force of gravity on the unsupported region of the glass plate, and subsequent cooling of the glass plate.. .
Endress+hauser Gmbh + Co. Kg

Controlled growth of nanoscale wires

The present invention generally relates to nanoscale wires, and to methods of producing nanoscale wires. In some aspects, the nanoscale wires are nanowires comprising a core which is continuous and a shell which may be continuous or discontinuous, and/or may have regions having different cross-sectional areas.
President And Fellows Of Harvard College

Microelectromechanical sensor device with reduced stress-sensitivity and corresponding manufacturing process

A mems device is provided with: a supporting base, having a bottom surface in contact with an external environment; a sensor die, which is of semiconductor material and integrates a micromechanical detection structure; a sensor frame, which is arranged around the sensor die and is mechanically coupled to a top surface of the supporting base; and a cap, which is arranged above the sensor die and is mechanically coupled to a top surface of the sensor frame, a top surface of the cap being in contact with an external environment. The sensor die is mechanically decoupled from the sensor frame..
Stmicroelectronics S.r.l.

Organic semiconductor material

[in the formula (1), t1 and t2 each independently represent an alkoxy group, a thioalkoxy group, a thiophene ring optionally substituted by a hydrocarbon group or an organosilyl group, a thiazole ring optionally substituted by a hydrocarbon group or an organosilyl group, or a phenyl group optionally substituted by a hydrocarbon group, an alkoxy group, a thioalkoxy group, an organosilyl group, a halogen atom or a trifluoromethyl group; and b1 and b2 each represent a thiophene ring optionally substituted by a hydrocarbon group, a thiazole ring optionally substituted by a hydrocarbon group, or an ethynylene group].. .

Semiconductor nanocrystals and compositions and devices including same

A semiconductor nanocrystal including a core comprising a first semiconductor material comprising at least three chemical elements and a shell disposed over at least a portion of the core, the shell comprising a second semiconductor material, wherein the semiconductor nanocrystal is capable of emitting light with an improved photoluminescence quantum efficiency. Also disclosed are populations of semiconductor nanocrystals, compositions and devices including a semiconductor nanocrystal capable of emitting light with an improved photoluminescence quantum efficiency.
Qd Vision, Inc.

Mos transistor and manufacturing the same

A mos transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions.
Stmicroelectronics (crolles 2) Sas

Thin film transistor substrate and fabricating the same

A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the gate electrode and includes an oxide semiconductor material; and a source electrode and a drain electrode disposed on the semiconductor layer, where the drain electrode is spaced apart from the source electrode. The source electrode and the drain electrode each include a barrier layer and a main wiring layer, the a main wiring layer is disposed on the barrier layer, and the barrier layer includes a first metal layer disposed on the semiconductor layer, and a second metal layer disposed on the first metal layer..
Samsung Display Co., Ltd.

Finfet device having a channel defined in a diamond-like shape semiconductor structure

The present disclosure provides a finfet device. The finfet device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions..
Taiwan Semiconductor Manufacturing Company Ltd.

Fin structure for a finfet device

A fin structure for a fin field effect transistor (finfet) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (sti) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the sti region, the first fin spaced apart from the second fin by a width of the first semiconductor material.
Taiwan Semiconductor Manufacturing Company, Ltd.

Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method

A transistor device is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at a position where a gate is to be located. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening.
Stmicroelectronics, Inc.

Methods of forming cmos based integrated circuit products using disposable spacers

Disclosed herein is a method of forming a cmos integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material..
Globalfoundries Inc.

Formation of nickel silicon and nickel germanium structure at staggered times

A semiconductor device includes a substrate, first and second metals, and a second semiconductor material. The substrate includes a first semiconductor material and has first and second substrate portions.
Taiwan Semiconductor Manufacturing Company Limited

Guided-wave photodetector apparatus employing mid-bandgap states of semiconductor materials, and fabrication methods for same

Guided-wave photodetectors based on absorption of infrared photons by mid-bandgap states in non-crystal semiconductors. In one example, a resonant guided-wave photodetector is fabricated based on a polysilicon layer used for the transistor gate in a soi cmos process without any change to the foundry process flow (‘zero-change’ cmos).

Wide bandgap semiconductor switching device with wide area schottky junction, and manufacturing process thereof

A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.. .
Stmicroelectronics S.r.l.

Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded sige source/drain

A semiconductor device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The semiconductor fin includes a channel region formed of a first semiconductor material interposed between opposing embedded source/drain regions formed of a second semiconductor material different from the first semiconductor material.
International Business Machines Corporation

Composite spacer enabling uniform doping in recessed fin devices

A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial semiconductor material is present on at least one of a source region portion and a drain region portion on the fin structure.
International Business Machines Corporation

Active regions with compatible dielectric layers

A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material.

Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded sige source/drain

A semiconductor device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The semiconductor fin includes a channel region formed of a first semiconductor material interposed between opposing embedded source/drain regions formed of a second semiconductor material different from the first semiconductor material.
International Business Machines Corporation

Composite spacer enabling uniform doping in recessed fin devices

A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial semiconductor material is present on at least one of a source region portion and a drain region portion on the fin structure.
International Business Machines Corporation

Methods and systems for reducing dislocation defects in high concentration epitaxy processes

Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures.
Shanghai Huali Microelectronics Corporation

Semiconductor device with surface integrated focusing element and producing a semiconductor device with focusing element

The semiconductor device comprises a semiconductor substrate (1), a sensor or sensor array (2) arranged at a main surface (10) of the substrate, an integrated circuit (3) arranged at or above the main surface, and a focusing element (17) comprising recesses (4) formed within a further main surface (11) of the substrate opposite the main surface. The focusing element may be arranged opposite the sensor or sensor array (2), which may be a photosensor or photodetector or an array of photosensors or photodetectors, for instance.
Ams Ag

Formation of ohmic contacts for a device provided with a region made of iii-v material and a region made of another semiconductor material

B) carrying out at least one thermal annealing so as to form on the first semiconductor regions first contact zones and on the second semiconductor regions second contact zones based on a semiconductor and metal compound while increasing the n-doping of the iii-v material.. .

Flip chip backside mechanical die grounding techniques

A semiconductor device includes an integrated circuit attached to a chip carrier in a flip chip configuration. A substrate extends to a back surface of the integrated circuit, and an interconnect region extends to a front surface of the integrated circuit.
Texas Instruments Incorporated

Flip chip backside die grounding techniques

An integrated circuit is attached to a chip carrier in a flip chip configuration. An electrically conductive conformal layer is disposed on a back surface of the substrate of the integrated circuit.
Texas Instruments Incorporated

Dicing method

The dicing method comprises the steps of providing a substrate (1) of semiconductor material, the substrate having a main surface (10), where integrated components (3) of chips (13) are arranged, and a rear surface (11) opposite the main surface, fastening a first handling wafer above the main surface, thinning the substrate at the rear surface, and forming trenches (20) penetrating the substrate and separating the chips by a single etching step after the substrate has been thinned.. .
Ams Ag

Use of ion beam etching to generate gate-all-around structure

Various embodiments herein relate to methods and apparatus for performing anisotropic ion beam etching to form arrays of channels. The channels may be formed in semiconductor material, and may be used in a gate-all-around device.
Lam Research Corporation

Hybrid ion-sensitive field-effect transistor

Ion-sensitive field-effect transistors including channel regions of inorganic semiconductor material and organic gate junctions are provided for detecting biological materials or reactions within an electrolyte. The transistors may include self-assembled monolayers to passivate a surface of the inorganic semiconductor material.
International Business Machines Corporation

High mobility polymer organic field-effect transistors by blade-coating semiconductor:insulator blend solutions

Conjugated polymer-based organic field-effect transistors have garnered attention since the solution processability of the semiconductor material raises the possibility of lower device fabrication costs, and considerable progress has been made on achieving high mobility systems. Further improvements in charge carrier mobility while using non-specialized deposition techniques and minimizing the volume of semiconductor used in the fabrication process are important considerations for practical implementation.
The Regents Of The University Of California

Four junction solar cell for space applications

A four junction solar cell having an upper first solar subcell composed of a semiconductor material having a first band gap; a second solar subcell adjacent to said first solar subcell and composed of a semiconductor material having a second band gap smaller than the first band gap and being lattice matched with the upper first solar subcell; a third solar subcell adjacent to said second solar subcell and composed of a semiconductor material having a third band gap smaller than the second band gap and being lattice matched with the second solar subcell; and a fourth solar subcell adjacent to said third solar subcell and composed of a semiconductor material having a fourth band gap smaller than the third band gap; wherein the fourth subcell has a direct bandgap of greater than 0.75 ev.. .
Solaero Technologies Corp.

Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors

Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate..
International Business Machines Corporation

Non-planar quantum well device having interfacial layer and forming same

Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group iv or iii-v semiconductor materials and includes a fin structure.
Intel Corporation

Strained finfet device fabrication

A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.. .
International Business Machines Corporation

Strained finfet device fabrication

A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.. .
International Business Machines Corporation

Pixel structure and manufacturing method thereof background

A method for manufacturing a pixel structure is provided. A patterned semiconductor material layer, an insulation material layer, and a gate electrode material layer are formed in sequence on a substrate to form a stacked structure.
Chunghwa Picture Tubes, Ltd.

Strain release in pfet regions

A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (ssoi) structure, the ssoi structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the ssoi structure, forming a gate structure over a portion of at least one fin in a nfet region, forming a gate structure over a portion of at least one fin in a pfet region, removing the gate structure over the portion of the at least one fin in the pfet region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pfet region, such that the new gate structure surrounds the portion on all four sides.. .
International Business Machines Corporation

Strained finfet device fabrication

A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.. .
International Business Machines Corporation

Semiconductor memory device and manufacturing the same

A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked.
Kabushiki Kaisha Toshiba

High-k gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type iii-v semiconductor material and silicon germanium semiconductor material

An electrical device that includes at least one n-type field effect transistor including a channel region in a type iii-v semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers.
International Business Machines Corporation

Optical semiconductor device

The present invention provides an optical semiconductor device for improving minimization and increase of detection precision. An optical semiconductor device a1 of the present invention includes: a substrate 1, including a semiconductor material, and including a main surface 111 and a back surface 112; a semiconductor light-emitting element 7a at the substrate; a semiconductor light-receiving element 7b at the substrate; a conductive layer 3, conducting the semiconductor light-emitting element 7a and the semiconductor light-receiving element 7b; and an insulating layer 2 between at least a portion of the conductive layer 3 and the substrate; wherein the substrate 1 includes a recess 14 recessed from the main surface 111 and including a bottom surface 142a of a light-emitting side recess where the semiconductor light-emitting element 7a is disposed, and a bottom surface 142b of a light-receiving side recess where the semiconductor light-receiving element 7b is disposed; a light-emitting side transparent portion 18a for light from the semiconductor light-emitting element 7a to pass through the bottom surface 142a of the light-emitting side recess to the back surface 112; and a light-receiving side transparent portion 18b for light from the back surface 112 to pass through the bottom surface 142b of the light-receiving side recess to the semiconductor light-receiving element 7b..
Rohm Co., Ltd.

Strained finfet device fabrication

A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.. .
International Business Machines Corporation

Selective epitaxy using epitaxy-prevention layers

A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material..
International Business Machines Corporation

Method for the production of a nitride compound semiconductor layer

Described is a method for producing a nitride compound semiconductor layer, involving the steps of:—depositing a first seed layer (1) comprising a nitride compound semiconductor material on a substrate (10);—desorbing at least some of the nitride compound semiconductor material in the first seed layer from the substrate (10);—depositing a second seed layer (2) comprising a nitride compound semiconductor material; and—growing the nitride compound semiconductor layer (3) containing a nitride compound semiconductor material onto the second seed layer (2).. .
Osram Opto Semiconductors Gmbh



Semiconductor Material topics:
  • Semiconductor
  • Semiconductor Material
  • Semiconductor Device
  • Transistors
  • Surfactant
  • Electric Conversion
  • Transparent Conductive Oxide
  • Semiconductor Substrate
  • Heating Devices
  • Semiconductor Devices
  • Organic Electroluminescence
  • Buffer Layer
  • Integrated Circuit
  • Crystallin
  • Electronic Device


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