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Semiconductor Material patents



      
           
This page is updated frequently with new Semiconductor Material-related patent applications. Subscribe to the Semiconductor Material RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Material RSS RSS


Schottky device and method of manufacture

Semiconductor Components Industries

Schottky device and method of manufacture

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

International Business Machines

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

International Business Machines

Tunnel field-effect transistors with a gate-swing broken-gap heterostructure

Date/App# patent app List of recent Semiconductor Material-related patents
03/26/15
20150087140
 Film forming method, film forming device, and film forming system patent thumbnailnew patent Film forming method, film forming device, and film forming system
A film forming method according to an embodiment includes: (a) a step of supplying a first precursor gas of a semiconductor material into a processing vessel in which a processing target substrate is disposed, the first precursor gas being adsorbed onto the processing target substrate during the step; (b) a step of supplying a second precursor gas of a dopant material into the processing vessel, the second precursor gas being adsorbed onto the processing target substrate during the step; and (c) a step of generating the plasma of a reaction gas in the processing vessel, a plasma treatment being performed during the step so as to modify a layer adsorbed onto the processing target substrate.. .
Tokyo Electron Limited
03/26/15
20150087090
 Monitor test key of epi profile patent thumbnailnew patent Monitor test key of epi profile
A method and apparatus for estimating a height of an epitaxially grown semiconductor material in other semiconductor devices. The method includes epitaxially growing first, second, and third portions of semiconductor material on a first semiconductor device, measuring a height of the third portion of semiconductor material and a height of the first or second portion of semiconductor material, measuring a first saturation current through the first and second portions of semiconductor material, measuring a second saturation current through the first and third portions of semiconductor material, and preparing a model of the first saturation current relative to the height of the first or second portion of semiconductor material and the second saturation current relative to an average of the height of the first and third portions of semiconductor material.
Taiwan Semiconductor Manufacturing Company, Ltd.
03/26/15
20150084153
 Schottky device and  manufacture patent thumbnailnew patent Schottky device and manufacture
A schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant profile. In accordance with an embodiment, the schottky device is formed from a semiconductor material of a first conductivity type.
Semiconductor Components Industries, Llc
03/26/15
20150084120
 Charge-compensation semiconductor device patent thumbnailnew patent Charge-compensation semiconductor device
An active area of a semiconductor body includes a first charge-compensation structure having spaced apart n-type pillar regions, and an n-type first field-stop region of a semiconductor material in ohmic contact with a drain metallization and the n-type pillar regions and having a doping charge per area higher than a breakdown charge per area of the semiconductor material. A punch-through area of the semiconductor body includes a p-type semiconductor region in ohmic contact with a source metallization, a floating p-type body region and an n-type second field-stop region.
Infineon Technologies Austria Ag
03/26/15
20150084096
 Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels patent thumbnailnew patent Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels
A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench.
International Business Machines Corporation
03/26/15
20150084095
 Method for producing a transistor patent thumbnailnew patent Method for producing a transistor
The invention concerns a method for producing a transistor. The gate of the transistor is produced after having produced source and drain electrodes of the transistor.
Commissariat A L'energie Atomique Et Aux Ene Alt
03/26/15
20150084091
 Tunnel field-effect transistors with a gate-swing broken-gap heterostructure patent thumbnailnew patent Tunnel field-effect transistors with a gate-swing broken-gap heterostructure
Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed.
International Business Machines Corporation
03/26/15
20150084074
 Gallium nitride material and device deposition on graphene terminated wafer and  forming the same patent thumbnailnew patent Gallium nitride material and device deposition on graphene terminated wafer and forming the same
A method of forming an epitaxial semiconductor material that includes forming a graphene layer on a semiconductor and carbon containing substrate and depositing a metal containing monolayer on the graphene layer. An epitaxial layer of a gallium containing material is formed on the metal containing monolayer.
International Business Machines Corporation
03/26/15
20150083969
 Nanocrystal particles and processes for synthesizing the same patent thumbnailnew patent Nanocrystal particles and processes for synthesizing the same
A nanocrystal particle including at least one semiconductor material and at least one halogen element, the nanocrystal particle including: a core comprising a first semiconductor nanocrystal; and a shell surrounding the core and comprising a crystalline or amorphous material, wherein the halogen element is present as being doped therein or as a metal halide. .
Samsung Electronics Co., Ltd.
03/26/15
20150083036
 Gallium nitride material and device deposition on graphene terminated wafer and  forming the same patent thumbnailnew patent Gallium nitride material and device deposition on graphene terminated wafer and forming the same
A method of forming an epitaxial semiconductor material that includes forming a graphene layer on a semiconductor and carbon containing substrate and depositing a metal containing monolayer on the graphene layer. An epitaxial layer of a gallium containing material is formed on the metal containing monolayer.
International Business Machines Corporation
03/19/15
20150080654

Endoscope


An endoscope (1) includes a first beam path (3) formed at least at a distal end (2), and an image recording chip (5), which captures the first beam path (3). The endoscope includes a shutter apparatus (7) having a shutter element (8) composed of a semiconductor material, which is formed in the first beam path (3).
SchÖlly Fiberoptic Gmbh
03/19/15
20150079803

Method of forming strain-relaxed buffer layers


Implementations described herein generally relate to methods for relaxing strain in thin semiconductor films grown on another semiconductor substrate that has a different lattice constant. Strain relaxation typically involves forming a strain relaxed buffer layer on the semiconductor substrate for further growth of another semiconductor material on top.
Applied Materials, Inc.
03/19/15
20150079766

Optimized fabricating patterns of iii-v semiconductor material on a semiconductor substrate


With r being determined to be greater than tan(θ).. .
03/19/15
20150079765

High aspect ratio memory hole channel contact formation


A method of fabricating a semiconductor device, such as a three-dimensional monolithic nand memory string, includes etching a select gate electrode over a first gate insulating layer over a substrate to form an opening, forming a second gate insulating layer over the sidewalls of the opening, forming a sacrificial spacer layer over the second gate insulating layer on the sidewalls of the opening, and etching the first gate insulating layer over the bottom surface of the opening to expose the substrate, removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening, and forming a protrusion comprising a semiconductor material within the opening and contacting the substrate, wherein the second gate insulating layer is located between the select gate electrode and first and second side surfaces of the protrusion.. .
Sandisk Technologies, Inc.
03/19/15
20150079751

Fin field effect transistor with merged metal semiconductor alloy regions


Raised active regions having faceted semiconductor surfaces are formed on semiconductor fins by selective epitaxy such that the raised active regions are not merged among one another, but are proximal to one another by a distance less than a thickness of a metal semiconductor alloy region to be subsequently formed. A contiguous metal semiconductor alloy region is formed by depositing and reacting a metallic material with the semiconductor material of raised active regions.
International Business Machines Corporation
03/19/15
20150079750

Tilt implantation for forming finfets


Methods for fabrication of fin devices for an integrated circuit are provided. Fin structures are formed in a semiconductor material, where the fin structures include sidewalls and tops.
Taiwan Semiconductor Manufacturing Company Limited
03/19/15
20150079733

Three-dimensional system-in-a-package


A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a cte of less than 10 ppm/° c. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package.
Tessera, Inc.
03/19/15
20150079725

Method and apparatus providing multi-step deposition of thin film layer


A multi-stage method and apparatus for vaporizing and depositing a tellurium containing semiconductor material on a substrate.. .
First Solar, Inc.
03/19/15
20150079717

Apparatus and methods for fabricating solar cells


A method for fabricating a solar cell generally comprises delivering a solar cell substructure to a chamber. Electromagnetic radiation is generated using a wave generating device that is coupled to the chamber such that the wave generating device is positioned proximate to the solar cell substructure.
Tsmc Solar Ltd.
03/19/15
20150078703

Hybrid optical apparatuses including optical waveguides


Described are embodiments of hybrid optical apparatuses including anti-resonant optical waveguides, and methods for making such apparatuses and systems. In one embodiment, a hybrid optical apparatus may include a first semiconductor region including an active region of one or more layers of semiconductor materials and a second semiconductor region coupled with the first semiconductor region.
03/19/15
20150076677

Cte matched interposer and making


The present interposer makes it possible to tailor the coefficient of thermal expansion of the interposer to match components to be attached thereto within very wide ranges. The semiconductor interposer, includes a substrate of a semiconductor material having a first side and an opposite second side.
Silex Microsystems Ab
03/19/15
20150076651

Thermocouple, thermopile, infrared ray sensor and manufacturing infrared ray sensor


An infrared ray sensor includes a thermopile. The thermopile includes a first semiconductor material part and a second semiconductor material part, the first semiconductor material part and the second semiconductor material part are laminated, and a dielectric film is provided between the first semiconductor material part and the second semiconductor material part..
Ricoh Company, Ltd.
03/19/15
20150076607

Fin field effect transistor with merged metal semiconductor alloy regions


Raised active regions having faceted semiconductor surfaces are formed on semiconductor fins by selective epitaxy such that the raised active regions are not merged among one another, but are proximal to one another by a distance less than a thickness of a metal semiconductor alloy region to be subsequently formed. A contiguous metal semiconductor alloy region is formed by depositing and reacting a metallic material with the semiconductor material of raised active regions.
International Business Machines Corporation
03/19/15
20150076604

Field effect transistor including a recessed and regrown channel


At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region.
International Business Machines Corporation
03/19/15
20150076586

Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device


A memory film layer is formed in a memory opening through an alternating stack of first material layers and second material layers. A sacrificial material layer is deposited on the memory film layer.
Sandisk Technologies, Inc.
03/19/15
20150076507

Epitaxy substrate, producing an epitaxy substrate and optoelectronic semiconductor chip comprising an epitaxy substrate


An epitaxy substrate (11, 12, 13) for a nitride compound semiconductor material is specified, which has a nucleation layer (2) directly on a substrate (1) wherein the nucleation layer (2) has at least one first layer (21) composed of alon with a column structure. A method for producing an epitaxy substrate and an optoelectronic semiconductor chip comprising an epitaxy substrate are furthermore specified..
Osram Opto Semiconductors Gmbh
03/19/15
20150076449

Semiconductor device and manufacturing method thereof


A semiconductor device includes a superlattice buffer layer formed on a substrate. An upper buffer layer is formed on the superlattice buffer layer.
Fujitsu Limited
03/19/15
20150075606

Integrated conductive substrate, and electronic device employing same


Provided are an integrated conductive substrate simultaneously serving as a substrate and an electrode, and an electronic device using the same. The integrated conductive substrate includes a conductive layer containing iron, which has a first surface having a first root mean square roughness, and a semiconductor layer containing a semiconductor material, which has a second surface having a second root mean square roughness and is formed on the first surface.
Postech Academy - Industry Foundation
03/19/15
20150075599

Pillar structured multijunction photovoltaic devices


A device operable to convert light to electricity, comprising: a substrate comprising a semiconductor material, one or more structures essentially perpendicular to the substrate, one or more layers conformally disposed on the one or more structures wherein the one or more structures and the one or more layers form one or more junctions, and an electrically conductive material disposed on the substrate in the area between the one or more structures.. .
Zena Technologies, Inc.
03/19/15
20150075578

Thermoelectric conversion material and manufacturing same


The present invention provides a thermoelectric conversion material having a reduced thermal conductivity and having an improved figure of merit, and a method for producing the material. The thermoelectric conversion material has, as formed on a resin substrate having recesses, a thermoelectric semiconductor layer formed of a thermoelectric semiconductor material, wherein the resin substrate comprises one formed by curing a resin layer of a curable resin composition.
Lintec Corporation
03/12/15
20150072512

Methods and apparatuses including strings of memory cells formed along levels of semiconductor material


Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes a stack comprised of a number of levels of single crystal silicon and a number of levels of dielectric material.
Micron Technology, Inc.
03/12/15
20150072495

High-mobility multiple-gate transistor with improved on-to-off current ratio


A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin.
Taiwan Semiconductor Manufacturing Company, Ltd.
03/12/15
20150071319

Emission source and forming the same


In various embodiments, an emission source may be provided. The emission source may also include a gain medium including a halide semiconductor material.
Nanyang Technological University
03/12/15
20150069570

Integrated circuit structure with active and passive devices in different tiers


An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein.
Taiwan Semiconductor Manufacturing Company, Ltd.
03/12/15
20150069567

Superjunction structures for power devices and methods of manufacture


A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type..
Fairchild Semiconductor Corporation
03/12/15
20150069526

Fin field effect transistor including asymmetric raised active regions


Merged and unmerged raised active regions on semiconductor fins can be simultaneously formed on a same substrate by control of growth rates of a deposited semiconductor material on surfaces of the semiconductor fins. In one embodiment, a growth-rate-retarding dopant can be implanted by angled ion implantation onto sidewall surfaces of first semiconductor fins on which retardation of growth rates is desired, while second semiconductor fins are masked by a masking layer.
International Business Machines Corporation
03/12/15
20150069474

Isolation structure of fin field effect transistor


The disclosure relates to a fin field effect transistor (finfet). An exemplary finfet comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material, wherein a bottom portion of the upper portion comprises a dopant with a first peak concentration; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and an isolation structure surrounding the fin structure, wherein a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration..
Taiwan Semiconductor Manufacturing Company, Ltd.
03/12/15
20150069443

Light-emitting diode with local photonic crystals


The light-emitting diode includes first and second layers of semiconductor material, having opposite conductivity types, an active light-emitting area located between the first and second layers of semiconductor material, an electrode arranged on the first layer of semiconductor material and a photonic crystal formed in the first layer of semiconductor material. The photonic crystal and the electrode are separated by a distance optimized to simultaneously promote the electric injection and minimize the light absorption in the led..
Commissariat A L'energie Atomique Et Aux Energies
03/12/15
20150069328

Stacked nanowire device with variable number of nanowire channels


A method of forming a semiconductor structure including forming a stack of layers on a top surface of a substrate, the stack of layers including alternating layers of a semiconductor material and a sacrificial material, where a bottommost layer of the stack of layers is a top semiconductor layer of the substrate, patterning a plurality of material stacks from the stack of layers, each material stack including an alternating stack of a plurality of nanowire channels and a plurality of sacrificial spacers, the plurality of nanowire channels including the semiconductor material, and the plurality of sacrificial spacers including the sacrificial material, and removing at least one of the plurality of nanowire channels from at least one of the plurality of material stacks without removing one or more of the plurality of nanowire channels from an adjacent material stack.. .
International Business Machines Corporation
03/12/15
20150069327

Fin field-effect transistors with superlattice channels


Finfet structures may be formed including superlattice fins. The structure may include a superlattice fin of alternating layers of silicon-germanium with a germanium concentration of approximately 10% to 80% and a second semiconductor material.
International Business Machines Corporation
03/12/15
20150069043

Anneal module for semiconductor wafers


An anneal module for annealing semiconductor material wafers and similar substrates reduces particle contamination and oxygen ingress while providing uniform heating including for 500° c. Processes.
Applied Materials, Inc.
03/12/15
20150068604

Spalling methods to form multi-junction photovoltaic structure


A method cleaving a semiconductor material that includes providing a germanium substrate having a germanium and tin alloy layer is present therein. A stressor layer is deposited on a surface of the germanium substrate.
International Business Machines Corporation
03/12/15
20150068586

Array of photovoltaic cells


A solar energy harvesting and storage system is disclosed having a dual-sided lithographically integrated light-to-electrical energy converter. The integrated light-to-electrical energy converter has at least one array of photovoltaic, cells having an array of optoelectronic components, each of which have a compound optical structure that spatially separates light into multiple wavelengths and a p/n junction having a gradient of semiconductor materials and/or dopants responsive to a narrow band of wavelengths.
Ftl Systems, Inc.
03/05/15
20150065671

Organic semiconductor material


A compound represented by the formula (1). A polymer compound comprising the compound.
Sumitomo Chemical Company, Limited
03/05/15
20150064933

Crystallization of amorphous films and grain growth using combination of laser and rapid thermal annealing


A method is disclosed for crystallizing semiconductor material so that it has large grains of uniform size comprising delivering a first energy exposure of high intensity and short duration, and then delivering at least one second energy exposures of low intensity and long duration. The first energy exposure heats the substrate to a high temperature for a duration less than about 0.1 sec.
Applied Materials, Inc.
03/05/15
20150064884

Trench sidewall protection for selective epitaxial semiconductor material formation


A method of forming a semiconductor device includes forming an insulator layer over a substrate; opening a trench in the insulator layer so as to expose one or more semiconductor structures formed on the substrate; forming a protective layer on sidewalls of the trench; subjecting the substrate to a precleaning operation in preparation for epitaxial semiconductor formation, wherein the protective layer prevents expansion of the sidewalls of the trench as a result of the precleaning operation; and forming epitaxial semiconductor material within the trench and over the exposed one or more semiconductor structures.. .
International Business Machines Corporation
03/05/15
20150064874

Dummy fin formation by gas cluster ion beam


Finfet structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (gcib) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide.
International Business Machines Corporation
03/05/15
20150064865

Memory devices including vertical pillars and methods of manufacturing and operating the same


In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate.
Samsung Electronics Co., Ltd.
03/05/15
20150061078

Compound semiconductor structure


A semiconductor structure comprises a substrate comprising a first crystalline semiconductor material, a dielectric layer, above the substrate, defining an opening, a second crystalline semiconductor material at least partially filling the opening, and a crystalline interlayer between the substrate and the second crystalline semiconductor material. The first crystalline semiconductor material and the second crystalline semiconductor material are lattice mismatched, and the crystalline interlayer comprises an oxygen compound.
International Business Machines Corporation
03/05/15
20150061077

Trench sidewall protection for selective epitaxial semiconductor material formation


A method of forming a semiconductor device includes forming an insulator layer over a substrate; opening a trench in the insulator layer so as to expose one or more semiconductor structures formed on the substrate; forming a protective layer on sidewalls of the trench; subjecting the substrate to a precleaning operation in preparation for epitaxial semiconductor formation, wherein the protective layer prevents expansion of the sidewalls of the trench as a result of the precleaning operation; and forming epitaxial semiconductor material within the trench and over the exposed one or more semiconductor structures.. .
International Business Machines Corporation
03/05/15
20150061076

High density resistor


At least one three dimensional semiconductor fin is formed from a top semiconductor material of a substrate. A dielectric material is formed along vertical sidewalls and an upper surface of the at least one three dimensional semiconductor fin.
International Business Machines Corporation
03/05/15
20150061038

Semiconductor device


The reliability of a power misfet made of a nitride semiconductor material is improved. A strain relaxation film is disposed between a polyimide film and a gate electrode, to suppress a stress exerted on an electron supply layer and a channel layer from the polyimide film, and suppress a stress strain generated in the electron supply layer and the channel layer.
Renesas Electronics Corporation
03/05/15
20150061010

Structure for improved contact resistance and extension diffusion control


Semiconductor structures are provided including a raised source region comprising, from bottom to top, a source-side phosphorus doped epitaxial semiconductor material portion and a source-side arsenic doped epitaxial semiconductor material portion and located on one side of a gate structure, and a raised drain region comprising from bottom to top, a drain-side phosphorus doped epitaxial semiconductor material portion and a drain-side arsenic doped epitaxial semiconductor material portion and located on another side of the gate structure.. .
International Business Machines Corporation
03/05/15
20150060998

Semiconductor device and manufacturing same


In one embodiment, a method of manufacturing a semiconductor device includes forming, on a semiconductor substrate, a sacrificial semiconductor pillar having a pillar-like shape extending in a first direction perpendicular to a main surface of the semiconductor substrate, and being formed of a first semiconductor material. The method further includes forming, around the sacrificial semiconductor pillar, a channel semiconductor layer having a tube-like shape extending in the first direction, and being formed of a second semiconductor material different from the first semiconductor material.
Kabushiki Kaisha Toshiba
03/05/15
20150060997

Suspended body field effect transistor


A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed.
International Business Machines Corporation
03/05/15
20150060990

Transistors, methods of manufacturing the same, and electronic devices including the transistors


Provided are transistors, methods of manufacturing the same, and electronic devices including the transistors. A transistor includes a channel layer having a multi-layer structure having first and second layers, the first and second semiconductor layers including a plurality of elements having respective concentrations, and the first layer is disposed closer to a gate than the second layer.
Samsung Electronics Co., Ltd.
03/05/15
20150060957

Three-dimensional gate-wrap-around field-effect transistor


A three-dimensional gate-wrap-around field-effect transistor (gwafet). The gwafet includes a substrate of iii-v semiconductor material.
Board Of Regents, The University Of Texas System
03/05/15
20150060853

Semiconductor device


A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used. A p-type oxide semiconductor material is contained in an n-type oxide semiconductor film, whereby carriers which are generated in the oxide semiconductor film without intention can be reduced.
Semiconductor Energy Laboratory Co., Ltd.
03/05/15
20150060802

Electronic device, manufacturing method thereof, and image display device


There is provided an electronic device including an electrode structure, an insulating layer, and an active layer. The active layer is formed from an organic semiconductor material.
Sony Corporation
03/05/15
20150060800

Organic thin film transistor, preparing method thereof, and preparation equipment


An organic thin film transistor, a preparing method thereof, and a preparation equipment. The preparation equipment of an organic thin film transistor comprises: forming a gate electrode, a gate insulating layer, an organic semiconductor layer, and source-drain electrodes on a substrate; the step of forming the organic semiconductor layer comprises: blade-coating a solution in which an organic semiconductor material used to forming the organic semiconductor layer is dissolved to form the organic semiconductor layer.
Boe Technology Group, Co., Ltd.
03/05/15
20150060771

Atomistic quantum dots


A quantum device is provided that includes controllably quantum mechanically coupled dangling bonds extending from a surface of a semiconductor material. Each of the controllably quantum mechanically coupled dangling bonds has a separation of at least one atom of the semiconductor material.
National Research Council Of Canada
02/26/15
20150056791

Depression filling method and processing apparatus


A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor substrate is provided. The depression penetrating the insulating film is configured so as to extend to the semiconductor substrate.
Tokyo Electron Limited
02/26/15
20150056752

Substrateless power device packages


A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer.. .
Alpha And Omega Semiconductor Incorporated
02/26/15
20150056751

Die edge sealing structures and related fabrication methods


Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region.
02/26/15
20150055677

Determination of the interstitial oxygen concentration in a semiconductor sample


A method for determining the oxygen concentration of a sample made from p-type semiconductor material includes a thermal treatment step to form the thermal donors, a measuring step of the charge carrier concentration of the sample at a temperature between 0 k and 100 k, a step of determining the thermal donor concentration of the sample from the charge carrier concentration and the temperature of the sample, and a step of determining the interstitial oxygen concentration from the thermal donor concentration.. .
Commissariat A L'energie Atomique Et Aux Energies Alternatives
02/26/15
20150055425

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory


Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology.
Unity Semiconductor Corporation


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Semiconductor Material topics: Semiconductor, Semiconductor Material, Semiconductor Device, Transistors, Surfactant, Electric Conversion, Transparent Conductive Oxide, Semiconductor Substrate, Heating Devices, Semiconductor Devices, Organic Electroluminescence, Buffer Layer, Integrated Circuit, Crystallin, Electronic Device

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