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Semiconductor Material patents



      

This page is updated frequently with new Semiconductor Material-related patent applications.




Date/App# patent app List of recent Semiconductor Material-related patents
05/26/16
20160149083 
 Semiconductor material including different crystalline orientation zones and related production process patent thumbnailnew patent Semiconductor material including different crystalline orientation zones and related production process
The intermediate layer being intended to be vaporised spontaneously during the step consisting of growing the layer of element iii nitride via epitaxy.. .

05/26/16
20160149025 
 Semiconductor device and  manufacturing the same patent thumbnailnew patent Semiconductor device and manufacturing the same
Provided is a technique of securing reliability of a gate insulating film, as much as in a si power mosfet, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an sic power mosfet. In order to achieve this object, in the in the sic power mosfet, the gate electrode ge is formed in contact with the gate insulating film gox, and is formed of the polycrystalline silicon film pf1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film pf2 formed in contact with the polycrystalline silicon film pf1, and having any thickness..
Hitachi Ltd.


05/26/16
20160149024 
 High-electron mobility transistor and process to form the same patent thumbnailnew patent High-electron mobility transistor and process to form the same
An electron device formed by primarily nitrides semiconductor materials and a method to form the electron device are disclosed. The electron device includes, on the sic substrate, a buffer layer of aln, a channel layer of gan, and an electron supplying layer of algan.
Sumitomo Electric Industries, Ltd.


05/26/16
20160149022 
 Heterojunction field effect transistor (hfet) variable gain amplifier having variable transconductance patent thumbnailnew patent Heterojunction field effect transistor (hfet) variable gain amplifier having variable transconductance
A heterojunction semiconductor field effect transistor hfet having a pair of layers of different semiconductor materials forming a quantum well within the structure to support the 2deg. Source, drain and gate electrodes are disposed above the channel.
Raytheon Company


05/26/16
20160148870 
 Low-k dielectric pore sealant and metal-diffusion barrier formed by doping and  forming the same patent thumbnailnew patent Low-k dielectric pore sealant and metal-diffusion barrier formed by doping and forming the same
A diffusion barrier and a method to form the diffusion bather are disclosed. A trench structure is formed in an inter layer dielectric (ild).
Samsung Electronics Co., Ltd.


05/26/16
20160148846 
 Semiconductor structure containing low-resistance source and drain contacts patent thumbnailnew patent Semiconductor structure containing low-resistance source and drain contacts
Semiconductor structures having a source contact and a drain contact that exhibit reduced contact resistance and methods of forming the same are disclosed. In one embodiment of the present application, the reduced contact resistance is provided by forming a layer of a dipole metal or metal-insulator-semiconductor (mis) oxide between an epitaxial semiconductor material (providing the source region and the drain region of the device) and an overlying metal semiconductor alloy.
International Business Machines Corporation


05/26/16
20160148807 
 Polycrystalline semiconductor nanostructured material patent thumbnailnew patent Polycrystalline semiconductor nanostructured material
A method for producing a network of nanostructures from at least one semiconductor material, including a step of forming nanostructures on the surface of a substrate, at least a part of the nanostructures having areas of contact between each other, comprising, in sequence and after the step of forming: a step of deoxidising the surface of the nanostructures and a step of reinforcing the bond between the nanostructures at the contact areas.. .
Institut Polytechnique De Grenoble


05/26/16
20160146752 
 Device for detecting at least one gaseous analyte and  the production thereof patent thumbnailnew patent Device for detecting at least one gaseous analyte and the production thereof
A device for detecting at least one gaseous analyte comprises a detection section including a semiconductor substrate and at least one sensor element, which is arranged on the semiconductor substrate. The at least one sensor element includes two electrodes and a solid electrolyte layer arranged between the electrodes.
Robert Bosch Gmbh


05/26/16
20160146692 
 Package for semiconductor devices sensitive to mechanical and thermo-mechanical stresses, such as mems pressure sensors patent thumbnailnew patent Package for semiconductor devices sensitive to mechanical and thermo-mechanical stresses, such as mems pressure sensors
A surface mounting device has one body of semiconductor material such as an asic, and a package surrounding the body. The package has a base region carrying the body, a cap and contact terminals.
Stmicroelectronics, Inc.


05/26/16
20160145767 
 Deposition systems having access gates at desirable locations, and related methods patent thumbnailnew patent Deposition systems having access gates at desirable locations, and related methods
Deposition systems include a reaction chamber, and a substrate support structure disposed at least partially within the reaction chamber. The systems further include at least one gas injection device and at least one vacuum device, which together are used to flow process gases through the reaction chamber.
Soitec


05/19/16
20160141529 

Method for producing an organic cmos circuit and organic cmos circuit protected against uv radiation


An organic cmos circuit including a substrate having an n-type organic transistor and a p-type organic transistor formed thereon, the transistors respectively including a layer of n-type semiconductor material and a layer of p-type semiconductor material. A surface of each of the semiconductor material layers, opposite to the substrate, is covered with an anti-ultraviolet layer made of electrically-insulating material absorbing and/or reflecting ultra-violet rays..
Commissariat A L'energie Atomique Et Aux Energies Alternatives


05/19/16
20160141463 

Composite having semiconductor structures embedded in a matrix


Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot.

05/19/16
20160141408 

Super junction field effect transistor with internal floating ring


A super junction field effect transistor (fet) device includes a charge compensation region disposed on a substrate of semiconductor material. The charge compensation region includes a set of strip-shaped p− type columns, a floating ring-shaped p− type column that surrounds the set of strip-shaped p− type columns, and a set of ring-shaped p− type columns that surrounds the floating ring-shaped p− type column.
Ixys Corporation


05/19/16
20160141294 

Three-dimensional memory structure with multi-component contact via structure and making thereof


A contact via structure can include a ruthenium portion formed by selective deposition of ruthenium on a semiconductor surface at the bottom of a contact trench. The ruthenium-containing portion can reduce contact resistance at the interface with an underlying doped semiconductor region.
Sandisk Technologies Inc.


05/19/16
20160141220 

Hetero-bipolar transistor and producing the same


A semiconductor device provided with a substrate made of material except for semiconductors and having thermal conductivity greater than that of the semiconductor material. The semiconductor device provides, on the support, a metal layer, a primary mesa, and electrodes formed on the primary mesa.
Sumitomo Electric Industries, Ltd.


05/19/16
20160141205 

Finfets with different fin height and epi height setting


An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/19/16
20160140450 

Atomistic quantum dots


A quantum device is provided that includes controllably quantum mechanically coupled dangling bonds extending from a surface of a semiconductor material. Each of the controllably quantum mechanically coupled dangling bonds has a separation of at least one atom of the semiconductor material.
The Governors Of The University Of Alberta


05/12/16
20160133794 

Optoelectronic semiconductor chip


An optoelectronic semiconductor chip includes a multiplicity of active regions arranged at a distance from one another, and a continuous current spreading layer, wherein at least one of the active regions has a main extension direction, one of the active regions has a core region formed with a first semiconductor material, the active region has an active layer covering the core region at least in directions transversely with respect to the main extension direction of the active region, the active region has a cover layer formed with a second semiconductor material and covers the active layer at least in directions transversely with respect to the main extension direction of the active region, and the current spreading layer covers all cover layers of the active region.. .
Osram Opto Semiconductors Gmbh


05/12/16
20160133787 

Diode-based devices and methods for making the same


In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


05/12/16
20160133751 

Hydrogenated p-channel metal oxide semiconductor thin film transistors


This disclosure provides p-type metal oxide semiconductor materials that display good thin film transistor (tft) characteristics. Also provided are tfts including channels that include p-type oxide semiconductors, and methods of fabrication.
Qualcomm Incorporated


05/12/16
20160133750 

Fabrication process for mitigating external resistance of a multigate device


A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench.. .
International Business Machines Corporation


05/12/16
20160133740 

Semiconductor device comprising a multi-layer channel region


One illustrative device disclosed herein includes, among other things, a substrate made of a first semiconductor material, at least one layer of insulating material positioned above the substrate, a fin structure positioned above the layer of insulating material and the substrate, the fin structure comprising first, second and third layers of semiconductor material, wherein the semiconductor materials of the first, second and third layers are different than the first semiconductor material, and a gate structure around a portion of the fin structure comprised of the first, second and third layers of semiconductor material.. .
Globalfoundries Inc.


05/12/16
20160133735 

Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition


Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate.

05/12/16
20160133715 

Semiconductor device


The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other.
Renesas Electronics Corporation


05/12/16
20160133709 

Monolithic integrated semiconductor structure


A monolithic integrated semiconductor structure includes: a) an si carrier layer, b) a layer having the composition bxalygazntpv, wherein x=0-0.1, y=0-1, z=0-1, t=0-0.1 and v=0.9-1, c) a relaxation layer having the composition bxalygazinupvsbw, wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1 and w=0-1, wherein w and/or u is on the side facing toward layer a) or b) smaller than, equal to, or bigger than on the side facing away from layer a) or b) and wherein v=1−w and/or y=1−u−x−z, and d) a group iii/v, semiconductor material. The sum of the above stoichiometric indices for all group iii elements and for all group v elements are each equal to one..
Nasp Iii/v Gmbh


05/12/16
20160133694 

Structures and methods with reduced sensitivity to surface charge


The present application provides (in addition to more broadly applicable inventions) improvements which are particularly applicable to two-sided power semiconductor devices which use bipolar conduction. In this class of devices, the inventor has realized that two or three of the four (or more) semiconductor doping components which form the carrier-emission structures and control structures in the active device (array) portion of a two-sided power device can also be used, with surprising advantages, to form field-limiting rings around the active arrays on both surfaces.
Ideal Power Inc.


05/12/16
20160133525 

Semiconductor devices and methods of manufacturing the same


In a method of manufacturing a semiconductor device, a first gate structure and a second gate structure are formed on a substrate in a first region and a second region, respectively. A first semiconductor pattern including germanium is formed in the first region on the substrate.

05/12/16
20160133517 

Self-limited, anisotropic wet etching of transverse vias in microfluidic chips


The present invention is notably directed to a method of fabrication of a microfluidic chip (1). Comprising: providing (s10-s20) a wafer (10, 12) of semiconductor material having a diamond cubic crystal structure, exhibiting two opposite main surfaces (s1, s2), one on each side of the wafer, and having, each, a normal in the <100> or <110> direction; and performing (s30) self-limited, anisotropic wet etching steps on each of the two main surfaces on each side of the wafer, to create a via (20, 20a) extending transversely through the thickness of the wafer, at a location such that the resulting via connects an in-plane microchannel (31) on a first one (51) of the two main surfaces to a second one (s2) of the two main surfaces, the via exhibiting slanted sidewalls (20s) as a result of the self-limited wet etching.
International Business Machines Corporation


05/12/16
20160133506 

Method of fabricating semiconductor device isolation structure


A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/05/16
20160126462 

Fullerene derivative and n-type semiconductor material


Ar represents aryl optionally substituted with at least one alkyl group.. .

05/05/16
20160126460 

Organic film transistor, organic semiconductor film, and organic semiconductor material and use applications thereof


(cy represents a benzene ring, a naphthalene ring, or an anthracene ring; each of r11 to r14 and r15 to r18 independently represents a hydrogen atom or a substituent; each of ar1 to ar4 independently represents a heteroarylene group or an arylene group; each of v1 and v2 represents a divalent linking group; m represents an integer of 0 to 6; when m is equal to or greater than 2, two or more groups represented by v1 may be the same as or different from each other; n is equal to or greater than 2; p represents an integer of 0 to 6; and when p is equal to or greater than 2, two or more groups represented by v2 may be the same as or different from each other.). .

05/05/16
20160126459 

Organic film transistor, organic semiconductor film, organic semiconductor material and application of these


(each of r1 and r2 represents a hydrogen atom or a substituent; each of ar1 and ar2 independently represents a heteroarylene group or an arylene group; v1 represents a divalent linking group; m represents an integer of 0 to 6; cy represents a naphthalene ring or an anthracene ring; each of r3 and r4 represents a hydrogen atom or a substituent; each of ar3 and ar4 represents a heterocyclic aromatic ring or an aromatic ring; v2 represents a divalent linking group; p represents an integer of 0 to 6; n represents an integer of equal to or greater than 2; a is a divalent linking group represented by formula (101′); each of ra1 to ra6 represents a hydrogen atom, a substituent, or a direct bond with ar101 or ar102 in formula (101); and among the groups represented by ra1 to ra6, two different groups are direct bonds with ar101 and ar102 in formula (101) respectively.). .

05/05/16
20160126440 

Method of producing nanoparticles, producing thermoelectric material, and thermoelectric material


A method of producing nanoparticles in a base material made of a semiconductor material including a base material element, each nanoparticle including the base material element and a heterogeneous element different from the base material element includes: a layering step of alternately layering a first layer and a second layer, the first layer including the heterogeneous element, the second layer not including the heterogeneous element; and an annealing step of forming the nanoparticles in the base material by performing an annealing treatment onto a layered structure including the first layer and the second layer layered on each other. In the layering step, the base material element is included in at least one of the first layer and the second layer, and the second layer is formed to be thicker than the first layer..
Sumitomo Electric Industries, Ltd.


05/05/16
20160126438 

Thermoelectric device


The present invention is directed to a thermoelectric device that includes a plurality of thermoelectric couples positioned between a top plate and a bottom plate, wherein each thermoelectric couple comprises n-type and p-type element assemblies electrically connected in series and thermally connected in parallel. When the device is used for electrical power generation, the efficiency is increased by using semiconductor materials with a high seebeck coefficient, increasing the distance between the n-type and p-type element assemblies, increasing the length of the electrical conductors/thermal distance between the top and bottom plates, and/or using an insulation plate spaced from the top plate.
Novation Iq Llc


05/05/16
20160126419 

Semiconductor light emitting device and manufacturing the same


There is provided a semiconductor light-emitting device including a base layer formed of a first conductivity-type semiconductor material, and a plurality of light-emitting nanostructures disposed on the base layer to be spaced apart from each other, and including first conductivity-type semiconductor cores, active layers, and second conductivity-type semiconductor layers. The first conductivity-type semiconductor cores include rod layers extending upwardly from the base layer, and capping layers disposed on the rod layers.
Samsung Electronics Co., Ltd.


05/05/16
20160126354 

Methods of forming transistors


Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material.
Micron Technology, Inc.


05/05/16
20160126335 

Lattice matched aspect ratio trapping to reduce defects in iii-v layer directly grown on silicon


A structure having application to electronic devices includes a iii-v layer having high crystal quality and a low defect density on a lattice mismatched substrate. Trenches are formed in a layer of iii-v semiconductor material grown on a substrate having a different lattice constant.
International Business Machines Corporation


05/05/16
20160126322 

Method and structure to improve film stack with sensitive and reactive layers


Embodiments of the present disclosure generally relate to a film stack including layers of group iii-v semiconductor materials. The film stack includes a phosphorous containing layer deposited over a silicon substrate, a gaas containing layer deposited on the phosphorous containing layer, and an aluminum containing layer deposited on the gaas containing layer.
Applied Materials, Inc.


05/05/16
20160126315 

Iii-nitride semiconductor structure with intermediate and transition layers


The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer.
Infineon Technologies Americas Corp.


05/05/16
20160126312 

Semiconductor structure including a doped buffer layer and a channel layer and a process of forming the same


A semiconductor structure can include a substrate, a high-voltage blocking layer overlying the substrate, a doped buffer layer overlying the high-voltage layer, and a channel layer overlying the doped buffer layer, wherein the doped buffer layer and the channel layer include a same compound semiconductor material, and the doped buffer layer has a carrier impurity type at a first carrier impurity concentration, the channel buffer layer has the carrier impurity type at a second carrier impurity concentration that is less than the first carrier impurity concentration. In an embodiment, the channel layer has a thickness of at least 650 nm.
Semiconductor Components Industries, Llc


05/05/16
20160126246 

Integrated circuit devices having metal-insulator-silicon contact and methods of fabricating the same


Integrated circuit devices and methods of forming the devices are provided. The devices may include an active area, a gate electrode in the active area and a source/drain area adjacent a side of the gate electrode in the active area.

05/05/16
20160126244 

Forming iv fins and iii-v fins on insulator


A semiconductor structure including: a set of first fins in a pfet region and a set of second fins in an nfet region, the first fins and the second fins are on a buried insulator layer, the first fins have a bottom surface coplanar with a bottom surface of the second fins, the first fins have a first pitch between adjacent first fins that is equal to a second pitch between adjacent second fins, the first fins include a group iv semiconductor material, the second fins include a group iii-v semiconductor material.. .
International Business Machines Corporation


05/05/16
20160126103 

Recess filling method and processing apparatus


There is provided a method of filling a recess of a workpiece, which includes: forming a first thin film made of a semiconductor material along a wall surface defining a recess in a semiconductor substrate; annealing the workpiece within a vessel whose internal process is set to a first pressure, and forming an epitaxial region which is generated by crystallizing the semiconductor material of the first thin film, along a surface defining the recess, without moving the first thin film; forming a second thin film made of the semiconductor material along the wall surface defining the recess; and annealing the workpiece within the vessel whose internal pressure is set to a second pressure lower than the first pressure, and forming a further epitaxial region which is generated by crystallizing the semiconductor material of the second thin film which is moved toward a bottom of the recess.. .
Tokyo Electron Limited


05/05/16
20160126095 

Method for determining preferential deposition parameters for a thin layer of iii-v material


First, second and third series of samples are successively made so as to determine the influence of the deposition parameters on the crystallographic quality of a layer of semiconductor material of iii-v type. The parameters studied are successively the deposition pressure, the deposition temperature and the deposited thickness of a sub-layer of semiconductor material of iii-v type so as to respectively determine a first deposition pressure, a first deposition temperature at the first deposition pressure, and a first deposited thickness at the first deposition temperature and at the first deposition pressure.
Commissariat À L'energie Atomique Et Aux Energies Alternatives


05/05/16
20160126094 

Lattice matched aspect ratio trapping to reduce defects in iii-v layer directly grown on silicon


A structure having application to electronic devices includes a iii-v layer having high crystal quality and a low defect density on a lattice mismatched substrate. Trenches are formed in a layer of iii-v semiconductor material grown on a substrate having a different lattice constant.
International Business Machines Corporation


05/05/16
20160125311 

Apparatus and quantum processing


The present disclosure provides a quantum processor realised in a semiconductor material and method to operate the quantum processor to implement error corrected quantum computation. The quantum processor comprises a plurality of qubit elements disposed in a two-dimensional matrix arrangement.
University Of Melbourne


05/05/16
20160125310 

Apparatus and quantum processing


The present disclosure provides a quantum processor realised in a semiconductor material and method to operate the quantum processor to implement adiabatic quantum computation. The quantum processor comprises a plurality of qubit elements disposed in a two-dimensional matrix arrangement.
University Of Melbourne


05/05/16
20160122181 

Microintegrated encapsulated mems sensor with mechanical decoupling and manufacturing process thereof


The microintegrated sensor comprises a stack formed by a sensor layer, of semiconductor material, by a cap layer, of semiconductor material, and by an insulating layer. The sensor layer and the cap layer have a respective peripheral portion surrounding a central portion, and the insulating layer extends between the peripheral portions of the sensor layer and of the cap layer.
Stmicroelectronics S.r.l.


05/05/16
20160122180 

Method of making a semiconductor device having a functional capping


A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes.
Silex Microsystems Ab


04/28/16
20160119064 

Lens system to enhance optical coupling efficiency of collimated beam to optical waveguide


An optical coupling system to couple a collimated beam with a waveguide made of semiconductor materials is disclosed. The waveguide is implemented in an optical modulator and/or an optical hybrid, and has a core with a restricted cross section because of the enhanced refractive index of the semiconductor materials.
Sumitomo Electric Industries, Ltd.


04/28/16
20160118483 

Multi-gate fets having corrugated semiconductor stacks and forming the same


The present disclosure provides, in various aspects of the present disclosure, a semiconductor device which includes a semiconductor stack disposed over a surface of a substrate and a gate structure partially formed over an upper surface and two opposing sidewall surfaces of the semiconductor stack, wherein the semiconductor stack includes an alternating arrangement of at least two layers formed by a first semiconductor material and a second semiconductor material which is different from the first semiconductor material.. .
Globalfoundries Inc.


04/28/16
20160118472 

Methods of forming 3d devices with dielectric isolation and a strained channel region


One illustrative method involves forming a finfet device or a nanowire device by forming a sacrificial gate structure above a substantially vertically oriented structure comprised of first and second semiconductor materials, forming epi semiconductor material in the source/drain regions, removing the sacrificial gate structure so as to define a replacement gate cavity and to expose the first and second semiconductor materials within the gate cavity, performing an etching process through the replacement gate cavity to selectively remove the exposed first sacrificial semiconductor material relative to the exposed second semiconductor material so as to define a gap under the second semiconductor material within the gate cavity, filling the gap with an insulating material, and forming a replacement gate structure in the gate cavity.. .
Globalfoundries Inc.


04/28/16
20160118463 

Floating body memory with asymmetric channel


A semiconductor structure and formation thereof. The semiconductor structure has a fin of a first semiconductor material.
International Business Machines Corporation


04/28/16
20160118438 

Isolated global shutter pixel storage structure


A pixel cell includes a photodiode disposed in a semiconductor material to accumulate image charge in response to incident light directed to the photodiode. A global shutter gate transistor disposed in the semiconductor material and is coupled to the photodiode to selectively deplete the image charge from the photodiode.
Omnivision Technologies, Inc.


04/28/16
20160118431 

Front-side imager having a reduced dark current on soi substrate


A front-side image sensor may include a substrate in a semiconductor material and an active layer in the semiconductor material. The front side image sensor may also include an array of photodiodes formed in the active layer and an insulating layer between the substrate and the active layer..
Stmicroelectronics Sa


04/28/16
20160118414 

Dual three-dimensional and rf semiconductor devices using local soi


Co-fabrication of a radio-frequency (rf) semiconductor device with a three-dimensional semiconductor device includes providing a starting three-dimensional semiconductor structure, the starting structure including a bulk silicon semiconductor substrate, raised semiconductor structure(s) coupled to the substrate and surrounded by a layer of isolation material. Span(s) of the layer of isolation material between adjacent raised structures are recessed, and a layer of epitaxial semiconductor material is created over the recessed span(s) of isolation material over which another layer of isolation material is created.
Globalfoundries Inc.


04/28/16
20160118397 

Nand memory strings and methods of fabrication thereof


Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process.
Sandisk Technologies, Inc.


04/28/16
20160118392 

Charge storage apparatus and methods


Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric.
Micron Technology, Inc.


04/28/16
20160118384 

Self-aligned contact metallization for reduced contact resistance


Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type iii-v semiconductor material layer is provided between n-type source/drain regions and their respective contact metals.
Intel Corporation


04/28/16
20160118255 

Methods of forming strained epitaxial semiconductor material(s) above a strain-relaxed buffer layer


One illustrative method disclosed herein includes, among other things, sequentially forming a first material layer, a first capping layer, a second material layer and a second capping layer above a substrate, wherein the first and second material layers are made of semiconductor material having a lattice constant that is different than the substrate, the first material layer is strained as deposited, and a thickness of the first material layer exceeds its critical thickness required to be stable and strained, performing an anneal process after which the strain in the first material layer is substantially relaxed through the formation of crystallographic defects that are substantially confined to the semiconducting substrate, the first material layer, the first capping layer and the second material layer, and forming additional epitaxial semiconductor material on an upper surface of the resulting structure.. .
Globalfoundries Inc.


04/28/16
20160118251 

Methods of forming doped epitaxial sige material on semiconductor devices


One illustrative method disclosed herein includes, among other things, performing first and second in situ doping, epitaxial deposition processes to form first and second layers of in situ doped epi semiconductor material, respectively, above a semiconductor substrate, wherein one of the first and second layers has a high level of germanium and a low level of p-type dopant material and the other of the first and second layers has a low level of germanium and a high level of p-type dopant material, and performing a mixing thermal anneal process on the first and second layers so as to form the final silicon germanium material having a high level of germanium and a high level of p-type dopant material.. .
Globalfoundries Inc.


04/28/16
20160118245 

Method for fabricating quasi-soi source/drain field effect transistor device


The present invention discloses a method for fabricating a quasi-soi source/drain field effect transistor device, which comprises the steps of forming an active region of the device; forming a gate stack structure of the device; doping a source/drain extension region, and forming a first layer of side wall at two sides of the gate stack structure; forming a recessed source/drain structure; forming a quasi-soi source/drain isolation layer; in-situ doping an epitaxial second semiconductor material source/drain, and activating by annealing; removing the previous dummy gate and re-depositing a high-k metal gate, if a post-gate process is employed; and forming contacts and metal interconnections. The method of the invention is well compatible with the existing cmos process, and it has the features of simple process and small heat budget; and in comparison with the traditional field effect transistor, by means of the quasi-soi source/drain field effect transistor device fabricated according to the method of the invention, the leakage current can be lowered effectively, thus the power consumption of the device can be reduced..
Peking University


04/21/16
20160111858 

Hybrid laser including anti-resonant waveguides


Described are embodiments of apparatuses and systems including a hybrid laser including anti-resonant waveguides, and methods for making such apparatuses and systems. A hybrid laser apparatus may include a first semiconductor region including an active region of one or more layers of semiconductor materials from group iii, group iv, or group v semiconductor, and a second semiconductor region coupled with the first semiconductor region and having an optical waveguide, a first trench disposed on a first side of the optical waveguide, and a second trench disposed on a second side, opposite the first side, of the optical waveguide.

04/21/16
20160111668 

Photovoltaic cells based on donor and acceptor nano-particulate conjugates in conductive polymer blends


A photovoltaic cell includes a substrate layer, an anode layer on the substrate layer, an active layer on the anode layer, and a cathode layer on the active layer, wherein the active layer comprises a plurality of disparately sized n-type and p-type nano-particles of different semiconductor materials randomly distributed in a conductive polymer blend. The n-type nano-particles can include either zno or in2o3 nano-particles, and the p-type nano-particles can include either nio or la2o3 nano-particles.

04/21/16
20160111639 

Select device for memory cell applications


The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device..

04/21/16
20160111619 

High performance high temperature thermoelectric composites with metallic inclusions


The present invention provides a composite thermoelectric material. The composite thermoelectric material can include a semiconductor material comprising a rare earth metal.

04/21/16
20160111575 

Mesoscopic solar cell based on perovskite light absorption material and making the same


A mesoscopic solar cell, including: a conductive substrate, a hole blocking layer, a mesoporous nanocrystalline layer, an insulation separating layer, and a hole collecting layer, and perovskite light absorption materials. The hole blocking layer, the mesoporous nanocrystalline layer, the insulation separating layer, and the hole collecting layer are sequentially laminated on the conductive substrate.

04/21/16
20160111544 

Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors


Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate..

04/21/16
20160111501 

Method to define the active region of a transistor employing a group iii-v semiconductor material


A group iii-v transistor device employing a novel layout for isolating and/or defining the active region is provided. A group iii-v heterojunction is arranged over or within a substrate, and an inner drain electrode is arranged over the group iii-v heterojunction.

04/21/16
20160111500 

Techniques for forming optoelectronic devices


Embodiments relate to use of a particle accelerator beam to form thin films of material from a bulk substrate are described. In particular embodiments, a bulk substrate having a top surface is exposed to a beam of accelerated particles.

04/21/16
20160111496 

Method and structure for iii-v finfet


A method for fabricating a semiconductor device comprises forming a fin in a layer of iii-v compound semiconductor material on a silicon-on-insulator substrate; forming a semiconductor extension on the fin, the semiconductor extension comprising a iii-v compound semiconductor material that is different from a material forming the fin in the iii-v compound semiconductor layer; forming a dummy gate structure and a spacer across and perpendicular to the fin; forming a source/drain layer on a top surface of the substrate adjacent to the dummy gate structure; planarizing the source/drain layer; removing the dummy gate structure to expose a portion of the semiconductor extension on the fin; removing the exposed portion of the semiconductor extension; etching the semiconductor extension to undercut the spacer; and forming a replacement gate structure in place of the removed dummy gate structure and removed exposed portion of the semiconductor extension.. .

04/21/16
20160111447 

Merged fin structures for finfet devices


Merged fin structures for finfet devices and methods of manufacture are disclosed. The method of forming the structure includes forming a plurality of fin structures on an insulator layer.

04/21/16
20160111436 

Vertical nand device containing peripheral devices on epitaxial semiconductor pedestal


A multilevel structure includes a stack of an alternating plurality of electrically conductive layers and insulator layers located over a semiconductor substrate, and an array of memory stack structures located within memory openings through the stack. An epitaxial semiconductor pedestal is provided, which is in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate and has a top surface within a horizontal plane located above a plurality of electrically conductive layers within the stack.

04/21/16
20160111434 

Three dimensional nand string memory devices and methods of fabrication thereof


Monolithic three-dimensional nand memory strings and methods of fabricating a monolithic three-dimensional nand memory string include forming single crystal or large grain polycrystalline semiconductor material charge storage regions by a metal induced crystallization process. In another embodiment, a plurality of front side recesses are formed having a concave-shaped surface and a blocking dielectric and charge storage regions are formed within the front side recesses and over the concave-shaped surface.

04/21/16
20160111432 

Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device


A memory film layer is formed in a memory opening through an alternating stack of first material layers and second material layers. A sacrificial material layer is deposited on the memory film layer.

04/21/16
20160111407 

Method and system for template assisted wafer bonding using pedestals


A multilayer semiconductor has stacks of composite semiconductor materials. Multiple composite devices are bonded on a silicon-on-insulator wafer forming an integrated device..

04/21/16
20160111390 

Method for manufacturing electronic devices


An embodiment for manufacturing electronic devices is proposed. The embodiment includes the following phases: a) forming a plurality of chips in a semiconductor material wafer including a main surface; each chip includes respective integrated electronic components and respective contact pads facing the main surface; said contact pads are electrically coupled to the integrated electronic components; b) attaching at least one conductive ribbon to at least one contact pad of each chip; c) covering the main surface of the semiconductor material wafer and the at least one conductive ribbon with a layer of plastic material; d) lapping an exposed surface of the layer of plastic material to remove a portion of the plastic material layer at least to uncover portions of the at least one conductive ribbon, and e) sectioning the semiconductor material wafer to separate the chips..

04/21/16
20160111338 

Method to co-integrate sige and si channels for finfet devices


A method for co-integrating finfets of two semiconductor material types, e.g., si and sige, on a bulk substrate is described. Fins for finfets may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator.

04/21/16
20160111294 

Use of ion beam etching to generate gate-all-around structure


Various embodiments herein relate to methods and apparatus for performing anisotropic ion beam etching to form arrays of channels. The channels may be formed in semiconductor material, and may be used in a gate-all-around device.

04/21/16
20160109732 

Oxide capacitor electro-optical phase shifter


An electro-optical phase shifter to be located in an optical waveguide may include a rib of a semiconductor material extending along a length of the optical waveguide and a control structure configured to modify a concentration of carriers in the rib according to a control voltage present between first and second control terminals of the phase shifter. The control structure may include a conductive layer covering a portion of the rib and electrically connected to a first of the control terminals.

04/21/16
20160109731 

Thin layer photonic integrated circuit based optical signal manipulators


Integrated optical intensity or phase modulators capable of very low modulation voltage, broad modulation bandwidth, low optical power loss for device insertion, and very small device size are of interest. Such modulators can be of electro-optic or electro-absorption type made of an appropriate electro-optic or electro-absorption material in particular or referred to as an active material in general.

04/14/16
20160105247 

Complementary metal oxide semiconductor device with iii-v optical interconnect having iii-v epitaxial semiconductor material formed using lateral overgrowth


An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate.

04/14/16
20160104998 

Light guiding for vertical external cavity surface emitting laser


The present invention relates to an active gain layer stack (21) for a vertical emitting laser device, the active gain layer stack (21) comprising a semiconductor material, wherein the semiconductor material is structured such that it forms at least one mesa (24) extending in a vertical direction. A transversally neighboring region (25) that at least partly surrounds said mesa (24) has a second refractive index (n2)—at least part of said mesa (24) has a first refractive index (n1) and a part of the neighboring region (25) transversally adjacent to said part of the mesa (24) has second refractive index (n 2)—said first refractive index (n1) is higher than said second refractive index (n2) and a diameter in transversal direction of said mesa (24) is chosen such that a transversal confinement factor in the active gain layer stack (21) is increased.

04/14/16
20160104842 

Organic semiconductor thin film production method


A raw material solution (6), in which an organic semiconductor material is dissolved in a solvent, is supplied to a substrate (1). The solvent is evaporated so that crystals of the organic semiconductor material are precipitated.

04/14/16
20160104793 

Structure and finfet device


The present disclosure provides an embodiment of a fin-like field-effect transistor (finfet) device. The device includes a fin structure disposed over a substrate.

04/14/16
20160104775 

Semiconductor device and fabricating the same


A semiconductor device includes a buffer layer on a semiconductor substrate including first and second regions, a first channel layer on the buffer layer of the first region, a second channel layer on the buffer layer of the second region, and a spacer layer between the second channel layer and the buffer layer. The buffer layer, the first and second channel layers, and the spacer layer are formed of semiconductor materials including germanium.

04/14/16
20160104706 

Fin-like field effect transistor (finfet) device and manufacturing same


A finfet device and method for fabricating a finfet device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion of the first and second fin structures, such that the gate structure traverses the first and second fin structures; epitaxially growing a first semiconductor material on exposed portions of the first and second fin structures, such that the exposed portions of the first and second fin structures are merged together; and epitaxially growing a second semiconductor material over the first semiconductor material..

04/14/16
20160104626 

Methods for singulating semiconductor wafer


Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces.

04/14/16
20160103286 

Optical transceiver implementing erbium doped fiber amplifier


An optical transceiver that installs an optical modulator with the mach-zehnder type and made of primarily semiconductor materials, and an erbium doped fiber amplifier (edfa) is disclosed. The edfa and the mz modulator, in addition to a wavelength tunable laser diode, an intelligent coherent receiver, and a polarization maintaining splitter, are installed within a compact case following the standard of cfp2..

04/14/16
20160103278 

Complementary metal oxide semiconductor device with iii-v optical interconnect having iii-v epitaxially formed material


An electrical device that in one embodiment includes a first semiconductor device positioned on a first portion of a type iv semiconductor substrate, and an optoelectronic light emission device of type iii-v semiconductor materials that is in electrical communication with the first semiconductor device. The optoelectronic light emission device is positioned adjacent to the first semiconductor device on the first portion of the type iv semiconductor substrate.



Semiconductor Material topics: Semiconductor, Semiconductor Material, Semiconductor Device, Transistors, Surfactant, Electric Conversion, Transparent Conductive Oxide, Semiconductor Substrate, Heating Devices, Semiconductor Devices, Organic Electroluminescence, Buffer Layer, Integrated Circuit, Crystallin, Electronic Device

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