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Semiconductor Devices

Semiconductor Devices-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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NEW Semiconductor optoelectronics and cmos on sapphire substrate
International Business Machines Corporation
June 22, 2017 - N°20170179681

The present disclosure relates to nitride based optoelectronic and electronic devices with si cmos. The disclosure provides a semiconductor device, comprising a sapphire substrate, and a laser region and a detector region deposed on the sapphire substrate. The laser is formed onto the substrate from layers of gan, ingan and optionally the algan. The detector can be an ingan detector. ...
NEW Semiconductor device with integrated magnetic tunnel junction
Imec Vzw
June 22, 2017 - N°20170179378

The disclosed technology generally relates to semiconductor devices and more particularly to semiconductor devices having an integrated magnetic tunnel junction (mtj), and relates to methods of fabricating the semiconductor devices. In one aspect, a semiconductor device includes a stack including successive layers of: a first metallization layer, a first dielectric layer, a second metallization layer, a second dielectric layer, and ...
NEW Semiconductor devices and methods for fabricating the same
Samsung Electronics Co., Ltd.
June 22, 2017 - N°20170179284

A semiconductor device includes a substrate including a first region and a second region, a first fin-type pattern in the first region, a second fin-type pattern in the second region, a first gate structure intersecting the first fin-type pattern, the first gate structure including a first gate spacer, a second gate structure intersecting the second fin-type pattern, the second gate ...
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NEW Partial, self-biased isolation in semiconductor devices
Freescale Semiconductor, Inc.
June 22, 2017 - N°20170179279

A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and ...
NEW Junction butting structure using nonuniform trench shape
Globalfoundries Inc.
June 22, 2017 - N°20170179257

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (soi) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (rie) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack ...
NEW Multi-threshold voltage structures with a lanthanum nitride film and methods of formation thereof
Applied Materials, Inc.
June 22, 2017 - N°20170179252

Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a ...
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Semiconductor Devices Patent Applications
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  • 1069+ full patent PDF documents of Semiconductor Devices-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
NEW Dielectrically isolated semiconductor device and method for manufacturing the same
Hangzhou Silan Integrated Circuit Co., Ltd.
June 22, 2017 - N°20170179227

The present disclosure relates to a dielectrically isolated semiconductor device and a method for manufacturing the same. The dielectrically isolated semiconductor device includes a semiconductor substrate, a first semiconductor layer above the semiconductor substrate, a second semiconductor layer above the first semiconductor layer, a semiconductor island in the second semiconductor layer, and a first dielectric isolation layer surrounding a bottom ...
NEW Power semiconductor devices, semiconductor devices and a method for adjusting a number of charge carriers
Infineon Technologies Ag
June 22, 2017 - N°20170179224

A power semiconductor device includes a semiconductor substrate including at least one electrical structure. The at least one electrical structure has a blocking voltage of more than 20v. Further, the power semiconductor device includes an electrically insulating layer structure formed over at least a portion of a lateral surface of the semiconductor substrate. The electrically insulating layer structure embeds one ...
NEW Semiconductor devices with integrated thin-film transistor circuitry
Hong Kong Beida Jade Bird Display Limited
June 22, 2017 - N°20170179192

Various embodiments include a semiconductor device with thin-film transistor (tft) circuitry monolithically integrated with other non-tft functional devices. One example is an integrated led display panel, in which an array of leds is integrated with corresponding tft driver circuitry. The tft driver circuitry typically is an array of pixel drivers that drive the leds.
NEW Three-dimensional semiconductor devices and fabricating methods thereof
Samsung Electronics Co., Ltd.
June 22, 2017 - N°20170179146

A three-dimensional (3d) semiconductor memory device includes a cmos circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the cmos circuit structure. The memory structure overlaps a first circuit region of the cmos circuit structure and does not overlap a second ...
NEW Making semiconductor devices with alignment bonding and substrate removal
Hong Kong Beida Jade Bird Display Limited
June 22, 2017 - N°20170179097

Embodiments include a manufacturing method of making a semiconductor device via multiple stages of alignment bonding and substrate removal. One example is an integrated full-color led display panel, in which multiple wafers with different arrays of leds are integrated onto a host wafer with driver circuitry. The driver circuitry typically is an array of pixel drivers that drive individual leds ...
NEW Method for interconnecting stacked semiconductor devices
Intel Corpration
June 22, 2017 - N°20170179082

A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the ...
NEW Electrical interconnections for semiconductor devices and methods for forming the same
Samsung Electronics Co., Ltd.
June 22, 2017 - N°20170179065

An electrical interconnection includes a wire loop having a first end bonded to a first bonding site using a first bonding portion, and a second end bonded to a second bonding site using a second bonding portion. The second bonding portion includes a folded portion having a wire that extends from the second end of the wire loop and is ...
NEW Semiconductor Devices Patent Pack
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Semiconductor Devices Patent Applications
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  • 1069+ full patent PDF documents of Semiconductor Devices-related inventions.
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  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
NEW Methods of processing wafer-level assemblies to reduce warpage, and related assemblies
Micron Technology, Inc.
June 22, 2017 - N°20170179045

Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of ...
NEW Oxidation resistant barrier metal process for semiconductor devices
Texas Instruments Incorporated
June 22, 2017 - N°20170179033

An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. ...
NEW Device architecture and method for precision enhancement of vertical semiconductor devices
D3 Semiconductor Llc
June 22, 2017 - N°20170179024

Improvement of key electrical specifications of vertical semiconductor devices, usually found in the class of devices known as discrete semiconductors, has a direct impact on the performance achievement and power efficiency of the systems in which these devices are used. Imprecise vertical device specifications cause system builders to either screen incoming devices for their required specification targets or to design ...
NEW Hybrid subtractive etch/metal fill process for fabricating interconnects
International Business Machines Corporation
June 22, 2017 - N°20170179023

In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive ...
NEW Semiconductor devices with improved thermal and electrical performance
Infineon Technologies Austria Ag
June 22, 2017 - N°20170179009

A device may include a carrier, a semiconductor chip arranged over a first surface of the carrier, and an encapsulation body comprising six side surfaces and encapsulating the semiconductor chip. A second surface of the carrier opposite to the first surface of the carrier is exposed from the encapsulation body. The device may further include electrical contact elements electrically coupled ...
NEW Semiconductor devices comprising getter layers and methods of making and using the same
Monolith Semiconductor Inc.
June 22, 2017 - N°20170178989

Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can ...
NEW Methods and devices for back end of line via formation
Globalfoundries Inc.
June 22, 2017 - N°20170178953

Back end of line via formation for semiconductor devices and methods of fabricating the semiconductor devices. One method includes, for instance: obtaining a wafer with a substrate and at least one contact in the substrate; depositing at least one lithography stack over the substrate; performing lithography to pattern at least one via opening; depositing a block co-polymer coating over the ...
NEW Semiconductor devices
Samsung Electronics Co., Ltd.
June 22, 2017 - N°20170178949

A semiconductor device may include a substrate, a first interlayered insulating layer on the substrate having openings, conductive patterns provided in the openings, first to fourth insulating patterns stacked on the substrate provided with the conductive patterns, and a second interlayered insulating layer provided on the fourth insulating pattern.
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