Images List Premium Download Classic

Semiconductor Devices

Semiconductor Devices-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


loading
Optical analyzer and method for producing the same
Shimadzu Corporation
June 14, 2018 - N°20180166605

A passage (3) for a sample solution is formed in a sapphire base body (2) used as a substrate for semiconductor devices. An led (4) and a photodiode (5) are formed on the base body (2) by a semiconductor manufacturing process so that they face each other across the passage (3).
Internal spacer formation for nanowire semiconductor devices
Imec Vzw
June 14, 2018 - N°20180166558

The present disclosure relates to a method of forming an internal spacer between nanowires in a semiconductor device. The method includes providing a semiconductor structure comprising at least one fin.
Horizontal nanowire semiconductor devices
Imec Vzw
June 14, 2018 - N°20180166535

The present disclosure relates to a method of forming a semiconductor device comprising horizontal nanowires. The method comprises depositing a multilayer stack on a substrate, the multilayer stack comprising first sacrificial layers alternated with layers of nanowire material; forming at least one fin in the multilayer stack; applying an additional sacrificial layer around the fin such that a resulting sacrificial ...
Semiconductor Devices Patent Pack
Download 1069+ patent application PDFs
Semiconductor Devices Patent Applications
Download 1069+ Semiconductor Devices-related PDFs
For professional research & prior art discovery
inventor
  • 1069+ full patent PDF documents of Semiconductor Devices-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Semiconductor devices and methods of fabricating the same
Samsung Electronics Co., Ltd.
June 14, 2018 - N°20180166440

A semiconductor device may include a substrate, a first doped region and a second doped region on the substrate, a base region on the first doped region, a channel region on the second doped region, and a third doped region and a fourth doped region on the base region and the channel region, respectively. The first doped region and the ...
Packaged semiconductor devices with multi-use input contacts and related methods
Semiconductor Components Industries, Llc
June 14, 2018 - N°20180166378

A semiconductor device includes a first contact receiving a first voltage, a second contact receiving a second voltage, one or more comparing elements comparing the first and second voltages, and one or more setting elements setting one or more parameters of the device in response to a comparison of the first and second voltages. When the first voltage is greater ...
Semiconductor devices including exposed opposing die pads
Infineon Technologies Austria Ag
June 14, 2018 - N°20180166366

A semiconductor device includes a first lead frame, a second lead frame, a first semiconductor chip, and an encapsulation material. The first lead frame includes a first die pad having a first surface and a second surface opposite to the first surface.
Semiconductor Devices Patent Pack
Download 1069+ patent application PDFs
Semiconductor Devices Patent Applications
Download 1069+ Semiconductor Devices-related PDFs
For professional research & prior art discovery
inventor
  • 1069+ full patent PDF documents of Semiconductor Devices-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Methods of manufacturing semiconductor devices
Samsung Electronics Co., Ltd.
June 14, 2018 - N°20180166343

A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other in a second direction, forming capping patterns on the gate electrodes, forming interlayer dielectric layer filling spaces between adjacent gate electrodes, forming a hardmask on the interlayer dielectric layer with an opening selectively exposing second ...
Innovative approach to minimize plasma doping induced fin height loss
Taiwan Semiconductor Manufacturing Co., Ltd.
June 14, 2018 - N°20180166341

A plasma doping process provides conformal doping profiles for lightly doped source/drain regions in fins, and reduces the plasma doping induced fin height loss. The plasma doping process overcomes the limitations caused by traditional plasma doping processes in fin structures that feature aggressive aspect ratios and tights pitches.
Semiconductor device with reduced trench loading effect
Taiwan Semiconductor Manufacturing Co., Ltd.
June 14, 2018 - N°20180166321

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having reduced trench loading effect. The present disclosure provides a novel multi-layer cap film incorporating one or more oxygen-based layers for reducing trench loading effects in semiconductor devices.
Semiconductor devices
Samsung Electronics Co., Ltd.
June 14, 2018 - N°20180166320

A semiconductor device includes: a plurality of lower electrodes arranged on a substrate in a first direction, which is parallel to a main surface of the substrate, and a second direction parallel to the main surface of the substrate and perpendicular to the first direction; and a support structure pattern configured to connect the plurality of lower electrodes to each ...
Semiconductor with through-substrate interconnect
Micron Technology, Inc.
June 14, 2018 - N°20180166317

Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer.
Semiconductor devices
Sk Hynix Inc.
June 14, 2018 - N°20180166110

A semiconductor device includes a flag signal generation circuit and a power-down signal generation circuit. The flag signal generation circuit generates a flag signal which is enabled in response to an operational frequency information signal.
Semiconductor devices and semiconductor systems including the same
Sk Hynix Inc.
June 14, 2018 - N°20180166107

A semiconductor system includes a semiconductor device. The semiconductor device outputs a first group of data and a second group of data to a first group of input/output (i/o) lines and a second group of i/o lines in response to a command and an address.
Semiconductor Devices Patent Pack
Download 1069+ patent application PDFs
Semiconductor Devices Patent Applications
Download 1069+ Semiconductor Devices-related PDFs
For professional research & prior art discovery
inventor
  • 1069+ full patent PDF documents of Semiconductor Devices-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Heat dissipation material
June 14, 2018 - N°20180163113

This heat dissipation material has excellent thermal conductivity, and further shows good thermoplastic properties and has excellent moldability, and hence can be suitably used as a resin material for heat dissipation materials and semiconductor devices and electronic parts in particular.. .
Mems package with roughend interface
Taiwan Semiconductor Manufacturing Co., Ltd.
June 14, 2018 - N°20180162720

A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first ...
Error detection code generation circuits of semiconductor devices, memory controllers including the same and semiconductor ...
Samsung Electronics Co., Ltd.
June 07, 2018 - N°20180159558

An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (crc) engine, a second crc engine and an output selection engine. The first crc engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first dbi bits in response to a mode signal.
Semiconductor device, control system, and synchronization method
Renesas Electronics Corporation
June 07, 2018 - N°20180159540

In a system for performing clock generation for each semiconductor device, synchronization between the semiconductor devices is achieved without causing a count value in a counter to be discontinuously changed. A semiconductor device 1 includes a clock oscillator 2, a counter 3 configured to count the number of clocks, a periodic register 4 in which a value corresponding to a period for synchronization is ...
Active gate-source capacitance clamp for normally-off hemt
Infineon Technologies Austria Ag
June 07, 2018 - N°20180159528

A semiconductor assembly includes a first fet having gate, source and drain terminals, a switching device being configured to electrically short a gate-source capacitance of the first fet responsive to a control signal, a first gate lead, a second gate lead, a drain lead, and a source lead. The first and second gate leads, the drain lead, and the source ...
Active gate clamping for inverter switching devices with enhanced common source inductance
Ford Global Technologies, Llc
June 07, 2018 - N°20180159440

An inverter phase leg has upper and lower gate drive circuits supplying gate drive signals to upper and lower transistors. Each gate drive circuit includes an active clamp for selectively deactivating the upper and lower transistors.
Semiconductor devices
Samsung Electronics Co., Ltd.
June 07, 2018 - N°20180159030

A semiconductor device includes a stacked structure of cell structures, an electrode structure, and a heating electrode. Each cell structure includes a capping layer, a selection layer, a buffer layer, a variable resistance layer, and a upper electrode layer sequentially stacked.
Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial ...
Intel Corporation
June 07, 2018 - N°20180158930

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate.
Loading