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Semiconductor Device patents



      
           
This page is updated frequently with new Semiconductor Device-related patent applications. Subscribe to the Semiconductor Device RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Device RSS RSS


Optoelectronic semiconductor device

Osram Opto Semiconductors

Optoelectronic semiconductor device

Semiconductor devices having bit line structures disposed in trenches, methods of fabricating the same, packages…

Sk Hynix

Semiconductor devices having bit line structures disposed in trenches, methods of fabricating the same, packages…

Semiconductor devices having bit line structures disposed in trenches, methods of fabricating the same, packages…

Spansion

Integrated circuits with non-volatile memory and methods for manufacture

Date/App# patent app List of recent Semiconductor Device-related patents
01/29/15
20150033201
 Systems and methods for fabricating semiconductor device structures patent thumbnailnew patent Systems and methods for fabricating semiconductor device structures
Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining raw measurement data for a wafer of semiconductor material from a metrology tool and adjusting a measurement model utilized by a metrology tool based at least in part on the raw measurement data and a value for a design parameter.
Globalfoundries, Inc.
01/29/15
20150033089
 Semiconductor device patent thumbnailnew patent Semiconductor device
A semiconductor device includes a compression block configured to compare and compress data of a plurality of core array blocks, by a unit of a group; a combination block configured to combine outputs of the compression block and output compression data; and a control block configured to latch the compression data and output latched data, and drive the latched data and the compression data and output resultant data to a first data line and a second data line.. .
Sk Hynix Inc.
01/29/15
20150032949
 Semiconductor device and  controlling non-volatile memory device patent thumbnailnew patent Semiconductor device and controlling non-volatile memory device
A control circuit of a semiconductor device (memory module) realizes long life and others by a mechanism that suppresses and smoothes variations in use of a memory by equalizing the sizes of data write and data erase with respect to a data write request and sequentially allocating and using addresses of the memory in data write to an overwritable non-volatile memory device without carrying out an overwriting operation even in the case of an overwrite request. The control circuit realizes data write by a set of two types of operations of (a) an operation of erasing data of a first address or an operation of setting a flag value to an invalid state and (b) an operation of writing data to a second address different from the first address or an operation of setting a flag value to a valid state..
Hitachi, Ltd.
01/29/15
20150031216
 Cleaning method,  manufacturing semiconductor device, substrate processing apparatus, and recording medium patent thumbnailnew patent Cleaning method, manufacturing semiconductor device, substrate processing apparatus, and recording medium
There is provided a method of cleaning an inside of a process chamber, which is formed by a reaction tube and a manifold configured to support the reaction tube and installed under a heater, after forming a stacked film of oxide and nitride films on a substrate in the process chamber by alternately performing forming the oxide film on the substrate and forming the nitride film thereon. The method includes supplying a hydrogen-free fluorine-based gas from a first nozzle, which is installed in the manifold to extend upward from the manifold to an inside of the reaction tube, to an inner wall of the reaction tube; and supplying a hydrogen fluoride gas from a second nozzle, which is installed in the manifold, to an inner wall of the manifold..
Hitachi Kokusai Electric, Inc.
01/29/15
20150031209
 Method for forming features with sub-lithographic pitch using directed self-assembly of polymer blend patent thumbnailnew patent Method for forming features with sub-lithographic pitch using directed self-assembly of polymer blend
There is provided a manufacturing method of a semiconductor device including forming a first pattern of first features, according to a lithography process, in a photoresist layer disposed on a substrate, the lithography process having a minimum printable dimension and a minimum printable pitch, applying an additional layer on the photoresist layer having the first pattern formed therein, forming a second pattern of second features in the additional layer, the second features concentric with the first features, and etching portions of the substrate exposed through the second pattern. Further, in the provided method, the first features include geometrical features separated by a distance less than the dimension of minimum printable feature, and the geometrical features are disposed at a pitch less than the minimum printable pitch..
Renesas Electronics Corporation
01/29/15
20150031208
 Method of manufacturing semiconductor device patent thumbnailnew patent Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device, includes the steps of forming a top surface nitride film on a top surface of a substrate and a bottom surface nitride film on a bottom surface of the substrate, forming a protective film on the top surface nitride film, removing the bottom surface nitride film by wet etching while the top surface nitride film is being protected by the protective film, removing the protective film after the removing of the bottom surface nitride film, patterning the top surface nitride film so as to form an opening in the top surface nitride film, and forming a second oxide film on the bottom surface of the substrate while forming a first oxide film on a surface portion of the substrate which is exposed by the opening.. .
Mitsubishi Electric Corporation
01/29/15
20150031205
 Polishing method patent thumbnailnew patent Polishing method
Provided is a polishing method including a step of preparing a substrate having (1) silicon nitride as a stopper, and to a direction of a surface subjected to polishing from the stopper, (2) at least a portion of a wiring metal, and (3) at least a portion of an insulating material; a step of supplying a cmp slurry, and thereby polishing the (2) wiring metal and (3) insulating material on the direction of the surface subjected to polishing; and a step of stopping polishing before the (1) silicon nitride is exposed and completely removed, in which method the cmp slurry contains (a) a copolymer of (a) a monomer that is anionic and does not contain a hydrophobic substituent and (b) a monomer containing a hydrophobic substituent; (b) an abrasive grain; (c) an acid; (d) an oxidizing agent; and (e) a liquid medium, the component (b) has a zeta potential of +10 mv or more in the cmp slurry, and the copolymerization ratio (a):(b) of the component (a) is 25:75 to 75:25 as a molar ratio, with the ph being 5.0 or less. Through this method, an interlayer insulating film and a stopper can be polished at a high selectivity while metal and the interlayer insulating film are removed at high polishing rates, and thus a semiconductor device having high dimensional accuracy can be produced..
Hitachi Chemical Company, Ltd.
01/29/15
20150031198
 Pattern forming method and  manufacturing semiconductor device patent thumbnailnew patent Pattern forming method and manufacturing semiconductor device
According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer.
Kabushiki Kaisha Toshiba
01/29/15
20150031197
 Integrated circuits with non-volatile memory and methods for manufacture patent thumbnailnew patent Integrated circuits with non-volatile memory and methods for manufacture
Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region.
Spansion Llc
01/29/15
20150031195
 Method of fabricating a semiconductor device patent thumbnailnew patent Method of fabricating a semiconductor device
A method of fabricating a semiconductor device may include conformally forming a gate insulating layer on a substrate having a recess, conformally forming a barrier layer containing fluorine-free tungsten nitride on the substrate with the gate insulating layer using an atomic layer deposition process, and forming a gate electrode on the barrier layer to fill at least a portion of the recess.. .
Samsung Electronics Co., Ltd.
01/29/15
20150031191
new patent

Method of manufacturing semiconductor device


To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension line of a dicing region provided between a first semiconductor device region and a second semiconductor device region but is provided between the extension line of the dicing region and a first imaginary extension line of a first outermost peripheral land row and between the extension line of the dicing region and a second imaginary extension line of a second outermost peripheral land row.
Renesas Electronics Corporation
01/29/15
20150031186
new patent

Method of fabricating semiconductor device having dielectric layer with improved electrical characteristics


A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.. .
01/29/15
20150031185
new patent

Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby


The method includes forming an array of first separation walls on an underlying layer. A block co-polymer (bcp) layer is formed to fill inside regions of the first separation walls and gaps between the first separation walls.
Sk Hynix Inc.
01/29/15
20150031183
new patent

Semiconductor devices including silicide regions and methods of fabricating the same


A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween.
Samsung Electronics Co., Ltd.
01/29/15
20150031176
new patent

Semiconductor device containing hemt and misfet and forming the same


A semiconductor structure with a misfet and a hemt region includes a first iii-v compound layer. A second iii-v compound layer is disposed on the first iii-v compound layer and is different from the first iii-v compound layer in composition.
Taiwan Semiconductor Manufacturing Company, Ltd.
01/29/15
20150031175
new patent

Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device, includes providing a silicon semiconductor substrate which is manufactured by a floating zone method; and performing thermal diffusion at a heat treatment temperature that is equal to or higher than 1290° c. And that is lower than a melting temperature of a silicon crystal to form a diffusion layer with a depth of 50 μm or more in the silicon semiconductor substrate, the thermal diffusion including a first heat treatment performed in an oxygen atmosphere or a mixed gas atmosphere of oxygen and inert gas, and a second heat treatment performed in a nitrogen atmosphere or a mixed gas atmosphere of nitrogen and oxygen to form the diffusion layer.
Fuji Electric Co., Ltd.
01/29/15
20150031169
new patent

Method for manufacturing semiconductor device


An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like.
Semiconductor Energy Laboratory Co., Ltd.
01/29/15
20150030051
new patent

Thermal observer and overload protection for power switches


The present disclosure proposes the placing of temperature sensors embedded in the power semiconductor device. In this, at least one of the embedded temperature sensors is placed within or close to the heat source, active areas or channels of the power semiconductor circuit, and at least one of the embedded temperature sensors is placed more apart from the heat source, active areas or channels of the power semiconductor circuit.
Infineon Technologies Ag
01/29/15
20150029800
new patent

Semiconductor device


An interface circuit provided in a semiconductor device supplies an operation clock to an external memory device based on a clock signal and receives a data signal and a strobe signal from the external memory device. The interface circuit includes a delay circuit delaying the received strobe signal.
Renesas Electronics Corporation
01/29/15
20150029776
new patent

Semiconductor device having a reduced area and enhanced yield


A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power supply line and the first node, a first anti-fuse connected between the first node and the second node, and a second anti-fuse connected between the first node and the third node. The second node and the third node are not connected to each other..
Micron Technology, Inc.
01/29/15
20150029627
new patent

Semiconductor device including a control circuit


A semiconductor device includes a semiconductor portion with a main fet and a control circuit. The main fet includes a gate electrode to control a current flow through a body zone between a source zone and a drift zone.
Infineon Technologies Austria Ag
01/29/15
20150029622
new patent

Electrostatic discharge protection


A semiconductor device is disclosed that includes a first well of a first conductivity type, a second well of a second conductivity type, a plurality of first regions, a second region and a plurality of electrodes. The first regions are of the first conductivity type and are formed in the second well.
Taiwan Semiconductor Manufacturing Company, Ltd.
01/29/15
20150029483
new patent

Exposure device, exposure method and manufacturing semiconductor device


The present invention provides a highly controllable device for exposure from the back side and an exposure method, and also provides a method of manufacturing a semiconductor device using the same. The present invention involves exposure with the use of the back side exposure device of which a reflecting means is disposed on the front side of a substrate, apart from a photosensitive thin film surface by a distance x (x=0.1 μm to 1000 μm), and formation of a photosensitive thin film pattern in a self alignment manner, with good controllability, at a position a distance y away from the end of a pattern.
Semiconductor Energy Laboratory Co., Ltd.
01/29/15
20150028956
new patent

Semiconductor device


The disclosed invention is intended to adjust the driving power of an oscillation circuit to be optimal with a simple circuit configuration. A chip includes an oscillation circuit, an amplifier, an effective value measuring circuit, and a control unit.
Renesas Electronics Corporation
01/29/15
20150028936
new patent

Semiconductor device and display device


A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (t1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (t2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (t1). A gate terminal of the transistor (t2) is connected to the source terminal of the transistor (t2).
Sharp Kabushiki Kaisha
01/29/15
20150028925
new patent

Drive circuit for semiconductor device


A drive circuit is provided with an input terminal for receiving input signals, an output terminal that outputs drive signals generated from the input signals, a control power supply terminal that receives a control power supply voltage, an output terminal that outputs an output signal, and a reset terminal that receives a reset signal. The output signal is given to a gate of a mosfet.
Mitsubishi Electric Corporation
01/29/15
20150028914
new patent

Semiconductor device and forming the same


A semiconductor device includes a through silicon via (tsv) formed in a semiconductor substrate including a first-type impurity; and a first doping region formed in the semiconductor substrate located below the tsv. The first doping region is configured to include a second-type impurity and selectively electrically coupled to the tsv..
Sk Hynix Inc.
01/29/15
20150028909
new patent

Semiconductor device


A semiconductor device includes: a first circuit; a first power switch provided either between a power supply potential terminal and a power supply potential node of the first circuit or between a reference potential terminal and a reference potential node of the first circuit; a power switch control circuit configured to control a voltage of a control terminal of the first power switch; a test terminal; and a first test control circuit configured to control connection of the test terminal and the control terminal of the first power switch.. .
Fujitsu Limited
01/29/15
20150028674
new patent

Four-terminal circuit element with photonic core


A four-terminal circuit element is described that includes a photonic core inside of the circuit element that uses a wide bandgap semiconductor material that exhibits photoconductivity and allows current flow through the material in response to the light that is incident on the wide bandgap material. The four-terminal circuit element can be configured based on various hardware structures using a single piece or multiple pieces or layers of a wide bandgap semiconductor material to achieve various designed electrical properties such as high switching voltages by using the photoconductive feature beyond the breakdown voltages of semiconductor devices or circuits operated based on electrical bias or control designs.
Lawrence Livermore National Security, Llc
01/29/15
20150028497
new patent

Encapsulant with base for use in semiconductor encapsulation, semiconductor apparatus, and manufacturing semiconductor apparatus


The present invention provides an encapsulant with a base for use in semiconductor encapsulation, for collectively encapsulating a device mounting surface of a substrate on which semiconductor devices are mounted, or a device forming surface of a wafer on which semiconductor devices are formed, the encapsulant comprising the base, an encapsulating resin layer composed of an uncured or semi-cured thermosetting resin formed on one surface of the base, and a surface resin layer formed on the other surface of the base. The encapsulant enables a semiconductor apparatus having a good appearance and laser marking property to be manufactured..
Shin-etsu Chemical Co., Ltd.
01/29/15
20150028496
new patent

Semiconductor device and forming overlapping semiconductor die with coplanar vertical interconnect structure


A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die.
Stats Chippac, Ltd.
01/29/15
20150028493
new patent

Semiconductor device and manufacturing method thereof


A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal.
Kabushiki Kaisha Toshiba
01/29/15
20150028492
new patent

Semiconductor devices having bit line structures disposed in trenches, methods of fabricating the same, packages including same, modules including the same, and systems including the same


Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate.
Sk Hynix Inc.
01/29/15
20150028483
new patent

Novel electromigration and adhesion using two selective deposition


A method of manufacturing a semiconductor device includes providing a semiconductor substrate, sequentially forming an etch stop layer and an interlayer dielectric layer on the semiconductor substrate, forming a copper metal interconnect structure in the interlayer dielectric layer, forming a copper layer in the copper metal interconnect structure, forming a cobalt layer on the copper layer, and forming an aluminum nitride layer on the cobalt layer. The stack of cobalt layer and copper layer effectively suppresses electromigration caused by diffusion of the copper layer into the interlayer dielectric layer, improves the adhesion between the copper layer and the etch stop layer, and prevents delamination..
Semiconductor Manufacturing International (shanghai) Corporation
01/29/15
20150028481
new patent

Semiconductor devices with ball strength improvement


A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region.
Taiwan Semiconductor Manufacturing Company, Ltd
01/29/15
20150028479
new patent

Semiconductor devices with close-packed via structures having in-plane routing and making same


The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (fs) and an opposite second side (bs). There is at least one conductive wafer-through via (v) comprising metal, and at least one recess (rdl) provided in the first side of the substrate and in the semiconductor material of the substrate.
Silex Microsystems Ab
01/29/15
20150028478
new patent

Semiconductor devices


A semiconductor device includes: a chip having at least one electrically conductive contact at a first side of the chip; an extension layer extending laterally from one or more sides of the chip; a redistribution layer on a surface of the extension layer and the first side, and coupled to the contact; an interposer having at least one electrically conductive contact at a first surface of the interposer and coupled to the redistribution layer, and at least one electrically conductive contact at a second surface of the interposer opposite to the first surface; a molding material at least partially enclosing the chip and the redistribution layer, and in contact with the interposer. Another semiconductor device includes: an interposer; a redistribution layer over the interposer; a circuit having first and second circuit portions, wherein the redistribution layer includes the first circuit portion, and the interposer includes the second circuit portion..
Intel Mobile Communications Gmbh
01/29/15
20150028476
new patent

Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs


Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming one or more openings in a front side of the semiconductor device and forming sacrificial plugs in the openings that partially fill the openings.
Micron Technology, Inc.
01/29/15
20150028475
new patent

Technique for wafer-level processing of qfn packages


Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip.
Maxim Integrated Products, Inc.
01/29/15
20150028471
new patent

Semiconductor device and forming through mold hole with alignment and dimension control


A semiconductor device includes a semiconductor die and an encapsulant formed over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface.
Stats Chippac, Ltd.
01/29/15
20150028469
new patent

Semiconductor assembly and manufacture


A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (si), and gallium nitride (gan) semiconductor device is fabricated on the substrate.
General Electric Company
01/29/15
20150028467
new patent

Semiconductor device and manufacturing the same


A semiconductor device can reduce the number of bonding wires. The semiconductor device includes two or more semiconductor elements each of which has electrodes on a first main surface and a second main surface, an electrode plate that has one surface which is bonded to electrodes on the first main surfaces of the semiconductor elements, with a first bonding material layer interposed therebetween, and extends over the electrodes on the first main surfaces of the two or more semiconductor elements, and a conductive plate that includes a first lead terminal and a semiconductor element bonding portion which is bonded to electrodes on the second main surfaces of the semiconductor elements.
Fuji Electric Co., Ltd.
01/29/15
20150028466
new patent

Semiconductor device and manufacturing method thereof


The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device has a plurality of power units placed in parallel in a predetermined direction, wherein each of the power units includes a plurality of semiconductor elements placed on a metal plate having predetermined gaps with each other.
Denso Corporation
01/29/15
20150028465
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes a semiconductor element that is mounted on a substrate, an electrode pad that contains aluminum as a main component and is provided in the semiconductor element, a copper wire that contains copper as a main component and connects a connection terminal provided on the substrate and the electrode pad, and an encapsulant resin that encapsulates the semiconductor element and the copper wire. When the semiconductor device is heated at 200° c.
Sumitomo Bakelite Company Limited
01/29/15
20150028458
new patent

Semiconductor device and fabricating the same


A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer.. .
Samsung Electronics Co., Ltd.
01/29/15
20150028457
new patent

Epitaxial substrate, semiconductor device, and manufacturing semiconductor device


The present invention includes: a silicon-based substrate; and an epitaxial growth layer that has a configuration in which first and second nitride semiconductor layers having different lattice constants and thermal expansion coefficients are alternately laminated, and is arranged on the silicon-based substrate so that a film thickness thereof is gradually reduced at an outer edge portion. As a result, there are provided an epitaxial substrate and a semiconductor device in which generation of cracks at the outer edge portion is suppressed, and a method for manufacturing the semiconductor device..
Shin-etsu Handotai Co., Ltd.
01/29/15
20150028456
new patent

Semiconductor device, a semiconductor wafer structure, and a forming a semiconductor wafer structure


Embodiments relate to a semiconductor device, a semiconductor wafer structure, and a method for manufacturing or forming a semiconductor wafer structure. The semiconductor device includes a semiconductor substrate with a first region having a first conductivity type and a second region having a second conductivity type.
Infineon Technologies Ag
01/29/15
20150028453
new patent

Semiconductor device and forming the same


A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate..
Sk Hynix Inc.
01/29/15
20150028451
new patent

Semiconductor device and designing the same


A semiconductor device includes: a semiconductor substrate having a memory cell array region and a peripheral circuit region; a ferroelectric capacitor formed over the semiconductor substrate in the memory cell array region; and a dummy capacitor formed over the semiconductor substrate in the peripheral circuit region, with a layered structure same as that of the ferroelectric capacitor, with an area larger than that of the ferroelectric capacitor, and with a line width not larger than the width of the ferroelectric capacitor.. .
Fujitsu Semiconductor Limited
01/29/15
20150028439
new patent

Memory cells, methods of fabrication, semiconductor device structures, memory systems, and electronic systems


A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure.
Micron Technology, Inc.
01/29/15
20150028430
new patent

Semiconductor devices and methods of manufacturing the same


Semiconductor devices and methods of manufacturing the same are disclosed. The semiconductor device a gate dielectric pattern on a substrate and a gate electrode on the gate dielectric pattern opposite the substrate.
Samsung Electronics Co., Ltd.
01/29/15
20150028429
new patent

Semiconductor device with reduced defects


A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate.
Semiconductor Manufacturing International Corp.
01/29/15
20150028428
new patent

Iii-v semiconductor device with interfacial layer


A semiconductor structure comprises a substrate including a iii-v material, and a high-k interfacial layer overlaying the substrate. The interfacial layer includes a rare earth aluminate.
Imec Vzw
01/29/15
20150028427
new patent

Semiconductor device


A semiconductor device includes: a substrate; a gate electrode which is arranged on a first surface of the substrate and has a plurality of gate finger electrodes, a source electrode which is arranged on the first surface of the substrate and has a plurality of source finger electrodes, the source finger electrode is close to the gate finger electrode; a drain electrode which is arranged on the first surface of the substrate and has a plurality of drain finger electrodes, the drain finger electrode faces the source finger electrode via the gate finger electrode; and a shield plate electrode which is arranged on the drain finger electrode and the first surface of the substrate between the gate finger electrode and the drain finger electrode via an insulating layer, is short-circuited to the source finger electrode, and shields electrically the gate finger electrode and the drain finger electrode from each other.. .
Kabushiki Kaisha Toshiba
01/29/15
20150028425
new patent

Three dimensional semiconductor device having lateral channel and manufacturing the same


A 3d semiconductor device and a method of manufacturing the same are provided. The 3d semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active line including a source region and a drain region formed on the insulating layer, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes..
Sk Hynix Inc.
01/29/15
20150028424
new patent

Method for fabricating semiconductor device


A semiconductor device includes a substrate including a first region and a second region, a gate dielectric layer formed on the substrate, and a metal electrode layer formed on the gate dielectric layer and including a compound of carbon and nitrogen, wherein a metal electrode formed from the metal electrode layer in the first region has a work function lower than a work function of a metal electrode formed from the metal electrode layer in the second region and a nitrogen concentration of the metal electrode of the first region is smaller than a nitrogen concentration of the metal electrode of the second region.. .
Sk Hynix Inc.
01/29/15
20150028423
new patent

Semiconductor device having dual metal silicide layers and manufacturing the same


A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers..
Samsung Electronics Co., Ltd.
01/29/15
20150028422
new patent

Analog circuit with improved layout for mismatch optimization


Embodiments include a semiconductor device comprising: a substrate; a first transistor formed on the substrate; and a second transistor formed on the substrate, wherein a common region of the semiconductor device forms (i) a drain region of the first transistor, and (ii) a source region of the second transistor, and wherein a gate region of the first transistor is electrically coupled to a gate region of the second transistor.. .
Marvell World Trade Ltd.
01/29/15
20150028421
new patent

Esd protection semiconductor device


A semiconductor substrate (1) is provided with a source region (2) and a drain region (3) of a first type of electrical conductivity arranged at a surface (10) at a distance from one another, a channel region (4) of a second type of electrical conductivity, which is opposite to the first type of electrical conductivity, arranged between the source region (2) and the drain region (3), and a gate electrode (6) arranged above the channel region (4). A substrate well (7) of the first type of electrical conductivity is arranged in the substrate (1) at a distance from the source region (2).
Ams Ag
01/29/15
20150028414
new patent

Insulated gate semiconductor device structure


In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers.
Semiconductor Components Industries, Llc
01/29/15
20150028413
new patent

Semiconductor device and manufacturing same


According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate.
Kabushiki Kaisha Toshiba
01/29/15
20150028412
new patent

Semiconductor device


A semiconductor device is provided that comprises a semiconductor substrate comprising an active area and a peripheral region adjacent the active area and structure positioned in the peripheral region for hindering the diffusion of mobile ions from the peripheral region into the active area.. .
Infineon Technologies Austria Ag
01/29/15
20150028411
new patent

Semiconductor device and forming the same


A semiconductor device includes a first gate structure formed in a semiconductor substrate; a second gate structure formed over the semiconductor substrate and over the first gate structure; and a bit line formed in the semiconductor substrate, and formed below the first gate structure.. .
Sk Hynix Inc.
01/29/15
20150028404
new patent

Semiconductor device with isolation insulating layer containing air gap


A semiconductor device having a solid-state image sensor which can prevent inter-pixel crosstalk more reliably. The device includes: a semiconductor substrate having a main surface; a first conductivity type impurity layer located over the main surface of the substrate; a photoelectric transducer including a first conductivity type impurity region and a second conductivity type impurity region which are joined to each other over the first conductivity type impurity layer; and transistors which configure a unit pixel including the photoelectric transducer and are electrically coupled to the photoelectric transducer.
Renesas Electronics Corporation
01/29/15
20150028400
new patent

Semiconductor device


A semiconductor device includes a gate electrode ge electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of t of a chip region ca wherein the gate electrode ge is formed as a film at the same layer level as a source electrode se electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode ge is constituted of a gate electrode portion g1 formed along a periphery of the chip region ca and a gate finger portion g2 arranged so that the chip region ca is divided into halves along the direction of x. The source electrode se is constituted of an upper portion and a lower portion, both relative to the gate finger portion g2, and the gate electrode ge and the source electrode se are connected to a lead frame via a bump electrode..
Renesas Electronics Corporation
01/29/15
20150028399
new patent

Semiconductor devices and methods of manufacturing the same


Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region.
Samsung Electronics Co., Ltd.
01/29/15
20150028391
new patent

Compound semiconductor device and manufacturing the same


A compound semiconductor device includes a substrate, a p-type first semiconductor layer over the substrate and contains antimony, a p-type second semiconductor layer over the first semiconductor layer and contains antimony, an n-type third semiconductor layer over the second semiconductor layer, a fourth semiconductor layer between the first semiconductor layer and the second semiconductor layer, the fourth semiconductor layer containing phosphorus and having a thickness in which electrons tunnel between the first semiconductor layer and the second semiconductor layer, a first electrode in ohmic contact with the first semiconductor layer, and a second electrode in ohmic contact with the third semiconductor layer. The first semiconductor layer is made from a material whose contact resistance with the first electrode is lower than contact resistance of the second semiconductor layer..
Fujitsu Limited
01/29/15
20150028389
new patent

Semiconductor devices comprising a fin


A semiconductor device may include a fin disposed over a workpiece. The fin may include: a first semiconductive material disposed over the workpiece; an oxide of the first semiconductive material disposed over the first semiconductive material; a second conductive material disposed over and spaced apart from the oxide of the first semiconductive material; a first insulating material disposed around and lining the second semiconductive material; a conductive material disposed around the first insulating material; and a second insulating material disposed between the oxide of the first semiconductive material and a portion of the conductive material facing the workpiece, the second insulating material further lining sidewalls of the conductive material..
Taiwan Semiconductor Manufacturing Company, Ltd.
01/29/15
20150028361
new patent

Optoelectronic semiconductor device


An optoelectronic semiconductor device includes at least one radiation-emitting and/or radiation-receiving semiconductor chip including a radiation passage surface and a mounting surface opposite the radiation passage surface, wherein the mounting surface includes a first electrical contact structure and a second electrical contact structure electrically insulated from the first electrical contact structure, and wherein the radiation passage surface is free of contact structures, a reflective sheath surrounding the at least one semiconductor chip at least in sections, and a protective sheath surrounding the at least one semiconductor chip and/or the reflective sheath at least in sections.. .
Osram Opto Semiconductors Gmbh
01/29/15
20150028355
new patent

Method of forming a semiconductor device


A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility.
Taiwan Semiconductor Manufacturing Company, Ltd.
01/29/15
20150028352
new patent

Semiconductor device


[solution means] a semiconductor device 1 includes a substrate 7 made of an n+ type sic and having a predetermined off-angle, a drift layer 8 made of an n− type sic and formed on the substrate 7, a plurality of unit cells 10 demarcated in the drift layer 8 by n− type epitaxial lines 13 including first lines 11 parallel to an off-direction of the substrate 7 and second lines 12 intersecting the first lines 11, a gate insulating film 17 formed on the drift layer 8, a gate electrode 18 formed on the gate insulating film 17, and a p− type relaxation layer 24 formed in the first lines 11 in the drift layer 8 and relaxing an electric field generated in the gate insulating film 17.. .
01/29/15
20150028351
new patent

Methods of forming buried junction devices in silicon carbide using ion implant channeling and silicon carbide devices including buried junctions


A semiconductor device structure according to some embodiments includes a silicon carbide substrate having a first conductivity type, a silicon carbide drift layer having the first conductivity type on the silicon carbide substrate and having an upper surface opposite the silicon carbide substrate, and a buried junction structure in the silicon carbide drift layer. The buried junction structure has a second conductivity type opposite the first conductivity type and has a junction depth that is greater than about one micron..
Cree, Inc.
01/29/15
20150028346
new patent

Aluminum nitride based semiconductor devices


Semiconductor structures and techniques are described which enable forming aluminum nitride (ain) based devices by confining carriers in a region of ain by exploiting the polar nature of ain materials. Embodiments of ain transistors utilizing polarization-based carrier confinement are described..
Massachusetts Institute Of Technology
01/29/15
20150028344
new patent

Semiconductor device, display device, and electronic device


A pixel includes a load, a transistor which controls a current supplied to the load, a storage capacitor, and first to fourth switches. By inputting a potential in accordance with a video signal into the pixel after the threshold voltage of the transistor is held in the storage capacitor, and holding a voltage of the sum of the threshold voltage and the potential, variations of a current value caused by variations of threshold voltage of a transistor can be suppressed.
Semiconductor Energy Laboratory Co., Ltd.
01/29/15
20150028339
new patent

Semiconductor device, display device, and electronic device


A semiconductor device including: one or more pieces of first wiring having a main wiring section and a bifurcation wiring section; one or a plurality of pieces of second wiring having a trunk wiring section and a plurality of branch wiring sections within a gap region between the main wiring section and the bifurcation wiring section; one or a plurality of transistors each divided and formed into a plurality of pieces, the plurality of branch wiring sections individually functioning as a gate electrode and the one or plurality of transistors having a source region formed within the main wiring section and within the bifurcation wiring section and having a drain region formed between the plurality of branch wiring sections; and one or a plurality of pieces of third wiring electrically connected to the drain region of the one or plurality of transistors.. .
C/o Japan Display West Inc.
01/29/15
20150028332
new patent

Semiconductor device, display device, and semiconductor device manufacturing method


This semiconductor device (100) includes a substrate (1), a gate electrode (11), a gate insulating film (12), an oxide semiconductor layer (13), a source electrode (14), a drain electrode (15), and a protective film (16). The upper and side surfaces of the oxide semiconductor layer are covered with the source and drain electrodes and the protective film.
Sharp Kabushiki Kaisha
01/29/15
20150028330
new patent

Semiconductor device and manufacturing semiconductor device


Provided is a semiconductor device in which a deterioration in electrical characteristics which becomes more noticeable as miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with each side surface of the first oxide semiconductor film and the second oxide semiconductor film; a first insulating film and a second insulating film over the source electrode and the drain electrode; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with an upper surface of the gate insulating film and facing an upper surface and the side surface of the second oxide semiconductor film..
Semiconductor Energy Laboratory Co., Ltd.
01/29/15
20150028329
new patent

Semiconductor device


The number of oxide semiconductor layers is increased with the parallel connection of a first transistor and a second transistor. The parasitic capacitance effects on the driving of the transistor.
Semiconductor Energy Laboratory Co., Ltd.


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