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Semiconductor Device patents



      
           
This page is updated frequently with new Semiconductor Device-related patent applications. Subscribe to the Semiconductor Device RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Device RSS RSS


Methods of forming semiconductor devices including low-k dielectric layer

Methods of forming semiconductor devices including low-k dielectric layer

Semiconductor device and method for manufacturing the same

Semiconductor device and method for manufacturing the same

Semiconductor device and method for manufacturing the same

Compound semiconductor device and method of manufacturing the same

Date/App# patent app List of recent Semiconductor Device-related patents
12/18/14
20140372958
 Triple-pattern lithography layout decomposition patent thumbnailnew patent Triple-pattern lithography layout decomposition
Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity.
12/18/14
20140372839
 Semiconductor device, semiconductor system and control method of semiconductor device patent thumbnailnew patent Semiconductor device, semiconductor system and control method of semiconductor device
A semiconductor device includes a mode register set suitable for generating a first internal control signal and a second internal control signal, a per-dram addressability (pda) driving unit suitable for resetting the mode register set in response to the first internal control signal and an input value of data inputted through a data pad, and a cycle redundancy check (crc) driving unit suitable for performing a crc operation by checking whether or not data are correctly inputted through the data pad without an error in response to the first internal control signal and the second internal control signal.. .
12/18/14
20140372690
 Memory system, semiconductor device and methods of operating the same patent thumbnailnew patent Memory system, semiconductor device and methods of operating the same
A memory system, a semiconductor memory device and methods of operating the same may perform a read operation on the basis of flag data stored in a flag register, without reading the flag data stored in a memory array, when performing the read operation, so that a time taken for the read operation may be reduced.. .
12/18/14
20140372666
 Semiconductor device with configurable support for multiple command specifications, and method regarding the same patent thumbnailnew patent Semiconductor device with configurable support for multiple command specifications, and method regarding the same
A device includes a nand flash memory, and a generic command interface configured to interpret both an open nand flash interface specification and a first nand flash specification to perform an associated one of command operations on the nand flash memory, the open nand flash interface specification and the first nand flash specification being different from each other.. .
12/18/14
20140371124
 Cleaning liquid for semiconductor device and method for cleaning substrate for semiconductor device patent thumbnailnew patent Cleaning liquid for semiconductor device and method for cleaning substrate for semiconductor device
(4)′ water.. .
12/18/14
20140370719
 Method of focus measurement, exposure apparatus, and method of manufacturing semiconductor device patent thumbnailnew patent Method of focus measurement, exposure apparatus, and method of manufacturing semiconductor device
A method of focus measurement of the embodiment irradiates exposure light from a first direction and projects first and second line-and-space patterns on a substrate. Further, exposure light is irradiated from a second direction and third and fourth line-and-space patterns are projected on the substrate.
12/18/14
20140370713
 Method of forming fine patterns of a semiconductor device patent thumbnailnew patent Method of forming fine patterns of a semiconductor device
A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region, where the widths of the narrow-width patterns are smaller than the resolution limitations in a photolithography process used to make the semiconductor device. The first and second regions may comprise cell array regions, with memory cells in the first region and peripheral circuits for operating the memory cells in the second region.
12/18/14
20140370706
 Semiconductor device and method for manufacturing the same patent thumbnailnew patent Semiconductor device and method for manufacturing the same
By using a conductive layer including cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a tft is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of cu can be prevented; thus, a highly reliable semiconductor device can be manufactured.
12/18/14
20140370704
 Methods of forming semiconductor devices including low-k dielectric layer patent thumbnailnew patent Methods of forming semiconductor devices including low-k dielectric layer
Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate.
12/18/14
20140370702
 Semiconductor device and method for fabricating the same patent thumbnailnew patent Semiconductor device and method for fabricating the same
A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment.
12/18/14
20140370699
new patent Method for fabricating semiconductor device
A method of fabricating a semiconductor device includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench and a second trench, forming a first conductive layer along sidewall surfaces and bottom surface of the first trench and forming a second conductive layer along sidewall surfaces and bottom surface of the second trench, forming a mask pattern on the second conductive layer, the mask pattern filling the second trench and being a bottom anti-reflective coating (barc), and removing the first conductive layer using the mask pattern.. .
12/18/14
20140370695
new patent Method for fabricating a semiconductor device
The present invention relates to a method for fabricating a semiconductor structure comprising a semiconductor layer and a metallic layer, to improve the breakdown voltage properties of the device and reduce leakage currents, the method comprises the steps of a) providing a semiconductor layer comprising defects and/or dislocations; b) removing material at one or more locations of the defects and/or dislocations thereby forming pits in the semiconductor layer, c) passivating the pits, and c) providing the metallic layer over the semiconductor layer. The invention also relates to a corresponding semiconductor structure..
12/18/14
20140370694
new patent Process for the manufacture of a semiconductor device
A method for the manufacture of at least part of a thin-film device including forming one or more indentations in a substrate, preferably a plastic substrate, an indentation having sidewalls and a base; filling at least one of the one or more indentations with a first ink, the first ink having a first material precursor, preferably a first metal-, semiconductor-, or a metal-oxide precursor; and, annealing at least a portion of the first ink such that a surface of the base inside the indentation is dewetted and a narrowed first structure of the first material inside of the indentation is formed.. .
12/18/14
20140370693
new patent Method for manufacturing a semiconductor device having a channel region in a trench
A method of manufacturing a semiconductor device includes forming a semiconductor diode by forming a drift region, forming a first semiconductor region of a first conductivity type in or on the drift region and electrically coupling the first semiconductor region to a first terminal via a first surface of a semiconductor body, etching a trench into the semiconductor body, and forming a channel region of a second conductivity type in the trench and electrically coupling the channel region to the first terminal via the first surface of the semiconductor body. A first side of the channel region adjoins the first semiconductor region..
12/18/14
20140370692
new patent Method of manufacturing semiconductor device, substrate processing apparatus and non-transitory computer-readable recording medium
Provided is a method of manufacturing a semiconductor device, which is capable of increasing the controllability of the concentration of carbon in a film by increasing the yield when a boron carbonitride film or a boron nitride film is formed. The method includes forming a film containing boron, carbon and nitrogen or a film containing boron and nitrogen on the substrate by performing, a predetermined number of times, a cycle including supplying a source gas consisting of boron and a halogen element to a substrate and supplying a reactive gas consisting of carbon, nitrogen and hydrogen to the substrate..
12/18/14
20140370688
new patent Method for separating and transferring ic chips
A method for separating a multiple number of semiconductor devices or semiconductor integrated circuits from a wafer on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed is provided. The method includes forming a mask pattern on a surface of the wafer, and separating each of the semiconductor devices or semiconductor integrated circuits along the mask pattern formed on the surface of the wafer.
12/18/14
20140370684
new patent Methods for forming sub-resolution features in semiconductor devices
Methods of forming semiconductor devices and features in semiconductor device structures include conducting an anti-spacer process to remove portions of a first mask material to form first openings extending in a first direction. Another anti-spacer process is conducted to remove portions of the first mask material to form second openings extending in a second direction at an angle to the first direction.
12/18/14
20140370682
new patent Method of manufacturing semiconductor device
Extension regions 7 are formed through implantation using offset sidewalls 6a of a footing profile as a mask, and sidewalls 9 are formed on the offset sidewalls 6a so that source and drain regions 10 are formed into the sidewall through implantation, so that the extension regions 7 are made separated away from both edges of the gate, contributing to enlargement in an effective gate length, and dealing with the narrowed gate pitch, without increasing the number of processes.. .
12/18/14
20140370679
new patent Semiconductor device and method of manufacturing the same
A semiconductor device according an aspect of the present disclosure may include an isolation layer formed within a substrate and formed to define an active region, a junction formed in the active region, well regions formed under the isolation layer, and a plug embedded within the substrate between the junction and the well regions and formed extend to a greater depth than the well regions.. .
12/18/14
20140370676
new patent Semiconductor device, memory system including the same, and method of manufacturing the same
The semiconductor device includes a vertical channel layer formed on a substrate; conductive layer patterns and insulating layer patterns alternately formed around a length of each of the vertical channel layer; and a charge storing layer pattern formed between each of the vertical channel layers and the conductive layer patterns, where each of the charge storing layer patterns is isolated by the insulating layer patterns.. .
12/18/14
20140370675
new patent Semiconductor device
A semiconductor device includes a plurality of conductive layers and a plurality of insulating layers formed alternately with each other, at least one channel layer passing through the plurality of conductive layers and the plurality of insulating layers, and at least one first charge blocking layer surrounding the at least one channel layer, wherein a plurality of first regions, interposed between the at least one channel layer and the plurality of conductive layers, and a plurality of second regions, interposed between the at least one channel layer and the plurality of insulating layers, are alternately defined on the at least one first charge blocking layer, and each of the plurality of first regions has a greater thickness than each of the plurality of second regions.. .
12/18/14
20140370674
new patent Semiconductor device and manufacturing method thereof
A vertical super junction mosfet and a lateral mosfet are integrated on the same semiconductor substrate. The lateral mosfet is electrically isolated from the vertical super junction mosfet by an n-buried isolating layer and an n-diffused isolating layer.
12/18/14
20140370672
new patent Method for fabricating semiconductor device
In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode.
12/18/14
20140370670
new patent Semiconductor device and manufacturing method thereof
It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed.
12/18/14
20140370669
new patent Method and system for a gallium nitride vertical jfet with self-aligned source and gate
A semiconductor device includes a iii-nitride substrate, a first iii-nitride epitaxial layer coupled to the iii-nitride substrate and having a mesa, and a second iii-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a iii-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second iii-nitride epitaxial layer and the iii-nitride gate structure..
12/18/14
20140370667
new patent Tapered nanowire structure with reduced off current
Non-planar semiconductor devices including at least one semiconductor nanowire having a tapered profile which widens from the source side of the device towards the drain side of the device are provided which have reduced gate to drain coupling and therefore reduced gate induced drain tunneling currents.. .
12/18/14
20140370665
new patent Power semiconductor device and method for manufacturing such a power semiconductor device
A method for manufacturing a power semiconductor device is disclosed which can include: providing a wafer of a first conductivity type; and applying on a second main side of the wafer at least one of a dopant of the first conductivity type for forming a layer of the first conductivity type and a dopant of a second conductivity type for forming a layer of the second conductivity type. A titanium layer with a metal having a melting point above 1300° c.
12/18/14
20140370660
new patent Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate.
12/18/14
20140370659
new patent Singulation apparatus and method
A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon.
12/18/14
20140370657
new patent Method of manufacturing semiconductor device
In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed.
12/18/14
20140370656
new patent Semiconductor device and manufacturing method thereof
A semiconductor device using an oxide semiconductor, with stable electric characteristics and high reliability. In a process for manufacturing a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation is performed by heat treatment and oxygen doping treatment is performed.
12/18/14
20140370654
new patent Semiconductor device and manufacturing method thereof
A step for forming an island-shaped semiconductor layer of a semiconductor device used in a display device is omitted in order to manufacture the semiconductor device with high productivity and low cost. The semiconductor device is manufactured through four photolithography processes: four steps for forming a gate electrode, for forming a source electrode and a drain electrode, for forming a contact hole, and for forming a pixel electrode.
12/18/14
20140370653
new patent Sputtering target and method for manufacturing semiconductor device
An object is to provide a deposition technique for depositing an oxide semiconductor film. Another object is to provide a method for manufacturing a highly reliable semiconductor element using the oxide semiconductor film.
12/18/14
20140370651
new patent Method of manufacturing semiconductor device
A semiconductor device includes a substrate made of a semiconductor material, an n-type semiconductor layer arranged on a portion of one principal surface of the substrate, and a p-type semiconductor layer arranged on a portion of the one principal surface of the substrate, the portion not provided with the n-type semiconductor layer. The n-type semiconductor layer includes a portion located right above the p-type semiconductor layer..
12/18/14
20140370645
new patent Method of manufacturing semiconductor device
An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, in an n-type semiconductor substrate, a p-type well as a p-type semiconductor region forming a part of a photodiode is formed and a gate electrode of a transfer transistor is formed.
12/18/14
20140370639
new patent Micro electro mechanical system, semiconductor device, and manufacturing method thereof
The present invention provides a mems and a sensor having the mems which can be formed without a process of etching a sacrifice layer. The mems and the sensor having the mems are formed by forming an interspace using a spacer layer.
12/18/14
20140370634
new patent Method for fabricating nitride semiconductor thin film and method for fabricating nitride semiconductor device using the same
A method for fabricating a nitride semiconductor thin film includes preparing a first nitride single crystal layer doped with an n-type impurity. A plurality of etch pits are formed in a surface of the first nitride single crystal layer by applying an etching gas thereto.
12/18/14
20140370631
new patent Removal of 3d semiconductor structures by dry etching
Various embodiments include methods of fabricating a semiconductor device that include providing a plurality of nanostructures extending away from a support, forming a flowable material layer between the nanostructures, forming a patterned mask over a first portion of the flowable material and the first portion of the plurality of nanostructures, such that a second portion of the flowable material and a second portion of the plurality of nanostructures are not located under the patterned mask and etching the second portion of the flowable material and the second portion of the plurality of nanostructures to remove the second portion of the flowable material and the second portion of the plurality of nanostructures to leave the first portion of the flowable material and the first portion of the plurality of nanostructures unetched.. .
12/18/14
20140370628
new patent Substrate processing apparatus, semiconductor device manufacturing method, substrate processing method, and recording medium
According to the present disclosure, it is possible to prevent particles from being generated and to improve substrate processing quality. A substrate processing apparatus includes cassette mounting unit on which process substrate cassette and dummy substrate cassette are mounted, the process substrate cassette being configured to accommodate a plurality of process substrates, and the dummy substrate cassette being configured to accommodate a plurality of dummy substrates, process chamber configured to process the process substrates and the dummy substrates, substrate support unit installed within the process chamber and provided with a plurality of substrate mounting portions where the process substrates and the dummy substrates are mounted, transfer unit configured to transfer the process substrates and the dummy substrates between the cassette mounting unit and the process chamber, and control unit configured to control substrate processing and to transfer processing of the process substrates and the dummy substrates..
12/18/14
20140370447
new patent Semiconductor device resolution enhancement by etching multiple sides of a mask
A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions.
12/18/14
20140370445
new patent Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes a photolithography process having steps of a developing solution immersing process. The steps of the developing solution immersing process includes step (a) of dropping a developing solution on a silicon carbide semiconductor substrate and forming a developing solution film so as to have a film thickness of more than 6 μm and step (b) of reducing the film thickness of the developing solution film to 6 μm or less..
12/18/14
20140370424
new patent Substrate with multilayer reflective film, reflective mask blank for euv lithography, method of manufacturing reflective mask for euv lithography and method of manufacturing semiconductor device
An object of the present invention is to provide a substrate with a multilayer reflective film and the like used in the manufacturing of a reflective mask blank for euv lithography which is to be subjected to dry etching with a cl-based gas, wherein in the substrate with the multilayer reflective film, the loss of protective films by the dry etching and subsequent wet cleaning is very limited. The present invention is a substrate with a multilayer reflective film used in the manufacturing of a reflective mask blank for euv lithography, comprising a substrate, a multilayer reflective film disposed on the substrate to reflect euv light, and a protective film disposed on the multilayer reflective film to protect the multilayer reflective film, the protective film includes an alloy containing at least two metals, the alloy being an all-proportional solid solution..
12/18/14
20140369646
new patent Methods of forming three-dimensionally integrated semiconductor systems including photoactive devices and semiconductor-on-insulator substrates
Three-dimensionally integrated semiconductor systems include a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (seoi) substrate. An optical interconnect is operatively coupled to the photoactive device.
12/18/14
20140369145
new patent Semiconductor device and test method thereof
A semiconductor chip includes a memory array including a plurality of memory cells, a plurality of terminals including a plurality of test terminals to output a result of a specific test, and a circuit that outputs the result to a selected one of the plurality of test terminals based on a chip identification data.. .
12/18/14
20140369144
new patent Chip tester and test method of semiconductor device
A chip tester includes a test unit suitable for performing a test on guarantee blocks and for detecting at least one second defective block from the guarantee blocks, a storage unit suitable for storing repair information, a determination unit suitable for comparing the number of available redundancy blocks, which are not allocated for first defective blocks, with the number of at least one second defective block, by referring to the repair information, and a guarantee block management unit suitable for updating the repair information to cancel allocation of at least one of a plurality of redundancy blocks based on a result of the comparison of the determination unit.. .
12/18/14
20140369131
new patent Method of operating semiconductor device
A semiconductor device is operated by, inter alia: programming selected memory cells by applying a first program voltage which is increased by a first step voltage to a selected word line and by applying a first pass voltage having a constant level to unselected word lines, and when a voltage difference between the first program voltage and the first pass voltage reaches a predetermined voltage difference, programming the selected memory cells by applying a second program voltage which is increased by a second step voltage lower than the first step voltage to the selected word line and by applying a second pass voltage which is increased in proportion to the second program voltage to first unselected word lines adjacent to the selected word line among the unselected word lines.. .
12/18/14
20140369125
new patent Semiconductor device, data programming device, and method for improving the recovery of bit lines of unselected memory cells for programming operation
A device comprises a non-volatile memory array, a first selection circuit selecting whether to make a first connection path between a first bit line and a first circuit node, and selecting whether to make a second connection path between the first bit line and a second circuit node, a power supplying circuit supplying a power supply voltage to the first circuit node, the power supply voltage being, when the first connection path is selected to be made, supplied to the first bit line, and a first voltage supplying circuit supplying a first voltage to the second circuit node, the first voltage being, when the second connection path is selected to be made, supplied to the first bit line, the first voltage and the power supply voltage being higher than a ground potential, and the first voltage being higher than the power supply voltage.. .
12/18/14
20140369121
new patent Semiconductor device
Disclosed is a semiconductor device, including: an active region defined in a shape extended in at least four different directions in a semiconductor substrate; and gates of first to fourth transistors formed on extended portions of the active region, respectively, in which the first to fourth transistors share one junction area.. .
12/18/14
20140369115
new patent Semiconductor device, method for fabricating the same, and memory system including the semiconductor device
Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an l shape, a second gate spacer formed on the first gate spacer to have an l shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer..
12/18/14
20140369106
new patent Semiconductor device with fuse array and operating method thereof
A semiconductor device includes a fuse array for storing normal fuse data and pattern data through a programming operation, a boot-up control unit suitable for generating an enable signal for enabling an output of the pattern data, and a pattern detection unit suitable for detecting a pattern of the pattern data in response to the enable signal, and generating a detection signal. The fuse array outputs the normal fuse data in response to the detection signal..
12/18/14
20140369080
new patent Compound semiconductor device and method of manufacturing the same
An algan/gan hemt includes: a compound semiconductor layer; a source electrode and a drain electrode formed on an upper side of the compound semiconductor layer; and an al—si—n layer being a high-resistance layer disposed in a lower portion of at least one of the source electrode and the drain electrode and higher in an electric resistance value than the source electrode and the drain electrode.. .
12/18/14
20140368635
new patent On-axis focus sensor and method
A focus height sensor in an optical system for inspection of semiconductor devices includes a sensor beam source that emits a beam of electromagnetic radiation. A reflector receives the beam of electromagnetic radiation from the sensor beam source and directs the beam toward a surface of a semiconductor device positioned within a field of view of the optical system.
12/18/14
20140368319
new patent Semiconductor device and chip identifier setting method
A semiconductor chip transmits a request signal which requests notification of the setting state of a chip identifier to another semiconductor chip connected to one of the upstream and downstream, receives a response signal indicating the setting state of the chip identifier and the value of the chip identifier, as a response to the request signal, and performs a chip identifier setting process based on the response signal. When receiving a request signal from another semiconductor chip connected to the other of the upstream and downstream, the semiconductor chip transmits a response signal indicating the setting state of the chip identifier and the value of the chip identifier, as a response to the request signal..
12/18/14
20140368261
new patent Semiconductor devices and semiconductor systems including the same
Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device.
12/18/14
20140368256
new patent Semiconductor systems
Semiconductor systems are provided. The semiconductor system includes a first semiconductor device and a second semiconductor device.
12/18/14
20140368246
new patent Semiconductor device and method for operating the same
Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock..
12/18/14
20140368245
new patent Duty rate detecter and semiconductor device using the same
A duty rate detection circuit includes a duty rate detection block suitable for outputting a duty rate detection signal by detecting a duty rate of a clock signal having a first logic duration and a second logic duration and an output control block suitable for comparing the number of the first logic duration and the number of the second logic duration for a detection period and controlling an output moment of the duty rate detection signal.. .
12/18/14
20140368243
new patent Clock phase adjusting circuit and semiconductor device including the same
A semiconductor device includes a buffer suitable for receiving an input signal, a clock buffer suitable for receiving a clock, a delay locked loop (dll) suitable for delaying the clock to generate a delay locked clock, a code generation unit suitable for generating a digital code corresponding to 1/n of the clock cycle where n is an integer equal to or more than two, a delay unit suitable for delaying the clock corrected by the dll by a value corresponding to the digital code to output a delayed clock, and a strobing unit suitable for strobing the input signal using the delayed clock.. .
12/18/14
20140368241
new patent Clock control device
A clock control device is disclosed, which relates to a technology for reducing the amount of current consumption when a semiconductor device operates at a high speed. The clock control device includes: a chip-select-signal control block configured to generate a chip-select-control signal by latching a chip select signal, and output a fast chip select signal according to the chip-select-control signal; and a clock control block configured to drive a clock signal in response to the fast chip select signal when a command clock enable signal is activated, thereby generating a clock control signal, wherein the chip-select-signal control block latches the chip-select-control signal, and controls the chip-select-control signal to be toggled after the command clock enable signal is transitioned..
12/18/14
20140368240
new patent Semiconductor device controllers
We describe a controller (130) for controlling a power semiconductor switching device (132) into a selected one of a plurality of states, the states including a fully-off state, a saturated-on state, and at least one intermediate state. The switching device controller includes a voltage sense input (142) to sense a voltage on the device; a current sense input (current feedback) to sense a current passing through the device; a negative feedback control circuit (138) coupled to the sense inputs, a control output (136) to provide to the power semiconductor switching device a drive signal with a response dependent on one or more adjustable parameters; and a circuit controller (140) to control the adjustable parameters responsive to state command data, to control the switching device into a selected state, in particular by controlling an effective resistance of the device.
12/18/14
20140368239
new patent Semiconductor device
Provided is a semiconductor device with an output circuit in which a variation of a common voltage is suppressed in an idling mode and in a normal mode. The output circuit provided in the semiconductor device includes a first termination resistor and a second termination resistor and a drive circuit which flows current through the termination resistors.
12/18/14
20140368238
new patent Semiconductor device and semiconductor system including the same
A semiconductor device includes a normal code generation unit capable of generating a normal code, a test code output unit capable of storing a plurality of preliminary test codes to output a test code in response to a test control signal, and a reference voltage generation unit capable of generating a normal reference voltage in a normal operation mode and generating a test reference voltage in a test operation mode in response to the normal code and the test code.. .
12/18/14
20140368230
new patent Semiconductor device, manufacturing method thereof, and measuring method thereof
To provide a semiconductor device capable of being easily subjected to a physical test without deteriorating characteristics. According to a measuring method of a semiconductor device in which an element layer provided with a test element including a terminal portion is sealed with first and second films having flexibility, the first film formed over the terminal portion is removed to form a contact hole reaching the terminal portion; the contact hole is filled with a resin containing a conductive material; heating is carried out after arranging a wiring substrate having flexibility over the resin with which filling has been performed so that the terminal portion and the wiring substrate having flexibility are electrically connected via the resin containing a conductive material; and a measurement is performed..
12/18/14
20140368226
new patent Semiconductor device and test method
A test voltage having a first voltage or a second voltage is applied to an output terminal of a complementary fuse that includes a first fuse to one end of which the first voltage is applied and the other end of which serves as the output terminal and a second fuse to one end of which the second voltage is applied and the other end of which is connected to the output terminal. The test voltage then stops being applied.
12/18/14
20140368224
new patent Test circuit and method for semiconductor device
A semiconductor device includes a first die, a second die coupled to the first die through a through-silicon-via (tsv), and a test circuit suitable for measuring a resistance of the tsv by controlling an amount of current flowing through the tsv.. .
12/18/14
20140368123
new patent Light-emitting metal-oxide-semiconductor devices and associated systems, devices, and methods
Various embodiments of solid state transducer (“sst”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (mos) capacitor, an active region operably coupled to the mos capacitor, and a bulk semiconductor material operably coupled to the active region.
12/18/14
20140368036
new patent Low power and low emi power stealing circuit for a control device
There is provided a device and a method for controlling a supply of power from an ac power source to a load. A switch is arranged in series electrical connection between the power source and the load, the switch having a first state in which the switch connects the load to the power source for supplying an electrical current from the power source to the load and a second state in which the switch disconnects the load from the power source.


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This listing is a sample listing of patent applications related to Semiconductor Device for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Semiconductor Device with additional patents listed. Browse our RSS directory or Search for other possible listings.
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Key IP Translations - Patent Translations



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