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Semiconductor Device patents



      

This page is updated frequently with new Semiconductor Device-related patent applications.




Date/App# patent app List of recent Semiconductor Device-related patents
05/19/16
20160143187 
 Semiconductor device and  manufacturing the same patent thumbnailnew patent Semiconductor device and manufacturing the same
A semiconductor device includes a semiconductor module which has an external terminal protruding from one surface thereof; a printed circuit board which is electrically and mechanically connected to the external terminal of the semiconductor module; a heatsink which abuts against the other surface of the semiconductor module opposite to the one surface; and a joint member which serves as an elastic support column having a first head portion and a second head portion. The first head portion is shaped like a truncated cone and disposed at one end of the elastic support column, and the second head portion is disposed at the other end of the elastic support column.
Fuji Electric Co., Ltd.


05/19/16
20160143133 
 Printed wiring board, semiconductor device and printed circuit board patent thumbnailnew patent Printed wiring board, semiconductor device and printed circuit board
A printed wiring board includes conductive layers laminated with insulator layers interposed. A land group including a plurality of lands arranged with intervals between each other, is formed in a rectangular region on a surface layer, among the plurality of conductive layers, when viewed in a direction perpendicular to the surface layer.
Canon Kabushiki Kaisha


05/19/16
20160142055 
 Semiconductor device patent thumbnailnew patent Semiconductor device
A semiconductor device includes a first circuit applying an enable signal having a first logic level and a clock signal having the first logic level, supplying a first voltage to a first node and converting a voltage level of the first node into a second logic level different from the first logic level, and a second circuit applying an enable signal having the second logic level and a clock signal having the first logic level, supplying a second voltage to a second node different from the first node and converting a voltage level of the second node into the second logic level. The second circuit includes an operation circuit performing a nand operation on the logic level of the enable signal and the voltage level of the second node, and a switch turned on in response to an output of the operation circuit and supplying the second voltage to the second node..

05/19/16
20160142050 
 Multiple-unit semiconductor device and  controlling the same patent thumbnailnew patent Multiple-unit semiconductor device and controlling the same
Provided are a multiple-unit semiconductor device that enables space savings and a method for controlling such a semiconductor device. A multiple-unit semiconductor device is brought into conduction by a si-fet being brought into conduction first and a gan device being brought into conduction after the si-fet has been brought into conduction..
Sharp Kabushiki Kaisha


05/19/16
20160142047 
 Semiconductor device patent thumbnailnew patent Semiconductor device
A sample-and-hold circuit including a transistor and a capacitor is connected to the differential circuit. The sample-and-hold circuit acquires voltage for correcting the offset voltage of the differential circuit by charging or discharging the capacitor through sampling operation.
Semiconductor Energy Laboratory Co., Ltd.


05/19/16
20160142011 
 Semiconductor device patent thumbnailnew patent Semiconductor device
A semiconductor device is formed by sealing, with a resin, a semiconductor chip (cp1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
Renesas Electronics Corporation


05/19/16
20160141447 
 Nitride semiconductor device and  producing the same patent thumbnailnew patent Nitride semiconductor device and producing the same
A method for producing a nitride semiconductor device. The method comprises providing a substrate made of a material other than a nitride semiconductor.
Nichia Corporation


05/19/16
20160141428 
 Process for manufacturing a semiconductor device comprising an empty trench structure and semiconductor device manufactured thereby patent thumbnailnew patent Process for manufacturing a semiconductor device comprising an empty trench structure and semiconductor device manufactured thereby
The process is based upon the steps of: forming a trench in a body including a substrate and at least one insulating layer; and depositing a metal layer above the body for closing the open end or mouth of the trench. The trench is formed by selectively etching the body, wherein the reaction by-products deposit on the walls of the trench and form a passivation layer along the walls of the trench and a restriction element in proximity of the mouth of the trench..
Stmicroelectronics S.r.l.


05/19/16
20160141423 
 Contacts for highly scaled transistors patent thumbnailnew patent Contacts for highly scaled transistors
A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (s/d) regions, a channel between the first and second s/d regions, a gate engaging the channel, and a contact feature connecting to the first s/d region.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/19/16
20160141422 
 Semiconductor device patent thumbnailnew patent Semiconductor device
A semiconductor device in which deterioration of electrical characteristics which becomes more noticeable as the transistor is miniaturized can be suppressed is provided. The semiconductor device includes an oxide semiconductor stack in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are stacked in this order from the substrate side over a substrate; a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor stack; a gate insulating film over the oxide semiconductor stack, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating film.
Semiconductor Energy Laboratory Co., Ltd.


05/19/16
20160141417 
new patent

Semiconductor device and fabricating the same


A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction..
Samsung Electronics Co., Ltd.


05/19/16
20160141416 
new patent

Semiconductor devices and fabrication methods


Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material.
Micron Technology, Inc.


05/19/16
20160141415 
new patent

Semiconductor device and fabrication method thereof


A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a p type well region and an n type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the p type well region and the n type well region, a gate electrode formed on the gate insulating layer, a p type well pick-up region formed in the p type well region, and a field relief oxide layer formed in the n type well region between the gate electrode and the drain region..
Magnachip Semiconductor, Ltd.


05/19/16
20160141414 
new patent

Method and power device with depletion structure


A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate.
Vanguard International Semiconductor Corporation


05/19/16
20160141413 
new patent

Semiconductor devices


Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region..

05/19/16
20160141412 
new patent

Silicon carbide semiconductor device and manufacture thereof


A silicon carbide semiconductor device and method of manufacture thereof is made by providing a channel control zone which has impurity concentration distribution increased gradually from a first doping boundary to reach a maximum value between the first doping boundary and a second doping boundary, then decreased gradually toward the second doping boundary, so that the silicon carbide semiconductor device is formed with a lower conduction resistance and increased drain current without sacrificing threshold voltage.. .
Hestia Power Inc.


05/19/16
20160141409 
new patent

Semiconductor device and manufacturing semiconductor device


A semiconductor device provided herein includes a trench in which a gate insulating layer (gil) and a gate electrode are located. A step is provided in a lateral surface of the trench.
Toyota Jidosha Kabushiki Kaisha


05/19/16
20160141407 
new patent

Semiconductor device and manufacturing semiconductor device


A method of manufacturing a semiconductor device is provided, the method including forming a first gate member on a semiconductor substrate through a gate insulating film, forming a spacer on the first gate member, flattening a surface of the spacer, forming a first gate by partially etching the first gate member using the spacer as a mask, forming a second gate member so as to cover the first gate and the spacer having the flattened surface, forming a first insulating film on a surface of the second gate member, and forming a second gate by causing the second gate member to retreat while removing the first insulating film by etching.. .
Lapis Semiconductor Co., Ltd.


05/19/16
20160141406 
new patent

Semiconductor to metal transition


A semiconductor device includes a diffusion barrier layer, a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers. The first semiconductor region includes a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers, a contact region in contact with the diffusion barrier layer, the contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration, and a damage region between the contact region and the transition region.
Infineon Technologies Ag


05/19/16
20160141405 
new patent

Semiconductor field plate for compound semiconductor devices


A transistor includes a source, a drain spaced apart from the source, and a heterostructure body having a two-dimensional charge carrier gas channel for connecting the source and the drain. The transistor further includes a semiconductor field plate disposed between the source and the drain.
Infineon Technologies Austria Ag


05/19/16
20160141403 
new patent

Semiconductor device and insulated gate bipolar transistor with transistor cells and sensor cell


A transistor cell region of a semiconductor device includes transistor cells that are electrically connected to a first load electrode. An idle region includes a gate wiring structure that is electrically connected to gate electrodes of the transistor cells.
Infineon Technologies Ag


05/19/16
20160141402 
new patent

Semiconductor device


A semiconductor substrate is provided with a first cell region, the first cell region including: an n-type emitter region; a p-type first top body region; an n-type first barrier region; an n-type first pillar region; and a p-type first bottom body region, the semiconductor substrate may further comprise: an n-type drift region; a p-type collector region; an n-type cathode region, the n-type first barrier region may include a first peak position where a peak of the n-type impurity density is present within a part linked to the n-type first pillar region, and a second peak position where a peak of the n-type impurity density is present within a part in contact with the gate insulating layer, and a depth of the first peak position from a front surface of the semiconductor substrate is different from a depth of the second peak position from the front surface of the semiconductor substrate.. .
Toyota Jidosha Kabushiki Kaisha


05/19/16
20160141401 
new patent

Semiconductor device


A semiconductor device has emitter regions disposed in at least one cell region in a first inter-trench region, not disposed in a middle inter-trench region, and disposed in at least one cell region in the second inter-trench region. Each of the emitter regions is disposed at a position that is not in contact with first trenches but is in contact with two second trenches defining the corresponding cell region..
Toyota Jidosha Kabushiki Kaisha


05/19/16
20160141400 
new patent

Semiconductor device


A semiconductor device is configured such that the distance between the trench gate in the igbt and the trench gate in the diode is reduced or a p-well layer is provided between the trench gate in the igbt and the trench gate in the diode.. .
Mitsubishi Electric Corporation


05/19/16
20160141399 
new patent

Method for forming a semiconductor device and a semiconductor device


A method for forming a semiconductor device comprises implanting a defined dose of protons into a semiconductor substrate and tempering the semiconductor substrate according to a defined temperature profile. At least one of the defined dose of protons and the defined temperature profile is selected depending on a carbon-related parameter indicating information on a carbon concentration within at least a part of the semiconductor substrate..
Infineon Technologies Ag


05/19/16
20160141397 
new patent

Semiconductor device and manufacturing the same


A semiconductor device including a transistor having a reduced number of oxygen vacancies in a channel formation region of an oxide semiconductor with stable electrical characteristics or high reliability is provided. A gate insulating film is formed over a gate electrode; an oxide semiconductor layer is formed over the gate insulating film; an oxide layer is formed over the oxide semiconductor layer by a sputtering method to form an stacked-layer oxide film including the oxide semiconductor layer and the oxide layer; the stacked-layer oxide film is processed into a predetermined shape; a conductive film containing ti as a main component is formed over the stacked-layer oxide film; the conductive film is etched to form source and drain electrodes and a depression portion on a back channel side; and portions of the stacked-layer oxide film in contact with the source and drain electrodes are changed to an n-type by heat treatment..
Semiconductor Energy Laboratory Co., Ltd.


05/19/16
20160141396 
new patent

Semiconductor device and manufacturing same


To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration.
Renesas Electronics Corporation


05/19/16
20160141394 
new patent

Semiconductor device and making


A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ild) layer proximate the gate structure, an ild stress layer proximate the top portion of gate structure and over the ild layer.
Taiwan Semiconductor Manufacturing Company Limited


05/19/16
20160141392 
new patent

Methods of manufacturing finfet semiconductor devices using sacrificial gate patterns and selective oxidization of a fin


A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.. .
Samsung Electronics Co., Ltd.


05/19/16
20160141388 
new patent

Methods of manufacturing semiconductor devices using masks having varying widths


In a method, a dummy gate layer structure and a mask layer are formed on a substrate. The mask layer is patterned to form masks.
Samsung Electronics Co., Ltd.


05/19/16
20160141386 
new patent

Method for forming semiconductor device with low sealing loss


A method for forming a semiconductor device, includes steps of: providing a substrate; forming a first seal layer over the substrate; forming a second seal layer atop the first seal layer; forming a patterned photoresist layer on the second seal layer; implanting a dopant into the substrate by using the patterned photoresist layer as a mask; executing a first removing process to remove the patterned photoresist layer, wherein the first seal layer has a higher etch rate than that of the second seal layer in the first removing process; and removing the second seal layer after removing the patterned photoresist layer.. .
United Microelectronics Corporation


05/19/16
20160141385 
new patent

Method of manufacturing nitride semiconductor device


A method of manufacturing a nitride semiconductor device includes: forming a transistor having a gate electrode schottky-joined to a nitride semiconductor layer; performing high-temperature annealing at a temperature of 200 to 360° c. For 8 to 240 hours on the transistor; and after the high-temperature annealing, performing rf burn-in by applying radiofrequency power to the transistor at a channel temperature of 180 to 360° c..
Mitsubishi Electric Corporation


05/19/16
20160141384 
new patent

Mask-less dual silicide process


A method of forming a semiconductor device is provided. The method includes forming a mask layer, such as an oxidized layer, over first source/drain regions in a first device region.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/19/16
20160141383 
new patent

Interlayer dielectric layer with two tensile dielectric layers


A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first tensile dielectric layer on the substrate; a metal gate in the first tensile dielectric layer; a second tensile dielectric layer on the first tensile dielectric layer; and a contact plug in the first tensile dielectric layer and the second tensile dielectric layer.
United Microelectronics Corp.


05/19/16
20160141381 
new patent

Semiconductor devices and methods for fabricating the same


Semiconductor devices and methods for fabricating the same are provided. The semiconductor devices include a fin active pattern formed to project from a substrate, a gate electrode formed to cross the fin active pattern on the substrate, a gate spacer formed on a side wall of the gate electrode and having a low dielectric constant and an elevated source/drain formed on both sides of the gate electrode on the fin active pattern.
Samsung Electronics Co., Ltd.


05/19/16
20160141380 
new patent

Method for manufacturing a semiconductor device, and semiconductor device


A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a main surface and a gate electrode which is within a trench between neighboring semiconductor mesas. The gate electrode is electrically insulated from the neighboring semiconductor mesas by respective dielectric layers.
Infineon Technologies Austria Ag


05/19/16
20160141379 
new patent

Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods


Devices and methods for forming semiconductor devices with middle of line capacitance reduction in self-aligned contact process flow and fabrication are provided. One method includes, for instance: obtaining a wafer with at least one source, drain, and gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; and forming at least one first and second small contact over the first and second contact regions.
Globalfoundries Inc.


05/19/16
20160141377 
new patent

Low temperature spacer for advanced semiconductor devices


Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (bn) spacer on a gate stack, such as a gate stack of a planar fet or finfet. The boron nitride spacer is fabricated using atomic layer deposition (ald) and/or plasma enhanced atomic layer deposition (peald) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (si), silicon germanium (sige), germanium (ge), and/or iii-v compounds.
International Business Machines Corporation


05/19/16
20160141376 
new patent

Vertical semiconductor device and manufacturing therefor


A vertical semiconductor device includes a semiconductor body having a front side, a backside arranged opposite to the front side and a lateral edge delimiting the semiconductor body in a horizontal direction perpendicular to the front side, a gate metallization arranged on the front side and extending at least close to the lateral edge; a contact metallization arranged on the front side and between the lateral edge and the gate metallization, and a backside metallization arranged on the backside and in electric contact with the contact metallization. The gate metallization is arranged around at least two sides of the contact metallization when viewed from above..
Infineon Technologies Austria Ag


05/19/16
20160141373 
new patent

Semiconductor devices including field effect transistors and methods of forming the same


A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern.

05/19/16
20160141371 
new patent

Silicon carbide semiconductor device and manufacturing the same


In order to provide a high-performance and reliable silicon carbide semiconductor device, in a silicon carbide semiconductor device including an n-type sic epitaxial substrate, a p-type body layer, a p-type body layer potential fixing region and a nitrogen-introduced n-type first source region formed in the p-type body layer, an n-type second source region to which phosphorus which has a solid-solubility limit higher than that of nitrogen and is easily diffused is introduced is formed inside the nitrogen-introduced n-type first source region so as to be separated from both of the p-type body layer and the p-type body layer potential fixing region.. .
Hitachi, Ltd.


05/19/16
20160141369 
new patent

Semiconductor and fabricating the same


Provided is a semiconductor and method of manufacturing the same, and a method of forming even doping concentration of respective semiconductor device when manufacturing multiple semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable in example by using ion injected blocking pattern.
Magnachip Semiconductor, Ltd.


05/19/16
20160141368 
new patent

Tall strained high percentage silicon-germanium fins


The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming one or more tall strained silicon germanium (sige) fins on a semiconductor on insulator (soi) substrate. The fins have a germanium (ge) concentration which may differ from the ge concentration within the top layer of the soi substrate.
Globalfoundries Inc.


05/19/16
20160141367 
new patent

Semiconductor devices including channel dopant layer


A semiconductor device includes a semiconductor substrate including a well dopant layer having a first conductivity type, a gate electrode on the well dopant layer, a channel dopant layer in the well dopant layer and spaced apart from a top surface of the semiconductor substrate, a channel region between the gate electrode and the channel dopant layer, and source/drain regions in the well dopant layer at both sides of the gate electrode. The channel dopant layer and the channel region have the first conductivity type.
Samsung Electronics Co., Ltd.


05/19/16
20160141366 
new patent

Field effect transistors and methods of forming same


Semiconductor devices and methods of forming the same are provided. A first gate stack is formed over a substrate, wherein the first gate stack comprises a first ferroelectric layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/19/16
20160141364 
new patent

Semiconductor device and manufacturing semiconductor device


Provided is a semiconductor device comprising: a first conductivity type base layer having a mos gate structure formed on its front surface side; a second conductivity type first collector layer formed on a rear surface side of the base layer; a second conductivity type second collector layer formed on a rear surface side of the first collector layer with a material the same with that of the base layer, the second collector layer formed to be thinner than the first collector layer and having a higher impurity concentration than that of the first collector layer; a collector electrode formed on a rear surface side of the second collector layer; and a second conductivity type separation layer surrounding the mos gate structure on a front surface side of the base layer and formed from a front surface of the base layer to a front surface of the first collector layer.. .
Fuji Electric Co., Ltd.


05/19/16
20160141360 
new patent

Iii-v semiconductor devices with selective oxidation


Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer..
International Business Machines Corporation


05/19/16
20160141357 
new patent

Semiconductor device and method


A semiconductor device and a method of making the same. The device includes a semiconductor substrate including a body region having a first conductivity type.
Nxp B.v.


05/19/16
20160141356 
new patent

Semiconductor device


A semiconductor device includes: a first conductivity type semiconductor substrate; and a plurality of second conductivity type semiconductor regions, the respective second conductivity type semiconductor regions being embedded in a plurality of stripe shaped trenches formed in the semiconductor substrate so that the respective second conductivity type semiconductor regions are extended in the row direction or the column direction in parallel with a first principal surface of the semiconductor substrate and are spaced in a fixed gap mutually. The semiconductor substrate and the plurality of the semiconductor regions are depleted by a depletion layer extended in the direction in parallel to the first principal surface from a plurality of pn junction interfaces, and the respective pn junction interfaces are formed between the semiconductor substrate and the plurality of the semiconductor regions..
Rohm Co., Ltd.


05/19/16
20160141355 
new patent

Active device and semiconductor device with the same


A semiconductor device is provided, comprising a substrate; a first well having a first conductive type and extending down from a surface of the substrate; a diffusion region doped with impurity of the first conductive type and extending down from a surface of the first well; and a plurality of active devices formed within the diffusion region, and the active devices arranged separately from each other. The active devices are electrically isolated from each other by the diffusion region.
Macronix International Co., Ltd.


05/19/16
20160141354 
new patent

Patterned back-barrier for iii-nitride semiconductor devices


A compound semiconductor device includes a iii-nitride buffer and a iii-nitride barrier on the iii-nitride buffer. The iii-nitride barrier has a different band gap than the iii-nitride buffer so that a two-dimensional charge carrier gas channel arises along an interface between the iii-nitride buffer and the iii-nitride barrier.
Infineon Technologies Austria Ag


05/19/16
20160141330 
new patent

Method for semiconductor selective etching and bsi image sensor


A method of selectively etching a semiconductor device and manufacturing a bsi image sensor device includes etching a doped silicon substrate with an hna solution for a predetermined time duration to obtain an etching solution having a concentration c1 of nitrite ions, etching the semiconductor device using the obtained etching solution. Etching the semiconductor device requires an initial concentration c0 of nitride ions that is lower than c1.
Semiconductor Manufacturing International (shanghai) Corporation


05/19/16
20160141320 
new patent

Wafer-level encapsulated semiconductor device, and fabricating same


A method of encapsulating semiconductor devices formed on a device wafer includes forming an assembly including a carrier wafer and a plurality of dams thereon. After the step of forming, the method attaches the plurality of dams to the device wafer to form a respective plurality of encapsulated semiconductor devices..

05/19/16
20160141302 
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes stacked groups each including interlayer insulating patterns and conductive patterns and stacked in at least two tiers, wherein the insulating patterns and the conductive patterns are alternately stacked over a substrate and separated by slits, and a support body including holes and formed between the stacked groups.. .
Sk Hynix Inc.


05/19/16
20160141297 
new patent

Semiconductor device and manufacturing the same


In one embodiment, a semiconductor device includes a substrate, and first to fourth interconnects provided on the substrate to be adjacent to one another. The device includes a first pad portion connected with the first or second interconnect, and a second pad portion adjacent to the first pad portion in a first direction.
Kabushiki Kaisha Toshiba


05/19/16
20160141292 
new patent

Cmos gate stack structures and processes


A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface..
Mie Fujitsu Semiconductor Limited


05/19/16
20160141289 
new patent

Semiconductor device and manufacturing same


To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate.
Renesas Electronics Corporation


05/19/16
20160141284 
new patent

Semiconductor device


A transistor (2) is provided on a semiconductor substrate (8). A temperature detection diode (4) for monitoring temperature of an upper surface of the semiconductor substrate (8) is provided on the semiconductor substrate (8).
Mitsubishi Electric Corporation


05/19/16
20160141282 
new patent

Method of fabricating multi-substrate semiconductor devices


A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer.
Samsung Electronics Co., Ltd.


05/19/16
20160141280 
new patent

Device-embedded image sensor, and wafer-level fabricating same


A device-embedded image sensor includes an image sensor formed in a first semiconductor substrate; a top conductive pad formed on a top surface of the first semiconductor substrate; and a semiconductor device formed in a second semiconductor substrate bonded to a bottom surface of the first semiconductor substrate, the semiconductor device electrically connected to the top conductive pad. A method for fabricating a device-embedded image sensor from a cmos image sensor wafer assembly that includes an image sensor and a conductive pad.
Omnivision Technologies, Inc.


05/19/16
20160141274 
new patent

Novel semiconductor device and structure


An integrated circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a first wire structure constructed to provide power to a portion of the first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and a second wire structure constructed to provide power to a portion of the second transistors, where the second wire structure is isolated from the first wire structure to provide a different power voltage to the portion of the second transistors.. .
Monolithic 3d Inc.


05/19/16
20160141273 
new patent

Semiconductor device


This semiconductor device is formed by stacking a plurality of semiconductor chips that each have a plurality of bump electrodes, each of the plurality of semiconductor chips being provided with an identification section formed on a respective side face. Each semiconductor chip has a similar arrangement for its respective plurality of bump electrodes, and each identification section is formed so that the positional relationship with a respective reference bump electrode provided at a specific location among the respective plurality of bump electrodes is the same in each semiconductor chip.
Ps4 Luxco S.a.r.l.


05/19/16
20160141272 
new patent

Semiconductor device and manufacturing same


A semiconductor device which is provided with: a wiring substrate which has a first region, and a relay pad and a connection pad that are arranged outside the first region; a first semiconductor chip which has an electrode pad that is formed on one surface, and which is mounted on the first region of the wiring substrate; a first wire that connects the electrode pad and the relay pad with each other; and a second wire that connects the relay pad and the connection pad with each other.. .
Ps4 Luxco S.a.r.l.


05/19/16
20160141269 
new patent

Multi-chip semiconductor device


A multi-chip semiconductor device includes a plate-shaped first semiconductor chip having a first connection portion in which a first semiconductor chip electrode is formed on a first main surface of the first semiconductor chip or on a first side surface vertical to the first main surface, and a plate-shaped second semiconductor chip having a second connection portion in which a second semiconductor chip electrode is formed on a second side surface vertical to a second main surface of the second semiconductor chip. Each of the first and second connection portions includes at least an inclined surface that is inclined with respect to each of the first and second main surfaces.
Olympus Corporation


05/19/16
20160141267 
new patent

Semiconductor device, manufacturing semiconductor device, and electronic apparatus


There is provided a semiconductor device, including a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a bonding electrode formed on a surface of the interlayer insulating layer, and a metal film which covers an entire surface of a bonding surface including the interlayer insulating layer and the bonding electrode.. .
Sony Corporation


05/19/16
20160141266 
new patent

Method of bonding with silver paste


A method for bonding with a silver paste includes coating a semiconductor device or a substrate with the silver paste. The silver paste contains a plurality of silver particles and a plurality of bismuth particles.
Hyundai Motor Company


05/19/16
20160141263 
new patent

Semiconductor device including built-in crack-arresting film structure


According to at least one embodiment of the present invention, a wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer.
International Business Machines Corporation


05/19/16
20160141260 
new patent

Pre-package and methods of manufacturing semiconductor package and electronic device using the same


Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate..

05/19/16
20160141256 
new patent

Method for manufacturing a semiconductor device, and semiconductor device


According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.. .
Infineon Technologies Ag


05/19/16
20160141250 
new patent

Barrier structure


A semiconductor device includes a dielectric material and an interconnect structure. The semiconductor device further includes a barrier layer positioned between the dielectric material and the interconnect structure.
Qualcomm Incorporated


05/19/16
20160141249 
new patent

Semiconductor devices


Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure.
Samsung Electronics Co., Ltd.


05/19/16
20160141247 
new patent

Semiconductor device and manufacturing method thereof


A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal.
Kabushiki Kaisha Toshiba


05/19/16
20160141246 
new patent

Semiconductor device


A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of international union of pure and applied chemistry (iupac) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench..

05/19/16
20160141243 
new patent

Semiconductor device and fabricating the same


A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed on the first region and the second region, respectively, a first contact formed on the first transistor, and a second contact formed on the second transistor.
Samsung Electronics Co., Ltd.


05/19/16
20160141241 
new patent

Semiconductor device and its manufacturing method


The reliability of a copper wire is improved without inhibiting the wiring resistance of the copper wire. For example, another metallic element segregates in the boundary region between a copper film cuf1 and a copper film cuf2, and at the upper side face part of a wiring gutter leading to the boundary region.
Renesas Electronics Corporation


05/19/16
20160141238 
new patent

Semiconductor device and forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp)


A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant.
Stats Chippac, Ltd.


05/19/16
20160141230 
new patent

Semiconductor device and lead frame having vertical connection bars


A semiconductor device includes a lead frame having a die support area and a plurality of inner and outer row leads surrounding the die support area, and a semiconductor die mounted on the die support area and electrically connected to the leads with bond wires. A molding material encapsulates the semiconductor die, the bond wires, and the leads, and defines a package body.

05/19/16
20160141228 
new patent

Device connection through a buried oxide layer in a silicon on insulator wafer


An approach to forming a semiconductor structure for a semiconductor device with connections through a buried oxide layer in a silicon on insulator wafer. A buried oxide layer is formed on a semiconductor substrate and at least one semiconductor device is formed on the buried oxide layer.
International Business Machines Corporation


05/19/16
20160141226 
new patent

Device connection through a buried oxide layer in a silicon on insulator wafer


An approach to forming a semiconductor structure for a semiconductor device with connections through a buried oxide layer in a silicon on insulator wafer. A buried oxide layer is formed on a semiconductor substrate and at least one semiconductor device is formed on the buried oxide layer.
International Business Machines Corporation


05/19/16
20160141220 
new patent

Hetero-bipolar transistor and producing the same


A semiconductor device provided with a substrate made of material except for semiconductors and having thermal conductivity greater than that of the semiconductor material. The semiconductor device provides, on the support, a metal layer, a primary mesa, and electrodes formed on the primary mesa.
Sumitomo Electric Industries, Ltd.


05/19/16
20160141215 
new patent

Method for manufacturing semiconductor device


The reliability of multipoint contact by a contact pin with an external terminal is improved while achieving an improvement in easiness of manufacture of the contact pin. The contact pin includes first and second contact pins.
Renesas Electronics Corporation


05/19/16
20160141211 
new patent

Semiconductor device including power and logic devices and related fabrication methods


semiconductor device structures and related fabrication methods are provided. An exemplary fabrication method involves forming a layer of gate electrode material overlying a semiconductor substrate, forming a layer of masking material overlying the gate electrode material, and patterning the layer of masking material to define a channel region within a well region in the semiconductor substrate that underlies the gate electrode material.

05/19/16
20160141204 
new patent

Trench having thick dielectric selectively on bottom portion


A method of fabricating a semiconductor device includes etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from the top surface into the semiconductor substrate. A dielectric liner of a first dielectric material is formed on the bottom surface and sidewalls of the trench to line the trench.
Texas Instruments Incorporated


05/19/16
20160141202 
new patent

Air gap formation in interconnection structure by implantation process


Methods for forming air gaps in an interconnection structure with desired materials formed on different locations of the interconnection structure using an ion implantation process to define an etching boundary followed by an etching process for semiconductor devices are provided. In one embodiment, a method for forming air gaps in an interconnection structure on a substrate, the method includes implanting ions in a first region of an insulating material disposed on a substrate, leaving a second region without implanted ions, the second region having a first surface interfaced with the first region and a second surface interfaced with the substrate, and performing an etching process to selectively etch the second region away from the substrate, forming an air gap between the first region and the substrate..
Applied Materials, Inc.


05/19/16
20160141186 
new patent

Decapsulation method and decapsulation system for plastic molded ic package


A plastic mold decapsulation method and decapsulation system is provided for decapsulating a semiconductor device molded by plastic. A plastic mold decapsulation method and decapsulation system for decapsulating a plastic molded semiconductor device includes decapsulating the molded semiconductor device using a solution having dissolved metal in a liquid including acid.
Nippon Scientific Co., Ltd.


05/19/16
20160141182 
new patent

Slurry compositions and methods of fabricating semiconductor devices using the same


Provided are slurry compositions for polishing a germanium-containing layer and methods of fabricating a semiconductor device using the same. The slurry composition may include a polishing particle, an oxidizing agent, a polishing accelerator, and a selectivity control agent.
Samsung Electronics Co., Ltd.


05/19/16
20160141181 
new patent

Semiconductor device, fabricating the same, and apparatus used in fabrication thereof


A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided..

05/19/16
20160141180 
new patent

Sonos stack with split nitride memory layer


A semiconductor device includes a polysilicon substrate, a first oxide layer formed on the polysilicon substrate, an oxygen-rich nitride layer formed on the first oxide layer, a second oxide layer formed on the oxygen-rich nitride layer, and an oxygen-poor nitride layer formed on the second oxide layer.. .
Cypress Semiconductor Corporation


05/19/16
20160141179 
new patent

Selective growth for high-aspect ration metal fill


An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon.
Taiwan Semiconductor Manufacturing Company, Ltd.


05/19/16
20160141173 
new patent

Method of manufacturing semiconductor device, substrate processing apparatus, gas supply system, and recording medium


A method of manufacturing a semiconductor device includes alternately performing supplying a first process gas containing silicon and a halogen element to a substrate having a surface on which monocrystalline silicon and an insulation film are exposed and supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing silicon to the substrate, whereby a first silicon film is homo-epitaxially grown on the monocrystalline silicon and a second silicon film differing in crystal structure from the first silicon film is grown on the insulation film.. .
Hitachi Kokusai Electric Inc.


05/19/16
20160141171 
new patent

Photoresist pattern trimming methods


Provided are methods of trimming photoresist patterns. The methods involve coating a photoresist trimming composition over a photoresist pattern, wherein the trimming composition includes a matrix polymer, a thermal acid generator and a solvent, the trimming composition being free of cross-linking agents.
Rohm And Haas Electronic Materials Llc


05/19/16
20160141043 
new patent

Semiconductor device


A semiconductor device is provided. The semiconductor device may include a memory block including memory strings connected to respective bit lines coupled to a substrate and commonly connected to a common source line coupled to the substrate.
Sk Hynix Inc.


05/19/16
20160141038 
new patent

Semiconductor device


A semiconductor device includes memory blocks including a plurality of memory cells, wherein the plurality of memory cells are divided into a plurality of pages, and an operation circuit suitable for outputting operating voltages to local lines of the memory blocks to perform a program loop, an erase loop and a read operation on the plurality of memory cells, wherein the operation circuit is suitable for applying a dummy pulse having a positive potential to the local lines after the program loop or the erase loop is completed.. .
Sk Hynix Inc.


05/19/16
20160141011 
new patent

Semiconductor device and operating method thereof


Provided is a semiconductor device and an operating method thereof. The operating method of the semiconductor device includes performing an erase operation on a memory block including bottom dummy cells, a plurality of memory cells, top dummy cells and selection transistors arranged in a vertical direction with respect to a pipe gate, increasing threshold voltages of the top and bottom dummy cells at substantially a same time by applying a first soft program voltage to a bottom dummy word line coupled to the bottom dummy cells and a second soft program voltage greater than the first soft program voltage to the top dummy word line coupled to the top dummy cells, verifying the top and bottom dummy cells, and repeatedly performing the erase operation and increasing the threshold voltages by gradually increasing the first and second soft program voltages until the verifying of the top and bottom dummy cells passes..
Sk Hynix Inc.






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