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Semiconductor Device patents



      
           
This page is updated frequently with new Semiconductor Device-related patent applications. Subscribe to the Semiconductor Device RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Device RSS RSS


Semiconductor device

Kabushiki Kaishi Toyota Jidoshokki

Semiconductor device

Semiconductor device and method of writing data to semiconductor device

Renesas Electronics

Semiconductor device and method of writing data to semiconductor device

Semiconductor device and method of writing data to semiconductor device

International Business Machines

Semiconductor device including enhanced variability


Date/App# patent app List of recent Semiconductor Device-related patents
07/23/15
20150208524 
 Semiconductor device patent thumbnailSemiconductor device
A connecting terminal includes an external terminal connecting portion, having an end surface to connect an external terminal thereto and located at a second principal surface side of a second circuit board faces, and a substrate-fixed portion which is securely connected to a first circuit board. A seal attachment portion is provided on a portion of the external terminal connecting portion including the end surface to attach thereto a seal member to seal a gap between the portion and the case.
Kabushiki Kaisha Toyota Jidoshokki


07/23/15
20150208500 
 Semiconductor device patent thumbnailSemiconductor device
A semiconductor device includes a terminal electrode and a terminal electrode placement member. The terminal electrode includes a substrate-fixed portion secured to the circuit substrate through a fastening member, and an external wiring connection portion to which an external wiring is connected.
Kabushiki Kaishi Toyota Jidoshokki


07/23/15
20150207629 
 Semiconductor device and  writing data to semiconductor device patent thumbnailSemiconductor device and writing data to semiconductor device
A semiconductor device in related art has a problem that security at the time of writing data cannot be sufficiently assured. A semiconductor device of the present invention has: a unique code generating unit generating an initial unique code which is a value unique to a device and includes an error in a random bit; a first error correcting unit correcting an error in the initial unique code to generate an intermediate unique code; a second error correcting unit correcting an error in the intermediate unique code to generate a first determinate unique code; and a decrypting unit decrypting, with the first determinate unique code, transmission data obtained by encrypting confidential information with key information generated on the basis of the intermediate unique code by an external device to generate confidential information..
Renesas Electronics Corporation


07/23/15
20150207505 
 Semiconductor device including enhanced variability patent thumbnailSemiconductor device including enhanced variability
A physical unclonable function (puf) semiconductor device includes a semiconductor substrate, and a well formed in the semiconductor substrate. The well includes a first region having a first concentration of ions, and at least one second region having a second concentration that is less than the first concentration.
International Business Machines Corporation


07/23/15
20150207445 
 Semiconductor device and driving apparatus patent thumbnailSemiconductor device and driving apparatus
In a drive system using a single synchronous motor which is not paired with a synchronous generator, even if a failure occurs in an analog angle data converter for detecting the rotation angle of the synchronous motor, the driving of the synchronous motor can be continued in a temporal emergency manner. In addition to an analog angle data converter for converting an analog sense signal which is output from a rotation angle sensor of a synchronous motor to digital angle data, a digital angle data converter for converting digital data generated by an analog-to-digital converter to digital angle data is provided.
Renesas Electronics Corporation


07/23/15
20150207407 
 Semiconductor device, semiconductor module, and electronic circuit patent thumbnailSemiconductor device, semiconductor module, and electronic circuit
According to one embodiment, in semiconductor device, first semiconductor region is provided between first electrode and second electrode. Second semiconductor region is provided between first semiconductor region and second electrode.
Kabushiki Kaisha Toshiba


07/23/15
20150207074 
 Deposition method and a deposition apparatus of fine particles, a forming method and a forming apparatus of carbon nanotubes, and a semiconductor device and a manufacturing  the same patent thumbnailDeposition method and a deposition apparatus of fine particles, a forming method and a forming apparatus of carbon nanotubes, and a semiconductor device and a manufacturing the same
A deposition method of fine particles, includes the steps of irradiating a fine particle beam formed by size-classified fine particles to an irradiated subject under a vacuum state, and depositing the fine particles on a bottom part of a groove structure formed at the irradiated subject.. .
Fujitsu Limited


07/23/15
20150207063 
 Semiconductor device patent thumbnailSemiconductor device
The present invention provides a magnetoresistive effect element which performs writing by a novel method. In a state in which a current does not flow in a magnetization free layer mfr, the magnetization free layer mfr has a magnetic wall mw1 on the side of a magnetization fixed layer mfx1.
Renesas Electronics Corporation


07/23/15
20150207050 
 Semiconductor package and manufacturing method thereof patent thumbnailSemiconductor package and manufacturing method thereof
For a semiconductor package mounted on a mounting member with wiring which connects an electrode on the upper surface of an led device (semiconductor device) and an electrode at the mounting member side formed by a droplet discharge method or printing method, a stress relaxation film to reduce stresses applied to the wiring due to the difference in expansion/contraction between a land at the level difference sections and the wiring is formed at least at the level difference sections in the land which forms wiring, and the wiring is formed by a droplet discharge method or printing method on the stress relaxation film. The stress relaxation film may be formed of an insulating material for which the difference of the linear expansion coefficient from wiring is as small as possible and for which the young's modulus is as large as possible..
Fuji Machine Mfg Co., Ltd.


07/23/15
20150207033 
 Nanopyramid sized opto-electronic structure and  manufacturing of same patent thumbnailNanopyramid sized opto-electronic structure and manufacturing of same
Aspects of the invention provide methods and devices. In one embodiment, the invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, leds and transistors.
Glo Ab


07/23/15
20150206981 

Semiconductor device, display device, and manufacturing semiconductor device


There is provided a semiconductor device including a first region which, in an oxide semiconductor layer, has a higher carrier concentration than a channel region immediately below a gate electrode formed over the oxide semiconductor layer and is formed at least in a partial region other than the channel region, and a second region which, in the oxide semiconductor layer, has a higher carrier concentration than the first region and is formed farther from the channel region than the first region. The first region is formed through a first reduction reaction by stacking a first reduction reaction film over the oxide semiconductor layer and reducing the oxide semiconductor layer by the first reduction reaction film.
Sony Corporation


07/23/15
20150206979 

Semiconductor device and manufacturing same


This semiconductor device (101) includes: a substrate (1); a thin-film transistor (10) which includes an oxide semiconductor layer (6) as its active layer; a protective layer (11) covering the thin-film transistor; a metal layer (9d, 9t) interposed between the protective layer (11) and the substrate (1); a transparent conductive layer (13, 13t) formed on the protective layer (11); and a connecting portion (20, 30) to electrically connect the metal layer (9d, 9t) and the transparent conductive layer (13, 13t) together. The connecting portion (20, 30) includes an oxide connecting layer (6a, 6t) which is formed out of a same oxide film as a oxide semiconductor layer (6) and which has a lower electrical resistance than the oxide semiconductor layer (6).
Sharp Kabushiki Kaisha


07/23/15
20150206975 

Fin-type semiconductor device and manufacturing method


One embodiment of a semiconductor device includes a fin at a first side of a semiconductor body, a body region of a second conductivity type in at least a part of the fin, a drain extension region of a first conductivity type, a source region and a drain region of the first conductivity type, a source contact in contact with the source region, the source contact extending along a vertical direction along the source region, and a gate structure adjoining opposing walls of the fin. The body region and the drain extension region are arranged one after another between the source region and the drain region.
Infineon Technologies Austria Ag


07/23/15
20150206974 

Semiconductor device and fabricating the same


A semiconductor device includes a semiconductor substrate comprising a group iii element and a group v element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region.

07/23/15
20150206973 

Semiconductor device and manufacturing same


[solution] a method according to the present invention comprises: a step of forming dopant-diffused layers 5a, 5b on the main surface of a semiconductor substrate 1; a step of forming a trench 11 on a bottom surface of which is erected at least one semiconductor beam 4, each connected at one end to the dopant-diffused layer 5a and connected at the other end to the dopant-diffused layer 5b; a step of forming a gate insulating film 6 on an inner surface of the trench 11, including the side surfaces of each at least one semiconductor beam 4, and on an upper surface of each at least one semiconductor beam 4; a step of depositing a gate electrode material having a film thickness that fills the trench 11, after the gate insulating film 6 has been formed; and a step of removing the gate electrode material that is located outside the trench 11 as seen in a plan view, while leaving the gate electrode material that is located inside the trench 11 as seen in a plan view.. .

07/23/15
20150206972 

Method of making a cmos semiconductor device using a stressed silicon-on-insulator (soi) wafer


A method for forming a complementary metal oxide semiconductor (cmos) semiconductor device includes providing a stressed silicon-on-insulator (ssoi) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region.
Stmicroelectronics, Inc.


07/23/15
20150206969 

Semiconductor device, related manufacturing method, and related electronic device


A semiconductor device may include a semiconductor substrate. The semiconductor device may further include a gate electrode that overlaps the semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/23/15
20150206968 

Power ldmos semiconductor device with reduced on-resistance and manufacturing method thereof


An electronic semiconductor device including a semiconductor body having a first structural region and a second structural region, which extends on the first structural region and houses a drain region; a body region, which extends into the second structural region; a source region, which extends into the body region; and a gate electrode, which extends over the semiconductor body for generating a conductive channel between the source region and the drain region. The device includes a first conductive trench extending through, and electrically insulated from, the second structural region on one side of the gate electrode; and a second conductive trench extending through the source region, the body region, and right through the second structural region on an opposite side of the gate electrode, electrically insulated from the second structural region and electrically coupled to the body region and to the source region..
Stmicroelectronics S.r.l.


07/23/15
20150206967 

Semiconductor device


A semiconductor device includes a silicon carbide semiconductor substrate, a silicon carbide layer, a switching element section, and an overvoltage detection element section whose area is smaller than that of the switching element section. The switching element section includes a first electrode pad, a first terminal section surrounding the first electrode pad and provided in the silicon carbide layer, and a first insulating film covering the first terminal section.
Panasonic Intellectual Property Management Co., Ltd.


07/23/15
20150206966 

Semiconductor device and fabricating the same


The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region.. .
Vanguard International Semiconductor Corporation


07/23/15
20150206964 

Semiconductor device structure with metal ring on silicon-on-insulator (soi) substrate


In accordance with some embodiments, a semiconductor device is provided. The semiconductor device structure includes a substrate, and the substrate has a device region and an edge region.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/23/15
20150206962 

Semiconductor device, transistor having doped seed layer and manufacturing the same


A semiconductor device includes a substrate, and a seed layer over the substrate, wherein the seed layer comprises carbon dopants. The semiconductor device further includes a channel layer over the seed layer, and an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206960 

Semiconductor device


A semiconductor device 1 in which an igbt region 2 and a diode region 3 adjoining each other are formed on a same substrate 4 is presented. The semiconductor device 1 is provided with a plurality of first gate trenches 11 extending abreast in a first direction in the igbt region 2 and a plurality of second gate trenches 12 extending abreast in a second direction intersecting the first direction.
Toyota Jidosha Kabushiki Kaisha


07/23/15
20150206959 

Formation of a high aspect ratio trench in a semiconductor substrate and a bipolar semiconductor device having a high aspect ratio trench isolation region


Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening.
International Business Machines Corporation


07/23/15
20150206957 

Low-temperature fabrication of nanomaterial-derived metal composite thin films


Disclosed are new methods of fabricating nanomaterial-derived metal composite thin films via solution processes at low temperatures (<400° c.). The present thin films are useful as thin film semiconductors, thin film dielectrics, or thin film conductors, and can be implemented into semiconductor devices such as thin film transistors and thin film photovoltaic devices..
Polyera Corporation


07/23/15
20150206956 

Semiconductor device and manufacturing the same


A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (seg) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate..
Samsung Electronics Co., Ltd.


07/23/15
20150206955 

Methods of selectively growing source/drain regions of fin field effect transistor and manufacturing semiconductor device including a fin field effect transistor


The inventive concepts provide methods of manufacturing a semiconductor device. The method includes patterning a substrate to form an active pattern, forming a gate pattern intersecting the active pattern, forming a gate spacer on a sidewall of the gate pattern, forming a growth-inhibiting layer covering an upper region of the gate pattern, and forming source/drain electrodes at opposite first and second sides of the gate pattern..
Samsung Electronics Co., Ltd.


07/23/15
20150206946 

Semiconductor device and manufacturing method thereof


A semiconductor device includes a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; and an interconnect plug on the doped region. The raised source/drain region includes a top surface being elevated from a surface of the substrate; and a doped region exposed on the top surface.
Taiwan Semiconductor Manufacturing Company Ltd.


07/23/15
20150206945 

Semiconductor device and manufacturing method thereof


A semiconductor device includes a metal oxide semiconductor device disposed over a substrate and an interconnect plug. The metal oxide semiconductor device includes a gate structure located on the substrate and a raised source/drain region disposed adjacent to the gate structure.
Taiwan Semiconductor Manufacturing Company Ltd.


07/23/15
20150206941 

Silicon carbide semiconductor device having junction barrier schottky diode


A silicon carbide semiconductor device includes a junction barrier schottky diode including a substrate, a drift layer, an insulating film, a schottky barrier diode, and a plurality of second conductivity type layers. The schottky barrier diode includes a schottky electrode and an ohmic electrode.
Denso Corporation


07/23/15
20150206940 

Semiconductor device and producing same


The aim of the present invention is to provide a semiconductor device containing a graphene p-n vertical tunneling-junction diode by assessing the optical and electrical characteristics of a graphene p-n junction produced by varying the doping concentration. The semiconductor device includes first graphene of a first doping type, and second graphene of a second doping type different from the first doping type, which is arranged on the first graphene and is in contact therewith..
University-industry Cooperation Group Of Kyung Hee University


07/23/15
20150206937 

Trench-based power semiconductor devices with increased breakdown voltage characteristics


Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.. .
Fairchild Semiconductor Corporation


07/23/15
20150206936 

Semiconductor device and manufacturing method thereof


A semiconductor device includes a base dielectric layer, a semiconductor substrate layer disposed on the base dielectric layer, and a transistor disposed in the semiconductor substrate layer. The transistor includes a gate dielectric layer disposed on the semiconductor substrate layer, a gate electrode disposed on the gate dielectric layer, source and drain electrodes disposed within the semiconductor substrate layer on opposite sides of the gate electrode, an undoped channel region, a base dopant region, and a threshold voltage setting region.
Semiconductor Manufacturing International (shanghai) Corporation


07/23/15
20150206935 

Compound semiconductor device and manufacturing the same


An embodiment of a compound semiconductor device includes: a substrate; a compound semiconductor stacked structure formed over the substrate; and an amorphous insulating film formed between the substrate and the compound semiconductor stacked structure.. .
Fujitsu Limited


07/23/15
20150206934 

Method of manufacturing semiconductor device


Provided is a semiconductor device having improved reliability. Over a semiconductor substrate, a first coil is formed via a first insulating film.
Renesas Electronics Corporation


07/23/15
20150206923 

Semiconductor device and manufacturing semiconductor device


A semiconductor device includes a first fin-shaped semiconductor layer on a semiconductor substrate, a first insulating film around the first fin-shaped semiconductor layer, a first pillar-shaped semiconductor layer on the first fin-shaped semiconductor layer, a first gate insulating film around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film and extending in a direction perpendicular to the first fin-shaped semiconductor layer, a second diffusion layer disposed in a lower portion of the first pillar-shaped semiconductor layer, a third gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer, a first contact electrode surrounding the third gate insulating film, a second contact electrode that connects an upper portion of the first contact electrode to an upper portion of the first pillar-shaped semiconductor layer, and a first magnetic tunnel junction memory element on the second contact electrode.. .
Unisantis Electronics Singapore Pte. Ltd.


07/23/15
20150206920 

Semiconductor device


The performance of a semiconductor device is improved by preventing 1/f noise from being generated in a peripheral transistor, in the case where the occupation area of photodiodes, which are included in each of a plurality of pixels that form an image pickup device, is expanded. In the semiconductor device, the gate electrode of an amplification transistor is formed by both a gate electrode part over an active region and a large width part that covers the boundary between the active region and an element isolation region and the active region near the boundary and that.
Renesas Electronics Corporation


07/23/15
20150206916 

Semiconductor device and manufacturing method thereof


A manufacturing method of a semiconductor device includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer.
Xintec Inc.


07/23/15
20150206902 

Semiconductor device and forming the same


Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/23/15
20150206897 

Semiconductor device and manufacturing method thereof


A semiconductor device according to the embodiment includes a first stack structure. The first stack structure includes at least one first insulating film and a plurality of first conducting films above a surface of a substrate.
Kabushiki Kaisha Toshiba


07/23/15
20150206896 

Three-dimensional semiconductor device


A 3d semiconductor device is provided, comprising plural memory layers vertically stacked on a substrate and parallel to each other; plural selection lines disposed on the memory layers and parallel to each other; plural bit lines disposed on the selection lines, and the bit lines arranged in parallel to each other and in perpendicular to the selection lines; plural strings formed vertically to the memory layers and the selection lines, and the strings electrically connected to the corresponding selection lines; a plurality of cells respectively defined by the strings, the selection lines and the bit lines correspondingly, and the cells arranged in a plurality of rows and columns, wherein a column direction is parallel to the bit lines while a row direction is parallel to the selection lines. The adjacent cells in the same column are electrically connected to the different bit lines..
Macronix International Co., Ltd.


07/23/15
20150206895 

Semiconductor device and manufacturing the same


A semiconductor device may include interlayer insulating patterns and local word lines which are alternately stacked to form a stepped structure, and a first insulating layer formed on a surface of the stepped structure. The semiconductor device may also include a word line selection gate formed along a surface of the first insulating layer, and active patterns passing through the word line selection gate and the first insulating layer, and connected to the local word lines, respectively..
Sk Hynix Inc.


07/23/15
20150206891 

Semiconductor device and manufacturing the same


The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/23/15
20150206889 

Semiconductor device


A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an sram memory cell. In the sram memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor.
Renesas Electronics Corporation


07/23/15
20150206887 

Semiconductor device structure and manufacturing the same


In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate, and the substrate has a cell region and a logic region.
Taiwan Semiconductor Manufacturing Co., Ltd


07/23/15
20150206883 

Manufacturing capacitor structure and semiconductor device using the same


The instant disclosure relates to a semiconductor device which includes a semiconductor substrate, at least one patterned reinforcing layer, a plurality of lower electrodes, and a supporting layer. The at least one patterned reinforcing layer is arranged above the semiconductor substrate, wherein the at least one patterned reinforcing layer has a plurality of reinforcing structures configured to define a plurality of alignment apertures.
Inotera Memories, Inc.


07/23/15
20150206881 

Formation of silicide contacts in semiconductor devices


Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nfet) region and a p-type field effect transistor (pfet) region; performing a pre-amorphized implantation (pai) process to an n-type doped silicon (si) feature in on the nfet region and a p-type doped silicon germanium (sige) feature in the pfet region, thereby forming an n-type amorphous silicon (a-si) feature and a p-type amorphous silicon germanium (a-sige) feature; depositing a metal layer over each of the a-si and a-sige features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-si and the p-type a-sige features.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206877 

Non-merged epitaxially grown mosfet devices


Semiconductor devices having non-merged fin extensions. A semiconductor device includes fins formed in trenches in an insulator layer, each of the fins having a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench.
Renesas Electronics Corporation


07/23/15
20150206876 

Fin field effect transistors having heteroepitaxial channels


Disposable gate structures are formed over semiconductor material portions, and source and drain regions can be formed in the semiconductor material portions. After formation of a planarization dielectric layer, one type of disposable gate structure can be removed selective to at least another type of disposable gate structure employing a patterned hard dielectric mask layer.
International Business Machines Corporation


07/23/15
20150206875 

Finfet semiconductor device with germanium diffusion over silicon fins


A method for manufacturing a semiconductor device is described that comprises providing a substrate, forming a plurality of fins having a first semiconductor material, replacing a first portion of at least one of the fins with a second semiconductor material, and distributing the second semiconductor material from the first portion to a second portion of the at least one of the fins.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206874 

Semiconductor device and fabricating the same


Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a gate structure formed on a substrate, a source/drain extension formed at one side of the gate structure while not being formed at the other side of the gate structure, and doped with a first type impurity, a halo region formed at one side of the gate structure while not being formed at the other side of the gate structure, and doped with a second type impurity different from the first type impurity, a first source/drain region formed at one side of the gate structure and doped with the first type impurity, and a second source/drain region formed at the other side of the gate structure and doped with the first type impurity..
Samsung Electronics Co., Ltd.


07/23/15
20150206868 

Flip chip semiconductor device


A semiconductor device package comprises a lead frame having a die paddle comprising a first chip installation area and a second chip installation area, a recess area formed in the first chip installation area, and multiple metal pillars formed in the recess area, a notch divides the first chip installation area into a transverse base extending transversely and a longitudinal base extending longitudinally, and separates the recess area into a transverse recess part formed in the transverse base and a longitudinal recess part formed in longitudinal base; a portion of a transverse extending part connecting to an external pin extends into a portion inside of the notch.. .

07/23/15
20150206864 

Semiconductor device


The semiconductor device 10 is provided with a switching element (fet 14) provided on a substrate 18, a first electrode (electrode 13) provided on an opposite side of the substrate 18 interposing the switching element, a diode 12 provided on an opposite side of the switching element interposing the first electrode, and a second electrode (electrode 11) provided on an opposite side of the first electrode interposing the diode 12.. .

07/23/15
20150206863 

Semiconductor tsv device package to which other semiconductor device package can be later attached


A first package includes a laminate layer, an overmold layer above and in direct contact with the laminate layer, and a logic circuit-through-silicon via (tsv) layer including a first logic die and tsvs. The logic circuit-tsv layer is within the overmold layer, and the tsvs are electrically exposed at a top surface of the overmold layer.
International Business Machines Corporation


07/23/15
20150206860 

Semiconductor device


A plurality of arm elements is arrayed along a first direction of a substrate. Each arm element includes a plurality of semiconductor elements connected in parallel.
Kabushiki Kaishi Toyota Jidoshokki


07/23/15
20150206845 

Interconnect arrangement with stress-reducing structure and fabricating the same


Embodiments of a semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a substrate and a first layer formed over the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


07/23/15
20150206843 

Semiconductor device having a nanotube layer and forming


A method of forming a semiconductor device includes forming a first conductive layer over the substrate. A dielectric layer, having a first opening, is formed over the first conductive layer.
Freescale Semiconductor, Inc.


07/23/15
20150206842 

Semiconductor device and manufacturing the same


According to one embodiment, there is provided a semiconductor device using graphene, includes a catalyst layer formed on or in a substrate along with an interconnect pattern and a graphene layer formed on the catalyst layer. The graphene layer is arranged parallel to a narrower linewidth than the width of the interconnect pattern..
Kabushiki Kaisha Toshiba


07/23/15
20150206841 

Semiconductor device and manufacturing method thereof


A semiconductor device according to the present embodiment includes a first wiring made of copper. A metal film is provided on the first wiring and is made of cobalt, a cobalt alloy, nickel, or a nickel alloy.
Kabushiki Kaisha Toshiba


07/23/15
20150206840 

Semiconductor device structure and manufacturing the same


Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


07/23/15
20150206834 

Semiconductor device with combined power and ground ring structure


A semiconductor device includes a lead frame, and an integrated circuit die. The lead frame has a flag for supporting the die and leads that surround that flag and die.

07/23/15
20150206832 

Printed circuit board and stacked semiconductor device


A semiconductor package includes an interposer and a semiconductor element mounted on one surface of the interposer. A plurality of lands are formed on another surface of the interposer.
Canon Kabushiki Kaisha


07/23/15
20150206831 

Semiconductor device with webbing between leads


A quad flat package integrated circuit (ic) device has alternating inner and outer leads that protrude from a package body. The inner leads are j-shaped leads and the outer leads are gull-wing shaped leads.
Freescale Seminconductor, Inc.


07/23/15
20150206830 

Method of manufacturing semiconductor device and the semiconductor device


A lead frame having a first chip-mounting part on which a first semiconductor chip is mounted and having a second chip-mounting part on which a second semiconductor chip is mounted is prepared. Moreover, a process is provided, the process connecting a first electrode pad, which is formed on a top surface of the first semiconductor chip, with a first end of a first metal ribbon and connecting a ribbon-connecting surface on the second chip-mounting part with a second end of the first metal ribbon on the opposite side of the first end.
Renesas Electronics Corporation


07/23/15
20150206829 

Semiconductor package with interior leads


A packaged semiconductor device has a lead frame, a semiconductor die, and bond wires. The lead frame has a two-dimensional array of leads with a subset of interior leads located in the interior of the array that do not extend to the perimeter of the array.

07/23/15
20150206828 

Semiconductor device having barrier metal layer


According to one embodiment, a semiconductor device having an interlayer insulating film, a molybdenum containing layer, a barrier metal layer and a plug material layer is provided. The interlayer insulating film is formed on a substrate or on a conductive layer formed on a substrate.
Kabushiki Kaisha Toshiba


07/23/15
20150206827 

Semiconductor device with through silicon via and alignment mark


A semiconductor device with a semiconductor substrate having a first surface and an opposite-facing second surface, a through electrode electrically connected to the semiconductor element and penetrating the semiconductor substrate from the first surface to the second surface, and a conductor, not electrically connected to the semiconductor element, penetrating the semiconductor substrate from the first surface to the second surface, where the through electrode and the conductor have different shapes in plan view.. .
Ps4 Luxco S.a.r.l.


07/23/15
20150206826 

Semiconductor device and manufacturing semiconductor device


A semiconductor device including: a base material portion that includes a semiconductor substrate and an insulating film that is formed on one face of the semiconductor substrate and on which a vertical hole is formed along the thickness direction of the semiconductor substrate; a vertical hole wiring portion that includes a vertical hole electrode formed on a side wall of the base material portion that forms the vertical hole; a metallic film that is formed within the insulating film and that is electrically connected to the vertical hole wiring portion; and a conductive protective film that is formed to be in contact with the metallic film within the insulating film and that is formed in a region that includes a contact region of a probe during a probe test that is performed in the middle of manufacture on a film face of the metallic film.. .
Sony Corporation


07/23/15
20150206825 

Semiconductor device having through-silicon via


A semiconductor device includes a through electrode vertically passing through the semiconductor device; a metal pad electrically coupling the through electrode and an exterior; a data input block suitable for transferring a data signal to the metal pad in response to a write command; a through electrode storage block suitable for storing the data signal transferred through the metal pad; and a data output block suitable for outputting the data signal, which is stored in the through electrode storage block, to the exterior in response to a read command.. .
Sk Hynix Inc.


07/23/15
20150206822 

Carbon nanotube sheet, semiconductor device, manufacturing carbon nanotube sheet, and manufacturing semiconductor device


A carbon nanotube sheet includes a carbon nanotube aggregate in which a plurality of carbon nanotubes are arrayed, a thermoplastic resin portion formed in a center area of the carbon nanotube aggregate, and an uncured thermosetting resin portion formed in an outer periphery area of the carbon nanotube aggregate so as to surround the thermoplastic resin portion.. .
Shinko Electric Industries Co., Ltd.


07/23/15
20150206817 

Chip package and manufacturing the same


A package comprises a semiconductor device. The semiconductor device comprises an active surface and side surfaces.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206814 

Layer structure for mounting semiconductor device and fabrication method thereof


A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.. .
Siliconware Precision Industries Co., Ltd.


07/23/15
20150206813 

Methods and structures for processing semiconductor devices


Methods of processing a semiconductor device include attaching a semiconductor substrate to a carrier substrate, forming a silane material over an exposed portion of the carrier substrate, and curing the silane material to form a hydrophobic coating over the carrier substrate. The hydrophobic coating may reduce or prevent undercut of the semiconductor substrate due to wicking of adhesive from between the semiconductor substrate and the carrier substrate during processing.
Micron Technology, Inc.


07/23/15
20150206811 

Semiconductor device


According to one embodiment, a semiconductor device includes a semiconductor chip including a first terminal surface and a second terminal surface located on a side opposite to the first terminal surface. An insulation unit surrounds an outer circumference of a side surface of the semiconductor chip.
Kabushiki Kaisha Toshiba


07/23/15
20150206808 

Systems and methods for microwave-radiation annealing


Systems and methods are provided for annealing a semiconductor structure using microwave radiation. A semiconductor structure is provided.
Taiwan Semiconductor Manufacturing Company Limited


07/23/15
20150206807 

Semiconductor device and manufacturing method thereof


A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise connection verification for a first one or more mounted components prior to additional assembly..
Amkor Technology, Inc.


07/23/15
20150206806 

Method and system of measuring semiconductor device and fabricating semiconductor device using the same


The measurement method may include obtaining first measurement data from a recess region formed in a semiconductor substrate, obtaining second measurement data from a conductive pattern filling a portion of the recess region, calculating a first volume of the recess region from the first measurement data, calculating a second volume of the conductive pattern from the second measurement data, and calculating a measurement target parameter using a difference between the first and second volumes.. .

07/23/15
20150206805 

Semiconductor device with metal gate and high-k materials and fabricating the same


A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust species is formed over the first region and a second gate stack structure containing a second effective work function adjust species is formed over the second region.
Sk Hynix Inc.


07/23/15
20150206801 

Devices, systems, and methods related to planarizing semiconductor devices after forming openings


Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stop layer and a dielectric liner including dielectric material along sidewalls of openings, e.g., through-substrate openings, of the semiconductor device and excess dielectric material outside the openings.
Micron Technology, Inc.


07/23/15
20150206800 

Semiconductor device with air gap and fabricating the same


A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening; a second conductive pattern covering a top surface and sidewalls of the first conductive pattern; an air gap defined between sidewalls of the opening and the second conductive pattern; and a third conductive pattern capping the second conductive pattern and the air gap.. .
Sk Hynix Inc.


07/23/15
20150206797 

Semiconductor device and making same


One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.. .
Infineon Technologies Ag


07/23/15
20150206794 

Method for removing micro scratches in chemical mechanical polishing processes


A chemical mechanical polishing process for manufacturing a semiconductor device includes forming a conductive layer over a first dielectric layer formed over a semiconductor substrate. The conductive layer is patterned to form a patterned conductive layer with a plurality of openings.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206791 

Method for forming semiconductor device structure


In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer on a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/23/15
20150206787 

Method of manufacturing semiconductor device


An object of the invention is to provide a semiconductor device having improved performance. A method of manufacturing a semiconductor device includes: forming a trench and then forming a first insulating film made of a silicon oxide film through cvd using a gas containing an o3 gas and a teos gas to cover the side surface of the trench with the insulating film; forming a second insulating film made of a silicon oxide film through pecvd to cover the side surface of the trench with the second insulating film via the first insulating film; and forming a third insulating film made of a silicon oxide film through cvd using a gas containing an o3 gas and a teos gas to close the trench with the third insulating film while leaving a space in the trench..
Renesas Electronics Corporation


07/23/15
20150206769 

Lead frame based semiconductor device with power bars


A semiconductor device includes a semiconductor die having first and second opposing main surfaces and a die bonding pads on the first main surface, and a conductive member having first and second opposing main surfaces that surrounds the die. The die and the conductive member are encapsulated with a first encapsulant and form an expanded die.

07/23/15
20150206767 

Method of manufacturing semiconductor device


A false report on appearance inspection of a semiconductor device is prevented by suppressing variation in surface state of an electrodeposited gold electrode. In formation of an electrodeposited gold electrode, an electrodeposited gold electrode comprised of a plurality of electrodeposited gold layers in the stack is formed by alternately repeating a step of performing energization between an anode electrode and a cathode electrode provided in a treatment cup of a plating apparatus to cause crystal growth of an electrodeposited gold layer (energization on), and a step of performing no energization between the anode electrode and the cathode electrode (energization off).
Renesas Electronics Corporation


07/23/15
20150206758 

Method for manufacturing semiconductor device


A method includes: forming a front surface structure of a semiconductor element on a front surface side of a semiconductor substrate; forming crystal defects in the semiconductor substrate by implanting charged particles into the semiconductor substrate; subjecting the semiconductor substrate to a heat treatment after having formed the crystal defects; attaching a supporting plate on the front surface side of the semiconductor substrate after the heat treatment; thinning the semiconductor substrate by grinding a back surface side of the semiconductor substrate to which the supporting plate has been attached; and forming a back surface structure of the semiconductor element on a back surface of the thinned semiconductor substrate.. .
Toyota Jidosha Kabushiki Kaisha


07/23/15
20150206756 

Lowering tungsten resistivity by replacing titanium nitride with titanium silicon nitride


Semiconductor devices, methods and apparatus for forming the same are provided. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions.
Applied Materials, Inc.


07/23/15
20150206755 

Method of patterning a metal gate of semiconductor device


Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206746 

Semiconductor fins on a trench isolation region in a bulk semiconductor substrate and a forming the semiconductor fins


Disclosed are semiconductor structures with monocrystalline semiconductor fins, which are above a trench isolation region in a semiconductor substrate and which can be incorporated into semiconductor device(s). Also disclosed are methods of forming such structures by forming sidewall spacers on opposing sides of mandrels on a dielectric cap layer.
International Business Machines Corporation


07/23/15
20150206742 

Method of manufacturing semiconductor device and substrate processing apparatus


Provided is a technique of forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes: forming a first layer including a first element, wherein the first layer is a discontinuous layer, a continuous layer, or a layer in which at least one of the discontinuous layer or the continuous layer is overlapped; forming a second layer including the first layer and a discontinuous layer including a second element stacked on the first layer; forming a third layer by supplying a gas containing a third element to the substrate to modify the second layer; and forming a fourth layer including the first element, the second element, the third element and a fourth element by supplying a gas containing the fourth element to the substrate to modify the third layer..
Hitachi-kokusai Electric Inc.


07/23/15
20150206737 

Method of manufacturing semiconductor device and substrate processing apparatus


Provided is a technique of forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes: forming a first layer by supplying a gas containing a first element to the substrate, wherein the first layer is a discontinuous layer, a continuous layer, or a layer in which at least one of the discontinuous layer or the continuous layer is overlapped; forming a second layer including the first layer and a discontinuous layer including a second element stacked on the first layer; and forming a third layer by supplying a gas containing a third element to the substrate to modify the second layer under a condition where a modifying reaction of the second layer by the gas containing the third element is not saturated..
Hitachi-kokusai Electric Inc.


07/23/15
20150206736 

Method of manufacturing semiconductor device, substrate processing apparatus and non-transitory computer-readable recording medium


The uniformity of the thickness of the film of a film to be formed on a substrate within a plane of the substrate can be improved. A method of manufacturing a semiconductor includes performing a cycle, a predetermined number of times, to form a film on a substrate, the cycle including non-simultaneously performing: (a) supplying a source gas to the substrate in a process chamber; (b) removing the source gas from the process chamber; (c) supplying a reactive gas having a chemical structure different from that of the source gas to the substrate in the process chamber; and (d) removing the reactive gas from the process chamber, wherein the (d) includes alternately repeating: (d-1) exhausting an inside of the process chamber to depressurize the inside of the process chamber; and (d-2) purging the inside of the process chamber using an inert gas..
Hitachi Kokusai Electric Inc.


07/23/15
20150206603 

E-fuse structure of semiconductor device


Provided is an e-fuse structure of a semiconductor device having improved fusing performance so as to enable a program operation at a low voltage. The e-fuse structure includes a first metal pattern formed at a first vertical level, the first metal pattern including a first part extending in a first direction and a second part extending in the first direction and positioned to be adjacent to the first part, and a third part adjacent to the second part, the second part being positioned between the first part and the third part, the first part and the second part being electrically connected to each other, and the third part being electrically disconnected from the second part; and a second metal pattern electrically connected to the first metal pattern and formed at a second vertical level different from the first vertical level..

07/23/15
20150206588 

Semiconductor device


A semiconductor device has a smaller area. That is, in a row selection decoder including mos transistors, which selectively connect a plurality of selection signal lines to row selection lines of nand flash memories having an sgt structure, the mos transistors are formed on a planar silicon layer that is formed on a substrate, and each have a structure such that a drain, a gate, and a source are disposed in the vertical direction and the gate surrounds a silicon pillar.
Unisantis Electronics Singapore Pte. Ltd.


07/23/15
20150206571 

Semiconductor device


A semiconductor device including an operation initiation block suitable for sequentially generating a plurality of operation initiation signals at a predetermined time interval in response to an operation initiation source signal, a clock-based signal generation block suitable for generating an operation termination source signal in response to one of the multiple operation initiation signals and a clock, an operation termination block suitable for sequentially generating a plurality of operation termination signals at the predetermined time interval in response to the operation termination source signal, and an operation control block suitable for sequentially generating a plurality of first operation control signals in response to the multiple operation initiation signals and the multiple operation termination signals.. .
Sk Hynix Inc.




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