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Semiconductor Device patents

      

This page is updated frequently with new Semiconductor Device-related patent applications.




Date/App# patent app List of recent Semiconductor Device-related patents
08/18/16
20160242313 
 Electronic assembly with one or more heat sinks patent thumbnailnew patent Electronic assembly with one or more heat sinks
An electronic assembly comprises a semiconductor device that has conductive pads on a semiconductor first side and a metallic region on a semiconductor second side opposite the first side. A lead frame provides respective separate terminals that are electrically and mechanically connected to corresponding conductive pads.
Deere & Company


08/18/16
20160242312 
 Electronic assembly with one or more heat sinks patent thumbnailnew patent Electronic assembly with one or more heat sinks
An electronic assembly comprises a semiconductor device that has conductive pads on a semiconductor first side and a metallic region on a semiconductor second side opposite the first side. A lead frame provides respective separate terminals that are electrically and mechanically connected to corresponding conductive pads.
Deere & Company


08/18/16
20160242298 
 Partially depopulated interconnection arrays for packaged semiconductor devices and printed circuit boards patent thumbnailnew patent Partially depopulated interconnection arrays for packaged semiconductor devices and printed circuit boards
In one embodiment, a ball grid array (bga) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors.
Lattice Semiconductor Corporation


08/18/16
20160241294 
 Switched-mode power supply with switch resizing patent thumbnailnew patent Switched-mode power supply with switch resizing
Switched-mode power supply with switch resizing. A power converter can include an inductor coupled between an input node and an intermediate node, a semiconductor device coupled between the intermediate node and an output node, and a plurality of drive transistors.
Skyworks Solutions, Inc.


08/18/16
20160241255 
 Semiconductor device, electronic component, and electronic device patent thumbnailnew patent Semiconductor device, electronic component, and electronic device
A semiconductor device with a novel structure. An upper-bit grayscale voltage and a lower-bit grayscale voltage are separately produced, and then the grayscale voltages are converted into currents and the currents are synthesized.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160241218 
 Semiconductor device patent thumbnailnew patent Semiconductor device
In a semiconductor device, a charge pump operates in accordance with a clock signal and thereby generates a boosted voltage of a polarity which is the same as or reverse to the polarity of an input voltage. An oscillation circuit generates and outputs a clock signal.
Renesas Electronics Corporation


08/18/16
20160241136 
 Power unit and power conversion apparatus patent thumbnailnew patent Power unit and power conversion apparatus
To reduce radiation noise generated when a semiconductor device in a power unit performs switching, a core is provided outside the power unit. The closer the core is disposed to the semiconductor device that is generating the radiation noise, the greater the effect of reducing the radiation noise is obtained.
Mitsubishi Electric Corporation


08/18/16
20160241018 
 Semiconductor device and semiconductor module patent thumbnailnew patent Semiconductor device and semiconductor module
The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.. .
Rohm Co., Ltd.


08/18/16
20160240781 
 Organic semiconductor doping process patent thumbnailnew patent Organic semiconductor doping process
The present invention relates to the doping of organic semiconductors and processes for producing layers of p-doped organic semiconductors. Disclosed is a process for p-doping organic semiconductors comprising treating the organic semiconductor with an oxidised salt of the organic semiconductor.
Isis Innovation Limited


08/18/16
20160240774 
 Semiconductor device and  producing the same patent thumbnailnew patent Semiconductor device and producing the same
A memory device includes memory elements arranged in two or more rows and two or more columns. Each memory element includes a pillar-shaped insulator layer, a phase change film around an upper portion of the pillar-shaped insulator layer, a lower electrode formed around a lower portion of the pillar-shaped insulator layer and connected to the phase change film, a reset gate insulating film surrounding the phase change film, and a reset gate surrounding the reset gate insulating film.
Unisantis Electronics Singapore Pte. Ltd.


08/18/16
20160240734 
new patent

Optoelectronic semiconductor device


An optoelectronic semiconductor component includes a layer stack based on a nitride compound semiconductor and has an n-type semiconductor region , a p-type semiconductor region and an active layer arranged between the n-type semiconductor region and the p-type semiconductor region. In order to form an electron barrier, the p-type semiconductor region includes a layer sequence having a plurality of p-doped layers composed of alxinga1-x-yn where 0<=x<=1, 0<=y<=1 and x+y<=1.
Osram Opto Semiconductors Gmbh


08/18/16
20160240719 
new patent

Semiconductor devices comprising 2d-materials and methods of manufacture thereof


Semiconductor devices comprising two-dimensional (2d) materials and methods of manufacture thereof are described. In an embodiment, a method for manufacturing a semiconductor device comprising 2d materials may include: epitaxially forming a first 2d material layer on a substrate; and epitaxially forming a second 2d material layer over the first 2d material layer, the first 2d material layer and the second 2d material layer differing in composition..
National Taiwan University


08/18/16
20160240710 
new patent

Photodetection semiconductor device having light receiving element


In order to provide a photodetection semiconductor device including a light receiving element configured to reduce afterimages, a photodiode is formed by a pn junction into a circular shape so that a uniform distance from an end portion of a light receiving element to an electrode serving as a carrier outlet is realized, to thereby enable carriers to be uniformly taken out from all directions.. .
Sii Semiconductor Corporation


08/18/16
20160240694 
new patent

Oxide semiconductor film and semiconductor device


An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240693 
new patent

Semiconductor device and manufacturing method thereof


A transistor having a multi-layer structure of oxide semiconductor layers is provided in which a second oxide semiconductor layer having a crystalline structure including indium zinc oxide is formed over a first oxide semiconductor layer having an amorphous structure, and at least a third oxide semiconductor layer is formed stacked over the second oxide semiconductor layer. The second oxide semiconductor layer mainly serves as a carrier path for the transistor.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240690 
new patent

Semiconductor device


A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240685 
new patent

Semiconductor device and electronic device including the semiconductor device


In a semiconductor device including a transistor, an oxygen release type oxide insulating film is formed in contact with a channel formation region of the transistor. The channel formation region is formed in an oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240684 
new patent

Semiconductor device and manufacturing the same


A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including the transistor is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor that are in contact with the oxide semiconductor, a second insulator that is over the first and second conductors and has an opening reaching the oxide semiconductor, a third insulator over the oxide semiconductor and the second insulator, and a fourth conductor over the third insulator.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240683 
new patent

Semiconductor device and display device including the semiconductor device


To reduce parasitic capacitance in a semiconductor device having a transistor including an oxide semiconductor. The transistor includes a first gate electrode, a first gate insulating film over the first gate electrode, an oxide semiconductor film over the first gate insulating film, and source and drain electrodes electrically connected to the oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240682 
new patent

Oxide semiconductor film and semiconductor device


To provide a novel oxide semiconductor film. The oxide semiconductor film includes in, m, and zn.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240680 
new patent

Semiconductor device having a silicon and germanium material filling a cavity region comprising a notch region formed within a semiconductor substrate


The present invention is directed to semiconductor processes and devices. More specifically, embodiments of the present invention provide a semiconductor device that comprises a shaped cavity formed from two trench structures, and the shaped cavity is filled with silicon and germanium material.
Shanghai Huali Microelectronics Corporation


08/18/16
20160240676 
new patent

Reacted conductive gate electrodes and methods of making the same


A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240674 
new patent

Method for manufacturing semiconductor device with recess, epitaxial growth and diffusion


A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate..
Sony Corporation


08/18/16
20160240673 
new patent

Methods and doped sige source/drain stressor deposition


A method of manufacturing a semiconductor device includes etching a recess into a substrate and epitaxially growing a source/drain region in the recess. The source/drain region includes a first undoped layer of stressor material lining the recess, a lightly doped layer of stressor material over the first undoped layer, a second undoped layer of stressor material over the lightly doped layer, and a highly doped layer of stressor material over the second undoped layer..
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240672 
new patent

Semiconductor devices with shaped cavities for embedding germanium material and manufacturing processes thereof


The present invention is directed to semiconductor processes and devices. More specifically, embodiments of the present invention provide a shaped cavity that this later to be filled with sige material.
Shanghai Huali Microelectronics Corporation


08/18/16
20160240670 
new patent

Semiconductor device, related manufacturing method, and related electronic device


A semiconductor device may include the following elements: a first doped region; a second doped region, which contacts the first doped region; a third doped region, which contacts the first doped region; a first dielectric layer, which contacts the above-mentioned doped regions; a first gate member, which is conductive and comprises a first gate portion, a second gate portion, and a third gate portion, wherein the first gate portion contacts the first dielectric layer, wherein the second gate portion is positioned between the first gate portion and the third gate portion, and wherein a width of the second portion is unequal to a width of the third gate portion; a doped portion, which is positioned between the third gate portion and the third doped region; a second gate member; and a second dielectric layer, which is positioned between the third gate portion and the second gate member.. .
Semiconductor Manufacturing International (shanghai) Corporation


08/18/16
20160240668 
new patent

Ultra high voltage device


According to an embodiment, a semiconductor device is provided. The device includes: the second region has a greater curvature than the first region.
Taiwan Semiconductor Manufacturing Company Limited


08/18/16
20160240667 
new patent

Medium high voltage mosfet device


A semiconductor device includes a medium voltage mosfet having a vertical drain drift region between resurf trenches containing field plates which are electrically coupled to a source electrode of the mosfet. A split gate with a central opening is disposed above the drain drift region between the resurf trenches.
Texas Instruments Incorporated


08/18/16
20160240666 
new patent

Semiconductor device and manufacturing method thereof


A device includes a first and a second semiconductor-layer. The second semiconductor-layer is on the first semiconductor-layer, and has a first and a second side-surface.
Kabushiki Kaisha Toshiba


08/18/16
20160240664 
new patent

Semiconductor device


There is provided a semiconductor device having ldmos transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each ldmos transistor, the trench having a gate electrode partially embedded therein.
Renesas Electronics Corporation


08/18/16
20160240663 
new patent

Semiconductor device and fabricating the same


A semiconductor device includes: a semiconductor substrate; a semiconductor layer disposed over the semiconductor layer; a first well region disposed in the semiconductor layer and the semiconductor substrate; a second well region disposed in the semiconductor layer; a first isolation element disposed in the first well region; a second isolation element disposed in the second well region; a gate structure disposed in the semiconductor layer between the first isolation element and the second isolation element; a first doped region disposed in the first well region; and a second doped region disposed in the second well region. The bottom surface of the gate structure is above, below or substantially level with a bottom surface of the first isolation structure..
Vanguard International Semiconductor Corporation


08/18/16
20160240661 
new patent

Semiconductor device comprising a transistor array and a termination region and manufacturing such a semiconductor device


A semiconductor device formed in a semiconductor substrate having a first main surface comprises a transistor array and a termination region. The transistor array comprises a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region.

08/18/16
20160240659 
new patent

Laterally diffused metal oxide semiconductor device and manufacturing method therefor


An ldmos device, comprising a substrate (202), a gate electrode (211) on the substrate (202), a buried layer area in the substrate (202), and a diffusion layer on the buried layer area, wherein the buried layer area comprises a first buried layer (201) and a second buried layer (203), wherein the conduction types of impurities doped in the first buried layer (201) and the second buried layer (203) are opposite; the diffusion layer comprises a first diffusion area (205) and a second diffusion area (206), wherein the first diffusion area (205) is located on the first buried layer (201) and abuts against the first buried layer (201), and the second diffusion area (206) is located on the second buried layer (203) and abuts against the second buried layer (203); and the conduction types of impurities doped in the first buried layer (201) and the first diffusion area (205) are the same, and the conduction types of impurities doped in the second buried layer (203) and the second diffusion area (206) are the same. Additionally, also disclosed is a manufacturing method for the ldmos device.
Csmc Technologies Fab1 Co., Ltd.


08/18/16
20160240657 
new patent

Semiconductor device having buried layer


A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and formed in the substrate, a drift region formed in the high-voltage well, and a buried layer having the first conductivity type formed below the high-voltage well and vertically aligned with the drift region.. .
Macronix International Co., Ltd.


08/18/16
20160240656 
new patent

Silicon carbide semiconductor device and manufacturing the same


A silicon carbide semiconductor device includes a silicon carbide semiconductor layer having a main surface, the main surface of the silicon carbide semiconductor layer being provided with a trench having a closed shape when seen in plan view, the trench including a bottom, a plurality of sidewalls continuous with the bottom, and a sidewall-connecting corner portion at a connection portion between two adjacent sidewalls of the plurality of sidewalls, the silicon carbide semiconductor device further including a gate insulating film covering the bottom and the sidewalls of the trench, and a gate electrode provided on the gate insulating film, between the bottom and an upper end of the trench, the thickness of the gate insulating film at the sidewall-connecting corner portion of the trench being greater than the thickness of the gate insulating film at a portion other than the sidewall-connecting corner portion.. .
Sumitomo Electric Industries, Ltd.


08/18/16
20160240655 
new patent

Method for manufacturing silicon carbide semiconductor device


A method for manufacturing a sic semiconductor device includes the steps of: forming an impurity region in a sic layer; forming a first carbon layer on a surface of the sic layer having the impurity region formed therein, by selectively removing silicon from the surface; forming a second carbon layer on the first carbon layer; and heating the sic layer having the first carbon layer and the second carbon layer formed therein.. .
Sumitomo Electric Industries, Ltd.


08/18/16
20160240654 
new patent

Semiconductor device manufacturing method and semiconductor device


In order to improve the performance of a semiconductor device, a p type impurity is ion implanted into an area of an n type semiconductor film that is epitaxially grown over a p type semiconductor substrate, and the p type impurity is not ion implanted into an area of the n type semiconductor film, which is adjacent to the area in which the p type impurity is ion implanted. In this way, a p− type drift layer comprised of the area in which the p type impurity is introduced, as well as an n− type semiconductor region comprised of the area in which the p type impurity is not introduced are formed..
Renesas Electronics Corporation


08/18/16
20160240653 
new patent

Medium high voltage mosfet device


A semiconductor device includes a medium voltage mosfet having a vertical drain drift region between resurf trenches containing field plates which are electrically coupled to a source electrode of the mosfet. A split gate with a central opening is disposed above the drain drift region between the resurf trenches.
Texas Instruments Incorporated


08/18/16
20160240651 
new patent

Structure and formation finfet device


Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a fin structure over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


08/18/16
20160240648 
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes a first nitride semiconductor layer formed above a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer, a trench passing through the second nitride semiconductor layer and into the first nitride semiconductor layer, a gate insulation film formed in the trench, and a gate electrode disposed by way of the gate insulation film in an inside of the trench. The corner of the trench between a side wall of the trench and a bottom of the trench includes a rounded shape, and a corner of the gate insulation film in contact with the corner of the trench includes a rounded shape..
Renesas Electronics Corporation


08/18/16
20160240645 
new patent

Semiconductor device


In an embodiment, a semiconductor device includes a substrate, a group iii nitride-based semiconductor layer formed on the substrate, a first current electrode and a second current electrode formed on the group iii nitride-based semiconductor layer and spaced from each other, and a control electrode formed on the group iii nitride-based semiconductor layer between the first current electrode and the second current electrode. The control electrode includes at least a middle portion, configured to switch off a channel below the middle portion when a first voltage is applied to the control electrode, and second portions adjoining the middle portion.
Infineon Technologies Austria Ag


08/18/16
20160240644 
new patent

Semiconductor devices and a forming a semiconductor device


A semiconductor device includes a first transistor structure including a first transistor body region of a first conductivity type located within a semiconductor substrate. At least part of the first transistor body region is located between a first source/drain region of the first transistor structure and a second source/drain region of the first transistor structure.
Infineon Technologies Ag


08/18/16
20160240643 
new patent

Semiconductor device


A switching loss is prevented from being deteriorated by suppressing increase in a gate capacitance due to a cell shrink of an ie type trench gate igbt. A cell formation region is configured of a linear active cell region, a linear hole collector cell region, and a linear inactive cell region between them.
Renesas Electronics Corporation


08/18/16
20160240642 
new patent

Semiconductor devices and a forming a semiconductor device


Some embodiments relate to a method for forming a semiconductor device. The method includes forming a source region of a field effect transistor structure in a semiconductor substrate.
Infineon Technologies Ag


08/18/16
20160240641 
new patent

Semiconductor device and manufacturing the semiconductor device


A semiconductor device includes: a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode. In the semiconductor substrate, a body region, a pillar region, and a barrier region are formed.
Toyota Jidosha Kabushiki Kaisha


08/18/16
20160240640 
new patent

Power semiconductor device


A semiconductor substrate has a first surface and a second surface. A gate electrode has a part buried in a first trench.
Mitsubishi Electric Corporation


08/18/16
20160240639 
new patent

Semiconductor device


A semiconductor device includes: metal collector layer on backside, p-type collector layer, n-type field stop layer, n-drift layer and n-type cs layer within the n-drift layer near the top side. Multiple trench structures are formed by polysilicon core and gate oxide layer near the front side.
Changzhou Zhongmin Semi-tech Co. Ltd.


08/18/16
20160240638 
new patent

Semiconductor device


Provided is a semiconductor device including a plurality of trenches, including an emitter electrode; a floating layer of a first conduction type provided between adjacent trenches; and a low-dielectric-constant film provided between the floating layer and the emitter electrode, in which a dielectric constant of the low-dielectric-constant film is less than 3.9. Also provided is a semiconductor device further including a gate electrode formed in the trenches, in which capacitance between the gate electrode and the floating layer is greater than capacitance between the emitter electrode and the floating layer..
Fuji Electric Co., Ltd.


08/18/16
20160240637 
new patent

Semiconductor device and semiconductor module


In a semiconductor device, an element forming region formed with a semiconductor element for controlling a current is defined on a surface of a semiconductor substrate. A termination region is defined so as to surround the element forming region.
Mitsubishi Electric Corporation


08/18/16
20160240635 
new patent

Semiconductor device


A semiconductor device includes a first main electrode; a second main electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of the first conductivity type; a third semiconductor region of a second conductivity type arranged between the first semiconductor region and the second semiconductor region; and a depletion layer suppression region arranged inside of the third semiconductor region and being configured to suppress a spread of a depletion layer extending in the third semiconductor region when a reverse bias voltage is applied between the second semiconductor region and the third semiconductor region. The third semiconductor region includes a shortest region where a distance between a first boundary surface and a second boundary surface is shortest, and the shortest region includes a region where the depletion layer suppression region does not exist between the first boundary surface and the second boundary surface..
Toyota Jidosha Kabushiki Kaisha


08/18/16
20160240633 
new patent

Semiconductor device


A p-type well is formed in a semiconductor substrate, and an n+-type semiconductor region and a p+-type semiconductor region are formed in the p-type well to be spaced apart from each other. The n+-type semiconductor region is an emitter semiconductor region of a bipolar transistor, and the p-type well and the p+-type semiconductor region are base semiconductor regions of the bipolar transistor.
Renesas Electronics Corporation


08/18/16
20160240630 
new patent

Semiconductor devices and methods for fabricating the same


The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves.

08/18/16
20160240625 
new patent

Semiconductor device


The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer.
Renesas Electronics Corporation


08/18/16
20160240624 
new patent

Semiconductor devices and methods for manufacturing the same


Semiconductor devices and methods for manufacturing the same are provided. An example method may include: forming a sacrificial gate stack on a substrate; forming a gate spacer on sidewalls of the sacrificial gate stack; forming an interlayer dielectric layer on the substrate and planarizing it to expose the sacrificial gate stack; partially etching back the sacrificial gate stack to form an opening; expanding the resultant opening so that the opening is in a shape whose size gradually increases from a side adjacent to the substrate towards an opposite side away from the substrate; and removing a remaining portion of the sacrificial gate stack and forming a gate stack in a space defined by the gate spacer..
Institute Of Microelectronics, Chinese Academy Of Sciences


08/18/16
20160240621 
new patent

Insulating block in a semiconductor trench


A semiconductor device is produced by: creating an opening in a mask formed on a semiconductor body; creating, underneath the opening, a trench in the semiconductor body which has a side wall and a trench bottom; creating, while the mask is on the semiconductor body, an insulating layer covering the trench bottom and the side wall; depositing a spacer layer including a first electrode material on the insulating layer; removing the spacer layer from at least a portion of the insulating layer that covers the trench bottom; filling at least a portion of the trench with an insulating material; removing the part of the insulating material laterally confined by the spacer layer so as to leave an insulating block in the trench; and filling at least a portion of the trench with a second electrode material so as to form an electrode within the trench.. .
Infineon Technologies Austria Ag


08/18/16
20160240620 
new patent

Doped zinc oxide and n- doping to reduce junction leakage


A semiconductor device includes a substrate and a p-doped layer including a doped iii-v material on the substrate. An n-doped layer is formed on the p-doped layer, the n-doped layer including a doped iii-v material.
International Business Machines Corporation


08/18/16
20160240619 
new patent

Semiconductor device having buried gate structure and fabricating the same


A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer.
Samsung Electronics Co., Ltd.


08/18/16
20160240616 
new patent

Nmos and pmos strained devices without relaxed substrates


Techniques and methods related to strained nmos and pmos devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor.. .

08/18/16
20160240615 
new patent

Semiconductor device and a forming a semiconductor device


A semiconductor device comprises at least one strip-shaped cell compensation region of a vertical electrical element arrangement, at least one strip-shaped edge compensation region and a bridge structure. The at least one strip-shaped cell compensation regions extends into a semiconductor substrate and comprises a first conductivity type.
Infineon Technologies Austria Ag


08/18/16
20160240614 
new patent

Semiconductor device and semiconductor package


A semiconductor device according to an embodiment includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a first electrode, a gate electrode, a third insulating layer, a second electrode, a third electrode, and a fourth electrode. The third insulating layer is provided between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region.
Kabushiki Kaisha Toshiba


08/18/16
20160240613 
new patent

Iii-v semiconductor devices with selective oxidation


Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer..
International Business Machines Corporation


08/18/16
20160240612 
new patent

Non-planar semiconductor device having group iii-v material active region with multi-dielectric gate stack


Non-planar semiconductor devices having group iii-v material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate.

08/18/16
20160240610 
new patent

Junction interlayer dielectric for reducing leakage current in semiconductor devices


A semiconductor device includes a substrate and a p-doped layer including a doped iii-v material on the substrate. A dielectric interlayer is formed on the p-doped layer.
International Business Machines Corporation


08/18/16
20160240609 
new patent

Semiconductor device structure and forming the same


A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first trench between a first active region and a second active region of the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


08/18/16
20160240607 
new patent

Oxide material and semiconductor device


Stable electrical characteristics are given to a transistor and a highly reliable semiconductor device is provided. In addition, an oxide material which enables manufacture of such a semiconductor device is provided.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240586 
new patent

Memory device, semiconductor device, and methods for producing memory device and semiconductor device


A memory that includes a memory device having a phase change layer that can be reset by using a reset gate is provided. A memory device includes memory elements arranged in two or more rows and two or more columns.
Unisantis Electronics Singapore Pte. Ltd.


08/18/16
20160240578 
new patent

Cmos image sensor structure


A semiconductor device includes a substrate, a logic gate structure, a photosensitive gate structure, a hard mask layer, a first spacer, a first source, a first drain, a second spacer, a second source and a second drain. The logic gate structure and the photosensitive gate structure are disposed on a surface of the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/18/16
20160240576 
new patent

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device, comprising forming an insulating member on a structure having a height difference, and forming openings in the insulating member, the forming openings including first etching under a condition with a microloading phenomenon and second etching under a condition with a reverse microloading phenomenon, wherein the first etching is stopped before an upper face of the structure is exposed and then the second etching is started.. .
Canon Kabushiki Kaisha


08/18/16
20160240574 
new patent

Integrated circuit and image sensing device having metal shielding layer and related fabricating method


An integrated circuit includes a first semiconductor device, a second semiconductor device, and a metal shielding layer. The first semiconductor device includes a first substrate and a first multi-layer structure, and the first substrate supports the first multi-layer structure.
Taiwan Semiconductor Manufacturing Company Ltd.


08/18/16
20160240566 
new patent

Semiconductor device


A semiconductor device having a high aperture ratio and including a capacitor capable of increasing the charge capacity is provided. A semiconductor device includes a transistor over a substrate, a first light-transmitting conductive film over the substrate, an oxide insulating film covering the transistor and having an opening over the first light-transmitting conductive film, a nitride insulating film over the oxide insulating film and in contact with the first light-transmitting conductive film in the opening, a second light-transmitting conductive film connected to the transistor and having a depressed portion in the opening, and an organic resin film with which the depressed portion of the second light-transmitting conductive film is filled..
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240564 
new patent

Semiconductor device and semiconductor device manufacturing method


A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view..
Renesas Electronics Corporation


08/18/16
20160240563 
new patent

Semiconductor device and fabricating the same


Provided is a semiconductor device. The semiconductor device includes a second semiconductor pattern disposed on the substrate and configured to provide a channel region, and a first semiconductor pattern disposed between the substrate and the second semiconductor pattern, wherein the first semiconductor pattern includes a channel region that is a portion in contact with the second semiconductor pattern and source/drain regions that are portions exposed by the second semiconductor pattern..
Korea Advanced Institute Of Science And Technology


08/18/16
20160240562 
new patent

Semiconductor device and manufacturing the same


An object is to provide a display device with high productivity by reducing the number of masks and the number of steps. Another object is to provide a display device with high yield.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240555 
new patent

Three-dimensional (3d) semiconductor devices and methods of fabricating 3d semiconductor devices


A three-dimensional (3d) semiconductor device includes a stack of conductive layers spaced from each other in a vertical direction, the stack having a staircase-shaped section in a connection region, and ends of the conductive layers constituting treads of the staircase-shaped section, respectively. The 3d semiconductor device further includes buffer patterns disposed on and protruding above the respective ends of the conductive layers, an interconnection structure disposed above the stack and including conductive lines, and contact plugs extending vertically between the conductive lines and the buffer patterns and electrically connected to the conductive layers of the stack via the buffer patterns..
Samsung Electronics Co., Ltd.


08/18/16
20160240549 
new patent

Method for manufacturing semiconductor device


According to one embodiment, a method for manufacturing a semiconductor device includes forming a first film on a multilayer body including two or more stacked films. One stacked film includes a first layer and a second layer.
Kabushiki Kaisha Toshiba


08/18/16
20160240543 
new patent

Semiconductor device manufacturing method and semiconductor device


A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.. .
Fujitsu Semiconductor Limited


08/18/16
20160240540 
new patent

Semiconductor structure having a center dummy region


A semiconductor structure is provided, including a substrate, a plurality of first semiconductor devices, a plurality of second semiconductor devices, and a plurality of dummy slot contacts. The substrate has a device region, wherein the device region includes a first functional region and a second functional region, and a dummy region is disposed therebetween.
United Microelectronics Corp.


08/18/16
20160240538 
new patent

Semiconductor device having buried gate, fabricating the same, and module and system having the same


A semiconductor device includes junction regions formed in upper portions of both sidewalls of a trench formed in a semiconductor substrate, a first gate electrode buried in the trench and having a stepped upper surface, and a second gate electrode formed on the first gate electrode to overlap a junction region.. .
Sk Hynix Inc.


08/18/16
20160240537 
new patent

Semiconductor device including fin structures and manufacturing method thereof


A semiconductor device includes a fin fet transistor. The fin fet transistor includes a first fin structure extending in a first direction, a gate stack and a source and a drain.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/18/16
20160240536 
new patent

Structure and formation finfet device


Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack and a second gate stack over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


08/18/16
20160240532 
new patent

Gate-all-around semiconductor device and fabricating the same


The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between sti regions at least one suspended nanostructure anchored by a source region and a drain region.
Imec Vzw


08/18/16
20160240531 
new patent

Finfet device and manufacturing same


A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240530 
new patent

Finfet structure and forming same


A method of forming a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes fins formed thereon and a patterned hard mask layer formed on a top surface of the fins.
Semiconductor Manufacturing International (shanghai) Corporation


08/18/16
20160240525 
new patent

Semiconductor devices and arrangements for electrostatic discharge protection


A semiconductor device and device arrangement including a plurality of semiconductor regions of different conductivity types and a plurality of gates which form electrically conducting paths between the semiconductor regions. The semiconductor device and device arrangement may be configured to protect against electrostatic discharge..
Intel Ip Corporation


08/18/16
20160240523 
new patent

Method for manufacturing semiconductor device, sheet-shaped resin composition, and dicing tape-integrated sheet-shaped resin composition


Provided is a method for manufacturing a semiconductor device, which can manufacture a semiconductor device at a high yield ratio by suppressing dissolution of a sheet-shaped resin composition when cleaning a wafer after peeling a supporting member from the wafer. The present invention provides a method for manufacturing a semiconductor device, the method including: a step a of preparing a wafer; a step b of pasting together a second main surface of the wafer and a supporting member including a support and a temporary fixing layer formed on the support with the temporary fixing layer interposed between the second main surface and the supporting member; a step c of preparing a laminate including a dicing tape and an ultraviolet curable sheet-shaped resin composition laminated on the dicing tape; a step d of pasting together a first main surface of the wafer and the sheet-shaped resin composition; a step e of peeling the supporting member from the wafer after the step d; a step f of cleaning the second main surface of the wafer after the step e; and a step s of irradiating a peripheral part of the sheet-shaped resin composition with ultraviolet light to cure the peripheral part after the step d and before the step f, the peripheral part not overlapping with the wafer in a plan view..
Nitto Denko Corporation


08/18/16
20160240516 
new patent

Method of manufacturing semiconductor device array


Present disclosure provides a method for manufacturing a semiconductor device array, including (1) providing a temporary substrate; (2) forming a plurality of discrete semiconductor structures over the temporary substrate; and (3) removing a surface portion of the temporary substrate to expose a peripheral bottom surface of the discrete semiconductor structure. Present disclosure also provides a method for transferring discrete semiconductor device, including (1) detaching discrete semiconductor structures of a first type from a first temporary substrate supporting the discrete semiconductor structures of the first type by a transfer stamp; (2) carrying the discrete semiconductor structures over a target substrate by the transfer stamp; and (3) dismounting the discrete semiconductor structures of the first type from the transfer stamp to predetermined sites on the target substrate.
Globalwafers Co., Ltd.


08/18/16
20160240511 
new patent

Power package lid


The present disclosure relates to a ring-frame power package. In this regard, the ring-frame power package includes a thermal carrier and a ring structure.
Triquint Semiconductor, Inc.


08/18/16
20160240504 
new patent

Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device includes a first step of forming a first electrode on one main surface side of a semiconductor wafer; a second step of bonding a first film to another main surface side of the semiconductor wafer; a third step of bonding a second film to an outer peripheral portion of the semiconductor wafer by applying pressure to the second film on the semiconductor wafer using a plurality of cylindrical rollers, after the second step; and a fourth step of forming a plating layer on the first electrode on the one main surface side of the semiconductor wafer by a plating process, after the third step.. .
Fuji Electric Co., Ltd.


08/18/16
20160240500 
new patent

Packaged semiconductor devices


A packaged semiconductor device is provided, which includes a substrate comprising a contact pad; a passivation layer disposed on the substrate, where the passivation layer covers part of the contact pad; an under bump metallization (ubm) layer disposed on the substrate, where the ubm layer is coupled to the contact pad; a conductive bump disposed on the ubm layer, where the conductive bump comprises a column connecting the ubm layer and a cap disposed on top of the column; and a solder ball encapsulating the conductive bump. The cap includes a bottom area larger than a cross-sectional area of the column, and a bottom of the cap is distant from an upper surface of the passivation layer by a space..
Chipmos Technologies (bermuda) Ltd.


08/18/16
20160240499 
new patent

Semiconductor device and manufacturing the same


The semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad formed on an uppermost wiring layer of the plurality of wiring layers, a surface protection film which includes an opening on the pad and is made of an inorganic insulating film, a rewiring formed on the surface protection film; a pad electrode formed on the rewiring, and a wire connected to the pad electrode. The rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion which couples the pad electrode mounting portion and the connection portion, and the pad electrode mounting portion has a rectangular shape when seen in a plan view..

08/18/16
20160240493 
new patent

Semiconductor device packages and making the same


The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a semiconductor device, a plurality of electronic components, a first package body, a patterned conductive layer and a feeding element.
Advanced Semiconductor Engineering, Inc.


08/18/16
20160240490 
new patent

Method for fabricating semiconductor devices having reinforcing elements


The present disclosure provides a method for fabricating semiconductor devices having reinforcing elements. The method includes steps of providing a first wafer having a lower electrode layer and an insulation layer; forming a device layer; etching the device layer and the insulation layer to form recesses; etching the device layer to form separation trenches and upper electrodes; forming reinforcing elements; and depositing metal pads.
Asia Pacific Microsystems, Inc.


08/18/16
20160240488 
new patent

Semiconductor device with an isolation structure coupled to a cover of the semiconductor device


A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate.
Freescale Semiconductor, Inc.


08/18/16
20160240487 
new patent

Semiconductor device


Signal transmission characteristics of a semiconductor device are improved. A plurality of wirings of a wiring substrate on which a semiconductor chip is mounted include a first wiring and a second wiring that constitute a differential pair for use in transmitting a differential signal.
Renesas Electronics Corporation


08/18/16
20160240485 
new patent

Middle-of-line integration methods and semiconductor devices


An electronic device includes a middle-of-line (mol) stack. The electronic device includes a top local interconnect layer and a contact coupling the top local interconnect layer to a gate of a semiconductor device through a first dielectric layer.
Qualcomm Incorporated


08/18/16
20160240484 
new patent

Semiconductor device and manufacturing same


To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a cu film, an ni film, and a pd film which have been formed successively from the side of a semiconductor substrate.
Renesas Electronics Corporation


08/18/16
20160240476 
new patent

Self-aligned integrated line and via structure for a three-dimensional semiconductor device


At least one via level dielectric layer and at least one line level dielectric layer are sequentially formed over an array of device structures. Conductive line structures are formed within the at least one line level dielectric layer.
Sandisk Technologies Inc.


08/18/16
20160240475 
new patent

Semiconductor devices including sealing regions and decoupling capacitor regions


Semiconductor devices may include an internal circuit, a sealing region surrounding the internal circuit, and a decoupling capacitor region in the sealing region. The decoupling capacitor region may include decoupling capacitors.
Samsung Electronics Co., Ltd.


08/18/16
20160240473 
new patent

Wafer with improved plating current distribution


A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of die seals, each of the plurality of die seals being formed at a perimeter of one of the plurality of dies, and a plurality of electrically conductive links, each of the plurality of conductive links connecting one of the plurality of die seals with another one of the plurality of die seals.. .
Globalfoundries Inc.


08/18/16
20160240472 
new patent

Semiconductor device, layout design and manufacturing a semiconductor device


A semiconductor device includes a first interconnect structure. The first interconnect structure includes a first interconnect portion, a second interconnect portion and a third interconnect portion.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240456 
new patent

Semiconductor device


A semiconductor device (10) includes a metallic base plate (22) provided with an upper surface (22a) and a lower surface (22b), a plurality of insulating substrates (24) provided on the upper surface (22a), and a plurality of semiconductor elements (26) and (28) mounted side by side on the respective insulating substrates (24). Annular grooves (50) and (52) for storing insulating grease are provided on the lower surface (22b) of the base plate (22).
Mitsubishi Electric Corporation


08/18/16
20160240454 
new patent

Semiconductor structure having thermal backside core


A semiconductor structure includes a semiconductor substrate having a recess disposed beneath a semiconductor device. The semiconductor structure also includes a thermally conductive core disposed in the recess, and a package substrate including a heat sink.
Avago Technologies General Ip (singapore) Pte. Ltd.


08/18/16
20160240453 
new patent

Semiconductor device and manufacturing the same


The method of manufacturing a semiconductor device includes receiving a substrate. The substrate comprises at least one chip region and at least one scribe line next to the chip region, and each chip region comprises an active region.
Taiwan Semiconductor Manufacturing Company Ltd.


08/18/16
20160240452 
new patent

Semiconductor packages with sub-terminals and related methods


A semiconductor device package includes a substrate having first and second opposing surfaces. A first surface of a die couples to the second surface of the substrate, and a first surface of an electrically conductive sub-terminal electrically couples with an electrical contact of the die and physically couples to the second surface of the substrate.
Semiconductor Components Industries, Llc


08/18/16
20160240450 
new patent

Semiconductor device


A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces.
Rohm Co., Ltd.


08/18/16
20160240446 
new patent

Semiconductor manufacturing apparatus and manufacturing semiconductor device


According to one embodiment, a semiconductor manufacturing apparatus includes a manufacturing processor, a signal acquisition unit, a frequency characteristic acquisition unit, and an end-point acquisition unit. The signal acquisition unit acquires a first processing signal which shows a different behavior during processing of a stacked body and after the processing of the stacked body.
Kabushiki Kaisha Toshiba


08/18/16
20160240442 
new patent

Semiconductor device and forming the same


A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of the gate stack, forming a stress film over the substrate, performing a process to form a dislocation with a pinchoff point in the substrate, removing at least a portion of the dislocation to form a recess cavity with a tip in the substrate, and forming a source/drain feature in the recess cavity.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240439 
new patent

Semiconductor device and method


A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240433 
new patent

Ruthenium film forming method, film forming apparatus, and semiconductor device manufacturing method


A ruthenium film forming method includes a deposition process of introducing a mixed gas of a ruthenium carbonyl gas and a co gas into a processing vessel 1 by supplying the co gas as a carrier gas from a co gas container 43 configured to contain the co gas into a film forming source container 41 configured to contain ruthenium carbonyl in a solid state as a film forming source material, and forming ruthenium film by decomposing the ruthenium carbonyl on a wafer w; and a co gas introduction process of bringing the co gas into contact with a surface of the wafer w by introducing the co gas directly into the processing vessel 1 from the co gas container 43 after stopping the introducing of the mixed gas into the processing vessel 1. The deposition process and the co gas introduction process are repeated multiple times..
Tokyo Electron Limited


08/18/16
20160240430 
new patent

Method of fabricating semiconductor device


A method for fabricating a semiconductor device includes forming a hard mask (hm) layer over a material layer, forming a first trench in the hm layer, which extends along a first direction. The method also includes forming a first patterned resist layer over the hm layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240428 
new patent

Method of forming an interconnect structure having an air gap and structure thereof


A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240411 
new patent

Multi-processing manufacturing semiconductor device


A multi-processing apparatus includes an electron beam irradiation unit, a dry etching unit and a transfer unit. The transfer unit is connected to the electron beam irradiation unit and the dry etching unit, and is configured to transfer a wafer under a reduced-pressure atmosphere from the electron beam irradiation unit to the dry etching unit..
Kabushiki Kaisha Toshiba


08/18/16
20160240409 
new patent

Systems and methods for microwave-radiation annealing


Systems and methods are provided for annealing a semiconductor structure using microwave radiation. A semiconductor structure is provided.
Taiwan Semiconductor Manufacturing Company Limited


08/18/16
20160240394 
new patent

Semiconductor device manufacturing method


A method for producing a semiconductor device includes: a step a of preparing a chip with sheet-shaped resin composition in which a sheet-shaped resin composition is pasted onto a bump formation surface of a semiconductor chip, a step b of preparing a substrate for mounting on which an electrode is formed, a step c of pasting the chip with resin composition to the substrate for mounting so that the resin composition serves as a pasting surface with the bump formed on the semiconductor chip facing toward the electrode formed on the substrate for mounting, a step d of heating the resin composition to semi-cure the resin composition after the step c, and a step e of heating the resin composition at a higher temperature than that in the step d to cure the resin composition after the step d while bonding the bump and the electrode.. .
Nitto Denko Corporation


08/18/16
20160240387 
new patent

Method of fabricating semiconductor device


A method for fabricating a semiconductor device includes forming a first hard mask (hm) layer over a material layer, forming a patterned second hm layer over the first hm layer. The patterned second hm layer has first trench extending along a first direction.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240386 
new patent

Self-aligned multiple spacer patterning process


Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including pattering a mandrel layer disposed over a semiconductor device layer to form a mandrel, forming a first set of spacers on sidewalls of the mandrel using a first material, selectively removing the mandrel disposed between the first set of spacers.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240380 
new patent

Method of manufacturing silicon carbide semiconductor device


A method of manufacturing a silicon carbide semiconductor device includes a step of preparing a silicon carbide substrate having a first main surface and a second main surface located opposite to the first main surface, a step of forming a doped region in the silicon carbide substrate by doping the first main surface with an impurity, a step of forming a first protecting film on the first main surface, and a step of forming a second protecting film on the second main surface, the step of forming a first protecting film being performed after the step of forming a doped region, the method further including a step of activating the impurity included in the doped region by annealing with at least a portion of the first main surface covered with the first protecting film and at least a portion of the second main surface covered with the second protecting film.. .
Sumitomo Electric Industries, Ltd.


08/18/16
20160240374 
new patent

Method for forming insulating film and manufacturing semiconductor device


In a method for forming a fluorocarbon-based insulating film to be in contact with a metal, a microwave is irradiated to the metal to which moisture is adhered in a hydrogen-containing atmosphere. Then plasma cvd using a fluorocarbon-based gas is performed on the metal to which the microwave is irradiated to form the insulating film..
Tokyo Electron Limited


08/18/16
20160240368 
new patent

Method and composition for selectively removing metal hardmask and other residues from semiconductor device substrates comprising low-k dielectric material and copper


An aqueous removal composition having a ph in the range of from 2 to 14 and method for selectively removing an etching mask consisting essentially of tin, tan, tinxoy, tiw, w, or alloy of ti or w relative to low-k materials from a semiconductor substrate comprising said low-k materials having a tin, tan, tinxoy, tiw, w, or alloy of ti or w etching mask thereon wherein the removal composition comprises at least one oxidizing agent and a carboxylate compound.. .
Ekc Technology, Inc.


08/18/16
20160240366 
new patent

Processing of semiconductor devices


A method of thinning a wafer includes thinning the wafer using a grinding process. The wafer, after the grinding processing, has a first non-uniformity in thickness.
Infineon Technologies Ag


08/18/16
20160240243 
new patent

Semiconductor device


A semiconductor device capable of reconfiguration, including a plurality of logic units which are connected to each other by an address line or a data line, wherein each of the logic units includes: a plurality of address lines; a plurality of data lines; a clock signal line to receive a system clock signal; a first and a second memory cell units which operate synchronously with the clock signal; a first address decoder which decodes an address signal and outputs a decode signal to the first memory cell unit; a second address decoder which decodes an address signal and outputs a decode signal to the second memory cell unit; and an address transition detection unit which generates an internal clock signal and outputs the internal clock signal to the first memory cell unit, when a transition of the address signal input from the plurality of address lines is detected, wherein the first memory cell unit operates synchronously with the internal clock signal, and the second memory cell unit operates synchronously with the system clock signal.. .
Taiyo Yuden Co., Ltd.


08/18/16
20160240239 
new patent

Semiconductor device and electronic device


A semiconductor device capable of generating a signal (e.g., a potential signal or a current signal) suitable for usage environment or a purpose. The semiconductor device includes a first memory circuit, a first circuit, and a second memory circuit.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240233 
new patent

Memory, semiconductor device including the same, and testing the same


A memory includes a first memory cell, a second memory cell, a latch unit, and a switch unit. The latch unit has a true node and a complement node.
Taiwan Semiconductor Manufacturing Company Limited


08/18/16
20160240232 
new patent

Semiconductor device having high-voltage transistor


A semiconductor device includes a semiconductor device, comprising a memory cell array including a plurality of memory cells connected to a first bit line and a second bit line, respectively, a page buffer group, and bit line selection circuits including a plurality of selection circuit blocks to connect the first bit lines or the second bit lines to the page buffer group, wherein each of the selection circuit blocks includes a first contact region and a second contact region to which the first and second bit lines coupled, and same bit lines of the first and second bit lines are coupled to contact regions adjacent to one another of the first and second contact regions included in bit line selection circuits adjacent to one another of the bit line selection circuits.. .
Sk Hynix Inc.


08/18/16
20160240227 
new patent

Semiconductor device package with mirror mode


semiconductor device assemblies with semiconductor device packages configured to operate in mirror mode are disclosed herein. In one embodiment a semiconductor device assembly includes a first semiconductor device package attached to a front side of a support substrate, and a second semiconductor device package attached to a back side of the support substrate.
Micron Technology, Inc.






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