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 Semiconductor device patent thumbnailSemiconductor device
A semiconductor device according to an embodiment comprises a first terminal receiving a high-frequency signal as an input and a second terminal outputting the high-frequency signal. A first switching part is provided on a path of the high-frequency signal between the first terminal and the second terminal.
Kabushiki Kaisha Toshiba


 Semiconductor device patent thumbnailSemiconductor device
[problem] to provide an input receiver making it possible to obtain adequate gain with respect to a broad reference potential level. [solution] the present invention is provided with a differential circuit (110) and a current-supplying circuit (120).
Ps4 Luxco S.a.r.l.


 Driver for normally on iii-nitride transistors to get normally-off functionality patent thumbnailDriver for normally on iii-nitride transistors to get normally-off functionality
A semiconductor device includes a depletion mode gan fet and an integrated driver/cascode ic. The integrated driver/cascode ic includes an enhancement mode cascoded nmos transistor which is connected in series to a source node of the gan fet.
Texas Instruments Incorporated


 Semiconductor device patent thumbnailSemiconductor device
A semiconductor device includes a clock supplying unit that independently supplies clocks to a plurality of bus slaves and a plurality of bus masters. The number of waits in accordance with an operating frequency can be set for each bus slave such as a memory.

 Dead time control patent thumbnailDead time control
Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors.
Peregrine Semiconductor Corporation


 Level shifter patent thumbnailLevel shifter
Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors.
Peregrine Semiconductor Corporation


 Semiconductor device, power source unit, and electrical device patent thumbnailSemiconductor device, power source unit, and electrical device
A semiconductor device includes a first signal outputting portion; a second signal outputting portion; and a voltage outputting portion. The first signal outputting portion compares a first voltage output from a first power source and a second voltage output from a second power source, and to output a comparison result.
Lapis Semiconductor Co., Ltd.


 Optical semiconductor device and  manufacturing the same patent thumbnailOptical semiconductor device and manufacturing the same
A semiconductor light-emitting device according to one embodiment includes a substrate, a first light reflection structure provided in contact with the substrate, a buried layer surrounding the first light reflection structure, an optical semiconductor structure including an active layer, provided above the first light reflection structure, a second light reflection structure provided above the optical semiconductor structure, and a pair of electrodes which supply current to the optical semiconductor structure. The surface of the first light reflection structure and the surface of the buried layer are included in the same plane..
Kabushiki Kaisha Toshiba


 Semiconductor device patent thumbnailSemiconductor device
In a semiconductor device having a magnetic sensor configured to detect a direction of magnetism, stress applied by a magnetic flux concentrator that is a magnetic material is small. The magnetic sensor includes, in combination, hall elements arranged on a surface of a semiconductor substrate, and a magnetic flux concentrator formed of a magnetic material having the function of amplifying magnetism, the magnetic flux concentrator being arranged on the semiconductor substrate, for at least partly covering each of the hall elements.
Sii Semiconductor Corporation


 Semiconductor device patent thumbnailSemiconductor device
According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region. The first semiconductor region is provided between the first and second electrodes.
Kabushiki Kaisha Toshiba


Semiconductor device and manufacturing method thereof


A semiconductor device includes a sic substrate having first and second surfaces, p-type first sic areas on the first surface of the sic substrate, an n-type second sic area between the first sic areas and the second surface, a third sic area having an n-type dopant concentration higher than that of the second sic area, on the second surface of the sic substrate, a first electrode on the first surface and electrically connected to the first sic areas, and a second electrode on the second surface and electrically connected to the third sic area. Where the area between the first sic areas and the second surface is a first area, and the area between a portion between adjacent first sic areas and the second surface is set as a second area, a z1/2 level density of the first area is higher than that of the second area..
Kabushiki Kaisha Toshiba


Semiconductor device and manufacturing method thereof


An object is to achieve high electrical characteristics (a high on-state current value, an excellent s value, and the like) and a highly reliable semiconductor device. A high on-state current value is achieved, whereby a further reduction in channel width (w) is achieved.
Semiconductor Energy Laboratory Co., Ltd.


Semiconductor device


One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line.
Semiconductor Energy Laboratory Co., Ltd.


Semiconductor device and manufacturing method thereof


An object is to suppress conducting-mode failures of a transistor that uses an oxide semiconductor film and has a short channel length. A semiconductor device includes a gate electrode 304, a gate insulating film 306 formed over the gate electrode, an oxide semiconductor film 308 over the gate insulating film, and a source electrode 310a and a drain electrode 310b formed over the oxide semiconductor film.
Sharp Kabushiki Kaisha


Semiconductor device


A transistor with stable electrical characteristics. A semiconductor device that includes an oxide semiconductor, a first conductor, a first insulator, a second insulator, a third insulator, and a fourth insulator.
Semiconductor Energy Laboratory Co., Ltd.


Semiconductor device and manufacturing method thereof


A transistor with favorable electrical characteristics is provided. A minute transistor is provided.
Semiconductor Energy Laboratory Co., Ltd.


Semiconductor device, manufacturing the same, or display device including the same


To suppress a change in electrical characteristics and improve reliability in a transistor including an oxide semiconductor film. Provided is a semiconductor device including a transistor including a first gate electrode, a first insulating film over the first gate electrode, a first oxide semiconductor film over the first insulating film, a source electrode electrically connected to the first oxide semiconductor film, a drain electrode electrically connected to the first oxide semiconductor film, a second insulating film over the first oxide semiconductor film, a second oxide semiconductor film as a second gate electrode over the second insulating film, and a third insulating film over the second oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.


Semiconductor device and manufacturing the semiconductor device


A semiconductor device includes at least one first gate structure and at least one second gate structure on a semiconductor substrate. The at least one first gate structure has a flat upper surface extending in a first direction and a first width in a second direction perpendicular to the first direction.

Non-planar semiconductor device having hybrid geometry-based active region


Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-fet portion disposed above a fin-fet portion.
Intel Corporation


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Semiconductor device including active fin


A semiconductor device includes first through fourth active fins, which extend alongside one another in a first direction; and a field insulating film that covers lower portions of the first through fourth active fins, the first and second active fins protrude from the field insulating film at a first height, the third active fin protrudes from the field insulating film at a second height different from the first height, and an interval between the first and second active fins is different from an interval between the third and fourth active fins.. .

Semiconductor device structure with raised source/drain having cap element


Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a source/drain structure adjacent to the gate stack.
Taiwan Semiconductor Manufacturing Co., Ltd


Vertical fin field-effect semiconductor device


A vertical finfet semiconductor device and a method of forming the same are disclosed. In one aspect, the semiconductor device includes a current-blocking structure formed over a semiconductor structure and a semiconductor fin formed on the current-blocking structure.
Globalfoundries Inc.


Semiconductor device


To provide a high-withstand-voltage lateral semiconductor device in which on-resistance or drain current density is uniform at an end portion and a center portion of the device in a gate width direction. A lateral n-type mos transistor 11 formed on an soi substrate includes a trench isolation structure 10b filled with an insulating film at an end portion of the transistor.
Hitachi Automotive Systems, Ltd.


Methods of manufacturing trench semiconductor devices with edge termination structures


Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate.
Freescale Semiconductor, Inc.


Semiconductor device


A semiconductor device according to an embodiment includes a first active region and a second active region. The first active region includes a n-type first source region at a first surface of the sic substrate having the first surface and a second surface, a n-type first drain region, a first gate insulating film, a first gate electrode, a p-type second source region at the first surface and electrically connected to the first source region, a p-type second drain region, a second gate insulating film, and a second gate electrode electrically connected to the first gate electrode.
Kabushiki Kaisha Toshiba


Semiconductor device and manufacturing method thereof


A semiconductor device includes a substrate, a buffer layer and a device layer. The buffer layer is deposited on the substrate and comprises at least one gallium nitride (gan) epitaxy layer and at least one insertion layer deposited on the gan epitaxy layer, wherein the gan epitaxy layer adjacent to an interface between the gan epitaxy layer and the upper insertion layer is doped with a trapping electron element.
Hermes-epitek Corp.


Vertical-type semiconductor device


A buffer layer includes an n+-type first buffer region and an n+-type second buffer region. The first buffer region is provided at a first depth from a first main surface of a semiconductor layer and has an impurity concentration higher than an impurity concentration of a drift layer.
Toyota Jidosha Kabushiki Kaisha


Semiconductor device


According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a first electrode, a first insulating layer, and a second electrode. The first semiconductor region includes a first region and a second region.
Kabushiki Kaisha Toshiba


Method of using an ion implantation process to prevent a shorting issue of a semiconductor device


The present invention provides a manufacturing method of a semiconductor device, including providing a substrate, where a first dielectric layer is formed on the substrate, at least one gate is formed in the first dielectric layer, at least one hard mask is disposed on the top surface of the gate, and at least two spacers are disposed on two sides of the gate respectively. Next, a blanket implantation process is performed on the hard mask and the first dielectric layer, so as to form an ion rich region in the first dielectric layer, in the hard mask and in the spacer respectively.
United Microelectronics Corp.


Method of forming epitaxial buffer layer for finfet source and drain junction leakage reduction


A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion.
Renesas Electronics Corporation


Semiconductor device and fabricating method thereof


A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer.
Taiwan Semiconductor Manufacturing Co., Ltd.


Method for fabricating semiconductor device having fin structure that includes dummy fins


A method for fabricating semiconductor device is disclosed. First, a substrate, and a sacrificial mandrel is formed on the substrate, in which the sacrificial mandrel includes a first side and a second side with the indentation.
United Microelectronics Corp.


Semiconductor device and fabricating method thereof


A semiconductor device includes a substrate, a first and second source/drain regions, and a gate stack. The first and second source/drain regions are disposed on the substrate.
Taiwan Semiconductor Manufacturing Company Ltd.


Conductive cap for metal-gate transistor


A semiconductor device includes a gate region, a conductive cap, and an interconnect. The gate region (e.g., a metal-gate transistor) includes a metal gate region and a high dielectric constant (high-k) gate dielectric region.
Qualcomm Incorporated


Semiconductor devices and structures and methods of formation


A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate.
Micron Technology, Inc.


Method for manufacturing a semiconductor device having a schottky contact


A semiconductor device includes an n-doped monocrystalline semiconductor substrate having a substrate surface, an amorphous n-doped semiconductor surface layer at the substrate surface of the n-doped monocrystalline semiconductor substrate, and a schottky-junction forming material in contact with the amorphous n-doped semiconductor surface layer. The schottky-junction forming material forms at least one schottky contact with the amorphous n-doped semiconductor surface layer..
Infineon Technologies Austria Ag


Semiconductor device


A semiconductor device includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type adjacent to the first semiconductor region in a first direction. A third semiconductor region of the first conductivity type is disposed on the second semiconductor region and separated from the first semiconductor region in the first direction by the second semiconductor region.
Kabushiki Kaisha Toshiba


Semiconductor device and fabricating the same


An semiconductor device is provided. A fin is disposed on a substrate, extending in a lengthwise direction.
Samsung Electronics Co., Ltd.


Semiconductor device


A semiconductor device according to an embodiment includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes an element region and a termination region provided around the element region.
Kabushiki Kaisha Toshiba


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Semiconductor device, and manufacturing semiconductor device


A semiconductor device comprises: an n-type semiconductor substrate; a p-type anode region formed in the semiconductor substrate on its front surface side; an n-type field stop region formed in the semiconductor substrate on its rear surface side with protons as a donor; and an n-type cathode region formed in the semiconductor substrate to be closer to its rear surface than the field stop region is, wherein a concentration distribution of the donor in the field stop region in its depth direction has a first peak, and a second peak that is closer to the rear surface of the semiconductor substrate than the first peak is, and has a concentration lower than that of the first peak, and a carrier lifetime in at least a partial region between the anode region and the cathode region is longer than carrier lifetimes in the anode region.. .
Fuji Electric Co., Ltd.


Semiconductor device


According to one embodiment, a semiconductor device includes: a first semiconductor region; a second semiconductor region on the first semiconductor region; a third semiconductor region on the second semiconductor region; an fourth insulating film on the second semiconductor region and the third semiconductor region; a first electrode under the first semiconductor region; a second electrode on the fourth insulating film; a plurality of first contact regions extending in a first direction from the first electrode toward the second electrode in the fourth insulating film, and the plurality of first contact regions electrically connecting the third semiconductor region to the second electrode; a plurality of second contact regions extending in the first direction in the fourth insulating film, and one of the plurality of second contact regions between adjacent ones of the first contact regions; and a third electrode in the second semiconductor region via a first insulating film.. .
Kabushiki Kaisha Toshiba


Semiconductor device


A semiconductor device according to an embodiment includes a cell region, a gate connection region, and a cell end region between the cell region and the gate connection region. The cell region includes, an n-type first sic region, a p-type second sic region, a n-type third sic region, a p-type fourth sic region, a gate insulating film, a gate electrode, a first electrode contacting with the first and fourth sic regions, a second electrode.
Kabushiki Kaisha Toshiba


Semiconductor device and manufacturing the same


A semiconductor device according to an embodiment includes a first-conductivity-type sic substrate, a first-conductivity-type sic layer provided on the sic substrate, having a first surface, and having a lower first-conductivity-type impurity concentration than the sic substrate, first second-conductivity-type sic regions provided in the first surface of the sic layer, second second-conductivity-type sic regions provided in the first sic regions and having a higher second-conductivity-type impurity concentration than the first sic region, silicide layers provided on the second sic regions and having a second surface, a difference between a distance from the sic substrate to the second surface and a distance from the sic substrate to the first surface being equal to or less than 0.2 μm, a first electrode provided to contact with the sic layer and the silicide layers, and a second electrode provided to contact with the sic substrate.. .
Kabushiki Kaisha Toshiba


Semiconductor device


A semiconductor device includes an sic substrate including a first surface and a second surface, the sic substrate having a first sic region of a first conductivity type at the first surface, and a second sic region of a second conductivity type between the first sic region and the second surface, an insulating film on the first surface around an element region of the semiconductor device and in contact with the first sic region, a first electrode on the insulating film and comprising a contact electrically connected to the first sic region, and a second electrode in contact with the second surface. A first conductivity type impurity concentration of the first sic region that is directly under a center portion of the contact is greater than a first conductivity type impurity concentration of the first sic region that is directly under a peripheral portion of the contact..
Kabushiki Kaisha Toshiba


Semiconductor devices and methods of manufacture thereof


Semiconductor devices and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a semiconductor device may include: patterning a substrate to have a first region and a second region extending from the first region of the substrate; depositing an isolation layer over a surface of the first region of the substrate; and epitaxially forming source/drain regions over the isolation layer and adjacent to sidewalls of the second region of the substrate..
National Chiao Tung University


Semiconductor device


According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, an insulating section, and a semiconductor section. The second semiconductor region is provided on the first semiconductor region.
Kabushiki Kaisha Toshiba


Semiconductor device formed with nanowire


A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires..
United Microelectronics Corp.


Field effect transistors and methods of forming same


Semiconductor devices and methods of forming the same are provided. A template layer is formed on a substrate, the template layer having a recess therein.
Taiwan Semiconductor Manufacturing Company, Ltd.


Semiconductor device


According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a first insulating layer, and a first insulating region. The second semiconductor region is provided on the first semiconductor region.
Kabushiki Kaisha Toshiba


Semiconductor device and fabricating the same


A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, a spacer layer and a dummy gate structure. The fin shaped structure is disposed on a substrate, wherein the fin shaped structure has a trench.
United Microelectronics Corp.


High-voltage transistor device


A semiconductor device is provided including a substrate, a buried oxide layer formed over the substrate, a semiconductor layer formed over the buried oxide layer, and a transistor device including a gate electrode, a gate insulation layer and a channel region, wherein the gate insulation layer comprises a part of the buried oxide layer.. .
Globalfoundries Inc.


Semiconductor device


A semiconductor device according to an embodiment includes a first semiconductor layer of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a gate electrode, an insulating layer, and a first electrode. The first semiconductor layer includes first semiconductor regions.
Kabushiki Kaisha Toshiba


Semiconductor device


A semiconductor device includes: a semiconductor substrate; and a thin film resistor formed over an upper surface of the semiconductor substrate, the thin film resistor including first thin film resistor units and second thin film resistor units alternately connected in series, each of the first thin film resistor units having an elongated main portion and end portions that are connected to the elongated main portion, the end portions each forming a u-shape together with the elongated main portion in a plan view, and respectively overlapping with two of the second thin film resistor units that are adjacent to and connected to the first thin film resistor unit in series.. .
Fuji Electric Co., Ltd.


High thermal budget magnetic memory


Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes forming a storage unit of a magnetic memory cell.
Globalfoundries Singapore Pte. Ltd.


Semiconductor devices comprising magnetic memory cells


Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions.
Micron Technology, Inc.


Semiconductor device and manufacturing the same


A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.. .
Sony Corporation


Semiconductor device


Provided is a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) or a semiconductor device including a transistor with high reliability. In the channel width direction of a channel-etched transistor in which an oxide semiconductor film is between first and second gate electrodes, the first and second gate electrodes are connected to each other through an opening portion in first and second gate insulating films.
Semiconductor Energy Laboratory Co., Ltd.


Semiconductor device and electronic device


To provide a semiconductor device with excellent electrical characteristics or a semiconductor device with stable electrical characteristics. A semiconductor device includes a first transistor, a second transistor, a first insulator, a second insulator, a first wiring, and a first plug.
Semiconductor Energy Laboratory Co., Ltd.


Semiconductor device


A semiconductor device includes a first pillar-shaped semiconductor layer, a first selection gate insulating film, a first selection gate, a first gate insulating film, a first contact electrode, a first bit line connected to an upper portion of the first pillar-shaped semiconductor layer and an upper portion of the first contact electrode, a second pillar-shaped semiconductor layer, a layer including a first charge storage layer, a first control gate, a layer including a second charge storage layer and formed above the first control gate, a second control gate, a second gate insulating film, a second contact electrode having an upper portion connected to an upper portion of the second pillar-shaped semiconductor layer, and a first lower internal line that connects a lower portion of the first pillar-shaped semiconductor layer and a lower portion of the second pillar-shaped semiconductor layer.. .
Unisantis Electronics Singapore Pte. Ltd.


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Semiconductor device and manufacturing the same


The present invention discloses a semiconductor device and a method for manufacturing the same, and the semiconductor device includes: a first area in which a plurality of device elements are stacked, wherein adjacent ones of the plurality of device elements are spaced by an interlayer insulation layer, and each of the device elements includes a corresponding gate conductor; and a second area adjacent to the first area, wherein the interlayer insulation layer and the gate conductors extend from the first area to the second area, and there are electrically conductive vias in the second area through which the gate conductors and connected with wires, wherein there are also support posts in the second area to support the interlayer insulation layer and the gate conductors. The support posts provides a mechanical support for the floating layers in the process of manufacturing and also supports the gate conductors in the resulting device to thereby improve the yield ratio and reliability of the semiconductor device..

Semiconductor device including memory cell array and power supply region


A semiconductor device having an sram which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions..
Renesas Electronics Corporation


Semiconductor device and semiconductor memory device


According to one embodiment, a semiconductor device includes a first region having a first conductivity type in a semiconductor region; a second region having a second conductivity type in the semiconductor region; a gate electrode above a first part of the semiconductor region between the first region and the second region; a gate insulating layer between the first part and the gate electrode; a third region having the first conductivity type below the second region; and a fourth region across the second region and the third region and including a first impurity.. .
Kabushiki Kaisha Toshiba


Semiconductor devices having bit lines and fabricating the same


Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a bit line provided to cross an active region of a substrate, isolation patterns provided on the substrate to face each other in a direction parallel to the bit line, a storage node contact provided between the isolation patterns to be in contact with a source/drain region provided in an upper portion of the active region, and a spacer provided between the bit line and the storage node contact.
Samsung Electronics Co., Ltd.


Dual strained cladding layers for semiconductor devices


Techniques and methods related to dual strained cladding layers for semiconductor devices, and systems incorporating such semiconductor devices.. .

Semiconductor devices having fin active regions


Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region..

Semiconductor devices including shallow trench isolation (sti) liners


Semiconductor devices including sti liners are provided. The semiconductor devices may include a sti trench that defines an active region in a substrate, a sti liner that extends conformally along side walls and a bottom surface of the sti trench, a device isolation film that is on the sti liner and fills up at least a part of the sti trench, a first gate structure that is disposed on the active region, and a second gate structure that is spaced apart from the first gate structure.
Samsung Electronics Co., Ltd.


Semiconductor device


A semiconductor device is provided. The semiconductor device may include a field insulating film on a substrate, a first fin type pattern which is formed on the substrate and protrudes upward from an upper surface of the field insulating film, and a gate electrode which intersects with the first fin type pattern on the field insulating film.

Semiconductor device and manufacturing method thereof


A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin.
Taiwan Semiconductor Manufacturing Co., Ltd.


Transistors patterned with electrostatic discharge protection and methods of fabrication


High-voltage semiconductor devices with electrostatic discharge (esd) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first s/d contacts and a plurality of second s/d contacts associated with the common gate(s).
Globalfoundries Inc.


Semiconductor device and testing the semiconductor device


A semiconductor device and a method for testing the semiconductor device are provided. The semiconductor device includes a diode (protection element) and a semiconductor element having a withstand voltage that is higher than that of the diode provided on one and the same first-conductive-type semiconductor substrate, the diode having a second-conductive-type first semiconductor region selectively provided in a front surface layer of the semiconductor substrate.
Fuji Electric Co., Ltd.


Flexible light emitting semiconductor device with large area conduit


A flexible polymeric dielectric layer (12) having first and second major surfaces, the first major surface having a conductive layer (20) thereon, the dielectric layer having at least one conduit (10) extending from the second major surface to the first major surface, the conduit having at least one lateral dimension of at least about one centimeter and being at least partially filled with conductive material (18), the conductive layer including at least one conductive feature (21) substantially aligned with the conduit (10), the conductive feature (21) supporting a plurality of light emitting semiconductor devices (22).. .
3m Innovative Properties Company


Semiconductor device and manufacturing method thereof


A semiconductor device according to the present embodiment includes a semiconductor substrate, an insulating film and a conductive film. The insulating film is disposed on a first surface of the semiconductor substrate.
Kabushiki Kaisha Toshiba


Semiconductor device and manufacturing the same


A semiconductor device includes a wiring substrate, a first semiconductor chip provided on the wiring substrate, a supporting member provided on the wiring substrate in a region which does not overlap with the first semiconductor chip in a plan view when viewed from a direction perpendicular to the wiring substrate, a resin member provided on the first semiconductor chip, and a second semiconductor chip provided on the supporting member and the resin member. A method for manufacturing a semiconductor device includes providing a first semiconductor chip in a first region on a wiring substrate, providing a supporting member in a second region on the wiring substrate, providing a resin member in at least a portion on the first semiconductor chip, and providing a second semiconductor chip on the supporting member and the resin member..
Kabushiki Kaisha Toshiba


Edge structure for backgrinding asymmetrical bonded wafer


Semiconductor devices and methods of forming a semiconductor device are disclosed. The device includes a wafer with top and bottom surfaces.
Globalfoundries Singapore Pte. Ltd.


Semiconductor device and manufacturing method thereof


An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various electronic devices, and methods of making thereof, that comprise a permanently coupled carrier that enhances reliability of the electronic devices..
Amkor Technology, Inc.


Thermally enhanced package-on-package structure


A semiconductor package comprises a bottom package and a top package. The bottom package comprises at least one bottom-package semiconductor device.
Samsung Electronics Co., Ltd.


Semiconductor device and forming pop semiconductor device with rdl over top package


A pop semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate.
Stats Chippac, Ltd.


Semiconductor device and manufacturing method thereof


A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer.
Kabushiki Kaisha Toshiba


Packaging devices and methods of manufacture thereof


Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring.
Taiwan Semiconductor Manufacturing Company, Ltd.


Semiconductor device and manufacturing semiconductor device


According to one embodiment, a semiconductor device includes: a semiconductor substrate; and an insulating film provided above the semiconductor substrate. The insulating film includes: a plurality of first particles having a periodic structure; a plurality of second particles provided between the plurality of first particles and having an average particle outline size smaller than an average particle outline size of the plurality of first particles; and a filler provided between at least one of the plurality of first particles and the plurality of second particles..
Kabushiki Kaisha Toshiba


Wafer structure for electronic integrated circuit manufacturing


A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits.
Aeroflex Colorado Springs Inc.


Semiconductor package and semiconductor device including electromagnetic wave shield layer


A semiconductor package is provided with an electromagnetic wave shielding layer, and a conductive ground layer connected thereto. For example, in certain embodiments, the conductive ground layer is formed in a package substrate of the semiconductor package.
Samsung Electronics Co., Ltd.


Semiconductor device


A semiconductor device capable of achieving a reduction of noise is provided. For example, the semiconductor device includes a first region for forming a core circuit block crbk, a power-source voltage line lnvd1 disposed in the first region, a power-source voltage line lnvd2 disposed on the outside of the first region, and an on-chip capacitor cc.
Renesas Electronics Corporation


Semiconductor device and manufacturing same


A semiconductor device includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a second insulating film provided on the first insulating film and including a material different from a material of the first insulating film, a first interconnect extending in a first direction along a surface of the semiconductor layer on the second insulating film, a second interconnect disposed side by side with the first interconnect on the second insulating film, and a third insulating film covering the first interconnect and the second interconnect, the third insulating film including a first gap between the first interconnect and the second interconnect. An upper surface of the second insulating film directly below the first gap is located at a level equal to or below a lower end of the first interconnect and a lower end of the second interconnect..
Kabushiki Kaisha Toshiba


Semiconductor device


A semiconductor device includes a semiconductor chip, an electrically insulating element separated from the semiconductor chip by a space, and encapsulation material disposed in the space. The semiconductor chip includes a first face having a contact, and the electrically insulating element defines at least one through-hole.
Infineon Technologies Ag


Packaged semiconductor devices, methods of packaging semiconductor devices, and pop devices


Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (pop) devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming through-package vias (tpvs) over a carrier, and coupling a semiconductor device to the carrier.
Taiwan Semiconductor Manufacturing Company, Ltd.


Semiconductor device and wafer level package including such semiconductor device


An rdl structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.. .
Mediatek Inc.


Semiconductor device


According to one embodiment, a semiconductor device includes a substrate; a first interconnect portion provided on the substrate and including a plurality of interconnect layers separately stacked each other; a second interconnect portion provided separately from the first interconnect portion on the substrate and including the plurality of interconnect layers having a number of stacked layers same as a number of stacked layers of the first interconnect portion; a first pillar provided adjacent to the first interconnect portion and the second interconnect portion and extending in a stacking direction of the plurality of interconnect layers; and a plurality of conductive layers. The plurality of conductive layers is separately stacked each other, surrounding a side surface of the first pillar, and electrically connected to the first interconnect portion and the second interconnect portion..
Kabushiki Kaisha Toshiba


Mis (metal-insulator-semiconductor) contact structures for semiconductor devices


An mis contact structure comprises a layer of semiconductor material, a layer of insulating material having a contact opening formed therein, a layer of contact insulating material having substantially vertically oriented portions and a substantially horizontally oriented portion, the vertically oriented portions of the layer of contact insulating material contacting a portion, but not all, of the sidewalls of the contact opening and the horizontally oriented portion of the layer of contact insulating material contacting the semiconductor layer. A conductive material is positioned on the layer of contact insulating material within the contact opening, the conductive material layer having vertically oriented portions and a horizontally oriented portion and a conductive contact positioned in the contact opening that contacts the uppermost surfaces of the conductive material layer and the layer of contact insulating material..
International Business Machines Corporation


Semiconductor device with air gap and fabricating the same


A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.. .
Sk Hynix Inc.


Semiconductor device structure and forming the same


A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


Semiconductor device structure and forming the same


A semiconductor device structure is provided. The semiconductor device structure includes a substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


Semiconductor device and manufacturing same


An object of the invention is to provide a semiconductor device having less cracking or peeling and a method of manufacturing the same. A fuse portion of a semiconductor device has bit lines electrically coupled to a sram memory cell.
Renesas Electronics Corporation


Methods of forming wiring structures in a semiconductor device


Methods of forming wiring structures and methods of manufacturing semiconductor devices include forming a lower structure on a substrate, forming an interlayer insulating film including an opening on the lower structure, forming a liner film on an inner surface of the opening, treating a surface of the liner film by an ion bombardment, and forming a first conductive film on the liner film. The first conductive film is formed to be at least partially filled in the opening through a reflow process.

Semiconductor device


A semiconductor device which can achieve a reduction of emi noises is provided. For example, a first region which is used for forming a core circuit block crbk, a first power-source voltage line (lnvd1) in the first region, a first power-source voltage generating circuit (vreg), a first power source pad (pdvcl) outside the first region, a second power-source voltage line lnvd2 which connects the lnvd1 and the pdvcl, and an on-chip capacitor cc are provided.
Renesas Electronics Corporation


Semiconductor device


According to one embodiment, a semiconductor device includes lower layer wirings formed on a semiconductor chip, a protection film arranged on the lower layer wirings, an upper layer wiring arranged on the protection film and across a plurality of lower layer wirings, and connected to the lower layer wirings, wherein the upper layer wiring is larger than the lower layer wirings in terms of wiring line width and wiring line thickness, and a stress relaxing portion configured to reduce a stress at an in-corner portion of the upper layer wiring on the protection film, as compared with a case where the in-corner portion is set in 90°.. .
Kabushiki Kaisha Toshiba


Semiconductor device and manufacturing semiconductor device


According to one embodiment, a semiconductor device includes an insulating layer provided on a semiconductor substrate, an opening provided on the insulating layer, a spacer film provided in a side wall of the opening in a stepped shape, and configured to have an etching resistance lower than that of the insulating layer, and a conductive body provided in the opening to be configured to cover the spacer film.. .
Kabushiki Kaisha Toshiba


Semiconductor device


A semiconductor device includes a first memory block and a second memory block in a cell region and a first transistor and a second transistor, respectively corresponding to the first and second memory blocks, in a pass transistor region located below the cell region, wherein each of the first and second transistors includes: a first gate electrode coupled to the first memory block and a second gate electrode coupled to the second memory block.. .
Sk Hynix Inc.


Semiconductor device and forming an embedded sop fan-out package


A semiconductor device includes a bga package including first bumps. A first semiconductor die is mounted to the bga package between the first bumps.
Stats Chippac Pte. Ltd.


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Through electrode substrate and semiconductor device using through electrode substrate


A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.. .
Dai Nippon Printing Co., Ltd.


Wiring substrate and semiconductor device


The wiring substrate includes an insulation layer that includes a lower surface, an upper surface, and an intermediate surface located between the lower surface and the upper surface. A first wiring layer is formed on the lower surface of the insulation layer.
Shinko Electric Industries Co., Ltd.


Semiconductor device and a manufacturing the same and a mounting structure of a semiconductor device


The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion..
Renesas Semiconductor Package & Test Solutions Co., Ltd.


Semiconductor package for a lateral device and related methods


A semiconductor package. Implementations may include a lateral device that may include a lateral semiconductor device including one of interspersed and interdigitated source and drain regions and one or more gate regions, a single layer clip, and a leadframe.
Semiconductor Components Industries, Llc


Semiconductor device


A semiconductor device includes a mounting member that includes first and second regions. First peripheral portions are provided along at least a portion of an outer periphery of the first region.
Kabushiki Kaisha Toshiba


Semiconductor device and manufacturing semiconductor device


According to one embodiment, a semiconductor device includes a first conductor, a second conductor, and an envelope. The first conductor includes a first radiation surface.
Kabushiki Kaisha Toshiba


Semiconductor device


According to the present invention, a grease layer having a grease as a constituent material is provided in a filling region lying between a heat dissipation surface that is a bottom surface of a heat dissipation material of a semiconductor module and a surface of a cooler. Further, a seal material is formed on the surface of the cooler and covers the entire side surface region of the grease layer without any gap.
Mitsubishi Electric Corporation


Semiconductor device and forming stacked vias within interconnect structure for fo-wlcsp


A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier.
Stats Chippac Pte. Ltd.


Semiconductor device and forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package


A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die.
Stats Chippac Pte. Ltd.


Semiconductor device and method to minimize stress on stack via


A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die.
Stats Chippac Pte. Ltd.


Semiconductor device and forming build-up interconnect structures over carrier for testing at interim stages


A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good.
Stats Chippac Pte. Ltd.


Semiconductor devices and methods of fabricating semiconductor devices


Semiconductor devices are provided. A semiconductor device includes a substrate including first through fourth areas.
Samsung Electronics Co., Ltd.


Semiconductor device and forming the same


The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor.
United Microelectronics Corp.


Semiconductor device and manufacturing method thereof


A semiconductor device includes a substrate that includes a first region and a second region adjacent to the first region. The first region has a thickness that is smaller than a thickness of the second region, and a nitride semiconductor layer is provided on the first region of the substrate..
Kabushiki Kaisha Toshiba


Structure and formation damascene structure


A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first conductive feature over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


Semiconductor device and manufacturing the same


According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a graphene film on a catalytic layer, removing a part of the graphene film to form an exposed side surface of the graphene film, introducing dopant into the graphene film from the exposed side surface, and forming a graphene interconnect by patterning the graphene film into which the dopant is introduced.. .
Kabushiki Kaisha Toshiba


Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device is provided. The method comprises steps as follows.
United Microelectronics Corporation


Reliable contacts


semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate having a device component with a contact region.
Globalfoundries Singapore Pte. Ltd.


Method for producing semiconductor device


A semiconductor device is produced while keeping a short circuit margin between its interconnects. A method therefor includes a step in which when a multilayered resist is used to make an interconnect trench in an interlayer dielectric, a mixed gas including, as components thereof, at least cf4 gas, c3h2f4 gas and o2 gas is used to perform dry etching in order to form the multilayered resist..
Renesas Electronics Corporation


Manufacturing semiconductor device


In order to provide a semiconductor device with high reliability while manufacturing cost is being suppressed, dry etching for an insulating film is performed by using mixed gas containing at least cf4 gas and c3h2f4 gas as its components.. .
Renesas Electronics Corporation


Handle substrate for use in manufacture of semiconductor-on-insulator structure and manufacturing thereof


A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (box) of the final semiconductor-on-insulator structure.
Sunedison Semiconductor Limited (uen201334164h)


Method and transfer of semiconductor devices


An apparatus includes a first frame to hold a wafer tape having a first side and a second side. A plurality of semiconductor device dies are disposed on the first side of the wafer tape.
Rohinni, Inc.


Method of manufacturing semiconductor device and semiconductor manufacturing apparatus


A method of manufacturing a semiconductor device uses a semiconductor manufacturing apparatus including a turn table allowing placement of at least first and second semiconductor substrates and being capable of moving positions of the first and the second semiconductor substrates by turning, a first film forming chamber, and a second film forming chamber. The first and the second film forming chambers are provided with an opening capable of loading and unloading the first and the second semiconductor substrates by lifting and lowering the first and the second semiconductor substrates placed on the turn table.
Kabushiki Kaisha Toshiba


Method for transfer of semiconductor devices


A method of transferring semiconductor devices to a product substrate includes positioning a surface of the product substrate to face a first surface of a semiconductor wafer having the semiconductor devices thereon, and actuating a transfer mechanism to cause the transfer mechanism to engage a second surface of the semiconductor wafer. The second surface of the semiconductor wafer is opposite the first surface of the semiconductor wafer.
Rohinni, Inc.


Semiconductor device and manufacturing method thereof


An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices made thereby, that utilize a film assist mold process..
Amkor Technology, Inc.


Lead frame structure, manufacturing lead frame structure, and semiconductor device


A lead frame structure includes a lead frame having a first surface, a second surface opposed to, and facing away from, the first surface, and a first through-hole extending through the lead frame from the first surface to the second surface, and a heat sink having a third surface contacting the second surface, a fourth surface opposed to, and facing away from, the third surface, and a second through-hole extending through the heat sink from the third surface to the fourth surface, and overlying the location of the first through-hole. The material of one of the heat sink and the lead frame extends through a through opening of the other of the heat sink and the lead frame and extends over a portion of the surface of the other of the heat sink and the lead frame on the second or fourth surfaces..
Kabushiki Kaisha Toshiba


Semiconductor device and manufacturing method thereof


A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias..
Amkor Technology, Inc.


Semiconductor device, manufacturing the same and power converter


An object is to avoid an increase in contact resistance of an ohmic electrode by etching in a semiconductor device. There is provided a method of manufacturing a semiconductor device.
Toyoda Gosei Co., Ltd.


Method of manufacturing semiconductor device


In one embodiment, a method of manufacturing a semiconductor device includes forming a first silicon oxide film having a first carbon content above a substrate. The method further includes forming a second silicon oxide film having a second carbon content different from the first carbon content on the first silicon oxide film.
Kabushiki Kaisha Toshiba


Method of interfacial oxide layer formation in semiconductor device


A method of an interfacial oxide layer formation comprises a plurality of steps. The step (s1) is to remove a native oxide layer from a surface of a substrate; the step (s2) is to form an oxide layer on a surface of a substrate by piranha solution (spm); the step (s3) is to cleaning a surface of the oxide layer by standard clean 1 (sc1), and the step (s4) is to etch he oxide layer by a solution comprising diluted hydrogen fluoride (dhf) and ozonized pure water (dio3)..
United Microelectronics Corporation


Method for forming patterns with sharp jogs


The present disclosure provides a method for forming patterns in a semiconductor device. The method includes forming a main pattern on a substrate; forming a spacer on sidewalls of the main pattern; forming a cut pattern having an opening by a first lithography process; and performing a cut process to selectively remove portions of the spacer within the opening of the cut pattern while the main pattern remains unetched, thereby defining a circuit pattern by the main pattern and the spacer.
Taiwan Semiconductor Manufacturing Company, Ltd.


Silicide region of gate-all-around transistor


The disclosure relates to a semiconductor device and methods of forming same. A representative structure for a semiconductor device comprises a substrate; a nanowire structure protruding from the substrate having a channel region disposed between a source region and a drain region; a pair of silicide regions extending into opposite sides of the source region, wherein each of the pair of silicide regions comprise a vertical portion adjacent to the source region and a horizontal portion adjacent to the substrate; and a metal gate surrounding a portion the channel region..
Taiwan Semiconductor Manufacturing Company, Ltd.


Method of forming a semiconductor structure


A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided.
United Microelectronics Corp.


Semiconductor device and manufacturing process thereof


A semiconductor device is provided which includes a dielectric layer over a gate structure of the semiconductor device. The semiconductor device also includes a conductive interconnect configured to couple the gate structure with an i/o region over the conductive interconnect.
Taiwan Semiconductor Manufacturing Company Ltd.


Self-aligned patterning process


Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a plurality of spacers over a first hard mask layer to form a first mask pattern, and forming a first photoresist over the plurality of spacers.
Taiwan Semiconductor Manufacturing Company, Ltd.


Semiconductor device


The trimming range of a reference current is extended larger than that of the related art. A semiconductor device includes a reference current generating circuit that generates a reference current.
Renesas Electronics Corporation






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