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Semiconductor Device patents



      
           
This page is updated frequently with new Semiconductor Device-related patent applications. Subscribe to the Semiconductor Device RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Device RSS RSS


Semiconductor device

Thin film semiconductor device, organic light-emitting display device, and method of manufacturing the thin film…

Semiconductor device and method of confining conductive bump material during reflow with solder mask patch

Date/App# patent app List of recent Semiconductor Device-related patents
08/14/14
20140227888
 Remote plasma radical treatment of silicon oxide patent thumbnailnew patent Remote plasma radical treatment of silicon oxide
Embodiments described herein generally relate to methods for manufacturing flash memory devices. In one embodiment, the method includes generating a plasma comprising nitrogen-containing radicals in a remote plasma applicator, flowing the plasma comprising nitrogen-containing radicals into a processing region of the processing chamber where a semiconductor device is disposed, wherein the semiconductor device has a substrate comprising an oxide layer formed thereon, exposing an exposed surface of the oxide layer to the nitrogen-containing radicals, and incorporating nitrogen in the exposed surface of the oxide layer of the substrate..
08/14/14
20140227886
 Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium patent thumbnailnew patent Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
A method of manufacturing a semiconductor device is disclosed. The method includes forming a thin film containing a predetermined element, boron, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times.
08/14/14
20140227876
 Semiconductor device manufacturing method patent thumbnailnew patent Semiconductor device manufacturing method
In a semiconductor device manufacturing method having a plasma etching process, a substrate is plasma etched using a resist layer as a mask. The plasma etching process has: a first etching step wherein a mixed gas having a deposition gas and an etching gas mixed at a ratio is introduced into the processing chamber, and the substrate is plasma etched in the mixed gas atmosphere; and a step of repeating multiple times a deposition step, wherein the deposition gas is introduced into the processing chamber, and the plasma-etched substrate is subjected to deposition treatment in an atmosphere having the deposition gas as a main component, and a second etching step, wherein the etching gas is introduced into the processing chamber, and the substrate that has been subjected to the deposition treatment in the deposition step is plasma etched in an atmosphere having the etching gas as a main component..
08/14/14
20140227873
 Semiconductor device and process for producing the same patent thumbnailnew patent Semiconductor device and process for producing the same
A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer..
08/14/14
20140227870
 Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via patent thumbnailnew patent Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via
A method for fabricating through-silicon vias (tsvs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill tsvs with plated-conductive material (e.g., copper) from an electroplating solution.
08/14/14
20140227869
 Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions patent thumbnailnew patent Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions
One method disclosed includes forming a sidewall spacer proximate a gate structure, forming a sacrificial layer of material above a protective cap layer, the sidewall spacer and a substrate, forming a sacrificial protection layer above the sacrificial layer, reducing a thickness of the sacrificial protection layer such that its upper surface is positioned at a level that is below the upper surface of the protective cap layer, performing a first etching process to remove a portion of the sacrificial layer and thereby expose the protective cap layer for further processing, performing a wet acid etching process that includes diluted hf acid in the etch chemistry to remove the protective cap layer and performing at least one process operation to remove at least one of the reduced-thickness sacrificial protection layer or the sacrificial layer from above the surface of the substrate.. .
08/14/14
20140227868
 Semiconductor device and method for fabricating the same patent thumbnailnew patent Semiconductor device and method for fabricating the same
A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.. .
08/14/14
20140227867
 Self-aligned insulating etchstop layer on a metal contact patent thumbnailnew patent Self-aligned insulating etchstop layer on a metal contact
A semiconductor device comprising a substrate having a transistor that includes a metal gate structure; a first oxide layer formed over the substrate; a silane layer formed on the first oxide layer; and a non-conductive metal oxide layer grown on the metal gate structure, wherein the silane layer inhibits nucleation and growth of the non-conductive metal oxide layer.. .
08/14/14
20140227863
 Methods of forming a metal telluride material, related methods of forming a semiconductor device structure, and related semiconductor device structures patent thumbnailnew patent Methods of forming a metal telluride material, related methods of forming a semiconductor device structure, and related semiconductor device structures
Accordingly, a method of forming a metal chalcogenide material may comprise introducing at least one metal precursor and at least one chalcogen precursor into a chamber comprising a substrate, the at least one metal precursor comprising an amine or imine compound of an alkali metal, an alkaline earth metal, a transition metal, a post-transition metal, or a metalloid, and the at least one chalcogen precursor comprising a hydride, alkyl, or aryl compound of sulfur, selenium, or tellurium. The at least one metal precursor and the at least one chalcogen precursor may be reacted to form a metal chalcogenide material over the substrate.
08/14/14
20140227858
 Shallow trench isolation integration methods and devices formed thereby patent thumbnailnew patent Shallow trench isolation integration methods and devices formed thereby
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a tsv device having a “buffer zone” or gap layer between the tsv and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices.
08/14/14
20140227857
new patent Methods of fabricating semiconductor devices including fin-shaped active regions
A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.. .
08/14/14
20140227856
new patent Methods of fabricating semiconductor device having shallow trench isolation (sti)
Methods of fabricating a semiconductor device include forming a field trench in a silicon substrate, forming a first oxide layer in the field trench, forming a first thinned oxide layer by partially removing a surface of the first oxide layer, and forming a first nitride layer on the first thinned oxide layer.. .
08/14/14
20140227855
new patent Semiconductor device having gate trench and manufacturing method thereof
Disclosed herein is a semiconductor device that includes a trench formed across active regions and the element isolation regions. A conductive film is formed at a lower portion of the trench, and a cap insulating film is formed at an upper portion of the trench.
08/14/14
20140227854
new patent Semiconductor device and fabricating method of the same
Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 μm.. .
08/14/14
20140227851
new patent Semiconductor device and method for manufacturing the same
A semiconductor device and a method for manufacturing the same are disclosed. An additional spacer is formed at a lateral surface of an upper part of the bit line so that the distance of insulation films between a storage node and a neighboring storage node contact plug is increased.
08/14/14
20140227848
new patent Semiconductor device and method of fabricationg the same
A method of fabricating a semiconductor device includes forming first gate patterns on a semiconductor substrate using an etch mask pattern, forming a trench in the semiconductor substrate between the first gate patterns, forming an insulating layer in the trench, such that the insulating layer fills the trench and is disposed on the etch mask pattern, planarizing the insulating layer until a top surface of the etch mask pattern is exposed, etching a portion of the planarized insulating layer to form a device isolation layer in the trench, forming a second gate layer covering the etch mask pattern and disposed on the device isolation pattern, and planarizing the second gate layer until the top surface of the etch mask pattern is exposed, such that a second gate pattern is formed.. .
08/14/14
20140227847
new patent Method for fabricating a semiconductor device
A method for fabricating a semiconductor device includes forming a pre-isolation layer covering a fin formed on a substrate, the pre-isolation layer including a lower pre-isolation layer making contact with the fin and an upper pre-isolation layer not making contact with the fin, removing a portion of the upper pre-isolation layer by performing a first polishing process, and planarizing the pre-isolation layer such that an upper surface of the fin and an upper surface of the pre-isolation layer are coplanar by performing a second polishing process for removing the remaining portion of the upper pre-isolation layer.. .
08/14/14
20140227845
new patent Methods of forming multiple n-type semiconductor devices with different threshold voltages on a semiconductor substrate
One illustrative method disclosed herein involves forming an integrated circuit product comprised of first and second n-type transistors formed in and above first and second active regions, respectively. The method generally involves performing a common threshold voltage adjusting ion implantation process on the first and second active regions, forming the first and second transistors, performing an amorphization ion implantation process to selectively form regions of amorphous material in the first active region but not in the second active region, after performing the amorphization ion implantation process, forming a capping material layer above the first and second transistors and performing a re-crystallization anneal process to convert at least portions of the regions of amorphous material to a crystalline material.
08/14/14
20140227843
new patent Method of manufacturing a semiconductor device
A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of misfet are formed in the peripheral circuit region.
08/14/14
20140227839
new patent Method of manufacturing semiconductor device
Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a misfet is formed.
08/14/14
20140227838
new patent Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device which includes forming first and second gate patterns, forming first and second sidewall spacers on sidewalls of the first and second gate patterns respectively, implanting a first impurity into the semiconductor substrate, forming a third sidewall spacer on the first sidewall spacer and a fourth sidewall spacer on the second sidewall spacer in such a manner that the third sidewall spacer is in contact with the fourth sidewall spacer between the first and second gate patterns, implanting a second impurity into the semiconductor substrate, and removing the third and the fourth sidewall spacers.. .
08/14/14
20140227836
new patent Nitride based semiconductor device and method for manufacturing the same
Disclosed herein is a nitride based semiconductor device including: a base substrate; an epitaxial growth layer disposed on the base substrate and generating a 2-dimensional electron gas in an inner portion thereof; and an electrode structure disposed on the epitaxial growth layer, wherein the electrode structure includes: a gate electrode; a source electrode disposed at one side of the gate electrode; and a drain electrode disposed at the other side of the gate electrode and having an extension part extended to the inner portion of the epitaxial growth layer to contact the 2-dimensional electron gas.. .
08/14/14
20140227832
new patent Semiconductor packages and methods of packaging semiconductor devices
A device is disclosed. The device includes a carrier substrate having first and second major surfaces.
08/14/14
20140227807
new patent Semiconductor manufacturing apparatus and manufacturing method of semiconductor device
A semiconductor manufacturing apparatus according to the present embodiment includes a vacuum chamber. A stage mounts a semiconductor substrate thereon within the vacuum chamber.
08/14/14
20140227804
new patent System and process to remove film from semiconductor devices
Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming a magnetic tunnel junction (mtj) device, and a process tool. An embodiment is a process tool comprising an ion beam etch (ibe) chamber, an encapsulation chamber, a transfer module interconnecting the ibe chamber and the encapsulation chamber, the transfer module being capable of transferring a workpiece from the ibe chamber to the encapsulation chamber without exposing the workpiece to an external environment..
08/14/14
20140227802
new patent Process to remove film from semiconductor devices
Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming an mram device, and a method of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a second layer over a first layer, and performing a first etch process on the second layer to define a feature, wherein the first etch process forms a film on a surface of the feature.
08/14/14
20140226781
new patent Semiconductor device
A register for a scan test has a data saving function. A scan flipflop includes first to third memory circuits.
08/14/14
20140226428
new patent Semiconductor device, information processing system including same, and controller for controlling semiconductor device
A system includes a control chip includes a plurality of command terminals receiving a plurality of command signals, respectively; a command decoder coupled to the command terminals, the command decoder being configured to output an internal command in response to the command signals; and a layer address buffer configured to output a layer address each time the command decoder outputs a row command as the internal command and outputs a column command as the internal command; and a plurality of core chips stacked with one another, each of the core chips being configured to receive the, row command and the layer address output together with the row command, to receive the column command and the layer address output together with the column command.. .
08/14/14
20140226401
new patent Memory device and semiconductor device
A memory device in which data can be retained for a long time is provided. The memory device includes a memory element and a transistor which functions as a switching element for controlling supply, storage, and release of electrical charge in the memory element.
08/14/14
20140226400
new patent Semiconductor device
According to one embodiment, a semiconductor device includes a nonvolatile memory, a volatile memory, and a controller. The controller is configured to transition a part of the volatile memory to a self-refresh mode when a request for stopping supplying of power to the nonvolatile memory is received..
08/14/14
20140226394
new patent Integrated circuit, method for driving the same, and semiconductor device
An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided.
08/14/14
20140226244
new patent Voltage surge protection device and high voltage circuit breakers
A voltage surge protection device for protection of a high voltage device includes a varistor having a first part and a second part separated by varistor material. The voltage surge protection device further includes an expandable member arranged to act on a movable electrical contact for short-circuiting the voltage surge protection device upon a threshold voltage being applied between the first part and the second part of the varistor.
08/14/14
20140226137
new patent Pattern forming method and manufacturing method of semiconductor device
A pattern forming method includes forming a spin on dielectric film on a substrate, washing the spin on dielectric film by using a washing liquid, drying a surface of the spin on dielectric film after the washing, forming a photosensitive film on the dried coating type insulation film, emitting energy rays to a predetermined position of the photosensitive film in order to form a latent image on the photosensitive film, developing the photosensitive film in order to form a photosensitive film pattern which corresponds to the latent image, and processing the spin on dielectric film with the photosensitive film pattern serving as a mask.. .
08/14/14
20140225661
new patent Semiconductor device with bypass functionality and method thereof
A device includes a semiconductor chip and a bypass layer electrically coupled to a contact region of the semiconductor chip. The bypass layer is configured to change from behaving as an insulator to behaving as a conductor in response to a condition of the semiconductor chip..
08/14/14
20140225647
new patent Semiconductor device and a display device
A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side, and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small.. .
08/14/14
20140225644
new patent Programmable logic device and semiconductor device
To provide a pld having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element.
08/14/14
20140225641
new patent Programmable logic device and semiconductor device
A programmable logic device includes a plurality of programmable logic elements (ple) whose electrical connection is controlled by first configuration data. Each of the ples includes an lut in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an ff to which the output signal of the lut is input, and an mux.
08/14/14
20140225640
new patent Semiconductor device and method of adjusting characteristic thereof
To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a drzqp signal supplied from a counter.
08/14/14
20140225477
new patent Receiving circuit, semiconductor device, and sensor device
A receiving circuit (10) includes an amplifier (15) which amplifies receiving signals (sp, sn) of a piezoelectric sensor (2), and a plurality of transistors (11a, 11b) or (12a, 12b), which are connected in parallel to between one end of the piezoelectric sensor (2) and one end of the amplifier (15), and are turned on with phase shift when switching is performed to receiving operations.. .
08/14/14
20140225282
new patent System in package (sip) with dual laminate interposers
There is provided a semiconductor device assembly with an interposer and method of manufacturing the same. More specifically, in one embodiment, there is provided a semiconductor device assembly comprising a semiconductor substrate, at least one semiconductor die attached to the semiconductor substrate, an interposer disposed on the semiconductor die, and a controller attached to the interposer.
08/14/14
20140225280
new patent Semiconductor device having stacked memory elements and method of stacking memory elements on a semiconductor device
A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the die opposite the substrate and a second memory device such that the second memory device at least partially overlaps the first memory device. Also disclosed is method of mounting first and second memory devices on a die in an at least partially overlapping manner..
08/14/14
20140225279
new patent Semiconductor device and method of forming insulating layer in notches around conductive tsv for stress relief
A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer.
08/14/14
20140225266
new patent Semiconductor device and manufacturing method for same
The present invention is directed to a semiconductor device including a semiconductor substrate, a through hole penetrating the semiconductor substrate, a base film covering the through hole, a conductive layer disposed on the base film, an insulating film formed on the side wall of the through hole, and a conductive material embedded in the through hole via the insulating film, in which the base film has a stepped portion formed by an opening pattern that selectively exposes the conductive layer therethrough into the through hole, and in which the conductive material is connected electrically to the conductive layer through the opening pattern.. .
08/14/14
20140225263
new patent Semiconductor device and method for manufacturing semiconductor device
During the production of a semiconductor device having a cu wiring line of a damascene structure, diffusion of fluorine from a cf film that serves as an interlayer insulating film is prevented in cases where a heat treatment is carried out, thereby suppressing increase in the leakage current. A semiconductor device of the present invention having a damascene wiring structure is provided with: an interlayer insulating film (2) that is formed of, for example, a fluorine-added carbon film; and a copper wiring line (4) that is embedded in the interlayer insulating film.
08/14/14
20140225258
new patent 3d packages and methods for forming the same
Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure.
08/14/14
20140225257
new patent Semiconductor device and method of confining conductive bump material during reflow with solder mask patch
A semiconductor device has a semiconductor die with die bump pads and substrate with trace lines having integrated bump pads. A solder mask patch is formed interstitially between the die bump pads or integrated bump pads.
08/14/14
20140225256
new patent Semiconductor device with conductive pillars having recesses or protrusions to detect interconnect continuity between semiconductor die and substrate
A semiconductor device has a semiconductor die and conductive pillar with a recess or protrusion formed over a surface of the semiconductor die. The conductive pillar is made by forming a patterning layer over the semiconductor die, forming an opening with a recess or protrusion in the patterning layer, depositing conductive material in the opening and recess or protrusion, and removing the patterning layer.
08/14/14
20140225251
new patent Semiconductor devices and methods of fabricating the same
Semiconductor devices, and methods of fabricating the same, include first conductive lines on a substrate, and a first molding layer covering the first conductive lines. The first conductive lines have air gaps between adjacent first conductive lines.
08/14/14
20140225249
new patent Semiconductor device and method for manufacturing semiconductor device
A semiconductor device according to the present invention has a semiconductor module 2; a cooling unit 3, the semiconductor module 2 being joined to an upper surface of the cooling unit 3, and a pipe 14, 15 for circulating a refrigerant being fixed to a side surface 20, 22 of the cooling unit 3; and a resin mold layer 4 that covers outer peripheries of the semiconductor module 2 and the cooling unit 3 . Further, a protruding portion 25, 26 that protrudes from the side surface 20, 22 of the cooling unit 3 and surrounds the pipe 14, 15 is provided on the side surface 20, 22 of the cooling unit 3..
08/14/14
20140225245
new patent Power semiconductor module and power semiconductor module assembly with multiple power semiconductor modules
A power semiconductor module and a power semiconductor module assembly, which includes a plurality of power semiconductor modules, are disclosed. The power semiconductor module includes an electrically conducting base plate, an electrically conducting top plate, arranged in parallel to the base plate and spaced apart from the base plate, at least one power semiconductor device, which is arranged on the base plate in a space formed between the base plate and the top plate, and at least one presspin, which is arranged in the space formed between the base plate and the top plate to provide contact between the semiconductor device and the top plate.
08/14/14
20140225243
new patent Semiconductor device
A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof..
08/14/14
20140225242
new patent Semiconductor packages and methods of packaging semiconductor devices
A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias.
08/14/14
20140225240
new patent Manufacturing method of semiconductor device, and semiconductor device
To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space.
08/14/14
20140225239
new patent Resin-encapsulated semiconductor device and method of manufacturing the same
A resin-encapsulated semiconductor device includes a semiconductor element mounted on a die pad portion, a plurality of lead portions arranged so that leading end portions thereof are opposed to the die pad portion, and thin metal wires for connecting together electrodes of the semiconductor element and the lead portions. Those members are partially encapsulated by a resin.
08/14/14
20140225238
new patent Semiconductor device
A semiconductor device includes a metal substrate, semiconductor elements, wires, a control terminal, a main electrode terminal, a control substrate, a cover, a sealing resin, a case, and an insulator. The metal substrate includes a metal plate, an insulating layer formed on the top surface of the metal plate, and electrode patterns provided on the insulating layer.
08/14/14
20140225236
new patent Semiconductor device, semiconductor package, and electronic device
A semiconductor device, a semiconductor package, and an electronic device are provided. The electronic device includes a first semiconductor package disposed on a circuit substrate.
08/14/14
20140225234
new patent Semiconductor device having lateral diode
A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion.
08/14/14
20140225231
new patent Modulating bow of thin wafers
Apparatus and methods modulate the bowing of thin wafers. According to a method, a wafer is formed of semiconductor material.
08/14/14
20140225229
new patent Group iii nitride composite substrate and method for manufacturing the same, and method for manufacturing group iii nitride semiconductor device
A group iii nitride composite substrate includes a group iii nitride film and a support substrate formed from a material different in chemical composition from the group iii nitride film. The group iii nitride film has a thickness of 10 μm or more.
08/14/14
20140225221
new patent Semiconductor device, method of manufacturing the same, and signal transmitting/receiving method using the semiconductor device
A semiconductor device includes a semiconductor chip including a main surface, an internal circuit including a plurality of transistors, formed on the main surface, a bonding pad electrically connected to the internal circuit, formed on the main surface, an inductor for communicating an external device in a non-contact manner, formed on the main surface, and a seal ring formed along an outer peripheral edge of the semiconductor chip to surround the internal circuit and the bonding pad in a plan view. The inductor has a configuration to surround the internal circuit and the bonding pad in the plan view and along the seal ring.
08/14/14
20140225217
new patent Semiconductor device and method of manufacturing the same
A semiconductor device and method of manufacturing the semiconductor device is disclosed in which the tradeoff relationship between the eoff and the turning off dv/dt is improved at a low cost using a trench embedding method. The method comprises a step of forming a parallel pn layer that is a superjunction structure using a trench embedding method and a step of ion implantation into an upper part of an n type semiconductor layer, i.e., an n type column, forming a high concentration n type semiconductor region.
08/14/14
20140225209
new patent Semiconductor device, electrical device system, and method of producing semiconductor device
A semiconductor device includes a first semiconductor layer having a first conductive type; a circuit layer including a second semiconductor layer; and a plurality of layered members. Each of the layered members includes an interlayer insulation film and a wiring layer formed on the interlayer insulation film.
08/14/14
20140225198
new patent Semiconductor device and method for fabricating the same
A semiconductor device includes a substrate having a first region and a second region, first and second gate electrodes disposed on the first and second regions, respectively, and first and second source/drain regions disposed on at least one side of the first and second gate electrodes, respectively. The device further includes first and second silicide regions in the first and second source/drain regions, respectively.
08/14/14
20140225196
new patent Semiconductor device and method of manufacturing the same
The present invention improves the aperture ratio of a pixel of a reflection-type display device or a reflection type display device without increasing the number of masks and without using a blackmask. A pixel electrode (167) is arranged so as to partially overlap a source wiring (137) for shielding the gap between pixels from light, and a thin film transistor is arranged so as to partially overlap a gate wiring (166) for shielding a channel region of the thin film transistor from light, thereby realizing a high pixel aperture ratio..
08/14/14
20140225191
new patent Laterally difffused metal oxide semiconductor device and method of forming the same
A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region.
08/14/14
20140225190
new patent Semiconductor device employing trenches for active gate and isolation
A semiconductor device with multiple transistor devices includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer including a first trench gate; a second trench formed in the semiconductor layer and extending into the substrate and including a second trench gate; a first transistor device being an ldmos transistor formed in the semiconductor layer between the first trench and the second trench; and a second transistor device formed in the semiconductor layer on the other side of the second trench. The first transistor device is electrically isolated from the second transistor device by the second trench..
08/14/14
20140225189
new patent Method of fabricating semiconductor device
In a method of fabricating a semiconductor device having a misfet of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.. .
08/14/14
20140225188
new patent Source and body contact structure for trench-dmos devices using polysilicon
A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed.
08/14/14
20140225185
new patent Method of making a low-rdson vertical power mosfet device
The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the rdson (drain-source on resistance) of power mosfets, and a power mosfet device made by the method.
08/14/14
20140225183
new patent Three-dimensional semiconductor memory device
A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.. .
08/14/14
20140225170
new patent Semiconductor device and method of manufacturing the same
In one embodiment, a semiconductor device includes a first diffusion layer of a first conductivity type and a second diffusion layer of a second conductivity type that are provided in a semiconductor layer at a distance, the second conductivity type being an opposite conductivity type of the first conductivity type, a first insulating film and a second insulating film that are provided on the semiconductor layer between the first diffusion layer and the second diffusion layer at a distance, a gate electrode provided on the first insulating film, and a threshold regulating electrode provided on the second insulating film.. .
08/14/14
20140225169
new patent Gate all around semiconductor device
A gate all around (gaa) type semiconductor device is provided. The gaa type semiconductor device includes source/drain layers formed to be spaced apart from each other, a channel layer connecting the source/drain layers, and a gate electrode formed along the periphery of at least a portion of the channel layer, wherein lower portions of the source/drain layers are formed more deeply than the channel layer, and an insulation pattern is formed between the lower portions of the source/drain layers and lower portions of the gate electrode..
08/14/14
20140225168
new patent Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device
One method includes forming first and second spaced-apart trenches extending at least partially into a semiconducting substrate defining a fin structure for the device, forming a stress-inducing material having a first type of stress in the first trench, forming a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different than the first type of stress, and forming a gate structure around a portion of the fin structure. One device includes first and second spaced-apart trenches in a semiconducting substrate defining at least a portion of a fin for the device, a stress-inducing material having a first type of stress in the first trench, a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different type than the first stress, and a gate structure around a portion of the fin structure..
08/14/14
20140225164
new patent Semiconductor device
A standard cell has gate patterns extending in y direction and arranged at an equal pitch in x direction. End portions of the gate patterns are located at the same position in y direction, and have an equal width in x direction.
08/14/14
20140225161
new patent Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer above the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a p-type nitride semiconductor layer above the second nitride semiconductor layer; two third nitride semiconductor layers of n-type above the second nitride semiconductor layer and located separately on either side of the p-type nitride semiconductor layer; and a first ohmic electrode above one of the two third nitride semiconductor layers and a second ohmic electrode above the other of the two third nitride semiconductor layers; and a gate electrode above the p-type nitride semiconductor layer. The second nitride semiconductor layer includes, in a region above which neither the p-type nitride semiconductor layer nor the two third nitride semiconductor layers is located, a surface layer including p-type impurities identical to those in the p-type nitride semiconductor layer..
08/14/14
20140225155
new patent Semiconductor device
A semiconductor device includes: a first semiconductor region; a second semiconductor region, which is arranged on the first semiconductor region; a third semiconductor region, which is arranged on the second semiconductor region; a plurality of fourth semiconductor regions, each of which is arranged with being spaced from each other on the third semiconductor region; a insulation film arranged on a inner wall of a recess, which extends from upper faces of the fourth semiconductor region to pass through the third semiconductor region and the fourth semiconductor region and reaches the second semiconductor region; a control electrode, a first main electrode, a second main electrode, which is electrically connected to the third semiconductor region and the fourth semiconductor region, wherein a ratio of a width of the recess to a width of the third semiconductor region abutting on the second main electrode is 1 or more.. .
08/14/14
20140225143
new patent Light emitting device
A semiconductor device has a light emitting element, and a resin layer; the light emitting element includes a semiconductor laminated body in which a first semiconductor layer and a second semiconductor layer are laminated in sequence, a second electrode connected to the second semiconductor layer on an upper surface of the second semiconductor layer that forms an upper surface of the semiconductor laminated body, and a first electrode connected to the first semiconductor layer on an upper surface of the first semiconductor layer in which a portion of the second semiconductor layer on one surface of the semiconductor laminated body is removed and a portion of the first semiconductor layer is exposed; and the resin layer is configured to cover at least a side surface of the light emitting element, and an upper surface of the resin layer is lower than the upper surface of the semiconductor laminated body.. .
08/14/14
20140225132
new patent Lightweight solid state light source with common light emitting and heat dissipating surface
Lightweight solid state light sources with common light emitting and heat dissipating surfaces consisting of light emitting diodes (led) in thermal contact to light transmitting thermally conductive elements and combined with a reflector element to form a light recycling cavity, provide both convective and radiative cooling from their light emitting surfaces, eliminating the need for appended heatsinks. The lightweight self-cooling solid state light sources integrate the electrical interconnect of the leds and other semiconductor devices to a single substrate that is both the heatsink and the light emitting element.
08/14/14
20140225129
new patent Antenna module and method for manufacturing the same
An electrode is formed on at least one surface of first and second surfaces of a dielectric film formed of resin to be capable of receiving or transmitting an electromagnetic wave in a terahertz band. A semiconductor device operable in the terahertz band is mounted on at least one surface of the first and second surfaces of the dielectric film to be electrically connected to the electrode.
08/14/14
20140225126
new patent Semiconductor device, and manufacturing method for same
The present invention is directed to a semiconductor device including a semiconductor chip formed with an sic-igbt including an sic semiconductor layer, a first conductive-type collector region formed such that the collector region is exposed on a second surface of the sic semiconductor layer, a second conductive-type base region formed such that the base region is in contact with the collector region, a first conductive-type channel region formed such that the channel region is in contact with the base region, a second conductive-type emitter region formed such that the emitter region is in contact with the channel region to define a portion of a first surface of the sic semiconductor layer, a collector electrode connected to the collector region, and an emitter electrode connected to the emitter region, and a mosfet including a second conductive-type source region electrically connected to the emitter electrode and a second conductive-type drain region electrically connected to the collector electrode, the mosfet connected in parallel to the sic-igbt.. .
08/14/14
20140225120
new patent Gallium nitride semiconductor device with improved termination scheme
This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein..
08/14/14
20140225114
new patent Power semiconductor device
A power semiconductor device includes a second conductive type sense outer-peripheral well formed to surround a plurality of sense wells on the surface of a drift layer, a first conductive type main-cell source region selectively formed on the surface of the main cell well, a first conductive type sense source region selectively formed on the surface of the sense well, a first conductive type capacitor lower electrode region selectively formed on the surface of the sense outer-peripheral well, a gate insulation film formed on the channel regions and on the sense outer-peripheral well, a gate electrode formed on the gate insulation film, and a sense pad electrically connected to the sense well and the sense source region as well as on the sense outer-peripheral well and the capacitor lower electrode region.. .
08/14/14
20140225111
new patent Semiconductor device and method of manufacturing semiconductor device
A semiconductor device including: a base material portion that includes a semiconductor substrate and an insulating film that is formed on one face of the semiconductor substrate and on which a vertical hole is formed along the thickness direction of the semiconductor substrate; a vertical hole wiring portion that includes a vertical hole electrode formed on a side wall of the base material portion that forms the vertical hole; a metallic film that is formed within the insulating film and that is electrically connected to the vertical hole wiring portion; and a conductive protective film that is formed to be in contact with the metallic film within the insulating film and that is formed in a region that includes a contact region of a probe during a probe test that is performed in the middle of manufacture on a film face of the metallic film.. .
08/14/14
20140225109
new patent Semiconductor device
The concentration of impurity elements included in an oxide semiconductor film in the vicinity of a gate insulating film is reduced. Further, crystallinity of the oxide semiconductor film in the vicinity of the gate insulating film is improved.
08/14/14
20140225107
new patent Semiconductor device
An object of the invention is to improve the accuracy of light detection in a photosensor, and to increase the light-receiving area of the photosensor. The photosensor includes: a light-receiving element which converts light into an electric signal; a first transistor which transfers the electric signal; and a second transistor which amplifies the electric signal.
08/14/14
20140225106
new patent Thin film, method of forming thin film, semiconductor device including thin film, and method of manufacturing semiconductor device
A thin film, a method of forming the thin film, a semiconductor device including the thin film, and a method of manufacturing the semiconductor device include forming a thin film including a metal oxynitride, and treating the thin film with inert gas ions so as to stabilize properties of the thin film. The metal oxynitride may include zinc oxynitride (znoxny).
08/14/14
20140225105
new patent Semiconductor device
A transistor or the like having excellent electrical characteristics is provided. A semiconductor device includes a gate electrode; a gate insulating film in contact with the gate electrode; and a multilayer film which is in contact with the gate insulating film and includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer in the order from a side farthest from the gate insulating film.
08/14/14
20140225104
new patent Semiconductor device
An object is to provide a semiconductor device that includes an oxide semiconductor and is suitable for a power device. An object is to provide a semiconductor device in which large current can flow.
08/14/14
20140225103
new patent Semiconductor device and manufacturing method of semiconductor device
A highly reliable semiconductor device including an oxide semiconductor is provided. Oxygen is supplied from a base insulating layer provided below an oxide semiconductor layer to a channel formation region, whereby oxygen vacancies which might be generated in the channel formation region are filled.
08/14/14
20140225089
new patent Organic semiconductor device and method of manufacturing the same
According to one embodiment, an organic semiconductor device includes a supporting substrate, a plurality of organic el light emitting elements, a first barrier layer, a flattening layer, and a second barrier layer. The flattening layer exists sporadically and makes gentle in inclination steep elevation change present in the surface of the first barrier layer.
08/14/14
20140225075
new patent Thin film semiconductor device, organic light-emitting display device, and method of manufacturing the thin film semiconductor device
Provided is a thin film semiconductor device such as an organic light-emitting display which includes a thin film transistor (tft) having a lightly doped region. The thin film semiconductor includes a substrate, a first active pattern, a first lower conductive pattern, and a first upper conductive pattern.
08/14/14
20140225028
new patent Wet etchants including at least one etch blocker
Methods for preventing isotropic removal of materials at corners faulted by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film.


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