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Semiconductor Device patents



      

This page is updated frequently with new Semiconductor Device-related patent applications.




Date/App# patent app List of recent Semiconductor Device-related patents
04/07/16
20160099715 
 Level shift circuit and semiconductor device patent thumbnailLevel shift circuit and semiconductor device
A level shift circuit includes: a latch circuit (q5, q6, q7, q8) including first (q5, q7) and second (q6, q8) inverter circuits; a first input mos transistor (q1) operating in accordance with an input signal; a second input mos transistor (q2) operating in accordance with an inversion signal of the input signal; and a current-voltage control mos transistor (q9). The latch circuit (q5, q6, q7, q8) outputs a voltage having been converted from the input voltage in level.
Renesas Electronics Corporation


04/07/16
20160099711 
 Semiconductor device, and on-vehicle electronic device and automobile each including semiconductor device patent thumbnailSemiconductor device, and on-vehicle electronic device and automobile each including semiconductor device
A load driving device 10 includes a temperature detector td1 that sets a temperature difference detection signal dt_ot to active when a temperature difference tdif between a temperature ttr of an output transistor t1 and an ambient temperature becomes more than a reference temperature difference tdref1, and sets an over temperature detection signal at_ot to active when the temperature ttr of the output transistor t1 becomes higher than a reference temperature tref1, a current limiter il1 that limits a gs current of the output transistor t1 when any one of the detection signals becomes active, and the output transistor t1 that turns off regardless of an external input signal in when any one of the detection signals becomes active. The temperature detector td1 sets the temperature difference detection signal dt_ot to inactive when the temperature difference tdif between the output transistor temperature ttr and the ambient temperature becomes equal to or less than a reference temperature difference tdref2, and sets the over temperature detection signal at_ot to inactive when the output transistor temperature ttr becomes equal to or lower than a reference temperature tref2..
Renesas Electronics Corporation


04/07/16
20160099395 
 Led leadframe or led substrate, semiconductor device, and  manufacturing led leadframe or led substrate patent thumbnailLed leadframe or led substrate, semiconductor device, and manufacturing led leadframe or led substrate
An led leadframe or led substrate includes a main body portion having a mounting surface for mounting an led element thereover. A reflection metal layer serving as a reflection layer for reflecting light from the led element is disposed over the mounting surface of the main body portion.
Dai Nippon Printing Co., Ltd.


04/07/16
20160099383 
 Semiconductor device and  manufacturing the same patent thumbnailSemiconductor device and manufacturing the same
A semiconductor device including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer which are sequentially stacked; a first conductivity type upper electrode portion and a first conductivity type lower electrode portion disposed to correspond to each other with the first conductivity type semiconductor layer interposed therebetween; a second conductivity type upper electrode portion and a second conductivity type lower electrode portion disposed to correspond to each other with the first and second conductivity type semiconductor layers interposed therebetween; and a second conductivity type electrode connection portion electrically connecting the second conductivity type upper electrode portion and the second conductivity type lower electrode portion.. .
Lg Electronics Inc.


04/07/16
20160099381 
 Epitaxy base, semiconductor light emitting device and manufacturing methods thereof patent thumbnailEpitaxy base, semiconductor light emitting device and manufacturing methods thereof
An epitaxy base including a substrate and a nucleating layer disposed on the substrate. The nucleating layer is an aln layer with a single crystal structure.
Playnitride Inc.


04/07/16
20160099374 
 Semiconductor device patent thumbnailSemiconductor device
A semiconductor device used for a semiconductor relay includes: a first diode; a second diode; an electric field shield film for covering the second semiconductor island region, where the second diode is formed; and a wiring for electrically connecting the first diode to the second diode. The wiring is arranged so as to cross above a silicon oxide film surrounding the second semiconductor island region.
Renesas Electronics Corporation


04/07/16
20160099358 
 Method of manufacturing semiconductor device patent thumbnailMethod of manufacturing semiconductor device
A semiconductor device including a nonvolatile memory cell and a field effect transistor together is improved in performance. In a method of manufacturing a semiconductor device, a hydrogen-containing insulating film is formed before heat treatment of a semiconductor wafer, the hydrogen-containing insulating film covering a gate electrode and agate insulating film in a region that will have a memory cell therein, and exposing a region that will have therein a misfet configuring a peripheral circuit.
Renesas Electronics Corporation


04/07/16
20160099356 
 Semiconductor device, manufacturing method thereof, and display device patent thumbnailSemiconductor device, manufacturing method thereof, and display device
A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a tft which is in an on state is reduced to increase an on current.
Semiconductor Energy Laboratory Co., Ltd.


04/07/16
20160099353 
 Semiconductor device patent thumbnailSemiconductor device
A semiconductor device in which release of oxygen from side surfaces of an oxide semiconductor film including c-axis aligned crystal parts can be prevented is provided. The semiconductor device includes a first oxide semiconductor film, a second oxide semiconductor film including c-axis aligned crystal parts, and an oxide film including c-axis aligned crystal parts.
Semiconductor Energy Laboratory Co., Ltd.


04/07/16
20160099350 
 Semiconductor device patent thumbnailSemiconductor device
A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and extends in a first direction with a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped semiconductor layer resides on the fin-shaped semiconductor layer.
Unisantis Electronics Singapore Pte. Ltd.


04/07/16
20160099349 

Semiconductor device with non-isolated power transistor with integrated diode protection


A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.. .
Freescale Semiconductor, Inc.


04/07/16
20160099347 

Laterally diffused metal oxide semiconductor device and manufacturing method therefor


Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (s210); coating a photoresist on the surface of the wafer (s220); performing photoetching by using a first photoetching mask, and exposing a first implantation window after development (s230); performing ion implantation via the first implantation window to form a drift region in the substrate (s240); coating one layer of photoresist on the surface of the wafer again after removing the photoresist (s250); performing photoetching by using the photoetching mask of the oxide layer of the drift region (s260); and etching the oxide layer to form the oxide layer of the drift region (s270). Further provided is a laterally diffused metal oxide semiconductor device..
Csmc Technologies Fab1 Co., Ltd.


04/07/16
20160099346 

Semiconductor device


A semiconductor device including a gate structure, a source region, a drain region, a first conductive type epitaxial layer, a high voltage second conductive type well, a linear graded high voltage first conductive type well and a first conductive type buried layer is provided. The first conductive type buried layer is located within the first conductive type epitaxial layer and below the high voltage second conductive type well, and a length of the first conductive type buried layer is smaller than a length of the high voltage second conductive type well..
Nuvoton Technology Corporation


04/07/16
20160099344 

Facilitating fabricating gate-all-around nanowire field-effect transistors


Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s).
Globalfoundries Inc.


04/07/16
20160099335 

Semiconductor device and manufacturing the same


A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.. .
Fujitsu Limited


04/07/16
20160099332 

Partial sacrificial dummy gate with cmos device with high-k metal gate


A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.. .
International Business Machines Corporation


04/07/16
20160099330 

Semiconductor device with nanowires in different regions at different heights


A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels.

04/07/16
20160099324 

Structure and formation semiconductor device with gate stack


A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


04/07/16
20160099322 

Semiconductor devices with sidewall spacers of equal thickness


Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack.
International Business Machines Corporation


04/07/16
20160099321 

Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers


A semiconductor device includes a silicide contact region positioned at least partially in a semiconductor layer, an etch stop layer positioned above the semiconductor layer, and a dielectric layer positioned above the etch stop layer. A contact structure that includes a conductive contact material extends through at least a portion of the dielectric layer and through an entirety of the etch stop layer to the silicide contact region, and a silicide protection layer is positioned between sidewalls of the etch stop layer and sidewalls of the contact structure..
Globalfoundries Inc.


04/07/16
20160099317 

Vertical semiconductor devices including superlattice punch through stop layer and related methods


A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion.
Mears Technologies, Inc.


04/07/16
20160099316 

Semiconductor device and manufacturing method thereof


In a silicon carbide semiconductor device having a trench type mos gate structure, the present invention makes it possible to inhibit the operating characteristic from varying. A p-type channel layer having an impurity concentration distribution homogeneous in the depth direction at the sidewall part of a trench is formed by applying angled ion implantation of p-type impurities to a p-type body layer formed by implanting ions having implantation energies different from each other two or more times after the trench is formed.
Renesas Electronics Corporation


04/07/16
20160099315 

Nanotube semiconductor devices


Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer.
Alpha And Omega Semiconductor Incorporated


04/07/16
20160099314 

Method of forming a semiconductor device and structure therefor


In one embodiment, a method of forming an mos transistor includes forming a threshold voltage (vth) of the mos transistor to have a first value at interior portions of the mos transistor and a second value at other locations within the mos transistor that are distal from the interior portion wherein the second value is less than the first value.. .
Semiconductor Components Industries, Llc


04/07/16
20160099310 

Semiconductor device integrating high and low voltage devices


The present invention is directed to a method for forming multiple active components, such as bipolar transistors. Mosfets, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components.
Alpha & Omega Semiconductor Incorporated


04/07/16
20160099308 

Oxide terminated trench mosfet with three or four masks


An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region.
Alpha And Omega Semiconductor Incorporated


04/07/16
20160099302 

Embedded metal-insulator-metal capacitor


A method of manufacturing a semiconductor device comprising a capacitor structure is provided, including the steps of forming a first metallization layer comprising a first dielectric layer and a first conductive layer functioning as a lower electrode for the capacitor structure over a semiconductor substrate, forming a barrier layer functioning as a capacitor insulator for the capacitor structure on the first metallization layer, forming a metal layer on the barrier layer and etching the metal layer to form an upper electrode of the capacitor structure.. .
Globalfoundries Inc.


04/07/16
20160099297 

Flexible active matrix display


High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate.
Globalfoundries Inc.


04/07/16
20160099286 

Semiconductor device including image pick up device


The performance of a semiconductor device is improved by preventing 1/f noise from being generated in a peripheral transistor, in the case where the occupation area of photodiodes, which are included in each of a plurality of pixels that form an image pickup device, is expanded. In the semiconductor device, the gate electrode of an amplification transistor is formed by both a gate electrode part over an active region and a large width part that covers the boundary between the active region and an element isolation region and the active region near the boundary and that has a gate length larger than that of the gate electrode part..
Renesas Electronics Corporation


04/07/16
20160099259 

Wiring layer and manufacturing method therefor


To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator.
Semiconductor Energy Laboratory Co., Ltd.


04/07/16
20160099258 

Semiconductor device and electronic device


To provide a novel semiconductor device or a semiconductor device capable of operating at high speed. The semiconductor device includes a plurality of circuits each having a function of storing data and a wiring el.
Semiconductor Energy Laboratory Co., Ltd.


04/07/16
20160099251 

Semiconductor device


An insulating film, which is sandwiched between a gate electrode formed on an soi layer constituting an soi substrate and an epitaxial layer formed on the soi layer and including a high-concentration diffusion region and is formed in contact with a side wall of the gate electrode, is set as a target of dielectric breakdown in a write operation in an anti-fuse element.. .
Renesas Electronics Corporation


04/07/16
20160099249 

Integrated fin and strap structure for an access transistor of a trench capacitor


At least one dielectric pad layer is formed on a semiconductor-on-insulator (soi) substrate. A deep trench is formed in the soi substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the soi substrate.
International Business Machines Corporation


04/07/16
20160099248 

Semiconductor memory device with improved active area/word line layout


One semiconductor device includes a bit line extending in a straight line in an x direction, a first and a second horizontal active region extending in the x direction, and a sloped active region arranged between the first and the second horizontal regions and inclined with respect to the x direction, an active region arranged at the center of a bit line impurity diffusion region, a first word line arranged in the first horizontal active region segment, a second word line arranged in the second horizontal active region segment, and a third and a fourth word line arranged in the sloped active region segment next to each other with the bit line impurity diffusion region interposed therebetween.. .
Ps5 Luxco S.a.r.l.


04/07/16
20160099247 

Semiconductor devices with capacitors


A semiconductor device includes bottom electrodes two-dimensionally arranged on a substrate and transistors connected to the bottom electrodes, respectively. Each of the bottom electrodes may include first side surfaces facing each other in a first direction and second side surfaces facing each other in a second direction crossing the first direction.

04/07/16
20160099245 

Semiconductor devices with sidewall spacers of equal thickness


Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack.
International Business Machines Corporation


04/07/16
20160099244 

Methods of forming semiconductor devices and structures thereof


Methods of forming semiconductor devices and structures thereof are disclosed. In some embodiments, a semiconductor device includes a substrate that includes fins.
Taiwan Semiconductor Manufacturing Company, Ltd.


04/07/16
20160099243 

Semiconductor device and manufacturing the same


A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction.
Samsung Electronics Co., Ltd.


04/07/16
20160099242 

Semiconductor device employing trenches for active gate and isolation


A semiconductor device includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer including a first trench gate; a second trench formed in the semiconductor layer and extending into the substrate and including a second trench gate; a first transistor device formed in the semiconductor layer adjacent the first trench. The second trench encircles active area of the first transistor device to provide electrical isolation of the first transistor device..
Alpha And Omega Semiconductor Incorporated


04/07/16
20160099239 

Methods, apparatus and system for reduction of power consumption in a semiconductor device


At least one method, apparatus and system disclosed herein involves performing power reduction process on a finfet device. A first design is provided.
Globalfoundries Inc.


04/07/16
20160099232 

Fingerprint recognition semiconductor device and semiconductor device


A fingerprint recognition semiconductor device includes an insulation layer, a wiring pattern formed on a lower surface of the insulation layer, and a sensor element flip-chip-connected to the wiring pattern. The sensor element includes an active surface, including a sensor portion that recognizes a fingerprint, and a rear surface, located at a side opposite to the active surface.
Shinko Electric Industries Co., Ltd.


04/07/16
20160099229 

Semiconductor devices having through electrodes, semiconductor packages including the same, methods of manufacturing the same, electronic systems including the same, and memory cards including the same


A semiconductor device includes a substrate having a first surface and a second surface that are opposite to each other, a plurality of through electrodes penetrating the substrate and extending from the first surface to the second surface, front-side bumps disposed on the first surface and connected to odd-numbered through electrodes among the plurality of through electrodes, and backside bumps disposed on the second surface and connected to even-numbered through electrodes among the plurality of through electrodes. Related semiconductor packages, fabrication methods, electronic systems and memory cards are also provided..
Sk Hynix Inc.


04/07/16
20160099228 

Method and die-to-die pad contact


A semiconductor device includes at least a first semiconductor die and a second semiconductor die. The first semiconductor dies comprises a first and second side, and includes at least a first contact pad located on the first side of the first semiconductor die.
Hgst Netherlands B.v.


04/07/16
20160099224 

Semiconductor device and manufacturing the same


A semiconductor device according to the present invention includes an insulating substrate having a circuit pattern, semiconductor elements bonded on the circuit pattern with a brazing material, and a wiring terminal bonded with a brazing material on an electrode provided on each of the semiconductor elements on an opposite side of the circuit pattern, in which a part of the wiring terminal is in contact with the insulating substrate, and insulated from the circuit pattern.. .
Mitsubishi Electric Corporation


04/07/16
20160099223 

Semiconductor device and manufacturing method thereof


A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (ppi) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the ppi by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the ppi and around the metallic paste and the conductive bump.. .
Taiwan Semiconductor Manufacturing Company Ltd.


04/07/16
20160099219 

Semiconductor device having features to prevent reverse engineering


It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques.
Secure Silicon Layer, Inc.


04/07/16
20160099218 

Semiconductor package and manufacturing the same


Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the substrate, wherein the mold is formed to cover the semiconductor device such that at least one inner side surface of the mold has a slope; providing a molding material into the mold to encapsulate the semiconductor device; removing the mold from the substrate; and forming an electromagnetic shielding (ems) layer to cover a top surface and side surfaces of the molding material..
Samsung Electronics Co., Ltd.


04/07/16
20160099216 

Semiconductor device structure and forming the same


A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


04/07/16
20160099206 

Wafer level packaging of electronic device


Wafer level packaged semiconductor device with enhanced heat dissipation properties. The semiconductor device includes a top and a bottom face and at least one metal pad is positioned on the top and the bottom faces.
Viagan Ltd.


04/07/16
20160099200 

Aluminum alloy lead frame for a semiconductor device and corresponding manufacturing process


Described herein is a semiconductor device provided with: a die of semiconductor material; a lead frame, defining a support plate, which is designed to carry the die, and leads, which are designed to be electrically coupled to the die; and a package, of encapsulating material, which is designed to encapsulate the die and partially coming out of which are the leads. The lead frame has as constituent material an aluminum alloy comprising a percentage of silicon ranging between 1% and 1.5%..
Stmicroelectronics S.r.l.


04/07/16
20160099197 

Semiconductor package and circuit substrate for the semiconductor package


Provided is a circuit substrate for a semiconductor package used for mounting a plurality of semiconductor devices. The circuit substrate including: a first circuit substrate unit; and a second circuit substrate unit that is formed on the first circuit substrate unit, wherein young's modulus of a first dielectric material composing the dielectric layer of the first circuit substrate unit is higher than young's modulus of a second dielectric material composing the dielectric layer of the second circuit substrate unit, and a coefficient of thermal expansion of the first dielectric material composing the dielectric layer of the first circuit substrate unit is smaller than a coefficient of thermal expansion of the second dielectric material composing the dielectric layer of the second circuit substrate unit..
Hitachi Metals, Ltd.


04/07/16
20160099193 

Semiconductor device


A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor substrate; an electrode pad provided on the main plane of the semiconductor substrate and connected to the semiconductor element; a guard ring surrounding the semiconductor element and the electrode pad, and provided on the main plane of the semiconductor substrate; and an insulating film covering all region of a semiconductor of the main plane of the semiconductor substrate exposed inside the guard ring, wherein the insulating film is made of a water impermeable material.. .
Mitsubishi Electric Corporation


04/07/16
20160099188 

Semiconductor device with sensor potential in the active region


A semiconductor device includes semiconductor body region and a surface region, the semiconductor body region including a first conductivity type first semiconductor region type and a second conductivity type second semiconductor region. The semiconductor device further includes: a first load contact structure included in the surface region and arranged for feeding a load current into the semiconductor body region; a first trench extending into the semiconductor body region and having a sensor electrode and a first dielectric, the first dielectric electrically insulating the sensor electrode from the second semiconductor region; an electrically conductive path electrically connecting the sensor electrode to the first semiconductor region; a first semiconductor path, wherein the first semiconductor region is electrically coupled to the first load contact structure by at least the first semiconductor path; a sensor contact structure included in the surface region and arranged for receiving an electrical potential of the sensor electrode..
Infineon Technologies Ag


04/07/16
20160099185 

Method of controlling an etching process for forming fine patterns of a semiconductor device


A method of controlling an etching process for forming fine patterns of a semiconductor device includes forming a lower pattern having a plurality of openings on a substrate, obtaining a width value of the lower pattern, and controlling a process recipe of an etching process for forming the lower pattern by using the width value.. .
Samsung Electronics Co., Ltd.


04/07/16
20160099181 

Semiconductor device and fabricating the same


A semiconductor device comprises a substrate, a semiconductor fin, a first isolation structure and a first dummy structure. The semiconductor fin comprises a first sub-fin and a second sub-fin protruding from a surface of the substrate.
United Microelectronics Corp.


04/07/16
20160099180 

Method for manufacturing a semiconductor switching device with different local cell geometry


A method for manufacturing a semiconductor device includes providing a semiconductor substrate having an outer rim, an active area, and an edge termination region arranged between the active area and the outer rim, and forming a plurality of switchable cells in the active area. Each of the switchable cells includes a body region, a gate electrode structure, and a source region.
Infineon Technologies Austria Ag


04/07/16
20160099179 

Method of forming semiconductor device


A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided.
United Microelectronics Corp.


04/07/16
20160099177 

Methods of manufacturing a semiconductor device


In a method, an isolation layer pattern is formed on a substrate to define first and second active fins. An arc layer is formed on the isolation layer pattern to at least partially cover sidewalls of the first and second active fins.

04/07/16
20160099174 

Method of forming an interconnect structure for a semiconductor device


Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate. A via pattern including a plurality of openings may be defined above the substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


04/07/16
20160099173 

Methods for etching a barrier layer for an interconnection structure for semiconductor applications


Embodiments of the present disclosure provide methods for etching a barrier layer disposed under a metal layer, such as a copper layer, when the metal layer is etched open exposing the barrier layer, to form an interconnection structure in semiconductor devices. In one embodiment, a method of etching a barrier layer disposed under a metal layer formed on a substrate includes supplying a first etching gas mixture comprising a hydrogen containing gas and an inert gas into a processing chamber to clean a surface of a barrier layer disposed on a substrate for a first period of time, supplying a second etching gas mixture comprising fluorine containing gas into the processing chamber to etch the barrier layer, and switching to supply the first etching gas in the processing chamber to clean the etched barrier layer for a second period of time..
Applied Materials, Inc.


04/07/16
20160099170 

Methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby


Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure.

04/07/16
20160099165 

Semiconductor wafer device and manufacturing method thereof


A method of manufacturing a semiconductor device comprises providing a carrier, disposing a plurality of dies over the carrier along a first direction and a second direction orthogonal to the first direction to arrange the plurality of dies in a plurality of rows, and shifting one of the plurality of rows along the first direction or the second direction in a predetermined distance.. .
Taiwan Semiconductor Manufacturing Company Ltd.


04/07/16
20160099158 

Method for removing metal oxide


The present invention relates to a method of selectively removing metal oxide, particularly tungsten oxide without etching the un-oxidized metal. The method removes metal oxide with little or no loss of the clean metal to improve the contact resistance for contact metal in semiconductor device fabrication.
International Business Machines Corporation


04/07/16
20160099155 

Methods of forming a hard mask layer and of fabricating a semiconductor device using the same


A method of forming a hard mask layer on a substrate includes forming an amorphous carbon layer using nitrous oxide (n2o). A source of carbon and the nitrous oxide (n2o) are introduced to the substrate under a plasma ambient of an inert gas.
Samsung Electronics Co., Ltd.


04/07/16
20160099152 

Semiconductor device and fabricating the same


A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region.. .
Sk Hynix Inc.


04/07/16
20160099077 

Test system simultaneously testing semiconductor devices


Individual memory chips are simultaneously tested by a tester using selectively enabled stress modules that apply a corresponding stress test to memory cells, wherein each stress test is associated with a corresponding failure attribute for the memory cells. Built-in self-test (bist)/built-in self-stress (biss) circuitry is provided in each stress module and may configured to selectively apply one or more stress test(s) during the simultaneous testing of a plurality of memory chips..

04/07/16
20160099063 

Semiconductor device


A semiconductor device includes memory strings each including a drain select transistor, memory cells and a source select transistor, which are connected between a bit line and a common source line and suitable for operating based on voltages applied to a drain select line, word lines and a source select line, respectively, and an operation circuit suitable for performing a pre-program operation, an erase operation and a post-program operation on the memory strings. The operation circuit sequentially performs erase operations on the drain select transistors included in the memory strings..
Sk Hynix Inc.


04/07/16
20160099041 

Semiconductor device


Disclosed herein is a device that includes a memory cell array including plurality of word lines, a plurality of bit lines each intersecting the word lines and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines, and the device further includes a driver configured to drive a selected one of the word lines from an inactive level to an active and to drive the selected one of the word lines from the active level to an intermediate level at a first rate and from the intermediated level to the inactive level at a second rate. The intermediate level is between the active and inactive levels, and the first rate is greater than the second rate..
Ps4 Luxco S.a.r.l.


04/07/16
20160098509 

Integrated circuit and designing layout of integrated circuit


A method of designing a layout of an integrated circuit (ic) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern.

04/07/16
20160098508 

Method and system for designing semiconductor device


A method of designing a semiconductor device and system for designing a semiconductor device are provided. The method of designing a semiconductor device includes providing a standard cell layout which includes an active region and a dummy region; determining a first fin pitch between a first active fin and a second active fin in the active region and a second fin pitch between a first dummy fin and a second dummy fin in the dummy region; placing the first and second active fins in the active region and the first and second dummy fins in the dummy region using the first and second fin pitches; and verifying the standard cell layout..

04/07/16
20160098280 

Semiconductor device and semiconductor system including the same


A semiconductor device includes a boot-up signal generator suitable for generating a boot-up signal based on an external reset signal and a specific mode signal; and an internal circuit suitable for performing a boot-up operation based on the boot-up signals. .
Sk Hynix Inc.


04/07/16
20160097944 

Semiconductor device and manufacturing same


A semiconductor device (1001) includes a thin-film transistor (103) including a gate electrode (3a), source and drain electrodes (13as, 13ad), and an oxide semiconductor layer (7), and a source bus line (13s). The source electrode, the source bus line and the drain electrode include a first metallic element and the oxide semiconductor layer includes a second metallic element.
Sharp Kabushiki Kaisha


04/07/16
20160097810 

Semiconductor device and testing the same


A semiconductor device and a method for testing the same are provided. The semiconductor device includes a plurality of semiconductor dies staked, a plurality of through-electrodes disposed between the semiconductor dies, a first calculation unit calculating a first output value from input signals inputted into the through-electrodes by a logical operation, a second calculation unit calculating a second output value from output signals outputted from the through-electrodes by a logical operation, and a comparator comparing the first output value with the second output value..
Industry-aca-demic Cooperation Foundation, Yonsei University


04/07/16
20160097809 

Semiconductor device and multi-semiconductor package including the same


A semiconductor device includes a built-in self-test controller suitable for generating a test command and test data, and generating a test result signal in response to test result data, in a built-in self-test mode, an internal circuit suitable for performing a test operation in response to the test command and the test data and generating the test result data as a result of the test operation, and a signal transfer controller suitable for outputting the test command, the test data, and the test result signal through a set probe pad and a set bump pad in the built-in self-test mode.. .
Sk Hynix Inc.


04/07/16
20160097692 

Semiconductor device, and resistance measuring system and pressure instrumentation device each including the semiconductor device


According to one embodiment, a semiconductor device 1 includes: a variable current generating unit 11 that sends a direct current idac of a value according to a control signal s1 from one measurement node of a bridge circuit b1 in which a change amount Δr4 of a resistance value of a pressure-sensitive resistance element r4 appears as a potential difference Δv between measurement nodes na, nb; a potential difference determining unit 12 that determines whether or not the potential difference Δv has been generated; and a control unit 13 that outputs the control signal s1 to the variable current generating unit 11 so that the variable current generating unit 11 sends the direct current idac of a value that does not generate the potential difference Δv based on a determination result d1 of the potential difference determining unit 12.. .
Renesas Electronics Corporation


04/07/16
20160097131 

Methods for cyclically etching a metal layer for an interconnection structure for semiconductor applications


Embodiments of the present disclosure provide methods for etching a metal layer, such as a copper layer, to form an interconnection structure in semiconductor devices. In one example, a method of patterning a metal layer on a substrate includes supplying a first etching gas mixture comprising a hydro-carbon gas and a hydrogen containing gas into a processing chamber having a substrate disposed therein, the substrate having a metal layer disposed thereon, supplying a second gas mixture comprising the hydrogen containing gas to a surface of the etched metal layer disposed on the substrate, and supplying a third gas mixture comprising an inert gas into the processing chamber to sputter clean the surface of the etched metal layer..
Applied Materials, Inc.


04/07/16
20160097126 

Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium


A technique includes forming a film on a substrate in a process chamber by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing supplying a precursor gas to the substrate, exhausting the precursor gas from the process chamber, supplying an oxygen-containing gas to the substrate, exhausting the oxygen-containing gas from the process chamber, supplying a hydrogen-containing gas to the substrate, and exhausting the hydrogen-containing gas from the process chamber.
Hitachi Kokusai Electric Inc.


04/07/16
20160096726 

Mems device and making a mems device


A mems device and a method of making a mems device are disclosed. In one embodiment a semiconductor device comprises a substrate, a moveable electrode and a counter electrode, wherein the moveable electrode and the counter electrode are mechanically connected to the substrate.
Infineon Technologies Ag


04/07/16
20160096725 

Semiconductor device, display module, and electronic device


To reduce the amplitude voltage of control signals of a mems device. A semiconductor device includes a mems device, a first transistor, a second transistor whose source or drain is electrically connected to a source or a drain of the first transistor, a third transistor which sets the potential of a gate of the first transistor to a value at which the first transistor is turned on, a fourth transistor which sets the potential of the gate of the first transistor to a value at which the first transistor is turned off, and a fifth transistor which supplies a signal to a gate of the second transistor and a gate of the fourth transistor..
Semiconductor Energy Laboratory Co., Ltd.


04/07/16
20160096155 

Apparatus for supporting a semiconductor wafer and vibrating a semiconductor wafer


In embodiments of the present disclosure, a vibrator is used to generate a vibration wave with a variable frequency that can agitate and facilitate the circulation of the processing fluids, thereby enhancing the uniformity and efficiency of the resulting semiconductor device features, the vibrator may be a piezoelectric vibrator or other similar vibrators. In some embodiments, the vibration of the processing fluids can facilitate the processing fluids in circulating in and out of narrow channels or features, or the vibration of the processing fluids can facilitate the bubbling out of the microbubbles entrapped in the processing liquid or entrapped between the surface of the semiconductor wafer and the processing liquid.
Taiwan Semiconductor Manufacturing Co., Ltd.


03/31/16
20160095264 

Power module and power conversion apparatus using same


A power module includes a plurality of semiconductor devices constituting upper/lower arms of an inverter circuit, a plurality of conductive plates arranged to face electrode surfaces of the semiconductor devices and a module case configured to accommodate the semiconductor devices and conductive plates, wherein the module case includes a heat-radiation member made of plate-like metal and facing a surface of the conductive plate and a metallic frame body having an opening that is closed by the heat-radiation member, and wherein a heat-radiation fin unit having a plurality of heat-radiation fins vertically arranged thereon is provided at a center of the heat-radiation member, and a joint portion with the frame body is provided at an peripheral edge of the heat-radiation member, and the heat radiation member has a heat conductivity higher than that of the frame body, and the frame body has a higher rigidity than that of the heat-radiation member.. .
Hitachi Automotive Systems, Ltd.


03/31/16
20160095225 

Inductor system for multi-phase power management integrated circuits


A semiconductor device includes a first integrated circuit chip, a second integrated circuit chip, a coupled inductor system, and a semiconductor package. The first integrated circuit chip is connected to a substrate and configured to process digital data.
Qualcomm Incorporated


03/31/16
20160095219 

Printed wiring board and semiconductor device having the same


A printed wiring board includes a main wiring board having a main wiring pattern, and a sub wiring board mounted to the main board and having a sub wiring pattern such that the sub pattern electrically connects first and second electronic components, first conductor pads positioned to connect the first component to the main board and the sub board and having surfaces such that the first component is mounted onto the surfaces of the first pads via solder bumps, and second conductor pads positioned to connect the second component to the main board and the sub board and having surfaces such that the second component is mounted onto the surfaces of the second pads via solder bumps. The first and second pads are formed such that the surfaces of the first and second pads are formed on the same plane and have the same shape and the same size..
Ibiden Co., Ltd.


03/31/16
20160095213 

Semiconductor device


A semiconductor device includes a semiconductor element and a ceramic circuit substrate on which the semiconductor element is mounted. The ceramic circuit substrate includes a ceramic substrate having one surface and the other surface facing each other, a metal circuit board joined to the one surface of the ceramic substrate and electrically connected to the semiconductor element, and a metal heat-dissipation plate joined to the other surface of the ceramic substrate.
Mitsubishi Electric Corporation


03/31/16
20160094628 

App store for state machines


An app store includes a plurality of state machines that describe the function of a product. The system allows a user to select at least one app from this plurality of apps.
Linestream Technologies, Inc.


03/31/16
20160094239 

Semiconductor device


A semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type adc when n times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits..
Renesas Electronics Corporation


03/31/16
20160094236 

Semiconductor device, wireless sensor, and electronic device


An object is to reduce power consumption of an analog-digital converter circuit. An analog potential obtained in a sensor or the like is held in a sample-and-hold circuit including a transistor with an extremely low off-state current.
Semiconductor Energy Laboratory Co., Ltd.


03/31/16
20160094224 

Logic circuit, semiconductor device, electronic component, and electronic device


A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is diode-connected, and a capacitor.
Semiconductor Energy Laboratory Co., Ltd.


03/31/16
20160094168 

Semiconductor device and electrically-powered equipment


When electricity is supplied sequentially one by one to coils with a plurality of coil phases provided in a stator of a brushless dc motor, detection is made on a difference of signals corresponding to currents flowing respectively to coils with another plurality of coil phases coupled to the electrically conductive coil phases due to an effect of a magnetic flux of a stopped rotor. A stop position of the rotor with respect to the stator is determined, based on the relationship between a result of the detection operation and a coil phase in association with each other..
Renesas Electronics Corporation


03/31/16
20160094027 

Semiconductor device


Provided is a semiconductor device making it possible to promote area reduction while maintaining esd resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge.
Renesas Electronics Corporation






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