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Semiconductor Device patents



      
           
This page is updated frequently with new Semiconductor Device-related patent applications. Subscribe to the Semiconductor Device RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Device RSS RSS


Semiconductor device and method of forming insulating layer around semiconductor die

Semiconductor device and method of forming insulating layer around semiconductor die

Probe member for pogo pin

Probe member for pogo pin

Probe member for pogo pin

Semiconductor device

Date/App# patent app List of recent Semiconductor Device-related patents
11/20/14
20140344771
 Optical semiconductor device, socket, and optical semiconductor unit patent thumbnailnew patent Optical semiconductor device, socket, and optical semiconductor unit
An optical semiconductor unit of the present invention has an led device provided with an led (light emitting diode) and a socket to which the led device is mounted, the led device has a main body to which the led is mounted, the main body has a first surface to which block-shaped electrode portions are connected.. .
11/20/14
20140344612
 Semiconductor device, semiconductor device testing method, and data processing system patent thumbnailnew patent Semiconductor device, semiconductor device testing method, and data processing system
1. A semiconductor device includes an interface chip, a core chip, and a measurement-target signal line and a reference signal line, each including a through electrode penetrating through the core chip and each having a first end provided on the core chip and a second end provided on the interface chip.
11/20/14
20140344505
 Semiconductor device and method of operating the same patent thumbnailnew patent Semiconductor device and method of operating the same
A semiconductor device includes a memory block including memory cells coupled to bit lines, read/write circuits each including cache latch suitable for temporarily storing data to be stored in the memory cells, wherein the read/write circuits are divided into a plurality of groups and perform a program operation to store the data in the memory cells coupled to the bit lines, and an initialization control unit suitable for initializing the cache latches of the read/write circuits of a group corresponding to the address before the data is input to the cache latches, when a program command and an address are input.. .
11/20/14
20140342573
 Method for manufacturing semiconductor device, method for processing substrate, substrate processing apparatus and recording medium patent thumbnailnew patent Method for manufacturing semiconductor device, method for processing substrate, substrate processing apparatus and recording medium
There is provided a method for manufacturing a semiconductor device, including forming a thin film containing a specific element and having a prescribed composition on a substrate by alternately performing the following steps prescribed number of times: forming a first layer containing the specific element, nitrogen, and carbon on the substrate by alternately performing prescribed number of times: supplying a first source gas containing the specific element and a halogen-group to the substrate, and supplying a second source gas containing the specific element and an amino-group to the substrate, and forming a second layer by modifying the first layer by supplying a reactive gas different from each of the source gases, to the substrate.. .
11/20/14
20140342566
 Manufacturing method of semiconductor device patent thumbnailnew patent Manufacturing method of semiconductor device
To improve the manufacturing yield of semiconductor devices. Over a semiconductor wafer, a film to be processed is formed; over that film, an antireflection film is formed; and, over the antireflection film, a resist layer is formed.
11/20/14
20140342552
 Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via patent thumbnailnew patent Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via
A method for fabricating through-silicon vias (tsvs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill tsvs with plated-conductive material (e.g., copper) from an electroplating solution.
11/20/14
20140342551
 Semiconductor devices and method of fabricating the same patent thumbnailnew patent Semiconductor devices and method of fabricating the same
In a method of fabricating a semiconductor device, a first sacrificial layer, a first insulating layer, and a second sacrificial layer are successively provided on a substrate. The second sacrificial layer, the first insulating layer, and the first sacrificial layer are patterened to define an opening exposing a portion of the substrate and successively forming second sacrificial patterns, capping patterns, and first sacrificial patterns on the substrate.
11/20/14
20140342550
 Method for fabricating semiconductor device by damascene process patent thumbnailnew patent Method for fabricating semiconductor device by damascene process
A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes.. .
11/20/14
20140342548
 Integrated circuit devices including interconnections insulated by air gaps and methods of fabricating the same patent thumbnailnew patent Integrated circuit devices including interconnections insulated by air gaps and methods of fabricating the same
Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection.
11/20/14
20140342544
 Method for manufacturing semiconductor device patent thumbnailnew patent Method for manufacturing semiconductor device
A semiconductor wafer is subjected to a protection film formation step process as a process before evaluation of electrical characteristics. In this process, after an insulating film serving as a protection film is formed, a photolithography process and an etching process are performed so as to form a protection film having a plurality of openings exposing an emitter electrode.
11/20/14
20140342540
new patent Semiconductor device and method of manufacturing the same
A semiconductor device having a buried gate is provided. The semiconductor device is formed in a structure in which a plurality of contacts having small step differences are stacked without forming a metal contact applying an operation voltage to the buried gate in a single contact and a contact pad is formed between the contacts so that failure due to misalignment can be prevented without a separate additional process for forming the contacts..
11/20/14
20140342539
new patent Semiconductor device having mixedly mounted components with common film layers and method of manufacturing the same
A metal gate electrode and a poly-silicon resistance element are mixedly mounted in the same semiconductor substrate. The metal gate electrode is formed on a first gate insulating film and includes a first gate metal film and a first gate silicon film.
11/20/14
20140342537
new patent Mechanisms for forming ultra shallow junction
A method of making a semiconductor device includes forming a fin structure over a substrate. The method further includes performing a plasma doping process on the fin structure.
11/20/14
20140342533
new patent Method of strain and defect control in thin semiconductor films
A method of managing strain and preventing defect formation in semiconductor materials is described. In structures featuring two or more semiconductor materials with different lattice constants, buffer layers may be used to form deposition surfaces that result in defect-free semiconductor devices.
11/20/14
20140342521
new patent Transistor performance using a two-step damage anneal
A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device.
11/20/14
20140342517
new patent Method for fabricating trench type power semiconductor device
A method of forming a trench type semiconductor power device is disclosed. An epitaxial layer is formed on a substrate.
11/20/14
20140342512
new patent High voltage iii-nitride semiconductor devices
A iii-n device is described has a buffer layer, a first iii-n material layer on the buffer layer, a second iii-n material layer on the first iii-n material layer on an opposite side from the buffer layer and a dispersion blocking layer between the buffer layer and the channel layer. The first iii-n material layer is a channel layer and a compositional difference between the first iii-n material layer and the second iii-n material layer induces a 2deg channel in the first iii-n material layer.
11/20/14
20140342499
new patent Semiconductor device and manufacturing method thereof
The contact resistance between an oxide semiconductor film and a metal film is reduced. A transistor that uses an oxide semiconductor film and has excellent on-state characteristics is provided.
11/20/14
20140342498
new patent Semiconductor device and method for manufacturing the same
A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween.
11/20/14
20140342491
new patent Method for manufacturing waveguide-type semiconductor device
A method for manufacturing a waveguide-type semiconductor device includes the steps of forming an epitaxial structure including a waveguide mesa and a device mesa; forming a mask for selective growth on the epitaxial structure; growing a semiconductor region on an end surface of the device mesa by using the mask for selective growth, the semiconductor region including a side portion having a layer shape and a protruding wall portion; forming an ohmic electrode on a top surface of the device mesa; forming a resin layer on the device mesa and the semiconductor region; forming a resin mask having an opening on the ohmic electrode; forming an electric conductor connecting the ohmic electrode to an electrode pad, the electric conductor passing over the protruding wall portion while making contact with a surface of the resin mask; and removing the resin mask after forming the electric conductor.. .
11/20/14
20140342476
new patent Land grid array semiconductor device packages
A semiconductor device package includes a land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads on the same side of the interposer substrate as the at least one semiconductor die.
11/20/14
20140342474
new patent Temperature detecting apparatus, substrate processing apparatus and method of manufacturing semiconductor device
A temperature detecting apparatus is provided which is capable of suppressing disconnection of a thermocouple wire or positional deviation of a thermocouple junction portion caused by change over time. The temperature detecting apparatus includes: an insulation rod installed to extend in a vertical direction and including a through-hole in vertical direction; a thermocouple wire inserted in the through-hole of the insulation rod, the thermocouple wire including a thermocouple junction portion at an upper end thereof and an angled portion at a lower end of the insulation rod; and a buffer area installed below the insulation rod and configured to suppress a restriction of a horizontal portion of the angled portion upon heat expansion, wherein an upper portion of the thermocouple wire or a middle portion in the vertical direction are supported by the insulation rod..
11/20/14
20140341328
new patent Clock reproducing and timing method in a system having a plurality of devices
A system includes a memory controller and a plurality of semiconductor devices that are series-connected. Each of the devices has memory core for storing data.
11/20/14
20140341242
new patent Resin composition, semiconductor device using same, and method of manufacturing semiconductor device
According to the present invention, a resin composition having superior workability is provided. The paste-like resin composition of the present invention adheres a semiconductor element and a base material, and contains (a) a thermosetting resin and (b) metal particles.
11/20/14
20140340976
new patent Information processing system including semiconductor device having self-refresh mode
A method for controlling termination impedance of a data terminal in a dynamic random access memory device includes receiving a mode register set command to set an operation mode to a first mode, setting the operation mode in a mode register to the first mode, receiving a self-refresh entry command, entering self-refresh mode, activating a first input buffer connected to a termination impedance control terminal, and receiving an impedance control signal at the first buffer, wherein the termination impedance of the data terminal is set to a first impedance value if the termination impedance control signal has a first level and the termination impedance of the data terminal is set to a second impedance value if the termination impedance control signal has a second level.. .
11/20/14
20140340973
new patent Semiconductor device having pda function
A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal, generating a first mode register setting signal, delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal, receiving a data signal in synchronization with the second mode register setting signal, and writing the mode signal to the mode register only if the received data signal has a first logic level.. .
11/20/14
20140340953
new patent Semiconductor device
An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation.
11/20/14
20140340608
new patent Semiconductor device
A semiconductor device which includes an oxide semiconductor and in which formation of a parasitic channel due to a gate bt stress is suppressed is provided. Further, a semiconductor device including a transistor having excellent electrical characteristics is provided.
11/20/14
20140340607
new patent Semiconductor device, method for fabricating the semiconductor device and display device
This semiconductor device (100a) includes: a thin-film transistor (101); a gate line layer; an interlevel insulating layer (14) including a first insulating layer (12) which contacts at least with the surface of a drain electrode (11d); a first transparent conductive layer (15) on the interlevel insulating layer (14); a drain connected transparent conductive layer (15a) arranged on the interlevel insulating layer (14) and not electrically connected to the first transparent conductive layer (15); a dielectric layer (17) arranged on the first transparent conductive layer (15); and a second transparent conductive layer (19a) which is arranged over the dielectric layer (17) so as to overlap at least partially with the first transparent conductive layer (15) with the dielectric layer (17) interposed between them. The interlevel insulating layer (14) and the dielectric layer (17) have a first contact hole (ch1), in which a part of the surface of the drain electrode (11d) contacts with the drain connected transparent conductive layer (15a) and another part contacts with the second transparent conductive layer (19a)..
11/20/14
20140340134
new patent Semiconductor device
To reduce power consumption of a circuit (tedc) which detects timing errors in a main flip-flop by determining whether or not output data signals of the main flip-flop and a shadow flip-flop correspond. The tedc includes a power gating circuit (pgc) which performs power gating of the shadow ff and a reset circuit (rstc) which resets an output signal of the shadow ff.
11/20/14
20140340127
new patent Semiconductor device
A semiconductor device with short overhead time. The semiconductor device includes a first wiring supplied with a power supply potential, a second wiring, a switch for controlling electrical connection between the first wiring and the second wiring, a load electrically connected to the second wiring, a transistor whose source and drain are electrically connected to the second wiring, and a power management unit having functions of controlling the conduction state of the switch and controlling a gate potential of the transistor.
11/20/14
20140340116
new patent Programmable logic device and semiconductor device
A programmable logic device having low power consumption with operation speed maintained is provided. The programmable logic device includes a first circuit; a second circuit; a first transistor making electrical connection between the first circuit and the second circuit depending on a potential of a gate of the first transistor; a first switch configured to control supply of a signal to a first node; a second switch configured to control supply of the signal to a second node; a second transistor having a gate and one of a source and a drain that are electrically connected to the first node and having the other of the source and the drain that is electrically connected to the second node; and a capacitor that holds a potential of the signal supplied to the first node..
11/20/14
20140340113
new patent Through silicon via repair circuit of semiconductor device
Tsv repair circuit of a semiconductor device includes a first chip, a second chip, at least two tsv, at least two data path circuits and an output logic circuit. Each data path circuit comprises an input driving circuit, a tsv detection circuit, a memory device, a protection circuit and a power control circuit.
11/20/14
20140340108
new patent Test assembly
A test assembly adapted to test a semiconductor device is provided. The test assembly includes a main circuit board, a space transformer, a plurality of electrical connection elements, an intermediary stiffener, and a plurality of test probes.
11/20/14
20140340106
new patent Probe member for pogo pin
Provided is probe member for a pogo pin used for testing a semiconductor device, at least a portion of the probe member being inserted into a cylindrical body and supported by an elastic member and an upper end of the probe member contacting a terminal of the semiconductor device.. .
11/20/14
20140340105
new patent Test assembly
A test assembly adapted to test a semiconductor device is provided. The test assembly includes a main circuit board, an intermediate dielectric board, an intermediate circuit board, a plurality of intermediate conductive elements and a plurality of test probes.
11/20/14
20140339714
new patent Semiconductor device
A semiconductor device including a substrate and at least one alignment mark disposed on the substrate and having at least one hollow pattern. Therefore, the identification rate of the alignment mark can be high by the hollow pattern..
11/20/14
20140339713
new patent Semiconductor device manufacturing method and semiconductor device
A semiconductor device manufacturing method includes sealing a first surface of a semiconductor wafer with a resin, causing a resin-made warp suppression member to be adhered to a second surface on the opposite side of the first surface of the semiconductor wafer and causing the warp suppression member to shrink, measuring the amount of warp of the semiconductor wafer, and forming cuts in the warp suppression member in accordance with the amount of warp of the semiconductor wafer.. .
11/20/14
20140339712
new patent Semiconductor device comprising mold for top side and sidewall protection
Some implementations provide a semiconductor device that includes a substrate, several metal and dielectric layers coupled to the substrate, and a pad coupled to one of the several metal layers. The semiconductor device also includes a first metal layer coupled to the pad and an under bump metallization layer coupled to the first metal redistribution layer.
11/20/14
20140339711
new patent Semiconductor device, method of positioning semiconductor device, and positioning apparatus for semiconductor device
A semiconductor device includes: a semiconductor chip that has a first connection terminal for wiring connection; a substrate that has a second connection terminal for wiring connection, the second connection terminal being electrically connected to the first connection terminal; and a reflective surface that reflects light from the first connection terminal and the second connection terminal in a thickness direction of the substrate or the semiconductor chip.. .
11/20/14
20140339701
new patent Method of forming metal interconnections of semiconductor device
A method of forming a metal interconnection of semiconductor device is provided. The method includes forming a low-k dielectric layer including an opening; forming a barrier metal pattern conformally covering a bottom surface and an inner sidewall of the opening; forming a metal pattern exposing a part of the inner sidewall of the barrier metal pattern in the opening; forming a metal capping layer on the top surfaces of the metal pattern and the low-k dielectric layer using a selective chemical vapor deposition process, wherein the thickness of the metal capping layer on the metal pattern is greater than the thickness of the metal capping layer on the low-k dielectric layer; and forming a metal capping pattern covering the top surface of the metal pattern by planarizing the metal capping layer down to the top surface of the low-k dielectric layer..
11/20/14
20140339700
new patent Graphene-based metal diffusion barrier
Contacts for semiconductor devices are formed where a barrier layer comprising graphene is situated between a first layer comprising a conductor, and a second layer comprising a second conductor or a semiconductor. For example, a metal layer can be formed on a graphene layer residing on a semiconductor.
11/20/14
20140339698
new patent Semiconductor device with through-substrate via covered by a solder ball and related method of production
The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate.
11/20/14
20140339694
new patent Semiconductor devices having a glass substrate, and method for manufacturing thereof
A method for manufacturing semiconductor devices includes providing a stack having a semiconductor wafer and a glass substrate with openings and at least one trench attached to the semiconductor wafer. The semiconductor wafer includes a plurality of semiconductor devices.
11/20/14
20140339691
new patent Semiconductor device having a plurality of circuits arranged on a side of a semiconductor chip
A semiconductor device includes a base member and a first semiconductor chip mounted over the base member. The first semiconductor chip including a first circuit, a second circuit, and a third circuit arranged between the first circuit and the second circuit and a plurality of pads.
11/20/14
20140339687
new patent Power plane for multi-layered substrate
A semiconductor device includes a ground plane and a power plane that lie in spaced, parallel planes. The power plane includes a number of openings formed around its outer edge.
11/20/14
20140339685
new patent Glass composition for protecting semiconductor junction, method of manufacturing semiconductor device and semiconductor device
A glass composition for protecting a semiconductor junction contains at least sio2, b2o3, al2o3, zno, and at least two oxides of alkaline earth metal selected from the group consisting of cao, mgo and bao, and substantially contains none of pb, p, as, sb, li, na and k.. .
11/20/14
20140339683
new patent Semiconductor device and method of forming insulating layer around semiconductor die
A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier.
11/20/14
20140339682
new patent Semiconductor device and method for manufacturing semiconductor device
Provided are a semiconductor device in which abrasive grain marks are formed in a surface of a semiconductor substrate, a dopant diffusion region has a portion extending in a direction which forms an angle included in a range of −5° to +5° with a direction in which the abrasive grain marks extend, and the dopant diffusion region is formed by diffusing a dopant from a doping paste placed on one surface of the semiconductor substrate; and a method for manufacturing the semiconductor device.. .
11/20/14
20140339677
new patent Hybrid plasma-semiconductor transistors, logic devices and arrays
A hybrid plasma semiconductor device has a thin and flexible semiconductor base layer. An emitter region is diffused into the base layer forming a pn-junction.
11/20/14
20140339676
new patent Semiconductor device and method of forming the same
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate, the first region comprising a first n type material; a second region over the substrate and laterally adjacent to the first region, the second region comprising a first p type material; a third region disposed within the second region and laterally separated from the first region, the third region comprising a second n type material; a fourth region disposed atop the third region, the fourth region comprising a second p type material; a fifth region disposed within the first region and laterally separated from the second region, the fifth region comprising a third p type material; and a sixth region disposed atop the fifth region, the sixth region comprising a third n type material..
11/20/14
20140339675
new patent Polysilicon fuse, manufacturing method thereof, and semiconductor device including polysilicon fuse
A polysilicon fuse is disclosed that is capable of securing good insulation after being cut into small areas. A manufacturing method for the fuse and a small-size and highly-reliable semiconductor device including a polysilicon fuse also are disclosed.
11/20/14
20140339674
new patent Semiconductor device
A semiconductor device includes: a substrate; a lower wiring on the substrate; an inter-layer insulating film covering the lower wiring; first and second upper wirings on the inter-layer insulating film and separated from each other; and a semi-insulating protective film covering the first and second upper wirings, wherein the protective film is not provided in a region right above the lower wiring and between the first upper wiring and the second upper wiring.. .
11/20/14
20140339671
new patent Method to form stepped dielectric for field plate formation
A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform.
11/20/14
20140339670
new patent Semiconductor device with a thick bottom field plate trench having a single dielectric and angled sidewalls
Disclosed is a power device, such as a power mosfet device and a method for fabricating same. The device includes a field plate trench.
11/20/14
20140339669
new patent Semiconductor device with a field plate trench having a thick bottom dielectric
Disclosed is a power device, such as a power mosfet, and methods for fabricating same. The device includes a field plate trench.
11/20/14
20140339667
new patent Semiconductor device, manufacturing method thereof, and electronic apparatus
A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.. .
11/20/14
20140339652
new patent Semiconductor device with oxygen-containing metal gates
A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate.
11/20/14
20140339651
new patent Semiconductor device with a field plate double trench having a thick bottom dielectric
Disclosed is a power device, such as power mosfet, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the upper trench is wider than the lower trench.
11/20/14
20140339649
new patent Finfet type device using ldmos
The present invention is a finfet type semiconductor device using ldmos features. The device includes a first portion of a substrate doped with a second doping type and has a first trench, second trench, and first fin.
11/20/14
20140339645
new patent Methods of forming semiconductor devices with different insulation thicknesses on the same semiconductor substrate and the resulting devices
One method includes forming first and second devices by forming a first layer of gate insulation material having a first thickness for the first device, forming a layer of high-k insulation material having a second thickness that is less than the first thickness for the second device and forming first and second metal-containing gate electrode structures that contact the first layer of gate insulation material and the high-k insulation material. A device disclosed herein includes first and second semiconductor devices wherein the first gate structure comprises a layer of insulating material having a first portion of a first metal layer positioned on and in contact with the layer of insulating material and a second gate structure comprised of a layer of high-k insulation material and a second portion of the first metal layer positioned on and in contact with the layer of high-k insulation material..
11/20/14
20140339641
new patent Semiconductor device and fabrication method thereof
A semiconductor device includes a substrate, a first fin structure, an electrical contact structure and a gate structure. The first fin structure includes a horizontal fin structure extending along a first direction and a vertical fin structure extending along a second direction.
11/20/14
20140339637
new patent Method of forming semiconductor device
A semiconductor device may include a semiconductor substrate, a first conductive type well and a second conductive type drift region in the semiconductor substrate, the drift region including a first drift doping region and a second drift doping region, the second drift doping region vertically overlapping the well, and a first conductive type body region in the well, the body region being in contact with a side of the first drift doping region. The first drift doping region and the second doping region may include a first conductive type dopant and a second conductive type dopant, and an average density of the first conductive type dopant in the first drift doping region may be less than an average density of the first conductive type dopant in the second drift doping region..
11/20/14
20140339635
new patent Semiconductor device
According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type provided on part of the first semiconductor layer in each of a first region and a second region separated from each other. A first distance is a distance between both ends of the first insulating film in a direction connecting the fourth semiconductor layer and the sixth semiconductor layer.
11/20/14
20140339633
new patent Semiconductor device, integrated circuit and method of manufacturing a semiconductor device
A semiconductor device includes a transistor. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode adjacent to the body region.
11/20/14
20140339629
new patent Contact formation for ultra-scaled devices
Embodiments of the invention provide approaches for forming gate and source/drain (s/d) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a s/d contact formed over a trench-silicide (ts) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the ts layer.
11/20/14
20140339628
new patent Semiconductor device
A semiconductor device includes a fin-shaped silicon layer on a silicon substrate and a first insulating film around the fin-shaped silicon layer. A pillar-shaped silicon layer resides on the fin-shaped silicon layer.
11/20/14
20140339627
new patent Semiconductor device
A semiconductor device includes a pillar-shaped silicon layer and a first-conductivity-type diffusion layer in an upper portion of the pillar-shaped silicon layer. A sidewall having a laminated structure including an insulating film and polysilicon resides on an upper sidewall of the pillar-shaped silicon layer.
11/20/14
20140339619
new patent Semiconductor device
Solution: the semiconductor device 1, includes: a semiconductor substrate 10 of a p-type having a principal surface 10a; an element isolation insulating film 131 that partitions one end of an active region k1 embedded in the principal surface 10a; a gate electrode 311 embedded interposing a gate insulating film 30 in a gate trench gt1 provided on the principal surface 10a so as to pass through the active region k1; a semiconductor pillar p1 disposed between the gate trench gt1 and the element isolation insulating film 131; an upper diffusion layer 201 of an n-type disposed on an upper part of the semiconductor pillar p1; a lower diffusion layer 211 of an n-type disposed to span from a lower side of the gate trench gt1 to a lower side of the semiconductor pillar p1; and a side face diffusion layer 111 disposed between the element isolation insulating film 131 and the semiconductor pillar p1 and containing an impurity of a p-type having a concentration higher than an impurity concentration of the lower diffusion layer 211.. .
11/20/14
20140339613
new patent Semiconductor device and method of manufacturing same
In one embodiment, a semiconductor device includes a semiconductor substrate, and a gate insulator arranged on the semiconductor substrate. The device further includes a gate electrode including a semiconductor layer and a metal layer which are sequentially arranged on the gate insulator.
11/20/14
20140339609
new patent Transistor performance using a two-step damage anneal
A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device.
11/20/14
20140339604
new patent Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode
A semiconductor device includes a gate electrode structure of a transistor, the gate electrode structure being positioned above a semiconductor region and having a gate insulation layer that includes a high-k dielectric material, a metal-containing cap material positioned above the gate insulation layer, and a gate electrode material positioned above the metal-containing cap material. A bottom portion of the gate electrode structure has a first length and an upper portion of the gate electrode structure has a second length that is different than the first length, wherein the first length is approximately 50 nm or less.
11/20/14
20140339603
new patent Semiconductor device and method of manufacturing a semiconductor device
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate; a second region laterally adjacent to the first region; a third region disposed laterally adjacent to the second region on a side of the second region opposite the first region; a fourth region disposed within a portion of the first region proximate the second region; a fifth region disposed within a portion of the second region proximate the first region, wherein the fourth region and the fifth region are separated by a first isolation area; a sixth region disposed within a portion of the third region proximate the second region; and a seventh region disposed within the second region and below the fifth region..
11/20/14
20140339602
new patent Semiconductor device
In a trench-gate-type insulated gate bipolar transistor, a current will not flow down to a lower portion of a trench, a high electrical field at the lower portion of the trench is suppressed even if a high voltage is applied, such as at a time of turning off, an increase in on-state resistance and a decrease in breakdown resistance and withstand voltage are suppressed. In the semiconductor device, a plurality of trenches is disposed to reach a rear surface of a drift layer, and a collector layer is disposed at a tip end side in an extended direction of the trenches in a surface layer portion of the drift layer.
11/20/14
20140339600
new patent Semiconductor device
A trench gate mos structure is provided on one main surface of a semiconductor substrate which will be an n− drift region. An n shell region is provided in the n− drift region so that it contacts a surface of a p base region close to the n− drift region forming the trench gate mos structure.
11/20/14
20140339599
new patent Semiconductor device
A semiconductor device includes a first gate electrode that is provided on a first insulating film along one side wall of a first trench and is provided in a second trench, a shield electrode that is provided on a second insulating film along the other side wall of the first trench and is provided in a third trench, a gate runner that is an extended portion of the second trench, has a portion which is provided on the first gate electrode, and is connected to the first gate electrode, and an emitter polysilicon layer that is an extended portion of the third trench, has a portion which is provided on the shield electrode, and is connected to the shield electrode. The semiconductor device has improved turn-on characteristics with a slight increase in the number of process steps, while preventing increase in costs and reduction in yield..
11/20/14
20140339578
new patent Method for manufacturing semiconductor device
The present invention provides a manufacturing technique of a semiconductor device and a display device using a peeling process, in which a transfer process can be conducted with a good state in which a shape and property of an element before peeling are kept. Further, the present invention provides a manufacturing technique of more highly reliable semiconductor devices and display devices with high yield without complicating the apparatus and the process for manufacturing.
11/20/14
20140339569
new patent Semiconductor device
A semiconductor device formed on a silicon carbide substrate that has a front surface on which an electrode is provided and a back surface on which an electrode is provided includes a drain layer, a drift layer, a base layer, a gate electrode that is located in a trench that extends from the front surface into the drift layer and is insulated by an insulating film, a some layer, a buried layer that is provided between the drift layer and the base layer and is formed such that the depth from the front surface to an end thereof on the side of the drift layer is greater than the depth from the front surface to a distal end of the trench, and a first epitaxial layer that is provided between the buried layer and the base layer and has a higher impurity concentration than the buried layer.. .
11/20/14
20140339568
new patent Semiconductor device with substrate via hole and method to form the same
A process to form a substrate via hole is disclosed. The process includes steps of (1) forming a semiconductor layer on a substrate; (2) forming a gate and an auxiliary electrode simultaneously on a semiconductor layer; and (3) etching the substrate and the semiconductor layer from the back surface of the substrate to the auxiliary electrode to form a substrate via hole.
11/20/14
20140339566
new patent Semiconductor device and method of fabricating the same
Disclosed are a semiconductor device and a method of fabricating the same. The method includes forming a first gan layer, a sacrificial layer and a second gan layer on a gan substrate, wherein the sacrificial layer has a bandgap narrower than those of the gan layers; forming a groove penetrating the second gan layer and the sacrificial layer; growing gan-based semiconductor layers on the second gan layer to form a semiconductor stack; forming a support substrate on the semiconductor stack; and removing the gan substrate from the semiconductor stack by etching the sacrificial layer.
11/20/14
20140339560
new patent Semiconductor device
A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack.
11/20/14
20140339559
new patent Semiconductor device having test structure
A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures.
11/20/14
20140339557
new patent Semiconductor device
A transistor in a display device is expected to have higher withstand voltage, and it is an object to improve the reliability of a transistor which is driven by high voltage or large current. A semiconductor device includes a transistor in which buffer layers are provided between a semiconductor layer forming a channel formation region and source and drain electrode layers.
11/20/14
20140339556
new patent Semiconductor device
A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased..
11/20/14
20140339555
new patent Semiconductor device
Provided is a transistor which includes an oxide semiconductor film and has stable electrical characteristics. In the transistor, over an oxide film which can release oxygen by being heated, a first oxide semiconductor film which can suppress oxygen release at least from the oxide film is formed.
11/20/14
20140339553
new patent Semiconductor device and electronic device
To suppress variation of a signal in a semiconductor device. By suppressing the variation, formation of a stripe pattern in displaying an image on a semiconductor device can be suppressed, for example.
11/20/14
20140339552
new patent Semiconductor device and manufacturing method thereof
To provide a highly reliable semiconductor device including a transistor using an oxide semiconductor. After a source electrode layer and a drain electrode layer are formed, an island-like oxide semiconductor layer is formed in a gap between these electrode layers so that a side surface of the oxide semiconductor layer is covered with a wiring, whereby light is prevented from entering the oxide semiconductor layer through the side surface.
11/20/14
20140339551
new patent Semiconductor device
A nonvolatile memory is provided. A semiconductor device (a nonvolatile memory) has a circuit configuration similar to that of a general sram.
11/20/14
20140339549
new patent Semiconductor device and method for manufacturing the same
A first trench and a second trench are formed in an insulating layer, a transistor including an oxide semiconductor layer in the first trench is formed, and a capacitor is formed along the second trench. A first gate electrode is formed over the first trench, and a second gate electrode is formed under the first trench..
11/20/14
20140339548
new patent Semiconductor device
To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor device, an oxide semiconductor layer filling a groove is surrounded by insulating layers including an aluminum oxide film containing excess oxygen.
11/20/14
20140339547
new patent Semiconductor device and method for manufacturing the same
A transistor with stable electric characteristics is provided. A transistor with small variation in electrical characteristics is provided.
11/20/14
20140339546
new patent Semiconductor device
A structure is employed in which a first protective insulating layer; an oxide semiconductor layer over the first protective insulating layer; a source electrode and a drain electrode that are electrically connected to the oxide semiconductor layer; a gate insulating layer that is over the source electrode and the drain electrode and overlaps with the oxide semiconductor layer; a gate electrode that overlaps with the oxide semiconductor layer with the gate insulating layer provided therebetween; and a second protective insulating layer that covers the source electrode, the drain electrode, and the gate electrode are included. Furthermore, the first protective insulating layer and the second protective insulating layer each include an aluminum oxide film that includes an oxygen-excess region, and are in contact with each other in a region where the source electrode, the drain electrode, and the gate electrode are not provided..
11/20/14
20140339545
new patent Semiconductor device, method for manufacturing the same, and apparatus for manufacturing semiconductor device
To manufacture a semiconductor device using an oxide semiconductor with high reliability and less variation in electrical characteristics, objects are to provide a method for manufacturing a semiconductor device with which an oxide semiconductor film with a fairly uniform thickness is formed, a manufacturing apparatus, and a method for manufacturing a semiconductor device with the manufacturing apparatus. In order to form an oxide semiconductor film with a fairly uniform thickness with use of a sputtering apparatus, an oxide semiconductor film the thickness uniformity of which is less than ±3%, preferably less than or equal to ±2% is formed by using a manufacturing apparatus in which a deposition chamber is set to have a reduced pressure atmosphere, preferably, to have a high degree of vacuum and power is adjusted to be applied uniformly to the entire surface of a substrate during film deposition..
11/20/14
20140339544
new patent Semiconductor device
Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film.
11/20/14
20140339543
new patent Semiconductor device
A semiconductor device includes a dual-gate transistor including an oxide semiconductor film between a first gate electrode and a second gate electrode, a gate insulating film between the oxide semiconductor film and the second gate electrode, and a pair of electrodes in contact with the oxide semiconductor film. The semiconductor device further includes an insulating film over the gate insulating film, and a conductive film over the insulating film and connected to one of the pair of electrodes.
11/20/14
20140339542
new patent Semiconductor device
A semiconductor device includes a dual-gate transistor in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In the channel width direction of the transistor, a side surface of each of the first and second gate electrodes is on the outer side of a side surface of the oxide semiconductor film.
11/20/14
20140339541
new patent Semiconductor device
A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor.
11/20/14
20140339539
new patent Semiconductor device
A semiconductor device including a transistor having excellent electrical characteristics is provided. Alternatively, a semiconductor device having a high aperture ratio and including a capacitor capable of increasing capacitance is provided.
11/20/14
20140339538
new patent Semiconductor device
To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor device, an oxide semiconductor layer is surrounded by an insulating layer including an aluminum oxide film containing excess oxygen.
11/20/14
20140339536
new patent Tft with insert in passivation layer or etch stop layer
Embodiments disclosed herein generally relate to thin film transistors with one or more trenches to control the threshold voltage and off-current and methods of making the same. In one embodiment, a semiconductor device can include a substrate comprising a surface with a thin film transistor formed thereon, a first passivation layer formed over the thin film transistor, a trench formed within the first passivation layer and a second passivation layer formed over the first passivation layer and within the trench..
11/20/14
20140339501
new patent Low-resistivity p-type gasb quantum wells for low-power electronic devices
A semiconductor device including a heterostructure having at least one low-resistivity p-type gasb quantum well is provided. The heterostructure includes a layer of inwal1−was on a semi-insulating (100) inp substrate, where the inwal1−was is lattice matched to inp, followed by an alasxsb1−x buffer layer on the inwal1−was layer, an alasxsb1−x spacer layer on the buffer layer, a gasb quantum well layer on the spacer layer, an alasxsb1−x barrier layer on the quantum well layer, an inyal1−ysb layer on the barrier layer, and an inas cap.
11/20/14
20140339488
new patent Semiconductor device and method for fabricating the same, and microprocessor, processor, system, data storage system and memory system including the semiconductor device
A semiconductor device includes a first conductive layer; a second conductive layer; and a resistance variable element interposed between the first conductive layer and the second conductive layer and includes a doped first metal oxide layer and a second metal oxide layer. A density of oxygen vacancies of the second metal oxide layer is higher than that of the doped first metal oxide layer.
11/20/14
20140339313
new patent Semiconductor device and an identification tag
A semiconductor device includes a semiconductor substrate, a battery attached to the semiconductor substrate, and a sensor attached to the semiconductor substrate. The battery is electrically connected to the sensor and configured to supply the sensor with electrical power..


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