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Semiconductor Device patents



      
           
This page is updated frequently with new Semiconductor Device-related patent applications. Subscribe to the Semiconductor Device RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Device RSS RSS


Semiconductor device, antenna switch circuit, and radio communication apparatus

Semiconductor device, antenna switch circuit, and radio communication apparatus

Method of manufacturing semiconductor device, substrate processing apparatus and non-transitory computer-readable…

Method of manufacturing semiconductor device, substrate processing apparatus and non-transitory computer-readable…

Method of manufacturing semiconductor device, substrate processing apparatus and non-transitory computer-readable…

Semiconductor device and method for manufacturing the same

Date/App# patent app List of recent Semiconductor Device-related patents
11/13/14
20140337603
 Semiconductor device patent thumbnailSemiconductor device
An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix.
11/13/14
20140335800
 Semiconductor device, antenna switch circuit, and radio communication apparatus patent thumbnailSemiconductor device, antenna switch circuit, and radio communication apparatus
A semiconductor device includes: a laminated body including a channel layer that is configured of a compound semiconductor; and at least one gate electrode that is provided on a top surface side of the laminated body, wherein the laminated body includes a first low-resistance region that is provided on the top surface side of the laminated body, the first low-resistance region facing the at least one gate electrode, and a second low-resistance region that is provided externally of the first low resistance region on the top surface side of the laminated body, the second low-resistance region being continuous with the first low-resistance region.. .
11/13/14
20140335701
 Method of manufacturing semiconductor device, substrate processing apparatus and non-transitory computer-readable recording medium patent thumbnailMethod of manufacturing semiconductor device, substrate processing apparatus and non-transitory computer-readable recording medium
A thin film containing boron and a borazine ring structure is formed on a substrate by performing a cycle a predetermined number of times under a condition where the borazine ring structure is preserved in a borazine compound. The cycle includes: supplying a source gas containing boron and a halogen element to the substrate; and supplying a reactive gas including a borazine compound to the substrate..
11/13/14
20140335690
 Semiconductor device and method for manufacturing the same patent thumbnailSemiconductor device and method for manufacturing the same
A semiconductor device includes: a contact hole formed over a structure including a conductive pattern; a contact plug formed in the contact hole; a first metal silicide film surrounding the contact plug; and a second metal silicide film formed over the contact plug.. .
11/13/14
20140335687
 Method of making a conductive pillar bump with non-metal sidewall protection structure patent thumbnailMethod of making a conductive pillar bump with non-metal sidewall protection structure
A method of making a semiconductor device includes forming an under bump metallurgy (ubm) layer over a substrate, the ubm layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the ubm layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the ubm layer.
11/13/14
20140335684
 Manufacturing method and manufacturing apparatus of semiconductor device patent thumbnailManufacturing method and manufacturing apparatus of semiconductor device
A manufacturing method for a semiconductor device includes implanting dopants into a silicon carbide substrate, applying a carbon-containing material on at least one surface of the silicon carbide substrate, and heating the silicon carbide substrate having the carbon-containing material applied thereon to form a carbon layer on surfaces of the silicon carbide substrate. The heating is performed in a non-oxidizing atmosphere, and is followed by another heating step for activating the dopants..
11/13/14
20140335682
 Semiconductor device and manufacturing method thereof patent thumbnailSemiconductor device and manufacturing method thereof
A semiconductor device according to an embodiment includes a first-conductive-type semiconductor substrate; a first-conductive-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductive-type second semiconductor layer epitaxially formed on the first semiconductor layer; and a second-conductive-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer. The semiconductor device also includes a recess formed in the third semiconductor layer, and at least a corner portion of a side face and a bottom surface is located in the second semiconductor layer.
11/13/14
20140335674
 Manufacturing method of semiconductor device patent thumbnailManufacturing method of semiconductor device
A manufacturing method of a semiconductor device is provided. The method includes at least the following steps.
11/13/14
20140335673
 Methods of manufacturing finfet semiconductor devices using sacrificial gate patterns and selective oxidization of a fin patent thumbnailMethods of manufacturing finfet semiconductor devices using sacrificial gate patterns and selective oxidization of a fin
A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.. .
11/13/14
20140335670
 Semiconductor device including finfet and diode having reduced defects in depletion region patent thumbnailSemiconductor device including finfet and diode having reduced defects in depletion region
A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin.
11/13/14
20140335668
Contact landing pads for a semiconductor device and methods of making same
A method of forming a conductive contact landing pad and a transistor includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, and performing an etching process to remove the layer of gate insulation material formed on the second active region so as to thereby expose the second active region. The method further includes performing a common process operation to form a gate electrode structure above the layer of gate insulation material on the first active region for the transistor and the conductive contact landing pad that is conductively coupled to the second active region, and forming a contact to the conductive contact landing pad..
11/13/14
20140335667
Semiconductor device
A semiconductor device includes an active area having a source and a gate. A gate metal contact is deposited above and forms an electrical contact with the gate and a source metal contact is deposited above and forms an electrical contact with the source.
11/13/14
20140335659
Method of manufacturing semiconductor device
A semiconductor device includes a first semiconductor chip including a first surface, a second surface and a first terminal arranged on the first surface, a second semiconductor chip including a first surface, a second surface and a second terminal arranged on the first surface of the second semiconductor chip, a support substrate including a first surface bonded to the second surfaces of the first semiconductor chip and the second semiconductor chip, and an isolation groove formed on the first surface of the support substrate. The isolation includes a pair of side surfaces continuously extending from opposing side surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the isolation groove is formed into the support substrate to extend from the first surface of the support substrate.
11/13/14
20140335658
Semiconductor device and method of land grid array packaging with bussing lines
A semiconductor device and method of making a semiconductor device is described. An embedded die panel comprising a plurality of semiconductor die separated by saw streets is provided.
11/13/14
20140335654
Method and apparatus for semiconductor device fabrication using a reconstituted wafer
Method and apparatus for semiconductor device fabrication using a reconstituted wafer is described. In one embodiment, diced semiconductor chips are placed within openings on a frame.
11/13/14
20140335652
Semiconductor device and method for manufacturing the same
A miniaturized semiconductor device including a transistor in which a channel formation region is formed using an oxide semiconductor film and variation in electric characteristics due to a short-channel effect is suppressed is provided. In addition, a semiconductor device whose on-state current is improved is provided.
11/13/14
20140335634
Mold release film and method of process for producing a semiconductor device using the same
A mold release film, which is adapted to be disposed on the cavity surface of a mold to form a resin-encapsulated portion by encapsulating a semiconductor element of a semiconductor device with a curable encapsulation resin, has a tensile modulus of elasticity of from 10 to 24 mpa at 132° c. As measured in accordance with jis k 7127, and a peak peel resistance of at most 0.8 n/25 mm..
11/13/14
20140335632
Manufacturing method of semiconductor device, and semiconductor device
Provided is a semiconductor device that suppresses the occurrence of defects due to photocorrosion. A method for manufacturing the semiconductor device includes the steps of: forming an insulating layer with a concave portion over a substrate; forming a conductive film over the insulating film and the inside of the concave portion; polishing and removing the conductive film positioned over the insulating layer; and cleaning the insulating layer in a light-shielded state.
11/13/14
20140335453
Method for producing resist composition
Provided by the present invention is a method for producing a resist composition, especially a silicon-containing resist underlayer film composition, with fewer film defects, the composition used in immersion exposure, double patterning, development by an organic solvent, and so forth. Specifically, provided is a method for producing a resist composition to be used for manufacturing a semiconductor device, wherein the resist composition is filtered using a filter which filters through 5 mg or less of an eluate per unit surface area (m2) in an extraction using an organic solvent..
11/13/14
20140334507
Mount for semiconductor devices using conformable conductive layers, and method
A mount for semiconductor laser devices comprises thermally conductive anode and cathode blocks on either side of a semiconductor laser device such as a laser diode. Interposed between at least the anode block and the anode of the semiconductor laser device is a sheet of conformable electrically conductive material with high thermal conductivity such as pyrolytic highly-oriented graphite.
11/13/14
20140334234
Semiconductor device including memory cell having charge accumulation layer
A semiconductor device includes mos transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The mos transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively.
11/13/14
20140334229
Semiconductor device with floating gate and electrically floating body
Techniques for providing floating body memory devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor device comprising a floating gate, a control gate disposed over the floating gate, a body region that is electrically floating, wherein the body region is configured so that material forming the body region is contained under at least one lateral boundary of the floating gate, and a source region and a drain region adjacent the body region..
11/13/14
20140334218
Semiconductor device
Provided is a memory device in which memory capacity per unit area is increased without making the manufacturing process complicated. The memory device includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines.
11/13/14
20140334212
Semiconductor device and power converter
A semiconductor device of this invention (an igbt with a built-in diode) includes: an n−-type drift layer 1; a p-type channel region 2 that is arranged in contact with the surface side of this n−-type drift layer 1; a gate electrode 5 that is provided in a trench t provided so as to penetrate this p-type channel region 2 and reach to the n−-type drift layer 1 through a gate insulating film 3; an n-type source region 4 that is provided so as to contact the trench t on the surface side of the p-type channel region 2; a high-concentration n-type region 6 that is arranged in contact with the back side of the n−-type drift layer 1; and a high-concentration p-type region 7 that is arranged in contact with the back side of this high-concentration n-type region 6; in which a junction of the high-concentration n-type region 6 and the high-concentration p-type region 7 is a tunnel junction. According to this semiconductor device, it is possible to form the igbt and the diode on a single chip.
11/13/14
20140334102
Power conversion apparatus
In general, according to an embodiment, a power conversion apparatus includes a first inverter, second inverter and a cooler. The first inverter includes a plurality of semiconductor devices connected together in parallel per phase.
11/13/14
20140333932
Spectroscopic sensor device and electronic equipment
A spectroscopic sensor that applies lights in a wavelength band containing plural wavelengths to an object and spectroscopically separates reflected lights or transmitted lights from the object using plural light band-pass filters that transmit the respective specific wavelengths and plural photosensor parts to which corresponding transmitted lights are input based on output results of independent photosensors. The spectroscopic sensor may be integrated in a semiconductor device or module by integration using a semiconductor process and downsizing may be realized..
11/13/14
20140333505
Semiconductor package having integrated antenna pad
An apparatus for a semiconductor-package includes a semiconductor device having a radio frequency (rf) input or output, an antenna pad, and a package structured to house the semiconductor device and the antenna pad. The antenna pad may be coupled to the radio frequency (rf) input or output, and the antenna pad is structured to reduce the inductance of the package.
11/13/14
20140333461
Semiconductor device having analog-to-digital converter with gain-dependent dithering and communication apparatus
A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a delta-sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the delta-sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the delta-sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes..
11/13/14
20140333365
Semiconductor device
An object is to prevent malfunction of a power device. In a semiconductor device for driving a power device for power supply, a buffer circuit and a level-shift circuit are configured by transistors having the same conductivity type.
11/13/14
20140333363
Semiconductor device
There is provided a semiconductor device having: a latch circuit having a plurality of data holding nodes; a first capacitance element connected to the first data holding node included in the plurality of data holding nodes; and a first switch element provided between the first data holding node and the first capacitance element.. .
11/13/14
20140333341
Testing fuse configurations in semiconductor devices
Methods, systems, and apparatus for testing semiconductor devices.. .
11/13/14
20140332986
Semiconductor device and method of forming adhesive material to secure semiconductor die to carrier in wlcsp
A semiconductor device is made by providing a temporary carrier and providing a semiconductor die having a plurality of bumps formed on its active surface. An adhesive material is deposited as a plurality of islands or bumps on the carrier or active surface of the semiconductor die.
11/13/14
20140332984
Adhesive composition, process for producing the same, adhesive film using the same, substrate for mounting semiconductor and semiconductor device
Disclosed is an adhesive composition which includes (a) an epoxy resin, (b) a curing agent and (c) a polymer compound incompatible with said epoxy resin, and further optionally includes (d) a filler and/or (e) a curing accelerator. Also disclosed are a process for producing an adhesive composition, including mixing (a) the epoxy resin and (b) the curing agent with (d) the filler, followed by mixing the resultant mixture with (c) the polymer compound incompatible with the epoxy resin; an adhesive film including the above-mentioned adhesive composition formed into a film; a substrate for mounting a semiconductor including a wiring board and the above-mentioned adhesive film disposed thereon on its side where chips are to be mounted; and a semiconductor device which includes the above-mentioned adhesive film or the substrate for mounting a semiconductor..
11/13/14
20140332977
Semiconductor device
A semiconductor device includes a metal pad formed over a semiconductor substrate; a dummy metal pad spaced apart from the metal pad by an open region; and a polymide isoindro quirazorindione (piq) layer formed to cover the open region and to define a pad open region by exposing a center part of the metal pad. The semiconductor device forms an additional open region at a region spaced apart from an edge part of the pad open region, preventing short-circuiting between the metal pad and the adjacent circuit line which might be caused by a crack generated at the edge of the pad open region when a probe is connected to the metal pad, and further preventing a defective semiconductor device from being generated..
11/13/14
20140332970
Semiconductor device and method forming patterns with spaced pads in trim region
In a semiconductor device, parallel first and second conductive lines having a unit width extend from a memory cell region into a connection region. A trim region in the connection region includes pads respectively connected to the first and second conductive lines but are separated by a width much greater than the unit width..
11/13/14
20140332959
Method of manufacturing semiconductor device and semiconductor device
A method of manufacturing a semiconductor device includes: a groove portion formation step of forming a groove portion in a base; a barrier layer formation step of forming a barrier layer that covers at least an inner wall surface of the groove portion; a seed layer formation step of forming a seed layer that covers the barrier layer; and a burial step of burying a conductive material in an inside region of the seed layer, wherein the seed layer is made of cu, and the conductive material is made of cu.. .
11/13/14
20140332954
Semiconductor device
Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5).
11/13/14
20140332951
Semiconductor device
A semiconductor device includes an insulating substrate with a conductive pattern including an insulating substrate, a conductive pattern formed on a front surface of the insulating substrate, and a rear heat-sink formed on a back surface of the insulating substrate; a semiconductor chip joined on the conductive pattern through joining material, and leading terminals; and a mold resin exposing a surface of the rear heat-sink and end portions of the leading terminals, and sealing a front surface of the insulating substrate with the conductive pattern, a back surface of the insulating substrate with the conductive pattern, the semiconductor chip, the rear heat-sink excluding the exposed surface thereof, and the leading terminals excluding the end portions thereof. Each of side surfaces of the conductive pattern and the rear heat-sink is formed with a recessed groove, and the recessed grooves are filled with the mold resin..
11/13/14
20140332950
Semiconductor device
A semiconductor device includes a cooling portion, which is made of ceramic or resin and includes a mounting surface, a metal circuit board, which is mounted on the mounting surface of the cooling portion and includes an element mounting surface, and a semiconductor element mounted on the element mounting surface of the circuit board. At least a part of the circuit board, which corresponds to the element mounting surface, is covered with resin with respect to the cooling portion..
11/13/14
20140332944
Resin-encapsulated semiconductor device and its manufacturing method
A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device (100) comprises a semiconductor chip (1) including a silicon substrate, a die pad (10) to which the semiconductor chip (1) is secured through a first solder layer (2), a resin-encapsulating layer (30) encapsulating the semiconductor chip (1), and lead terminals (21) electrically connected to the semiconductor chip (1) and including inner lead portion (21b) covered with the resin-encapsulating layer (30).
11/13/14
20140332942
Method of manufacturing semiconductor device and semiconductor device
Reliability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes a step of arranging a plurality of semiconductor chips next to each other over a chip mounting surface of a die pad.
11/13/14
20140332941
System, method and apparatus for leadless surface mounted semiconductor package
A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface.
11/13/14
20140332937
Workpiece with semiconductor chips, semiconductor device and method for producing a workpiece with semiconductor chips
A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer..
11/13/14
20140332934
Substrates for semiconductor devices
A method of manufacturing a composite substrate for a semiconductor device, the method comprising: selecting a substrate wafer comprising: a first layer of single crystal material suitable for epitaxial growth of a compound semiconductor thereon and having a thickness of 100 μm or less;a second layer having a thickness of no less than 0.5 μm and formed of a material having a lower thermal expansion coefficient than the first layer of single crystal material and/or is formed of a material which has a higher fracture strength than that of the first layer of single crystal material; and a third layer forming a handling wafer on which the first and second layers are disposed, wherein the substrate wafer has an aspect ratio, defined by a ratio of thickness to width, of no less than 0.25/100; growing a first polycrystalline cvd diamond layer on the first layer of single crystal material using a chemical vapour deposition technique to form a composite comprising the substrate wafer bonded to the polycrystalline diamond layer via the first layer of single crystal material, wherein during growth of the first polycrystalline cvd diamond layer a temperature difference at a growth surface between an edge and a centre point thereof is maintained to be no more than 80° c.; and removing the second and third layers of the substrate wafer to form a composite substrate comprising the polycrystalline diamond layer directly bonded to the first layer of single crystal material.. .
11/13/14
20140332921
Semiconductor devices having a trench isolation layer and methods of fabricating the same
Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating insulation layer filling the micro trenches and a lower region of the trench that are surrounded by the liner insulation layer, and a second isolating insulation layer filling the trench on the first isolating insulation layer.
11/13/14
20140332917
Magnetic-field sensing device
Apparatus and associated methods may relate to magneto-resistive sensing devices (mrsds). In accordance with an exemplary embodiment, an mrsd comprises an underlying semiconductor device and a magneto-resistive sensor.
11/13/14
20140332907
Semiconductor device and method for manufacturing the same
A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device uses an aluminum alloy, rather than aluminum, for a metal gate.
11/13/14
20140332905
Method of fabricating semiconductor device
A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the mask as an etch mask to thereby form a gate electrode, wherein the oxide of the gate dielectric layer and the material of the at least one conductive layer are selected such that a byproduct of the etching of the at least one conductive layer, formed on the mask during the etching of the at least one conductive layer, comprises an oxide having a higher etch rate with respect to an etchant than the oxide of the gate dielectric layer.. .
11/13/14
20140332902
Novel method to tune narrow width effect with raised s/d structure
A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (vt) of a field effect transistor (fet) with raised source/drain (s/d) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle.
11/13/14
20140332901
Semiconductor device with notched gate
A semiconductor device includes a semiconductor substrate, a body region disposed in the semiconductor substrate and having a first conductivity type, a source region disposed in the semiconductor substrate adjacent the body region and having a second conductivity type, a drain region disposed in the semiconductor substrate, having the second conductivity type, and spaced from the source region to define a conduction path, a gate structure supported by the semiconductor substrate, configured to control formation of a channel in the conduction path during operation, and having a side adjacent the source region that comprises a notch, the notch defining a notch area, and a notch region disposed in the semiconductor substrate in the notch area and having the first conductivity type.. .
11/13/14
20140332897
Low noise and high performance lsi device
In semiconductor devices in which both nmos devices and pmos devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., nmos and/or pmos devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc.
11/13/14
20140332896
Semiconductor device and method for forming the same
A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a peripheral region including the first region, the second region, and a third region; a second active region defined by the device isolation film contained in the semiconductor substrate of the third region; a buried metal layer buried in the recess; a first conductive layer formed over the semiconductor substrate of the first region; and a second conductive layer formed over the semiconductor substrate of the second region, wherein the first conductive layer or the second conductive layer is formed over the semiconductor substrate of the third region. A three-dimensional dual gate is formed in a peripheral region, such that performance or throughput of transistors is maximized even in the peripheral region..
11/13/14
20140332888
Semiconductor device including finfet structures with varied epitaxial regions, related method and design structure
A semiconductor device including a substrate; a finfet disposed on the substrate, the finfet including: a set of epitaxial regions disposed in a source/drain region on a set of fins, the set of epitaxial regions including: a first epitaxial region on a first inner surface of a first outer fin, the first epitaxial region having a first thickness defined as one of: a distance from the first inner surface to an edge of the epitaxial region in the case of a non-merged state of adjacent inner epitaxial regions of adjacent fins, and half of a distance from the first inner surface to an opposing inner surface of an adjacent fin in a merged state of adjacent inner epitaxial regions of adjacent fins, and a second epitaxial region with a second thickness disposed on a first outer surface of the first outer fin. The second thickness is thinner than the first thickness..
11/13/14
20140332886
Single poly plate low on resistance extended drain metal oxide semiconductor device
A semiconductor device, in particular, an extended drain metal oxide semiconductor (ed-mos) device, defined by a doped shallow drain implant in a drift region. For example, an extend drain n-channel metal oxide semiconductor (ed-nmos) device is defined by an n doped shallow drain (ndd) implant in the drift region.
11/13/14
20140332883
Semiconductor device having dummy gate and gate
A fin-shaped active region is defined on a substrate. First and second gate electrodes crossing the fin-shaped active region are arranged.
11/13/14
20140332881
Semiconductor device
A semiconductor device includes a transistor array, including first transistors and second transistors. Gate electrodes of the first transistors are disposed in first trenches in a first main surface of a semiconductor substrate, and gate electrodes of the second transistors are disposed in second trenches in the first main surface.
11/13/14
20140332879
Power semiconductor device with reduced on-resistance and increased breakdown voltage
In one implementation, a power semiconductor device includes an active region and a termination region. A depletion trench finger extends from the active region and ends in the termination region.
11/13/14
20140332878
Semiconductor device and a manufacturing method of the same
In a non-insulated dc-dc converter having a circuit in which a power mos•fet high-side switch and a power mos•fet low-side switch are connected in series, the power mos•fet low-side switch and a schottky barrier diode to be connected in parallel with the power mos•fet low-side switch are formed within one semiconductor chip. The formation region sdr of the schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power mos•fet low-side switch are disposed.
11/13/14
20140332877
Semiconductor device
A switching component includes a control element and an integrated circuit. The integrated circuit includes a first transistor element and a second transistor element electrically connected in parallel to the first transistor element.
11/13/14
20140332874
Semiconductor devices
A semiconductor device includes a substrate, a first poly-silicon pattern on the substrate, a metal pattern on the first poly-silicon pattern, and an interface layer between the first poly-silicon pattern and the metal pattern. The interface layer may include at least one selected from the group of a metal-silicon oxynitride layer, a metal-silicon oxide layer, and a metal-silicon nitride layer..
11/13/14
20140332873
Semiconductor device
A semiconductor device includes at least one channel layer, insulating layers stacked on top of one another while surrounding the at least one channel layer, first grooves and second grooves alternately interposed between the insulating layers, wherein the first groves have a greater width than the second grooves having a second width, and conductive layers formed in the first grooves.. .
11/13/14
20140332872
Semiconductor device and method for forming the same
A semiconductor device includes a semiconductor substrate including a pad region and a peripheral region, a first buffer layer formed to include a capacitor over the semiconductor substrate in the pad region, a second buffer layer formed to include a first contact pad over the first buffer layer, and a third buffer layer formed to include a second contact pad over the first contact pad. The semiconductor device, by additionally forming a buffer layer at a lower part in the pad region, reduces a stress caused by wire bonding.
11/13/14
20140332871
Semiconductor device having jumper pattern and blocking pattern
A semiconductor device includes a substrate having a transistor area, a gate structure disposed on the transistor area of the substrate, a first interlayer insulating layer covering the gate structure, a blocking pattern disposed on the first interlayer insulating layer, and a jumper pattern disposed on the blocking pattern. The jumper pattern includes jumper contact plugs vertically penetrating the first interlayer insulating layer to be in contact with the substrate exposed at both sides of the gate structure, and a jumper section configured to electrically connect the jumper contact plugs..
11/13/14
20140332870
Spin transistor, and semiconductor device, memory device, microprocessor, processor, system, data storage system and memory system including the spin transistor
A spin transistor includes a source electrode, including a magnetic material, is disposed in a substrate. A drain electrode, including a magnetic material is disposed in the substrate and is spaced apart from the source electrode in a first direction.
11/13/14
20140332868
Semiconductor device and manufacturing method thereof
A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region.
11/13/14
20140332867
Semiconductor device and manufacturing method thereof
It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires.
11/13/14
20140332866
Semiconductor device
A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a mosfet, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.. .
11/13/14
20140332865
Semiconductor device
A semiconductor device includes a substrate having an edge, a semiconductor layer provided on a substrate, an electrode pad provided on the semiconductor layer, an inorganic insulating film having a first opening through which an upper surface of the electrode pad is exposed, and a resin film provided on the inorganic insulating film, the resin film having a second opening and a third opening separated from each other, where the upper surface of the electrode pad is exposed through the second opening, where the third opening is located between the second opening and the edge of the substrate, and where a bottom of the third opening is constituted by the resin film or the inorganic insulating film.. .
11/13/14
20140332863
Semiconductor device and method of manufacturing the same
Provided are a semiconductor device and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an active fin on a substrate; oxidizing a portion of the active fin to form an insulating pattern between the active fin and the substrate; forming a first gate pattern on the substrate, wherein the first gate pattern crosses the active fin; exposing the substrate on both sides of the first gate pattern; and forming source/drain regions on the exposed substrate..
11/13/14
20140332858
Junction gate field-effect transistor (jfet), semiconductor device having jfet and method of manufacturing
A junction gate field-effect transistor (jfet) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions.
11/13/14
20140332857
Junction gate field-effect transistor (jfet), semiconductor device and method of manufacturing
A junction gate field-effect transistor (jfet) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions.
11/13/14
20140332855
Reduced short channel effect of iii-v field effect transistor via oxidizing aluminum-rich underlayer
In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of iii-v semiconductor substrate. The iii-v semiconductor substrate including a iii-v base substrate layer, an aluminum containing iii-v semiconductor layer that is present on the iii-v base substrate layer, and a iii-v channel layer.
11/13/14
20140332854
Stress release structures for metal electrodes of semiconductor devices
This invention teaches stress release metal electrodes for gate, drain and source in a field effect transistor and stress release metal electrodes for emitter, base and collector in a bipolar transistor. Due to the large difference in the thermal expansion coefficients between semiconductor materials and metal electrodes, significant strain and stresses can be induced in the devices during the fabrication and operation.
11/13/14
20140332852
Non-planar semiconductor device having group iii-v material active region with multi-dielectric gate stack
Non-planar semiconductor devices having group iii-v material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate.
11/13/14
20140332851
Reduced short channel effect of iii-v field effect transistor via oxidizing aluminum-rich underlayer
In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of iii-v semiconductor substrate. The iii-v semiconductor substrate including a iii-v base substrate layer, an aluminum containing iii-v semiconductor layer that is present on the iii-v base substrate layer, and a iii-v channel layer.
11/13/14
20140332849
Semiconductor device and method of manufacturing the same
A semiconductor device includes a silicon substrate, an initial buffer layer disposed on the silicon substrate and including aluminum nitride (aln), and a semiconductor device layer disposed on the initial buffer layer and including a semiconductor compound. There is no sin between the initial buffer layer and the silicon substrate, and a silicon lattice of the silicon substrate directly contacts a lattice of the initial buffer layer..
11/13/14
20140332821
Semiconductor device, light emitting device using the same, and light emitting device package including the same
A semiconductor device includes a silicon substrate, an initial buffer layer disposed on the silicon substrate, a transition layer disposed on the initial buffer layer, and a device structure disposed on the transition layer. The transition layer includes at least one of alxga1-xn (where 0<x<1) layers provided on the initial buffer layer and an inserted buffer layer provided at least one of between the alxga1-xn layers, at a lower end portion of the transition layer, or at an upper end portion of the transition layer..
11/13/14
20140332816
Semiconductor device
A semiconductor device includes a first insulating film formed on a memory cell region of the semiconductor substrate, a first polysilicon layer formed on the first insulating film, and memory cell transistors formed on the first polysilicon layer, each including a charge storage layer, an inter-electrode insulating film and a control gate electrode. The semiconductor device further includes a laminated structure formed on a peripheral circuit region of the semiconductor substrate that includes a second insulating film, a second polysilicon layer, a third insulating film, a third polysilicon layer, a fourth insulating film formed from the same material as a material of the inter-electrode insulating film, and a first electrode formed from the same material as a material of the control gate electrode.
11/13/14
20140332815
Semiconductor device including finfet and diode having reduced defects in depletion region
A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin.
11/13/14
20140332813
Semiconductor device
A device comprises a semiconductor chip including an edge elongated in a first direction. A plurality of first pads is formed on the semiconductor chip.
11/13/14
20140332811
Semiconductor device with bond and probe pads
A semiconductor die has an active face with an arrangement of i/o pads around its edges. The i/o pads include bond pads and probe pads.
11/13/14
20140332809
Semiconductor device
With a combination of a transistor including an oxide semiconductor material and a transistor including a semiconductor material other than an oxide semiconductor, a semiconductor device with a novel structure in which data can be retained for a long time and does not have a limitation on the number of writing can be obtained. When a connection electrode for connecting the transistor including a semiconductor material other than an oxide semiconductor to the transistor including an oxide semiconductor material is smaller than an electrode of the transistor including a semiconductor material other than an oxide semiconductor that is connected to the connection electrode, the semiconductor device with a novel structure can be highly integrated and the storage capacity per unit area can be increased..
11/13/14
20140332808
Semiconductor device and method for manufacturing the same
A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. In a semiconductor device including a bottom-gate transistor in which an insulating layer functioning as a channel protective film is provided over an oxide semiconductor film, elements contained in an etching gas can be prevented from remaining as impurities on a surface of the oxide semiconductor film by performing impurity-removing process after formation of an insulating layer provided over and in contact with the oxide semiconductor film and/or formation of source and drain electrode layers.
11/13/14
20140332807
Semiconductor device and manufacturing method thereof
When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer or the source and drain electrode layers by an etching step, a step of removing a residue remaining by the etching step and existing on a surface of the gate electrode layer or a surface of the oxide semiconductor film and in the vicinity of the surface is performed. The surface density of the residue on the surface of the oxide semiconductor film or the gate electrode layer can be 1×1013 atoms/cm2 or lower..
11/13/14
20140332806
Semiconductor device
One object is to provide a new semiconductor device whose standby power is sufficiently reduced. The semiconductor device includes a first power supply terminal, a second power supply terminal, a switching transistor using an oxide semiconductor material and an integrated circuit.
11/13/14
20140332805
Semiconductor device
A semiconductor device having a novel structure is provided. The semiconductor device includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor.
11/13/14
20140332804
Analog circuit and semiconductor device
An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated.
11/13/14
20140332802
Semiconductor device
In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period..
11/13/14
20140332801
Semiconductor device and method for manufacturing the same
A bottom-gate transistor with a short channel length and a method for manufacturing the transistor are provided. A bottom-gate transistor with a short channel length in which portions of a source electrode and a drain electrode which are proximate to a channel formation region are thinner than other portions thereof was devised.
11/13/14
20140332800
Semiconductor device and manufacturing method thereof
To provide a semiconductor device having a structure with which the device can be easily manufactured even if the size is decreased and which can suppress a decrease in electrical characteristics caused by the decrease in the size, and a manufacturing method thereof. A source electrode layer and a drain electrode layer are formed on an upper surface of an oxide semiconductor layer.
11/13/14
20140332799
Semiconductor device
A semiconductor device includes a substrate, a gate electrode, an insulating layer, a source electrode, a drain electrode, a semiconductor channel layer, a first passivation layer and a second passivation layer. The gate is formed on the substrate.
11/13/14
20140332749
Semiconductor device and method of manufacturing same
A semiconductor device includes: a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening.. .
11/13/14
20140332730
Diketopyrrolopyrrole polymers for use in organic semiconductor devices
The present invention relates to polymers (i), or (ii), and their use as organic semiconductor in organic devices, especially in organic photovoltaics (solar cells) and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties.
11/13/14
20140332500
Dc current switching apparatus, electronic device, and method for switching an associated dc circuit
Exemplary embodiments are directed to a direct current switching apparatus including at least a first mechanical switching device which is suitable to be positioned along an operating path of an associated dc circuit and includes a fixed contact and a corresponding movable contact which can be actuated between a closed position and an open position along the operating path, wherein an electric arc can ignite between the contacts under separation. The switching apparatus includes an electronic circuit having a semiconductor device which is suitable to be positioned along a secondary path and connected in parallel with the first mechanical switching device.
11/13/14
20140332404
Process for producing high-purity tin
High purity tin and tin alloy are provided in which the respective contents of u and th are 5 ppb or less, the respective contents of pb and bi are 1 ppm or less, and the purity is 5n or higher, provided that this excludes the gas components of o, c, n, h, s and p. A cast ingot of the tin or alloy has an α ray count of 0.001 cph/cm2 or less.


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