FreshPatents.com Logo
Enter keywords:  

Track companies' patents here: Public Companies RSS Feeds | RSS Feed Home Page
Popular terms

[SEARCH]

Follow us on Twitter
twitter icon@FreshPatents

Web & Computing
Cloud Computing
Ecommerce
Search patents
Smartphone patents
Social Media patents
Video patents
Website patents
Web Server
Android patents
Copyright patents
Database patents
Programming patents
Wearable Computing
Webcam patents

Web Companies
Apple patents
Google patents
Adobe patents
Ebay patents
Oracle patents
Yahoo patents

[SEARCH]

Semiconductor Device patents



      
           
This page is updated frequently with new Semiconductor Device-related patent applications. Subscribe to the Semiconductor Device RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Device RSS RSS


Non-volatile semiconductor device

Toshiba

Non-volatile semiconductor device

Semiconductor device and method of manufacturing a semiconductor device

Transphorm Japan

Semiconductor device and method of manufacturing a semiconductor device

Semiconductor device and method of manufacturing a semiconductor device

Intermolecular

Reduction of forming voltage in semiconductor devices

Date/App# patent app List of recent Semiconductor Device-related patents
05/21/15
20150143324
 Semiconductor device design methods and conductive bump pattern enhancement methods patent thumbnailnew patent Semiconductor device design methods and conductive bump pattern enhancement methods
semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150143312
 Method of designing patterns of semiconductor devices patent thumbnailnew patent Method of designing patterns of semiconductor devices
A method of designing patterns of semiconductor devices includes forming a plurality of tiles having patterns on a wafer, measuring the patterns of the plurality of tiles, analyzing the measurements of the patterns and determining a tile having such a size that the measurements linearly vary according to a design size and pattern density, and modifying the pattern density of the determined tile.. .
Samsung Electronics Co., Ltd.
05/21/15
20150143311
 Method, system and computer program product for designing semiconductor device patent thumbnailnew patent Method, system and computer program product for designing semiconductor device
A method of designing a semiconductor device is performed by at least one processor. In the method, a first environment temperature for a first substrate is determined based on an operational temperature of a second substrate, the first and second substrates stacked one upon another in the semiconductor device.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150143203
 Semiconductor device and  operating the same patent thumbnailnew patent Semiconductor device and operating the same
A semiconductor device includes a memory device suitable for outputting health monitoring data including information on a threshold voltage distribution, and outputting read data read from memory cells included in the memory device, and a controller suitable for receiving a predetermined quantity of the read data from the memory device based on the health monitoring data, and performing a decoding operation for an error correction by using the received read data.. .
Sk Hynix Inc.
05/21/15
20150140835
 Substrate processing apparatus,  manufacturing semiconductor device, and recording medium patent thumbnailnew patent Substrate processing apparatus, manufacturing semiconductor device, and recording medium
A substrate processing apparatus is disclosed. The substrate processing apparatus includes a process chamber configured to accommodate a substrate; a gas supply unit configured to supply a process gas into the process chamber; a lid member configured to block an end portion opening of the process chamber; an end portion heating unit installed around a side wall of an end portion of the process chamber; and a thermal conductor installed on a surface of the lid member in an inner side of the process chamber, and configured to be heated by the end portion heating unit..
Hitachi Kokusai Electric Inc.
05/21/15
20150140817
 Apparatuses facilitating fluid flow into via holes, vents, and other openings communicating with surfaces of substrates of semiconductor device components patent thumbnailnew patent Apparatuses facilitating fluid flow into via holes, vents, and other openings communicating with surfaces of substrates of semiconductor device components
A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate includes pressurizing fluid so as to cause the fluid to flow into the at least one recess or the at least one aperture. The fluid may be pressurized by generating a pressure differential across the substrate, which causes the fluid to flow into or through the at least one aperture or recess.
Micron Technology, Inc.
05/21/15
20150140811
 Spacer-damage-free etching patent thumbnailnew patent Spacer-damage-free etching
A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150140808
 Semiconductor device having buried bit lines and  fabricating the same patent thumbnailnew patent Semiconductor device having buried bit lines and fabricating the same
A semiconductor device includes body lines, formed substantially perpendicular to a substrate, and having recessed sidewalls, buried bit lines, buried in the recessed sidewalls, and including a metal silicide, and a barrier layer interposed between each of the buried bit lines and the body lines corresponding thereto, and containing germanium.. .
Sk Hynix Inc.
05/21/15
20150140807
 Vias in porous substrates patent thumbnailnew patent Vias in porous substrates
A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material.
Tessera, Inc.
05/21/15
20150140804
 Semiconductor device and  manufacturing the same patent thumbnailnew patent Semiconductor device and manufacturing the same
A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes adjacent storage node contact plugs having different heights, and lower-electrode bowing profiles having different heights, such that a spatial margin between the lower electrodes is assured and a bridge fail is prevented, resulting in improved device operation characteristics.
Sk Hynix Inc.
05/21/15
20150140802
new patent

Semiconductor device and process for producing semiconductor device


A semiconductor device includes: a substrate in which a product region and scribe regions are defined; a 1st insulation film formed above the substrate; a metal film in the 1st insulation film, disposed within the scribe regions in such a manner as to surround the product region; a 2nd insulation film formed on the 1st insulation film and the metal film; a 1st groove disposed more inside than the metal film in such a manner as to surround the product region, and reaching from a top surface of the 2nd insulation film to a position deeper than a top surface of the metal film; and a 2nd groove disposed more outside than the metal film in such a manner as to surround the metal film, and reaching from the top surface of the 2nd insulation film to a position deeper than the top surface of the metal film.. .
Fujitsu Semiconductor Limited
05/21/15
20150140800
new patent

Method of fabricating semiconductor device


A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided.
United Microelectronics Corp.
05/21/15
20150140799
new patent

Asymmetric spacers


A semiconductor device having asymmetric spacers and steps for forming the same are disclosed. The spacers have difference capacitances, with the spacer having a higher capacitance formed over a source region of the device and the spacer having a lower capacitance formed over a drain region of the device.
International Business Machines Corporation
05/21/15
20150140796
new patent

Formation of contact/via hole with self-alignment


In a method for manufacturing a semiconductor device, a substrate is provided, and a dielectric layer is formed to cover the substrate. A recess portion is formed in the dielectric layer.
Taiwan Semiconductor Manufacturing Co., Ltd.
05/21/15
20150140791
new patent

Apparatus for producing metal chloride gas and producing metal chloride gas, and hydride vapor phase epitaxy, nitride semiconductor wafer, nitride semiconductor device, wafer for nitride semiconductor light emitting diode, manufacturing nitride semiconductor freestanidng substrate and nitride semiconductor crystal


There is provided an apparatus for producing metal chloride gas, comprising: a source vessel configured to store a metal source; a gas supply port configured to supply chlorine-containing gas into the source vessel; a gas exhaust port configured to discharge metal chloride-containing gas containing metal chloride gas produced by a reaction between the chlorine-containing gas and the metal source, to outside of the source vessel; and a partition plate configured to form a gas passage continued to the gas exhaust port from the gas supply port by dividing a space in an upper part of the metal source in the source vessel, wherein the gas passage is formed in one route from the gas supply port to the gas exhaust port, with a horizontal passage width of the gas passage set to 5 cm or less, with bent portions provided on the gas passage.. .
Hitachi Metals, Ltd.
05/21/15
20150140788
new patent

Apparatus and producing group iii nitride semiconductor device and producing semiconductor wafer


The production apparatus includes a shower head electrode, a susceptor for supporting a growth substrate, a first gas supply pipe, and a second gas supply pipe. The first gas supply pipe has at least one first gas exhaust outlet and supplies an organometallic gas containing group iii metal as a first gas, and the second gas supply pipe supplies a gas containing nitrogen gas as the second gas.
National University Corporation Nagoya University
05/21/15
20150140785
new patent

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device include preparing an initial substrate including an edge region and a central region in which circuit patterns are formed, forming a reforming region in the edge region of the initial substrate, grinding the initial substrate to form a substrate, and cutting the substrate to form a semiconductor chip including each of the circuit patterns. A crystal structure of the reforming region is different from that of the initial substrate..
Samsung Electronics Co., Ltd.
05/21/15
20150140783
new patent

Wafer dicing press and method and semiconductor wafer dicing system including the same


In a wafer dicing press for reducing time and cost for wafer dicing and for evenly applying a dicing pressure to a whole wafer, a wafer dicing press includes a support unit supporting a first side of a wafer; and a pressurization device applying a pressure, by dispersing the pressure, to a second side of the wafer so that a laser-scribed layer of the wafer operates as a division starting point. Accordingly, the wafer dicing press reduces laser radiation and pressure-application times for dividing a wafer into semiconductor devices.
05/21/15
20150140781
new patent

Semiconductor isolation structure and manufacture


A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.. .
Micron Technology, Inc.
05/21/15
20150140777
new patent

Methods of selectively doping chalcogenide materials and methods of forming semiconductor devices


Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide.
Micron Technology, Inc.
05/21/15
20150140774
new patent

Method of fabricating semiconductor device


A method of fabricating a semiconductor device comprises forming a first etch stop layer over a first dielectric layer. The method also comprises forming a first trench in the first etch stop layer and the first dielectric layer.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150140771
new patent

Method for fabricating a bipolar transistor having self-aligned emitter contact


A method of producing a semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, the portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a t-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connection region, wherein the base connection region, aside from a seeding layer adjacent the substrate or a metallization layer adjacent a base contact, consists of a semiconductor material which differs in its chemical composition from the semiconductor material of the collector, the base and the emitter and in which the majority charge carriers of the first conductivity type have greater mobility compared thereto.. .
Ihp Gmbh - Innovations For High Performance Microelectronics/leibniz-institut Fur Innovative M
05/21/15
20150140768
new patent

Method of manufacturing semiconductor device


A performance of a semiconductor device is improved. A gate electrode is formed on an soi substrate via a gate insulating film, and a laminated film including an insulating film il2 and an insulating film il3 on the insulating film il2 is formed on the soi substrate so as to cover the gate electrode, and then, a sidewall spacer formed of the laminated film is formed on a side wall of the gate electrode by etching back the laminated film.
Renesas Electronics Corporation
05/21/15
20150140765
new patent

Method of fabricating a gate dielectric layer


A method of making a semiconductor device, the method includes forming an active region in a substrate. The method further includes forming a first gate structure over the active region, where the forming the first gate structure includes forming a first interfacial layer.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150140764
new patent

Single poly plate low on resistance extended drain metal oxide semiconductor device


A semiconductor device, in particular, an extended drain metal oxide semiconductor (ed-mos) device, defined by a doped shallow drain implant in a drift region. For example, an extend drain n-channel metal oxide semiconductor (ed-nmos) device is defined by an n doped shallow drain (ndd) implant in the drift region.
Macronix International Co., Ltd.
05/21/15
20150140763
new patent

Contact structure of semiconductor device


The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ild) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer..
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150140762
new patent

Finfet with merge-free fins


A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions..
International Business Machines Corporation
05/21/15
20150140761
new patent

Device isolation in finfet cmos


Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage.
Renesas Electronics Corporation
05/21/15
20150140757
new patent

Methods of forming semiconductor devices including an embedded stressor, and related apparatuses


Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming preliminary trenches adjacent opposing sides of an active region.
Samsung Electronics Co., Ltd.
05/21/15
20150140755
new patent

Method for producing a semiconductor device with surrounding gate transistor


A method for producing a semiconductor device includes a first step of forming a fin-shaped silicon layer on a silicon substrate using a first resist and forming a first insulating film therearound; and a second step of forming a second insulating film around the fin-shaped silicon layer and etching the second insulating film so as to be left on a side wall of the fin-shaped silicon layer, depositing a third insulating film on the first and second insulating films and the fin-shaped silicon layer, depositing a polysilicon thereon, planarizing a surface thereof, and etching back the polysilicon to expose the third insulating film, forming a second resist, etching the second and third insulating films and then etching the fin-shaped silicon layer and the polysilicon, and removing the second insulating film to form a pillar-shaped silicon layer and a dummy gate formed of the polysilicon.. .
Unisantis Electronics Singapore Pte. Ltd.
05/21/15
20150140754
new patent

Semiconductor device, manufacturing the same, and power module


A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.. .
Rohm Co., Ltd.
05/21/15
20150140749
new patent

Semiconductor device having reduced-damage active region and manufacturing the same


A semiconductor device according to example embodiments may include a substrate having an nmos area and a pmos area, isolation regions and well regions formed in the substrate, gate patterns formed on the substrate between the isolation regions, source/drain regions formed in the substrate between the gate patterns and the isolation regions, source/drain silicide regions formed in the source/drain regions, a tensile stress layer formed on the nmos area, and a compressive stress layer formed on the pmos area, wherein the tensile stress layer and compressive stress layer may overlap at a boundary region of the nmos area and the pmos area. The semiconductor devices according to example embodiments and methods of manufacturing the same may increase the stress effect on the active region while reducing or preventing surface damage to the active region..
Samsung Electronics Co., Ltd.
05/21/15
20150140747
new patent

Semiconductor device including transistor and manufacturing the same


A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface..
Samsung Electronics Co., Ltd.
05/21/15
20150140740
new patent

Method of fabrication, device structure and submount comprising diamond on metal substrate for thermal dissipation


A method of fabrication, a device structure and a submount comprising high thermal conductivity (htc) diamond on a htc metal substrate, for thermal dissipation, are disclosed. The surface roughness of the diamond layer is controlled by depositing diamond on a sacrificial substrate, such as a polished silicon wafer, having a specific surface roughness.
Advanced Diamond Technologies, Inc.
05/21/15
20150140739
new patent

Discrete semiconductor device package and manufacturing method


Disclosed is a discrete semiconductor device package (100) comprising a semiconductor die (110) having a first surface and a second surface opposite said first surface carrying a contact (112); a conductive body (120) on said contact; an encapsulation material (130) laterally encapsulating said conductive body; and a capping member (140, 610) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap (150) may be provided over the first surface.
Nxp B.v.
05/21/15
20150140738
new patent

Circuit connecting material and semiconductor device manufacturing method using same


Provided are a circuit connecting material able to provide good bonding with an opposing electrode, and a semiconductor device manufacturing method using the same. The present invention uses a circuit connecting material, in which a first adhesive layer to be adhered to the semiconductor chip side, and a second adhesive layer having a lowest melting viscosity attainment temperature higher than that of the first adhesive layer are laminated.
Dexerials Corporation
05/21/15
20150140736
new patent

Semiconductor device and forming wire bondable fan-out ewlb package


A semiconductor device has a first semiconductor die and a first encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and first encapsulant.
Stats Chippac, Ltd.
05/21/15
20150140734
new patent

Semiconductor device


To provide a highly reliable semiconductor device which includes a transistor including an oxide semiconductor, in a semiconductor device including a staggered transistor having a bottom-gate structure provided over a glass substrate, a gate insulating film in which a first gate insulating film and a second gate insulating film, whose compositions are different from each other, are stacked in this order is provided over a gate electrode layer. Alternatively, in a staggered transistor having a bottom-gate structure, a protective insulating film is provided between a glass substrate and a gate electrode layer.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150140733
new patent

Method for manufacturing semiconductor device


To provide a semiconductor device including an oxide semiconductor which is capable of having stable electric characteristics and achieving high reliability, by a dehydration or dehydrogenation treatment performed on a base insulating layer provided in contact with an oxide semiconductor layer, the water and hydrogen contents of the base insulating layer can be decreased, and by an oxygen doping treatment subsequently performed, oxygen which can be eliminated together with the water and hydrogen is supplied to the base insulating layer. By formation of the oxide semiconductor layer in contact with the base insulating layer whose water and hydrogen contents are decreased and whose oxygen content is increased, oxygen can be supplied to the oxide semiconductor layer while entry of the water and hydrogen into the oxide semiconductor layer is suppressed..
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150140732
new patent

Method for manufacturing semiconductor device


It is an object to drive a semiconductor device at high speed or to improve the reliability of the semiconductor device. In a method for manufacturing the semiconductor device, in which a gate electrode is formed over a substrate with an insulating property, a gate insulating film is formed over the gate electrode, and an oxide semiconductor film is formed over the gate insulating film, the gate insulating film is formed by deposition treatment using high-density plasma.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150140731
new patent

Method for manufacturing semiconductor device


To improve productivity of a transistor that includes an oxide semiconductor and has good electrical characteristics. In a top-gate transistor including a gate insulating film and a gate electrode over an oxide semiconductor film, a metal film is formed over the oxide semiconductor film, oxygen is added to the metal film to form a metal oxide film, and the metal oxide film is used as a gate insulating film.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150140730
new patent

Oxide semiconductor film, semiconductor device, and manufacturing semiconductor device


A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used. In a transistor using an oxide semiconductor film for an active layer, a microvoid is provided in a source region and a drain region adjacent to a channel region.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150140726
new patent

Method for manufacturing semiconductor device


A transparent conductive substrate (1) in which a transparent conductive film (12) is placed on a light-transmissive base plate (11) is brought into a reaction chamber of a plasma apparatus without being rinsed (step (a)) and the transparent conductive film (12) is treated with plasma using a ch4 gas and an h2 gas (step (b)). After step (b), semiconductor devices are deposited on the transparent conductive film (12) in series (steps (c) and (d)) and a semiconductor device (10) is manufactured (step (e))..
Sharp Kabushiki Kaisha
05/21/15
20150140713
new patent

Peeling apparatus and manufacturing apparatus of semiconductor device


To eliminate electric discharge when an element formation layer including a semiconductor element is peeled from a substrate used for manufacturing the semiconductor element, a substrate over which an element formation layer and a peeling layer are formed and a film are made to go through a gap between pressurization rollers. The film is attached to the element formation layer between the pressurization rollers, bent along a curved surface of the pressurization roller on a side of the pressurization rollers, and collected.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150140711
new patent

Method of separating a wafer of semiconductor devices


A method according to embodiments of the invention includes providing a wafer comprising a semiconductor structure grown on a growth substrate. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region.
Koninklijke Philips N.v.
05/21/15
20150140699
new patent

Methods of forming oxide semiconductor devices and methods of manufacturing display devices having oxide semiconductor devices


A method of forming an oxide semiconductor device may be provided. In the method, a substrate comprising a first major surface and a second major surface that faces away from the first major surface may be provided.
Industry-academic Cooperation Foundation, Yonsei University
05/21/15
20150140695
new patent

Method and system for determining overlap process windows in semiconductors by inspection techniques


The formation of overlap areas in sophisticated semiconductor devices is a critical aspect which may not be efficiently evaluated on the basis of conventional measurement and design strategies. For this reason, the present disclosure provides measurement techniques and systems in which overlying device patterns are transformed into the same material layer, thereby forming a combined pattern which is accessible by well-established defect inspection techniques.
Globalfoundries Inc.
05/21/15
20150140692
new patent

Advanced process control controlling width of spacer and dummy sidewall in semiconductor device


An advanced process control (apc) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer.. .
Taiwan Semiconductor Manufacturing Co., Ltd.
05/21/15
20150139261
new patent

Semiconductor device having a semiconductor dbr layer


A semiconductor device includes a silicon substrate, alight-emitting function layer made of nitride semiconductor, and at least one multilayer film in which two to four lamination pairs are laminated, the lamination pair being a laminated body of a first semiconductor layer made of alxga1-xn and a second semiconductor layer made of alyga1-yn, the multilayer film being arranged between the silicon substrate and the light-emitting function layer, wherein in the lamination pair that is the closest to the light-emitting function layer in the multilayer film, an al composition x is equal to or larger than an al composition y, in the other lamination pair, the al composition x is larger than the al composition y.. .
Sanken Electric Co., Ltd.
05/21/15
20150138885
new patent

Non-volatile semiconductor storage device, and semiconductor device


A non-volatile semiconductor storage device includes a memory cell array divided into blocks, each of which is a erasable unit, the blocks, the blocks including a first block which is determined to be a bad block and a second block which is determined to be a partial bad block, a storage unit configured to store address information of the first block and the second block, and a block decoder including a latch section which is configured to control selection and non-selection of the blocks, and to release data held by the latch section based on the stored address information of the second block.. .
Kabushiki Kaisha Toshiba
05/21/15
20150138883
new patent

Non-volatile semiconductor device


A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop that includes an erase operation and a verifying operation. The control circuit increases an erasing voltage in accordance with the number of times the erasing loop is repeated..
Kabushiki Kaisha Toshiba
05/21/15
20150138862
new patent

Three-dimensional semiconductor devices and fabricating methods thereof


A three-dimensional (3d) semiconductor memory device includes a cmos circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the cmos circuit structure. The memory structure overlaps a first circuit region of the cmos circuit structure and does not overlap a second circuit region of the cmos circuit structure, and the plurality of column blocks are contained within the first circuit region of the cmos circuit structure..
05/21/15
20150138735
new patent

Semiconductor memory device


A semiconductor memory device is included. The semiconductor device includes a semiconductor memory device, comprising: a first substrate including a first semiconductor device mounted on the first substrate and a first connection terminal disposed at an edge of the first substrate; a second substrate including a second semiconductor device mounted on the second substrate and a second connection terminal at an edge of the second substrate; and an interface connector including a first socket portion configured to receive the first connection terminal and a second socket portion configured to receive the second connection terminal.
Samsung Electronics Co., Ltd.
05/21/15
20150138733
new patent

Semiconductor device


Each of semiconductor module includes a semiconductor chip, a case surrounding the semiconductor chip, and a main electrode connected to the semiconductor chip and led out to an upper surface of case. A connecting electrode is connected and fixed to the main electrodes of the adjacent semiconductor modules.
Mitsubishi Electric Corporation
05/21/15
20150138732
new patent

Semiconductor device


A semiconductor device includes: a first output unit configured to output a first phase; a second output unit configured to output a second phase different from the first phase, the second output unit being disposed to be stacked on the first output unit; and a controller configured to control the output units.. .
Rohm Co., Ltd.
05/21/15
20150138682
new patent

Switching circuit protector


A switching circuit protector switches a semiconductor device (11) provided in a switching circuit connecting a power supply (vb) to a load (rl), from a pwm drive state to a dc drive state when an estimated temperature of a cable of the switching circuit estimated by a temperature estimator (22) exceeds a threshold temperature (tth), in the state where the semiconductor device (11) is controlled to operate in the pwm drive state to drive the load (rl). Therefore, when an overcurrent is caused in the cable, the estimated temperature exceeds the threshold temperature (tth) so as to break the semiconductor device (11).
Yazaki Corporation
05/21/15
20150138680
new patent

Semiconductor device


A first overcurrent detection unit detects whether a drain-source voltage of an output transistor is greater than or equal to a first reference value and outputs a first detection signal. A second overcurrent detection unit detects whether an output current passing through the output transistor is greater than or equal to a second reference value and outputs a second detection signal.
Renesas Electronics Corporation
05/21/15
20150138049
new patent

Semiconductor device and display device utilizing the same


A source-drain voltage of one of two transistors connected in series becomes quite small in a set operation (write signal), thus the set operation is performed to the other transistor. In an output operation, two transistors operate as a multi-gate transistor, therefore, a current value can be small in the output operation.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150137843
new patent

Signal transmission circuit device, semiconductor device, inspecting semiconductor device, signal transmission device, and motor drive apparatus using signal transmission device


Disclosed is a signal transmission circuit device (200) including a feedback signal transmission unit (210) that feeds back a control output signal (sout) as a feedback signal (sf) to an input side circuit (200a). A logical comparison circuit (212) detects “mismatch” between input and output by performing logical comparison between a control input signal (sin) and the feedback signal (sf).
Rohm Co., Ltd.
05/21/15
20150137838
new patent

Automated test system with edge steering


A semiconductor device-under-test (dut) may be tested by an automated test system that processes test programs specifying a number of edges per tester cycle that may be greater than the number of edges the tester is capable of generating. The test system may include circuitry that reduces the number of edges in each cycle of a test program based on data specifying operation of the tester in that cycle and/or a prior cycle.
Teradyne, Inc.
05/21/15
20150137388
new patent

Semiconductor devices


A semiconductor device includes a first low-k dielectric layer structure including at least one first low-k dielectric layer sequentially stacked on a substrate, a via structure extending through at least a portion of the substrate and the first low-k dielectric layer structure, and a first blocking layer pattern structure spaced apart from the via structure in the first low-k dielectric layer structure. The first blocking layer pattern structure surrounds a sidewall of the first blocking layer structure..
05/21/15
20150137386
new patent

Semiconductor device


There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another.
Ps4 Luxco S.a.r.l.
05/21/15
20150137384
new patent

Semicondutor device with through-silicon via-less deep wells


Methods and systems for a semiconductor device with through-silicon via-less deep wells are disclosed and may include forming a mask pattern on a silicon carrier, etching wells in the silicon carrier, and forming metal contacts in the etched wells, wherein the metal contacts comprise a plurality of deposited metal layers. Redistribution layers may be formed on a subset of the contacts and a dielectric layer may be formed on the silicon carrier and formed redistribution layers.
Amkor Technology, Inc.
05/21/15
20150137378
new patent

Semiconductor device having voids and forming same


A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150137367
new patent

Method for forming transparent electrode and semiconductor device manufactured using same


Provided are a method for forming a transparent electrode and a semiconductor device where the transparent electrode is formed by using the method. The method for forming a transparent electrode includes: forming a transparent electrode by using a transparent material of which resistance state is to be changed from a high resistance state into a low resistance state according to an applied electric field; and performing a forming process of changing the resistance state of the transparent electrode into the low resistance state by applying a voltage to the transparent electrode, so that the transparent electrode has conductivity.
05/21/15
20150137365
new patent

Semiconductor device assembly with through-package interconnect and associated systems, devices and methods


Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface.
Micron Technology, Inc.
05/21/15
20150137363
new patent

Semiconductor device and semiconductor package


A semiconductor device includes a substrate, a sealing portion, a controller, a semiconductor chip, and a plurality of differential signal balls. The substrate has a first surface and a second surface positioned on a side opposite to the first surface.
Kabushiki Kaisha Toshiba
05/21/15
20150137359
new patent

Method for forming through silicon via with wafer backside protection


Semiconductor devices with through silicon vias (tsvs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a tsv in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the tsv using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the tsv..
Globalfoundries Singapore Pte. Ltd.
05/21/15
20150137358
new patent

Semiconductor device and semiconductor device production method


A semiconductor device according to the present invention includes: a combination object; and a chip having a front surface opposed to a front surface of the combination object. The chip includes: a multi-level wiring structure provided in the front surface of the chip; a connection electrode provided in the multi-level wiring structure and electrically connected to the combination object; an alignment mark set provided in the multi-level wiring structure and electrically isolated from the connection electrode; and an electrically conductive film provided at a higher level than the alignment mark set in association with the multi-level wiring structure to cover the alignment mark set and electrically isolated from the connection electrode..
Rohm Co., Ltd.
05/21/15
20150137357
new patent

Semiconductor device and semiconductor device production method


An inventive semiconductor device includes: a first semiconductor chip; a second semiconductor chip having a front surface opposed to a front surface of the first semiconductor chip; a first electrode region including a first electrode provided between the first semiconductor chip and the second semiconductor chip to electrically connect the first semiconductor chip to the second semiconductor chip; and a juncture portion provided between the first semiconductor chip and the second semiconductor chip as surrounding the first electrode region to connect the first semiconductor chip to the second semiconductor chip.. .
Rohm Co., Ltd.
05/21/15
20150137355
new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a first substrate including a surface, and a pad array on the surface of the substrate, wherein the pad array comprises a first type pad and a second type pad located on a same level. The semiconductor device further includes a conductive bump connecting either the first type pad or the second type pad to a second substrate and a via connected a conductive feature at a different level to the first type pad and the via located within a projection area of the first type pad and directly contacting the first type pad.
Taiwan Semiconductor Manufacturing Company Ltd.
05/21/15
20150137352
new patent

Mechanisms for forming post-passivation interconnect structure


Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.
05/21/15
20150137351
new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a die, a conductive post disposed adjacent to the die, and a molding surrounding the conductive post and the die, the molding includes a protruded portion protruded from a sidewall of the conductive post and disposed on a top surface of the conductive post. Further, a method of manufacturing a semiconductor device includes disposing a die, disposing a conductive post adjacent to the die, disposing a molding over the conductive post and the die, removing some portions of the molding from a top of the molding, and forming a recess of the molding above a top surface of the conductive post..
Taiwan Semiconductor Manufacturing Company Ltd.
05/21/15
20150137350
new patent

Semiconductor device and fabricating method thereof


A semiconductor structure includes an oval-shaped pad and a dielectric layer. The oval-shaped pad is on a substrate and includes a major axis corresponding to the largest distance of the oval-shaped pad.
Taiwan Semiconductor Manufacturing Company Ltd.
05/21/15
20150137349
new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (nsmd) pad and a solder mask defined (smd) pad, and the nsmd pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads..
Taiwan Semiconductor Manufacturing Company Ltd.
05/21/15
20150137347
new patent

Adhesive composition and semiconductor device using same


An adhesive composition comprising silver particles containing silver atoms and zinc particles containing metallic zinc, wherein the silver atom content is 90 mass % or greater and the zinc atom content is from 0.01 mass % to 0.6 mass %, with respect to the total transition metal atoms in the solid portion of the adhesive composition.. .
Hitachi Chemical Company, Ltd.
05/21/15
20150137344
new patent

Semiconductor device and manufacturing same


A semiconductor device has a circuit board including an insulation layer, a wiring layer formed on one surface of the insulation layer, and a buffer layer formed on the other surface of the insulation layer, a semiconductor element bonded to the wiring layer, a radiator member bonded to the buffer layer of the circuit board, and a resin member to seal the semiconductor element and an entire surface of the circuit board including an outer peripheral surface of the buffer layer in the circuit board. A method for manufacturing the semiconductor device includes bonding the buffer layer of the circuit board to the radiator member, bonding the semiconductor element to the wiring layer of the circuit board, and sealing the semiconductor element and an entire surface of the circuit board including an outer peripheral surface of the buffer layer in the circuit board with resin after the two bonding steps..
Kabushiki Kaisha Toyota Jidoshokki
05/21/15
20150137336
new patent

Semiconductor device, manufacturing the same, in-millimeter-wave dielectric transmission device, manufacturing the same, and in-millimeter-wave dielectric transmission system


A millimeter-wave dielectric transmission device. The millimeter-wave dielectric transmission device includes a semiconductor chip provided on one interposer substrate and capable of millimeter-wave dielectric transmission, an antenna structure connected to the semiconductor chip, two semiconductor packages including a molded resin configured to cover the semiconductor chip and the antenna structure, and a dielectric transmission path provided between the two semiconductor packages to transmit a millimeter wave signal.
Sony Corporation
05/21/15
20150137334
new patent

Semiconductor device and forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die tsv


A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity.
Stats Chippac, Ltd.
05/21/15
20150137327
new patent

Semiconductor device and fabrication method thereof


The invention provides a semiconductor device. A buried layer is formed in a substrate.
Vanguard International Semiconductor Corporation
05/21/15
20150137326
new patent

Semiconductor devices having through-electrodes and methods for fabricating the same


A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer..
05/21/15
20150137325
new patent

Semiconductor device having metal patterns and piezoelectric patterns


Provided is a semiconductor device. The semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an inter-layer insulating layer disposed on a second surface of the substrate, and a piezoelectric pattern formed between the metal pattern and the passivation layer on the first surface of the substrate.
Samsung Electronics Co., Ltd.
05/21/15
20150137322
new patent

Semiconductor device and forming wlcsp using wafer sections containing multiple die


A semiconductor wafer contains semiconductor die separated by saw streets. The semiconductor wafer is singulated through a portion of the saw streets to form wafer sections each having multiple semiconductor die per wafer section attached by uncut saw streets.
Stats Chippac, Ltd.
05/21/15
20150137320
new patent

Semiconductor device and fabricating the same


A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region.
Samsung Electronics Co., Ltd.
05/21/15
20150137319
new patent

Iii nitride semiconductor substrate, epitaxial substrate, and semiconductor device


In a semiconductor device 100, it is possible to prevent c from piling up at a boundary face between an epitaxial layer 22 and a group iii nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of s and 2 at % to 20 at % of oxide in terms of o in a surface layer 12. By thus preventing c from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group iii nitride semiconductor substrate 10.
Sumitomo Electric Industies, Ltd.
05/21/15
20150137316
new patent

Semiconductor device including a resistor and the formation thereof


A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure.
Globalfoundries Inc.
05/21/15
20150137314
new patent

Semiconductor device and semiconductor module


The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.. .
Rohm Co., Ltd.
05/21/15
20150137309
new patent

Methods of fabricating isolation regions of semiconductor devices and structures thereof


Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece.
Infineon Technologies Ag
05/21/15
20150137306
new patent

Semiconductor device and manufacturing the same


An n type diffusion layer in which a high-side circuit region is disposed is formed from a surface of a p type epitaxial layer covering a surface of a p type semiconductor substrate to reach the surface of the semiconductor substrate. An n type high breakdown voltage isolation region is formed with a prescribed width to surround high-side circuit region.
Mitsubishi Electric Corporation
05/21/15
20150137291
new patent

Magnetic memory cells and methods of formation


Methods of forming magnetic memory cells are disclosed. Magnetic and non-magnetic materials are formed into a primal precursor structure in an initial stress state of essentially no strain, compressive strain, or tensile strain.
Micron Technology, Inc.
05/21/15
20150137282
new patent

Flow sensor, manufacturing flow sensor and flow sensor module


A flow sensor structure seals the surface of an electric control circuit and part of a semiconductor device via a manufacturing method that prevents occurrence of flash or chip crack when clamping the semiconductor device via a mold. The flow sensor structure includes a semiconductor device having an air flow sensing unit and a diaphragm, and a board or lead frame having an electric control circuit for controlling the semiconductor device, wherein a surface of the electric control circuit and part of a surface of the semiconductor device is covered with resin while having the air flow sensing unit portion exposed.
Hitachi Automotive Systems, Ltd.
05/21/15
20150137279
new patent

Multi-die sensor device


A semiconductor device includes a lead frame having a flag and leads that surround the flag. The leads include a dummy lead that has first and second wire bonding areas.
05/21/15
20150137278
new patent

Semiconductor package with gel filled cavity


A semiconductor device package is assembled using a jig that alters the shape of gel material disposed in a cavity in the package. In one embodiment, a jig having a concave bottom surface is inserted onto uncured gel material disposed within a cavity in a housing of the package to change a top surface of the gel from having a concave shape to a convex shape.
05/21/15
20150137271
new patent

Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices


One method disclosed herein includes, among other things, performing a process operation on an exposed surface of a substrate so as to form an h-terminated silicon surface, selectively forming a sacrificial material layer within a replacement gate cavity but not on the h-terminated silicon surface, forming a high-k layer of insulating material within the replacement gate cavity above the h-terminated silicon surface and laterally between first spaced-apart portions of the sacrificial material layer, and forming a work-function adjusting material layer in the gate cavity, wherein the work-function adjusting material layer has a substantially planar upper surface that extends between second spaced-apart portions of the sacrificial material layer formed on the sidewall spacers.. .
Global Foundries Inc.
05/21/15
20150137268
new patent

Non-planar sige channel pfet


Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a channel layer formed of a germanium compound having a germanium concentration b formed on a semiconductor substrate having a germanium concentration of a, the germanium concentration of the substrate a being less than the germanium concentration of the channel layer b.
Taiwan Semiconductor Manfacturing Company Limited
05/21/15
20150137266
new patent

Replacement channels for semiconductor devices and methods for forming the same using dopant concentration boost


A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer.
Taiwan Semiconductor Manufacturing Co., Ltd.
05/21/15
20150137264
new patent

Finfet body contact and making same


A semiconductor device may include body contacts on a finfet device for esd protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150137263
new patent

Semiconductor device having fin-type field effect transistor and manufacturing the same


A field effect transistor includes a fin structure, having a sidewall, protruding from a substrate, and a device isolation structure on the substrate, the device isolation structure defining the sidewall of the fin structure, wherein the fin structure includes a buffer semiconductor pattern disposed on the substrate and a channel pattern disposed on the buffer semiconductor pattern, wherein the buffer semiconductor pattern has a lattice constant different from that of the channel pattern, and wherein the device isolation structure includes a gap-fill insulating layer, and includes an oxidation blocking layer pattern disposed between the buffer semiconductor pattern and the gap-fill insulating layer.. .
05/21/15
20150137262
new patent

Semiconductor device and fabricating the same


A semiconductor device includes: active fins protruding from an active layer and extending in a first direction; a gate structure on the active fins extending in a second direction intersecting the first direction; and a spacer on at least one side of the gate structure, wherein each of the active fins includes a first region and a second region adjacent to the first direction in the first direction, and a width of the first region in the second direction is different from a width of the second region in the second direction.. .
Samsung Electronics Co., Ltd.
05/21/15
20150137261
new patent

Semiconductor device


A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.. .
Samsung Electronics Co., Ltd.
05/21/15
20150137260
new patent

Semiconductor device


A plurality of unit misfet elements connected in parallel with each other to make up a power misfet are formed in an ldmosfet forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power misfet is formed in a driver circuit region on the main surface of the semiconductor substrate.
Renesas Electronics Corporation
05/21/15
20150137259
new patent

Semiconductor device


A semiconductor device includes a substrate including a conductive region, an insulating layer disposed on the substrate and including an opening exposing the conductive region, and a conductive layer buried within the opening and including a first region disposed on inner side walls of the opening and a second region disposed within the first region. The first region includes a plurality of first crystal grains and the second region includes a plurality of second crystal grains.
05/21/15
20150137257
new patent

Semiconductor device with dual work function gate stacks and fabricating the same


A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate; forming a metal containing layer, containing an effective work function adjust species, over the gate dielectric layer; forming an anti-reaction layer over the metal containing layer; increasing an amount of the effective work function adjust species contained in the metal containing layer; and forming, on the substrate, a gate stack by etching the anti-reaction layer, the metal containing layer, and the gate dielectric layer.. .
Sk Hynix Inc.
05/21/15
20150137255
new patent

Semiconductor device


A semiconductor device is described, including a substrate including a first area and a second area, a first mos element of a first conductivity type in the first area, and a second mos element of the first conductivity type in the second area. The first area is closer to a pick-up region of the substrate than the second area.
United Microelectronics Corp.
05/21/15
20150137252
new patent

Layout design system, layout design method, and semiconductor device fabricated by using the same


A layout design system includes a processor; a storage unit configured to store a first unit design having a first area, wherein in the first unit design, a termination is not placed on a border thereof; and a design module configured to generate a second unit design having a second area larger than the first area by placing the termination on a border of the first unit.. .
05/21/15
20150137251
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes a substrate and a device isolation pattern extending from a surface of the substrate into the substrate. The device isolation pattern has an electrically negative property and a physically tensile property.
Samsung Electronics Co., Ltd.
05/21/15
20150137249
new patent

Inter-level connection for multi-layer structures


Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure.
Taiwan Semiconductor Manufacturing Company Limited
05/21/15
20150137248
new patent

Semiconductor device


A standard cell has gate patterns extending in y direction and arranged at an equal pitch in x direction. End portions of the gate patterns are located at the same position in y direction, and have an equal width in x direction.
Panasonic Corporation
05/21/15
20150137247
new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a p-type metal oxide semiconductor device (pmos) and an n-type metal oxide semiconductor device (nmos) disposed over a substrate. The pmos has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region.
Taiwan Semiconductor Manufacturing Company Ltd.
05/21/15
20150137246
new patent

Floating body contact circuit improving esd performance and switching speed


Embodiments of systems, methods, and apparatus for improving esd performance and switching time for semiconductor devices including metal-oxide-semiconductor (mos) field effect transistors (fets), and particularly to mosfets fabricated on semiconductor-on-insulator (“sot”) and silicon-on-sapphire (“sos”) substrates.. .
Peregrine Semiconductor Corporation
05/21/15
20150137240
new patent

Semiconductor device with a low-k spacer and forming the same


A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer.
International Business Machines Corporation
05/21/15
20150137239
new patent

Semiconductor device and manufacturing the same


To suppress performance degradation of a semiconductor device, when the width of a first active region having a first field effect transistor formed therein is smaller than the width of a second active region having a second field effect transistor formed therein, the height of a surface of a first raised source layer of the first field effect transistor is made larger than the height of a surface of a second raised source layer of the second field effect transistor. Moreover, the height of a first surface of a raised drain layer of the first field effect transistor is made larger than a surface of a second raised drain layer of the second field effect transistor..
Renesas Electronics Corporation
05/21/15
20150137238
new patent

High-frequency semiconductor device and manufacturing the same


A high-frequency semiconductor device, wherein on one surface of a semiconductor substrate, a first insulating layer, an undoped epitaxial polysilicon layer in a state of column crystal, a second insulating layer, and a semiconductor layer are formed in order from a side of the one surface, and a high-frequency transistor is formed in a location of the semiconductor layer facing the undoped epitaxial polysilicon layer with the second insulating layer in between.. .
Sony Corporation
05/21/15
20150137235
new patent

Finfet semiconductor device having local buried oxide


There is set forth herein in one embodiment a finfet semiconductor device having a fin extending from a bulk silicon substrate, wherein there is formed wrapped around a portion of the fin a gate, and wherein proximate a channel area of the fin aligned to the gate there is formed a local buried oxide region aligned to the gate. In one embodiment, the local buried oxide region is formed below a channel area of the fin..
Globalfoundries Inc
05/21/15
20150137234
new patent

Mechanisms for forming semiconductor device structure with floating spacer


Embodiments of mechanisms for forming a semiconductor device structure with floating spacers are provided. The semiconductor device structure includes a silicon-on-insulator (soi) substrate and a gate stack formed on the soi substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.
05/21/15
20150137232
new patent

Lateral double diffused metal oxide semiconductor device and manufacturing method thereof


The present invention discloses a lateral double diffused metal oxide semiconductor (ldmos) device and a manufacturing method thereof. The ldmos device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain.
Richtek Technology Corporation
05/21/15
20150137231
new patent

Lateral double diffused metal-oxide-semiconductor device and fabricating the same


A lateral double diffused metal-oxide-semiconductor device includes: a semiconductor substrate; an epitaxial semiconductor layer disposed over the semiconductor substrate; a gate structure disposed over the epitaxial semiconductor layer; a first doped region disposed in the epitaxial semiconductor layer at a first side of the gate structure; a second doped region disposed in the epitaxial semiconductor layer at a second side of the gate structure; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a trench formed in the third doped region, the first doped region and the epitaxial semiconductor layer under the first doped region; a conductive contact formed in the trench; and a fifth doped region disposed in the epitaxial semiconductor layer under the trench.. .
Vanguard International Semiconductor Corporation
05/21/15
20150137229
new patent

Semiconductor device and fabricating the same


The invention provides a semiconductor device, including: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region, wherein the first conductivity type is opposite to the second conductivity type; and a drain region formed in the drift region; a multiple reduced surface field (resurf) structure embedded in the drift region of the substrate; and a gate dielectric layer having a thick portion formed over the substrate, wherein the gate dielectric includes at least a stepped-shape or a curved shape curved-shape formed thereon, and wherein the multiple resurf structure is aligned with the thick portion of the gate dielectric layer.. .
Vanguard International Semiconductor Corporation
05/21/15
20150137226
new patent

Semiconductor device and producing a semiconductor device


A semiconductor device includes a semiconductor substrate having first regions of a first conductivity type and body regions of the first conductivity type, which are arranged in a manner adjoining the first region and overlap the latter in each case on a side of the first region which faces a first surface of the semiconductor substrate, and having a multiplicity of drift zone regions arranged between the first regions and composed of a semiconductor material of a second conductivity type, which is different than the first conductivity type. The first regions and the drift zone regions are arranged alternately and form a superjunction structure.
Infineon Technologies Ag
05/21/15
20150137225
new patent

Oxide terminated trench mosfet with three or four masks


An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region.
Alpha And Omega Semiconductor Incorporated
05/21/15
20150137224
new patent

Semiconductor device, integrated circuit and forming a semiconductor device


A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region.
Infineon Technologies Ag
05/21/15
20150137222
new patent

Stress-reduced field-effect semiconductor device and forming therefor


A field-effect semiconductor device is provided. The field-effect semiconductor device includes a semiconductor body with a first surface defining a vertical direction.
Infineon Technologies Austria Ag
05/21/15
20150137221
new patent

Semiconductor device and manufacturing same


A semiconductor device includes: a substrate with an off-angle; an sic layer provided on a principal surface of the substrate, including an n type drift region, and having a trench whose bottom is located in the drift region; and a gate electrode provided in the trench in the sic layer. In the trench in the sic layer, a first angle formed by at least part of a first sidewall on an off-direction side and the principal surface of the substrate is an obtuse angle, and a second angle formed by at least part of a second sidewall opposite to the first sidewall and the principal surface of the substrate is an acute angle, in a cross section parallel to a direction of a normal line to the principal surface of the substrate and a direction of a c-axis of the substrate..
Panasonic Intellectual Property Management Co., Ltd.
05/21/15
20150137219
new patent

Semiconductor device


A semiconductor device includes a fin-shaped silicon layer and a pillar-shaped silicon layer on the fin-shaped silicon layer, where a width of the pillar-shaped silicon layer is equal to a width of the fin-shaped silicon layer. Diffusion layers reside in upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and in a lower portion of the pillar-shaped silicon layer to form.
Unisantis Electronics Singapore Pte. Ltd.
05/21/15
20150137218
new patent

Semiconductor device with surrounding gate transistor


A method for producing a semiconductor device includes a first step of forming a fin-shaped silicon layer on a silicon substrate using a first resist and forming a first insulating film therearound; and a second step of forming a second insulating film around the fin-shaped silicon layer and etching the second insulating film so as to be left on a side wall of the fin-shaped silicon layer, depositing a third insulating film on the first and second insulating films and the fin-shaped silicon layer, depositing a polysilicon thereon, planarizing a surface thereof, and etching back the polysilicon to expose the third insulating film, forming a second resist, etching the second and third insulating films and then etching the fin-shaped silicon layer and the polysilicon, and removing the second insulating film to form a pillar-shaped silicon layer and a dummy gate formed of the polysilicon.. .
Unisantis Electronics Singapore Pte. Ltd.
05/21/15
20150137215
new patent

Semiconductor device


A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction.
Renesas Electronics Corporation
05/21/15
20150137211
new patent

Semiconductor device manufacturing method and semiconductor device


A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.. .
Fujitsu Semiconductor Limited
05/21/15
20150137209
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes a first channel layer, a second channel layer protruding from the first channel layer, a pipe gate including a silicide area surrounding the first channel layer, a tunnel insulating layer surrounding the second channel layer, a data storage layer surrounding the second channel layer with the tunnel insulating layer interposed therebetween, and interlayer insulating layers and conductive patterns which are alternately stacked while surrounding the second channel layer with the data storage layer and the tunnel insulating layer interposed therebetween.. .
Sk Hynix Inc.
05/21/15
20150137186
new patent

Formation of an asymmetric trench in a semiconductor substrate and a bipolar semiconductor device having an asymmetric trench isolation region


Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench.
International Business Machines Corporation
05/21/15
20150137184
new patent

Semiconductor device and manufacturing a semiconductor device


A method of manufacturing a semiconductor device includes laminating and forming an electron transit layer, an electron supplying layer, an etching stop layer, and a p-type film on a substrate sequentially, the p-type film being formed of a nitride semiconductor material that includes al doped with an impurity element that attains p-type, the etching stop layer being formed of a material that includes gan, removing the p-type film in an area except an area where a gate electrode is to be formed, by dry etching to form a p-type layer in the area where the gate electrode is to be formed, the dry etching being conducted while plasma emission in the dry etching is observed, the dry etching being stopped after the dry etching is started and plasma emission originating from al is not observed, and forming the gate electrode on the p-type layer.. .
Transphorm Japan, Inc.
05/21/15
20150137182
new patent

Semiconductor device having v-shaped region


Among other things, a semiconductor device or transistor and a method for forming the semiconductor device are provided for herein. The semiconductor device comprises one or more v-shaped recesses in which stressed monocrystalline semiconductor material, such as silicon germanium, is grown, to form at least one of a source or a drain of the semiconductor device.
Taiwan Semiconductor Manufacturing Company Limited
05/21/15
20150137177
new patent

Semiconductor device having polysilicon plugs with silicide crystallites


A semiconductor device includes a field effect transistor structure having source zones of a first conductivity type and body zones of a second conductivity type which is the opposite of the first conductivity type, the source zones adjoining a first surface of a semiconductor die comprising the source and the body zones. The semiconductor device further includes a dielectric layer adjoining the first surface and polysilicon plugs extending through openings in the dielectric layer and electrically connected to the source and the body zones.
Infineon Technologies Austria Ag
05/21/15
20150137176
new patent

Semiconductor power device


A semiconductor power device is provided, comprising a substrate of a first conductive type, a buffering layer of a second conductive type formed on the substrate, a voltage supporting layer formed on the buffering layer, and alternating sections of different conductive types formed at the substrate. The voltage supporting layer comprises first semiconductor regions of the first conductive type and second semiconductor regions of the second conductive type, wherein the first semiconductor regions and the second semiconductor regions are alternately arranged.
United Microelectronics Corp.
05/21/15
20150137174
new patent

Methods and increased holding voltage in silicon controlled rectifiers for esd protection


Methods and apparatus for increased holding voltage scrs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150137166
new patent

Epoxy resin composition for optical semiconductor device and optical semiconductor device using the same


The present invention relates to an epoxy resin composition for an optical semiconductor device having an optical semiconductor element mounting region and having a reflector that surrounds at least a part of the region, the epoxy resin composition being an epoxy resin composition for forming the reflector, the epoxy resin composition including the following ingredients (a) to (e): (a) an epoxy resin; (b) a curing agent; (c) a white pigment; (d) an inorganic filler; and (e) a specific release agent.. .
Nitto Denko Corporation
05/21/15
20150137145
new patent

Semiconductor device and semiconductor device manufacturing method


The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using sic and a semiconductor device producing method. A semiconductor device includes: a silicon carbide substrate; a first-conductive-type first silicon carbide layer provided on a first principal surface of the silicon carbide substrate; a second-conductive-type first silicon carbide region formed at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region formed at a surface of the first silicon carbide region; a second-conductive-type third silicon carbide region formed below the second silicon carbide region; a trench piercing through the second silicon carbide region to reach the third silicon carbide region; a gate insulating film; a gate electrode; an interlayer insulating film with which the gate electrode is covered; a first electrode that is formed on the second silicon carbide region and the interlayer insulating film in a side surface of the trench while containing a metallic element selected from a group consisting of ni, ti, ta, mo, and w; a second electrode that is formed on the third silicon carbide region in a bottom portion of the trench and the first electrode while containing al; a first main electrode formed on the second electrode; and a second main electrode formed on a second principal surface of the silicon carbide substrate..
Kabushiki Kaisha Toshiba
05/21/15
20150137143
new patent

Junction field effect transistor cell with lateral channel region


A junction field effect transistor cell of a semiconductor device includes a top gate region, a lateral channel region and a buried gate region arranged along a vertical direction. The lateral channel region includes first zones of a first conductivity type and second zones of a second conductivity type which alternate along a lateral direction perpendicular to the vertical direction.
Infineon Technologies Ag
05/21/15
20150137142
new patent

Junction field effect transistor cell with lateral channel region


A semiconductor device includes a junction field effect transistor cell with a top gate region, a lateral channel region and a buried gate region. The lateral channel region is arranged between the top gate region and the buried gate region along a vertical direction with respect to a first surface of a semiconductor body.
Infineon Technologies Ag
05/21/15
20150137141
new patent

Gallium nitride devices


Semiconductor structures comprising a iii-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance.
International Rectifier Corporation
05/21/15
20150137139
new patent

Semiconductor device and fabricating a semiconductor device


A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials.
Infineon Technologies Austria Ag
05/21/15
20150137135
new patent

Semiconductor devices with integrated schotky diodes and methods of fabrication


An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a schottky metal layer disposed over the substrate adjacent the gate electrode. The schottky metal layer includes a schottky contact electrically coupled to the channel which provides a schottky junction and at least one alignment mark disposed over the semiconductor substrate.
05/21/15
20150137125
new patent

Semiconductor device


A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad..
Renesas Electronics Corporation
05/21/15
20150137124
new patent

Method for manufacturing semiconductor device


In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150137123
new patent

Semiconductor device and manufacturing the same


In the transistor including an oxide semiconductor film, which includes a film for capturing hydrogen from the oxide semiconductor film (a hydrogen capture film) and a film for diffusing hydrogen (a hydrogen permeable film), hydrogen is transferred from the oxide semiconductor film to the hydrogen capture film through the hydrogen permeable film by heat treatment. Specifically, a base film or a protective film of the transistor including an oxide semiconductor film has a stacked-layer structure of the hydrogen capture film and the hydrogen permeable film.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150137122
new patent

Semiconductor device


A semiconductor device in which release of oxygen from side surfaces of an oxide semiconductor film including c-axis aligned crystal parts can be prevented is provided. The semiconductor device includes a first oxide semiconductor film, a second oxide semiconductor film including c-axis aligned crystal parts, and an oxide film including c-axis aligned crystal parts.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150137121
new patent

Method of manufacturing semiconductor device


A highly reliable transistor which includes an oxide semiconductor and has high field-effect mobility and in which a variation in threshold voltage is small is provided. By using the transistor, a high-performance semiconductor device, which has been difficult to realize, is provided.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150137120
new patent

Semiconductor device


Oxide layers which contain at least one metal element that is the same as that contained in an oxide semiconductor layer including a channel are formed in contact with the top surface and the bottom surface of the oxide semiconductor layer, whereby an interface state is not likely to be generated at each of an upper interface and a lower interface of the oxide semiconductor layer. Further, it is preferable that an oxide layer, which is formed using a material and a method similar to those of the oxide layers be formed over the oxide layers accordingly, the interface state hardly influences the movement of electrons..
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150137119
new patent

Semiconductor device and manufacturing the same


It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150137076
new patent

Semiconductor device and manufacturing the same


A semiconductor device including a graphene layer and a method of manufacturing the same are disclosed. A method in which graphene is grown on a catalyst metal by a chemical vapor deposition or the like is known.
Fujitsu Limited
05/21/15
20150137072
new patent

Mask for forming semiconductor layer, semiconductor device, and fabricating the same


A mask for forming a semiconductor layer and a semiconductor device manufactured using the same. The mask for forming a semiconductor layer includes oblique openings.
Gwangju Institute Of Science And Technology
05/21/15
20150137064
new patent

Reduction of forming voltage in semiconductor devices


This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (reram) approaches to provide a memory device with more predictable operation.
Intermolecular Inc.


Popular terms: [SEARCH]



Follow us on Twitter
twitter icon@FreshPatents

###

This listing is a sample listing of patent applications related to Semiconductor Device for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Semiconductor Device with additional patents listed. Browse our RSS directory or Search for other possible listings.
     SHARE
  
         















0.5808

9839

0 - 1 - 174