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Semiconductor Device patents



      
           
This page is updated frequently with new Semiconductor Device-related patent applications. Subscribe to the Semiconductor Device RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Device RSS RSS


Three-dimensional charge trapping nand cell with discrete charge trapping film

Spansion

Three-dimensional charge trapping nand cell with discrete charge trapping film

Heterogeneous integration of memory and split-architecture processor

Texas Instruments

Heterogeneous integration of memory and split-architecture processor

Heterogeneous integration of memory and split-architecture processor

Taiwan Semiconductor Manufacturing

Mechanisms for forming protection layer on back side of wafer

Date/App# patent app List of recent Semiconductor Device-related patents
04/23/15
20150113493
 Method, system and computer program product for generating layout for semiconductor device patent thumbnailnew patent Method, system and computer program product for generating layout for semiconductor device
A method is performed at least in part by at least one processor. In the method, a plurality of circuit elements are placed in a layout for a semiconductor device, the plurality of circuit elements having a plurality of pins.
Taiwan Semiconductor Manufacturing Company, Ltd.
04/23/15
20150113350
 Selective test pattern processor patent thumbnailnew patent Selective test pattern processor
A method, system, and computer program product to test a semiconductor device are described. The system includes an input interface to receive a set of test patterns to test the semiconductor device and a user selection corresponding to a subset of the set of test patterns.
International Business Machines Corporation
04/23/15
20150113349
 Selective test pattern processor patent thumbnailnew patent Selective test pattern processor
A method, system, and computer program product to test a semiconductor device are described. The method includes receiving a set of test patterns for testing the semiconductor device and a user selecting a subset of the set of test patterns.
International Business Machines Corporation
04/23/15
20150113343
 Semiconductor device, test structure of the semiconductor device, and  testing the semiconductor device patent thumbnailnew patent Semiconductor device, test structure of the semiconductor device, and testing the semiconductor device
A semiconductor device, a test structure of the semiconductor device, and a method of testing the semiconductor device are provided. The test structure including a first pad and a second pad being separated from each other, and a first test element and a second test element connected between the first pad and the second pad, a first value of a characteristic parameter of the first test element being different from a second value of the characteristic parameter of the second test element, may be provided..
04/23/15
20150113322
 Data storing system and operating method thereof patent thumbnailnew patent Data storing system and operating method thereof
A data storing system includes a semiconductor device suitable for repeatedly performing a read operation by changing a level of a read voltage according to read voltages listed on a read retry table when a read operation on a selected page is passed, in response to a command and an address, and a controller suitable for controlling the read operation of the semiconductor device by generating the command and the address, wherein a read voltage to be used for performing the read operation is determined among the read voltages listed on the read retry table when the semiconductor device performs the read operation based on data read as a result of a predetermined number of read operations.. .
Sk Hynix Inc.
04/23/15
20150113303
 Semiconductor device predictive dynamic thermal management patent thumbnailnew patent Semiconductor device predictive dynamic thermal management
A semiconductor device includes a memory storing a lookup table including stored values associated with modes of operation of a component of the semiconductor device. A monitor monitors an operating parameter of the component in real-time, and reports a calculated value associated with the same.
Broadcom Corporation
04/23/15
20150112624
 Metrology through use of feed forward feed sideways and measurement cell re-use patent thumbnailnew patent Metrology through use of feed forward feed sideways and measurement cell re-use
Metrology may be implemented during semiconductor device fabrication by a) modeling a first measurement on a first test cell formed in a layer of a partially fabricated device; b) performing a second measurement on a second test cell in the layer; c) feeding information from the second measurement into the modeling of the first measurement; and after a lithography pattern has been formed on the layer including the first and second test cells, d) modeling a third and a fourth measurement on the first and second test cells respectively using information from a) and b) respectively.. .
Kla-tencor Corporation
04/23/15
20150111395
 Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium patent thumbnailnew patent Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
According to the present disclosure, a film containing a predetermined element, carbon and nitrogen is formed with high controllability of a composition thereof. A method of manufacturing a semiconductor device includes forming a film containing a predetermined element, carbon and nitrogen on a substrate by performing a cycle a predetermined number of times.
Hitachi Kokusai Electric Inc.
04/23/15
20150111393
 Manufacturing  semiconductor device and lithography template patent thumbnailnew patent Manufacturing semiconductor device and lithography template
In the manufacturing method of a semiconductor device according to the present embodiment, a resist is supplied on a base material. A template including a first template region having a device pattern and a second template region being adjacent to the device pattern and having supporting column patterns is pressed against the resist on the base material.
Kabushiki Kaisha Toshiba
04/23/15
20150111381
 Method of fabricating semiconductor device and computing system for implementing the method patent thumbnailnew patent Method of fabricating semiconductor device and computing system for implementing the method
Provided are method of fabricating semiconductor device and computing system for implementing the method. The method of fabricating a semiconductor device includes forming a target layer, forming a first mask on the target layer to expose a first region, subsequently forming a second mask on the target layer to expose a second region separated from the first region in a first direction, subsequently forming a third mask in the exposed first region to divide the first region into a first sub region and a second sub region separated from each other in a second direction intersecting the first direction, and etching the target layer using the first through third masks such that the first and second sub regions and the second region are defined in the target layer..
04/23/15
20150111380
new patent

Self-aligned double patterning


A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer and masking layers over the dielectric layer.
Taiwan Semiconductor Manufacturing Company, Ltd.
04/23/15
20150111378
new patent

Method of manufacturing semiconductor device and substrate processing apparatus


There is provided a method of manufacturing a semiconductor device, the method including: forming an amorphous metal film on a substrate while maintaining the substrate at a first temperature by performing, in a time-divisional manner, supplying in the time-divisional manner a metal-containing gas and a first reducing gas to the substrate a predetermined number of times to form a first amorphous metal film on the substrate; and simultaneously supplying the metal-containing gas and a second reducing gas to the substrate having the first amorphous metal film formed thereon to form a second amorphous metal film on the first amorphous metal film; and heating the substrate having the amorphous metal film formed thereon to a second temperature higher than the first temperature.. .
04/23/15
20150111374
new patent

Surface treatment in a dep-etch-dep process


Embodiments of present invention provide a method of forming semiconductor devices. The method includes creating an opening in a semiconductor structure; depositing a first layer of metal inside the opening with the first layer of metal partially filling up the opening; modifying a top surface of the first layer of metal in an etching process; passivating the modified top surface of the first layer of metal to form a passivation layer; and depositing a second layer of metal directly on top of the passivation layer..
International Business Machines Corporation
04/23/15
20150111369
new patent

Semiconductor buffer structure, semiconductor device including the semiconductor buffer structure, and manufacturing the semiconductor device using the semiconductor buffer structure


A semiconductor buffer structure includes a silicon substrate, a nucleation layer formed on the silicon substrate, and a buffer layer formed on the nucleation layer. The buffer layer includes a first layer formed of a nitride semiconductor material having a uniform composition rate, a second layer formed of the same material as the nucleation layer on the first layer, and a third layer formed of the same material with the same composition ratio as the first layer on the second layer..
04/23/15
20150111361
new patent

Integrated circuit resistor


A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor.
Taiwan Semiconductor Manufacturing Company, Ltd.
04/23/15
20150111360
new patent

Method of manufacturing a semiconductor device


A method of manufacturing a semiconductor device includes forming a first conductive layer on a substrate, partially removing the first conductive layer and an upper portion of the substrate to form a recess, forming a second conductive layer pattern to fill the recess, forming a third conductive layer on the second conductive layer pattern and the first conductive layer, and patterning the third conductive layer and the second conductive layer pattern to form a bit line structure and a bit line contact, respectively.. .
Samsung Electronics Co., Ltd.
04/23/15
20150111357
new patent

Manufacturing semiconductor device


First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.. .
04/23/15
20150111354
new patent

Superjunction devices having narrow surface layout of terminal structures, buried contact regions and trench gates, and methods of manufacturing the devices


Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at least a first side of the body contact region other than a portion of a first main surface of the semiconductor substrate..
Icemos Technology Ltd.
04/23/15
20150111353
new patent

Semiconductor device and the manufacturing the same


The semiconductor device according to the invention and the method of manufacturing the semiconductor device according to the invention facilitate lowering the on-state voltage, preventing the breakdown voltage from lowering, lowering the gate capacitance, and reducing the manufacturing costs.. .
04/23/15
20150111352
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.. .
Sk Hynix Inc.
04/23/15
20150111348
new patent

Semiconductor device and manufacturing the same


A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the soi substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed.
04/23/15
20150111340
new patent

Method for forming wiring, semiconductor device, and manufacturing semiconductor device


A wiring which is formed using a conductive film containing copper and whose shape is controlled is provided. A transistor including an electrode which is formed in the same layer as the wiring is provided.
Semiconductor Energy Laboratory Co., Ltd.
04/23/15
20150111327
new patent

Method for forming semiconductor device package with slanting structures


A method for forming semiconductor device package comprises providing a substrate with via contact pads and via through holes through said substrate, terminal pads on a bottom surface of said substrate and an exposed type through hole through said substrate. A die is provided with bonding pads thereon and an exposed type pad on a bottom surface of said die.
King Dragon International Inc.
04/23/15
20150111318
new patent

Heterogeneous integration of memory and split-architecture processor


A method for fabricating a semiconductor device provides a first chip having first terminals, a second chip having second terminals, and a third chip having third terminals. A first silicon interposer having first through silicon vias tsvs and a second silicon interposer having second tsvs is provided.
Texas Instruments Incorporated
04/23/15
20150111317
new patent

Method of manufacturing semiconductor device


Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes).
Renesas Electronics Corporation
04/23/15
20150111310
new patent

Semiconductor device and manufacturing the same


A lower electrode film, a ferroelectric film, and an upper electrode film are formed on an insulation film covering a transistor formed on a semiconductor substrate. Furthermore, a pt film is formed as a cap layer on the upper electrode film.
Fujitsu Semiconductor Limited
04/23/15
20150111309
new patent

Method for fabricating semiconductor device


In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer.
Sk Hynix Inc.
04/23/15
20150110383
new patent

Methods of inspecting a semiconductor device and semiconductor inspection systems


Inventive concepts provide a method of inspecting a semiconductor device including obtaining inspection image data of an inspection pattern of an inspection layer on a substrate. The method may include extracting inspection contour data including an inspection pattern contour from the inspection image data, and merging the inspection contour data with comparison contour data of a comparison layer to obtain merged data.
Samsung Electronics Co., Ltd.
04/23/15
20150109841
new patent

Semiconductor device and operating the same


A semiconductor device comprises a memory block having a content addressable memory (cam) cell array storing data for internal operation conditions, and a memory cell array. The semiconductor device also comprises a page buffer to program data in the memory block or read the data programmed in the memory block; a control logic to activate a reset enable signal for initializing the page buffer during a reset operation and output the activated reset enable signal; and a power-supply controller to output a reset control signal for initializing the page buffer when the reset enable signal is activated, and provide a page buffer power-supply signal to the page buffer.
Sk Hynix Inc.
04/23/15
20150109840
new patent

Semiconductor device and operating the same


A semiconductor device employs a technology for improving data retention characteristics of a cell array storing data regarding conditions for controlling internal operations of the semiconductor device. The semiconductor device includes a content addressable memory (cam) cell array configured to store cam data regarding conditions for controlling the internal operations, a control logic configured to store the cam data read out of the cam cell array, and a microprocessor configured to perform a reprogramming operation on the cam cell array using the cam data stored in the control logic..
Sk Hynix Inc.
04/23/15
20150109738
new patent

Unit for semiconductor device and semiconductor device


A semiconductor device has a single unit capable of improving adhesion to a cooling body and a heat dissipation performance, and an aggregate of the single units is capable of configuring any circuit at a low cost. A single unit includes copper blocks, an insulating substrate with a conductive pattern, an igbt chip, a diode chip, a collector terminal pin, implant pins fixed to the chips by solder, a printed circuit board having the implant pins fixed thereto, an emitter terminal pin, a control terminal pin, a collector terminal pin, and a resin case having the above-mentioned components sealed therein.
Fuji Electric Co., Ltd.
04/23/15
20150109736
new patent

Electronic device assemblies and vehicles employing dual phase change materials


Electronic device assemblies employing dual phase change materials and vehicles incorporating the same are disclosed. In one embodiment, an electronic device assembly includes a semiconductor device having a surface, wherein the semiconductor device operates in a transient heat flux state and a normal heat flux state, a coolant fluid thermally coupled to the surface of the semiconductor device, and a phase change material thermally coupled to the surface of the semiconductor device.
Toyota Motor Engineering & Manufacturing North America, Inc.
04/23/15
20150109706
new patent

Semiconductor device


The semiconductor device includes a power chip including a switching element that switches a supply of power from a power supply to a load between an on-state and an off-state, a control chip in which is incorporated a control circuit that controls the switching element of the power chip, and a reverse connection protection circuit, provided in the control chip, that controls the switching element of the power chip into an on-state when the power supply is reverse-connected, wherein the reverse connection protection circuit has protective resistors, interposed between the control circuit and the positive electrode side of the power supply, and a control voltage formation circuit into which is input an intermediate voltage of the protective resistors and which forms a control voltage that controls the switching element of the power chip into an on-state when the power supply is reverse-connected.. .
Fuji Electric Co., Ltd
04/23/15
20150109594
new patent

Multiple phase-shift photomask and semiconductor manufacturing method


Manufacturing of semiconductor devices often involves performed photolithography to pattern and etch the various features of those devices. Such photolithography involves masking and focusing light onto a surface of the semiconductor device for exposing and etching the features of the semiconductor devices.
Spansion Llc
04/23/15
20150109201
new patent

Semiconductor device


Provided is a device capable of displaying an image with small power consumption by adjusting output of the device in accordance with the physical and mental state of a user, such as tiredness or excitement. An electronic device includes one or a plurality of sensor portions which collects data from a user; a chaotic attractor generation portion which calculates a chaotic attractor by arithmetic processing of the collected data; and a lyapunov index generation portion which calculates an index indicating the degree to which the chaotic attractor is matched to chaos definition conditions.
Semiconductor Energy Laboratory Co., Ltd.
04/23/15
20150109155
new patent

Semiconductor device and electronic control device


To suppress detection accuracy of a measurement resistance from decreasing by an on-resistance of a selector switch. The selector switch is provided between a first node coupled to a first voltage through a reference resistance and multiple second nodes coupled to the second voltage through measurement resistances, and selects the second node to be coupled to the first node with the selector switch.
Renesas Electronics Corporation
04/23/15
20150109054
new patent

Ready-flag circuitry for differential amplifiers


Ready-flag circuitry for differential amplifiers. In some embodiments, a semiconductor device may include an amplifier including two inputs, and a ready-flag circuit operably coupled to the amplifier, the ready-flag circuit configured to monitor two or more internal nodes of the amplifier and to produce a signal indicating whether a voltage or current difference between the two inputs has been minimized.
Freescale Semiconductor, Inc.
04/23/15
20150109050
new patent

Method of operating a reverse conducting igbt


According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode. The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device..
Infineon Technologies Ag
04/23/15
20150109019
new patent

Method for evaluating semiconductor device


A method for evaluating a buried channel in a semiconductor device including a semiconductor layer having a stacked-layer structure is provided. A method for evaluating a semiconductor device is provided, which includes the steps of: electrically short-circuiting a source and a drain of a transistor; applying dc voltage and ac voltage to a gate to obtain a cv characteristic that indicates a relationship between the dc voltage and a capacitance between the gate and each of the source and the drain; and determining that a semiconductor layer of the transistor includes a stacked-layer structure, when the capacitance in a region in an accumulation state in the cv characteristic is increased stepwise..
Semiconductor Energy Laboratory Co., Ltd.
04/23/15
20150109013
new patent

Semiconductor device and testing the same


A semiconductor device includes a unit region including a circuit test region and a probe test region. The circuit test region includes a test circuit and a plurality of circuit test pads operatively coupled to the test circuit.
Samsung Electronics Co., Ltd.
04/23/15
20150108961
new patent

Frequency dependent analog boost converter for low voltage applications


An analog open-loop self-oscillating boost converter is provided including: an output terminal for supplying an output voltage bus; an input terminal for receiving variable input power; a varactor positioned in series with the input terminal; and an oscillating network having an inductor, a resistor and a capacitor in a parallel orientation, the oscillating network connected to a semiconductor device and the varactor.. .
The Governors Of The University Of Alberta
04/23/15
20150108664
new patent

Semiconductor device


Provided is a semiconductor device which includes a bonding wire, one end of which is connected to a bipolar device, the other end of which is connected to a conductive member, and the center of which is connected to a unipolar device, said semiconductor device being capable of improving the reliability of wire bonding. A package (4) includes a die pad (61), a source lead (63), a first mosfet (11), and a first schottky barrier diode (21).
Rohm Co., Ltd.
04/23/15
20150108657
new patent

Electronic device


A semiconductor device and electronic device comprising the same includes at least one dummy chip having at least one through silicon via (tsv), and at least one active chip connected to the at least one dummy chip. The at least one active chip exchanges an electrical signal through the at least one tsv.
Samsung Electronics Co., Ltd.
04/23/15
20150108655
new patent

Semiconductor device and manufacturing the same


Both enhancement of embeddability of a wiring groove and suppression of the generation of a coupling failure between a wiring and a coupling member are simultaneously achieved. In a cross-section perpendicular to a direction passing through the contact and a direction in which the second wiring extends, the center of the contact is more close to a first side surface of the second wiring than the center of the second wiring.
Renesas Electronics Corporation
04/23/15
20150108654
new patent

Reliable passivation layers for semiconductor devices


Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided.
Globalfoundries Singapore Pte. Ltd.
04/23/15
20150108652
new patent

Semiconductor device and fabrication method


A semiconductor device and its fabrication method are provided. A first dielectric layer is provided to cover a substrate.
Semiconductor Manufactruing International (shanghai) Corporation
04/23/15
20150108649
new patent

Method of forming hybrid diffusion barrier layer and semiconductor device thereof


In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall.
Taiwan Semiconductor Manufacturing Co., Ltd.
04/23/15
20150108648
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes first and second semiconductor members and a first barrier film. The first semiconductor member includes a first insulating film, and a first wiring film in the first insulating film, the surface of which is exposed in the first insulating film.
Kabushiki Kaisha Toshiba
04/23/15
20150108643
new patent

Semiconductor device with embedded semiconductor die and substrate-to-substrate interconnects


A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump.
Amkor Technology, Inc.
04/23/15
20150108641
new patent

Semiconductor device and manufacturing method thereof


A method of manufacturing a semiconductor device includes providing a carrier including a first layer, a second layer, a first surface of the first layer and a second surface of the second layer, disposing a plurality of solder bumps on the second surface, disposing a molding between the plurality of solder bumps and over the second surface, cutting the first layer to form a first recess in the first layer, wherein the first recess is above a position between at least two of the plurality of solder bumps, and cutting the molding from a bottom surface of the first recess to form a second recess in the molding between the at least two of the plurality of solder bumps. Further, a semiconductor device includes a carrier including a first layer and a second layer, a plurality of solder bumps disposed on the second layer, a molding disposed over the second layer and surrounding the plurality of solder bumps, the molding includes a protruded portion protruding from a sidewall of the first layer adjacent to an end portion of the first layer..
Taiwan Semiconductor Manufacturing Company Ltd.
04/23/15
20150108639
new patent

Semiconductor device and manufacturing method thereof


Of three chips (2a), (2b), and (2c) mounted on a main surface of a package substrate (1) in a multi-chip module (mcm), a chip (2a) with a dram formed thereon and a chip (2b) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2a), (2b) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2c) with a high-speed microprocessor formed thereon is mounted over the two chips (2a) and (2b) and is electrically connected to bonding pads (9) of the package substrate (1) through au wires (8)..
Renesas Electronics Corporation
04/23/15
20150108637
new patent

Semiconductor device including two or more chips mounted over wiring substrate


A semiconductor device includes a composite chip mounted over the a wiring substrate, the composite chip including a first area and a second area that is provided independently from the first area, the first area including a first circuit formed in the first area, and the second area including a second circuit formed in the second area.. .
Micron Technology, Inc.
04/23/15
20150108634
new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a die, a pad disposed on the die and configured to be electrically coupled with a bump through a conductive trace attached on the pad, a polymer disposed over the die and patterned to provide a path for the conductive trace passing through, and a molding surrounding the die and the polymer. A top surface of the molding is substantially in a same level as a top surface of the polymer.
Taiwan Semiconductor Manufacturing Company Ltd.
04/23/15
20150108633
new patent

Mechanisms for forming protection layer on back side of wafer


Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure is provided.
Taiwan Semiconductor Manufacturing Co., Ltd.
04/23/15
20150108629
new patent

Semiconductor device


A cooling fin 9 is joined to a semiconductor element 1. A resin 10 encapsulates the semiconductor element 1.
Mitsubishii Electric Corporation
04/23/15
20150108625
new patent

Semiconductor device with heat spreader


A semiconductor device includes a package body, a semiconductor die embedded in the package body and a heat spreader attached to a top surface of the package body and spaced from semiconductor die. The heat spreader may be formed of solder that is melted within a recess in the top surface of the package body..
Freescale Semiconductor, Inc.
04/23/15
20150108624
new patent

Semiconductor device


A semiconductor device includes: a semiconductor chip, and a lead frame. The semiconductor chip is mounted over a die pad.
Renesas Electronics Corporation
04/23/15
20150108622
new patent

Interconnect board and semiconductor device


An interconnect board according to an embodiment of the present technique includes: interconnect layers and insulating layers that are alternately stacked; vias that electrically connect the interconnect layers; front-surface-side electrode pads formed on the front-surface side; back-surface-side electrode pads that are formed on the back-surface side and are arranged in an array; and a conductor loop that is formed in a conductor path connecting one of the front-surface-side electrode pads and one of the back-surface-side electrode pads, the conductor loop being formed with interconnects in the interconnect layers and the vias, the conductor loop extending in a direction perpendicular to the thickness direction of the interconnect board.. .
04/23/15
20150108620
new patent

Superjunction semiconductor device and producing thereof


A method of forming a superjunction device includes forming at least one trench in a first surface of a first semiconductor layer of a first doping type, and a semiconductor mesa region adjoining the at least one trench. A second semiconductor layer is formed at least on sidewalls and a bottom of the at least one trench.
Infineon Telchnologies Austria Ag
04/23/15
20150108614
new patent

Semiconductor device, circuit substrate, and electronic device


A semiconductor device has a through electrode formed in a through hole which penetrates a si substrate from one surface to the other surface of the si substrate, wherein a rectangular electrode pad is provided on the other surface with an insulation film laid between the electrode pad and the other surface, an opening of the through hole on the one surface side is circular, an opening of the through hole on the other surface side is rectangular, and the area of the opening on the other surface side is made smaller than the area of the opening on the one surface side.. .
Seiko Epson Corporation
04/23/15
20150108613
new patent

Semiconductor chip with seal ring and sacrificial corner pattern


A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.. .
Renesas Electronics Corporation
04/23/15
20150108612
new patent

Method for thinning, metalizing, and dicing a semiconductor wafer, and semiconductor device made using the method


There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines.. .
Lapis Semiconductor Co., Ltd.
04/23/15
20150108603
new patent

Semiconductor device with patterned ground shielding


Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (pgs) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the pgs to a second portion of the pgs.
Taiwan Semiconductor Manufacturing Company Limited
04/23/15
20150108602
new patent

Semiconductor device including fuse structure


A semiconductor device includes a substrate having a fuse area and a device area; a fuse structure in an insulating layer of the fuse area, and a wire structure in the insulating layer of the device area. The fuse structure includes a fuse via, a fuse line electrically connected to a top end of the fuse via pattern and extending in a direction.
Samsung Electronics Co., Ltd.
04/23/15
20150108601
new patent

Semiconductor device including a wall oxide film and forming the same


A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region.
Sk Hynix Inc.
04/23/15
20150108599
new patent

Semiconductor apparatus, manufacturing semiconductor apparatus, designing semiconductor apparatus, and electronic apparatus


A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.. .
Sony Corporation
04/23/15
20150108584
new patent

Semiconductor device and fabricating the same


A semiconductor device includes a first device isolation pattern defining a first active region, a second device isolation pattern defining a second active region, a first gate disposed on the first active region, the first gate including a gate insulating pattern of a first thickness and a second gate disposed on the second active region, the second gate including a gate insulating pattern of a second thickness greater than the first thickness. A top surface of the first device isolation pattern is curved down toward the first active region such that the first active region has an upper portion protruded from the top surface and rounded corners..
Samsung Electronics Co., Ltd.
04/23/15
20150108579
new patent

Semiconductor device


The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover.
Renesas Electronics Corporation
04/23/15
20150108578
new patent

Aqueous cleaning techniques and compositions for use in semiconductor device manufacture


Some embodiments relate to a manufacturing method for a semiconductor device. In this method, a semiconductor workpiece, which includes a metal gate electrode thereon, is provided.
Taiwan Semiconductor Manufacturing Co., Ltd.
04/23/15
20150108577
new patent

Selective growth of a work-function metal in a replacement metal gate of a semiconductor device


Approaches for forming a replacement metal gate (rmg) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-fet) and an n-channel field effect transistor (n-fet) formed over a substrate, the p-fet and the n-fet each having a recess formed therein, a high-k layer and a barrier layer formed within each recess, a work-function metal (wfm) selectively grown within the recess of the n-fet, wherein the high-k layer, barrier layer, and wfm are each recessed to a desired height within the recesses, and a metal material (e.g., tungsten) formed within each recess.
Globalfoundries Inc.
04/23/15
20150108574
new patent

Semiconductor device and forming the same


A semiconductor device has a semiconductor substrate including a cell region and a peripheral region and includes: a silicon-metal-silicon (sms)-structured wafer formed in the cell region, which includes a stacked structure of a first silicon substrate, a metal layer, and a second silicon substrate; and a silicon on insulator (soi)-structured wafer formed in the peripheral region, which includes a stacked structure of the first silicon substrate, a silicon insulation film, and the second silicon substrate.. .
Sk Hynix Inc.
04/23/15
20150108573
new patent

Semiconductor device including vertically spaced semiconductor channel structures and related methods


A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material.
Stmicroelectronics, Inc.
04/23/15
20150108571
new patent

Self-aligned maskless junction butting for integrated circuits


A method for forming a semiconductor device includes forming gate stacks on a crystalline semiconductor layer; depositing a spacer layer over a top and sidewalls of the gate stacks; recessing the semiconductor layer between the gates stacks; and depositing a non-conformal layer over the gates stacks and within the recesses such that the non-conformal layer forms a pinch point over the recesses. The non-conformal layer is etched at a bottom of the recesses through the pinch point to expose the semiconductor layer.
International Business Machines Corporation
04/23/15
20150108570
new patent

Semiconductor device


A transistor having a trench gate is controlled such that values settable as on current of the transistor are not discrete. A first transistor includes a plurality of first trenches, a first gate insulating film, and a first gate electrode.
Renesas Electronics Corporation
04/23/15
20150108569
new patent

Method of forming a semiconductor device including trench termination and trench structure therefor


In an embodiment, a method of forming a semiconductor may include forming a plurality of active trenches and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches. The method may also include forming at least one active trench of the plurality of active trenches having corners linking trench ends to sides of active trenches wherein each active trench of the plurality of active trenches has a first profile along the first length and a second profile at or near the trench ends; and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches and having a second profile wherein one of the first profile or the second profile includes a non-linear shape..
Semiconductor Components Industries, Llc
04/23/15
20150108568
new patent

Semiconductor structure with high energy dopant implantation


A semiconductor device has an epitaxial layer grown over a substrate, each having a first dopant type. A structure disposed within the epitaxial layer has multiple trenches, each of which has a gate and a source electrode disposed within a shield oxide matrix.
Vishay-siliconix
04/23/15
20150108566
new patent

Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls


A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer.
Micron Technology, Inc.
04/23/15
20150108565
new patent

Power semiconductor devices, structures, and related methods


Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.. .
Maxpower Semiconductor Inc.
04/23/15
20150108564
new patent

Semiconductor device and manufacturing same


A source region of a mosfet includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region.
Mitsubishi Electric Corporation
04/23/15
20150108562
new patent

Three-dimensional charge trapping nand cell with discrete charge trapping film


A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole.
Spansion Llc
04/23/15
20150108561
new patent

Semiconductor device and fabricating the same


Provided is a semiconductor device and a method of fabricating the same. The method may include forming trenches in a substrate and lower gate patterns on the substrate between the trenches, forming sacrificial patterns filling the trenches, forming a porous insulating layer on the lower gate patterns to cover top surfaces of the sacrificial patterns, removing the sacrificial patterns through pores of the porous insulating layer to form air gaps surrounded by the trenches and the porous insulating layer, and forming a liner insulating layer on inner surfaces of the trenches through the pores of the porous insulating layer..
Samsung Electronics Co., Ltd.
04/23/15
20150108559
new patent

Method of fabricating a tunnel oxide layer and a tunnel oxide layer for a semiconductor device


A method of fabricating a tunnel oxide layer for a semiconductor memory device, the method comprising: fabricating on a substrate a first oxide layer by an in-situ-steam-generation process; and fabricating at least one further oxide layer by a furnace oxidation process, wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer.. .
X-fab Semiconductor Foundries Ag
04/23/15
20150108557
new patent

Metal-insulator-metal capacitor structure


A capacitor structure in a semiconductor device includes a semiconductor substrate having a top surface and a bottom surface opposite the top surface, an isolation region having a top surface and a bottom surface, opposite the top surface, the bottom surface of the isolation region being disposed on the top surface of the semiconductor substrate. The capacitor structure also includes a gate terminal structure disposed on the top surface of the isolation region and a diffusion contact structure disposed on the top surface of the isolation region and arranged parallel to the gate terminal structure.
Broadcom Corporation
04/23/15
20150108556
new patent

Semiconductor device and driving method thereof


A semiconductor device includes a photodiode, a first transistor, a second transistor, and a third transistor. The second transistor and the third transistor have a function of retaining a charge accumulated in a gate of the first transistor.
Semiconductor Energy Laboratory Co., Ltd.
04/23/15
20150108553
new patent

Semiconductor device


A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.. .
United Microelectronics Corp.
04/23/15
20150108552
new patent

Semiconductor device


In a cross section in a channel width direction, a semiconductor layer includes a first region of which one end portion is in contact with an insulating layer and which is positioned at one side portion of the semiconductor layer; a second region of which one end portion is in contact with the other end portion of the first region and which is positioned at an upper portion of the semiconductor layer; and a third region of which one end portion is in contact with the other end portion of the second region and the other end portion is in contact with the insulating layer and which is positioned at the other side portion of the semiconductor layer. In the second region, an interface with a gate insulating film is convex and has three regions respectively having curvature radii r1, r2, and r3 that are connected in this order from the one end portion side toward the other.
Semiconductor Energy Laboratory Co., Ltd.
04/23/15
20150108549
new patent

Formation of a high aspect ratio trench in a semiconductor substrate and a bipolar semiconductor device having a high aspect ratio trench isolation region


Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening.
International Business Machines Corporation
04/23/15
20150108543
new patent

Source/drain structure of semiconductor device


The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a cavity below the major surface; a gate stack on the major surface of the substrate; a spacer adjoining one side of the gate stack; a shallow trench isolations (sti) region disposed on the side of the gate stack, wherein the sti region is within the substrate; and a source/drain (s/d) structure distributed between the gate stack and sti region, wherein the s/d structure comprises a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; and a s/d extension disposed between the substrate and strained material, wherein the s/d extension comprises a portion extending below the spacer and substantially vertical to the major surface..
Taiwan Semiconductor Manufacturing Company, Ltd.
04/23/15
20150108541
new patent

Semiconductor device


A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of igbts (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an igbt located at an extreme end in the one direction and an igbt located more centrally than the igbt located at the extreme end.
Renesas Electronics Corporation
04/23/15
20150108540
new patent

Semiconductor device


A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess that extends from an upper surface of the fourth semiconductor region and reaches the second semiconductor region with penetrating the fourth semiconductor region and the third semiconductor region; a control electrode, which is arranged on the insulation film on a side surface of the recess and faces the third semiconductor region; a first main electrode, which is electrically connected to the first semiconductor region, and a second main electrode, which is electrically connected to the fourth semiconductor region, wherein a ratio of a width of the recess to a width of the third semiconductor region contacting the second main electrode is 1 or larger.. .
Sanken Electric Co., Ltd.
04/23/15
20150108539
new patent

Fabrication semiconductor device and the semiconductor device


A fabrication method of a semiconductor device includes forming a mask insulating film having a specified thickness on the top surface of an n-type semiconductor substrate, forming an opening at a specified position in the mask insulating film, carrying out ion implantation with p-type impurity ions onto the top surface, removing a layer portion formed in the mask insulating film with the p-type impurities included by the ion implantation, and carrying out heat treatment to diffuse the p-type impurities implanted into the n-type semiconductor substrate from the opening to a depth, thereby forming the p-type isolation region.. .
Fuji Electric Co., Ltd.
04/23/15
20150108517
new patent

Light emitting module and lighting apparatus having the same


A light emitting module according to an exemplary embodiment of the present invention includes a printed circuit board (pcb) and first through m-th lighting blocks (‘m’ is an integer greater than one). The pcb has wiring patterns electrically connecting optical semiconductor devices.
Posco Led Company Ltd.
04/23/15
20150108504
new patent

Method for producing 3c-sic epitaxial layer, 3c-sic epitaxial substrate, and semiconductor device


A 3c-sic epitaxial layer is produced by a production method including: epitaxially growing a first 3c-sic layer on a si substrate; oxidizing the first 3c-sic layer; removing an oxide film on a surface of the 3c-sic layer; and epitaxially growing a second 3c-sic layer on the 3c-sic layer after the oxide film is removed.. .
Seiko Epson Corporation
04/23/15
20150108503
new patent

Semiconductor device and manufacturing same


A semiconductor device of the present disclosure includes a semiconductor layer provided on a main surface of a substrate. A cell region is provided with a gate insulating film disposed on the semiconductor layer and a gate electrode disposed on the gate insulating film, and a wiring region is provided with a field insulating film disposed on the semiconductor layer and a gate wire disposed on the field insulating film.
Panasonic Intellectual Property Management Co., Ltd.
04/23/15
20150108501
new patent

Semiconductor device


In an active region, p+ regions are selectively disposed in a surface layer of an n− drift layer on an n+ semiconductor substrate. A p-base layer is disposed on surfaces of the n− drift layer and the p+ regions, and an mos structure is disposed on the p-base layer.
Fuji Electric Co., Ltd.
04/23/15
20150108500
new patent

Semiconductor device and manufacturing the same


A semiconductor device comprises a semiconductor body of a first semiconductor material, wherein at least a part of the semiconductor body constitutes a drift zone of a first conductivity type. The semiconductor device further comprises a channel layer structure comprising a semiconductor heterojunction between first and second semiconductor layers electrically coupled to the drift zone.
Infineon Technologies Austria Ag
04/23/15
20150108499
new patent

Semiconductor devices with graphene nanoribbons


Semiconductor devices with graphene nanoribbons and methods of manufacture are disclosed. The method includes forming at least one layer of si material on a substrate.
International Business Machines Corporation
04/23/15
20150108487
new patent

Semiconductor device and manufacturing method thereof


A means of forming unevenness for preventing specular reflection of a pixel electrode, without increasing the number of process steps, is provided. In a method of manufacturing a reflecting type liquid crystal display device, the formation of unevenness (having a radius of curvature r in a convex portion) in the surface of a pixel electrode is performed by the same photomask as that used for forming a channel etch type tft, in which the convex portion is formed in order to provide unevenness to the surface of the pixel electrode and give light scattering characteristics..
Semiconductor Energy Laboratory Co., Ltd.
04/23/15
20150108478
new patent

Semiconductor device and manufacturing the same


An object is to provide a method for manufacturing a highly reliable semiconductor device including thin film transistors which have stable electric characteristics and are formed using an oxide semiconductor. A method for manufacturing a semiconductor device includes the steps of: forming an oxide semiconductor film over a gate electrode with a gate insulating film interposed between the oxide semiconductor film and the gate electrode, over an insulating surface; forming a first conductive film including at least one of titanium, molybdenum, and tungsten, over the oxide semiconductor film; forming a second conductive film including a metal having lower electronegativity than hydrogen, over the first conductive film; forming a source electrode and a drain electrode by etching of the first conductive film and the second conductive film; and forming an insulating film in contact with the oxide semiconductor film, over the oxide semiconductor film, the source electrode, and the drain electrode..
Semiconductor Energy Laboratory Co., Ltd.
04/23/15
20150108476
new patent

Semiconductor device


Provided is a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and which does not have a limitation on the number of writing. The semiconductor device includes both a memory circuit including a transistor including an oxide semiconductor (in a broader sense, a transistor whose off-state current is sufficiently small), and a peripheral circuit such as a driver circuit including a transistor including a material other than an oxide semiconductor (that is, a transistor capable of operating at sufficiently high speed).
Semiconductor Energy Laboratory Co., Ltd.
04/23/15
20150108475
new patent

Semiconductor device and manufacturing the same


To improve the electrical characteristics of a semiconductor device including an oxide semiconductor, and to provide a highly reliable semiconductor device with a small variation in electrical characteristics. The semiconductor device includes a first insulating film, a first barrier film over the first insulating film, a second insulating film over the first barrier film, and a first transistor including a first oxide semiconductor film over the second insulating film.
Semiconductor Energy Laboratory Co., Ltd.
04/23/15
20150108473
new patent

Semiconductor device, manufacturing the same, and etchant used for the same


A method for manufacturing a semiconductor device includes the steps of forming a first conductive film over a substrate; forming an insulating film over the first conductive film; forming an oxide semiconductor film over the insulating film to overlap with the first conductive film; forming a second conductive film including a metal film containing molybdenum as its main component and a metal film containing copper as its main component over the oxide semiconductor film; and etching the second conductive film by an etchant. At the time of etching the second conductive film by the etchant, the oxide semiconductor film is used as an etching stopper film.
Semiconductor Energy Laboratory Co., Ltd.
04/23/15
20150108472
new patent

Semiconductor device


A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided.
Semiconductor Energy Laboratory Co., Ltd.
04/23/15
20150108470
new patent

Semiconductor device


To provide a semiconductor device that is suitable for miniaturization. The semiconductor device includes a first transistor, a second transistor over the first transistor, a barrier layer between the first transistor and the second transistor, a first electrode between the first transistor and the barrier layer, and a second electrode between the hairier layer and the second transistor and overlapping the first electrode with the barrier layer therebetween.
Semiconductor Energy Laboratory Co., Ltd.
04/23/15
20150108467
new patent

Semiconductor device and display device


A semiconductor device (100) according to the present invention is a semiconductor device with a thin-film transistor (10), and includes: a gate electrode (62) which has been formed on a substrate (60) as a part of the thin-film transistor (10); a gate insulating layer (66) which has been formed on the gate electrode (62); an oxide semiconductor layer (68) which has been formed on the gate insulating layer (66); a source electrode (70s) and a drain electrode (70d) which have been formed on the oxide semiconductor layer (68); a protective layer (72) which has been formed on the oxide semiconductor layer (68), the source electrode (70s) and the drain electrode (70d); an oxygen supplying layer (74) which has been formed on the protective layer (72); and an anti-diffusion layer (78) which has been formed on the oxygen supplying layer (74).. .
Sharp Kabushiki Kaisha
04/23/15
20150108431
new patent

Multilayer transition metal dichalcogenide device, and semiconductor device using same


The present invention relates to a multilayer transition metal dichalcogenide device and a semiconductor device using the same, wherein the invention, preferably comprising three or more layers, is formed with a conventional single-layered transition metal chalcogenide, thereby enabling absorption of the light over a wide wavelength range from ultraviolet rays to near infrared rays. To this end, disclosed is a transition metal dichalcogenide formed to allow absorption of the light over a relatively wider wavelength range compared with a single-layered transition metal chalcogenide, and a transition metal dichalcogenide device having a semiconductor channel formed by a transition metal dichalcogenide..
University-industry Cooperation Group Of Kyung Hee University
04/23/15
20150108427
new patent

Growth of cubic crystalline phase strucure on silicon substrates and devices comprising the cubic crystalline phase structure


A semiconductor device is disclosed. The semiconductor device includes a substrate comprising a groove.
Stc. Unm


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