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Semiconductor Device patents



      
           
This page is updated frequently with new Semiconductor Device-related patent applications. Subscribe to the Semiconductor Device RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Device RSS RSS


Split gate flash cell semiconductor device

Wafertech,llc

Split gate flash cell semiconductor device

Semiconductor device and method for manufacturing the same

Semiconductor device and method for manufacturing the same

Semiconductor device and method for manufacturing the same

Sawtooth electric field drift region structure for power semiconductor devices

Date/App# patent app List of recent Semiconductor Device-related patents
03/26/15
20150089261
 Information processing device and semiconductor device patent thumbnailnew patent Information processing device and semiconductor device
According to an embodiment, an information processing device includes a memory device, one or more peripheral devices, a processor, and a state controller. The processor is able to change between a first state, in which a command is executed, and a second state, in which an interrupt is awaited.
Kabushiki Kaisha Toshiba
03/26/15
20150087247
 Semiconductor device and wireless communication device patent thumbnailnew patent Semiconductor device and wireless communication device
A semiconductor device according to the present invention includes two diodes connected in parallel between power supplies, and a resistor circuit and a capacitance element connected in parallel between one power supply and each of the two diodes, and outputs a comparison result between voltages outputted from the two resistor circuits as a reset signal.. .
03/26/15
20150087160
 Substrate processing apparatus,  manufacturing semiconductor device, and recording medium patent thumbnailnew patent Substrate processing apparatus, manufacturing semiconductor device, and recording medium
A substrate processing apparatus includes: a processing gas supply pipe configured to supply a processing gas into a processing chamber; a substrate mounting table that is installed in the processing chamber and on which a substrate to be processed is mounted; a driving unit configured to drive the substrate mounting table to move the substrate mounted on the substrate mounting table; a first plasma generating unit configured to generate plasma of the processing gas supplied into the processing chamber with a first density; and a second plasma generating unit that is installed adjacent to the first plasma generating unit in a traveling direction of the substrate and configured to generate plasma of the processing gas supplied into the processing chamber with a second density lower than the first density.. .
Hitachi Kokusai Electric Inc.
03/26/15
20150087159
 Substrate processing apparatus,  manufacturing semiconductor device and non-transitory computer readable recording medium patent thumbnailnew patent Substrate processing apparatus, manufacturing semiconductor device and non-transitory computer readable recording medium
Provided is a technique of efficiently purging source gases remaining on a substrate and improving in-plane uniformity of a substrate. A method of processing a substrate includes forming a thin film on a substrate accommodated in a process chamber by (a) supplying a source gas into the process chamber, and (b) supplying an inert gas into the process chamber while alternately increasing and decreasing a flow rate of the inert gas supplied into the process chamber and exhausting the source gas and the inert gas from the process chamber..
Hitachi Kokusai Electric Inc.
03/26/15
20150087156
 Etching method, and  producing semiconductor substrate product and semiconductor device using the same, as well as kit for preparation of etching liquid patent thumbnailnew patent Etching method, and producing semiconductor substrate product and semiconductor device using the same, as well as kit for preparation of etching liquid
A method of etching a semiconductor substrate, having the steps of: preparing an etching liquid by mixing a first liquid with a second liquid to be in the range of ph from 8.5 to 14, the first liquid containing a basic compound, the second liquid containing an oxidizing agent; and then applying the etching liquid to a semiconductor substrate on a timely basis for etching a ti-containing layer in or on the semiconductor substrate.. .
Fujifilm Corporation
03/26/15
20150087144
 Apparatus and  manufacturing metal gate semiconductor device patent thumbnailnew patent Apparatus and manufacturing metal gate semiconductor device
A method of manufacturing a semiconductor device includes providing a semiconductor substrate and forming a structure over the semiconductor substrate. The structure includes a sacrificial dielectric on the semiconductor substrate and a dummy gate over the sacrificial dielectric.
Taiwan Semiconductor Manufacturing Company Ltd.
03/26/15
20150087132
 Wafer processing patent thumbnailnew patent Wafer processing
semiconductor device and method for forming a semiconductor device are presented. A substrate having top and bottom pad stacks is provided.
Globalfoundries Singapore Pte. Ltd.
03/26/15
20150087128
 Method of manufacturing a semiconductor device that includes a misfet patent thumbnailnew patent Method of manufacturing a semiconductor device that includes a misfet
An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film.
Renesas Electronics Corporation
03/26/15
20150087125
 Method of manufacturing semiconductor device patent thumbnailnew patent Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device of an embodiment includes: preparing a substrate; and growing a p-type sic single-crystal layer on the surface of the substrate from a liquid phase that contains si (silicon), c (carbon), a p-type impurity, and an n-type impurity, the p-type impurity being an element a, the n-type impurity being an element d, the element a and the element d forming a first combination that is at least one combination selected from al (aluminum) and n (nitrogen), ga (gallium) and n (nitrogen), and in (indium) and n (nitrogen), and/or a second combination of b (boron) and p (phosphorus), the ratio of the concentration of the element d to the concentration of the element a in the first or second combination being higher than 0.33 but lower than 1.0.. .
Kabushiki Kaisha Toshiba
03/26/15
20150087124
 Semiconductor device and  manufacturing the same patent thumbnailnew patent Semiconductor device and manufacturing the same
According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth semiconductor region, a control electrode, and an insulating film. The first region contains silicon carbide.
Kabushiki Kaisha Toshiba
03/26/15
20150087122
new patent

Manufacturing semiconductor device


Provided is a semiconductor device that can be manufactured at low cost and that can reduce a reverse leak current, and a manufacturing method thereof. A semiconductor device has: a source region and a drain region having a body region therebetween; a source trench that reaches the body region, penetrating the source region; a body contact region formed at the bottom of the source trench; a source electrode embedded in the source trench; and a gate electrode that faces the body region.
Rohm Co., Ltd.
03/26/15
20150087120
new patent

Raised source/drain and gate portion with dielectric spacer or air gap spacer


A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes epitaxial raised source/drain (rsd) regions formed on the surface of a semiconductor substrate through selective epitaxial growth.
International Business Machines Corporation
03/26/15
20150087119
new patent

Compound semiconductor device, manufacturing the same, power supply device and high-frequency amplifier


A compound semiconductor device includes a substrate having an opening formed from the rear side thereof; a compound semiconductor layer disposed over the surface of the substrate; a local p-type region in the compound semiconductor layer, partially exposed at the end of the substrate opening; and a rear electrode made of a conductive material, disposed in the substrate opening so as to be connected to the local p-type region.. .
Fujitsu Limited
03/26/15
20150087117
new patent

Power semiconductor device and manufacturing the same


Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction.. .
Samsung Electro-mechanics Co., Ltd.
03/26/15
20150087116
new patent

Sawtooth electric field drift region structure for power semiconductor devices


This invention discloses a semiconductor power device formed in a semiconductor substrate includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*nd*wn=q*na*wp and a punch through condition of wp<2*wd*[nd/(na+nd)] where nd and wn represent the doping concentration and the thickness of the n type layers 160, while na and wp represent the doping concentration and thickness of the p type layers; wd represents the depletion width; and q represents an electron charge, which cancel out.
03/26/15
20150087113
new patent

Electrically isolated power semiconductor package with optimized layout


A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object.
Ixys Corporation
03/26/15
20150087112
new patent

Manufacturing the semiconductor device


The semiconductor device is manufactured through the following steps: after first heat treatment is performed on an oxide semiconductor film, the oxide semiconductor film is processed to form an oxide semiconductor layer; immediately after that, side walls of the oxide semiconductor layer are covered with an insulating oxide; and in second heat treatment, the side surfaces of the oxide semiconductor layer are prevented from being exposed to a vacuum and defects (oxygen deficiency) in the oxide semiconductor layer are reduced.. .
Semiconductor Energy Laboratory Co., Ltd.
03/26/15
20150087111
new patent

3 dimensional semiconductor device and manufacturing the same


A 3d semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes..
Sk Hynix Inc.
03/26/15
20150087110
new patent

Low-temperature fabrication of spray-coated metal oxide thin film transistors


The present teachings relate to a method of enabling metal oxide film growth via solution processes at low temperatures (≦350° c.) and in a time-efficient manner. The present thin films are useful as thin film semiconductors, thin film dielectrics, or thin film conductors, and can be implemented into semiconductor devices such as thin film transistors and thin film photovoltaic devices..
Polyera Corporation
03/26/15
20150087109
new patent

Dyketopyrrolopyrrole polymers for use in organic semiconductor devices


The present invention relates to polymers comprising one or more (repeating) unit(s) of the formula *a-d* (i), or a polymer of formula *a-dxb-dy* (ii), or *a-drb-dsa-etb-eu (iii), and their use as organic semiconductor in organic devices, especially in organic photovoltaics (solar cells) and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties.
Basf Se
03/26/15
20150087101
new patent

Method for forming semiconductor device


A method for forming a semiconductor device includes providing a wafer having a plurality of chip regions, in which each chip region includes a sensing array on a front side of the wafer. A plurality of through silicon vias is formed in the wafer from a back side of the wafer, in which the plurality of through silicon vias is electrically connected to the plurality of sensing arrays.
Silicon Optronics, Inc.
03/26/15
20150087091
new patent

Manufacturing method and test semiconductor device


Provided is a test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a bt test. Provided is to detect a transistor whose reliability is high in a shorter period of time than a bt test and manufacture an electronic device with high reliability efficiently.
Semiconductor Energy Laboratory Co., Ltd.
03/26/15
20150087090
new patent

Monitor test key of epi profile


A method and apparatus for estimating a height of an epitaxially grown semiconductor material in other semiconductor devices. The method includes epitaxially growing first, second, and third portions of semiconductor material on a first semiconductor device, measuring a height of the third portion of semiconductor material and a height of the first or second portion of semiconductor material, measuring a first saturation current through the first and second portions of semiconductor material, measuring a second saturation current through the first and third portions of semiconductor material, and preparing a model of the first saturation current relative to the height of the first or second portion of semiconductor material and the second saturation current relative to an average of the height of the first and third portions of semiconductor material.
Taiwan Semiconductor Manufacturing Company, Ltd.
03/26/15
20150087083
new patent

Bonding apparatus and manufacturing semiconductor device


Chips (20) and (30); and a control unit (50) having a relative-position detection program (53) for detecting relative positions of the first-layer of the semiconductor chip (20) and the second-layer of the semiconductor chip (30) that are stacked and bonded based on an image of the first through-silicon vias on a surface of the first-layer of the semiconductor chip (20) taken by the double-view camera (16) before stacked bonding, and an image of the second through-silicon vias on a surface of the second-layer of the semiconductor chip (30) taken by the double-view camera (16) after stacked bonding. This provides accurate connection between through-silicon vias using a simple method..
03/26/15
20150087082
new patent

Selective heating during semiconductor device processing to compensate for substrate uniformity variations


In some embodiments, a system includes (1) a controller configured to receive information regarding substrate uniformity; (2) a processing tool configured to perform a semiconductor device manufacturing process on a substrate; and (3) a laser delivery mechanism coupled to the controller, the laser delivery mechanism configured to selectively deliver laser energy to the substrate during processing within the processing tool so as to selectively heat the substrate during processing. The controller is configured to employ the substrate uniformity information to determine a temperature profile to apply to the substrate during processing within the processing tool and to employ the laser delivery mechanism to selectively heat the substrate during processing within the processing tool based on the temperature profile.
Applied Materials, Inc.
03/26/15
20150086912
new patent

Actinic ray-sensitive or radiation-sensitive resin composition, resist film and pattern forming method using the same, manufacturing semiconductor device, and semiconductor device


There is provided an actinic ray-sensitive or radiation-sensitive resin composition comprising (p) a resin having a repeating unit (a) represented by the specific formula (i) capable of generating an acid on the side chain of the resin upon irradiation with an actinic ray or radiation, and a resist film formed with the actinic ray-sensitive or radiation-sensitive resin composition, and a pattern forming method comprising: exposing the resist film, and developing the exposed resist film, and a method for manufacturing a semiconductor device, containing the pattern forming method, and a semiconductor device manufactured by the manufacturing method of the semiconductor device.. .
Fujifilm Corporation
03/26/15
20150085913
new patent

Data receiving circuit and semiconductor device


A data receiving circuit that can accurately obtain a data signal corresponding to information data from a high speed high density transmitted signal, and a semiconductor device including the data receiving circuit. The amplitude of a first differential signal corresponding to a level difference between a pair of received differential signals, generated in a first differential stage, is amplified and binalized to obtain a received data signal.
Lapis Semiconductor Co., Ltd.
03/26/15
20150085888
new patent

Method for manufacturing semiconductor device and semiconductor device


To improve characteristics of a semiconductor device (semiconductor laser), an active layer waveguide (awg) comprised of inp is formed over an exposed part of a surface of a substrate having an off angle ranging from 0.5° to 1.0° in a [1-1-1] direction from a (100) plane to extend in the [0-1-1] direction. A cover layer comprised of p-type inp is formed over the awg with a v/iii ratio of 2000 or more.
Renesas Electronics Corporation
03/26/15
20150085596
new patent

Semiconductor devices having multi-channel regions and semiconductor systems including the same


The semiconductor device includes a first channel region suitable for including a first pad region and a first core region and receiving a first power signal through a first power line, a second channel region suitable for including a second pad region and a second core region and receiving the first power signal through a second power line, and a switch unit suitable for electrically disconnecting the second power line from a first power stabilization unit if a predetermined operation of the first channel region is performed and electrically disconnecting the first power line from the first power stabilization unit if the predetermined operation of the second channel region is performed.. .
Sk Hynix Inc.
03/26/15
20150085590
new patent

Semiconductor devices and semiconductor systems including the same


Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device.
Sk Hynix Inc.
03/26/15
20150085561
new patent

Semiconductor device and write method


A semiconductor device includes a memory cell array including a plurality of first and second memory cells each comprising a variable resistance element that establishes an electrical resistance that changes in response to an application of a write voltage after a forming voltage has been applied, the first memory cell to which the forming voltage is applied, and the second memory cell to which the forming voltage is not applied, and the second memory cell being configured to store one of first and second logic values constituting first information, the first and second logic values being different from each other.. .
Micron Technology, Inc.
03/26/15
20150084846
new patent

Semiconductor device, liquid crystal display panel, and mobile information terminal


A semiconductor device includes a plurality of sets of external drive terminals in a marginal region along one long side of a rectangular semiconductor substrate, a plurality of sets of esd protection circuits arranged in the marginal region and coupled to corresponding sets of the drive terminals, and a plurality of output circuits coupled to corresponding sets of the drive terminals. Each set of drive terminals in a plurality of n columns along a y direction is laid out in a staggered arrangement with drive terminals in adjacent columns shifted relative to each other.
Renesas Electronics Corporation
03/26/15
20150084796
new patent

Semiconductor device


The present invention realizes reliably control so that, at the time of ad converting reference voltage, a low-voltage transistor in a reference voltage generating circuit is not destroyed by voltage held in a sample and hold circuit. In a semiconductor device, when an instruction of detecting a reference voltage value is received, a switch control unit controlling switching of an input signal of an internal ad converter temporarily automatically couples an input node of a sample and hold circuit and a ground node and, after that, couples the input node of the sample and hold circuit and an output node of a reference voltage generating circuit..
Renesas Electronics Corporation
03/26/15
20150084717
new patent

Measurement device, semiconductor device and impedance adjustment method


A measurement device includes an electric current generation circuit and a monitor device. The electric current generation circuit supplies an electric current whose electric current amount monotonically increases during a setup period of time to the electric circuit including a power supply.
Nec Corporation
03/26/15
20150084684
new patent

Temperature dependent biasing for leakage power reduction


Temperature dependent biasing for leakage power reduction. In some embodiments, a semiconductor device may include a biasing circuit configured to generate a voltage that varies dependent upon a temperature of the semiconductor device and a logic circuit operably coupled to the biasing circuit, where the voltage is applied to a bulk terminal of one or more transistors within the logic circuit, and where the voltage has a value outside of a voltage supply range of the logic circuit.
Freescale Semiconductor, Inc.
03/26/15
20150084668
new patent

Semiconductor device and semiconductor system including the same


A semiconductor device includes a test control unit suitable for activating an on-die termination signal in response to a control signal activated in a test mode, and a data mask pad suitable for pull-down driving a data mask signal when the on-die termination signal is activated.. .
Sk Hynix Inc.
03/26/15
20150084667
new patent

Method and system for testing semiconductor device


A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing.. .
Sk Hynix Inc.
03/26/15
20150084665
new patent

Method and system for testing semiconductor device


A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing.. .
Sk Hynix Inc.
03/26/15
20150084662
new patent

Apparatus and terminating probe apparatus of semiconductor wafer


A probe apparatus and method of terminating a probe that probes a semiconductor device with a signal cable from a tester site by site at a proximal end of the probe and a distal end of the signal cable. In one embodiment, the probe apparatus includes: a chassis; a dielectric block mounted in the chassis for retaining the probe, the probe extending on the chassis from a proximal end of the probe to the dielectric block, extending through the dielectric block, and projecting from the dielectric block towards the semiconductor device at a distal end of the probe; and a terminating apparatus, mounted in the chassis, for terminating the proximal end of the probe with a distal end of the signal cable side by side..
Celadon Systems, Inc.
03/26/15
20150084657
new patent

Heating system and testing a semiconductor device using a heating system


A heating system is described for generating heat and bringing heat to a semiconductor device under test. The heating system comprises a conduction heating unit comprising a heating resistor, a thermal contact area for thermally contacting the semiconductor device under test, and a thermally conductive and electrically insulating connection between the heating resistor and the thermal contact area.
Freescale Semiconductor, Inc.
03/26/15
20150084213
new patent

Semiconductor device and controlling warpage in reconstituted wafer


A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape.
Stats Chippac, Ltd.
03/26/15
20150084209
new patent

Semiconductor device


A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part.
Renesas Electronics Corporation
03/26/15
20150084208
new patent

Connection member, semiconductor device, and stacked structure


A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and a second metal plane provided n or on the dielectric material in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane.. .
Kabushiki Kaisha Toshiba
03/26/15
20150084207
new patent

Embedded semiconductor device package and manufacturing thereof


A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s).
General Electric Company
03/26/15
20150084206
new patent

Semiconductor device and forming dual fan-out semiconductor package


A semiconductor device has a semiconductor die with a first encapsulant disposed over the semiconductor die. A first build-up interconnect structure is formed over the semiconductor die and first encapsulant.
Stats Chippac, Ltd.
03/26/15
20150084205
new patent

Chip package and forming the same


A semiconductor device comprises a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate and the insulation layer.
Nanya Technology Corporation
03/26/15
20150084204
new patent

Semiconductor device and fabricating the same


Provided are a semiconductor device and a method of fabricating the same. The device may include a substrate including a cell array region and a peripheral circuit region, stacks on the cell array region of the substrate, the stacks having a first height and extending along a direction, a common source structure disposed between adjacent ones of the stacks, a peripheral logic structure disposed on the peripheral circuit region of the substrate and having a second height smaller than the first height, a plurality of upper interconnection lines disposed on the peripheral logic structure and extending parallel to each other, and a interconnection structure disposed between the peripheral logic structure and the upper interconnection lines, when viewed in vertical section, and electrically connected to at least two of the upper interconnection lines..
03/26/15
20150084197
new patent

Semiconductor packages and methods of packaging semiconductor devices


Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate.
United Test And Assembly Center Ltd.
03/26/15
20150084195
new patent

Semiconductor device having features to prevent reverse engineering


An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.. .
Secure Silicon Layer, Inc.
03/26/15
20150084193
new patent

Embedded on-chip security


Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (puf), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate.
International Business Machines Corporation
03/26/15
20150084187
new patent

Methods of forming hydrophobic surfaces on semiconductor device structures, methods of forming semiconductor device structures, and semiconductor device structures


A method of forming a hydrophobic surface on a semiconductor device structure. The method comprises forming at least one structure having at least one exposed surface comprising titanium atoms.
Micron Technology, Inc.
03/26/15
20150084185
new patent

Semiconductor device with a semiconductor die embedded between an extended substrate and a bottom substrate


A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member.
Amkor Technology, Inc.
03/26/15
20150084184
new patent

Semiconductor device


A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted.
Ps4 Luxco S.a.r.l.
03/26/15
20150084180
new patent

Semiconductor device including heat dissipating structure


A semiconductor device includes a substrate serving as a base and having a surface on which electrodes are provided, a semiconductor chip mounted to the surface of the substrate, a sealing portion sealing the semiconductor chip and the surface of the substrate, first vias each penetrating the sealing portion in a thickness direction of the sealing portion to reach the electrodes on the surface of the substrate, external terminals connected to the first vias, and second vias provided near the semiconductor chip, extending to such a depth that the second vias do not penetrate the sealing portion, and insulated from the substrate and the semiconductor chip.. .
Panasonic Corporation
03/26/15
20150084177
new patent

Lead frame for mounting led elements, lead frame with resin, manufacturing semiconductor devices, and lead frame for mounting semiconductor elements


A lead frame for mounting led elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an led element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region.
Dai Nippon Printing Co., Ltd.
03/26/15
20150084175
new patent

Semiconductor device leadframe


For so called film assisted moulding (fam) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion..
Nxp B.v.
03/26/15
20150084174
new patent

Semiconductor device leadframe


For so called film assisted moulding (fam) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion..
Nxp B.v.
03/26/15
20150084173
new patent

Semiconductor device and manufacturing the same


There is provided a semiconductor device having a converter circuit, a brake circuit and an inverter circuit and manufacturable by a simplified manufacturing process. The semiconductor device has a plurality of die pads, igbts, diodes, freewheel diodes, an hvic and lvics mounted on the plurality of die pads, a plurality of leads, and an encapsulation resin body that covers these component parts.
Mitsubishi Electric Corporation
03/26/15
20150084169
new patent

Semiconductor package with stress relief and heat spreader


A semiconductor device has a die mounted on a die paddle that is elevated above and thermally connected via tie bars to a heat sink structure. Heat generated by the die flows from the die to the die paddle to the tie bars to the heat sink structure and then to either the external environment or to an external heat sink.
03/26/15
20150084167
new patent

Ebg structure, semiconductor device, and circuit board


An ebg structure of an embodiment includes an electrode plane, a first insulating layer provided on the electrode plane, a first metal patch provided on the first insulating layer, a second metal patch provided on the first insulating layer, a second insulating layer provided on the first and second metal patches, an interconnect layer provided on the second insulating layer, a third insulating layer provided on the interconnect layer, a first via connected to the electrode plane and the first metal patch, and a second via connected to the electrode plane and the second metal patch. The second metal patch is separately adjacent to the first metal patch.
Kabushiki Kaisha Toshiba
03/26/15
20150084166
new patent

Semiconductor device having plural memory chip


A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip.
Ps4 Luxco S.a.r.l.
03/26/15
20150084164
new patent

Semiconductor device


The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side.
Renesas Electronics Corporation
03/26/15
20150084163
new patent

Epitaxial substrate, semiconductor device, and manufacturing semiconductor device


The present invention provides an epitaxial substrate including a silicon substrate containing oxygen atoms in concentrations of 4×1017 cm−3 or more and 6×1017 cm−3 or less and containing boron atoms in concentrations of 5×1018 cm−3 or more and 6×1019 cm−3 or less and a semiconductor layer that is placed on the silicon substrate and is made of a material having a thermal expansion coefficient different from the thermal expansion coefficient of the silicon substrate. As a result, the epitaxial substrate in which the occurrence of warpage caused by the stress between the silicon substrate and the semiconductor layer is suppressed is provided..
Shin-etsu Handotai Co., Ltd.
03/26/15
20150084160
new patent

Semiconductor device and manufacturing the same


A ferroelectric capacitor formed above a semiconductor substrate includes a lower electrode, a dielectric film (ferroelectric film) having ferroelectric characteristics, and an upper electrode. The upper electrode includes a conductive oxide film made of a ferroelectric material to which conductivity is provided by adding a conductive material such as ir, and the conductive oxide film is in contact with the dielectric film..
Fujitsu Semiconductor Limited
03/26/15
20150084159
new patent

Semiconductor device and manufacturing method thereof


The present invention is capable of suppressing a variation in the characteristics of a semiconductor device. In a conductor pattern cpa and a conductor pattern cpb arranged so as to run side by side with each other, the conductor pattern cpa is divided into a first portion p1 (a) and a second portion p2 (a), and the conductor pattern cpb is also divided into a first portion p1 (b) and a second portion p2 (b).
Renesas Electronics Corporation
03/26/15
20150084155
new patent

Semiconductor device and fabricating the same


A method for fabricating a semiconductor device includes defining a curved active region by forming a plurality of trenches over a semiconductor substrate, forming an insulating layer to fill the plurality of trenches, and forming a pair of gate lines crossing the curved active region, so that it is possible to prevent leaning of an active region by forming a curved active region.. .
Sk Hynix Inc.
03/26/15
20150084154
new patent

Methods and esd structures


Methods and apparatus for esd structures. A semiconductor device includes a first active area containing an esd cell coupled to a first terminal and disposed in a well; a second active area in the semiconductor substrate, the second active area comprising a first diffusion of the first conductivity type for making a bulk contact to the well; and a third active area in the semiconductor substrate, separated from the first and second active areas by another isolation region, a portion of the third active area comprising an implant diffusion of the first conductivity type within a first diffusion of the second conductivity type and adjacent a boundary with the well of the first conductivity type; wherein the third active area comprises a diode coupled to the terminal and reverse biased with respect to the well of the first conductivity type..
Taiwan Semiconductor Manufacturing Company, Ltd.
03/26/15
20150084141
new patent

Semiconductor device and manufacturing the same


According to one embodiment, a semiconductor device includes a mram chip including a semiconductor substrate and a memory cell array area includes magnetoresistive elements which are provided on the semiconductor substrate, and a magnetic shield layer surrounding the memory cell array area in a circumferential direction of the mram chip, and having a closed magnetic path.. .
Kabushiki Kaisha Toshiba
03/26/15
20150084138
new patent

Integrated circuit having varying substrate depth and forming same


A semiconductor device is formed such that a semiconductor substrate of the device has a non-uniform thickness. A cavity is etched at a selected side of the semiconductor substrate, and the selected side is then fusion bonded to another substrate, such as a carrier substrate.
Freescale Semiconductor, Inc.
03/26/15
20150084137
new patent

Mechanism for forming metal gate structure


Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a metal gate stack formed over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.
03/26/15
20150084135
new patent

Semiconductor device


A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points.
Renesas Electronics Corporation
03/26/15
20150084134
new patent

Finfet-based esd devices and methods for forming the same


A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other.
Taiwan Semiconductor Manufacturing Company, Ltd.
03/26/15
20150084131
new patent

Gate height uniformity in semiconductor devices


Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height..
Globalfoundries Inc.
03/26/15
20150084130
new patent

Semiconductor structure and manufacturing the same


The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing an soi substrate, onto which a heavily doped buried layer and a surface active layer are formed; forming a gate stack and sidewall spacers on the substrate; forming an opening at one side of the gate stack, wherein the opening penetrates through the surface active layer, the heavily doped buried layer and reaches into a silicon film located on an insulating buried layer of the soi substrate; filling the opening to form a plug; forming source/drain regions, wherein the source region overlaps with the heavily doped buried layer, and a part of the drain region is located in the plug. Accordingly, the present invention further provides a semiconductor structure.
Institute Of Microelectronics, Chinese Academy Of Sciences
03/26/15
20150084129
new patent

Dummy cell array for fin field-effect transistor device and semiconductor integrated circuit including the dummy cell array


A semiconductor device includes a substrate; a device area of the substrate, the device area including a plurality of device unit cells; and a dummy cell array arranged around the device area. The dummy cell array includes a plurality of dummy unit cells repeatedly arranged in a first direction and a second direction perpendicular to the first direction, each of the dummy cell unit having a structure corresponding to a device unit cell.
Samsung Electronics Co., Ltd.
03/26/15
20150084127
new patent

Semiconductor device and manufacturing the same


High integrity, lower power consuming semiconductor devices and methods for manufacturing the same. The semiconductor device includes: semiconductor substrate; a well region in the semiconductor substrate; an interlayer structure over the well region, the interlayer structure including a back gate conductor, semiconductor fins at both sides of the back gate conductor and respective back gate dielectric isolating the back gate conductor from the semiconductor fins, respectively, wherein the well region functions as one portion of a conductive path of the back gate conductor; a punch-through stop layer at a lower portion of the semiconductor fin; a front gate stack intersecting the semiconductor fin, the front gate stack including a front gate dielectric and a front gate conductor and the front gate dielectric isolating the front gate conductor from the semiconductor fin; and a source region and a drain region connected to a channel region provided by the semiconductor fin..
03/26/15
20150084124
new patent

Semiconductor device


A semiconductor device includes a semiconductor substrate having an element region and a termination region. The element region includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and first floating regions having the first conductivity type.
Denso Corporation
03/26/15
20150084123
new patent

Semiconductor device


A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess extending from an upper surface to the second semiconductor region; a control electrode, which is arranged on a region of the insulation film on a side surface of the recess; a first main electrode connected to the first semiconductor region; a second main electrode connected to the fourth semiconductor region; and a bottom electrode, which is arranged on the insulation film and is electrically connected to the second main electrode, and a length of the recess in an extension direction thereof is equal to or larger than a width of the recess, and the width of the recess is wider than an interval between the adjacent recesses.. .
Sanken Electric Co., Ltd.
03/26/15
20150084122
new patent

Semiconductor device


A semiconductor device has an active region defined by a device isolation region arranged on a surface of a semiconductor substrate, a plurality of transistor pillars arranged along a first direction within the active region, and a first dummy pillar disposed in the device isolation region. The first dummy pillar is arranged on a line extending along the first direction from the transistor pillars.
Micron Technology, Inc.
03/26/15
20150084120
new patent

Charge-compensation semiconductor device


An active area of a semiconductor body includes a first charge-compensation structure having spaced apart n-type pillar regions, and an n-type first field-stop region of a semiconductor material in ohmic contact with a drain metallization and the n-type pillar regions and having a doping charge per area higher than a breakdown charge per area of the semiconductor material. A punch-through area of the semiconductor body includes a p-type semiconductor region in ohmic contact with a source metallization, a floating p-type body region and an n-type second field-stop region.
Infineon Technologies Austria Ag
03/26/15
20150084119
new patent

Layout configurations for integrating schottky contacts into a power transistor device


A semiconductor device includes a vertical field-effect-transistor (fet) and a bypass diode. The vertical fet device includes a substrate, a drift layer formed over the substrate, a gate contact and a plurality of source contacts located on a first surface of the drift layer opposite the substrate, a drain contact located on a surface of the substrate opposite the drift layer, and a plurality of junction implants, each of the plurality of junction implants laterally separated from one another on the surface of the drift layer opposite the substrate and extending downward toward the substrate.
Cree, Inc.
03/26/15
20150084118
new patent

Semiconductor device including a power transistor device and bypass diode


A semiconductor device includes a vertical fet device and a schottky bypass diode. The vertical fet device includes a gate contact, a source contact, and a drain contact.
Cree, Inc.
03/26/15
20150084115
new patent

Semiconductor device


Provided is a semiconductor device including a plurality of pillar columns, each of the plurality of pillar columns including a plurality of pillars arranged in one direction to be offset from each other, wherein an mth pillar and an (m+1)th pillar, among the plurality of pillars included in each pillar column, are aligned with each other (m is an integer of 0 or more).. .
Sk Hynix Inc.
03/26/15
20150084113
new patent

Semiconductor device and manufacturing the same


It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto..
Kabushiki Kaisha Toshiba
03/26/15
20150084112
new patent

Split gate flash cell semiconductor device


A split gate flash cell device with floating gate transistors is provided. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source.
Wafertech,llc
03/26/15
20150084109
new patent

Semiconductor devices and methods of fabricating the same


A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.. .
Samsung Electronics Co., Ltd.
03/26/15
20150084104
new patent

Method of manufacturing a semiconductor device and the semiconductor device


Characteristics of a high electron mobility transistor are improved. A stack having an n-type contact layer (n-type algan layer), an electron supply layer (undoped algan layer), and a channel layer (undoped gan layer) is formed in a growth mode over a ga plane parallel with a [0001] crystal axis direction.
Renesas Electronics Corporation
03/26/15
20150084103
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes: a si substrate having first and second major surfaces facing in opposite directions; a buffer layer of alxga1-xn (0≦x≦1) on the first major surface of the si substrate; an epitaxially grown crystalline layer of alyga1-yn (0≦y≦1, x≠y) on the buffer layer; a transistor on the epitaxially grown crystalline layer; and a filler of alxga1-xn and having the same x as the buffer layer. A through hole in the si substrate extends from the second major surface to the buffer layer, and the through hole is filled with the filler..
Mitsubishi Electric Corporation
03/26/15
20150084102
new patent

Semiconductor device


The semiconductor device including: a semiconductor layer extending in a first direction, the semiconductor layer including a pair of source/drain regions and a channel region, a gate extending on the semiconductor layer to cover the channel region, and a gate dielectric layer interposed between the channel region and the gate, a corner insulating spacer having a first surface and a second surface, the first surface extending in the second direction along a side wall of the gate, the first surface covering from a side portion of the gate dielectric layer to at least a portion of the side wall of the gate, and the second surface covering a portion of the semiconductor layer, and an outer portion insulating spacer covering the side wall of the gate above the corner insulating spacer, the outer portion insulating spacer having a smaller dielectric constant than the corner insulating spacer, may be provided.. .
Samsung Electronics Co., Ltd.
03/26/15
20150084097
new patent

Semiconductor device and forming the same


A semiconductor device includes a substrate on which a plurality of logic cells are provided, and a plurality of active portions provided on the substrate and extending in a first direction. Contacts and gate structures extend in a second direction intersecting the first direction and are alternately arranged.
Samsung Electronics Co., Ltd.
03/26/15
20150084093
new patent

Semiconductor device


A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess extending from an upper surface to the second semiconductor region; a control electrode, which is arranged on a region of the insulation film on a side surface of the recess; a first main electrode connected to the first semiconductor region; a second main electrode connected to the fourth semiconductor region; and a bottom electrode, which is arranged on the insulation film and is electrically connected to the second main electrode, and a length of the recess in an extension direction thereof is equal to or larger than a width of the recess, and the width of the recess is wider than an interval between the adjacent recesses.. .
Sanken Electric Co., Ltd.
03/26/15
20150084068
new patent

Semiconductor device and manufacturing the same


A semiconductor device of an embodiment includes: an sic layer; a gate insulating film provided on a surface of the sic layer, the gate insulating film including an oxide film or an oxynitride film in contact with the surface of the sic layer, the oxide film or the oxynitride film containing at least one element selected from b, al, ga (gallium), in, sc, y, la, mg, ca, sr, and ba, a concentration peak of the element in the gate insulating film being on the sic side of the gate insulating film, the concentration peak of the element being in the oxide film or the oxynitride film, the gate insulating film having a region with a concentration of the element being not higher than 1×1016 cm−3 on the opposite side to the sic layer with the concentration peak; and a gate electrode on the gate insulating film.. .
Kabushiki Kaisha Toshiba
03/26/15
20150084067
new patent

Semiconductor device and manufacturing the same


The semiconductor device of this embodiment includes: a first region of a first conductivity type sic; a second region of a first conductivity type sic, impurity concentration of first conductivity type of the second region being lower than impurity concentration of first conductivity type of the first region; a third region of a second conductivity type sic provided between the first region and the second region; a si layer provided on surfaces of the first, second, and third regions, a thickness of-the si layer on the third region being thicker than a thickness of the si layer on the second region; a gate insulating film provided on the si layer; and a date electrode provided on the gate insulating film.. .
Kabushiki Kaisha Toshiba
03/26/15
20150084064
new patent

Semiconductor device and manufacturing the same


The semiconductor device has a gate electrode ge formed on a substrate via a gate insulating film gi and a source/drain semiconductor layer ep1 formed on the substrate. The upper surface of the semiconductor layer ep1 is positioned higher than the upper surface of the substrate straight below the gate electrode ge.
03/26/15
20150084063
new patent

Semiconductor device with a current spreading layer


A semiconductor device includes a substrate, a drift layer over the substrate, a spreading layer over the drift layer, and a pair of junction implants in a surface of the spreading layer opposite the drift layer. An anode covers the surface of the spreading layer opposite the drift layer, and a cathode covers a surface of the substrate opposite the drift layer.
Cree, Inc.
03/26/15
20150084059
new patent

Semiconductor device and manufacturing the same


A semiconductor device according to an embodiment includes a first gan based semiconductor layer of a first conductive type, a second gan based semiconductor layer of the first conductive type provided above the first gan based semiconductor layer, a third gan based semiconductor layer of a second conductive type provided above a part of the second gan based semiconductor layer, a epitaxially grown fourth gan based semiconductor layer of the first conductive type provided above the third gan based semiconductor layer, a gate insulating film provided on the second, third, and fourth gan based semiconductor layer, a gate electrode provided on the gate insulating film, a first electrode provided on the fourth gan based semiconductor layer, a second electrode provided at the side of the first gan based semiconductor layer opposite to the second gan based semiconductor layer, and a third electrode provided on the second gan based semiconductor layer.. .
Kabushiki Kaisha Toshiba
03/26/15
20150084051
new patent

Electronic device, test board, and semiconductor device manufacturing method


Electrical characteristics of a mounting board over which a semiconductor device is mounted is improved. A mounting board (wiring board) includes a plurality of first through holes and second through holes extending from its upper surface bearing a semiconductor device (semiconductor package) to its lower surface and through-hole wirings formed in the respective through holes.
Renesas Electronics Corporation
03/26/15
20150084050
new patent

Semiconductor device and manufacturing method thereof


Hydrogen concentration and oxygen vacancies in an oxide semiconductor film are reduced. Reliability of a semiconductor device which includes a transistor using an oxide semiconductor film is improved.
Semiconductor Energy Laboratory Co., Ltd.
03/26/15
20150084049
new patent

Method for manufacturing semiconductor device


An object is to provide a method for manufacturing a semiconductor device including an oxide semiconductor and having improved electric characteristics. The semiconductor device includes an oxide semiconductor film, a gate electrode overlapping the oxide semiconductor film, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.
03/26/15
20150084047
new patent

Semiconductor device


A semiconductor device including a transistor and a capacitor which occupies a small area is provided. The semiconductor device includes a semiconductor, a first and second conductive films each including a first region in contact with a top surface of the semiconductor and a second region in contact with a side surface of the semiconductor, a first insulating film including a third region in contact with the semiconductor, a third conductive film including a fourth region facing the semiconductor with the first insulating film therebetween, and a fourth conductive film comprising a sixth region facing the second region of the first conductive film with the second insulating film therebetween..
Semiconductor Energy Laboratory Co., Ltd.
03/26/15
20150084046
new patent

Semiconductor device


A semiconductor device including a transistor and a capacitor which occupies a small area is provided. The semiconductor device includes a semiconductor, first and second conductive films each comprising a region in contact with top and side surfaces of the semiconductor, a first insulating film comprising a region in contact with the top and side surfaces of the semiconductor, a third conductive film comprising a region facing the top and side surfaces of the semiconductor with the first insulating film therebetween, a second insulating film which is in contact with the first conductive film and comprises an opening, a fourth conductive film comprising a region in contact with the opening, a third insulating film comprising a region facing the opening with the fourth conductive film therebetween, and a fifth conductive film comprising a region facing the fourth conductive film with the third insulating film therebetween..
Semiconductor Energy Laboratory Co., Ltd.
03/26/15
20150084045
new patent

Semiconductor device


An oxide semiconductor film with a low density of defect states is formed. In addition, an oxide semiconductor film with a low impurity concentration is formed.
Semiconductor Energy Laboratory Co., Ltd.
03/26/15
20150084044
new patent

Semiconductor device


Provided is a semiconductor device having a structure with which a decrease in electrical characteristics that becomes more significant with miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film, a gate electrode overlapping with the first oxide semiconductor film, a first gate insulating film between the first oxide semiconductor film and the gate electrode, and a second gate insulating film between the first gate insulating film and the gate electrode.
Semiconductor Energy Laboratory Co., Ltd.
03/26/15
20150084043
new patent

Semiconductor device


Defects in an oxide semiconductor film are reduced in a semiconductor device including the oxide semiconductor film. The electrical characteristics of a semiconductor device including an oxide semiconductor film are improved.
Semiconductor Energy Laboratory Co., Ltd.
03/26/15
20150084041
new patent

Semiconductor devices and methods of fabricating the same


A gate-all-around (gaa) semiconductor device can include a fin structure that includes alternatingly layered first and second semiconductor patterns. A source region can extend into the alternatingly layered first and second semiconductor patterns and a drain region can extend into the alternatingly layered first and second semiconductor patterns.
Samsung Electronics Co., Ltd.
03/26/15
20150084040
new patent

Semiconductor device and imaging device


According to one embodiment, a semiconductor device includes a semiconductor layer including a first semiconductor portion and a second semiconductor portion being continuous with the first semiconductor portion, a first gate electrode, a second gate electrode, an insulating film. The first semiconductor portion includes a first portion, a second portion and a third portion provided between the first portion and the second portion.
Kabushiki Kaisha Toshiba
03/26/15
20150084039
new patent

Semiconductor device and manufacture thereof


This semiconductor device (100a) includes: an oxide layer (15) which includes a semiconductor region (5) and a conductor region (7) that contacts with the semiconductor region; a source electrode (6s) and a drain electrode (6d) which are electrically connected to the semiconductor region; an insulating layer (11) formed on the source and drain electrodes; a transparent electrode (9) arranged to overlap at least partially with the conductor region with the insulating layer interposed between them; a source line (6a) formed out of the same conductive film as the source electrode; and a gate extended line (3a) formed out of the same conductive film as a gate electrode (3). The source line is electrically connected to the gate extended line via a transparent connecting layer (9a) which is formed out of the same conductive film as the transparent electrode..
Sharp Kabushiki Kaisha
03/26/15
20150084013
new patent

Organic semiconductor element and cmis semiconductor device including the same


There is provided with an organic semiconductor element. The organic semiconductor element has a source electrode portion, a drain electrode portion, an active layer region of an organic semiconductor, a gate insulating film, and a gate electrode portion.
Tohoku University
03/26/15
20150084001
new patent

Gate-all-around nanowire mosfet and formation


A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.. .
International Business Machines Corporation


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