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Semiconductor Device patents

      

This page is updated frequently with new Semiconductor Device-related patent applications.




 Semiconductor device and driving system patent thumbnailSemiconductor device and driving system
A semiconductor device includes a high side driver, in which the high side driver has an output transistor configured to supply a power voltage to an output terminal based on a driving voltage applied to a gate electrode of the output transistor; a short circuit transistor configured to couple the gate electrode of the output transistor with the output terminal; and a switch transistor connected in series between the gate electrode of the output transistor and a drain electrode of the short circuit transistor. The switch transistor is controlled by a back gate of the switch transistor..
Renesas Electronics Corporation


 Semiconductor device and  manufacturing semiconductor device patent thumbnailSemiconductor device and manufacturing semiconductor device
A semiconductor device includes a plurality of semiconductor switching elements disposed on a single semiconductor substrate comprising a semiconductor having a bandgap that is wider than that of silicon; and a plurality of electrode pads that are disposed in a predetermined planar layout on a front surface of the semiconductor substrate, the plurality of electrode pads each being electrically connected to the plurality of semiconductor switching elements. A plurality of terminal pins to externally carry out voltage of the electrode pads is bonded through a plated film to all of the plurality of electrode pads by solder..
Fuji Electric Co., Ltd.


 Semiconductor device and manufacturing method thereof patent thumbnailSemiconductor device and manufacturing method thereof
As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film..
Semiconductor Energy Laboratory Co., Ltd.


 Film and organic semiconductor device containing the film patent thumbnailFilm and organic semiconductor device containing the film
A film comprising a polymer compound and a low molecular weight compound having carrier transportability, wherein the content of the low molecular weight compound is 5 to 40 parts by mass with respect to 100 parts by mass of the sum of the polymer compound and the low molecular weight compound, the diffraction intensity a specified by the following measuring method a is 3 to 50, and the intensity ratio (a/b) of the diffraction intensity a specified by the following measuring method a to the diffraction intensity b specified by the following measuring method b is 30 or less: (measuring method a) the diffraction intensity a is the maximum diffraction intensity in a range of scattering vector of 1 nm−1 to 5 nm−1 in a profile obtained by an out-of plane measuring method using a film x-ray diffraction method; (measuring method b) the diffraction intensity b is the maximum diffraction intensity in a range of scattering vector of 10 nm−1 to 21 nm−1 in a profile obtained by an in-plane measuring method using a film x-ray diffraction method.. .
Sumitomo Chemical Company, Limited


 Semiconductor device, semiconductor device package, and lightning apparatus patent thumbnailSemiconductor device, semiconductor device package, and lightning apparatus
A semiconductor device includes a light emitting structure, and an interconnection bump including an under bump metallurgy (ubm) layer disposed on an electrode of at least one of the first and second conductivity-type semiconductor layers, and having a first surface disposed opposite to a surface of the electrode and a second surface extending from an edge of the first surface to be connected to the electrode, an intermetallic compound (imc) disposed. On the first surface of the ubm layer, a solder bump bonded to the ubm layer with the imc therebetween, and a barrier layer disposed on the second surface of the ubm layer and substantially preventing the solder bump from being diffused into the second surface of the ubm layer..
Samsung Electronics Co., Ltd.


 Semiconductor device and  forming semiconductor die with active region responsive to external stimulus patent thumbnailSemiconductor device and forming semiconductor die with active region responsive to external stimulus
A semiconductor device has a first semiconductor die including an active region formed on a surface of the first semiconductor die. The active region of the first semiconductor die can include a sensor.
Stats Chippac Pte. Ltd.


 Semiconductor device and zener diode having branch impurity regions patent thumbnailSemiconductor device and zener diode having branch impurity regions
A semiconductor device includes a substrate, a well region of a first-conductivity type disposed in the substrate, a first impurity region of a second-conductivity type and having a plurality of branches disposed in the well region, a second impurity region of the first-conductivity type and having a plurality of branches, and a third impurity region of the first-conductivity type disposed in the well region. The second-conductivity type is opposite to the first-conductivity type.
Macronix International Co., Ltd.


 Semiconductor device patent thumbnailSemiconductor device
Provided is a device with improved reverse-recovery immunity of a diode element. The device includes: a first conductivity-type drift layer; a second conductivity-type anode region provided in an upper portion of the drift layer; a second conductivity-type extraction region in contact with and surrounding the anode region; and a second conductivity-type field limiting ring region surrounding and separated from the extraction region at the upper portion of the drift layer, wherein the extraction region has a greater depth than the anode region and the field limiting ring region..
Fuji Electric Co., Ltd.


 Semiconductor device and  manufacturing the same patent thumbnailSemiconductor device and manufacturing the same
An object is to provide a structure of a transistor which has a channel formation region formed using an oxide semiconductor and a positive threshold voltage value, which enables a so-called normally-on switching element. The transistor includes an oxide semiconductor stack in which at least a first oxide semiconductor layer and a second oxide semiconductor layer with different energy gaps are stacked and a region containing oxygen in excess of its stoichiometric composition ratio is provided..
Semiconductor Energy Laboratory Co., Ltd.


 Semiconductor device and  manufacturing the same patent thumbnailSemiconductor device and manufacturing the same
A semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, and an oxide insulating film covering the transistor. The multilayer film includes an oxide semiconductor film and an oxide film containing in or ga, the oxide insulating film contains more oxygen than that in the stoichiometric composition, and in the transistor, by a bias-temperature stress test, threshold voltage does not change or the amount of the change in a positive direction or a negative direction is less than or equal to 1.0 v, preferably less than or equal to 0.5 v..
Semiconductor Energy Laboratory Co., Ltd.


Semiconductor device and manufacturing the same

An oxide semiconductor layer is formed, a gate insulating layer is formed over the oxide semiconductor layer, a gate electrode layer is formed to overlap with the oxide semiconductor layer with the gate insulating layer interposed therebetween, a first insulating layer is formed to cover the gate insulating layer and the gate electrode layer, an impurity element is introduced through the insulating layer to form a pair of impurity regions in the oxide semiconductor layer, a second insulating layer is formed over the first insulating layer, the first insulating layer and the second insulating layer are anisotropically etched to form a sidewall insulating layer in contact with a side surface of the gate electrode layer, and a source electrode layer and a drain electrode layer in contact with the pair of impurity regions are formed.. .
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device

A semiconductor device or the like capable of preventing malfunction of a driver circuit is provided. In a driver circuit for driving a power device used for current supply, a transistor including an oxide semiconductor is used as a transistor in a circuit (specifically, for example, a level shift circuit) requiring a high withstand voltage.
Semiconductor Energy Laboratory Co., Ltd.

High doped iii-v source/drain junctions for field effect transistors

A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a iii-v material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped iii-v material between doped iii-v materials, the doped iii-v materials including a dopant in an amount in a range from about le18 to about le20 atoms/cm3 and contacting the epitaxial contacts.. .
Stmicroelectronics, Inc.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, an insulating structure, and a gate stack. The substrate has at least one semiconductor fin.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor devices including a stressor in a recess and methods of forming the same

Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region.
Samsung Electronics Co., Ltd.

Interlayer dielectric film in semiconductor devices

A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (ht) doping process on the flowable dielectric layer.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device and fabricating the same

A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium..
Samsung Electronics Co., Ltd.

Semiconductor device with control structure including buried portions and manufacturing

A semiconductor device includes transistor cells and control structures. The transistor cells include source zones of a first conductivity type and body zones of a second conductivity type.
Lnfineon Technologies Ag

Method of manufacturing a semiconductor device with trench gate by using a screen oxide layer

A screen oxide layer is formed on a main surface of a semiconductor layer and a passivation layer is formed on the screen oxide layer. A gate trench is formed in a portion of the semiconductor layer exposed by a mask opening in a trench mask that comprises the passivation layer.
Infineon Technologies Austria Ag

Semiconductor devices, power semiconductor devices, and methods for forming a semiconductor device

A semiconductor device includes a drift region of a device structure arranged in a semiconductor layer. The drift region includes at least one first drift region portion and at least one second drift region portion.
Infineon Technologies Ag

Semiconductor device and manufacturing semiconductor device

In a front surface of a semiconductor base body, a gate trench is disposed penetrating an n+-type source region and a p-type base region to a second n-type drift region. In the second n-type drift region, a p-type semiconductor region is selectively disposed.
National Institute Of Advanced Industrial Science And Technology

Semiconductor devices and methods of manufacturing the same

A semiconductor device includes a gate structure on a substrate, a source/drain layer on a portion of the substrate adjacent the gate structure, a first contact plug contacting an upper surface of the source/drain layer, and a second contact plug contacting upper surfaces of the gate structure and the first contact plug. A bottom surface of the second contact plug has a first portion not contacting the upper surface of the first contact plug, and the first portion is higher than the upper surface of the gate structure..
Samsung Electronics Co., Ltd.

Semiconductor device

A semiconductor device includes: a substrate; a semiconductor stack including a first nitride semiconductor layer and a second nitride semiconductor layer formed above the substrate; a source electrode and a drain electrode formed above a lower surface of the semiconductor stack; a gate electrode; in plan view, a current-drift area; a non-current-drift area; and a collapse reducing electrode formed on the non-current-drift area in the second nitride semiconductor layer, the collapse reducing electrode being formed to have a substantially same potential as the gate electrode. In the semiconductor device, the collapse reducing electrode and the second nitride semiconductor layer have a junction surface functioning as an energy barrier having a rectifying effect in a forward direction from the collapse reducing electrode to the second nitride semiconductor layer..
Panasonic Intellectual Property Management Co., Ltd.

Semiconductor device including two-dimensional material

A semiconductor device includes a substrate, a two-dimensional (2d) material layer formed on the substrate and having a first region and a second region adjacent to the first region, and a source electrode and a drain electrode provided to be respectively in contact with the first region and the second region of the 2d material layer, the second region of the 2d material layer including an oxygen adsorption material layer in which oxygen is adsorbed on a surface of the second region.. .
Research & Business Foundation Sungkyunkwan University

Trench-type insulated gate semiconductor device including an emitter trench and an overlapped floating region

A semiconductor device of the present invention includes a semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode filled via a gate insulating film in the plurality of gate trenches, an n+-type emitter region, a p-type base region, and an n−-type drift region disposed, lateral to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, a p+-type collector region disposed on a back surface side of the semiconductor layer with respect to the n−-type drift region, a plurality of emitter trenches formed between the plurality of gate trenches adjacent to each other, a buried electrode filled via an insulating film in the plurality of emitter trenches, and electrically connected with the n+-type emitter region, and a p-type floating region formed between the plurality of emitter trenches, and the p-type floating region is formed deeper than the p-type base region, and includes an overlap portion that goes around to a lower side of an emitter trench closest to the gate trench out of the plurality of emitter trenches and has an end portion positioned on a side closer to the gate trench with respect to a center in a width direction of the emitter trench.. .
Rohm Co., Ltd.

Semiconductor device

A planar mosfet is provided on the upper surface of the n−-type semiconductor substrate in a mesa portion between the trenches. A p+-type emitter layer is provided between the trench and the planar mosfet in the mesa portion.
Mitsubishi Electric Corporation

Multiple zone power semiconductor device

A power semiconductor device is comprised of a plurality of zones having similar structure. Each of the zones may be characterized by a switching loss during transitions to a non-conducting state.
Ford Global Technologies, Llc

Semiconductor device

To provide a semiconductor device in which an edge termination structure can be made smaller easily. A semiconductor device is provided, the semiconductor device including an active region and an edge termination structure formed on a front surface side of a semiconductor substrate, wherein an edge termination structure has a guard ring provided surrounding an active region on a front surface side of a semiconductor substrate, a first field plate provided on a front surface side of a guard ring, an electrode unit provided on a front surface side of a first field plate, a second field plate provided between a first field plate and a electrode unit, and a conductive connecting unit which mutually electrically connects a first field plate, an electrode unit, a second field plate, and a guard ring..
Fuji Electric Co., Ltd.

Source/drain structure of semiconductor device

An exemplary method for forming a semiconductor device includes etching a top portion etching a top portion of a first semiconductor fin to produce a recessed top portion of the fin. A dielectric layer is deposited over the first semiconductor fin and an adjacent isolation structure.
Taiwan Semiconductor Manufacturing Company, Ltd.

Method for fabricating finfet isolation structure

A method for forming a semiconductor device. In this method, a semiconductor fin is formed on a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device and manufacturing the same

A method of manufacturing a semiconductor device that includes a junction field effect transistor, the junction field effect transistor including a semiconductor substrate of a first conductivity type, an epitaxial layer of the first conductivity type formed on the semiconductor substrate, a source region of the first conductivity type formed on a surface of the epitaxial layer, a channel region of the first conductivity type formed in a lower layer of the source region, a pair of trenches formed in the epitaxial layer so as to sandwich the source region therebetween, and a pair of gate regions of a second conductivity type, opposite to the first conductivity type, formed below a bottom of the pair of trenches.. .
Renesas Electronics Corporation

Method and device for metal gate stacks

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, a high-k dielectric layer on the substrate, a capping layer on the high-k dielectric layer, forming a first n-type work function metal layer on the capping layer, forming a second n-type work function metal layer on the first n-type work function metal layer, and forming a metal electrode layer on the second n-type work function metal layer. The second n-type work function metal layer has a ti/al atomic ratio greater than the ti/al atomic ratio of the first n-type work function metal layer.
Semiconductor Manufacturing International (shanghai) Corporation

Gate structure, semiconductor device and the forming semiconductor device

A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device with a gate contact positioned above the active region

One illustrative device disclosed herein includes a stepped conductive source/drain structure with a cavity defined therein, the cavity being located vertically above an active region, a non-conductive structure positioned in the cavity, a layer of insulating material positioned above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, a gate contact opening defined in the layer of insulating material and a conductive gate contact positioned in the gate contact opening that is conductively coupled to the gate structure, wherein at least a portion of the conductive gate contact is positioned vertically above the non-conductive structure.. .
Globalfoundries Inc.

Nitride semiconductor device using insulating films having different bandgaps to enhance performance

The semiconductor device includes: a channel layer, a barrier layer, a first insulating film, and a second insulating film, each of which is formed above a substrate; a trench that penetrates the second insulating film, the first insulating film, and the barrier layer to reach the middle of the channel layer; and a gate electrode arranged in the trench and over the second insulating film via a gate insulating film. The bandgap of the second insulating film is smaller than that of the first insulating film, and the bandgap of the second insulating film is smaller than that of the gate insulating film gi.
Renesas Electronics Corporation

Semiconductor devices and fabricating methods thereof

Provided are semiconductor devices and fabricating methods thereof. The semiconductor device includes a field insulating layer formed in a substrate, an interlayer dielectric layer formed on the field insulating layer and including a trench exposing at least a portion of the field insulating layer, a deposition insulating layer formed in the trench to be disposed on the field insulating layer, a gate insulating layer formed the trench to be disposed on the deposition insulating layer, and a metal gate formed the trench on the gate insulating layer..
Samsung Electronics Co., Ltd.

Reduction of defect induced leakage in iii-v semiconductor devices

A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 10 cm−2. An n-type layer is formed on or in the p-doped layer.
International Business Machines Corporation

Semiconductor device

According to the present invention, a semiconductor device includes a first conductivity type sic layer, an electrode that is selectively formed upon the sic layer, and an insulator that is formed upon the sic layer and that extends to a timing region that is set at an end part of the sic layer. The insulator includes an electrode lower insulating film that is arranged below the electrode, and an organic insulating layer that is arranged so as to cover the electrode lower insulating film.
Rohm Co., Ltd.

Semiconductor device and manufacturing semiconductor device

A semiconductor device includes a wide-bandgap semiconductor substrate of a first conductivity type, a wide-bandgap semiconductor deposition layer of the first conductivity type, semiconductor regions of a second conductivity type, a wide-bandgap semiconductor layer of the second conductivity type, first regions of the first conductivity type, and second regions of the first conductivity type. The width w of a plating film formed on a source electrode of the semiconductor device is greater than or equal to 10 μm.
Fuji Electric Co., Ltd.

Three-dimensional semiconductor devices

A three-dimensional (3d) semiconductor device includes a plurality of gate electrodes stacked on a substrate in a direction normal to a top surface of the substrate, a channel structure passing through the gate electrodes and connected to the substrate, and a void disposed in the substrate and positioned below the channel structure.. .

Semiconductor device having multi-channel and forming the same

A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.. .

Deep trench isolation structures and systems and methods including the same

Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device.
Nxp Usa, Inc.

Silicon carbide semiconductor device, and manufacturing same

The silicon carbide substrate includes a first impurity region, a second impurity region, and a third impurity region. The first impurity region includes: a first region in contact with the second impurity region; a second region that is in contact with the first region, that is located opposite to the second impurity region when viewed from the first region, and that has an impurity concentration higher than an impurity concentration of the first region; and a third region that is in contact with the second region, that is located opposite to the first region when viewed from the second region, and that has an impurity concentration lower than the impurity concentration of the second region.
Sumitomo Electric Industries, Ltd.

Method of producing a semiconductor device

A semiconductor device includes four or more first memory cells arranged on a row, the first memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film formed around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film, and a first magnetic tunnel junction storage element formed on the first pillar-shaped semiconductor layer. The semiconductor device further includes a first source line that connects lower portions of the first pillar-shaped semiconductor layers to each other, a first bit line that extends in a direction perpendicular to a direction in which the first gate line extends and that is connected to an upper portion of the first magnetic tunnel junction storage element, and a second source line that extends in a direction perpendicular to a direction in which the first source line extends..
Unisantis Electronics Singapore Pte. Ltd.

Semiconductor device and forming the same

A semiconductor device includes an active region defining an isolation region. First and second cell interconnection structures are on the active region and the isolation region, and have line shapes that are parallel to each other.

Semiconductor device

A plurality of pixel regions are aligned in a matrix in a semiconductor substrate, and each of the plurality of pixel regions includes an active region, two photoelectric conversion elements, two floating capacitance regions, and a first transistor. Each of the plurality of pixel regions includes two transfer transistors each having each of the two photoelectric conversion elements and each of the two floating capacitance regions.
Renesas Electronics Corporation

Semiconductor device and forming the same

A semiconductor device includes a semiconductor substrate, a radiation-sensing region, at least one isolation structure, and a doped passivation layer. The radiation-sensing region is present in the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method of tuning source/drain proximity for input/output device reliability enhancement

A semiconductor device includes a first finfet device and a second finfet device. The first finfet device includes a first gate, a first source, and a first drain.
Taiwan Semiconductor Manufacturing Company, Ltd.

Three-dimensional semiconductor devices

A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.. .

Semiconductor device and manufacturing the same

A semiconductor device includes a first stack including a plurality of alternating layers of first interlayer insulating layers and first conductive patterns; a second stack including a plurality of alternating layers of second conductive patterns and second interlayer insulating layers, the second stack being positioned above the first stack; a plurality of pillar-structures each pillar structure passing through the first and second stacks; and a ring pattern layer disposed between the first and second stacks, the ring pattern layer comprising a plurality of ring patterns, each ring pattern surrounding each pillar-structure.. .
Sk Hynix Inc.

Semiconductor device

According to one embodiment, a semiconductor device includes a stacked body; a columnar portion; a plate portion; and a blocking insulating film. The stacked body includes a plurality of electrode layers.
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing same

According to one embodiment, the stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body extends in a stacking direction through the stacked body.
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing the same

The semiconductor device may include a first sub-pipe gate having a pipe hole formed therein; a second sub-pipe gate disposed on the first sub-pipe gate and passed-through by vertical holes being coupled to the pipe hole, wherein a material of the second sub-pipe gate has a lower oxidation rate than that of a material of the first sub-pipe gate; a first oxidized layer formed within a portion of the first sub-pipe gate to conform to a contour of the pipe hole; and a second oxidized layer formed within a portion of the second sub-pipe gate to conform to a contour of the vertical holes and the contour of the pipe hole.. .
Sk Hynix Inc.

Semiconductor device

At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device, electronic component, and electronic device

A semiconductor device excellent in writing operation is provided. In a structure where a data voltage supplied to a source line is supplied to a node of a memory cell via a bit line, a switch is provided between memory cells connected to the bit line.
Semiconductor Energy Laboratory Co., Ltd.

Transistor, fabricating the same, and electronic device including the same

A semiconductor device includes a stressed substrate stressed by a first stress, a first stressed channel formed in the substrate and having the first stress, and a first strained gate electrode strained by a first strain generating element. A first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel..
Sk Hynix Inc.

Semiconductor devices including insulating materials in fins

Semiconductor devices are provided. A semiconductor device includes a first insulating material in a first fin.
Samsung Electronics Co., Ltd.

Semiconductor device and semiconductor integrated circuit using the same

A semiconductor device includes a channel region of a first conductivity type, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film, a first region of a second conductivity type and a second region of the second conductivity type, which are formed along the gate electrode while facing each other with the gate electrode interposed between the first region and the second region, a semiconductor region of the second conductivity type on which the first region, the second region and the channel region are formed, and an element isolation region which surrounds the semiconductor region. The gate electrode extends beyond a boundary portion between the channel region and the element isolation region.
Rohm Co., Ltd.

Semiconductor device and manufacturing method thereof

A semiconductor device includes first and second fin fet and a separation plug made of an insulating material and disposed between the first and second fin fets. The first fin fet includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending a second direction perpendicular to the first direction.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

A semiconductor device with a small number of transistors is provided. The semiconductor device includes a first transistor, a second transistor, a third transistor, a first wiring, and a second wiring.
Semiconductor Energy Laboratory Co., Ltd.

Method of manufacturing a semiconductor device having reduced on-state resistance and structure

A semiconductor device includes a singulated region of semiconductor material having a first major surface and a second major surface opposite to the first major surface. In one embodiment, the second major surface includes a recessed surface portion bounded by opposing sidewall portions extending outward from the region of semiconductor material in cross-sectional view.
Semiconductor Components Industries, Llc

Semiconductor device and manufacturing semiconductor device

A second electrode provided on the fifth semiconductor region and the seventh semiconductor region.. .

Electrostatic discharge protection semiconductor device

An esd protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a first doped region formed in the drain region. The source region and the drain region include a first conductivity type, and the first doped region includes a second conductivity type.
United Microelectronics Corp.

Semiconductor devices having hybrid stacking structures and methods of fabricating the same

A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other.

Semiconductor device

A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion..
Renesas Electronics Corporation

Semiconductor device and manufacturing method thereof

A semiconductor device includes a plurality of semiconductor dies stacked vertically to have a vertical height and a dielectric surrounding the stacked semiconductor dies. The semiconductor device further has a conductive post external to the stacked semiconductor dies and extending through the dielectric.
Taiwan Semiconductor Manufacturing Company Ltd.

Wire bond cleaning method and wire bonding recovery process

Methods, systems and devices are disclosed for performing a semiconductor processing operation. In some embodiments this includes configuring a wire bonding machine to perform customized movements with a capillary tool of the wire bonding machine, etching bulk contaminants over one or more locations of a semiconductor device with the capillary tool, and applying plasma to the semiconductor device to remove residual contaminants..
Skyworks Solutions, Inc.

Press fitting head and semiconductor manufacturing apparatus using the same

A press fitting head comprising an elastic member in a part where the press fitting head contacts a semiconductor device, and an alignment mark recognition area capable of detecting an optically readable marker provided on a surface to be contacted to the semiconductor device is provided. Additionally, a semiconductor manufacturing apparatus in which the press fitting head is applied is provided..
J-devices Corporation

Bonding wire for semiconductor device

The present invention provides a bonding wire which can satisfy bonding reliability, spring performance, and chip damage performance required in high-density packaging. A bonding wire contains one or more of in, ga, and cd for a total of 0.05 to 5 at %, and a balance being made up of ag and incidental impurities..
Nippon Micrometal Corporation

Semiconductor device with an anti-pad peeling structure and associated method

A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a through substrate via (tsv); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the tsv when being seen from a top-down perspective..
Taiwan Semiconductor Manufacturing Company Ltd.

Lid structure and semiconductor device package including the same

The present disclosure relates to a semiconductor device package, which includes a carrier, a lid, a first adhesive layer and a constraint structure. The carrier includes a surface and a first conductive pad on the surface of the carrier.
Advanced Semiconductor Engineering, Inc.

Semiconductor device and method

A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material..
Taiwan Semiconductor Manufacturing Company, Ltd.

Wafer level package with tsv-less interposer

A semiconductor device includes an interposer having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side within a first chip mounting area through a plurality of first bumps; a second semiconductor die mounted on the first side within a second chip mounting area being adjacent to the first chip mounting area; a ring-shaped supporting feature disposed on the first side and encompassing the first chip mounting area and the second chip mounting area; and a plurality of solder bumps mounted on the second side.. .
Inotera Memories, Inc.

Method for manufacturing semiconductor apparatus and semiconductor apparatus

A method for manufacturing a semiconductor apparatus, including an encapsulating step of collectively encapsulating a device mounting surface of a substrate having semiconductor devices mounted thereon with a base-attached encapsulant having a base and a thermosetting resin layer formed on one surface of the base, the semiconductor devices being mounted by flip chip bonding, the encapsulating step including a unifying stage of unifying the substrate having the semiconductor devices mounted thereon and the base-attached encapsulant under a reduced pressure condition with a vacuum of 10 kpa or less, and a pressing stage of pressing the unified substrate with a pressure of 0.2 mpa or more.. .
Shin-etsu Chemical Co., Ltd.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package.
Taiwan Semiconductor Manufacturing Company Ltd.

Trench mosfet with self-aligned body contact with spacer

Trench mosfet with self-aligned body contact with spacer. In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor substrate, and at least two gate trenches formed in the semiconductor substrate.
Vishay-siliconix

Conductive structures, systems and devices including conductive structures and related methods

Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures.
Micron Technology, Inc.

Semiconductor device and manufacturing the same

A semiconductor device includes an interlayer insulating film ins2, adjacent cu wirings m1w formed in the interlayer insulating film ins2, and an insulating barrier film br1 which is in contact with a surface of the interlayer insulating film ins2 and surfaces of the cu wirings m1w and covers the interlayer insulating film ins2 and the cu wirings m1w. Between the adjacent cu wirings m1w, the interlayer insulating film ins2 has a damage layer dm1 on its surface, and has an electric field relaxation layer er1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer dm1 at a position deeper than the damage layer dm1..
Renesas Electronics Corporation

Semiconductor device

A semiconductor device, in which a plurality of control terminals that correspond to a main terminal and the same semiconductor chip protrude from a surface of an encapsulating part, and a plurality of signal paths that include the plurality of control terminals are positioned so as to be aligned with the main terminal in a first direction. Provided in each of the plurality of signal paths are pairs of relay members having identical functions, and a first relay grouping that includes one relay member of the pair of relay and a second relay grouping that includes the other relay member of the pair are positioned neighboring each other aligned in the first direction, with the ordering of the first relay grouping being mirror-inverted relative to the second relay grouping..
Denso Corporation

Single or multi chip module package and related methods

Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die.
Semiconductor Components Industries, Llc

Lead frame and semiconductor device

A semiconductor device includes a lead frame; a semiconductor chip mounted on the lead frame; and an encapsulation resin, wherein a convexo-concave portion including a plurality of concave portions is provided at a covered portion of the lead frame that is covered by the encapsulation resin, wherein the planer shape of each of the concave portions is a circle, the diameter of which is greater than or equal to 0.020 mm and less than or equal to 0.060 mm, or a polygon, the diameter of whose circumcircle is greater than or equal to 0.020 mm and less than or equal to 0.060 mm, and wherein a ratio s/s0 is greater than or equal to 1.7 where “s” is a surface area of the convexo-concave portion that is formed at a flat surface whose surface area is “s0”.. .
Shinko Electric Industries Co., Ltd.

Semiconductor device

A semiconductor device includes a semiconductor chip having an active surface and a non-active surface opposite to the active surface, an upper insulating layer provided on the non-active surface of semiconductor chip, and a via and a connection pad penetrating the semiconductor chip and the upper insulating layer, respectively. The connection pad has a first surface exposed outside the upper insulating layer and a second surface opposite to the first surface and facing the semiconductor chip.
Samsung Electronics Co., Ltd.

Semiconductor device with heat information mark

A semiconductor device includes a semiconductor package and a mark. The semiconductor package includes a semiconductor chip including a hot spot from which heat is generated, and a mold layer encapsulating the semiconductor chip.
Samsung Electronics Co., Ltd.

Semiconductor device including electromagnetic absorption and shielding

A semiconductor device is disclosed including material for absorbing emi and/or rfi. The device includes a substrate, one or more semiconductor die, and molding compound around the one or more semiconductor die.
Sandisk Information Technology (shanghai) Co. Ltd.

Monitoring method and manufacturing semiconductor device

A monitoring method that can detect a sign of disconnection of a heat generation source is provided. Further, a highly reliable semiconductor device is provided.
Renesas Electronics Corporation

Semiconductor device and fabricating the same

A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.. .
Samsung Electronics Co., Ltd.

Selective bottom-up metal feature filling for interconnects

A method for selective bottom-up filling of recessed features with a low resistivity metal for semiconductor devices is described in several embodiments. The method includes providing a substrate containing a patterned dielectric layer having a recessed feature with dielectric layer surfaces and a metal-containing surface on a bottom of the recessed feature, reacting the dielectric layer surfaces with a reactant gas containing a hydrophobic functional group to form hydrophobic dielectric layer surfaces, and at least substantially filling the recessed feature with a metal in a bottom-up gas phase deposition process that hinders deposition of the metal on the hydrophobic dielectric layer surfaces.
Tokyo Electron Limited

Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device

In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer.
Qualcomm Incorporated

Liquid composition for cleaning semiconductor device, cleaning semiconductor device, and fabricating semiconductor device

[solution] a liquid cleaning composition of the present invention used for fabricating a semiconductor device comprises hydrogen peroxide at 1-30% by mass, potassium hydroxide at 0.01-1% by mass, aminopolymethylene phosphoric acid at 0.0001-0.01% by mass, a zinc salt at 0.0001-0.1% by mass and water.. .

Dielectric with air gaps for use in semiconductor devices

Aspects of the invention are directed to a method for forming a semiconductor device. A dielectric layer is formed on a semiconductor substrate.
International Business Machines Corporation

Semiconductor device leadframe

For so called film assisted moulding (fam) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion..
Ampleon Netherlands B.v.

Semiconductor device manufacturing method

A pressing unit including a pressing pin is attached to a mold, a semiconductor chip, first and second heat sinks, and solders are disposed in a cavity of the mold, a mold closing state is made, and a reflow is carried out in a state where the first and second heat sinks are pressed against first and second wall surfaces by the pressing pin to form a laminated body. After the laminated body is formed, the pressing pin is pulled out from the cavity, and a resin molded body is formed by injecting a resin..
Denso Corporation

Manufacturing semiconductor device

A semiconductor device including an oxide conductor with high conductivity and high transmittance is provided. A manufacturing method for a semiconductor device includes the steps of: forming an oxide semiconductor over a first insulator; forming a second insulator over the first insulator and the oxide semiconductor; forming a first conductor over the second insulator; forming an etching mask over the first conductor; forming a second conductor including a region overlapping with the oxide semiconductor by etching the first conductor with use of the etching mask as a mask; removing the etching mask; and performing heat treatment after forming a hydrogen-containing layer over the second insulator and the second conductor..
Semiconductor Energy Laboratory Co., Ltd.

Methods for forming semiconductor devices

A method for forming a semiconductor device includes etching, in a masked etching process, through a layer stack located on a surface of a semiconductor substrate to expose the semiconductor substrate at unmasked regions of the layer stack. The method further includes etching, in a selective etching process, at least a first layer of the layer stack located adjacently to the semiconductor substrate.
Infineon Technologies Austria Ag

Method of fabricating semiconductor device

Methods for fabricating semiconductor devices include forming a fin-type pattern protruding on a substrate, forming a gate electrode intersecting the fin-type pattern, forming a first recess adjacent to the gate electrode and within the fin-type pattern by using dry etching, forming a second recess by treating a surface of the first recess with a surface treatment process including a deposit process and an etch process, and forming an epitaxial pattern in the second recess.. .
Samsung Electronics Co., Ltd.

Semiconductor manufacturing apparatus and manufacturing semiconductor device

According to one embodiment, a semiconductor manufacturing apparatus includes a chamber, a stage, and first gas injector. The chamber is configured to contain a wafer.
Kabushiki Kaisha Toshiba

Method of fabricating semiconductor device

Provided is a method of fabricating a semiconductor device. In the method, a double patterning technology is used to form various patterns with different widths..
Samsung Electronics Co., Ltd.

Semiconductor forming a semiconductor device

A method for forming a semiconductor device includes implanting doping ions into a semiconductor substrate. A deviation between a main direction of a doping ion beam implanting the doping ions and a main crystal direction of the semiconductor substrate is less than ±0.5° during the implanting of the doping ions into the semiconductor substrate.
Infineon Technologies Ag

Orientation layer for directed self-assembly patterning process

Disclosed is a method of forming a semiconductor device using a self-assembly (dsa) patterning process. The method includes forming a patterned feature over a substrate; applying an orientation material that includes a first polymer and a second polymer over the substrate, wherein the first polymer has a first activation energy and the second polymer has a second activation energy; baking the substrate at first temperature thereby forming a first orientation layer that includes the first polymer; baking the substrate at second temperature thereby forming a second orientation layer that includes the second polymer; and performing a directed self-assembly (dsa) process over the first and the second orientation layers..
Taiwan Semiconductor Manufacturing Company, Ltd.

Chemical vapor deposition manufacturing semiconductor device using the same

A method for manufacturing a semiconductor device includes forming a transistor on a substrate. Precursor gases are provided from a showerhead of a chemical vapor deposition (cvd) apparatus to form a contact etch stop layer (cesl) to cover the transistor and the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method of cleaning substrate and fabricating semiconductor device using the same

A method of cleaning a substrate includes providing the substrate, the substrate including a metal material film, performing physical cleaning of the substrate, performing chemical cleaning of the substrate, and drying a surface of the substrate. Performing the chemical cleaning includes supplying a chemical cleaning solution including an anionic surfactant at a concentration that is equal to or greater than a critical micelle concentration (cmc) onto the surface of the substrate..
Samsung Electronics Co., Ltd.

Method and decoding commands

Method and apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles; validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle..
Micron Technology, Inc.

Semiconductor devices including reversible and one-time programmable magnetic tunnel junctions

A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (otp) resistance state..

Semiconductor device having redistribution lines

A semiconductor device includes, a semiconductor chip having a first surface over which bonding pads are positioned, a second surface which faces away from the first surface, and a plurality of signal lines formed over the first surface, extending in a first direction; a plurality of redistribution lines formed over the first surface, having one set of ends electrically coupled to the bonding pads of the semiconductor chip, and extending in a direction oblique to the first direction; and a plurality of redistribution pads disposed over the first surface, and electrically coupled with an other set of ends of the redistribution lines which face away from the one set of ends.. .
Sk Hynix Inc.

Semiconductor device and control the same

A semiconductor device includes semiconductor chips stacked each other. Each of the semiconductor chips converts second reception data received by second reception terminals arranged in point symmetry on the first face by a conversion method to convert first reception data received by first reception terminals arranged in point symmetry on the first face into a reference data; and generates an identification information of the each semiconductor chip based upon the converted second reception data; and outputs the bit sequence obtained by converting the generated identification information by means of the inverse conversion method of the conversion method..
Fujitsu Limited





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