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Semiconductor Device patents



      
           
This page is updated frequently with new Semiconductor Device-related patent applications. Subscribe to the Semiconductor Device RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Device RSS RSS


Power semiconductor device and fabrication method thereof

Anpec Electronics

Power semiconductor device and fabrication method thereof

Method of inspecting semiconductor device, method of fabricating semiconductor device, and inspection tool

Toshiba

Method of inspecting semiconductor device, method of fabricating semiconductor device, and inspection tool

Method of inspecting semiconductor device, method of fabricating semiconductor device, and inspection tool

Samsung Electro-mechanics

Semiconductor package, method of manufacturing semiconductor package and stack type semiconductor package

Date/App# patent app List of recent Semiconductor Device-related patents
02/26/15
20150058817
 Semiconductor overlay production system and method patent thumbnailnew patent Semiconductor overlay production system and method
Disclosed herein is a system and method for producing semiconductor devices using overlays, the method comprising associating one or more patterned overlays with respective ones of reserved regions in a layer template, receiving a layer design based on the layer template, identifying the reserved regions in the layer design, generating a production layer design based on the layer design, the production layer design describing at least one production overlay in one of the reserved regions, and fabricating one or more devices based on the production layer design.. .
Taiwan Semiconductor Manufacturing Company, Ltd.
02/26/15
20150058654
 Semiconductor device, battery pack and personal data assistant patent thumbnailnew patent Semiconductor device, battery pack and personal data assistant
A semiconductor device includes a voltage measurement unit that measures a voltage of a battery, a current measurement unit that measures charging and discharging currents of the battery, a data processing control unit, and a current detection unit. The voltage measurement unit and the current measurement unit are able to measure the voltage and the discharging current of the battery in case that the current detection unit detects that the discharging current exceeds a predetermined threshold.
Renesas Electronics Corporation
02/26/15
20150058588
 Semiconductor device and memory protection method patent thumbnailnew patent Semiconductor device and memory protection method
According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor.
Kabushiki Kaisha Toshiba
02/26/15
20150056817
 Semiconductor device manufacturing method patent thumbnailnew patent Semiconductor device manufacturing method
A direction change of space formed in an etching target layer can be suppressed while maintaining an etching selectivity for the etching target layer against a mask. A semiconductor device manufacturing method mt includes exciting a first gas by supplying the first gas containing a fluorocarbon gas, a fluorohydrocarbon gas and an oxygen gas into a processing chamber 12 (st2); and exciting a second gas by supplying the second gas containing an oxygen gas and a rare gas into the processing chamber (st3), and a cycle including the exciting of the first gas (st2) and the exciting of the second gas (st3) is repeated multiple times..
Tokyo Electron Limited
02/26/15
20150056816
 Semiconductor device manufacturing method and computer-readable storage medium patent thumbnailnew patent Semiconductor device manufacturing method and computer-readable storage medium
A semiconductor device manufacturing method for etching a substrate having a multilayer film formed by alternately stacking a first film and a second film, and a photoresist layer to form a step-shaped structure is provided. The step-shaped structure is formed by repeatedly performing a first step of plasma-etching the first film by using the photoresist layer as a mask, a second step of exposing the photoresist layer formed on the substrate to a plasma generated from a processing gas containing argon gas and hydrogen gas by applying a high frequency power to a lower electrode while applying a negative dc voltage to an upper electrode, a third step of trimming the photoresist layer, and a fourth step of plasma-etching the second film..
Tokyo Electron Limited
02/26/15
20150056807
 Semiconductor device and manufacturing method thereof patent thumbnailnew patent Semiconductor device and manufacturing method thereof
According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires.. .
Kabushiki Kaisha Toshiba
02/26/15
20150056805
 Methods of forming semiconductor device using bowing control layer patent thumbnailnew patent Methods of forming semiconductor device using bowing control layer
A bowing control pattern is formed on an intermediate layer. A hardmask pattern is formed on the bowing control layer.
02/26/15
20150056801
 Semiconductor device with air gap patent thumbnailnew patent Semiconductor device with air gap
A method of fabricating a semiconductor device may include forming isolation structures that include openings, over a substrate; forming sacrificial spacers on sidewalks of the openings; forming, on the sacrificial spacers, first conductive patterns that are recessed in the openings; removing the sacrificial spacers, and defining air gaps; forming a liner layer that caps the first conductive patterns and the air gaps; forming second conductive patterns through silicidation of the liner layer; and forming third conductive patterns over the second conductive patterns.. .
Sk Hynix Inc.
02/26/15
20150056797
 Semiconductor device and  manufacturing the same patent thumbnailnew patent Semiconductor device and manufacturing the same
A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer..
Samsung Electronics Co., Ltd.
02/26/15
20150056796
 Method for forming a semiconductor device having a metal gate recess patent thumbnailnew patent Method for forming a semiconductor device having a metal gate recess
Provided are approaches of forming a semiconductor device (e.g., transistor such as a finfet or planar device) having a gate metal recess. In one approach, a liner layer and a metal layer (e.g., w) are applied in a trench (e.g., via cvd and/or ald).
Globalfoundries Inc.
02/26/15
20150056795
new patent

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor devices includes providing a semiconductor substrate that includes a channel region. The method includes forming a gate electrode material film including a stepped portion on the channel region.
Samsung Electronics Co., Ltd
02/26/15
20150056794
new patent

Method for forming a semiconductor device with an integrated poly-diode


A method for forming a field effect power semiconductor device includes providing a semiconductor body comprising a main horizontal surface and a conductive region arranged next to the main horizontal surface, forming an insulating layer on the main horizontal surface, and etching a narrow trench through the insulating layer so that a portion of the conductive region is exposed, the narrow trench comprising, in a given vertical cross-section, a maximum horizontal extension. The method further includes forming a vertical poly-diode structure comprising a horizontally extending pn-junction.
Infineon Technologies Austria Ag
02/26/15
20150056788
new patent

Semiconductor device with a passivation layer


A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer..
Infineon Technologies Ag
02/26/15
20150056784
new patent

Method for manufacturing a semiconductor device by thermal treatment with hydrogen


A semiconductor device is manufactured by forming semiconductor elements extending between a front surface and a rear side of a semiconductor layer. This includes forming a porous area at a surface of a semiconductor body that includes a porous structure in the porous area, forming the semiconductor layer on the porous area by epitaxial growth so as to have a thickness in a range of 5 μm to 200 μm, and forming semiconductor regions including source, drain, body, emitter, base and/or collector regions in a front surface of the semiconductor layer by ion implantation.
Infineon Technologies Austria Ag
02/26/15
20150056782
new patent

Method of manufacturing a super junction semiconductor device with overcompensation zones


According to an embodiment, a super junction semiconductor device may be manufactured by introducing impurities of a first impurity type into an exposed surface of a first semiconductor layer of the first impurity type, thus forming an implant layer. A second semiconductor layer of the first impurity type may be provided on the exposed surface and trenches may be etched through the second semiconductor layer into the first semiconductor layer.
Infineon Technologies Austria Ag
02/26/15
20150056779
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes a semiconductor substrate divided into a cell region and a peripheral circuit region defined in a first direction, wherein the peripheral circuit region is divided into a first region and a second region defined in a second direction substantially orthogonal to the first direction; gate lines formed over the semiconductor substrate in the cell region and arranged in the second direction; and a capacitor including lower electrodes over the semiconductor substrate, a dielectric layer and an upper electrode, wherein the lower electrodes in the first and second regions, separated from each other in the first direction and coupled to each other in the first region, the dielectric layer is formed along surfaces of the lower electrodes in the second region, and the upper electrode is formed over the dielectric layer.. .
Sk Hynix Inc.
02/26/15
20150056778
new patent

Semiconductor device and manufacturing method therefor


A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane..
Renesas Electronics Corporation
02/26/15
20150056776
new patent

Method of manufacturing mos-type semiconductor device


A method of manufacturing a mos-type semiconductor device capable of increasing the thickness of a gate oxide film and obtaining high gate withstanding power and reduced switching loss without increasing a gate threshold voltage vth is provided. A p-type well region is selectively formed on one principle surface of a semiconductor substrate having an n-type low impurity concentration layer by using an oxide film as a mask.
Fuji Electric Co., Ltd.
02/26/15
20150056773
new patent

Semiconductor device manufacturing method


A semiconductor device manufacturing method includes exciting a processing gas containing a hbr gas and a cl2 gas within a processing chamber that accommodates a target object including a substrate, regions made of silicon, which are protruded from the substrate and arranged to form a gap, a metal layer formed to cover the regions, a polycrystalline silicon layer formed on the metal layer, and an organic mask formed on the polycrystalline silicon layer. The cl2 gas is supplied at a flow rate of about 5% or more to about 10% or less with respect to a flow rate of the hbr gas in the processing gas..
Tokyo Electron Limited
02/26/15
20150056772
new patent

Semiconductor device comprising buried gate and fabricating the same


The present invention provides a semiconductor device including a buried gate and a method for fabricating the same, in which the width of a contact plug may not exceed a predetermined width. The method including forming a plurality of trenches over a substrate using the mask pattern, forming a gate insulating film in each of the plurality of trenches, forming a plurality of gate electrodes filling portions of the plurality of trenches, removing an exposed gate insulating film formed over each of the plurality of gate electrodes in each of the plurality of the trenches, forming a plurality of sealing films filling remaining portions of the plurality of trenches, and forming a plurality of contact plugs over the substrate between the trenches..
Sk Hynix Inc.
02/26/15
20150056771
new patent

Method for fabricating semiconductor device with super junction structure


A semiconductor device with a super-junction structure is provided, including: a semiconductor substrate having a first conductivity type; an epitaxial layer having the first conductivity type formed over the semiconductor substrate; a first doping region having the first conductive type formed in a portion of the epitaxial layer; a second doping region having a second conductivity type formed in a portion of the of the epitaxial layer; a third doping region having the second conductivity type formed in a portion of the of the epitaxial layer, wherein the doping region partially comprises doped polysilicon materials having the second conductivity type; a gate dielectric layer formed over the epitaxial layer, partially overlying the well region; and a gate electrode formed over a portion of the gate dielectric layer.. .
Vanguard International Semiconductor Corporation
02/26/15
20150056769
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line..
Sk Hynix Inc.
02/26/15
20150056768
new patent

Method for fabricating semiconductor device


A method of fabricating a semiconductor device is disclosed. The method includes the steps of: sequentially forming agate dielectric layer and a first gate layer on a semiconductor substrate, wherein the gate dielectric layer is between the first gate layer and the semiconductor substrate; forming at least an opening in the first gate layer; forming a first dielectric layer conformally on the semiconductor substrate wherein the first dielectric layer covers the first gate layer; and forming a second gate layer filling the opening and overlapping the first gate layer..
United Microelectronics Corp.
02/26/15
20150056765
new patent

Semiconductor device and manufacturing the same


A semiconductor device which provides compactness and enhanced drain withstand voltage. The semiconductor device includes: a gate electrode; a source electrode spaced from the gate electrode; a drain electrode located opposite to the source electrode with respect to the gate electrode in a plan view and spaced from the gate electrode; at least one field plate electrode located between the gate and drain electrodes in a plan view, provided over the semiconductor substrate through an insulating film and spaced from the gate electrode, source electrode and drain electrode; and at least one field plate contact provided in the insulating film, coupling the field plate electrode to the semiconductor substrate.
Renesas Electronics Corporation
02/26/15
20150056763
new patent

Selective deposition of diamond in thermal vias


A method for fabricating a semiconductor device, such as a gan high electron mobility transistor (hemt) device, including etching a thermal via into a back-side of a semiconductor substrate and depositing a diamond nucleation seed layer across the back-side of the substrate. The method further includes coating the diamond nucleation with a mask layer and removing mask material outside of the thermal via on the planar portions of the back-side of the substrate.
02/26/15
20150056762
new patent

Semiconductor device manufacturing method


The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer.
Renesas Electronics Corporation
02/26/15
20150056760
new patent

Semiconductor device having diffusion barrier to reduce back channel leakage


A semiconductor-on-insulator (soi) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer.
International Business Machines Corporation
02/26/15
20150056752
new patent

Substrateless power device packages


A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer.. .
Alpha And Omega Semiconductor Incorporated
02/26/15
20150056751
new patent

Die edge sealing structures and related fabrication methods


Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region.
02/26/15
20150056750
new patent

Manufacturing semiconductor device


A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a transistor including the oxide semiconductor film, an etching mask is formed over the second insulating film, an opening portion exposing the electrode film is formed by etching a portion of the first insulating film and a portion of the second insulating film, the opening portion exposing the electrode film is exposed to argon plasma, the etching mask is removed, and a conductive film is formed in the opening portion exposing the electrode film. The first insulating film is an insulating film whose oxygen is partly released by heating.
Semiconductor Energy Laboratory Co., Ltd.
02/26/15
20150056730
new patent

Semiconductor device and manufacturing the same


According to an example of the invention, a method for manufacturing a semiconductor device, the method comprising: forming a light emitting semiconductor device layer that emits light by current injection; and forming at least one metal layer with etch barrier plated thereon on the semiconductor device layer, wherein the at least one metal layer provides mechanical support to the semiconductor device, wherein the etch barrier is plated on the at least one metal layer in a direction that the etch barrier can prevent side wall under-cut when the street lines are separated by wet chemical etching.. .
02/26/15
20150056727
new patent

Method of inspecting semiconductor device, fabricating semiconductor device, and inspection tool


A method of inspecting a semiconductor device includes attaching an inspection tool on a back surface of a semiconductor substrate including the semiconductor device, the inspection tool including a sheet and a holding frame, the sheet being larger than the semiconductor substrate and being provided with an opening in a center portion of the sheet, the opening being smaller than the semiconductor substrate, the holding frame holding an outer periphery of the sheet, and a supporting substrate being attached on a front surface of the semiconductor substrate, removing the supporting substrate attached on the front surface of the semiconductor substrate, and measuring electrical characteristics of the semiconductor device.. .
Kabushiki Kaisha Toshiba
02/26/15
20150055421
new patent

Semiconductor device


A semiconductor device includes a memory array including memory cells, page buffers suitable for reading data from the memory cells, cache latch circuits suitable for latching read data from the page buffers, and transmitting latched data to data lines in response to a column selection signal, a column selector suitable for outputting the column selection signal to the cache latch circuits through column selection lines in response to a column address, and sense amplifiers suitable for outputting transmitted data of the data lines by sensing voltages of the data lines, in which the cache latch circuits are connected to the column selector and the sense amplifiers through the column selection lines and the data lines, respectively, and have inverse relationship between the column selection lines and the data lines in length.. .
Sk Hynix Inc.
02/26/15
20150055401
new patent

Semiconductor devices including dual gate electrode structures and related methods


A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region.
Samsung Electronics Co., Ltd.
02/26/15
20150055399
new patent

Reservoir capacitor and semiconductor device including the same


A reservoir capacitor includes a first capacitor group having two or more capacitors, which are serially coupled to each other between a first power voltage supply terminal and a second power voltage supply terminal, a second capacitor group having two or more capacitors, which are serially coupled to each other between a third power voltage supply terminal and a fourth power voltage supply terminal and a connection line suitable for electrically coupling a first coupling node between the capacitors of the first capacitor group to a second coupling node between the capacitors of the second capacitor group.. .
Sk Hynix Inc.
02/26/15
20150055394
new patent

Semiconductor device


A semiconductor device comprises a semiconductor substrate including first and second regions that have different conductivity types from each other; an isolation region extending continuously over the first and second regions and having a shallow trench covered by a field insulator; first and second active regions placed in respective first and second regions and being each surrounded by the isolation region; a gate electrode disposed in a lower portion of a gate groove that extends continuously from the first active region to the second active region via the isolation region, the gate groove being shallower than the shallow trench; a cap insulating film disposed in an upper portion of the gate groove so as to cover an upper surface of the gate electrode; first and second transistors placed in respective first and second active regions and sharing the gate electrode; and a logic circuit including the first and second transistors connected in series.. .
Micron Technology, Inc.
02/26/15
20150055393
new patent

Semiconductor device having multi-level wiring structure


Disclosed herein is a device that includes a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer; a memory cell array area including a plurality of memory cells, a plurality of sense amplifiers and a plurality of sub amplifiers; a main amplifier area including a plurality of main amplifiers, the memory cell array area and the main amplifier area being arranged in line in a first direction; and a plurality of first i/o lines each connecting an associated one of the sub amplifiers to an associated one of the main amplifiers, each of the first i/o lines including first and second wiring portions that are elongated in the first direction, the first wiring portion being formed as the first wiring layer and the second wiring portion being formed as the second wiring layer.. .
Ps4 Luxco S.a.r.l.
02/26/15
20150055384
new patent

Five-level four-switch dc-ac converter


A single-phase dc-ac converter generates an ac voltage with five levels at the output converter side by using four controlled power switches. The converter has a relationship between the number of levels per number of switches (nl/ns) of five to four.
Indiana University Research & Technology Corporation
02/26/15
20150054571
new patent

Charge pump circuit and semiconductor device including the same


Efficiency of a charge pump circuit is increased. The charge pump circuit includes serially connected fundamental circuits each including a diode-connected transistor and a capacitor.
Semiconductor Energy Laboratory Co., Ltd.
02/26/15
20150054570
new patent

Semiconductor device with multiple space-charge control electrodes


A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device.
Sensor Electronic Technology, Inc.
02/26/15
20150054565
new patent

Systems and methods for operating high voltage switches


A system for communicating high voltages for a semiconductor device is provided. One system includes a controller having an input pad and an output pad, each of the input pad and the output pad being coupled to a respective high voltage switch of the controller.
Sandisk Technologies Inc.
02/26/15
20150054561
new patent

Semiconductor device and cascading matched frequency window tuned lc tank buffers


A tunable buffer circuit has a first tunable buffer cell receiving an input signal. A first transmission line is coupled to the first tunable buffer cell.
Semtech Corporation
02/26/15
20150054551
new patent

Line driving circuit improving signal characteristic and semiconductor device including the same


A line driving circuit in which a signal characteristic is improved and a semiconductor device including the same are provided. The semiconductor device includes: an line controller arranged in a first portion of at least one line; a first driver arranged in the first portion and configured to output through the at least one line a first signal according to a control of the line controller; and a second driver arranged in a second portion of the at least one line and configured to output through the at least one line a second signal according to a level of the first signal..
Samsung Electronics Co., Ltd.
02/26/15
20150054548
new patent

Semiconductor device and manufacturing semiconductor device


A manufacturing method of a semiconductor device in which the threshold is adjusted is provided. In a semiconductor device including a plurality of transistors arranged in a matrix each including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more.
Semiconductor Energy Laboratory Co., Ltd.
02/26/15
20150054532
new patent

Test device and test system including the same


A test device includes a test unit and a voltage selection circuit. The test unit is configured to detect a voltage at a test pad of a semiconductor device under test by applying a test current to the test pad.
Samsung Electronics Co., Ltd.
02/26/15
20150054176
new patent

Methods of fabricating semiconductor devices and devices fabricated thereby


Methods of fabricating semiconductor devices are provided including performing two photolithography processes and two spacer processes such that patterns are formed to have a pitch that is smaller than a limitation of photolithography process. Furthermore, line and pad portions are simultaneously defined by performing the photolithography process once and, thus, there is no necessity to perform an additional photolithography process for forming the pad portion.
02/26/15
20150054175
new patent

Semiconductor device and making same


One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.. .
Infineon Technologies Ag
02/26/15
20150054173
new patent

Semiconductor package, manufacturing semiconductor package and stack type semiconductor package


Disclosed herein are a semiconductor package, a method of manufacturing a semiconductor package, and a stack type semiconductor package. The semiconductor package according to a preferred embodiment of the present invention includes: a base substrate on which a first circuit layer is formed; a semiconductor device formed on the base substrate; a molding part formed on the base substrate and formed to enclose the first circuit layer and the semiconductor device; a first via formed on the first circuit layer and formed to penetrate through the molding part; and a second circuit layer formed on an upper surface of the molding part and integrally formed with the first via..
Samsung Electro-mechanics Co., Ltd.
02/26/15
20150054172
new patent

Semiconductor device and manufacturing the same


According to one embodiment, a semiconductor device includes an integrated circuit and a conductive material. The integrated circuit is provided on a surface of a semiconductor layer.
Kabushiki Kaisha Toshiba
02/26/15
20150054171
new patent

Semiconductor device and manufacturing the same


A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate on which a contact region and a cell region are defined, sub-patterns formed in the contact region, on the substrate, and insulating patterns and conductive patterns stacked alternately along the sub-patterns..
Sk Hynix Inc.
02/26/15
20150054170
new patent

Semiconductor devices and methods of manufacture thereof


Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes conductive features disposed over a workpiece, each conductive feature including a conductive line portion and a via portion.
Taiwan Semiconductor Manufacturing Company, Ltd.
02/26/15
20150054167
new patent

Semiconductor device and forming pad layout for flipchip semiconductor die


A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads.
Stats Chippac, Ltd.
02/26/15
20150054163
new patent

Systems and methods to enhance passivation integrity


A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer.
Taiwan Semiconductor Manufacturing Co., Ltd.
02/26/15
20150054161
new patent

Semiconductor bonding structure and process


A system and method for bonding semiconductor devices is provided. An embodiment comprises halting the flow of a eutectic bonding material by providing additional material of one of the reactants in a grid pattern, such that, as the eutectic material flows into the additional material, the additional material will change the composition of the flowing eutectic material and solidify the material, thereby stopping the flow.
Taiwan Semiconductor Manufacturing Company, Ltd.
02/26/15
20150054151
new patent

Semiconductor device and forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure


A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer.
Stats Chippac, Ltd.
02/26/15
20150054146
new patent

Semiconductor device


A semiconductor device of the present invention includes a semiconductor element having an electrode pad; a substrate over which the semiconductor element is mounted and which has an electrical bonding part; and a bonding wire electrically connecting the electrode pad to the electrical bonding part, wherein a main metal component of the electrode pad is the same as or different from a main metal component of the bonding wire, and when the main metal component of the electrode pad is different from the main metal component of the bonding wire, a rate of interdiffusion of the main metal component of the bonding wire and the main metal component of the electrode pad at a junction of the bonding wire and the electrode pad under a post-curing temperature of an encapsulating resin is lower than that of interdiffusion of gold (au) and aluminum (al) at a junction of aluminum (al) and gold (au) under the post-curing temperature.. .
Sumitomo Bakelite Co., Ltd.
02/26/15
20150054138
new patent

Semiconductor device having stacked substrates with protruding and recessed electrode connection


A first substrate with a penetration electrode formed thereon is stacked on a second substrate with a protruding electrode formed thereon. The penetration electrode has a recessed portion.
Seiko Epson Corporation
02/26/15
20150054137
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes a semiconductor substrate having opposed main and back surfaces; first and second electrodes in a device region of the substrate, and spaced apart from each other; a metal film on the main surface and joined to the second electrode; an air gap between part of the main surface and the metal film, enveloping the first electrode, and having an opening; a cured resin closing the opening; a liquid repellent film increasing contact angle of the resin, relative to contact angles on the substrate and the metal film; a first metal film joined to the metal film, covering the metal film and the cured resin, and joined to an outer peripheral region of the substrate, at a periphery of the device region; and a second metal film on the back surface and connected to the first electrode through a via hole penetrating the substrate.. .
Mitsubishi Electric Corporation
02/26/15
20150054136
new patent

Method of providing a via hole and routing structure


A method of providing a via hole and routing structure includes: providing a substrate wafer having recesses and blind holes provided in the surface of the wafer; providing an insulating layer in the recesses and holes; metallizing the holes and recesses; and removing the oxide layer in the bottom of the holes to provide contact between the back side and the front side of the wafer. A semiconductor device, including a substrate having at least one metallized via extending through the substrate and at least one metallized recess forming a routing together with the via.
Silex Microsystems Ab
02/26/15
20150054129
new patent

Semiconductor device with pads of enhanced moisture blocking ability


A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film..
Fujitsu Semiconductor Limited
02/26/15
20150054128
new patent

Semiconductor device including an electrode lower layer and an electrode upper layer and manufacturing semiconductor device


The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer.
Rohm Co., Ltd.
02/26/15
20150054119
new patent

Device structure for reducing leakage current of semiconductor devices with floating buried layer


A device structure is provided to reduce the leakage current of semiconductor devices with a floating buried layer (fbl), includes a substrate, a first epitaxial layer, a split floating buried layer, a second epitaxial layer, a doped trench, a protected device, a surface junction termination extension (s-jte) and a scribe street. The device and the s-jte are designed at the second epitaxial layer and the split floating buried layer at the joint of the first and second epitaxial layers.
China Electronic Technology Corporation, 24th Research Institute
02/26/15
20150054118
new patent

Semiconductor device


A semiconductor device includes a semiconductor substrate, and a field plate portion formed on a front surface of a non-cell region. The non-cell region includes a plurality of flr layers.
Toyota Jidosha Kabushiki Kaisha
02/26/15
20150054117
new patent

Semiconductor devices with guard rings


Semiconductor devices with guard rings are described. The semiconductor devices may be, e.g., transistors and diodes designed for high-voltage applications.
Transphorm Inc.
02/26/15
20150054110
new patent

Semiconductor device and manufacturing method thereof


Provided are a semiconductor device in which a solid-state image sensing element having a backside-illuminated structure and capacitor elements storing therein some of the charges supplied from light receiving elements has further improved reliability and a manufacturing method thereof. In the solid-state image sensing element of the semiconductor device, first and second substrates are joined together at a junction surface.
Renesas Electronics Corporation
02/26/15
20150054094
new patent

Semiconductor devices with asymmetric halo implantation and manufacture


A method includes forming a hardmask over one or more gate structures. The method further includes forming a photoresist over the hardmask.
International Business Machines Corporation
02/26/15
20150054089
new patent

Semiconductor devices having 3d channels, and methods of fabricating semiconductor devices having 3d channels


A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the second fin, and a second trench arranged between the second fin and the third fin. The semiconductor device further includes a first field insulating film arranged in the first trench, a second field insulating film formed in the second trench, a first dummy gate arranged on the first field insulating film, and a second dummy gate at least partly arranged on the second field insulating film.
Samsung Electronics Co., Ltd.
02/26/15
20150054086
new patent

Semiconductor device and manufacturing same


A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.. .
Micron Technology, Inc.
02/26/15
20150054083
new patent

Strain engineering in semiconductor devices by using a piezoelectric material


An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain..
Globalfoundries Inc.
02/26/15
20150054081
new patent

Epitaxial semiconductor resistor with semiconductor structures on same substrate


An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region.
International Business Machines Corporation
02/26/15
20150054075
new patent

Semiconductor device


There is provided a semiconductor device. An n-type transistor is formed on a (551) surface of a silicon substrate.
Tohoku University
02/26/15
20150054074
new patent

Semiconductor devices and methods of manufacturing the same


Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer..
Institute Of Microelectronics, Chinese Academy Of Sciences
02/26/15
20150054073
new patent

Semiconductor devices and methods for manufacturing the same


Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer; and forming a stressed interlayer dielectric layer on the substrate..
Institute Of Microelectronics, Chinese Academy Of Sciences
02/26/15
20150054071
new patent

High voltage semiconductor device and fabricating the same


A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein.
Vanguard International Semiconductor Corporation
02/26/15
20150054069
new patent

Semiconductor device including a mosfet


A semiconductor device for use in a power supply circuit has first and second mosfets. The source-drain path of one of the mosfets are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths.
Renesas Electronics Corporation
02/26/15
20150054068
new patent

Semiconductor device with enhanced mobility and method


In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor..
Semiconductor Components Industries, Llc
02/26/15
20150054066
new patent

Semiconductor devices including vertical transistors, electronic systems including the same and methods of manufacturing the same


The semiconductor device includes word lines on a semiconductor substrate, common gates connected to each of the word lines and vertically disposed in the semiconductor substrate, buried bit lines intersecting the word lines at a non-right angle in a plan view, and a pair of vertical transistors sharing each of the common gates. The pair of vertical transistors is disposed on both sides of one of the word lines.
Sk Hynix Inc.
02/26/15
20150054064
new patent

Power semiconductor device with super junction structure and interlaced, grid-type trench network


A power semiconductor device includes a semiconductor wafer having thereon a plurality of die regions and scribe lanes between the die regions. A first epitaxial layer is disposed on the semiconductor wafer.
Anpec Electronics Corporation
02/26/15
20150054062
new patent

Power semiconductor device and fabrication method thereof


A power semiconductor device includes a cell region on a semiconductor substrate, at least a transistor device in the cell region, a peripheral termination region encompassing the cell region, a plurality of epitaxial islands arranged around the cell region, and a grid type epitaxial layer in the peripheral termination region. The grid type epitaxial layer separates the plurality of epitaxial islands from one another..
Anpec Electronics Corporation
02/26/15
20150054054
new patent

Semiconductor devices


A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.. .
Samsung Electronics Co., Ltd.
02/26/15
20150054051
new patent

Semiconductor device and fabrication method


Semiconductor devices and fabrication methods are provided. A semiconductor substrate includes a first region and a second region.
Semiconductor Manufacturing International (beijing) Corporation
02/26/15
20150054045
new patent

Semiconductor device and manufacturing the same


Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a cg shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the cg shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region..
Renesas Electronics Corporation
02/26/15
20150054032
new patent

Methods for making a semiconductor device with shaped source and drain recesses and related devices


A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack..
International Business Machines Corporation
02/26/15
20150054028
new patent

Semiconductor devices having tensile and/or compressive stress and methods of manufacturing


Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers.
International Business Machines Corporation
02/26/15
20150054026
new patent

Inhomogeneous power semiconductor devices


A power semiconductor device includes a power transistor including a plurality of transistor cells on a semiconductor die. At least some of the transistor cells are inhomogeneous by design so that the number of current filaments in the transistor cells with reduced local current density increases and fewer transient avalanche oscillations occur in the power transistor during operation..
Infineon Technologies Ag
02/26/15
20150054025
new patent

Semiconductor device and semiconductor device manufacturing method


An n-type low lifetime adjustment region is provided in a portion inside an n− type drift region deeper than the bottom surface of a termination p-type base region or p-type guard ring from a substrate front surface, separated from the termination p-type base region and the p-type guard ring. The carrier lifetime of the n-type low lifetime adjustment region is shorter than the carrier lifetime of the n− type drift region.
Fuji Electric Co., Ltd.
02/26/15
20150054024
new patent

Semiconductor device


A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.. .
Mitsubishi Electric Corporation
02/26/15
20150054019
new patent

Semiconductor device


A semiconductor device includes an electrode including a plurality of pillars, a semiconductor element configured to be electrically-connected with the electrode, a substrate having electrode patterns, and a conductive adhesive layer located between the substrate and the electrode, the conductive adhesive layer including conductive substances configured to electrically-connect the pillars and the electrode patterns to each other, and including a body which encloses the conductive substances.. .
Lg Electronics Inc.


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