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Semiconductor Device patents



      
           
This page is updated frequently with new Semiconductor Device-related patent applications. Subscribe to the Semiconductor Device RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Device RSS RSS


Single layer bga substrate process

Method and system for a gallium nitride vertical jfet with self-aligned gate metallization

Methods and apparatus of packaging of semiconductor devices

Date/App# patent app List of recent Semiconductor Device-related patents
07/24/14
20140208142
 Semiconductor device patent thumbnailnew patent Semiconductor device
Supply of power to a plurality of circuits is controlled efficiently depending on usage conditions and the like of the circuits. An address monitoring circuit monitors whether a cache memory and an input/output interface are in an access state or not, and performs power gating in accordance with the state of the cache memory and the input/output interface.
07/24/14
20140208044
 Semiconductor device and method of operating the same patent thumbnailnew patent Semiconductor device and method of operating the same
A method of operating a semiconductor device may comprise storing data in memory cells coupled to first word lines of memory blocks including the first word lines and second word lines located respectively between the first word lines, detecting a memory block, where data stored in the memory cells of the first word lines is invalidated, from the memory blocks, and storing data in memory cells coupled to the second word lines of the detected memory block.. .
07/24/14
20140206204
 Substrate processing apparatus, method of manufacturing semiconductor device, and non-transitory computer-readable recording medium patent thumbnailnew patent Substrate processing apparatus, method of manufacturing semiconductor device, and non-transitory computer-readable recording medium
Provided is a substrate processing apparatus including a reaction chamber configured to heat a substrate; a transfer chamber configured to transfer the heated substrate; a refrigerant flow path installed in the reaction chamber; a refrigerant flow path installed in the reaction chamber; a refrigerant supply unit installed in the refrigerant flow path; a refrigerant exhaust unit installed in the refrigerant flow path; a transfer chamber refrigerant supply unit installed in the transfer chamber; a transfer chamber refrigerant exhaust unit installed in the transfer chamber; a heat exchanger connected to the refrigerant exhaust pipe and the transfer chamber refrigerant exhaust unit; a turbine connected to the heat exchanger; a generator connected to the turbine; and a control unit configured to control the refrigerant supply unit and the transfer chamber refrigerant supply unit.. .
07/24/14
20140206203
 Methods of forming a poruous insulator, and related methods of forming semiconductor device structures patent thumbnailnew patent Methods of forming a poruous insulator, and related methods of forming semiconductor device structures
Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough.
07/24/14
20140206202
 Manufacturing method of semiconductor device and semiconductor manufacturing apparatus patent thumbnailnew patent Manufacturing method of semiconductor device and semiconductor manufacturing apparatus
A manufacturing method of a semiconductor device according to the present invention comprises cleaning a semiconductor substrate. A first chemical liquid for forming a water-repellent protection film and a second chemical liquid coating the first chemical liquid are supplied on a surface of the semiconductor substrate.
07/24/14
20140206194
 Method for manufacturing a semiconductor device patent thumbnailnew patent Method for manufacturing a semiconductor device
A method for manufacturing a semiconductor device includes forming an etch-target layer over a semiconductor substrate having a lower structure, forming a first mask pattern over the etch-target layer, forming a spacer material layer with a uniform thickness over the etch-target layer including the first mask pattern, forming a second mask pattern on an indented region of the space material layer, and etching the etch-target layer with the first mask pattern and the second mask pattern as an etch mask to form a fine pattern.. .
07/24/14
20140206191
 Etchant and etching process patent thumbnailnew patent Etchant and etching process
A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate.
07/24/14
20140206187
 Method for manufacturing semiconductor device patent thumbnailnew patent Method for manufacturing semiconductor device
A method for manufacturing semiconductor device includes preparing a structure including a substrate, an insulating layer on the substrate and having a recess, a barrier film on the insulating layer, and a copper film on the barrier such that the copper film is filling the recess with the barrier between the insulating layer and copper film, removing the copper film down to interface with the barrier such that copper wiring is formed in the recess, etching the wiring such that surface of the wiring is recessed from surface of the insulating layer, and removing the barrier from the surface of the insulating layer such that the surface of the insulating layer is exposed. The etching includes positioning the structure removed down to the barrier in organic compound atmosphere having vacuum state, and irradiating oxygen gas cluster ion beam on the surface of the wiring to anisotropically etch the wiring..
07/24/14
20140206186
 Method of manufacturing a semiconductor device patent thumbnailnew patent Method of manufacturing a semiconductor device
A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.. .
07/24/14
20140206174
 Method of making semiconductor device patent thumbnailnew patent Method of making semiconductor device
A method for fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, and a first region, a second region and a third region are defined thereon.
07/24/14
20140206173
new patent Method for processing semiconductors using a combination of electron beam and optical lithography
Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as tan and the semiconductor device is a gan semiconductor device.
07/24/14
20140206169
new patent Methods of fabricating semiconductor device using nitridation of isolation layers
A method of forming a semiconductor device can include providing a plasma nitrided exposed top surface including an active region and an isolation region. The exposed top surface including the active region and the isolation region can be subjected to etching to form a deeper recess in the active region that in the isolation region and an unmerged epitaxial stress film can be grown in the deeper recess..
07/24/14
20140206167
new patent Contact structure of semiconductor device
A method of fabricating a semiconductor device comprises epitaxially-growing a strained material in a cavity of a substrate comprising a major surface and the cavity, the cavity being below the major surface. A lattice constant of the strained material is different from a lattice constant of the substrate.
07/24/14
20140206166
new patent Finfet device and method of manufacturing same
A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate.
07/24/14
20140206161
new patent Method of fabricating a semiconductor device having a capping layer
A method of semiconductor device fabrication includes forming a first dummy gate structure in a first region of a semiconductor substrate and forming a second dummy gate structure in a second region of the semiconductor substrate. A protective layer (e.g., oxide and/or silicon nitride hard mask) is formed on the second dummy gate structure.
07/24/14
20140206159
new patent Method for manufacturing compound semiconductor device
A compound semiconductor device includes: a compound semiconductor multilayer structure; a gate insulating film on the compound semiconductor multilayer structure; and a gate electrode, wherein the gate electrode includes a gate base portion on the gate insulating film and a gate umbrella portion, and a surface of the gate umbrella portion includes a schottky contact with the compound semiconductor multilayer structure.. .
07/24/14
20140206158
new patent Method for manufacturing semiconductor device
A semiconductor device includes: a semiconductor layer disposed above a substrate; an insulating film formed by oxidizing a portion of the semiconductor layer; and an electrode disposed on the insulating film, wherein the insulating film includes gallium oxide, or gallium oxide and indium oxide.. .
07/24/14
20140206156
new patent Finfet device and method of manufacturing same
A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate.
07/24/14
20140206155
new patent Semiconductor device and manufacturing method thereof
The reliability of a semiconductor device including a mosfet formed over an soi substrate is improved. A manufacturing method of the semiconductor device is simplified.
07/24/14
20140206154
new patent Semiconductor device comprising a passive component of capacitors and process for fabrication
A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside.
07/24/14
20140206152
new patent Single layer bga substrate process
The present disclosure provides semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board.
07/24/14
20140206148
new patent Semiconductor-encapsulating adhesive, semiconductor-encapsulating film-form adhesive, method for producing semiconductor device, and semiconductor device
The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator..
07/24/14
20140206147
new patent Stacked microelectronic assembly with tsvs formed in stages and carrier above chip
A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element.
07/24/14
20140206144
new patent Semiconductor device and manufacturing method thereof
In one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first and second semiconductor chips are electrically connected via first bump connection parts.
07/24/14
20140206133
new patent Method for manufacturing semiconductor device
To reduce defects in an oxide semiconductor film in a semiconductor device. To improve electrical characteristics of and reliability in the semiconductor device including an oxide semiconductor film.
07/24/14
20140206115
new patent Optoelectronic semiconductor device and the manufacturing method thereof
The present application provides a method of manufacturing an optoelectronic semiconductor device, comprising the steps of: providing a substrate; forming an optoelectronic system on the substrate; forming a barrier layer on the optoelectronic system; forming an electrode on the barrier layer; and annealing the optoelectronic semiconductor device; wherein the optoelectronic semiconductor device has a first forward voltage before the annealing step and has a second forward voltage after the annealing step, and a difference between the second forward voltage and the first forward voltage is smaller than 0.2 volt.. .
07/24/14
20140206111
new patent Semiconductor device manufacturing method
To improve the performance of a semiconductor device, a semiconductor device manufacturing method includes an exposing process of performing pattern exposure of a resist film formed on a substrate by using euv light reflected from a front surface of an euv mask as a reflective mask. In this exposing process, the resist film is subjected to pattern exposure by repeating a process of irradiating the resist film with the euv light by changing a focal position of the euv light with which the resist film is irradiated, along a film thickness direction of the resist film.
07/24/14
20140206110
new patent Etchant and etching process
A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration.
07/24/14
20140206107
new patent Semiconductor ferroelectric device, manufacturing method for the same, and electronic device
A manufacturing method for a semiconductor device, the method including forming a thin film transistor by forming a polysilicon thin film on an insulating substrate, forming a gate electrode via a gate insulating film, and forming source/drain regions and a channel region by ion implantation in the polysilicon thin film by using the gate electrode as a mask, forming an interconnection layer on an interlayer dielectric film covering this thin film transistor and forming a first contact to be connected to the thin film transistor through the interlayer dielectric film, forming a silicon hydronitride film on the interlayer dielectric film so as to cover the interconnection layer, forming a lower electrode on this silicon hydronitride film and forming a second contact to be connected to the interconnection layer through the silicon hydronitride film, and forming a ferroelectric layer on the lower electrode.. .
07/24/14
20140205954
new patent Method for forming patterns of semiconductor device by using mixed assist feature system
A method for forming patterns of a semiconductor device includes providing a photomask that includes an array of contact holes in an active region, a plurality of first dummy contact holes for restricting pattern distortion of the contact holes in an area outside of the array of the contact holes, a plurality of first assist features for restricting pattern distortion of the first dummy contact holes disposed inside a corresponding one of the first dummy contact holes, and an array of second assist features for additionally restricting pattern distortion of the first dummy contact holes. The array of second assist features is disposed outside of the first dummy contact holes.
07/24/14
20140205953
new patent Method for forming semiconductor device
A method for forming a semiconductor device comprises the following steps: first, a substrate is provided, a first photo-etching process is carried out with a first photomask to form at least one device structure and a plurality of compensation structures, wherein the first photomask comprises at least one device pattern and a plurality of dummy patterns. A photoresist layer is then formed on the device structure and each compensation structures; a second photo-etching process is then carried out with a second photomask to remove each compensation structure..
07/24/14
20140205952
new patent Methods of forming patterns for semiconductor device structures
Methods of forming a pattern in a semiconductor device structure include deprotecting an outer portion of a first photosensitive resist material, forming a second photosensitive resist material, exposing portions of the first and second photosensitive resist materials to radiation, and removing the deprotected outer portion of the first photosensitive resist material and the exposed portions of the first and second photosensitive resist materials. Additional methods include forming a first resist material over a substrate to include a first portion and a relatively thicker second portion, deprotecting substantially the entire first portion and an outer portion of the second portion while leaving an inner portion of the second portion protected, and forming a second resist material over the substrate.
07/24/14
20140205950
new patent Coating composition for duv filtering, method of forming photoresist pattern using the same and method of fabricating semiconductor device by using the method
Provided are a coating composition for deep ultraviolet (duv) filtering during an extreme ultraviolet (euv) exposure, the coating composition including about 100 parts by weight of a solvent including a first solvent (the first solvent being an alcoholic solvent); and about 0.05 parts by weight to about 5 parts by weight of a coating polymer having a degree of absorption of about 50%/μm or greater with respect to 193-nm incident light.. .
07/24/14
20140205937
new patent Mask blank, transfer mask, method of manufacturing a transfer mask, and method of manufacturing a semiconductor device
A mask blank is used for manufacturing a binary mask adapted to be applied with arf excimer laser exposure light and has a light-shielding film for forming a transfer pattern on a transparent substrate. The light-shielding film has a laminated structure of a lower layer and an upper layer and has an optical density of 2.8 or more for the exposure light.
07/24/14
20140205865
new patent Battery monitoring system, semiconductor device, battery assembly system, battery monitoring ic
Provides a battery monitoring system including a battery cell number setting section that sets each lsi with the respectively individual number of battery cells c to which they are connected. When a command to sequentially measure the battery voltage of the battery cells is input, a cell selection control section compares the setting value with the commanded measurement start battery cell number.
07/24/14
20140205816
new patent Dicing-tape-integrated adhesive sheet, semiconductor device, multilayered circuit board and electronic component
According to the present invention, a dicing-tape-integrated adhesive sheet is provided in which connection between terminals of opposing members and encapsulating of voids between the members can be simultaneously performed and thus excellent workability is achieved. The dicing-tape-integrated adhesive sheet of the present invention has a laminated structure including an adhesive film which has a first terminal of a support body and a second terminal of an adherend that are electrically connected using solder and by which the support body and the adherend are adhered to each other and a dicing tape.
07/24/14
20140204970
new patent Semiconductor device
A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.. .
07/24/14
20140204696
new patent Memory device and semiconductor device
Provided is a memory device with reduced overhead power. A memory device includes a first circuit retaining data in a first period during which a power supply voltage is supplied; a second circuit saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which the power supply voltage is not supplied; and a third circuit saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which the power supply voltage is not supplied.
07/24/14
20140204655
new patent Memory device, semiconductor device, and detecting method
To provide a memory device which can perform verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, accurately in a short time. Each memory cell includes at least a first capacitor, a second capacitor, and a transistor which functions as a switching element for controlling supply, storage, and release of charge in the first capacitor and the second capacitor.
07/24/14
20140204649
new patent Memory element, semiconductor device, and writing method
A memory element includes: an electrical fuse provided to be inserted between a first input node and a second input node; and an antifuse provided to be inserted between the second input node and a third input node. The third input node is configured to be a node to which a voltage is allowed to be applied separately from a voltage to be applied to the first input node..
07/24/14
20140204645
new patent Semiconductor device
To supply a signal in which the occurrence of delays is prevented to a storage circuit. To provide a novel semiconductor device in which a load applied to a logic circuit is low.
07/24/14
20140204397
new patent Metrology method and apparatus, and device manufacturing method
Methods are disclosed for measuring target structures formed by a lithographic process on a substrate. A grating or other structure within the target is smaller than an illumination spot and field of view of a measurement optical system.
07/24/14
20140204041
new patent Semiconductor device
A semiconductor device connected to the display panel including the in-cell type touch sensor is configured as follows. The semiconductor device includes a driving circuit of the display panel, a touch sensing circuit of the touch sensor, a power supply circuit that supplies a power source to these circuits, and a bias control circuit that controls a bias current flowing through these circuits.
07/24/14
20140203994
new patent Antenna module and method for manufacturing the same
An antenna module includes a support body and an antenna body. The support body has a flat support surface and a support surface that extends obliquely upward from one side of the support surface.
07/24/14
20140203978
new patent Semiconductor device
In a semiconductor device in which a copper plating layer is used for a conductor of an antenna and in which an integrated circuit and the antenna are formed over the same substrate, an object is to prevent an adverse effect on electrical characteristics of a circuit element due to diffusion of copper, as well as to provide a copper plating layer with favorable adhesiveness. Another object is to prevent a defect in the semiconductor device that stems from poor connection between the antenna and the integrated circuit, in the semiconductor device in which the integrated circuit and the antenna are formed over the same substrate.
07/24/14
20140203877
new patent Semiconductor device
A semiconductor device is provided with: a field-effect transistor that has a source electrode and a drain electrode that are connected to a semiconductor layer, a gate electrode that is provided on the surface of the semiconductor layer between the source electrode and the drain electrode, and a field plate electrode that is provided on the surface of the semiconductor layer in the vicinity of the gate electrode via an insulating layer, wherein the field-effect transistor amplifies high frequency signals received by the gate electrode to be outputted from the drain electrode; and a voltage dividing circuit that divides a potential difference between the drain electrode and a reference potential gnd, and applies a bias voltage such that respective parts of the field plate electrode have a mutually equal potential.. .
07/24/14
20140203859
new patent Semiconductor device
To provide a semiconductor device capable of adjusting the timing of a clock signal or a high-quality semiconductor device. The semiconductor device includes a first transistor and a circuit including a second transistor.
07/24/14
20140203847
new patent Reliability in semiconductor device control
A gate control device for a semiconductor device includes at least one power supply module, at least one optical communication interface for receiving optical signals from two valve control units and converting them to electric signals for supply to a corresponding power supply module, where in normal operations mode one valve control unit is an active valve control unit and the other is a standby valve control unit, where the optical signal of an active unit energizes the gate control device and provides semiconductor device controlling data, a semiconductor device control module and a reliability control module that performs selection of active valve control unit.. .
07/24/14
20140203845
new patent Semiconductor device
Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor.
07/24/14
20140203832
new patent Apparatus for spinning test tray of in-line test handler and in-line test handler
Disclosed is an apparatus for spinning a test tray and an in-line test handler including the above apparatus, wherein the apparatus may include a supporting unit for supporting a test tray transported between first and second chamber units facing in the different directions, wherein the first chamber unit is provided at a predetermined interval from the second chamber unit; a base unit to which the supporting unit is spinnably connected; and a spinning unit which spins the test tray so that semiconductor devices received in the test tray are tested at the same arrangement in each of the first chamber unit and the second chamber unit.. .
07/24/14
20140203831
new patent Coaxial probe
Disclosed is a coaxial probe comprising, an internal conductor comprising an upper contact configured to contact a semiconductor device; a lower contact configured to contact a tester for testing the semiconductor device; and an internal elastic member configured to elastically bias at least one of the upper and lower contacts to make the upper and lower contacts distant from each other; an external conductor configured to surround the internal conductor; a plurality of gap members which is respectively inserted into opposite ends between the internal conductor and the external conductor to create a predetermined air gap between the internal conductor and the external conductor; and at least one external elastic member that is inserted into an external circumferential surface of the external conductor to elastically bias at least one of the semiconductor device and the tester to a direction that makes either the semiconductor device or the test distant from the external conductor.. .
07/24/14
20140203829
new patent Test jig and semiconductor device test method
The test jig includes: a package mounting plate on which a semiconductor device is placed; a plurality of penetrating holes provided in the package mounting plate; a socket portion in which a plurality of probe pins are disposed, the probe pins designed to come in contact with electrodes of the semiconductor device through the penetrating holes; and a gas injecting unit configured to inject gas to the package mounting plate through the socket portion. The test of the semiconductor device is performed with the gas injected from the gas injecting unit to the package mounting plate..
07/24/14
20140203827
new patent Integrated circuits and methods of forming the same with embedded interconnect connection to through-semiconductor via
Integrated circuits, methods of forming integrated circuits, and methods of sensing voiding between a through-semiconductor via and a subsequent layer that overlies the through-semiconductor via in integrated circuits are provided. An exemplary method of forming an integrated circuit includes forming a plurality of semiconductor devices on a semiconductor substrate.
07/24/14
20140203814
new patent Method and apparatus for measuring alpha particle induced soft errors in semiconductor devices
An apparatus includes a probe card, an alpha particle source and a shutter. The probe card includes a plurality of contact elements.
07/24/14
20140203762
new patent Semiconductor device and battery pack
In a battery monitoring system included in a secondary battery, high-accuracy charge control is enabled at low cost. A semiconductor device includes: a drive unit which drives a transistor for controlling the charge current of a secondary battery and which is configured to be capable of selecting one of plural different voltages as a drive voltage (vgc) for turning on the transistor; and a data processing control unit which performs program processing.
07/24/14
20140203455
new patent Feature patterning methods and structures thereof
Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer.
07/24/14
20140203454
new patent Semiconductor device and semiconductor module
A semiconductor device includes an analog integrated circuit and a digital integrated circuit provided on a major surface of a substrate. An analog ground terminal is provided for the analog integrated circuit, and digital ground terminals are provided for the digital integrated circuit.
07/24/14
20140203449
new patent Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via
Integrated circuits and methods of forming integrated circuits are provided herein, in which a plurality of semiconductor devices is formed on a semiconductor substrate. At least one through-semiconductor via is formed in the semiconductor substrate and an interlayer dielectric layer is formed overlying the at least one through-semiconductor via and the plurality of semiconductor devices.
07/24/14
20140203446
new patent Through silicon via device having low stress, thin film gaps and methods for forming the same
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a tsv device having a “buffer zone” or gap layer between the tsv and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices.
07/24/14
20140203444
new patent Semiconductor device and power source device
A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.. .
07/24/14
20140203443
new patent Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer.
07/24/14
20140203442
new patent Wiring structures for three-dimensional semiconductor devices
Wiring structures of three-dimensional semiconductor devices and methods of forming the same are provided. The wiring structures may include an upper wordline and a lower wordline, each of which extends in a longitudinal direction.
07/24/14
20140203441
new patent Semiconductor device and method of manufacturing the same
The semiconductor device includes a first conductive layer, a first interlayer insulating film, a bit line, a first insulating film, a second interlayer insulating film, and a second conductive layer. The first insulating film that covers a side surface of the bit line has a portion perpendicular to a main surface of a semiconductor substrate in a region lower than a position lower than an uppermost portion of the first insulating film by a thickness, in a direction along the main surface of the semiconductor substrate, of the first insulating film that covers the side surface of the bit line at a lowermost portion of the bit line..
07/24/14
20140203438
new patent Methods and apparatus of packaging of semiconductor devices
Methods and apparatuses for forming an under-bump metallization (ubm) pad above a dielectric layer are disclosed. The dielectric layer may be above a metal layer and comprises a first opening and a second opening surrounding the first opening, which divide the dielectric layer into a first area and a second area.
07/24/14
20140203431
new patent Semiconductor device
To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width w1 and a narrow part (a second portion) with a second width w2.
07/24/14
20140203426
new patent Semiconductor device including cooler
A semiconductor device includes a package and a cooler. The semiconductor package includes a semiconductor element, a metal member, and a molding member for encapsulating the semiconductor element and the metal member.
07/24/14
20140203423
new patent Semiconductor device and method for manufacturing same
The present specification relates to a semiconductor device in which a metal plate is attached onto a surface of a resin package, and provides a structure in which the metal plate is not easy to separate. The semiconductor device disclosed in the present specification includes semiconductor chips (igbt, diode), a resin package molding the semiconductor chips, and metal plates fixed onto the surface of the resin package.
07/24/14
20140203420
new patent Method for producing semiconductor device, and semiconductor device produced using production method
A method for producing a semiconductor device includes laser welding to bond an upper terminal and a lower terminal as internal wiring members of the semiconductor device. When the upper terminal is fixed to the lower terminal by the laser welding, a gap between an upper surface of the lower terminal and a lower surface of the upper terminal is equal to or more than 20 μm and equal to or less than 400 μm..
07/24/14
20140203415
new patent Semiconductor device and manufacturing method thereof, delamination method, and transferring method
A substrate and a delamination film are separated by a physical means, or a mechanical means in a state where a metal film formed over a substrate, and a delamination layer comprising an oxide film including the metal and a film comprising silicon, which is formed over the metal film, are provided. Specifically, a tft obtained by forming an oxide layer including the metal over a metal film; crystallizing the oxide layer by heat treatment; and performing delamination in a layer of the oxide layer or at both of the interface of the oxide layer is formed..
07/24/14
20140203412
new patent Through silicon vias for semiconductor devices and manufacturing method thereof
The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad.
07/24/14
20140203411
new patent Production method of semiconductor device, semiconductor wafer, and semiconductor device
A semiconductor wafer, includes: a plurality of element regions; a surface electrode that is disposed in each of the plurality of element regions; an insulating layer that is disposed in each of the plurality of element regions and of which height from a front side surface of the semiconductor wafer is higher than that of the surface electrode in a periphery of the surface electrode; and a dicing line groove that is formed in a front side surface of the semiconductor wafer, that surrounds the surface electrode with the insulating layer therebetween, of which height from the front side surface of the semiconductor wafer is lower than that of the insulating layer, and that extends to a perimeter of the semiconductor wafer; in which the insulating layer is formed with a communication passage that extends from a side of the surface electrode to the dicing line groove.. .
07/24/14
20140203410
new patent Die edge sealing structures and related fabrication methods
Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region.
07/24/14
20140203399
new patent Integrated circuits with magnetic core inductors and methods of fabrications thereof
In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate.
07/24/14
20140203398
new patent Integrated magnetic core inductors with interleaved windings
A coupled inductor topology for a thin-film magnetic core power inductor that enables efficient integrated power conversion. Coupled magnetic core inductors with interleaved windings inductors comprise magnetic films and partially or fully interleaved conductors.
07/24/14
20140203397
new patent Methods and apparatus for inductors and transformers in packages
Methods and apparatus for forming a semiconductor device package with inductors and transformers using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top die and a bottom die, or between a die and an interposer.
07/24/14
20140203393
new patent Semiconductor device
A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings..
07/24/14
20140203377
new patent Semiconductor devices
Semiconductor devices include a first gate pattern provided on the first active region, a second gate pattern over the first active region, a third gate pattern over the second active region, and a fourth gate pattern over the second active region. The second gate pattern is parallel to the first gate pattern in a first direction.
07/24/14
20140203375
new patent Reduced substrate coupling for inductors in semiconductor devices
The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region.
07/24/14
20140203374
new patent N/p boundary effect reduction for metal gate transistors
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate.
07/24/14
20140203373
new patent Device and methods for high-k and metal gate stacks
A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate.
07/24/14
20140203372
new patent Semiconductor device and fabrication method thereof
A semiconductor device includes an inter-layer dielectric (ild) layer over a substrate; and a first gate feature in the ild layer, the first gate feature comprising a first gate material and having a first resistance, wherein the first gate material comprises a first conductive material. The semiconductor device further includes a second gate feature in the ild layer, the second gate feature comprising a second gate material and having a second resistance higher than the first resistance, wherein the second material comprises at least 50% by volume silicon oxide..
07/24/14
20140203370
new patent Semiconductor device and fabricating method thereof
A semiconductor device is provided. The semiconductor device includes a first fin on a substrate, a first gate electrode formed on the substrate to intersect the first fin, a first elevated source/drain on the first fin on both sides of the first gate electrode, and a first metal alloy layer on an upper surface and sidewall of the first elevated source/drain..
07/24/14
20140203366
new patent Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (cmos) device includes a pmos transistor having at least two first gate electrodes comprising a first parameter, and an nmos transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter.
07/24/14
20140203365
new patent Semiconductor device
There is disclosed a semiconductor device. The device comprises: a silicon layer; a tapered insulating layer formed on the silicon layer; and a plurality of bipolar cmos dmos device layers formed above the tapered insulating layer.
07/24/14
20140203364
new patent Semiconductor device and manufacturing method of semiconductor device
A semiconductor device having an n channel misfet formed on an soi substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon.
07/24/14
20140203362
new patent Semiconductor devices including gates and dummy gates of different materials
Semiconductor devices are provided. The semiconductor devices may include an active pattern and a insulation layer.
07/24/14
20140203358
new patent Semiconductor device with enhanced 3d resurf
A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region..
07/24/14
20140203357
new patent Semiconductor device and method of manufacturing the same
According to a method of manufacturing a semiconductor device, hard mask lines are formed in parallel in a substrate and the substrate between the hard mask lines is etched to form grooves. A portion of the hard mask line and a portion of the substrate between the grooves are etched.
07/24/14
20140203356
new patent Semiconductor device including vertical semiconductor element
A semiconductor device including a vertical semiconductor element has a trench gate structure and a dummy gate structure. The trench gate structure includes a first trench that penetrates a first impurity region and a base region to reach a first conductivity-type region in a super junction structure.
07/24/14
20140203354
new patent Semiconductor device
A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor device also includes a body layer extending a first predetermined distance into the semiconductor layer of the second conductivity type and a pair of trenches extending a second predetermined distance into the semiconductor layer of the second conductivity type.
07/24/14
20140203353
new patent Method for manufacturing semiconductor device and semiconductor device
A method of manufacturing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer, a first insulating film around the fin-shaped semiconductor layer, and a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A second step forms a gate insulating film around the pillar-shaped semiconductor layer, a gate electrode around the gate insulating film, and a gate line.
07/24/14
20140203348
new patent Semiconductor devices and methods of fabricating the same
Provided is a semiconductor device, which includes a gate electrode crossing over a semiconductor fin disposed on a substrate, a gate dielectric layer disposed between the gate electrode and the semiconductor fin, a channel region having a three dimensional structure defined in the semiconductor fin under the gate electrode, impurity regions disposed in the semiconductor fin at both sides of the gate electrode and spaced apart from the gate electrode, a first interlayer dielectric layer covering an entire surface of the substrate, except for the gate electrode, first contact plugs passing through the first interlayer dielectric layer and contacting the impurity regions, and a second interlayer dielectric layer covering the gate electrode and partially filling a space between the gate electrode and the impurity regions to define an air gap between the gate electrode and the impurity regions.. .
07/24/14
20140203346
new patent Vertical type semiconductor devices including a metal gate and methods of forming the same
Vertical type semiconductor devices including a metal gate and methods of forming the vertical type semiconductor devices are provided. The vertical type semiconductor devices may include a channel pattern.
07/24/14
20140203339
new patent Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure
A semiconductor device includes a high-k metal gate electrode structure that is positioned above an active region, has a top surface that is positioned at a gate height level, and includes a high-k dielectric material and an electrode metal. Raised drain and source regions are positioned laterally adjacent to the high-k metal gate electrode structure and connect to the active region, and a top surface of each of the raised drain and source regions is positioned at a contact height level that is below the gate height level.
07/24/14
20140203337
new patent Method of forming gate dielectric layer and method of fabricating semiconductor device
A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process.. .
07/24/14
20140203335
new patent Semiconductor devices and methods for fabricating the same
A semiconductor device includes an insulating film on a substrate and including a trench, a gate insulating film in the trench, a dit (density of interface trap) improvement film on the gate insulating film to improve a dit of the substrate, and a first conductivity type work function adjustment film on the dit improvement film. Related methods of forming semiconductor devices are also disclosed..
07/24/14
20140203333
new patent Semiconductor device having modified profile metal gate
In one embodiment, a method includes providing a semiconductor substrate having a trench disposed thereon and forming a plurality of layers in the trench. The plurality of layers formed in the trench is etched thereby providing at least one etched layer having a top surface that lies below a top surface of the trench.
07/24/14
20140203328
new patent Method and system for a gallium nitride vertical jfet with self-aligned gate metallization
A semiconductor device includes a iii-nitride substrate and a first iii-nitride epitaxial layer coupled to the iii-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the iii-nitride substrate by the drift region.
07/24/14
20140203327
new patent Deep gate-all-around semiconductor device having germanium or group iii-v active layer
Deep gate-all-around semiconductor devices having germanium or group iii-v active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate.
07/24/14
20140203323
new patent Primer composition and optical semiconductor apparatus using same
The invention provides a primer composition which adheres a substrate mounting an optical semiconductor device and a cured material of an addition reaction curing silicone composition that encapsulates the optical semiconductor device, includes (a) silazane compound or polysilazane compounds that has one or more silazane bonds in the molecule, (b) acrylic resin containing either one or both of acrylate ester and methacrylate ester that contains one or more sih groups in the molecule, and (c) solvent. There can be provided a primer composition in which the adhesion between a substrate mounting an optical semiconductor device and a cured material of an addition reaction curing silicone composition that encapsulates the optical semiconductor device can be improved, the corrosion of a metal electrode on the substrate can be prevented, and the heat resistance and flexibility of a primer can be improved..
07/24/14
20140203299
new patent Semiconductor device
The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage vth of 0.3 v to 0.7 v and a leakage current jr of 1×10−9 a/cm2 to 1×10−4 a/cm2 in a rated voltage vr.. .
07/24/14
20140203298
new patent Strained silicon carbide channel for electron mobility of nmos
A semiconductor is formed on a (110) silicon (si) substrate, with improved electron mobility. Embodiments include semiconductor devices having a silicon carbide (sic) portion in the nfet channel region.
07/24/14
20140203295
new patent Integrated power device with iii-nitride half bridges
A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die.. .
07/24/14
20140203294
new patent Gallium nitride devices
Semiconductor structures comprising a iii-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance.
07/24/14
20140203291
new patent Semiconductor device and method for fabricating the same
A semiconductor device includes: an fet chip; pads provided on an upper surface of the fet chip; bumps provided on at least one of the pads; leads having first portions that are connected to the fet chip by the bumps and extend along the upper surface of the fet chip, and second portions that contact surfaces of the first portions along the upper surface of the fet chip and extend along a side surface of the fet chip, the first and second portions being formed by press or cutting; and a seal layer that seals the fet chip and the leads and a surface from which the second portions of the leads are exposed, the surface of the seal layer being on a lower surface side of the fet chip.. .
07/24/14
20140203288
new patent Compound semiconductor device having gallium nitride gate structures
The present disclosure provides a semiconductor structure. The semiconductor structure includes a buffer layer on a substrate, an graded aluminum gallium nitride (algan) layer disposed on the buffer layer, a gallium nitride (gan) layer disposed on the graded algan layer, a second algan layer disposed on the gan layer and a gate stack disposed on the second algan layer.
07/24/14
20140203284
new patent Semiconductor device and method for manufacturing the same
A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer.
07/24/14
20140203279
new patent Test structure and method to faciltiate development/optimization of process parameters
A test structure and method are provided to facilitate developing or optimizing a fabrication process by determining values of one or more lithography process parameters for use in semiconductor device fabrication. The test structure is configured to facilitate determining values of the one or more fabrication process parameters, and includes a plurality of test structure components arranged on a substrate according to a test pattern.
07/24/14
20140203277
new patent Semiconductor device and method for manufacturing the same
A miniaturized transistor having high electrical characteristics can be provided with high yield. High performance, high reliability, and high productivity of a semiconductor device including the transistor can be achieved.
07/24/14
20140203276
new patent Semiconductor device and method for manufacturing the same
To provide a highly reliable semiconductor device. The semiconductor device includes a first oxide layer over an insulating film; an oxide semiconductor layer over the first oxide layer; a gate insulating film over the oxide semiconductor layer; and a gate electrode over the gate insulating film.
07/24/14
20140203242
new patent Nitride semiconductor device
In the nitride semiconductor device of the present invention, an active layer 12 is sandwiched between a p-type nitride semiconductor layer 11 and an n-type nitride semiconductor layer 13. The active layer 12 has, at least, a barrier layer 2a having an n-type impurity; a well layer 1a made of a nitride semiconductor that includes in; and a barrier layer 2c that has a p-type impurity, or that has been grown without being doped.
07/24/14
20140203239
new patent Solid-state transducer devices with optically-transmissive carrier substrates and related systems, methods, and devices
Semiconductor device assemblies having solid-state transducer (sst) devices and associated semiconductor devices, systems, and are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a support substrate, a transfer structure, and a plurality semiconductor structures between the support substrate and the transfer structure.


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