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Semiconductor Device patents



      
           
This page is updated frequently with new Semiconductor Device-related patent applications. Subscribe to the Semiconductor Device RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Device RSS RSS


Encoder, decoder and semiconductor device including the same

Encoder, decoder and semiconductor device including the same

Encoder, decoder and semiconductor device including the same

Encoder, decoder and semiconductor device including the same

Encoder, decoder and semiconductor device including the same

Semiconductor device

Date/App# patent app List of recent Semiconductor Device-related patents
10/23/14
20140317581
 Revising layout design through opc to reduce corner rounding effect patent thumbnailRevising layout design through opc to reduce corner rounding effect
The present disclosure provides a method of fabricating a semiconductor device. A first layout design for a semiconductor device is received.
10/23/14
20140317472
 Encoder, decoder and semiconductor device including the same patent thumbnailEncoder, decoder and semiconductor device including the same
Provided is a semiconductor device configured to encode input data into a codeword including m different symbols, each of which includes nm symbols. The semiconductor device including a first storage unit configured to store a first state value which is reset according to m and nm; a second storage unit corresponding to any one of the m different symbols and configured to store m second state values determined through the corresponding symbol and the first state value; a third storage unit configured to store a third state value..
10/23/14
20140317468
 Encoder, decoder and semiconductor device including the same patent thumbnailEncoder, decoder and semiconductor device including the same
A semiconductor device may include a first encoding unit configured to encode first data into an anti-drift code, and a second encoding unit configured to add parity information to the anti-drift code.. .
10/23/14
20140317344
 Semiconductor device patent thumbnailSemiconductor device
A semiconductor device may include a storage unit configured to store a number of times a first command has been provided to a memory cell array, a control unit configured to generate a second command operable to activate at least one word line in the memory cell array based on a comparison of the number stored at the storage unit with a threshold value, when the first command is received, and a selection unit configured to select one of the first command and the second command based on a result of the comparison and transmit the selected command to the memory cell array.. .
10/23/14
20140317332
 Semiconductor device for performing test and repair operations patent thumbnailSemiconductor device for performing test and repair operations
A semiconductor device may include: a storage unit configured to store program codes provided through control of a processor core; and a control unit configured to perform a control operation on a semiconductor memory device according to the program codes.. .
10/23/14
20140315393
 Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium patent thumbnailMethod of manufacturing semiconductor device, substrate processing apparatus, and recording medium
A method of manufacturing a semiconductor device includes: pre-treating a surface of a substrate by supplying an oxygen-containing gas and a hydrogen-containing gas to the substrate heated in a process chamber under a pressure less than atmospheric pressure; and forming a film on the pre-treated substrate by performing a cycle a predetermined number of times. The cycle includes: supplying a precursor gas to the substrate in the process chamber; and supplying a reaction gas to the substrate in the process chamber..
10/23/14
20140315391
 Method of manufacturing a semiconductor device including a stress relief layer patent thumbnailMethod of manufacturing a semiconductor device including a stress relief layer
A method of manufacturing a semiconductor device includes providing a layered structure having a hard dielectric layer containing a first dielectric material having a young's modulus greater than 10 gpa in a central portion of a main surface of a main body comprising a single crystalline semiconductor body, and providing a dielectric stress relief layer containing a second dielectric material having a lower young's modulus than the first dielectric material, the stress relief layer covering the layered structure and extending beyond an outer edge of the layered structure.. .
10/23/14
20140315388
 Method of manufacturing semiconductor device patent thumbnailMethod of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes forming a second insulating layer over a first insulating layer, forming a mask over the second insulating layer, after the forming the mask, a first etching of the second insulating layer which is not covered by the mask, and after the first etching, a second etching of the second insulating layer and the first insulating layer which are not covered by the mask. At the first etching, the second insulating layer left over the first insulating layer and the first insulating layer is not exposed.
10/23/14
20140315382
 Interconnection wires of semiconductor devices patent thumbnailInterconnection wires of semiconductor devices
A method of forming a semiconductor device includes forming a plurality of substantially equal-spaced first spacers having a first pitch over a substrate and forming first metal interconnecting wires utilizing the first spacers. The method also includes forming a plurality of substantially equal-spaced second spacers in such a way to abut, respectively, the plurality of first metal interconnecting wires and define a plurality of substantially equal-spaced trenches.
10/23/14
20140315377
 Work function adjustment with the implant of lanthanides patent thumbnailWork function adjustment with the implant of lanthanides
Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal.
10/23/14
20140315374
Selective epitaxial growth of semiconductor materials with reduced defects
A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls.
10/23/14
20140315371
Methods of forming isolation regions for bulk finfet semiconductor devices
One method disclosed herein includes forming a plurality of fin-formation trenches in a semiconductor substrate that define a plurality of spaced-apart fins, forming a patterned liner layer that covers a portion of the substrate positioned between the fins while exposing portions of the substrate positioned laterally outside of the patterned liner layer, and performing at least one etching process on the exposed portions of the substrate through the patterned liner layer to define an isolation trench in the substrate, wherein the isolation trench has a depth that is greater than a depth of the fin-formation trenches.. .
10/23/14
20140315369
Resistive random access memory cells having metal alloy current limiting layers
Provided are semiconductor devices, such as resistive random access memory (reram) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon.
10/23/14
20140315366
Semiconductor device and method of making
The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by concurrently formed metal-semiconductor compound contact regions at the source and drain and metal-semiconductor compounds in vias formed at positions corresponding to the source and drain.
10/23/14
20140315365
Method of forming semiconductor device
A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate.
10/23/14
20140315359
Semiconductor device manufacturing method
A semiconductor device includes a p-type semiconductor layer, n-type column regions formed of columnar thermal donors exhibiting an n-type property, a p-type column region interposed between the n-type column regions, the n-type column regions configured to form a super-junction structure in cooperation with the p-type column region, a channel region formed in the semiconductor layer, a source region formed in the channel region, a gate insulator film formed on the semiconductor layer, and a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film.. .
10/23/14
20140315356
Semiconductor device and method for manufacturing the same
In a manufacturing method of a semiconductor device, a semiconductor chip is sealed with a resin, and then a laser is applied to remove the resin so that a part of the semiconductor chip is exposed. The semiconductor chip is made of a material that has a lower absorptivity of the laser than the resin and is not melted by the laser.
10/23/14
20140315352
Semiconductor device fabricating method
A semiconductor device fabricating method includes forming device chip regions and a monitor chip region for processing management, on a substrate surface layer on one main surface side of a semiconductor substrate wafer, each device chip region having an active region and an edge region; after forming metal films on front surface of the device chip regions and the monitor chip region by vapor deposition and photolithography, forming protective films on the front surfaces of the device chip regions and monitor chip region; and grinding and polishing another main surface side of the semiconductor substrate wafer to thin the semiconductor substrate wafer. A difference between an area of one chip occupied by the protective film of the monitor chip region and an area of one chip occupied by the protective film of the device chip region is 20% or less..
10/23/14
20140315349
Semiconductor device and method for manufacturing the same
A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region.
10/23/14
20140315337
Semiconductor device and method for manufacturing the same
According to one embodiment, a semiconductor device includes first, second, and third molded bodies. The first molded body covers a first light emitting element, a part of a lead electrically connected to the first light emitting element, a first light receiving element configured to detect a light emitted from the first light emitting element, and a part of a lead electrically connected to the first light receiving element with a first resin.
10/23/14
20140315330
Measurement device, measurement method, and method for manufacturing semiconductor device
There is provided a measuring apparatus including: an illuminator configured to illuminate, with an illumination light, a substrate having a pattern formed by exposure on a surface; a detector configured to detect the illumination light modulated by the pattern to output a detection signal; and a measuring unit configured to measure an exposure condition of the pattern of a desired portion by using the detection signals detected at a plurality of portions of the pattern.. .
10/23/14
20140314370
Optical semiconductor apparatus
An optical semiconductor device includes a silicon oxide layer configured to be formed on a substrate; an optical waveguide part configured to be formed on the silicon oxide layer; a cladding layer configured to be formed covering the optical waveguide part; and a semiconductor laser configured to be disposed on the substrate. Laser light emitted from the semiconductor laser enters the optical waveguide part.
10/23/14
20140313812
Semiconductor device, and microprocessor, processor, system, data storage system and memory system including the semiconductor device
A semiconductor device includes: a write current generator configured to generate a write current corresponding to a write reference voltage in a write mode and to have a negative feedback structure. The semiconductor device may further comprise a variable resistance device configured to have a resistance value that varies with the write current..
10/23/14
20140313811
Semiconductor device
A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines.
10/23/14
20140313809
Semiconductor apparatus
A semiconductor device may include first conductive patterns coupled to a common source and selection lines of a memory block formed at a substrate, second conductive patterns configured to form a bit line coupled to the memory block, and third conductive patterns configured to transmit a block selection signal to couple local lines of the memory block to global lines. The first to third conductive patterns are arranged in different layers over the memory block..
10/23/14
20140313642
Power stack structure and method
A power conversion apparatus includes plural press-pack power semiconductor devices; plural thermal and electric conducting blocks provided among the plural press-pack power semiconductor devices; and plural bus bars provided among the plural press-pack power semiconductor devices and the plural thermal and electric conducting blocks to form a first column that is clamped under a predetermined mechanical force. The plural bus bars are directly pressed in the first or more columns for electrical connection, at least one of the press-pack power semiconductor devices is sandwiched between two thermal and electrical conducting blocks, and at least one of the bus bars is sandwiched between two thermal and electric conducting blocks.
10/23/14
20140313445
Liquid crystal display device and electronic device
To provide a semiconductor device, a liquid crystal display device, and an electronic device which have a wide viewing angle and in which the number of manufacturing steps, the number of masks, and manufacturing cost are reduced compared with a conventional one. The liquid crystal display device includes a first electrode formed over an entire surface of one side of a substrate; a first insulating film formed over the first electrode; a thin film transistor formed over the first insulating film; a second insulating film formed over the thin film transistor; a second electrode formed over the second insulating film and having a plurality of openings; and a liquid crystal over the second electrode.
10/23/14
20140313317
Handler for testing semiconductor device and method for checking whether semiconductor device remains using the same
A handler for testing semiconductor device is disclosed. The handler for testing semiconductor device includes a socket plate having a test socket to be electrically connected to a tester, a device feeder configured to feed a semiconductor device to the test socket or recover the semiconductor device from the test socket, a camera obtaining an image of the test socket, a sensor sensing an exposing moment that at least one photographing area among photographing areas on the test socket is exposed to the camera, while the device feeder moves, and a controller configured to operate the camera to take a photograph at the exposing moment and to determine whether a semiconductor device remains in the test socket, using the image obtained by the camera..
10/23/14
20140313146
Touch panel controller and semiconductor device
The drive circuit operable to output a drive pulse pattern to drive electrodes of a touch panel is arranged so that it can change the pulse frequency of the drive pulse pattern for each drive electrode. The detection circuit operable to detect signal changes arising on detection electrodes of the touch panel for each drive pulse pattern output by the drive circuit is arranged so that it can change the sampling frequency of signal change for each detection electrode.
10/23/14
20140313111
System and methods for extracting correlation curves for an organic light emitting device
A system for compensating the input signals to arrays of pixels that include semiconductor devices that age differently under different ambient and stress conditions. The system creates a library of compensation curves for different stress conditions of the semiconductor devices; identifies the stress conditions for at least a selected one of the semiconductor devices based on the rate of change or absolute value of at least one parameter of at least the selected device; selects a compensation curve for the selected device based on the identified stress conditions; calculates compensation parameters for the selected device based on the selected compensation curve; and compensates an input signal for the selected device based on the calculated compensation parameters..
10/23/14
20140312972
High-frequency amplifier circuit, semiconductor device, and magnetic recording and reproducing device
A high-frequency amplifier circuit includes a balanced-unbalanced converter converting a single-ended signal into differential signals. The output of a first amplifier amplifying the single-ended signal is connected to the signal terminal on the unbalanced side of the balanced-unbalanced converter.
10/23/14
20140312961
Semiconductor device compensating for negative bias temperature instability effects and related methods of operation
A semiconductor device comprises a metal oxide semiconductor (mos) transistor circuit configured to receive a body bias voltage, and a negative bias temperature instability compensation (nbtic) circuit configured to measure a negative bias temperature instability level on the mos transistor circuit using an operating timing variation measuring unit and to adaptively compensate for a bias according to the measured value.. .
10/23/14
20140312960
Semiconductor device and operating method thereof
A substrate including a plurality of transistors, and a piezoelectric formed to be contacted with the substrate. The piezoelectric is formed heat-expendably in a direction parallel to a gate direction of the transistors..
10/23/14
20140312940
Semiconductor device with clock-based signal input circuit
A semiconductor device includes a signal input circuit suitable for synchronizing an input signal with a dock signal and receiving the dock signal as a power source when the input signal has a first phase.. .
10/23/14
20140312932
Storage device and semiconductor device
A low-power storage device is provided. The storage device includes a first transistor, a second transistor, a logic element, and a semiconductor element.
10/23/14
20140312930
Semiconductor device, semiconductor system including the semiconductor device, and method for driving the semiconductor system
A semiconductor device includes a plurality of pads, a plurality of data input/output units connected with the plurality of pads and enabled in response to a plurality of enable signals, and a group programming unit suitable for grouping the plurality of pads into a number of pad groups in response to a mode register set (mrs) code and group information, and generating a number of groups of enable signals corresponding to the number of pad groups, wherein a number of groups of the data input/output units are sequentially enabled in response to respective groups of the enable signals.. .
10/23/14
20140312870
Boost-type switching regulator and semiconductor device for boost-type switching regulator
A boost-type switching regulator includes an inductor; a rectifying element; a capacitor; a switching element; an output terminal; a detection voltage generating unit; an output voltage controlling unit; and a detection voltage level shifting unit. The detection voltage generating unit generates a detection voltage according to an output voltage.
10/23/14
20140312818
Semiconductor device and inverter system
A semiconductor device includes first and second resistor groups, first and second switch groups, a register, and an amplifier. The first resistor group includes plural first resistors connected in series between a first terminal and an output of the amplifier.
10/23/14
20140312514
Semiconductor device
[object] a semiconductor device is configured to release heat from semiconductor chips more efficiently. [means for solution] a semiconductor device includes: a die pad 11 which has a die pad main surface 111 and a die pad rear surface 112; a semiconductor chip 41 mounted on the die pad main surface 111; a sealing resin portion 7 formed with a recess 75 for exposure of the die pad rear surface 11 and covering the die pad 11 and the semiconductor chip 41; and a heat releasing layer 6 disposed in the recess 75.
10/23/14
20140312513
Semiconductor device, substrate and semiconductor device manufacturing method
The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor chip to the junction plane of a chip junction portion such as an island or a die pad. This semiconductor device includes a semiconductor chip and a chip junction portion having a junction plane that is bonded to the back surface of the semiconductor chip with a soldering material.
10/23/14
20140312512
Semiconductor device and method of forming bump interconnect structure with conductive layer over buffer layer
A semiconductor device has a substrate with a plurality of contact pads. A first insulation layer is formed over the substrate and contact pads.
10/23/14
20140312511
Manufacturing method for semiconductor device
Provided is a method of manufacturing a semiconductor device that has a plurality of semiconductor components and a plurality of resin layers, the method including: a step in which resin layers and semiconductor components are laminated alternately on a substrate, and the same is adhered by being subjected to heating and pressurization at a temperature lower than the temperature at which the substrate and/or a solder layer of the semiconductor components melts; and a step in which heat and pressure are applied at a temperature at which the solder layer melts or a temperature higher than said temperature.. .
10/23/14
20140312510
Semiconductor device
The present invention provides a non-insulated type dc-dc converter having a circuit in which a power mos•fet for a high side switch and a power mos•fet for a low side switch are connected in series. In the non-insulated type dc-dc converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips.
10/23/14
20140312507
Semiconductor device having a multilayer interconnection structure
A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure.. .
10/23/14
20140312506
Semiconductor device and method for manufacturing same
A semiconductor device includes a semiconductor substrate including a first surface in which an integrated circuit and an i/o pad electrically connected to the integrated circuit are formed, and a second surface which is an opposite side to the first surface, where a two-stage through-hole is formed in the semiconductor substrate, the semiconductor substrate including a first shape portion having a tapered shape which has a wall surface and of which a diameter of an opening becomes smaller toward a bottom of the hole from the second surface side to a predetermined position of the semiconductor substrate in a thickness direction, and including a second shape portion having a cylindrical shape which extends from the first shape portion to the i/o pad on the first surface side, and that includes an inorganic insulating film which is formed on the wall surface of the two-stage through-hole and the second surface.. .
10/23/14
20140312505
Semiconductor devices and fabrication methods thereof
A semiconductor device includes a first semiconductor chip, a first connection structure disposed on a first side of the first semiconductor chip, a second semiconductor chip disposed on a second side of the first semiconductor chip, and a second connection structure disposed between the first and second semiconductor chips, wherein a number of the second connection structures is less than a number of the first connection structures.. .
10/23/14
20140312502
Through-vias for wiring layers of semiconductor devices
Through-via structures and methods of their formation are disclosed. In one such method, a first etch through at least a first dielectric material of a wiring layer is performed such that a first hole outlining a collar structure for the through-via is formed.
10/23/14
20140312500
Combining cut mask lithography and conventional lithography to achieve sub-threshold pattern features
Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip.
10/23/14
20140312499
Semiconductor device and manufacturing method thereof
The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed..
10/23/14
20140312498
Semiconductor device and method of manufacturing same
In a wiring board of bga, an insulation layer has thereon a plurality of bonding leads. The insulation layer is comprised of a prepreg having a glass cloth and a resin layer not having the glass cloth.
10/23/14
20140312497
Molding material and method for packaging semiconductor chips
A method and apparatus for packaging a semiconductor chip is presented. A semiconductor device includes a chip, a lead, and an encapsulant.
10/23/14
20140312496
Semiconductor package and semiconductor device
The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed.
10/23/14
20140312495
Fan out integrated circuit device packages on large panels
A method of manufacturing an integrated circuit package. The method comprises providing a carrier substrate having a planar surface.
10/23/14
20140312493
Semiconductor device and a method of manufacturing the same
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode.
10/23/14
20140312491
Semiconductor device, semiconductor package, and electronic system
Provided are a semiconductor device, a semiconductor package, and an electronic system. The device includes a substrate having a front side and a back side disposed opposite the front side.
10/23/14
20140312480
Double-side exposed semiconductor device
A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively.
10/23/14
20140312472
Method of manufacturing semiconductor device and semiconductor device
Provided is a method of manufacturing a semiconductor device which includes, in the following order: a first step of preparing a semiconductor element which includes a pn junction exposure portion; a second step of forming an insulation layer such that the insulation layer covers the pn junction exposure portion; and a third step of forming a glass layer on the insulation layer where a layer made of glass composition for protecting a semiconductor junction is formed on the insulation layer and, thereafter, the layer made of glass composition for protecting a semiconductor junction is baked.. .
10/23/14
20140312471
Semiconductor device and manufacturing method thereof
A semiconductor device has a plurality of closely spaced fins each coated at its top and sidewalls with a sige layer used for improving charge carrier mobility in a channel portion of the device. The sidewalls of the closely adjacent fins are selectively thinned so as to prevent an undesired bridging of sige material between immediately adjacent ones of the fins.
10/23/14
20140312470
Seal ring structure with capacitor
A semiconductor device includes a semiconductor substrate of a first conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate.
10/23/14
20140312467
Through-vias for wiring layers of semiconductor devices
Through-via structures and methods of their formation are disclosed. One such structure includes a conductor structure, a dielectric via lining and a stress-abating dielectric material.
10/23/14
20140312465
Die seal layout for vftl dual damascene in a semiconductor device
A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias.
10/23/14
20140312464
Semiconductor device manufacturing method and semiconductor device
In a method of manufacturing a semiconductor device, a molding die for molding a resin case for a semiconductor device is prepared such that the molding die has protrusions to fix each of a plurality of terminals having a leg portion in a predetermined position. Each of the plurality of terminals is held to the corresponding protrusions in the molding die, and resin is injected into the molding die to integrally mold the plurality of terminals and the resin case..
10/23/14
20140312463
Semiconductor structures, devices and engineered substrates including layers of semiconductor material having reduced lattice strain
Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a iii-v type semiconductor material, such as, for example, indium gallium nitride.
10/23/14
20140312462
Semiconductor device
A first impurity diffusion region is provided within a semiconductor substrate, a second impurity diffusion region is provided within the first impurity diffusion region, a third impurity diffusion region is provided within the second impurity diffusion region, a first portion of a fourth impurity diffusion region is provided within the second impurity diffusion region so as to be spaced from the third impurity diffusion region, and a second portion of the fourth impurity diffusion region is provided in a third portion of the first impurity diffusion region on a side of a surface of the semiconductor substrate, a first contact is provided so as to be in contact with the second portion, the first contact and the third portion overlap in plan view, and a first power supply is connected to the third impurity diffusion region.. .
10/23/14
20140312456
Semiconductor devices and methods of fabricating the same
A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines..
10/23/14
20140312455
Patterns of a semiconductor device and method of manufacturing the same
A semiconductor device including a plurality of active patterns, a plurality of first isolation layer patterns and a plurality of second isolation layer patterns may be provided. In particular, the active patterns may be arranged both in a first direction and in a second direction, and may protrude from a substrate and have a length in the first direction.
10/23/14
20140312452
Semiconductor device and termination region structure thereof
A termination region structure of a semiconductor device is provided, which includes: a semiconductor layer; a plurality of trenches, formed on a surface of the semiconductor layer; a connecting trench, formed on the surface of the semiconductor layer, for connecting two adjacent trenches in the plurality of trenches; a first insulating layer, formed on surfaces of the plurality of trenches, the connecting trench, and the semiconductor layer; a conductive material, formed in the plurality of trenches and the connecting trench; a second insulating layer, covering part of a surface of the first insulating layer and part of a surface of the conductive material; and a metal layer, covering part of a surface of the second insulating layer.. .
10/23/14
20140312440
Semiconductor device and manufacturing method thereof
An object of the present invention is to suppress an error in the value detected by a pressure sensor, which may be caused when environmental temperature varies. A semiconductor substrate has a first conductivity type.
10/23/14
20140312431
Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region.
10/23/14
20140312430
Semiconductor devices and methods of fabricating the same
A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate..
10/23/14
20140312429
Power semiconductor device with oscillation prevention
There are disclosed herein various implementations of composite semiconductor devices with active oscillation control. In one exemplary implementation, a normally off composite semiconductor device comprises a normally on iii-nitride power transistor and a low voltage (lv) device cascoded with the normally on iii-nitride power transistor to form the normally off composite semiconductor device.
10/23/14
20140312427
Semiconductor devices having fin shaped channels
Semiconductor devices are provided. The semiconductor devices include a first fin; a first gate electrode intersecting the first fin; a first elevated source and/or drain on respective sides of the first gate electrode on the first fin; and a first field dielectric film adjacent the first fin.
10/23/14
20140312418
Semiconductor device
In a semiconductor power device such as a power mosfet having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.. .
10/23/14
20140312417
Semiconductor device and method of manufacturing a semiconductor device
A semiconductor device formed in a semiconductor substrate includes an isolation trench in the semiconductor substrate to laterally insulate adjacent components of the semiconductor device. A lateral isolation layer is disposed in the isolation trench.
10/23/14
20140312416
Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes, in a cell region thereof: a low resistance semiconductor layer; a drift layer; a base region; a high-concentration semiconductor region; and a gate electrode layer. The semiconductor device includes, in a peripheral region thereof: the low resistance semiconductor layer; the drift layer; which is formed over the low resistance semiconductor layer; a gate lead line; a gate finger; and a gate pad.
10/23/14
20140312415
Semiconductor device and manufacturing method therefor
A semiconductor device includes: a semiconductor substrate including a first surface; a body region positioned in the semiconductor substrate and positioned to be in contact with the first surface; a gate insulating film positioned to be in contact with the body region on the first surface; a gate electrode positioned on the gate insulating film; a first insulator film covering at least a portion of a side surface of the gate electrode; a contact region positioned to be in contact with the first surface at a position different from that of the gate electrode, in a plan view relative to the first surface, in the body region; and a second insulator film including a material different from that of the first insulator film, positioned on the body region, the gate electrode, and the first insulator film, and including a contact hole on the contact region.. .
10/23/14
20140312411
Semiconductor device having super junction metal oxide semiconductor structure and fabrication method for the same
A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.. .
10/23/14
20140312406
Semiconductor device and manufacturing method thereof
To control a grain growth on laminated polysilicon films, a method of manufacturing a semiconductor device is provided. The method includes: forming a first polysilicon film (21) on a substrate (10); forming an interlayer oxide layer (22) on a surface of the first polysilicon film (21); forming a second polysilicon film (23) in contact with the interlayer oxide layer (22) above the first polysilicon film (21); and performing annealing at a temperature higher than a film formation temperature of the first and second polysilicon films in a gas atmosphere containing nitrogen, after formation of the second polysilicon film (23)..
10/23/14
20140312399
Semiconductor device and method of manufacturing the same
A gate insulating film of a conventional semiconductor device is subjected to dielectric breakdown at a low electric field strength and thus its service life is short. This is because since the size of the asperity of at least one of a semiconductor layer-side interface and an electrode-side interface is large and, an electric field applied to the gate insulating film is locally concentrated and has a variation in its strength.
10/23/14
20140312396
Split multi-gate field-effect transistor
A semiconductor device based on split multi-gate field-effect transistor radio frequency devices is provided. The semiconductor device includes a substrate and a gate structure above the substrate and orthogonal to a channel axis.
10/23/14
20140312394
Semiconductor device including a material to absorb thermal energy
A semiconductor device includes a semiconductor chip and a first material including molecules that are configured to absorb thermal energy by reversibly changing a spatial molecular structure of the molecules.. .
10/23/14
20140312389
Reacted conductive gate electrodes and methods of making the same
A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium.
10/23/14
20140312387
Semiconductor device and method for fabricating the same
A semiconductor device includes a base layer of a group iii-v compound, a channel layer disposed on the base layer and including a group iv element, a nitride layer disposed on the channel layer, a gate insulation layer disposed on the nitride layer and a gate electrode disposed on the gate insulation layer. The concentration of nitrogen atoms existing at a first interface between the nitride layer and the gate insulation layer is higher than that existing at a second interface between the nitride layer and the channel layer..
10/23/14
20140312384
Semiconductor device
A semiconductor device includes a first base layer of a first conductivity type formed on a semiconductor layer, a second base layer of a second conductivity type formed on a first surface of the first base layer, an emitter layer formed on the second base layer, a collector layer of the second conductivity type formed above the first base layer, and a barrier layer of the first conductivity type formed between the first base layer and the second base layer. The barrier layer has a depth from the first surface that is shallower than a depth of the second base layer from the first surface and a dopant concentration that is higher than a dopant concentration of the first base layer.
10/23/14
20140312383
Power semiconductor device and method of manufacturing the same
A power semiconductor device may include: abase substrate including a first conductive type drift layer; a second conductive type semiconductor substrate disposed on the other surface of the base substrate; a first conductive type diffusion layer disposed in the base substrate and having an impurity concentration higher than that of the drift layer; a second conductive type well layer disposed inside of one surface of the base substrate; a trench formed from one surface of the base substrate including the well layer so as to penetrate through the diffusion layer in a depth direction; a first insulation film disposed on a surface of the base substrate; and a first electrode disposed in the trench. A peak point of an impurity doping concentration of the diffusion layer in a transverse direction may be positioned in a region contacting a side surface of the trench..
10/23/14
20140312381
Nanoelectronic structure and method of producing such
The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement.
10/23/14
20140312377
Optoelectronic apparatuses with post-molded reflector cups
An optoelectronic apparatus includes one or more packaged optoelectronic semiconductor devices (posds), each including one or more optoelectronic elements encapsulated by a light transmissive molding compound. Each posd includes a top surface formed by a top surface of the light transmissive molding compound that encapsulates the one or more optoelectronic elements of the posd.
10/23/14
20140312362
Compound semiconductor device and method of manufacturing the same
An embodiment of a compound semiconductor device includes: a substrate; a compound semiconductor stacked structure of nitride over the substrate; a passivation film that covers the compound semiconductor stacked structure; a gate electrode, a source electrode, and a drain electrode at a level above the compound semiconductor stacked structure; and an si—c bond containing film that contains an si—c bond and includes a part between the source electrode and the drain electrode. The part contacts at least a part of an upper surface of the compound semiconductor stacked structure or at least a part of an upper surface of the passivation film..
10/23/14
20140312361
Semiconductor element, semiconductor device and method for manufacturing semiconductor element
The semiconductor element has an electrode including: a ni-inclusion metal layer containing nickel formed on a side of at least one surface of the semiconductor-element constituting part; a ni-barrier metal layer formed outwardly on a side of the ni-inclusion metal layer opposite to the side toward the semiconductor-element constituting part; and a surface metal layer outwardly formed on a side of the ni-barrier metal layer opposite to the side toward the semiconductor-element constituting part, to be connected to the metal nanoparticles sintered layer; wherein the ni-barrier metal layer contains a metal for suppressing diffusion of nickel toward the surface metal layer.. .
10/23/14
20140312360
Semiconductor power device having a heat sink
A semiconductor device includes an electrically conducting carrier having a mounting surface. The semiconductor device further includes a metal block having a first surface facing the electrically conducting carrier and a second surface facing away from the electrically conducting carrier.
10/23/14
20140312359
Method for bonding semiconductor substrates
A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate..
10/23/14
20140312358
Normally-off gallium nitride-based semiconductor devices
A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress.
10/23/14
20140312357
Semiconductor device
A semiconductor device of the invention includes an n-gan layer provided on a substrate, a channel layer provided in contact with the upper surface of the n-gan layer, an electron supply layer which is provided on the channel layer, and a gate electrode, a source electrode, and a drain electrode which are provided on the electron supply layer. The gate electrode is in contact with a underlying layer made from a nitride semiconductor.
10/23/14
20140312356
Semiconductor device
A semiconductor device and a method of making the same. The device includes a semiconductor substrate.
10/23/14
20140312352
Semiconductor device, electro-optical device, method of manufacturing semiconductor device, method of manufacturing electro-optical device, and electronic apparatus
A lower insulation layer includes a concave portion that has a back surface on a first base member side, first to third surfaces which are opposed to the back surface, a fourth surface which is arranged between the first surface and the third surface, and a fifth surface which is arranged between the second surface and the third surface. A semiconductor layer is arranged on the first surface and the second surface.
10/23/14
20140312347
Semiconductor device
Adverse effects of variation in threshold voltage are reduced. In a semiconductor device, electric charge is accumulated in a capacitor provided between a gate and a source of a transistor, and then, the electric charge accumulated in the capacitor is discharged; thus, the threshold voltage of the transistor is obtained.
10/23/14
20140312346
Semiconductor device and manufacturing method thereof
An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode.
10/23/14
20140312345
Semiconductor device and method for manufacturing the same
An object is to provide a thin film transistor having favorable electric characteristics and a semiconductor device including the thin film transistor as a switching element. The thin film transistor includes a gate electrode formed over an insulating surface, a gate insulating film over the gate electrode, an oxide semiconductor film which overlaps with the gate electrode over the gate insulating film and which includes a layer where the concentration of one or a plurality of metals contained in the oxide semiconductor is higher than that in other regions, a pair of metal oxide films formed over the oxide semiconductor film and in contact with the layer, and a source electrode and a drain electrode in contact with the metal oxide films.
10/23/14
20140312343
Semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device includes forming a metal oxide semiconductor layer and a first insulating layer on a substrate. A gate is formed on the first insulating layer.
10/23/14
20140312301
Production of a semiconductor device having at least one column-shaped or wall-shaped semiconductor element
Described is a method for producing a semiconductor device (100), in which at least one column-shaped or wall-shaped semiconductor device (10, 20) extending in a main direction (z) is formed on a substrate (30), wherein at least two sections (11, 13, 21, 23) of a first crystal type and one section (12, 22) of a second crystal type therebetween are formed in an active region (40), each section with a respective predetermined height (h1, h2), wherein the first and second crystal types have different lattice constants and each of the sections of the first crystal type has a lattice strain which depends on the lattice constants in the section of the second crystal type. According to the invention, at least a height (h2) of the section (12, 22) of the second crystal type and a lateral thickness (d) of the active region (40) is formed perpendicular to the main direction, in such a manner that the lattice strain in one of the sections (11) of the first crystal type also depends on the lattice constants in the other section (13) of the first crystal type.
10/23/14
20140312294
Semiconductor device and method for fabricating the same, and microprocessor, processor, system, data storage system and memory system including the semiconductor device
A method for fabricating a semiconductor device includes forming a first conductive pattern and a first pad over a substrate; forming a first and a second resistance variable elements over the first conductive pattern and the first pad, respectively; performing impurity doping into the second resistance variable element to produce a conductive contact; and forming a second conductive pattern over the first resistance variable element.. .
10/23/14
20140312265
Titanium-nitride removal
A chemical solution that removes undesired metal hard mask yet remains selective to the device wiring metallurgy and dielectric materials. The present invention decreases aspect ratio by selective removal of the metal hard mask before the metallization of the receiving structures without adverse damage to any existing metal or dielectric materials required to define the semiconductor device, e.g.
10/23/14
20140312102
Semiconductor device manufacturing method and soldering weight
A method for manufacturing a semiconductor device, includes preparing a solder, a soldering article, a base material, a weigh having a foot where a center of gravity of the weight is shifted from a center of the soldering article, a positioning jig having a hole for holding the soldering article in the base material, and a dam member; disposing the dam member on a side having a relatively lower height due to a warp of an edge portion of the base material; placing the positioning jig on a principal surface of the base material; placing the soldering article on the solder in the hole; placing the weight on an upper surface of the soldering article to position the center of gravity on the side having relatively lower height; and raising the temperature of the solder to a temperature equal to or higher than the melting point of the solder.. .


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