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Semiconductor Device patents



      
           
This page is updated frequently with new Semiconductor Device-related patents. Subscribe to the Semiconductor Device RSS feed to automatically get the update: related Semiconductor RSS feeds.

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Date/App# patent app List of recent Semiconductor Device-related patents
04/17/14
20140106652
 Polishing pad and manufacturing method therefor patent thumbnailPolishing pad and manufacturing method therefor
Provided are a polishing pad which remedies the problem of scratches occurring when a conventional hard (dry) polishing pad is used, which is excellent in polishing rate and polishing uniformity, and which can be used for not only primary polishing but also finish polishing, and a manufacturing method therefor. The polishing pad is a polishing pad for polishing a semiconductor device, comprising a polishing layer having a polyurethane-polyurea resin foam containing substantially spherical cells, wherein the polyurethane-polyurea resin foam has a young's modulus e in a range from 450 to 30000 kpa, and a density d in a range from 0.30 to 0.60 g/cm3..
04/17/14
20140106573
 Substrate processing apparatus and method of manufacturing semiconductor device patent thumbnailSubstrate processing apparatus and method of manufacturing semiconductor device
A substrate processing apparatus includes a substrate processing chamber including a plasma generation space where a plasma is generated and a substrate processing space where a substrate is placed during a substrate process; an inductive coupling structure outside the plasma generation space wherein a sum of electrical lengths of a coil of the inductive coupling structure and a waveform adjustment circuit connected to the coil is an integer multiple of a wavelength of an applied power; a substrate mounting table in the substrate processing space and supporting the substrate including grooves having high aspect ratios with a silicon-containing layer disposed thereon; a substrate transfer port at a wall of the substrate processing chamber; a substrate mounting table elevator moving the substrate mounting table upward/downward; an oxygen gas supply system to supply an oxygen-containing gas into the plasma generation space; and an exhaust unit exhausting gas from the substrate processing chamber.. .
04/17/14
20140106569
 Method of fabricating three-dimensional semiconductor device and three-dimensional semiconductor device fabricated using the same patent thumbnailMethod of fabricating three-dimensional semiconductor device and three-dimensional semiconductor device fabricated using the same
According to example embodiments of inventive concepts, a method of fabricating a 3d semiconductor device may include: forming a stack structure including a plurality of horizontal layers sequentially stacked on a substrate including a cell array region and a contact region; forming a first mask pattern covering the cell array region and defining openings extending in one direction over the contact region; performing a first etching process with a first etch-depth using the first mask pattern as an etch mask on the stack structure; forming a second mask pattern covering the cell array region and exposing a part of the contact region; and performing a second etching process with a second etch-depth using the second mask pattern as an etch mask structure on the stack structure. The second etch-depth may be greater than the first etch-depth..
04/17/14
20140106567
 Methods of forming fine patterns in semiconductor devices patent thumbnailMethods of forming fine patterns in semiconductor devices
Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer.
04/17/14
20140106558
 Semiconductor device having metal gate and manufacturing method thereof patent thumbnailSemiconductor device having metal gate and manufacturing method thereof
A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (stis) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.. .
04/17/14
20140106557
 Manufacturing method for semiconductor device having metal gate patent thumbnailManufacturing method for semiconductor device having metal gate
A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.. .
04/17/14
20140106556
 Method for manufacturing a dual work function semiconductor device patent thumbnailMethod for manufacturing a dual work function semiconductor device
A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types.
04/17/14
20140106555
 Method for forming a semiconductor device patent thumbnailMethod for forming a semiconductor device
A method for forming a semiconductor device. One embodiment provides a semiconductor substrate having a trench with a sidewall isolation.
04/17/14
20140106553
 Process for manufacturing a semiconductor device and an intermediate product for the manufacture of a semiconductor device patent thumbnailProcess for manufacturing a semiconductor device and an intermediate product for the manufacture of a semiconductor device
According to one aspect of the inventive concept there is provided a process for manufacturing a semiconductor device, comprising: providing a channel layer (104), providing a mask (106) on the channel layer, epitaxially growing a contact layer (108) in contact with the channel layer, epitaxially growing a support layer (110) on the contact layer, wherein the support layer is arranged to be etched at a higher rate than the contact layer, forming a trench extending through the support layer by removing the mask, and providing a conductor (118) in the trench. There is also provided an intermediate product for the manufacture of a semiconductor device..
04/17/14
20140106548
 Fabrication of iii-nitride semiconductor device and related structures patent thumbnailFabrication of iii-nitride semiconductor device and related structures
A method of fabricating a iii-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.. .
04/17/14
20140106547
Epitaxy of high tensile silicon alloy for tensile strain applications
Embodiments of the present invention generally relate to methods for forming silicon epitaxial layers on semiconductor devices. The methods include forming a silicon epitaxial layer on a substrate at increased pressure and reduced temperature.
04/17/14
20140106546
Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.. .
04/17/14
20140106539
Semiconductor isolation structure and method of manufacture
A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.. .
04/17/14
20140106537
Methods of manufacturing a semiconductor device
Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively..
04/17/14
20140106535
Methods of manufacturing semiconductor devices
A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.. .
04/17/14
20140106531
Field effect transistor device having a hybrid metal gate stack
A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer.
04/17/14
20140106530
Semiconductor device and method of manufacturing the same
In a power feeding region of a memory cell (mc) in which a sidewall-shaped memory gate electrode (mg) of a memory nmis (qnm) is provided by self alignment on a side surface of a selection gate electrode (cg) of a selection nmis (qnc) via an insulating film, a plug (pm) which supplies a voltage to the memory gate electrode (mg) is embedded in a contact hole (cm) formed in an interlayer insulating film (9) formed on the memory gate electrode (mg) and is electrically connected to the memory gate electrode (mg). Since a cap insulating film (cap) is formed on an upper surface of the selection gate electrode (cg), the electrical conduction between the plug (pm) and the selection gate electrode (cg) can be prevented..
04/17/14
20140106527
Method of producing semiconductor device
A method of producing a semiconductor device, includes: forming a semiconductor layer on a substrate; forming an a recess in the semiconductor layer by dry etching with a gas containing fluorine components, the recess having an opening portion on the surface of the semiconductor layer; forming a fluorine-containing region by heating the semiconductor layer and thus diffusing, into the semiconductor layer, the fluorine components attached to side surfaces and a bottom surface of the recess; forming an insulating film on an inner surface of the recess and on the semiconductor layer; and forming an electrode on the insulating film in a region in which the recess is formed.. .
04/17/14
20140106523
Vertical super-thin body semiconductor on dielectric wall devices and methods of their fabrication
The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (vstb) formed on dielectric body wall (such as sti-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to sti side surface. The body is made self-aligned to sti hard mask edge allowing tight control of body thickness.
04/17/14
20140106521
Method for manufacturing semiconductor device
Provided is a method for manufacturing a semiconductor device which includes, on a wafer which has a notch, a plurality of transistors parallel with and perpendicular to a notch direction extending between the center of the wafer and the notch, the method including: preparing the wafer having the front surface which has off angle of at least 2 degrees and at most 2.8 degrees from plane in a direction in which twist angle relative to the notch direction is at least 12.5 degrees and at most 32.5 degrees; and doping impurities into the front surface of the wafer in a direction perpendicular to the front surface.. .
04/17/14
20140106520
Semiconductor device manufacturing method
A semiconductor device manufacturing method with high productivity is disclosed with improved trade-off relationship between auto-doping and breakdown in alignment mark form. First to sixth epitaxial layers are grown sequentially on si {100} main surface of an arsenic doped substrate using multilayer epitaxial technology.
04/17/14
20140106517
Semiconductor devices with minimized current flow differences and methods of same
A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device..
04/17/14
20140106516
Self-doped ohmic contacts for compound semiconductor devices
A compound semiconductor device is manufactured by forming an iii-nitride compound semiconductor device structure on a silicon-containing semiconductor substrate, the iii-nitride compound semiconductor device structure including a gan alloy on gan and a channel region arising near an interface between the gan alloy and the gan. One or more silicon-containing insulating layers are formed on a surface of the iii-nitride compound semiconductor device structure adjacent the gan alloy, and a contact opening is formed which extends through the one or more silicon-containing insulating layers to at least the gan alloy.
04/17/14
20140106514
Method for manufacturing semiconductor device and method for growing graphene
A catalyst film (2) is formed over a substrate (1). A graphene (3) is grown on the catalyst film (2).
04/17/14
20140106509
Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion..
04/17/14
20140106506
Semiconductor device and manufacturing method thereof
A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer..
04/17/14
20140106505
Method for manufacturing semiconductor device
Disclosed is a method to manufacture a thin film transistor having an oxide semiconductor as a channel formation region. The method includes; forming an oxide semiconductor layer over a gate insulating layer; forming a source and drain electrode layers over and in contact with the oxide semiconductor layer so that at least portion of the oxide semiconductor layer is exposed; and forming an oxide insulating film over and in contact with the oxide semiconductor layer.
04/17/14
20140106504
Method for manufacturing semiconductor device
To provide a semiconductor device in which an increase in oxygen vacancies is suppressed. To provide a semiconductor device with favorable electrical characteristics.
04/17/14
20140106503
Method for manufacturing semiconductor device and manufacturing apparatus of semiconductor device
A semiconductor device including an oxide semiconductor and an organic resin film is manufactured in the following manner. Heat treatment is performed on a first substrate provided with an organic resin film over a transistor including an oxide semiconductor in a reduced pressure atmosphere; handling of the first substrate is performed in an atmosphere containing moisture as little as possible in an inert gas (e.g., nitrogen) atmosphere with a dew point of lower than or equal to −60° c., preferably with a dew point of lower than or equal to −75° c.
04/17/14
20140106502
Semiconductor device and method for manufacturing the same
Stable electrical characteristics and high reliability are provided for a miniaturized semiconductor device including an oxide semiconductor, and the semiconductor device is manufactured. The semiconductor device includes a base insulating layer; an oxide stack which is over the base insulating layer and includes an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide stack; a gate insulating layer over the oxide stack, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer; and an interlayer insulating layer over the gate electrode layer.
04/17/14
20140106479
End-cut first approach for critical dimension control
A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer..
04/17/14
20140104970
Semiconductor device outputting read data in synchronization with clock signal
A method for outputting data in a semiconductor device includes receiving an external clock signal, synchronizing, in a delay locked loop of the semiconductor device, a first internal clock signal to the external clock signal during a read period, synchronizing, in the delay locked loop, a second internal clock signal to the external clock signal during an active period, the second internal clock signal having a period longer than the first internal clock signal, and outputting data synchronized with the first internal clock signal during the read period.. .
04/17/14
20140104920
Semiconductor device
According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit.
04/17/14
20140104919
Semiconductor device having hierarchically structured bit lines and system including the same
A method for sensing data in an open bit line dynamic random access memory includes activating a word line in a first memory block of a first memory mat to transfer charge from memory cells to first sub-bit lines, the first memory mat being between a second memory mat and a third memory mat, activating first hierarchy switches corresponding to the first memory block to transfer charge from first sub-bit lines to global bit lines of the first memory mat, and activating second hierarchy switches corresponding to a second memory block in a second memory mat, to connect sub-bit lines to global bit lines of the second memory mat, the first memory block and the second memory block being equidistant from a first sense amplifier array located between the first memory mat and the second memory mat.. .
04/17/14
20140104916
Semiconductor device having memory cell array divided into plural memory mats
A semiconductor device includes a plurality of memory mats arranged in an x direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the x direction.
04/17/14
20140104888
Semiconductor device with shared region
A semiconductor device having a jfet and diode, includes a substrate, a second well region, and a second doped region that are of a first conductivity type. The jfet also includes a first well region, a first doped region, and a shared region that are of the second conductivity type.
04/17/14
20140104802
Semiconductor device and circuit board
A semiconductor device includes a semiconductor chip, a plurality of external terminals, and a board. The board includes a first main surface in which a plurality of first electrodes electrically connected to the semiconductor chip are formed, a second main surface in which a plurality of second electrodes electrically connected to the plurality of external terminals are formed, and a plurality of interconnect layers, provided between the first main surface and the second main surface, for forming a plurality of signal paths that electrically connect the first electrode and the second electrode corresponding thereto.
04/17/14
20140104790
Power modules and power module arrays having a modular design
Power modules and power module arrays are disclosed. In one embodiment, a power module includes a module support, a high temperature module, and a module cap.
04/17/14
20140104263
Semiconductor devices having image sensor and memory device operation modes
A semiconductor device may include a plurality of banks; and a control unit configured to receive a command from an external device and independently control the plurality of banks according to the received command. Each bank comprises a pixel array including a plurality of pixels; a row decoder configured to activate word lines connected to the plurality of pixels under control of the control unit; a column decoder configured to activate bit lines connected to the plurality of pixels under control of the control unit; a sense amplifier and write driver configured to control and detect respective voltages of the activated bit lines to provide respective amplified voltages; and an input/output buffer configured to output data states of the pixels based on the respective amplified voltages.
04/17/14
20140103981
Counting circuit of semiconductor device and duty correction circuit of semiconductor device using the same
A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.. .
04/17/14
20140103968
Field plate assisted resistance reduction in a semiconductor device
Embodiments of a semiconductor device, a circuit including a semiconductor device and a driver circuit, and a method for operating a semiconductor device are described. In one embodiment, a semiconductor device includes a substrate, a source region, a drain region, and a drain extension region formed in the substrate, and an insulation layer adjacent to the drain extension region.
04/17/14
20140103902
Semiconductor device having sensing functionality
A semiconductor package includes a power semiconductor chip having a control electrode, a first load electrode and a second load electrode. The package also includes a first terminal conductor electrically coupled to the control electrode, a second terminal conductor electrically coupled to the first load electrode and a third terminal conductor electrically coupled to the second load electrode.
04/17/14
20140103547
Alignment key of semiconductor device and method of fabricating the same
An alignment key of a semiconductor device includes: a material layer formed at a scribe region of a semiconductor substrate, a first dummy hole and a second dummy hole passing through the material layers, a first channel insulation layer formed inside the first dummy hole, a second channel insulation layer formed inside the second dummy hole, a first capping layer formed on a side wall of an upper portion of the first dummy hole and an upper portion of the first channel insulation layer, and a second capping layer formed on a side wall of an upper portion of the second dummy hole and an upper portion of the channel insulation layer, having a height of a lower surface portion greater than that of a lower surface portion of the first capping layer.. .
04/17/14
20140103544
Semiconductor device
A semiconductor device includes an extended semiconductor chip including a first semiconductor chip and an extension outwardly extending from a side surface of the first semiconductor chip; and a second semiconductor chip connected to the extended semiconductor chip through a plurality of bumps and electrically connected to the first semiconductor chip. The first semiconductor chip is smaller than the second semiconductor chip.
04/17/14
20140103543
Semiconductor device
A semiconductor device includes: a first semiconductor chip; a second semiconductor chip placed such that a front face of the second semiconductor chip faces a front face of the first semiconductor chip, and being smaller in size than the first semiconductor chip; an expansion portion extending outward from at least one side face of the second semiconductor chip; a wiring board placed such that a front face of the wiring board faces the front face of the first semiconductor chip and a back face of the second semiconductor chip; and a first interconnect formed on the back face of the second semiconductor chip and a back face of the expansion portion, and being in connection to the wiring board.. .
04/17/14
20140103542
Semiconductor package with bonding wires of reduced loop inductance
A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires.
04/17/14
20140103541
Semiconductor device, circuit substrate, and electronic device
A semiconductor device has a through electrode formed in a through hole which penetrates a si substrate from one surface to the other surface of the si substrate, wherein a rectangular electrode pad is provided on the other surface with an insulation film laid between the electrode pad and the other surface, an opening of the through hole on the one surface side is circular, an opening of the through hole on the other surface side is rectangular, and the area of the opening on the other surface side is made smaller than the area of the opening on the one surface side.. .
04/17/14
20140103539
Semiconductor device and method of fabricating the same
A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.. .
04/17/14
20140103537
Nitride semiconductor device
A nitride semiconductor device includes first electrode interconnect layers and second electrode interconnect layers formed over a nitride semiconductor layer, a first insulating film formed on the first and second electrode interconnect layers and including first openings, first interconnect layers and second interconnect layers formed on the first insulating film and respectively connected to the first electrode interconnect layers and the second electrode interconnection layers through the first openings, a second insulating film formed on the first and second interconnect layers and including second openings, and a first pad layer and a second pad layer formed on the second insulating film and respectively connected to the first interconnect layers and the second interconnect layers through the second openings.. .
04/17/14
20140103536
Semiconductor device
A semiconductor device includes: on an upper surface of a second semiconductor chip on a circuit board, a ring dam section formed at an outer circumference of a mounting region above which a first semiconductor chip is mounted; and an interconnect extending from the dam section to a center section of the first semiconductor chip or the second semiconductor chip in a region in which the first semiconductor chip faces the second semiconductor chip. The interconnect is electrically connected to a connection terminal on a circuit formation surface of the first or second semiconductor chip at the center section of the first or second semiconductor chip.
04/17/14
20140103529
Semiconductor device manufacturing method, semiconductor device, semiconductor device manufacturing apparatus and storage medium
In order to obtain a semiconductor device having an embedded electrode with low cost and high reliability, a semiconductor device manufacturing method includes forming a first film made of a metal oxide within an opening which is formed in an insulating film formed on a surface of a substrate; performing a hydrogen radical treatment by irradiating atomic hydrogen to the first film; forming a second film made of a metal within the opening after the performing of the hydrogen radical treatment; and forming an electrode made of a metal within the opening after the forming of the second film.. .
04/17/14
20140103528
Semiconductor device
A semiconductor device, that is approximately identical in package size to a semiconductor chip, such as a w-csp, is devised to secure a wider area for sealing such as laser marking. A semiconductor substrate has a plurality of via electrodes extending from the bottom of the semiconductor substrate to top electrodes, a bottom wire net formed at the bottom of the semiconductor substrate such that the bottom wire net is connected to the via electrodes, and an insulative film covering the bottom wire net.
04/17/14
20140103527
Semiconductor device and method of forming a pop device with embedded vertical interconnect units
A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate.
04/17/14
20140103526
Self-aligned protection layer for copper post structure
A semiconductor device includes a copper-containing post overlying and electrically connected to a bond pad region. The semiconductor device further includes a protection layer on a surface of the copper-containing post, where the protection layer includes manganese..
04/17/14
20140103525
Semiconductor device and a method of manufacturing the same
A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film.
04/17/14
20140103522
Semiconductor substrate, semiconductor device, and method of manfacturing semiconductor substrate
A semiconductor substrate having a base material and a connection portion provided on at least one surface of the base material. The connection portion includes: a non-conductive wall portion so as to surround a concave portion formed on the base material; an electrode portion disposed on a bottom surface of a concave portion; and a metal portion disposed in contact with the electrode portion..
04/17/14
20140103520
Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs
Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming one or more openings in a front side of the semiconductor device and forming sacrificial plugs in the openings that partially fill the openings.
04/17/14
20140103516
Semiconductor device and method of manufacturing the same
Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device includes an interposer and a first semiconductor package comprising a first substrate, and a first semiconductor chip mounted on the first substrate.
04/17/14
20140103515
Semiconductor device
In a qfp with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a bcb film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur..
04/17/14
20140103513
Semiconductor device with lead terminals having portions thereof extending obliquely
A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion.
04/17/14
20140103511
Semiconductor device, semiconductor device storage method, semiconductor device manufacturing method, and semiconductor manufacturing apparatus
A semiconductor package has a semiconductor chip, a lead frame in which a semiconductor chip is mounted on a die pad, and a resin sealing the semiconductor chip and the die pad from an upper surface and a lower surface, the resin has a concave portion disposed at the surface and a concave portion situated inside the concave portion in a plan view.. .
04/17/14
20140103510
Semiconductor device and method of manufacturing the same
A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is electrically connected. The metal clip includes a chip-connecting portion electrically connected to the source electrode pad via a conductive bonding material, a lead-connecting portion electrically connected to the lead via a conductive bonding material, and an intermediate portion positioned between the chip-connecting portion and the lead-connecting portion.
04/17/14
20140103509
Semiconductor device and method of forming conductive ink layer as interconnect structure between semiconductor packages
A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An opening is formed in a first surface of the encapsulant by etching or lda.
04/17/14
20140103504
Semiconductor device
A first chip including electrodes is mounted above an expanded semiconductor chip formed by providing an expanded portion at an outer edge of a second chip including chips. The electrodes of the first chip are electrically connected to the electrodes of the second chip by conductive members.
04/17/14
20140103503
Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability
A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer.
04/17/14
20140103502
Semiconductor device
A semiconductor device includes: a first semiconductor chip held on a substrate and including an expanded portion expanding outward from a side surface of a body of the first semiconductor chip; a first wire connecting the expanded portion of the first semiconductor chip to the substrate; and a second wire connecting the body of the first semiconductor chip to the substrate.. .
04/17/14
20140103494
Nearly buffer zone free layout methodology
The present disclosure relates to a layout arrangement and method to minimize the area overhead associated with a transition between a semiconductor device array and background features. A nearly buffer zone free layout methodology is proposed, wherein an array of square unit cells with a first pattern density value is surrounded by background features with a second pattern density value.
04/17/14
20140103491
Semiconductor devices
The present inventive concept provides semiconductor devices that may include a capacitor including a lower electrode, a dielectric layer, and an upper electrode which are sequentially stacked. An electrode-protecting layer may be provided on the capacitor.
04/17/14
20140103487
Semiconductor device
A semiconductor device, includes a first substrate having a main surface and a rear surface opposing to the main surface, a first circuit including a plurality of transistors formed over the main surface, a first insulating film formed over the main surface to cover the first circuit, a first inductor formed in the first insulating film over the main surface, the first inductor being electrically connected to the first circuit; and a bonding pad formed over the main surface, the bonding pad being located at a first area, the first inductor being located at a second area, the first area being different from the second area in a plan view, and a second substrate having a main surface, a rear surface opposing to the main surface and a second inductor formed over the main surface.. .
04/17/14
20140103483
Semiconductor device
A semiconductor device comprises a semiconductor substrate; an element-forming region that includes semiconductor elements formed on the semiconductor substrate; a buried electrode plug formed so as to penetrate through the semiconductor substrate; and a trench-type electrode that is buried in a trench within the semiconductor substrate positioned between the element-forming region and the buried electrode plug.. .
04/17/14
20140103482
Semiconductor device having vertical channels and method of manufacturing the same
A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions.
04/17/14
20140103481
Semiconductor substrate, semiconductor device, solid-state imaging device, and method of manufacturing semiconductor sustrate
A semiconductor substrate according to the present invention includes: a substrate; an electrode array which is provided on the surface on one side in a thickness direction of the substrate and in which a plurality of electrodes is two-dimensionally arranged in a plan view; and a resin layer which is provided on the surface on one side and seals peripheries of the plurality of electrodes. The plurality of electrodes protrudes by greater than or equal to 5% of its own height on the resin layer and is capable of being accommodated in the resin layer by being compressed in the thickness direction..
04/17/14
20140103475
Semiconductor device and manufacturing method of the semiconductor device
A semiconductor device includes a substrate, a multilayer wiring layer formed over the substrate, an mtj (magnetic tunnel junction) element formed in an insulating layer located lower than an uppermost wiring layer in the multilayer wiring layer, a wiring formed in a wiring layer immediately above the mtj element and coupled to the mtj element, and a shield conductor region provided in the wiring or a wiring layer immediately above the wiring, and covering an entirety of the mtj element in a plan view.. .
04/17/14
20140103459
Semiconductor device and method for fabricating the same
A semiconductor device includes: a channel layer made of gan; a barrier layer formed on the channel layer, the bather layer being made of algan and having a larger band gap than the channel layer; a p-type gan layer selectively formed on the barrier layer; a gate electrode made of ito on the p-type gan layer; and a source electrode and a drain electrode on regions of the barrier layer laterally outward of the gate electrode. The width of the gate electrode in the gate length direction is smaller than or equal to the width of the p-type gan layer in the gate length direction, and the difference between the width of the gate electrode in the gate length direction and the width of the p-type gan layer in the gate length direction is less than or equal to 0.2 μm..
04/17/14
20140103458
Gate electrode having a capping layer
A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed..
04/17/14
20140103457
Field effect transistor device having a hybrid metal gate stack
A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer.
04/17/14
20140103449
Oxygen free rta on gate first hkmg stacks
A method of fabricating a semiconductor device with improved vt and the resulting device are disclosed. Embodiments include forming an hkmg stack on a substrate; implanting dopants in active regions of the substrate; and performing an rta in an environment of nitrogen and no more than 30% oxygen..
04/17/14
20140103446
Semiconductor device
A semiconductor device includes first and second well regions having a first conductivity type, and a third well region between the first and second well regions having a second conductivity type different from the first conductivity type. A first active region is in the first well region.
04/17/14
20140103444
Semiconductor device with a dislocation structure and method of forming the same
A semiconductor device with bi-layer dislocation and method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility.
04/17/14
20140103443
Semiconductor device having metal gate and manufacturing method thereof
A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench.
04/17/14
20140103442
Semiconductor device, method of forming semiconductor device, and data processing system
A semiconductor device includes a semiconductor substrate including a fin. The fin includes first and second fin portions.
04/17/14
20140103441
Semiconductor device and method of fabricating the same
A semiconductor device includes an interlayer insulating film formed on a substrate, the insulating layer including a trench. A gate insulating layer is formed on a bottom surface of the trench and a reaction prevention layer is formed on the gate insulating layer on the bottom surface of the trench.
04/17/14
20140103438
Multi-gate semiconductor devices and methods of forming the same
A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type.
04/17/14
20140103433
High-voltage metal-dielectric-semiconductor device and method of the same
A high-voltage metal-dielectric-semiconductor transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate surrounding an active area; a gate overlying the active area; a drain doping region of a first conductivity type in the active area; a source doping region of the first conductivity type in a first well of a second conductivity type in the active area; and a source lightly doped region of the first conductivity type between the gate and the source doping region; wherein no isolation is formed between the gate and the drain doping region.. .
04/17/14
20140103432
Semiconductor device
According to one embodiment, a semiconductor device includes a base region of a second conductivity type, a drift region of a first conductivity type, an insulating layer, a drain region of the first conductivity type, a gate oxide film, a gate electrode, a first main electrode, and a second main electrode. The base region includes a source region of the first conductivity type.
04/17/14
20140103427
Semiconductor transistor device and method for manufacturing same
According to one embodiment, a semiconductor device includes a drift layer. The device includes a base layer.
04/17/14
20140103425
Semiconductor device
A semiconductor device includes a first semiconductor layer of a first conductivity type. A second semiconductor layer of a second conductivity type is on the first semiconductor layer.
04/17/14
20140103423
Method of producing precision vertical and horizontal layers in a vertical semiconductor structure
The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate.
04/17/14
20140103421
Semiconductor devices and method of making the same
In one embodiment, the semiconductor devices relate to using one or more super junction trenches for termination.. .
04/17/14
20140103420
Advanced faraday shield for a semiconductor device
One illustrative device disclosed herein includes a transistor comprising a gate electrode and a drain region formed in a semiconducting substrate, an isolation structure formed in the substrate, wherein the isolation structure is laterally positioned between the gate electrode and the drain region, and a faraday shield that is positioned laterally between the gate electrode and the drain region and above the isolation structure, wherein the faraday shield has a long axis that is oriented substantially vertically relative to an upper surface of the substrate.. .
04/17/14
20140103417
Semiconductor device and method of manufacturing the same
A semiconductor device includes a pipe gate, word lines stacked on the pipe gate, first channel layers configured to pass through the word lines, and a second channel layer formed in the pipe gate to connect the first channel layers and having a higher impurity concentration than the first channel layers.. .
04/17/14
20140103416
Semiconductor device having esd protection structure and associated method for manufacturing
A semiconductor device having an esd protection structure and a method for forming the semiconductor device. The semiconductor device further includes a semiconductor transistor formed in an active cell area of a substrate.
04/17/14
20140103415
Semiconductor device and method of preventing latch-up in a charge pump circuit
A charge pump circuit includes a substrate and first well region formed in the substrate. A first transistor includes first and second conduction regions disposed in the first well region.
04/17/14
20140103414
Vertical super-thin body semiconductor on dielectric wall devices and methods of their fabrication
The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (vstb) formed on dielectric body wall (such as sti-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to sti side surface. The body is made self-aligned to sti hard mask edge allowing tight control of body thickness.
04/17/14
20140103409
Soi substrate and manufacturing method thereof
An object is to provide an soi substrate provided with a semiconductor layer which can be used practically even when a glass substrate is used as a base substrate. Another object is to provide a semiconductor device having high reliability using such an soi substrate.
04/17/14
20140103407
Method for protecting a gate structure during contact formation
Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region and the drain region; a dielectric layer disposed over the substrate; and a gate contact, a source contact, and a drain contact.
04/17/14
20140103405
Method for fabricating semiconductor device
A method is provided for fabricating a semiconductor device that includes: forming a gate pattern on a substrate; forming a source/drain in the vicinity of the gate pattern; forming an etch stop film, which covers the gate pattern and the source/drain, on the substrate; forming an interlayer insulating film on the etch stop film; forming a shared contact hole that exposes the gate pattern and the source/drain by etching the interlayer insulating film, wherein a polymer is generated in the shared contact hole a process of etching the interlayer insulating film; removing the polymer by performing etching using hydrogen gas, nitrogen gas or a mixture of hydrogen and nitrogen before etching the etch stop film; and etching the etch stop film.. .
04/17/14
20140103403
Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device is provided. The method includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern along side and bottom surfaces of the trench, forming a second metal gate film on the first metal gate film pattern and the insulation film, and forming a second metal gate film pattern positioned on the first metal gate film pattern by removing the second metal gate film to expose at least a portion of the insulation film and forming a blocking layer pattern on the second metal gate film pattern by oxidizing an exposed surface of the second metal gate film pattern..
04/17/14
20140103398
Rf power hemt grown on a silicon or sic substrate with a front-side plug connection
A compound semiconductor device includes a plurality of high-resistance crystalline silicon epitaxial layers and a plurality of activated dopant regions disposed in a same region of at least some of the epitaxial layers so that the activated dopant regions are aligned in a vertical direction perpendicular to a main surface of the epitaxial layers. The compound semiconductor device further includes an iii-nitride compound semiconductor device structure disposed on the main surface of the epitaxial layers.
04/17/14
20140103394
Reduction of edge effects from aspect ratio trapping
A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an art technique.
04/17/14
20140103393
Surface mountable power components
According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically coupled to the component substrate. The power component also includes at least one first peripheral contact and at least one second peripheral contact situated on the component substrate.
04/17/14
20140103392
Semiconductor device
A semiconductor device comprises a vertical mos transistor including a semiconductor substrate having a silicon pillar, a gate electrode formed along a sidewall of the silicon pillar, a gate insulating film formed between the gate electrode and the silicon pillar, an upper diffusion layer formed on the top of the silicon pillar, and a lower diffusion layer formed lower than the upper diffusion layer in the semiconductor substrate; and a pad electrically connected to the lower diffusion layer. Breakdown occurs between the lower diffusion layer and the semiconductor substrate when a surge voltage is applied..
04/17/14
20140103365
Semiconductor device and method for manufacturing same
A semiconductor device includes: a substrate made of silicon carbide; an insulating film formed on a surface of the substrate; a buffer film containing no al; and an electrode containing al. The substrate has an electrically conductive region.
04/17/14
20140103360
Semiconductor device
A semiconductor device having: a substrate; a nitride semiconductor layer including a first semiconductor layer made of gan or inxga1-xn (0<x≦1) and formed on the substrate and a second semiconductor layer containing al and formed on the first semiconductor layer; and a protective film formed on the set of nitride semiconductor layers. The nitride semiconductor layer has an active section and an inactive section surrounding the active section, and a portion of the second semiconductor layer has been removed from the inactive section..
04/17/14
20140103353
Group iii nitride composite substrate and method for manufacturing the same, laminated group iii nitride composite substrate, and group iii nitride semiconductor device and method for manufacturing the same
A group iii nitride composite substrate includes a support substrate and a group iii nitride film. A ratio st/mt of a standard deviation st of the thickness of the group iii nitride film, to a mean value mt of the thickness thereof is 0.001 or more and 0.2 or less, and a ratio so/mo of a standard deviation so of an absolute value of an off angle between a main surface of the group iii nitride film and a plane of a predetermined plane orientation, to a mean value mo of the absolute value of the off angle thereof is 0.005 or more and 0.6 or less.
04/17/14
20140103346
Semiconductor device
A semiconductor device includes a transistor which includes a gate electrode, a gate insulating film in contact with the gate electrode, and a stacked-layer oxide film facing the gate electrode with the gate insulating film provided therebetween. In the semiconductor device, the stacked-layer oxide film includes at least a plurality of oxide films, at least one of the plurality of oxide films includes a channel formation region, a channel length of the transistor is greater than or equal to 5 nm and less than 60 nm, and a thickness of the gate insulating film is larger than a thickness of the oxide film including the channel formation region..
04/17/14
20140103340
Semiconductor device
A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided.
04/17/14
20140103339
Semiconductor device and method for manufacturing the same
A semiconductor device formed using an oxide semiconductor layer and having small electrical characteristic variation is provided. A highly reliable semiconductor device including an oxide semiconductor layer and exhibiting stable electric characteristics is provided.
04/17/14
20140103338
Semiconductor device
A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided.
04/17/14
20140103337
Semiconductor device
To provide a highly reliable semiconductor device including an oxide semiconductor by suppression of change in its electrical characteristics. Oxygen is supplied from a base insulating layer provided below an oxide semiconductor layer and a gate insulating layer provided over the oxide semiconductor layer to a region where a channel is formed, whereby oxygen vacancies which might be generated in the channel are filled.
04/17/14
20140103335
Semiconductor device
Stable electrical characteristics of a transistor including an oxide semiconductor layer are achieved. A highly reliable semiconductor device including the transistor is provided.
04/17/14
20140103251
Compositions for use in semiconductor devices
An improved composition and method for cleaning a surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of the wafer.
04/17/14
20140103210
Multi-stack film bolometer
A semiconductor device includes a substrate, suspension structures extending from the upper surface of the substrate, and an absorber stack attached to the substrate by the suspension structures. The suspension structures suspend the absorber stack over the substrate such that a gap is defined between the absorber stack and the substrate.
04/17/14
20140103097
Circuit board, semiconductor device, and method of manufacturing semiconductor device
There is provided a circuit board to which a solder ball composed of a lead (pb)-free solder is to be connected, a semiconductor device including an electrode and a solder ball composed of a lead (pb)-free solder disposed on the electrode, and a method of manufacturing the semiconductor device, in which mounting reliability can be improved by enhancing the bonding strength (adhesion strength) between the solder ball composed of a lead (pb)-free solder and the electrode.. .


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