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Semiconductor Device patents



      

This page is updated frequently with new Semiconductor Device-related patent applications.




Date/App# patent app List of recent Semiconductor Device-related patents
07/14/16
20160204792 
 Semiconductor device and semiconductor device operating method patent thumbnailSemiconductor device and semiconductor device operating method
A semiconductor device includes an analog-digital converter circuit. The analog-digital converter circuit includes a delay cell array that includes n-number (n is a natural number of 2 or more) of serially-coupled delay cells, receives a reference clock signal, and utilizes an analog input signal as the power supply voltage for delay cells in each stage, and an encoder that encodes the output signal of the delay cells in each stage of the delay cell array.
Renesas Electronics Corporation


07/14/16
20160204741 
 Semiconductor device patent thumbnailSemiconductor device
Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device..
Renesas Electronics Corporation


07/14/16
20160204694 
 Power supply device patent thumbnailPower supply device
According to one embodiment of the present invention, when a power supply device having first and second amplification units which share an energy storage element is used, it is possible to reduce voltage stress of a semiconductor device and to consistently maintain output voltage outputted to the first and second amplification units while individually adjusting the amplification rates of the first and second amplification units.. .
Lg Innotek Co., Ltd.


07/14/16
20160204653 
 Semiconductor device being capable of improving the breakdown characteristics patent thumbnailSemiconductor device being capable of improving the breakdown characteristics
A semiconductor device, wherein the semiconductor device includes a high-voltage supply circuit suitable for supplying a high voltage; a discharge circuit suitable for discharging the high voltage; and an auxiliary-voltage supply circuit suitable for supplying a first auxiliary voltage, which varies according to an operation state of the high-voltage supply circuit, to a reference node of the discharge circuit.. .
Sk Hynix Inc.


07/14/16
20160204344 
 Structure and formation  memory device patent thumbnailStructure and formation memory device
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first electrode over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


07/14/16
20160204281 
 Energy storage device with large charge separation patent thumbnailEnergy storage device with large charge separation
High density energy storage in semiconductor devices is provided. There are two main aspects of the present approach.
The Board Of Trustees Of The Leland Stanford Junior University


07/14/16
20160204280 
 Lateral charge storage region formation for semiconductor wordline patent thumbnailLateral charge storage region formation for semiconductor wordline
Devices and methods for forming charge storage regions are disclosed. In one embodiment, a semiconductor device comprises a semiconductor layer having a trench, charge storage layers formed at both side surfaces of the trench, a wordline buried in the trench in contact with the charge storage layers, and source-drain regions formed in the semiconductor layer at both sides of the trench..
Cypress Semiconductor Corporation


07/14/16
20160204277 
 Semiconductor device including nanowire transistor patent thumbnailSemiconductor device including nanowire transistor
A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire.
Samsung Electronics Co., Ltd.


07/14/16
20160204275 
 Semiconductor device patent thumbnailSemiconductor device
It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ito film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer.
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204271 
 Semiconductor device and  manufacturing the same patent thumbnailSemiconductor device and manufacturing the same
To manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor. An oxide semiconductor film is deposited by a sputtering method with the use of a polycrystalline sputtering target.
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204270 

Semiconductor device and manufacturing method thereof


A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased..
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204269 

Semiconductor device and manufacturing the same


It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer.
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204268 

Method for manufacturing semiconductor device


A semiconductor device which is miniaturized while favorable characteristics thereof are maintained is provided. In addition, the miniaturized semiconductor device is provided with a high yield.
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204264 

Semiconductor devices having gate structures with skirt regions


Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin..

07/14/16
20160204261 

Channel cladding last process flow for forming a channel region on a finfet device having a reduced size fin in the channel region


One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming a sacrificial gate structure around a portion of an initial fin, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure and removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove portions of the initial fin so as to thereby define a reduced size fin and recesses under the sidewall spacers, forming at least one replacement epi semiconductor cladding material around the reduced size fin in the replacement gate cavity and in the recesses under the sidewall spacers, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.. .
Globalfoundries Inc.


07/14/16
20160204260 

Structure and formation finfet device


Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a fin channel structure over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


07/14/16
20160204258 

Semiconductor device and manufacturing the same


To improve performance of a semiconductor device. Over a semiconductor substrate, a gate electrode is formed via a first insulating film for a gate insulating film, and a second insulating film extends from over a side wall of the gate electrode to over the semiconductor substrate.
Renesas Electronics Corporation


07/14/16
20160204257 

Self-aligned contact process enabled by low temperature


Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer.
International Business Machines Corporation


07/14/16
20160204254 

Semiconductor device


A semiconductor device includes a hetero junction structure including an electron transport layer of gan and an electron supply layer of inx1aly1ga1-x1-y1n (0≦x1≦1, 0≦y1≦1, 0≦1−x1−y1<1), source and drain electrodes provided above an surface of the electron supply layer, a p-type layer of inx2aly2ga1-x2-y2n (0≦x2≦1, 0≦y2≦1, 0≦1−x2−y2≦1) provided above the surface of the electron supply layer and between the source electrode and the drain electrode, a gate electrode provided to be electrical contact with the p-type layer, and an insulation layer covering at least one of the surface of the electron supply layer exposed between the source electrode and the p-type layer and the surface of the electron supply layer exposed between the drain electrode and the p-type layer, wherein positive charges are fixed in at least a part of the insulation layer.. .
Toyota Jidosha Kabushiki Kaisha


07/14/16
20160204253 

Iii-v mosfet with strained channel and semi-insulating bottom barrier


Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a semiconductor substrate. A channel is formed on the bottom barrier.
International Business Machines Corporation


07/14/16
20160204252 

Semiconductor device


A plurality of unit misfet elements connected in parallel with each other to make up a power misfet are formed in an ldmosfet forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power misfet is formed in a driver circuit region on the main surface of the semiconductor substrate.
Renesas Electronics Corporation


07/14/16
20160204251 

Pillar-shaped semiconductor device and production method therefor


A sio2 layer is formed at a middle of a si pillar. An opening is formed in a gate insulating layer and a gate conductor layer in a peripheral portion that includes a side surface of the sio2 layer.
Unisantis Electronics Singapore Pte. Ltd.


07/14/16
20160204250 

New layout for ldmos


A layout structure, a semiconductor device and an electronic apparatus are provided. The layout structure includes at least one ldmos.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204249 

Mosfet having dual-gate cells with an integrated channel diode


A semiconductor device includes mosfet cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region.
Texas Instruments Incorporated


07/14/16
20160204248 

Semiconductor device with vertical gate and manufacturing the same


A gate electrode is formed in a trench reaching a drain region so as to leave a concave portion on the top of the trench. A first insulating film is formed, which fills the concave portion and of which the thickness increases as the distance from an end of the trench increases on the substrate surface on both sides of the trench.
Panasonic Intellectual Property Management Co., Ltd.


07/14/16
20160204246 

Ge and iii-v channel semiconductor devices having maximized compliance and free surface relaxation


Ge and iii-v channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such ge and iii-v channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate.
Intel Corporation


07/14/16
20160204244 

Semiconductor device and making same


A semiconductor device and method of forming the same is described. In an example, a polysilicon layer is deposited on a substrate having at least one polysilicon ring.
Hewlett-packard Develoment Company, L.p.


07/14/16
20160204243 

Semiconductor device and a manufacturing a semiconductor device


The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region.
Renesas Electronics Corporation


07/14/16
20160204242 

Compound semiconductor device and manufacturing the same


An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. A recess positioning between the gate electrode and the drain electrode in a plan view is formed at a surface of the compound semiconductor stacked structure..
Fujitsu Limited


07/14/16
20160204241 

Semiconductor device and manufacturing method thereof


A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate, a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer, a gate trench formed in the second semiconductor layer or in the second and first semiconductor layers, a gate electrode formed at the gate trench, and a source electrode and a drain electrode formed on the second semiconductor layer. The gate trench has terminal parts of a bottom of the gate trench formed shallower than a center part of the bottom.
Fujitsu Limited


07/14/16
20160204240 

Power semiconductor device


A power semiconductor device is provided comprising: a collector electrode, a collector layer of a second conductivity type, a drift layer of a first conductivity type, a base layer of the second conductivity type, a first insulating layer having an opening, an emitter layer of the first conductivity type, the emitter layer contacts the base layer and separated from the drift layer by one of the first insulating layer or the base layer, a body layer of the second conductivity type arranged laterally to the emitter layer and separated from the base layer by the first insulating layer and the emitter layer, a source region of the first conductivity type separated from the emitter layer by the body layer, an emitter electrode contacted by the source region. The device further comprises a first layer of the second conductivity type contacting the emitter electrode and separated from the base layer, and a second layer of the first conductivity type arranged between the first layer and the base layer and separated from the emitter layer and the source region.
Abb Technology Ag


07/14/16
20160204237 

Semiconductor device


A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth p layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth p layers respectively have surface concentrations p(1) to p(4) that decrease in this order, bottom-end distances d(1) to d(4) that increase in this order, and distances b(1) to b(4) to the edge of the semiconductor substrate that increase in this order.
Mitsubishi Electric Corporation


07/14/16
20160204236 

Semiconductor device


A semiconductor device includes: a first conductivity-type collector region; a second conductivity-type field stop region disposed on the collector region; a second conductivity-type drift region, which is disposed on the field stop region and has an impurity concentration lower than the field stop region; a first conductivity-type base region disposed on the drift region; and a second conductivity-type emitter region disposed on the base region, wherein an impurity concentration gradient in a film thickness direction of the field stop region is larger in a region adjacent to the collector region than in a region adjacent to the drift region.. .
Sanken Electric Co., Ltd.


07/14/16
20160204235 

Bipolar transistor, semiconductor device, and bipolar transistor manufacturing method


Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor includes: a collector layer that has a long-side direction and a short-side direction in a plan view, in which the short-side direction is parallel to crystal orientation [011], a cross-section perpendicular to the short-side direction has an inverted mesa shape, and a cross-section perpendicular to the long-side direction has a forward mesa shape; a base layer that is formed on the collector layer; a base electrode that is formed on the base layer; and a base line that is connected to the base electrode and that is drawn out from an end in the short-side direction of the collector layer to the outside of the collector layer in a plan view..
Murata Manufacturing Co., Ltd.


07/14/16
20160204232 

Manufacturing the semiconductor device


The semiconductor device is manufactured through the following steps: after first heat treatment is performed on an oxide semiconductor film, the oxide semiconductor film is processed to form an oxide semiconductor layer; immediately after that, side walls of the oxide semiconductor layer are covered with an insulating oxide; and in second heat treatment, the side surfaces of the oxide semiconductor layer are prevented from being exposed to a vacuum and defects (oxygen deficiency) in the oxide semiconductor layer are reduced.. .
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204231 

Semiconductor device and manufacturing method thereof


A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204230 

Method for fabricating semiconductor device


A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a control gate) and the width of the second gate (may serve for a select gate).
United Microelectronics Corp.


07/14/16
20160204220 

Method for manufacturing silicon carbide semiconductor device


A method for manufacturing a silicon carbide semiconductor device includes steps of preparing a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, forming a groove portion in the first main surface of the silicon carbide substrate, and cutting the silicon carbide substrate at the groove portion. The step of forming the groove portion includes a step of thermally etching the silicon carbide substrate using chlorine.
Sumitomo Electric Industries, Ltd.


07/14/16
20160204219 

Semiconductor device comprising ferroelectric elements and fast high-k metal gate transistors


A semiconductor device comprises a first and second circuit element. The first circuit element comprises a first electrode structure including a first high-k dielectric layer, the first high-k dielectric layer having a first thickness and comprising hafnium.
Globalfoundries Inc.


07/14/16
20160204217 

Devices with fully and partially silicided gate structures in gate first cmos technologies


A semiconductor product with certain devices having a first device with a fully silicided (fusi) gate and a second device with a partially silicided gate is disclosed. In one example, the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process.
Globalfoundries Inc.


07/14/16
20160204215 

Semiconductor device and manufacturing method thereof


A fin fet semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The fin fet device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/14/16
20160204213 

Semiconductor device


A semiconductor device according to an embodiment switches high-frequency signals and includes a semiconductor layer of a first conductivity type. A first layer of a second conductivity type is provided in the semiconductor layer.
Kabushiki Kaisha Toshiba


07/14/16
20160204210 

Semiconductor device having field plate structures and gate electrode structures between the field plate structures


A semiconductor device includes a field effect transistor in a semiconductor substrate having a first surface. The field effect transistor includes a first field plate structure and a second field plate structure, each extending in a first direction parallel to the first surface, and gate electrode structures disposed over the first surface and extending in a second direction parallel to the first surface, the gate electrode structures being disposed between the first and the second field plate structures..
Infineon Technologies Austria Ag


07/14/16
20160204207 

Composite high-k metal gate stack for enhancement mode gan semiconductor devices


Enhancement mode gallium nitride (gan) semiconductor devices having a composite high-k metal gate stack and methods of fabricating such devices are described. In an example, a semiconductor device includes a gallium nitride (gan) channel region disposed above a substrate.
Intel Corporation


07/14/16
20160204206 

Silicon carbide semiconductor device and manufacturing same


A silicon carbide semiconductor device includes: a silicon carbide off substrate including a main surface having an off angle relative to a basal plane, the main surface being provided with a trench, the trench having a plurality of side walls and a bottom portion; a gate insulating film covering the side walls and the bottom portion; and a gate electrode provided on the gate insulating film, each of the side walls having an angle of more than 65° and not more than 80° relative to the basal plane in the trench, opening directions of the plurality of side walls being all at a silicon plane side or a carbon plane side.. .
Sumitomo Electric Industries, Ltd.


07/14/16
20160204203 

Metal oxide semiconductor having epitaxial source drain regions and a manufacturing same using dummy gate process


A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.. .
Sony Corporation


07/14/16
20160204201 

Semiconductor devices having channels with retrograde doping profile


A device isolation region is formed, delimiting an active region in a substrate. A word line is formed, extending across the active region and the device isolation region and buried therein.

07/14/16
20160204200 

Semiconductor device with non-linear surface


A semiconductor device includes a first channel having a first linear surface and a first non-linear surface. The semiconductor device includes a first dielectric region surrounding the first channel.
Taiwan Semiconductor Manufacturing Company Limited


07/14/16
20160204192 

Semiconductor device and manufacturing the semiconductor device


In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region.
Renesas Electronics Corporation


07/14/16
20160204178 

Semiconductor device


Semiconductor elements deteriorate or are destroyed due to electrostatic discharge damage. The present invention provides a semiconductor device in which a protecting means is formed in each pixel.
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204152 

Imaging device, imaging apparatus, production apparatus and method, and semiconductor device


There is provided an imaging device including a semiconductor having a light-receiving portion that performs photoelectric conversion of incident light, electrically conductive wirings, and a contact group including contacts that have different sizes and connect the semiconductor and the electrically conductive wirings.. .
C/o Sony Corporation


07/14/16
20160204137 

Semiconductor device and manufacturing method thereof


A manufacturing method of a semiconductor device comprises the steps of: providing a transparent substrate; forming a gate electrode on the transparent substrate; forming a gate insulation layer covering the gate electrode; forming an oxide semiconductor layer on the gate insulation layer and at least partially over the gate electrode; forming an etching stop layer over the gate electrode and at least covering a part of the oxide semiconductor layer, wherein the etching stop layer includes an opening; forming an electrode layer at the opening and on a part of the etching stop layer; and applying a low-resistance treatment to a part of the oxide semiconductor layer uncovered by the etching stop layer and the electrode layer to form a pixel electrode.. .
Hannstar Display Corporation


07/14/16
20160204131 

Strain release in pfet regions


A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (ssoi) structure, the ssoi structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the ssoi structure, forming a gate structure over a portion of at least one fin in a nfet region, forming a gate structure over a portion of at least one fin in a pfet region, removing the gate structure over the portion of the at least one fin in the pfet region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pfet region, such that the new gate structure surrounds the portion on all four sides.. .
International Business Machines Corporation


07/14/16
20160204129 

Fdsoi - capacitor


A method of manufacturing a semiconductor device including a capacitor structure is provided, including the steps of providing an soi wafer comprising a substrate, a buried oxide (box) layer formed over the substrate and a semiconductor layer formed over the box layer, removing the semiconductor layer in a first region of the wafer to expose the box layer, forming a dielectric layer over the exposed box layer in the first region, and forming a conductive layer over the dielectric layer. Moreover, a semiconductor device including a capacitor formed on a wafer is provided, wherein the capacitor comprises a first capacitor electrode comprising a doped semiconductor substrate of the wafer, a capacitor insulator comprising an ultra-thin box layer of the wafer and a high-k dielectric layer formed on the ultra-thin box layer, and a second capacitor electrode comprising a conductive layer formed over the high-k dielectric layer..
Globalfoundries Inc.


07/14/16
20160204128 

Cointegration of bulk and soi semiconductor devices


A method of forming a semiconductor device structure includes providing a substrate with a semiconductor-on-insulator (soi) configuration, the soi substrate comprising a semiconductor layer formed on a buried oxide (box) layer which is disposed on a semiconductor bulk substrate, forming trench isolation structures delineating a first region and a second region within the soi substrate, removing the semiconductor layer and the box layer in the first region for exposing the semiconductor bulk substrate within the first region, forming a first semiconductor device with an electrode in and over the exposed semiconductor bulk substrate in the first region, forming a second semiconductor device in the second region, the second semiconductor device comprising a gate structure disposed over the semiconductor layer and the box layer in the second region, and performing a polishing process for defining a common height level to which the electrode and the gate structure substantially extend.. .
Globalfoundries Inc.


07/14/16
20160204123 

Method of fabricating three-dimensional semiconductor devices, and three-dimensional semiconductor devices thereof


Present example embodiments relate generally to semiconductor devices and methods of fabricating a semiconductor device comprising providing a substrate and forming a plurality of layers over the substrate. The plurality of layers comprise alternating first composition material layers and second composition material layers.
Macronix International Co., Ltd.


07/14/16
20160204119 

Semiconductor device


A semiconductor device may include: a plurality of source-side half channels positioned in a first region and arranged in first to 2nth rows, wherein n is an integer equal to or greater than 2; a plurality of first drain-side half channels positioned in a second region at one side of the first region and arranged in first to nth rows; a plurality of second drain-side half channels positioned in a third region at the other side of the first region and arranged in first to nth rows; a plurality of first pipe channels suitable for connecting the first to nth rows of source-side half channels to the first to nth rows of first drain-side half channels, respectively; and a plurality of second pipe channels suitable for connecting the (n+1)th to 2nth rows of source-side half channels to the first to nth rows of second drain-side half channels, respectively.. .
Sk Hynix Inc.


07/14/16
20160204116 

Method for manufacturing a semiconductor device


The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate.
Renesas Electronics Corporation


07/14/16
20160204115 

Semiconductor device and fabricating the same


A semiconductor device includes stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.. .
Sk Hynix Inc.


07/14/16
20160204114 

Semiconductor device


A semiconductor device includes first and second well regions having a first conductivity type, and a third well region between the first and second well regions having a second conductivity type different from the first conductivity type. A first active region is in the first well region.
Samsung Electronics Co., Ltd.


07/14/16
20160204113 

Semiconductor device, related manufacturing method, and related electronic device


A semiconductor device may include a first inverter, a second inverter, a first access transistor, and a second access transistor. A drain electrode of the first access transistor or a source electrode of the first access transistor may be electrically connected to both an output terminal of the first inverter and an input terminal the second inverter.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204112 

Semiconductor device and fabricating the same


A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.. .

07/14/16
20160204109 

Semiconductor device and fabricating method thereof


A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench.. .

07/14/16
20160204108 

Cmos transistor, semiconductor device including the transistor, and semiconductor module including the device


Provided are a cmos transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The cmos transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate.

07/14/16
20160204106 

Semiconductor devices and methods of fabricating the same


A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a fin which comprises long sides and a first short side, a first trench which is immediately adjacent the first short side of the fin and has a first depth, a second trench which is immediately adjacent the first trench and has a second depth greater than the first depth, a first protrusion structure which protrudes from a bottom of the first trench and extends side by side with the first short side, and a gate which is formed on the first protrusion structure to extend side by side with the first short side..

07/14/16
20160204105 

Method and device for a finfet


A method of forming a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of fins formed thereon, a stress layer formed on the top surface of each of the fins, and a plurality of strip-shaped gate structures formed above the stress layers.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204103 

Semiconductor device structure


A semiconductor device structure having at least one thin-film resistor structure is provided. Through the metal plug(s) or metal wirings located on different layers, a plurality of stripe segments of the thin-film resistor structure is electrically connected to ensure the thin-film resistor structure with the predetermined resistance and less averting areas in the layout design..
United Microelectronics Corp.


07/14/16
20160204102 

Three-dimensional semiconductor device and manufacturing the same


A three-dimensional (3d) semiconductor device is provided, comprising a substrate having a staircase region comprising n steps, wherein n is an integer one or greater; a stack having multi-layers on the substrate, and the multi-layers comprising active layers alternating with insulating layers on the substrate, the stack comprising a plurality of sub-stacks formed on the substrate and the sub-stacks disposed in relation to the n steps to form respective contact regions; and a plurality of connectors formed in the respective contact regions, and the connectors extending downwardly to connect a bottom layer under the multi-layers.. .
Macronix International Co., Ltd.


07/14/16
20160204100 

Semiconductor device and formation method thereof


The present disclosure provides a semiconductor device and formation method thereof. A shallow trench isolation structure is formed in a semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204099 

Semiconductor device and manufacturing the same


Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion.
Renesas Electronics Corporation


07/14/16
20160204097 

Semiconductor device having overload current carrying capability


A semiconductor device includes a semiconductor region having charge carriers of a first conductivity type, a transistor cell in the semiconductor region, and a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type. A semiconductor auxiliary region in the semiconductor region has a second doping concentration of charge carriers of the second conductivity type, which is at least 30% higher than the first doping concentration.
Infineon Technologies Ag


07/14/16
20160204095 

Semiconductor device


A first impurity diffusion region is provided within a semiconductor substrate, a second impurity diffusion region is provided within the first impurity diffusion region, a third impurity diffusion region is provided within the second impurity diffusion region, a first portion of a fourth impurity diffusion region is provided within the second impurity diffusion region so as to be spaced from the third impurity diffusion region, and a second portion of the fourth impurity diffusion region is provided in a third portion of the first impurity diffusion region on a side of a surface of the semiconductor substrate, a first contact is provided so as to be in contact with the second portion, the first contact and the third portion overlap in plan view, and a first power supply is connected to the third impurity diffusion region.. .
Seiko Epson Corporation


07/14/16
20160204092 

Semiconductor device


The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed.
Renesas Electronics Corporation


07/14/16
20160204086 

Methods of manufacturing wide band gap semiconductor device and semiconductor module, and wide band gap semiconductor device and semiconductor module


A method of manufacturing a wide band gap semiconductor device includes the steps of preparing a wide band gap semiconductor substrate, separating the wide band gap semiconductor substrate into a plurality of first semiconductor chips (80), fixing the plurality of first semiconductor chips (80) on a fixation member (70), measuring a breakdown voltage of each of the first semiconductor chips (80) while immersing at least the first semiconductor chips (80) in inert liquid (91), and after the step of measuring a breakdown voltage of each of the first semiconductor chips (80), providing a plurality of second semiconductor chips each having each of the first semiconductor chips (80) fixed on the fixation member (70), by cutting the fixation member (70).. .
Sumitomo Electric Industries, Ltd.


07/14/16
20160204084 

Front-to-back bonding with through-substrate via (tsv)


Methods for forming a semiconductor device structure are provided. The method includes providing a first semiconductor wafer and a second semiconductor wafer.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/14/16
20160204083 

Integrated semiconductor device and wafer level fabricating the same


The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“tsv”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad..
Taiwan Semiconductor Manufacturing Company, Ltd.


07/14/16
20160204082 

Method of manufacturing semiconductor device


In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip..
Renesas Electronics Corporation


07/14/16
20160204081 

Semiconductor device and manufacturing the same


The present invention provides a semiconductor device with an improved yield ratio and reduced height and manufacturing cost; and a method of manufacturing the semiconductor device. According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a semiconductor element that is flip-chip connected to the substrate, and a molding portion that seals the semiconductor element.
Cypress Semiconductor Corporation


07/14/16
20160204079 

Methods and apparatus of packaging with interposers


Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/14/16
20160204072 

Semiconductor apparatus and manufacturing same


According to the embodiments, a semiconductor device includes a substrate, a plurality of insulating layers, a lower shield plate, a semiconductor device, an upper shield plate, and a side shield member. A first contact portion is formed on the substrate.
Kabushiki Kaisha Toshiba


07/14/16
20160204070 

Semiconductor device and manufacturing method thereof


A method for manufacturing a semiconductor device is provided. The method comprises the steps of: providing a transparent substrate having a visible region and an invisible region; forming a gate and at least an alignment mark coplanarly on the transparent substrate, wherein the gate is located in the visible region and the alignment mark is located in the invisible region; forming a gate insulation layer to cover the gate and cover the alignment mark; forming an oxide semiconductor layer on the gate insulation layer above the gate; and forming an etching stop layer above the gate and the alignment mark..
Hannstar Display (nanjing) Corporation


07/14/16
20160204069 

Semiconductor device with reduced via resistance


A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level.
International Business Machines Corporation


07/14/16
20160204068 

Semiconductor device and semiconductor device manufacturing method


A method includes forming a multilayered film including a conductive layer mainly containing aluminum, and a barrier metal layer formed thereon, forming a hard mask layer on the barrier metal layer, patterning a resist on the hard mask layer, patterning the hard mask layer by dry-etching the hard mask layer with the patterned resist as a mask, cleaning a surface of the barrier metal layer with a cleaning solution after the patterning the hard mask layer, and dry-etching the multilayered film with the patterned hard mask layer as a mask after the cleaning the surface of the barrier metal layer. In the patterning the hard mask layer, dry etching is performed with a ratio of a flow rate of an oxidizing gas to a total flow rate of a process gas at less than 1% in a state in which the barrier metal layer is exposed to the process gas..
Canon Kabushiki Kaisha


07/14/16
20160204066 

Semiconductor device and fabrication method thereof


The present disclosure provides a semiconductor device and fabrication method thereof. A dielectric layer is formed on a first surface of a semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204058 

Semiconductor device


A power supply wiring structure of a semiconductor device including a semiconductor chip flip-chip mounted on a substrate decreases the characteristic impedance of internal wiring and thereby increases the noise reduction effect, while achieving low impedance during high frequency power supply operation. A semiconductor device has an inner power supply plate structure on a first insulating film on a protection film of a semiconductor chip, in an inner region of a plurality of peripheral electrode pads on a mounting surface of the semiconductor chip as viewed in plan, for supplying power to the semiconductor chip.
Noda Screen Co., Ltd.


07/14/16
20160204057 

Semiconductor device


A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin.
Renesas Electronics Corporation


07/14/16
20160204056 

Wiring board with interposer and dual wiring structures integrated together and making the same


A wiring board with integrated interposer and dual wiring structures is characterized in that an interposer and a first wiring structure are positioned within a through opening of a stiffener whereas a second wiring structure is disposed beyond the through opening of the stiffener. The mechanical robustness of the stiffener can prevent the wiring board from warping.
Bridge Semiconductor Corporation


07/14/16
20160204052 

Packaged semiconductor device having leadframe features preventing delamination


A semiconductor device has a leadframe with a first (401a) and a parallel second surface, and an assembly pad (410) bordered by two opposing sides, which include a plurality of through-holes (420) from the first to the second pad surface. Another pad side includes one or more elongated windows (421) between the pad surfaces.
Texas Instruments Incorporated


07/14/16
20160204050 

Semiconductor device, related manufacturing method, and related electronic device


A method for manufacturing a semiconductor device may include the following steps: preparing a first substrate; providing a first conductor, which is configured to electrically connect two elements associated with the first substrate; providing a second conductor on the first substrate, wherein the second conductor is electrically connected to the first conductor; preparing a second substrate; providing a third conductor, which is configured to electrically connect two elements associated with the second substrate; providing a fourth conductor on the second substrate, wherein the fourth conductor is electrically connected to the third conductor; providing a fifth conductor on the fourth conductor; and combining the fifth conductor with the second conductor through eutectic bonding.. .
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204047 

Semiconductor device and manufacturing the same


A semiconductor device includes: a semiconductor element having a solder region and a non-solder region on a first face; a first metal member disposed on the first face of the semiconductor element; a second metal member disposed on a rear face of the semiconductor element; a first solder that connects the solder region of the semiconductor element and the first metal member; and a second solder that connects the rear face of the semiconductor element and the second metal member. At least the second solder provides a melt-bond.
Denso Corporation


07/14/16
20160204046 

Semiconductor device


A semiconductor device includes a semiconductor chip, a resin mold portion sealing a component in which the semiconductor chip is included, and a bonding layer disposed between the resin mold portion and the component. The bonding layer is made of an organic resin that is disposed at an obverse side of the component, and includes a first layer bonded to the component and a second layer bonded to the resin mold portion.
Denso Corporation


07/14/16
20160204041 

Method of inspecting semiconductor device and fabricating semiconductor device using the same


A method of inspecting a semiconductor device includes providing a substrate, on which a mold layer with a plurality of mold openings is provided, milling the mold layer in a direction inclined at a predetermined angle with respect to a direction normal to a top surface of the substrate, such that an inclined cutting surface exposing milled mold openings is formed, the milled mold openings including first milling openings along a first column extending in a first direction and having different heights, obtaining image data of the cutting surface, the image data including first contour images of the first milling openings, and obtaining a first process parameter, which represents an extent of bending of the mold openings according to a distance from a top surface of the substrate, using positions of center points of the first contour images.. .
Samsung Electronics Co., Ltd.


07/14/16
20160204040 

Manufacturing apparatus of semiconductor device and management manufacturing apparatus of semiconductor device


According to one embodiment, a management method of a manufacturing apparatus of a semiconductor device, the method includes measuring a weight of a pre-exposure substrate including a semiconductor substrate and a resist film provided on the semiconductor substrate, performing an exposure process for the resist film, measuring a weight of a post-exposure substrate including the semiconductor substrate and the resist film after the exposure process is performed, and acquiring a weight difference between the weight of the pre-exposure substrate and the weight of the post-exposure substrate.. .
Kabushiki Kaisha Toshiba


07/14/16
20160204035 

Backside processed semiconductor device


A method of forming a semiconductor device includes: providing a first substrate, forming at least one transistor on a first surface of the first substrate; forming a first dielectric cap layer covering the first surface of the first substrate; forming a first interconnect structure on the first dielectric cap layer; providing a carrier substrate; bonding the carrier substrate to the first substrate through the first dielectric cap layer; and from a second surface of the first substrate opposite to the first surface, thinning the first substrate to a second depth.. .
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204030 

Methods of forming semiconductor device


A sacrificial layer is formed to cover the gate structures. The sacrificial layer is patterned to form a first opening in the sacrificial layer.
Samsung Electronics Co., Ltd.


07/14/16
20160204025 

Transistor, semiconductor device and manufacturing the same


A semiconductor device including a central region, side regions located in both sides of the central region, and conductive layers including a first barrier pattern formed in the central region, a material pattern formed in the first barrier pattern and having an etch selectivity with respect to the first barrier pattern, and a second barrier pattern formed in the material pattern; and insulating layers alternately stacked with the conductive layers.. .
Sk Hynix Inc.


07/14/16
20160204022 

Semiconductor device structures with improved planarization uniformity, and related methods


Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines.
Micron Technology, Inc.


07/14/16
20160204010 

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device includes a step of vacuum packing a sawn wafer while being housed in a shipping case. The shipping case has the following structure.

07/14/16
20160204001 

Metal etchant compositions and methods of fabricating a semiconductor device using the same


The present inventive concepts provide metal etchant compositions and methods of fabricating a semiconductor device using the same. The metal etchant composition includes an organic peroxide in a range of about 0.1 wt % to about 20 wt %, an organic acid in a range of about 0.1 wt % to about 70 wt %, and an alcohol-based solvent in a range of about 10 wt % to about 99.8 wt %.

07/14/16
20160204000 

Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device in accordance with the present invention includes the steps of preparing a semiconductor substrate, placing the semiconductor substrate on an electrostatic chuck, chucking the semiconductor substrate after raising a temperature of the electrostatic chuck to a first temperature, raising a temperature of the electrostatic chuck to a second temperature which is higher than the above-described first temperature in a state where the semiconductor substrate is chucked, and performing a treatment to the semiconductor substrate in a state where a temperature of the electrostatic chuck is maintained at the above-described second temperature.. .
Sumitomo Electric Industries, Ltd.






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