|| List of recent Semiconductor Device-related patents
|Determining overall optimal yield point for a semiconductor wafer|
A computer determines a component optimal yield point for each component of the plurality of components, where the component optimal yield point represents the process parameter values where maximum yield is achieved for a component. The computer determines a weight factor for each component of the plurality of components, where the weight factor represents an importance of a component to the semiconductor device.
|Layout decomposition method and method for manufacturing semiconductor device applying the same|
A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system.
|Scan circuit, semiconductor device, and method for testing semiconductor device|
A semiconductor device includes: a combination circuit; and a scan circuit, wherein the scan circuit includes: a first scan chain in which a plurality of first flip-flops are connected in series; and a second scan chain in which a plurality of second flip-flops are connected in series. The first scan chain is configured to capture first output data of at least one of the first flip-flops of the second scan chain, and the second scan chain is configured to capture second output data of at least one of the second flip-flops of the first scan chain..
|Digital wireless data collection|
The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a portable device.
|Single-ended high voltage input-capable comparator circuit|
A single-ended comparator is disclosed herein. The comparator may be implemented with low-voltage semiconductor devices that are capable of operating with high-voltage signals at an input.
|Semiconductor device manufacturing method|
According to one embodiment, a semiconductor device manufacturing method includes depositing a silicon film above a semiconductor substrate, forming an insulating film which includes silicon oxide or silicon nitride on the silicon film, forming a physical guide having a depressed portion above the insulating film, forming a directed self-assembly material layer which includes a first polymer and a second polymer in the depressed portion of the physical guide, phase-separating the directed self-assembly material layer into a first region which includes the first polymer and a second region which includes the second polymer, removing the second region, processing the insulating film by using the physical guide and the first region as masks, and transferring a pattern corresponding to the second region to the insulating film. Further, the silicon film is processed by using the pattern transferred onto the insulating film as a mask..
|Method of manufacturing semiconductor device|
A method of manufacturing a semiconductor device is disclosed. The method may comprise: etching a plurality of first openings in an interlayer dielectric layer on a substrate; forming an opening modifying layer in the plurality of first openings; and etching the opening modifying layer until the substrate is exposed, resulting in a plurality of second openings, wherein the second openings have a depth-to-width ratio greater than that of the first openings.
|Selective removal of gate structure sidewall(s) to facilitate sidewall spacer protection|
Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s).
|Process for the manufacture of semiconductor devices comprising the chemical mechanical polishing of elemental germanium and/or si1-xgex material in the presence of a cmp composition having a ph value of 3.0 to 5.5|
A process for the manufacture of semiconductor devices comprising the chemical mechanical polishing of elemental germanium and/or si1-xgex material with 0.1≦x<1 in the presence of a chemical mechanical polishing (cmp) composition having a ph value in the range of from 3.0 to 5.5 and comprising: (a) inorganic particles, organic particles, or a mixture or composite thereof (b) at least one type of an oxidizing agent, and (c) an aqueous medium.. .
|Semiconductor device and method of forming through-silicon-via with sacrificial layer|
A semiconductor device can be formed by first providing a semiconductor wafer, and forming a conductive via into the semiconductor wafer. A portion of the semiconductor wafer can be removed so that the conductive via extends above a surface of the semiconductor wafer.
|Semiconductor device and a method of manufacturing the same|
For simplifying the dual-damascene formation steps of a multilevel cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film.
|Device and methods for small trench patterning|
A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers.
|Manufacturing method for semiconductor device|
A manufacturing method for a semiconductor device includes introducing an impurity into a sic substrate, forming a mixed material layer, which is made from a resin and a fibrous carbon material, on a surface of the sic material into which the impurity is introduced, performing heat treatment of the sic substrate in which the mixed material layer is formed on the surface of the sic substrate, and removing the mixed material layer after the heat treatment.. .
|Method for manufacturing semiconductor device|
An sot substrate (6), in which a silicon layer (5) is provided on a silicon substrate (3) via a silicon oxide film (4), is formed. Next, a plurality of semiconductor elements (8) is formed on a surface of the silicon layer (5).
|Methods of forming semiconductor device structures including an insulative material on a semiconductive material, and related semiconductor device structures and semiconductor devices|
A method of forming a semiconductor device structure. The method comprises forming an insulative material on a semiconductive material, and microwave annealing at least an interface between the insulative material and the semiconductive material.
|Methods of forming a pattern and methods of manufacturing a semiconductor device using the same|
A method of forming a pattern includes forming an underlayer on an etching target layer by a chemical vapor deposition (cvd) process, the underlayer including a silicon compound combined with a photoacid generator (pag), forming a photoresist layer on the underlayer, irradiating extreme ultraviolet (euv) light on the photoresist layer to form a photoresist pattern, and etching the etching target layer using the photoresist pattern as an etching mask.. .
|Methods of manufacturing a semiconductor device|
A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion.
|Method of manufacture for a semiconductor device|
A method of manufacturing a semiconductor device includes providing a semiconductor layer of a first conductivity type and forming a semiconductor layer of a second conductivity type thereon. The method also includes forming an insulator layer on the semiconductor layer of the second conductivity type, etching a trench into at least the semiconductor layer of the second conductivity type, and forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type.
|Methods for forming semiconductor devices using sacrificial layers|
A fabricating method for a semiconductor device is provided. The fabricating method includes providing a first wafer, forming a sacrificial layer on the first wafer, forming a release layer on the sacrificial layer, forming an adhesive layer on the release layer, and placing a second wafer on the adhesive layer and bonding the first wafer to the second wafer..
|Semiconductor device and manufacturing method thereof|
An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current.
|Semiconductor device having a bonding pad and shield structure and method of manufacturing the same|
A method of fabricating a semiconductor device includes providing a device substrate having a front side and a back side corresponding to a front side and a back side of the semiconductor device, forming, on the front side of the device substrate, a metal feature, forming, on the back side of the device substrate, an insulating layer, forming, on the back side of the semiconductor device, a trench exposing the metal feature, forming a bonding pad in the trench in electrical communication with the metal feature, and forming, on the insulating layer, a metal shield, in which the metal shield and the bonding pad have different thicknesses relative to each other.. .
|Sealing member, sealing method, and method for producing optical semiconductor device|
A sealing member includes an elongated releasing film, and a plurality of sealing resin layers composed of a sealing resin, the plurality of sealing resin layers being laminated on the releasing film so that the plurality of sealing resin layers are arranged in a row along the longitudinal direction of the releasing film with a space provided therebetween.. .
|Semiconductor device and a method of manufacturing the same|
A semiconductor device is manufactured by forming at least one epitaxial structure over a substrate. A portion of the substrate is cut and lifted to expose a partial surface of the epitaxial structure.
|Fabricating method of customized mask and fabricating method of semiconductor device using customized mask|
A fabricating method of a customized mask includes forming first patterns in a mold structure, forming second patterns in the mold structure using initial masks, the mold structure having the first patterns formed therein, measuring overlap failure between the first patterns and the second patterns, and fabricating customized masks by compensating for pattern positions of the initial masks based on the measuring results, wherein compensating for the pattern positions of the initial masks includes shifting positions of at least some patterns of the initial masks according to shift directions and sizes of at least some of the first patterns.. .
|Method and apparatus for making a semiconductor device|
Disclosed is an apparatus and method for yield enhancement of making a semiconductor device. The apparatus for yield enhancement of making a semiconductor device comprises: a semiconductor device comprising an epitaxial layer in which a defect is included, and a photo-resistor on the epitaxial layer and covering the defect; an image recognition system to detect and identify a location of the defect; and an exposing module comprising a first light source to expose a part of the photo-resistor substantially corresponding to the detected defect identified by the image recognition system..
|Semiconductor device defect inspection method and system thereof|
Provided are a semiconductor device defect inspection method and system thereof, with which predetermined hot spots are inspected using a sem, and with which the frequency of defects occurring at the hot spot is estimated statistically and with reliability. An inspection point is designated in design data by the defect type.
|Memory core and semiconductor memory device including the same|
A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages..
A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a mos type first transistor section (3) used for information storage, and a mos type second transistor section (4) which selects the first transistor section.
|String selection structure of three-dimensional semiconductor device|
A three-dimensional semiconductor device includes first and second selection lines stacked one on the other. An upper line horizontally crosses over the first and second selection lines.
|Semiconductor device having features to prevent reverse engineering|
A rom circuit includes a first n channel transistor having an output and having device geometry and device characteristics adapted to bias the output at a predetermined level when a p channel circuit is connected to the first n channel transistor; a pass transistor connected between the output and a data bus, the pass transistor connected to a word line, the word line adapted to turn on the pass transistor when the word line is asserted; and the p channel circuit connected to the data bus and adapted to provide leakage current to charge a gate in the first n channel transistor when pass transistor is turned on.. .
|Three-dimensional semiconductor devices and methods of fabricating the same|
According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.. .
|Motor-drive unit having heat radiator|
A compact motor-drive unit wherein each component can be stably fixed to the unit. A motor-drive unit has a plurality of substrates each having a circuit for driving a motor; semiconductor devices mounted on the respective substrates; at least one smoothing capacitor mounted on at least one of the substrates; and a heat radiator having a heat-transferring surface adjacent to the semiconductors.
|Optical semiconductor device|
An optical semiconductor device includes: semiconductor lasers; a wave coupling section multiplexing light output by the semiconductor lasers; first optical waveguides respectively optically connecting respective semiconductor lasers to the wave coupling section; a phase regulator regulating phase of reflected light that is reflected at a reflecting point located in the optical semiconductor device and that returns to the semiconductor lasers; a second optical waveguide optically connecting the wave coupling section to the phase regulator; an optical amplifying section amplifying output light of the phase regulator; and a third optical waveguide optically connecting an output of the phase regulator to the optical amplifying section. The phase regulator adjusts the phase of reflected light that returns to the semiconductor lasers to decrease line width of the light output by the semiconductor lasers..
|Semiconductor device, method for manufacturing the same, power supply device, and high-frequency amplifier|
A semiconductor device includes: a compound semiconductor stack structure including a plurality of compound semiconductor layers stacked over a semiconductor substrate; a first insulating film covering the surface of the compound semiconductor stack structure; and a conductive film provided on the surface of the first insulating film.. .
|Semiconductor device with igbt cell and desaturation channel structure|
A semiconductor device includes an igbt cell including a second-type doped drift zone, and a desaturation semiconductor structure for desaturating a charge carrier concentration in the igbt cell. The desaturation structure includes a first-type doped region forming a pn-junction with the drift zone, and two portions of a trench or two trenches arranged in the first-type doped region and beside the igbt cell in a lateral direction.
An object of one embodiment of the present invention to provide a latch circuit includes a level shifter and a buffer in which transistors each including a channel region formed in an oxide semiconductor film are connected in series. Thus, data can be held in the latch circuit even when power is not supplied..
|Test equipment for testing semiconductor device and methods of testing semiconductor device using the same|
A method of testing a semiconductor device using the test equipment includes loading an undivided printed circuit board (pcb) including unit pcbs in a test equipment. A semiconductor device is mounted in each of the unit pcbs.
A semiconductor device includes a substrate having a first surface, a height adjuster mounted on the first surface of the substrate via a first adhesive layer, a semiconductor chip mounted on the height adjuster via a second adhesive layer, an electronic component mounted on the first surface of the substrate via a third adhesive layer, a bonding wire, and a sealing member. The length of the electronic component in a first direction corresponding to the thickness direction of the substrate is larger than the length of the semiconductor chip in the first direction, and the sum of the lengths of the height adjuster, the second adhesive layer, and the semiconductor chip in the first direction is larger than the length of the electronic component in the first direction..
|Package on package structures and methods for forming the same|
A method of forming a semiconductor device package includes removing a portion of a first connector and a molding compound surrounding the first connector to form an opening, wherein the first connector is part of a first package, and removing the portion of the first connector comprises forming a surface on the first connector which is at an angle with respect to a top surface of the molding compound. The method further includes placing a second connector in the opening, wherein the second connector is part of a second package having a semiconductor die.
|Pad structures and wiring structures in a vertical type semiconductor device|
Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position.
|Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials|
Upon forming a complex metallization system, the parasitic capacitance between metal lines of adjacent metallization layers may be reduced by providing a patterned etch stop material. In this manner, the patterning process for forming the via openings may be controlled in a highly reliable manner, while, on the other hand, the resulting overall dielectric constant of the metallization system may be reduced, thereby also significantly reducing the parasitic capacitance between stacked metal lines..
|Semiconductor devices and methods of fabricating semiconductor devices|
Semiconductor devices are provided. A semiconductor device may include a substrate and a plurality of lines on the substrate.
|Extended redistribution layers bumped wafer|
A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape.
|Bonded system with coated copper conductor|
A semiconductor component includes a semiconductor die and a copper-containing electrical conductor. The semiconductor die has a semiconductor device region, an aluminum-containing metal layer on the semiconductor device region, and at least one additional metal layer on the aluminum-containing metal layer which is harder than the aluminum-containing metal layer.
|Semiconductor device and method for manufacturing the semiconductor device|
A method for manufacturing a semiconductor device is provided, the method including: mounting a first element on a wiring substrate, placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element, attaching the first heat sink to the first element via the metal material by heating and melting the metal material, and mounting a second element on the wiring substrate after the steps of attaching the first heat sink to the first element.. .
|Semiconductor module and method for manufacturing semiconductor module|
A semiconductor module includes a case including a receiving space that is formed by a frame portion and a pair of wall portions disposed to face each other with the frame portion therebetween. The wall portion includes a heat-dissipation portions and a support wall that supports the heat-dissipation portions at the frame portion, and the wall portion includes a heat-dissipation portion and a support wall that supports the heat-dissipation portion at the frame portion.
|Semiconductor device with chip having low-k-layers|
A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.. .
|Optical semiconductor apparatus|
An optical semiconductor apparatus includes a lid body bonded to an upper surface of a frame body, the lid body having an opening at a position vertically overlapping with an optical semiconductor device. The lid body has a first portion which is positioned to surround the opening and has an upper surface to which a light-transmissive member is bonded, a second portion which is positioned to surround the first portion, and a third portion which is positioned to surround the second portion and has a lower surface to which the frame body is bonded.
|Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods|
Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface.
|Semiconductor device having two-way conduction characteristics, and electrostatic discharge protection circuit incorporating the same|
A semiconductor device includes an n-type first doped region for receiving an external voltage, an n-type second doped region and a p-type third doped regions all formed in a p-type substrate, and is configured to have a first threshold voltage for forward conduction between the first and second doped regions, and a second threshold voltage for forward conduction between the first and third doped regions. A current is drained by flowing through the first doped region, the substrate and the second doped region if the external voltage is greater than the first threshold voltage or by flowing through the third doped region, the substrate and the first doped region if the external voltage is less than the second threshold voltage..
|Resistor and resistor fabrication for semiconductor devices|
In a particular embodiment, a method includes removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer. A resistive layer is formed at least partially within the region.
|Mim capacitor and mim capacitor fabrication for semiconductor devices|
In a particular embodiment, a method of forming a metal-insulator-metal (mim) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the mim capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region.
|Stacked structure semiconductor device|
A semiconductor device includes a capacitor formed in a semiconductor substrate of a first conductivity type. The capacitor includes: a heavily-doped layer of a second conductivity type placed over the substrate, a first insulating layer placed over the heavily-doped layer of the second conductivity type, and a first metal layer placed over the first insulating layer.
|Semiconductor device and method of manufacturing the same|
A semiconductor device that is equipped with a semiconductor substrate, a composite metal film, and a detection terminal is provided. The composite metal film is formed on a surface or a back face of the semiconductor substrate, and has a first metal film, and a second metal film that is joined to the first metal film and is different in seebeck coefficient from the first metal film.
A semiconductor device includes a substrate with first and second lower electrodes, a semiconductor element supported on the substrate and including upper and lower electrodes, a conductive bonding material bonding the lower electrode of the element and the substrate to each other, a wire connecting the upper electrode of the element and the substrate to each other, and a sealing resin covering the semiconductor element and the wire. The substrate includes a barrier that encloses at least partially the conductive bonding material..
|Semiconductor device and method of manufacturing semiconductor device|
A semiconductor device includes: an organic substrate; an integrated circuit and a chip part provided on the organic substrate; a molded section including a central portion and a peripheral portion, and forming, as a whole, a concave shape, the central portion sealing the integrated circuit and the chip part on the organic substrate, and the peripheral portion standing around the central portion; and a solid-state image pickup element provided on the central portion of the molded section, the solid-state image pickup element having a top edge that is lower in position in a thickness direction than a top edge of the peripheral portion of the molded section.. .
|Semiconductor device and method of forming the same|
A semiconductor device may include an n-mos transistor, and a p-mos transistor. The p-mos transistor may include, but is not limited to, a gate insulating film and a gate electrode.
|Trench silicide and gate open with local interconnect with replacement gate process|
A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel.
|Semiconductor device and fabrication method|
Semiconductor devices and fabrication methods are provided. In an exemplary method, a semiconductor layer including a first opening can be provided.
|Semiconductor device and manufacturing method thereof|
A semiconductor device and manufacturing method are disclosed which provide increased esd resistance. By disposing a slit mask when forming a second p-type well layer, impurity concentration of the second p-type well layer is partially reduced.
A semiconductor device with improved characteristics is provided. The semiconductor device includes a ldmos, a source plug electrically coupled to a source region of the ldmos, a source wiring disposed over the source plug, a drain plug electrically coupled to a drain region of the ldmos, and a drain wiring disposed over the drain plug.
|Ldmos power semiconductor device and manufacturing method of the same|
An electronic semiconductor device comprising: a semiconductor body, having a first side and a second side opposite to one another and including a first structural region facing the second side, and a second structural region extending over the first structural region and facing the first side; a body region extending in the second structural region at the first side; a source region extending inside the body region; an ldd region facing the first side of the semiconductor body; and a gate electrode. The device comprises: a trench dielectric region extending through the second structural region a first trench conductive region immediately adjacent to the trench dielectric region; and a second trench conductive region in electrical contact with the body region and with the source region.
|Power integrated circuit including series-connected source substrate and drain substrate power mosfets|
A semiconductor device containing a high voltage mos transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. Resurf trenches cut through the drain drift region and body region parallel to channel current flow.
|Semiconductor device and manufacturing method thereof|
A semiconductor device includes a substrate, and a gate electrode formed on the substrate on a gate insulation film. The semiconductor device also includes a source diffusion layer and a drain diffusion layer which are formed on the substrate where the gate electrode is sandwiched between the source diffusion layer and the drain diffusion layer, one or more source contacts formed on the source diffusion layer; and one or more drain contacts formed on the drain diffusion layer.
|Trench shielding structure for semiconductor device and method|
A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein.
|Semiconductor device and method of forming the same|
A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls.
|Vertical type semiconductor devices|
A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines.
|Semiconductor device having dual parallel channel structure and method of fabricating the same|
A semiconductor device may include a substrate having a drift region doped to a first conduction type. A trench may be etched into an upper surface of the substrate.
A superjunction semiconductor device is disclosed in which the tradeoff relationship between on-resistance and breakdown voltage is improved greatly so that reverse recovery capability is improved. A drain drift portion substantially corresponds to a portion just under p-base regions serving as an active region and forms a first parallel pn structure in which a first n-type region and a first p-type region are joined to each other alternately and repeatedly.
A semiconductor device includes element active portion x and element peripheral portion y. An interlayer insulating film is formed on upper surfaces of portions x and y.
|Semiconductor integrated circuit device and a method of manufacturing the same|
Semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.. .
|Non-volatile memory devices having reduced susceptibility to leakage of stored charges and methods of forming same|
Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode.
|Methods for forming etch stop layers, semiconductor devices having the same, and methods for fabricating semiconductor devices|
A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration.
|Three-dimensional semiconductor devices with current path selection structure and methods of operating the same|
Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns.
|Methods of forming semiconductor device with self-aligned contact elements and the resulting device|
One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A transistor device disclosed herein includes a final gate structure that has an upper surface positioned at a first height level above a surface of a substrate, sidewall spacers positioned adjacent the final gate structure, the sidewall spacers having an upper surface that is positioned at a second, greater height level above the substrate, an etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure, and a conductive contact that is conductively coupled to a contact region of the transistor..
|N-channel metal-oxide field effect transistor with embedded high voltage junction gate field-effect transistor|
A semiconductor device comprising a high-voltage (hv) n-type metal oxide semiconductor (nmos) embedded hv junction gate field-effect transistor (jfet) is provided. An hv nmos with embedded hv jfet may include, according to a first example embodiment, a substrate, an n-type well region disposed adjacent to the substrate, a p-type well region disposed adjacent to the n-type well region, and first and second n+ doped regions disposed adjacent to the n-type well and on opposing sides of the p-type well region.
|Semiconductor device, method for manufacturing the same, power supply device, and high-frequency amplifier|
A semiconductor device includes: a compound semiconductor stack structure including a plurality of compound semiconductor layers stacked over a semiconductor substrate; and a first insulating film covering the surface of the compound semiconductor stack structure, the first insulating film being a silicon nitride film including, on the top side, a first region containing nitrogen element in excess of the stoichiometric ratio.. .
Semiconductor device comprising a source electrode, a drain electrode and a semiconducting layer consisting of a single or double 2-dimensional layer(s) made from one of the following materials: mos2, mose2, ws2, wse2, mote2 or wte2.. .
|Finfet device and method of fabricating same|
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having isolation regions, a gate region, source and drain regions separated by the gate region, a first fin structure in a gate region.
|Semiconductor device and fabricating the same|
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (s/d) regions separated by the gate region and a first fin structure in a gate region in the n-fet region.
An insulated gate bipolar transistor having a gate electrode (7) and an emitter electrode (9) is provided in a transistor region. A termination region is arranged around the transistor region.
|Bidirectional semiconductor device for protection against electrostatic discharges|
An integrated circuit is produced on a bulk semiconductor substrate in a given cmos technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate thyristors coupled in parallel and head-to-tail.
|Silicon carbide semiconductor device|
A silicon carbide semiconductor device includes a silicon carbide substrate. The silicon carbide substrate is composed of an element region provided with a semiconductor element portion and a termination region surrounding the element region as viewed in a plan view.
|Electrode configurations for semiconductor devices|
A iii-n semiconductor device can include an electrode-defining layer having a thickness on a surface of a iii-n material structure. The electrode-defining layer has a recess with a sidewall, the sidewall comprising a plurality of steps.
|Semiconductor structure and method for manufacturing the same|
The present invention provides a method for manufacturing a semiconductor structure. The method comprises: providing an soi substrate and forming a gate structure on said soi substrate; etching a soi layer and a box layer of the soi substrate on both sides of the gate structure to form a trench exposing the box layer, said trench partially entering into the box layer; forming a stressed layer that fills up a part of said trench; forming a semiconductor layer covering the stressed layer in the trench.
|Semiconductor device and method for manufacturing the same|
Objects are to provide a semiconductor device for high power application in which a novel semiconductor material having high productivity is used and to provide a semiconductor device having a novel structure in which a novel semiconductor material is used. The present invention is a vertical transistor and a vertical diode each of which has a stacked body of an oxide semiconductor in which a first oxide semiconductor film having crystallinity and a second oxide semiconductor film having crystallinity are stacked.
|Rfid tags based on self-assembly nanoparticles|
A semiconductor device comprising a gate electrode; an insulating layer in electrical connection with the gate electrode; a source electrode and a drain electrode; and a semiconducting channel layer configured to selectively allow electrically connection between the source electrode and the drain electrode based on the voltage on the gate electrode; wherein the semiconducting channel layer comprises metal nanoparticles; and the semiconducting channel layer is in contact with the source electrode, the drain electrode and the insulating layer. A method of manufacturing the semiconductor device of the present invention is also disclosed..
|Cmos nanowire structure|
Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device.
The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of sige alloys or sigesn alloys, and the channel layer is formed of a gesn alloy. The semiconductor device according to the present invention uses a quantum well structure of sige/gesn/sige to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application..
|Compositions for controlled assembly and improved ordering of silicon-containing block copolymers|
The invention provides compositions and methods for inducing and enhancing order and nanostructures in organosilicon block copolymers compositions by including certain organic additives in such compositions that include one or more moieties comprising a hydrogen bond acceptor or a hydrogen bond donor. Such block copolymer compositions may be used, for example, as a mask for lithographic patterning as is used, for example, during various stages of semiconductor device fabrication..