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Semiconductor Device patents



      

This page is updated frequently with new Semiconductor Device-related patent applications.




Date/App# patent app List of recent Semiconductor Device-related patents
06/23/16
20160183391 
 Methods and devices for miniaturization of high density wafer based electronic 3d multi-chip modules patent thumbnailMethods and devices for miniaturization of high density wafer based electronic 3d multi-chip modules
Techniques for constructing a multi-chip module semiconductor device are provided herein. The techniques include placing electronic modules on a first surface and a second surface, with electrical connections for the electronic modules being proximate to respectively mounted surfaces, disposing a mold material on one of the mounting surfaces to substantially surround corresponding electronic modules, orienting the mounting surface without the mold material disposed thereon, relative to the mounting surface with the mold material disposed thereon to cause the mold material to substantially surround each electronic module while maintaining a minimum distance between the electronic modules mounted on each mounting surface.

06/23/16
20160182041 
 Semiconductor device and semiconductor system patent thumbnailSemiconductor device and semiconductor system
According to one embodiment, a semiconductor device includes: a voltage line to which a first voltage is applied; a first circuit configured to operate by using the first voltage; and a second circuit configured to control a connection between the voltage line and the first circuit. The second circuit includes: at least one first switch circuit configured to connect the first circuit and the voltage line based on a first control signal; and a second switch circuit including a plurality of switch sections configured to connect the first circuit and the voltage line based on a plurality of second control signals different from the first control signal..

06/23/16
20160182035 
 Semiconductor device patent thumbnailSemiconductor device
A driver ic (integrated circuit) includes a power supply terminal; an output terminal to be coupled to a load element; a connection node on a current path between the power supply terminal and the output terminal; a substrate resistance, having one end coupled to the connection node; an output transistor including a gate, wherein the output transistor is coupled in series with the substrate resistance through the connection node; a resistance, having one end coupled to an other end of the substrate resistance; and a voltage detecting circuit configured to detect a voltage depending on a voltage between the one end of the substrate resistance and the other end of the substrate resistance, and to output an output signal, which is as an output of the voltage detecting circuit, to the gate of the output transistor.. .

06/23/16
20160182032 
 Semiconductor device patent thumbnailSemiconductor device
First and second external terminals are connected to high-voltage and low-voltage terminals, respectively, of a direct-current voltage source circuit in which first and second direct-current voltage sources are connected in series. A third external terminal is connected to a connecting point between the first and second direct-current voltage sources.

06/23/16
20160182025 
 Semiconductor device and semiconductor system including the same patent thumbnailSemiconductor device and semiconductor system including the same
A semiconductor device may include a control signal generation block configured to shift a level of a trimming signal and generate a selection control signal, and shift a level of a first enable signal and generate a driving control signal, when an internal voltage is raised to a level greater than a sensing reference voltage after an initialization period is ended. The semiconductor device may include an internal voltage generation block configured to select one of a plurality of trimming division voltages as a selected reference voltage in response to the selection control signal, and drive the internal voltage by comparing levels of the selected reference voltage and the internal voltage in response to the driving control signal..

06/23/16
20160181992 
 Magnetically coupled load modulation patent thumbnailMagnetically coupled load modulation
A method, packaged semiconductor device, and system for controlling a secondary amplifier output current based on an input signal received from an amplifier input, converting electrical energy to magnetic energy at a secondary amplifier output inductor, coupling the magnetic energy from the secondary amplifier output inductor to a primary amplifier output inductor, converting the coupled magnetic energy to induced electrical energy at the primary amplifier output inductor, combining the induced electrical energy with output electrical energy from a primary amplifier gain element, and applying a combined electrical energy including the output electrical energy and the induced electrical energy to a primary amplifier load are provided.. .

06/23/16
20160181792 
 Semiconductor device and current limiting method patent thumbnailSemiconductor device and current limiting method
A semiconductor device, including a main transistor configured to supply power from a power source to a load, and a current limiting device including a control transistor. The current limiting device is configured to detect that the current flowing from the main transistor is an overcurrent, and to limit the current upon determining that the current is equal to or greater than a current limit value, and an operating voltage of the control transistor is equal to or greater than a current limiting activation voltage.

06/23/16
20160181556 
 Semiconductor device,  manufacturing the same, and electronic apparatus patent thumbnailSemiconductor device, manufacturing the same, and electronic apparatus
A semiconductor device includes: a gate electrode; an organic semiconductor film forming a channel; and a pair of source-drain electrodes formed on the organic semiconductor film, the pair of source-drain electrodes each including a connection layer, a buffer layer, and a wiring layer that are laminated in order.. .

06/23/16
20160181513 
 Semiconductor structures and devices and methods of forming semiconductor structures and magnetic memory cells patent thumbnailSemiconductor structures and devices and methods of forming semiconductor structures and magnetic memory cells
A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous region is proximate to the magnetic region and is formed from a precursor trap material comprising at least one attracter species having at least one trap site and a chemical affinity for the diffusive species.

06/23/16
20160181511 
 Semiconductor devices and methods of fabricating the same patent thumbnailSemiconductor devices and methods of fabricating the same
Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires.

06/23/16
20160181510 

Semiconductor device and fabricating the same


A semiconductor device includes a magnetic tunnel junction (mtj) element, an electrode layer pattern formed over the mtj element, a protective layer for protecting the mtj element and the electrode layer pattern, wherein the protective layer is arranged to expose a first area of the electrode layer pattern, a first insulation layer formed over the protective layer and arranged to form a first hole exposing the first area of the electrode layer pattern, a second insulation layer formed over the first insulation layer and arranged to form a second hole over the first hole, wherein the second hole has a larger width than the first hole, and an overhang pattern protruding from a sidewall of the first hole and suitable for preventing the protective layer on a sidewall of the mtj element.. .

06/23/16
20160181445 

Silicon photonics integration method and structure


Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device.

06/23/16
20160181442 

Semiconductor device and manufacturing same


A semiconductor device includes: a first conductive type semiconductor device; a first conductive type drift region formed by epitaxial growth on the semiconductor substrate; a plurality of first conductive type vertical implantation regions formed by multistage ion implantation in the drift region, the vertical implantation regions having a prescribed vertical implantation width and a prescribed drift region width; an anode electrode disposed on the front surface of the drift region opposite to the semiconductor substrate, the anode electrode being in schottky contact with the drift region and in ohmic contact with the first conductive type vertical implantation regions; and a cathode electrode disposed on the rear surface of the semiconductor substrate opposite to the drift region, the cathode electrode being in ohmic contact with the semiconductor substrate.. .

06/23/16
20160181441 

Semiconductor device and manufacturing a semiconductor device


A semiconductor device includes a semiconductor material having a bandgap larger than 2 ev and less than 10 ev, and a contact layer in contact with the semiconductor material. The contact layer includes a metal nitride.

06/23/16
20160181438 

Semiconductor device


A semiconductor device is provided with a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, and side and top surfaces of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the gate insulating film and faces the top and side surfaces a of the second oxide semiconductor film. A thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and the difference is larger than or equal to 20 nm..

06/23/16
20160181434 

Semiconductor device and manufacturing semiconductor device


A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed.

06/23/16
20160181432 

Semiconductor device


Reducing hydrogen concentration in a channel formation region of an oxide semiconductor is important in stabilizing threshold voltage of a transistor including an oxide semiconductor and improving reliability. Hence, hydrogen is attracted from the oxide semiconductor and trapped in a region of an insulating film which overlaps with a source region and a drain region of the oxide semiconductor.

06/23/16
20160181431 

Manufacturing crystalline semiconductor film and semiconductor device


A change in electrical characteristics is inhibited in a semiconductor device using a transistor including an oxide semiconductor having crystallinity, and the reliability of the semiconductor device is improved. Further, a semiconductor device with low power consumption is provided.

06/23/16
20160181429 

Finfet with dual workfunction gate structure


A semiconductor device includes a substrate having a fin structure, the fin structure having a height in a substantially perpendicular direction to the substrate, and having consecutive upper and lower portions along the height, the lower portion being closer to the substrate than the upper portion. The semiconductor device further includes a gate structure wrapping around a portion of the fin structure, the gate structure having a gate dielectric layer disposed around the fin structure, and a gate electrode layer disposed over the gate dielectric layer.

06/23/16
20160181427 

Semiconductor device


A semiconductor device includes an isolation feature in a substrate. The semiconductor device further includes a first source/drain feature in the substrate, wherein a first side of the first source/drain feature contacts the isolation feature, and the first source/drain feature exposes a portion of the isolation feature below a top surface of the substrate.

06/23/16
20160181426 

Methods of forming epi semiconductor material in a trench formed above a semiconductor device and the resulting devices


A device includes a gate structure having an axial length that is positioned above an active region of a semiconductor substrate and includes a first gate structure portion positioned above the active region and second gate structure portions positioned above an isolation region formed in the semiconductor substrate. An etch stop layer is positioned on the gate structure and covers sidewall surfaces of the second gate structure portions but does not cover any sidewall surfaces of the first gate structure portion.

06/23/16
20160181425 

Method for manufacturing semiconductor device


There is provided a method for manufacturing a semiconductor device including a substrate including a plurality of active regions, a plurality of gate electrodes extending in a first direction to intersect a portion of the plurality of active regions, and including first and second gate electrodes disposed to be adjacent to each other in the first direction, a gate isolation portion disposed between the first and second gate electrodes. The gate isolation portion includes a first layer and second layers disposed on both ends of the first layer in a second direction perpendicular to the first direction..

06/23/16
20160181421 

Semiconductor devices and related fabrication methods


semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body region of semiconductor material having a first conductivity type, a source region of semiconductor material having a second conductivity type within the body region, a junction isolation region of semiconductor material having the second conductivity type, a drain region of semiconductor material having the second conductivity type, and first and second drift regions of semiconductor material having the second conductivity type.

06/23/16
20160181419 

Semiconductor device


The present examples relate to a semiconductor device used in an electric device or high voltage device. The present examples improve rsp by minimizing drift region resistance by satisfying breakdown voltage by improving the structure of a drift region through which current flows in a semiconductor device to provide optimal results.

06/23/16
20160181418 

Semiconductor device and fabrication method thereof


A semiconductor device includes a well region of a first conductivity type, having a first depth, formed in a substrate. A source contact region of a second conductivity type is formed in the well region.

06/23/16
20160181416 

Charge-compensation device


A charge-compensation semiconductor device includes a semiconductor body having a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, a peripheral area arranged between the active area and the lateral edge, a drift region, first compensation regions forming respective first pn-junctions with the drift region, and second compensation regions extending from the first surface into the drift region and forming respective second pn-junctions with the drift region. The first compensation regions form in the active area a lattice comprising a first base vector having a first length.

06/23/16
20160181415 

Wide band gap semiconductor device


A semiconductor substrate having a main surface and made of a wide band gap semiconductor is provided, the semiconductor substrate including a device region formed in the semiconductor substrate, and a peripheral region formed to surround the device region. In the peripheral region, the semiconductor substrate includes a first semiconductor region having a first conductivity type, and a second semiconductor region formed on the first semiconductor region and having the main surface, the second semiconductor region having a second conductivity type different from the first conductivity type.

06/23/16
20160181414 

Semiconductor device including fin- fet and manufacturing method thereof


A semiconductor device includes a first fin structure for a first fin field effect transistor (fet). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer.

06/23/16
20160181413 

Semiconductor device


A semiconductor device is provided with an n−-type drift layer, a n+-type diffusion well region provided on a surface part of the n−-type drift layer, a p-type channel well region, an n+-type diffusion well region, a gate insulating film, a gate electrode laminated on the gate insulating film, a drain trench, a field plate provided in the drain trench with a silicon oxide film and an insulating film interposed therebetween and a field plate electrode formed on the field plate. The field plate is tapered toward a base part of the drain trench.

06/23/16
20160181412 

Semiconductor devices and methods for fabricating the same


Provided are a semiconductor device configured to block a physical diffusion path by forming an oxide layer between barrier layers to prevent impurities from being diffused through the physical diffusion path between the barrier layers, and a method for fabricating the semiconductor device. The semiconductor device includes a gate insulation layer formed on a substrate, a first barrier layer formed on the gate insulation layer, an oxide layer formed on the first barrier layer, the oxide layer including an oxide formed by oxidizing a material included in the first barrier layer, a second barrier layer formed on the oxide layer, a gate electrode formed on the second barrier layer, and source/drains disposed at opposite sides of the gate electrode in the substrate..

06/23/16
20160181411 

Semiconductor device


A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction).

06/23/16
20160181410 

Semiconductor device with low-conducting field-controlling element


A semiconductor device including a low conducting field-controlling element is provided. The device can include a semiconductor including an active region (e.g., a channel), and a set of contacts to the active region.

06/23/16
20160181409 

Bidirectional power switching with bipolar conduction and with two control terminals gated by two merged transistors


Power semiconductor devices, methods, and systems, in which additional switches are added on both surfaces of a two-sided power device with bidirectional conduction. The additional switches are preferably vertical trench mos transistors, and permit the emitter-base junction on either surface to be shunted easily..

06/23/16
20160181408 

Semiconductor device with stripe-shaped trench gate structures and gate connector structure


A semiconductor device includes a transistor cell with a stripe-shaped trench gate structure that extends from a first surface into a semiconductor body. A gate connector structure at a distance to the first surface is electrically connected to a gate electrode in the trench gate structure.

06/23/16
20160181406 

Semiconductor device and manufacturing the same


An object is to provide a semiconductor device including an oxynitride semiconductor whose carrier density is controlled. By introducing controlled nitrogen into an oxide semiconductor layer, a transistor in which an oxynitride semiconductor having desired carrier density and on characteristics is used for a channel can be manufactured.

06/23/16
20160181405 

Method for manufacturing semiconductor device


It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity.

06/23/16
20160181402 

Method of manufacturing a semiconductor device with lateral fet cells and field plates


A method of manufacturing a semiconductor device includes providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins. A first mask is provided that covers a first area including first stripe sections of the dielectric stripe structures and first fin sections of the semiconductor fins.

06/23/16
20160181399 

Methods for fabricating semiconductor devices


Methods of forming a semiconductor device are provided. The methods may include forming a gate structure on a substrate, forming a first sacrificial pattern and a second sacrificial pattern on opposing sides of the gate structure respectively and partially replacing the first sacrificial pattern with a first insulating pattern such that a portion of the first sacrificial pattern remains in the first insulating pattern and replacing the second sacrificial pattern with a second insulating pattern.

06/23/16
20160181397 

Method to improve reliability of high-k metal gate stacks


A method of fabricating a gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over an area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; annealing the replacement gate structure in an ambient atmosphere containing hydrogen; and depositing a gap fill layer.. .

06/23/16
20160181391 

Diode structures with controlled injection efficiency for fast switching


This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface.

06/23/16
20160181390 

Semiconductor devices having low contact resistance and low current leakage


The present disclosure is directed to a device and method for reducing the resistance of the middle of the line in a transistor. The transistor has electrical contacts formed above, and electrically connected to, the gate, drain and source.

06/23/16
20160181388 

Method for manufacturing a semiconductor device comprising a metal nitride layer and semiconductor device


A method of manufacturing a semiconductor device includes introducing nitrogen into a metal layer or into a metal nitride layer, the metal layer or metal nitride layer being formed in contact with a semiconductor material. A semiconductor device includes a semiconductor material and a metal nitride layer in contact with the semiconductor material.

06/23/16
20160181386 

Semiconductor device with an interconnect structure and forming the same


A semiconductor device structure and method for forming the semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate electrode formed on the substrate.

06/23/16
20160181385 

Semiconductor devices having buried contact structures and methods of manufacturing the same


Semiconductor devices are provided including a substrate defining a gate trench. A buried gate structure is provided in the gate trench and at least fills the gate trench.

06/23/16
20160181383 

Semiconductor device and manufacturing method thereof


The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, an epitaxial structure, and a recess.

06/23/16
20160181380 

Semiconductor device metal-insulator-semiconductor contacts with interface layers and methods for forming the same


Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided.

06/23/16
20160181379 

Semiconductor device and manufacturing the same


A semiconductor device includes: a semiconductor substrate; a plurality of trench gate electrodes that have a stripe shape in plan view and are located in parallel with each other at an interval; a gate insulating film located on surfaces of the trench gate electrodes; a first impurity layer located in an upper layer portion of the semiconductor substrate; a second impurity layer that is selectively located in a surface of the first impurity layer and is in contact with the gate insulating film; an interlayer insulating film that is located so as to cover upper portions of the trench gate electrodes and an upper portion of the second impurity layer, projects on the semiconductor substrate, and has a stripe shape in plan view; and a planarized buried film of metal that is buried in portions between projecting portions of the interlayer insulating film on the semiconductor substrate.. .

06/23/16
20160181377 

Semiconductor device having dual work function gate structure, fabricating the same, memory cell having the same, and electronic device having the same


A semiconductor device includes a body including a first junction region; a pillar positioned over the body, and including a vertical channel region and a second junction region over the vertical channel region; a gate trench exposing side surfaces of the pillar; a gate dielectric layer covering the gate trench; and a gate electrode embedded in the gate trench, with the gate dielectric layer interposed therebetween. The gate electrode includes a first work function liner overlapping with the vertical channel region, and including an aluminum-containing metal nitride; a second work function liner overlapping with the second junction region, and including a silicon-containing non-metal material; and an air gap positioned between the second work function liner and the second junction region..

06/23/16
20160181376 

Silicon carbide semiconductor device and manufacturing a silicon carbide semiconductor device


An infrared ray absorbing film is selectively formed on a surface of a silicon carbide semiconductor substrate in a predetermined area. An aluminum film and a nickel film are sequentially formed in this order on the silicon carbide semiconductor substrate in an area excluding the predetermined area in which the infrared ray absorbing film is formed.

06/23/16
20160181375 

Silicon carbide semiconductor substrate, manufacturing silicon carbide semiconductor substrate, and manufacturing silicon carbide semiconductor device


A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; and an epitaxial layer formed on the main surface. The silicon carbide semiconductor substrate has an amount of warpage of not less than −100 μm and not more than 100 μm when a substrate temperature is a room temperature and has an amount of warpage of not less than −1.5 mm and not more than 1.5 mm when the substrate temperature is 400° c..

06/23/16
20160181374 

Silicon carbide semiconductor device and manufacturing the same


A silicon carbide semiconductor device includes a silicon carbide substrate and a gate electrode. The silicon carbide substrate includes a first source region and a second source region, a first body region, a second body region, a first drift region, a second drift region, a third drift region, and a first connection region.

06/23/16
20160181373 

Silicon carbide semiconductor device and manufacturing the same


A silicon carbide semiconductor device includes a silicon carbide layer and a gate insulating layer. The silicon carbide layer has a main surface.

06/23/16
20160181372 

Silicon carbide semiconductor device and manufacturing same


A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type.

06/23/16
20160181371 

Semiconductor device and manufacturing the same


The semiconductor device includes: a substrate, an n-type drift region formed on a main surface of the substrate; a p-type well region, an n-type drain region and an n-type source region each formed in the drift region to extend from a second main surface of the drift region opposite to the first main surface of the drift region in contact with the substrate in a direction perpendicular to the second main surface; a gate groove extending from the second main surface in the perpendicular direction and penetrating the source region and the well region in a direction parallel to the first main surface of the substrate; and a gate electrode formed on a surface of the gate groove with a gate insulating film interposed therebetween, wherein the drift region has a higher impurity concentration than the substrate, and the well region extends to the inside of the substrate.. .

06/23/16
20160181368 

Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same


Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon arsenic layer have an arsenic doping level of greater than 5 e+20 arsenic atoms per cubic centimeter.

06/23/16
20160181366 

Field effect transistors including fin structures with different doped regions and semiconductor devices including the same


Field effect transistors are provided. According to the field effect transistor, a source region and a drain region are provided on a substrate and a fin portion is provided to protrude from the substrate.

06/23/16
20160181365 

Semiconductor devices having channel regions with non-uniform edge


A semiconductor device may include a drift region having a first conductivity type, a source region having the first conductivity type, and a well region having a second conductivity type disposed adjacent to the drift region and adjacent to the source region. The well region may include a channel region that has the second conductivity type disposed adjacent to the source region and proximal to a surface of the semiconductor device cell.

06/23/16
20160181362 

Silicide regions in vertical gate all around (vgaa) devices and methods of forming same


An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel region in the nanowire over the source/drain region. The source/drain region further extends into the semiconductor substrate past edges of the nanowire.

06/23/16
20160181361 

Semiconductor devices with cavities


A semiconductor device comprises a first semiconductor wafer including a cavity formed in the first semiconductor die. A second semiconductor die is bonded to the first semiconductor die over the cavity.

06/23/16
20160181357 

Semiconductor device


In a semiconductor device, a p+ back gate region (pbg) is arranged in a main surface (si) between first and second portions (p1, p2) of an n+ source region (sr), and arranged on a side closer to an n+ drain region (dr) with respect to the n+ source region (sr). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained..

06/23/16
20160181356 

Semiconductor device


A semiconductor device includes a first conductivity type semiconductor layer that includes a wide bandgap semiconductor and a surface. A trench, including a side wall and a bottom wall, is formed in the semiconductor layer surface, and a schottky electrode is connected to the surface.

06/23/16
20160181354 

Semiconductor device


A semiconductor device in which the concentration of an electric field is suppressed in a region overriding a drain region and a source region. A drain region is formed in a first region, a source region is formed in a second region.

06/23/16
20160181352 

Capacitor structure compatible with nanowire cmos


A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure.

06/23/16
20160181351 

Ultrahigh voltage resistor, semiconductor device, and the manufacturing method thereof


An example provides a semiconductor device including an insulator with a predetermined thickness between a well region of a semiconductor substrate and a resistor of polysilicon. The insulator has a structure that is able to withstand an ultrahigh voltage, and thereby allows the manufacture of a semiconductor device resistor that can bear an ultrahigh voltage without increasing the size of a semiconductor substrate and a semiconductor device including such a resistor.

06/23/16
20160181303 

Semiconductor device and semiconductor-device manufacturing method


It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line.

06/23/16
20160181301 

Semiconductor device and a manufacturing method thereof


A semiconductor device has a chip region including a back-side illumination type photoelectric conversion element, a mark-like appearance part, a pad electrode, and a coupling part. The mark-like appearance part includes an insulation film covering the entire side surface of a trench part formed in a semiconductor substrate.

06/23/16
20160181291 

Semiconductor device, display device, and manufacturing semiconductor device


A semiconductor device (100a) includes a first metal layer (12) including a gate electrode (12g); a gate insulating layer (14) formed on the first metal layer; an oxide semiconductor layer (16) formed on the gate insulating layer; a second metal layer (18) formed on the oxide semiconductor layer; an interlayer insulating layer (22) formed on the second metal layer; and a transparent electrode layer (te) including a transparent conductive layer (tc). The oxide semiconductor layer includes a first portion (16a) and a second portion (16b) extending while crossing an edge of the gate electrode.

06/23/16
20160181288 

Deformable electronic device and methods of providing and using deformable electronic device


Some embodiments include a method of providing an electronic device. The method includes: (i) providing a carrier substrate, (ii) providing a device substrate comprising a first side and a second side opposite the first side, the device substrate having a flexible substrate, (iii) coupling the first side of the device substrate to the carrier substrate; and (iv) after coupling the first side of the device substrate to the carrier substrate, providing two or more active sections over the second side of the device substrate, each active section of the two or more active sections being spatially separate from each other and having at least one semiconductor device.

06/23/16
20160181285 

Uniform junction formation in finfets


The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch finfet devices, using recessed source-drain (s-d) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the s-d region is formed, may be used to control the profile and dopant concentration of the junction under the channel.

06/23/16
20160181276 

Multi-orientation soi substrates for co-integration of different conductivity type semiconductor devices


A method of forming a semiconductor device that includes providing a base semiconductor substrate having a first orientation crystal plane, and forming an epitaxial oxide layer on the base semiconductor substrate. The epitaxial oxide layer has the first orientation crystal plane.

06/23/16
20160181274 

Semiconductor memory device


A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern..

06/23/16
20160181273 

Semiconductor device and manufacturing method thereof


Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-demensional vertical structure by the plasma-enhanced atomic layer deposition (peald) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced.

06/23/16
20160181271 

Methods of fabricating memory device with spaced-apart semiconductor charge storage regions


Methods of fabricating semiconductor devices, such as monolithic three-dimensional nand memory string devices, include selectively forming semiconductor material charge storage regions over first material layers exposed on a sidewall of a front side opening extending through a stack comprising an alternating plurality of first and second material layers using a difference in incubation time for the semiconductor material on the first material relative to an incubation time for the semiconductor material on the second material of the stack. In other embodiments, a silicon layer is selectively deposited on silicon nitride on a surface having at least one first portion including silicon oxide and at least one second portion including silicon nitride using a difference in an incubation time for the silicon on silicon nitride relative to an incubation time for the silicon on silicon oxide..

06/23/16
20160181259 

Vertical ferroelectric memory device and a manufacturing thereof


The disclosed technology generally relates to semiconductor devices, and more particularly to a ferroelectric memory device and a method of manufacturing and using the same. In one aspect, a vertical ferroelectric memory device includes a stack of horizontal layers formed on a semiconductor substrate, where the stack of layers includes a plurality gate electrode layers alternating with a plurality of insulating layers.

06/23/16
20160181258 

Methods of fabricating semiconductor devices


Methods of fabricating semiconductor devices include forming a first impurity region in a substrate by implanting a first impurity of a first conductivity type in a cell region and a peripheral region of the substrate to a first target depth from a top surface of the substrate; forming a second impurity region in the cell region and the peripheral region by implanting a second impurity of the first conductivity type into the cell region and the peripheral region to a second target depth that is smaller than the first depth from the top surface of the substrate; forming a cell transistor with a channel in the cell region, wherein the first impurity region forms the channel of the cell transistor; and forming a peripheral transistor with a channel in the peripheral region, wherein the second impurity region forms the channel of the peripheral transistor.. .

06/23/16
20160181256 

Low-drive current finfet structure for improving circuit density of ratioed logic in sram devices


A method of fabricating an sram semiconductor device includes forming first and second finfets on an upper surface of a bulk substrate. The first finfet includes a first source/drain region containing first dopants, and the second finfet includes a second source/drain region containing second dopants.

06/23/16
20160181254 

Low-drive current finfet structure for improving circuit density of ratioed logic in sram devices


A method of fabricating an sram semiconductor device includes forming first and second finfets on an upper surface of a bulk substrate. The first finfet includes a first source/drain region containing first dopants, and the second finfet includes a second source/drain region containing second dopants.

06/23/16
20160181251 

Semiconductor device


A semiconductor device includes a first memory cell including a first transistor and a first capacitor, the first transistor comprising a first gate electrode, a first source, and a first drain; a second memory cell including a second transistor and the first capacitor, the second transistor comprising a second gate electrode, a second source, and a second drain; a first word line coupled to the first gate electrode; and a second word line coupled to the second gate electrode. The first capacitor is electrically connected between the first and second transistors..

06/23/16
20160181247 

Field-isolated bulk finfet


Disclosed are isolation techniques for bulk finfets. A semiconductor device includes a semiconductor substrate with a fin structure on the semiconductor substrate.

06/23/16
20160181245 

Short channel effect suppression


A semiconductor device includes a semiconductor substrate having a first region and a second region. The first region includes a first set of fin structures, the first set of fin structures comprising a first set of epitaxial anti-punch-through features of a first conductivity type.

06/23/16
20160181244 

Short channel effect suppression


A method of fabricating a semiconductor device includes forming a plurality of isolation features on a semiconductor substrate, thereby defining a first set of semiconductor features, performing an etching process on the first set of semiconductor features such that larger semiconductor features are etched deeper than smaller semiconductor features, after the etching process, forming anti-punch-through features on surfaces of the exposed features of the first set of semiconductor features, forming a semiconductor layer over the anti-punch-through features, and forming transistors on the semiconductor layer of each of the features of the first set of semiconductor features. .

06/23/16
20160181243 

Methods of fabricating semiconductor devices including fin-shaped active regions


A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.. .

06/23/16
20160181240 

Semiconductor device and method


In an embodiment, a semiconductor device includes a silicon carbide layer comprising a lateral diode, and a group iii nitride based semiconductor device arranged on the silicon carbide layer.. .

06/23/16
20160181232 

Semiconductor module and semiconductor device


A semiconductor module includes first and second semiconductor elements connected in series, an insulating substrate, first and second metal patterns formed on a first main surface and a second main surface of the insulating substrate, and first, second, and third electrode plates. A lower surface electrode and an upper surface electrode of the first semiconductor element are bonded to the first metal pattern and the first electrode plate, respectively.

06/23/16
20160181229 

Mounting structure of semiconductor device and manufacturing the same


A semiconductor-device mounting structure includes a first semiconductor device and a plate-shaped second semiconductor device connected to the first semiconductor device. The first semiconductor device includes a flexible board, an electronic component, and a sealing resin.

06/23/16
20160181228 

Semiconductor device and manufacturing same


A semiconductor device includes a first laminated body and a second laminated body. The first laminated body includes sequentially a first element, a first wiring layer, and a first connection layer that includes a first junction electrode, on a main surface of a first substrate.

06/23/16
20160181225 

Corrosion-resistant copper bonds to aluminum


A method for fabricating a semiconductor device is disclosed. A packaged semiconductor device is provided having copper ball bonds attached to aluminum pads.

06/23/16
20160181224 

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device that includes: preparing a pair of substrates that respectively include a device structure on one primary surface or another primary surface thereof; stacking the substrates so that said one primary surfaces face each other, exposing said another surfaces to the outside, and fixing entire peripheral outer edges of the substrates that have been stacked to each other; and thereafter, plating said exposed another primary surfaces of the stacked and fixed substrates.. .

06/23/16
20160181219 

Solder joint structure for ball grid array in wafer level package


A semiconductor device package and a method for forming the same using an improved solder joint structure are disclosure. The package includes solder joints having a thinner bottom portion than a top portion.

06/23/16
20160181210 

Semiconductor device and manufacturing semiconductor device


An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip, a groove formed in a periphery of a surface of the semiconductor chip being tapered toward a rear surface of the semiconductor chip, wherein the sealing resin layer is partly disposed in the groove.. .

06/23/16
20160181205 

Discrete component backward traceability and semiconductor device forward traceability


A system is disclosed for providing backward and forward traceability by a methodology which identifies discrete components (die, substrate and/or passives) that are included in a semiconductor device. The present technology further includes a system for generating a unique identifier and marking a semiconductor device with the unique identifier enabling the semiconductor device, and the discrete components within that device, to be tracked and traced through each process and test in the production of the semiconductor device..

06/23/16
20160181199 

Semiconductor device


According to one embodiment, an integrated circuit is formed on a semiconductor chip, a regulator supplies power to the integrated circuit via the power-supply wire, a first resistor is connected between the first pad electrode and the power-supply wire on the semiconductor chip, and a second resistor is connected between the second pad electrode and the power-supply wire on the semiconductor chip and has a resistance smaller than that of the first resistor.. .

06/23/16
20160181198 

Semiconductor devices having expanded recess for bit line contact


A semiconductor device includes a first device isolation region and a second device isolation region defining a first active region, a second active region, and a third active region in a substrate, a recess region exposing an upper surface of the first active region and upper surfaces of the first and second device isolation regions, and active buffer patterns on the second and third active regions. The first active region is located between the second and third active regions, the first device isolation region is located between the first and second active regions, the second device isolation region is located between the first and third active regions.

06/23/16
20160181197 

Reliable passivation layers for semiconductor devices


Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided.

06/23/16
20160181194 

Semiconductor device


The present invention is to provide a semiconductor device in which the generation of the eddy current in a metal flat plate is reduced, and the q value of the rf circuit of the semiconductor device is improved even using the metal flat plate as a support.. .

06/23/16
20160181191 

Substrate core via structure


By now it should be appreciated that there has been provided methods for making a packaged semiconductor device (and the resultant device) including a via layer that includes a top surface and a bottom surface; a plurality of vias within the via layer, wherein the plurality of vias extend from the bottom surface to the top surface; a first via of the plurality of vias extending from the bottom surface to the top surface at a first angle; and a second via of the plurality of vias extending from the bottom surface to the top surface at a second angle.. .

06/23/16
20160181190 

Semiconductor device and making the same


A semiconductor device includes a first electronic component mounted to an upper face of a plated interconnect layer, a second electronic component mounted to a lower face of the plated interconnect layer, a first resin part covering the first electronic component on an upper side of the plated interconnect layer, and a second resin part covering the second electronic component on a lower side of the plated interconnect layer, wherein the first and second electronic components at least partially face each other across the plated interconnect layer, wherein the plated interconnect layer includes a sloping portion disposed on a sloping boundary between the first and second resin parts, and wherein an end part of the sloping portion is bent to have a face thereof exposed from the second resin part, and a lower surface of the second resin part is flush with the face of the end part.. .

06/23/16
20160181187 

Semiconductor device and lead frame


A semiconductor device includes a lead frame having terminals, a semiconductor chip electrically coupled to the terminals, and a resin part configured to encapsulate the semiconductor chip such as to expose part of the terminals, wherein a given one of the terminals includes a first lead and a second lead welded together such that an upper face of the first lead is placed against a lower face of the second lead, wherein the lower face of the second lead extends further than the upper face of the first lead toward the semiconductor chip in a longitudinal direction of the terminal, and also extends further sideways than the upper face of the first lead in a transverse direction of the terminal, and wherein an area of the lower face of the second lead is covered with the resin part, the area extending further than the upper face of the first lead.. .

06/23/16
20160181186 

Semiconductor device and production method therefor


A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50°, and the length of the stitch portion is not less than 33 μm..

06/23/16
20160181184 

Semiconductor device and its manufacturing method


The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a pad electrode formed at the uppermost layer of a plurality of wiring layers, a surface protective film having an opening over the pad electrode, a redistribution line being formed over the surface protective film and having an upper surface and a side surface, a sidewall barrier film comprising an insulating film covering the side surface and exposing the upper surface of the redistribution line, and a cap metallic film covering the upper surface of the redistribution line.

06/23/16
20160181183 

Method for preventing die pad delamination


The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a semiconductor device and a semiconductor device formed by such method. The method includes providing a leadframe having a top surface; coating said top surface of said leadframe with first and second silane coating; heating said silane coatings to form a pourous layer having a porosity of at least 10%; applying a die to said pourous layer; securing said die to said pourous layer by a die attaching compound; and after the curing of die attach material and wire bonding, a mold compound is applied through molding..

06/23/16
20160181182 

Electronic device and methods of providing and using electronic device


Some embodiments include a method of providing an electronic device. The method can comprise: providing a first device substrate; providing one or more first active sections over a second side of the first device substrate at a first device portion of the first device substrate; and after providing the first active section(s) over the second side of the first device substrate at the first device portion, folding a first perimeter portion of the first device substrate toward the first device portion at a first side of the first device substrate so that a first edge portion remains to at least partially frame the first device portion.

06/23/16
20160181180 

Packaged semiconductor device having attached chips overhanging the assembly pad


A semiconductor device (200) comprising a semiconductor chip (201) has an electrically active side (201a) and an opposite electrically inactive side (201b); the active side bordered by an edge having a first length (202a), and the inactive side bordered by a parallel edge having a second length (202b) smaller than the first length; a substrate has an assembly pad (210) bordered by a linear edge having a third length (210a) equal to or smaller than the first length; the inactive chip side attached to the pad so that the edge of the first length is parallel to the edge of the third length; the active side of the attached chip forms an overhang over the pad, when the third length is smaller than the first length.. .

06/23/16
20160181176 

Semiconductor package


The present disclosure relates to a semiconductor package. In an embodiment, the semiconductor package includes a substrate, a semiconductor device, a thermal conductive element and a molding compound.

06/23/16
20160181172 

Compositions and methods for semiconductor processing and devices formed therefrom


The present invention relates generally to the field of semiconductor devices, including solar cells, and compositions and methods for processing semiconductor devices, passivation of semiconductor surfaces, semiconductor etching and anti-reflective coatings for semiconductor devices.. .

06/23/16
20160181164 

Fin formation on an insulating layer


An approach to forming fins for a semiconductor device on a silicon-on-insulator wafer. The approach includes depositing a layer of mandrel material and etching the layer of mandrel material to form a mandrel.

06/23/16
20160181163 

Method and structure for metal gates


A semiconductor device having metal gates and methods of forming the same are disclosed. The method includes receiving a substrate, a dummy gate stack formed over the substrate, and a structure surrounding the dummy gate stack.

06/23/16
20160181160 

Method for manufacturing silicon carbide semiconductor device


When a gate insulating film is formed on a silicon carbide substrate, the silicon carbide substrate is first oxidized with an oxidation reactant gas to form the gate insulating film on the surface of the silicon carbide substrate. The silicon carbide substrate on which the gate insulating film has been formed is nitrided with a nitriding reactant gas.

06/23/16
20160181159 

Method for fabricating semiconductor device


A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.. .

06/23/16
20160181158 

Method and structure for a large-grain high-k dielectric


A method of forming a semiconductor device (100) includes depositing a metal oxide (104) over the substrate (102). The depositing includes combining a first metal and oxygen to form the metal oxide having grains and further adding a catalyst during the combining.

06/23/16
20160181154 

Semiconductor device with multi-layer metallization


One or more embodiments are related to a semiconductor device, comprising: a metallization layer comprising a plurality of portions, each of the portions having a different thickness. The metallization layer may be a final metal layer..

06/23/16
20160181152 

Semiconductor device metallization systems and methods


semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe.

06/23/16
20160181150 

Precursors of manganese and manganese-based compounds for copper diffusion barrier layers and methods of use


Semiconductor devices and methods of making semiconductor devices with a barrier layer comprising manganese nitride are described. Also described are semiconductor devices and methods of making same with a barrier layer comprising mn(n) and, optionally, an adhesion layer..

06/23/16
20160181148 

Semiconductor device and manufacturing the same


In one embodiment, a semiconductor device includes a substrate, first and second interconnects provided on the substrate to be apart from each other, and third and fourth interconnects provided on the substrate to be apart from each other. The device further includes a first pad portion connected with the first or third interconnect, and a second pad portion connected with the second or fourth interconnect, and provided to be apart from the first pad portion.

06/23/16
20160181147 

Semiconductor device and manufacturing the same


A first misfet which is a semiconductor element is formed on an soi substrate. The soi substrate includes a supporting substrate which is a base, box layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an soi layer which is a semiconductor layer formed on the box layer.

06/23/16
20160181143 

Semiconductor device with air gap and fabricating the same


A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.. .

06/23/16
20160181140 

Protective tape and manufacturing a semiconductor device using the same


A protective tape and a method for manufacturing a semiconductor device using the same capable of achieving excellent connection properties. The protective tape includes an adhesive layer, a thermoplastic resin layer and a backing material film in that order; a modulus ratio of a shear storage modulus of the adhesive layer to a shear storage modulus of the thermoplastic resin layer at an application temperature at which the protective tape is applied is 0.01 or less.

06/23/16
20160181124 

3d packages and methods for forming the same


Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure.

06/23/16
20160181109 

Semiconductor device manufacturing method


A semiconductor device manufacturing method includes forming a dielectric film on a semiconductor substrate; forming a resist pattern on the dielectric film; irradiating an ionized gas cluster to a region of the dielectric film where the resist pattern is not formed; and removing a part of the region of the dielectric film in a thickness direction thereof where the ionized gas cluster is irradiated by a wet etching. The dielectric film serves as a gate insulating film, and two regions having different thicknesses of the dielectric film are formed..

06/23/16
20160181108 

Doping of high-k dielectric oxide by wet chemical treatment


A method for fabricating a semiconductor device includes forming a first high-k (hk) dielectric layer over a substrate, performing a wet treatment process to the first hk dielectric layer. The wet treatment includes a dopant.

06/23/16
20160181104 

Method for forming a semiconductor device and a semiconductor substrate


A method for forming a semiconductor device includes incorporating chalcogen dopant atoms into a semiconductor doping region of a semiconductor substrate of a semiconductor device. The method further includes incorporating heavy metal atoms into the semiconductor doping region..

06/23/16
20160181103 

Semiconductor device including small pitch patterns


A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate.

06/23/16
20160181101 

Semiconductor device and manufacturing the same


A semiconductor device includes a plurality of line patterns including at least two continuous line repetition units having, as one of the line repetition unit, four line patterns continuously arranged in a first direction and having variable widths based on location. To form the plurality of line patterns including the at least two continuous line repetition units, a plurality of reference patterns are formed repeatedly at a uniform reference pitch on a feature layer.

06/23/16
20160181092 

Nitride spacer for protecting a fin-shaped field effect transistor (finfet) device


Approaches for protecting a semiconductor device (e.g., a fin field effect transistor device (finfet)) using a nitride spacer are provided. Specifically, a nitride spacer is formed over an oxide and a set of fins of the finfet device to mitigate damage during subsequent processing.





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