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Semiconductor Device patents



      
           
This page is updated frequently with new Semiconductor Device-related patent applications. Subscribe to the Semiconductor Device RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Device RSS RSS


Method of designing arrangement of tsv in stacked semiconductor device and designing system for arrangement of tsv in…

Automated test equipment and control method thereof

Semiconductor device and semiconductor system including the same

Date/App# patent app List of recent Semiconductor Device-related patents
09/11/14
20140258950
 Deriving effective corners for complex correlations patent thumbnailDeriving effective corners for complex correlations
Systems and methods are described for simultaneously deriving an effective x-sigma corner for multiple, different circuit and/or process metrics for a semiconductor device. The result is an effective sigma that is representative of design intent.
09/11/14
20140258949
 Method of designing arrangement of tsv in stacked semiconductor device and designing system for arrangement of tsv in stacked semiconductor device patent thumbnailMethod of designing arrangement of tsv in stacked semiconductor device and designing system for arrangement of tsv in stacked semiconductor device
A method of designing arrangement of through silicon vias (tsvs) in a stacked semiconductor device is provided the method includes: determining a plurality of tsv candidate grids representing positions, into which the tsvs are insertable, in each of a plurality of semiconductor dies stacked mutually and included in a stacked semiconductor device; creating a plurality of path graphs representing linkable signal paths for a plurality of signals transmitted through the stacked semiconductor device, respectively, based on the tsv candidate grids; determining initial tsv insertion positions corresponding to shortest signal paths for the signals based on the path graphs; and determining final tsv insertion positions by verifying the initial tsv insertion positions so that a plurality of signal networks corresponding to the shortest signal paths for the signals have routability.. .
09/11/14
20140258778
 Automated test equipment and control method thereof patent thumbnailAutomated test equipment and control method thereof
An automated test system for a semiconductor device to concurrently perform multiple device tests is provided. The system may include at least one test client, at least one test site and a test server.
09/11/14
20140258767
 Semiconductor device and semiconductor system including the same patent thumbnailSemiconductor device and semiconductor system including the same
A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to input/output a normal data synchronized with a center of a source clock, in response to data input/output commands; and a data recovery information signal input/output block configured to receive and store a data recovery information signal synchronized with an edge of the source clock and having a predetermined pattern, in response to either a command of the data input/output commands or the predetermined command upon entry to a data recovery operating mode, and to output the data recovery information signal after the passage of a predetermined time period.. .
09/11/14
20140258611
 Semiconductor device and method of operating the same patent thumbnailSemiconductor device and method of operating the same
A semiconductor device includes a memory cell array includes a plurality of memory blocks, each of the memory blocks including a plurality of pages, wherein at least one of the plurality of memory blocks functions as a first storage unit to store a plurality of page addresses associated with the plurality of pages. A second storage unit loads a page address stored in the first storage unit.
09/11/14
20140258582
 Semiconductor device with vias on a bridge connecting two buses patent thumbnailSemiconductor device with vias on a bridge connecting two buses
A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses.
09/11/14
20140257784
 System for simulating semiconductor device and related method of operation patent thumbnailSystem for simulating semiconductor device and related method of operation
A system for simulating a semiconductor device comprises a data input module configured to receive structural data of the semiconductor device comprising a first region and a second region, and a spatial discretization generating module configured to divide a space of the semiconductor device using the structural data through division of the first region into first type meshes and division of the second region into second type meshes different from the first type meshes.. .
09/11/14
20140256160
 Apparatus for manufacturing semiconductor device, method of manufacturing semiconductor device, and recording medium patent thumbnailApparatus for manufacturing semiconductor device, method of manufacturing semiconductor device, and recording medium
An apparatus for manufacturing semiconductor devices is provided with a processing liquid supply part for supplying processing liquid into a processing chamber which houses a substrate, a heater part for heating the processing liquid in the processing chamber, and a substrate support part which is provided in the processing chamber and supports the substrate.. .
09/11/14
20140256159
 Cvd precursors patent thumbnailCvd precursors
A method of producing silicon containing thin films by the thermal polymerization of a reactive gas mixture bisaminosilacyclobutane and source gas selected from a nitrogen providing gas, an oxygen providing gas and mixtures thereof. The films deposited may be silicon nitride, silicon carbonitride, silicon dioxide or carbon doped silicon dioxide.
09/11/14
20140256158
 Imprint mask, method for manufacturing the same, and method for manufacturing semiconductor device patent thumbnailImprint mask, method for manufacturing the same, and method for manufacturing semiconductor device
According to one embodiment, an imprint mask includes a quartz plate. The quartz plate has a plurality of concave sections formed in part of an upper surface on the quartz plate, and impurities are contained in a portion between the concave sections in the quartz plate..
09/11/14
20140256156
Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
A method of manufacturing a semiconductor device, includes treating a surface of an insulating film formed on a substrate by supplying a first precursor including a predetermined element and a halogen group to the substrate; and forming a thin film including the predetermined element on the treated surface of the insulating film by performing a cycle a predetermined number of times, the cycle comprising: supplying a second precursor including the predetermined element and the halogen group to the substrate; and supplying a third precursor to the substrate.. .
09/11/14
20140256152
Substrate processing apparatus, substrate processing method, method of manufacturing semiconductor device and recording medium
A substrate processing apparatus comprising: a processing chamber that can accommodate a plurality of substrates, the interior of which is divided into a plurality of zones; a gas supply system that supplies a first reactive gas, a second reactive gas, and an inert gas to each of the plurality of zones; and an exhaust system for removing the gas from the zones. A thin film is formed on the substrates in the zones by repeatedly executing a plurality of steps in relation to the zones, these steps include the following: a first reactive gas supply step; a first purge step; a second reactive gas supply step; and a second purge step.
09/11/14
20140256144
Semiconductor fin formation method and mask set
A mask set and method for forming finfet semiconductor devices provides a complementary set of fin-cut masks that are used in dpt (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks..
09/11/14
20140256141
Methods for fabricating integrated circuits utilizing silicon nitride layers
A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (pecvd) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval.
09/11/14
20140256138
Method and equipment for removing photoresist residue after dry etch
A method for removing photoresist residue includes etching a photoresist layer disposed over a front side of a semiconductor substrate during fabrication of a semiconductor device, and exposing at least one of the front side and the back side of the semiconductor substrate to an atmosphere comprising active oxygen. The method further includes cleaning at least one of the front side and the back side of the semiconductor substrate with a cleaning fluid..
09/11/14
20140256134
Method and apparatus for improving cmp planarity
Provided is a method of planarizing a semiconductor device. A dielectric layer is formed over a substrate.
09/11/14
20140256125
Semiconductor device and method for fabricating the same
A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer.. .
09/11/14
20140256116
Semiconductor device and manufacturing method thereof
There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly w, a material film containing mainly al, and a material film containing mainly ti to reduce a wiring resistance.
09/11/14
20140256113
Semiconductor device and method for forming the same
A method includes forming a recess in a substrate and filling a dielectric layer in the recess. The method further includes forming a capping layer over the substrate and the dielectric layer.
09/11/14
20140256112
Semiconductor devices and methods of fabricating the same
Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate.
09/11/14
20140256109
Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device is disclosed. In one aspect the method includes forming a gate stack over a substrate.
09/11/14
20140256107
High gate density devices and methods
A method of forming a semiconductor device includes providing a semiconductor substrate and forming a plurality of dummy gate structures in the substrate. The method further includes forming sidewall spacers on sidewalls of the dummy gate structures and forming a plurality of epitaxial growth regions between the dummy gate structures.
09/11/14
20140256106
Prevention of fin erosion for semiconductor devices
A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer.
09/11/14
20140256097
Methods for forming integrated circuit systems employing fluorine doping
A method for forming a semiconductor device is provided which includes providing a gate structure in an active region of a semiconductor substrate, wherein the gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to the gate structure and, thereafter, performing a fluorine implantation process. Also a method for forming a cmos integrated circuit structure is provided which includes providing a semiconductor substrate with a first active region and a second active region, forming a first gate structure in the first active region and a second gate structure in the second active region, wherein each gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to each of the first and second gate structures and, thereafter, performing a fluorine implantation process..
09/11/14
20140256096
Semiconductor device and method for manufacturing semiconductor device
A semiconductor device is provided, which includes a single crystal semiconductor layer formed over an insulating surface and having a source region, a drain region, and a channel formation region, a gate insulating film covering the single crystal semiconductor layer and a gate electrode overlapping with the channel formation region with the gate insulating film interposed therebetween. In the semiconductor device, at least the drain region of the source and drain regions includes a first impurity region adjacent to the channel formation region and a second impurity region adjacent to the first impurity region.
09/11/14
20140256095
Method for manufacturing semiconductor device
To provide a manufacturing method of a highly reliable tft, by which a more refined pattern can be formed through a process using four or three masks, and a semiconductor device. A channel-etched bottom gate tft structure is adopted in which a photoresist is selectively exposed to light by rear surface exposure utilizing a gate wiring to form a desirably patterned photoresist, and further, a halftone mask or a gray-tone mask is used as a multi-tone mask.
09/11/14
20140256094
Finfets and methods for forming the same
Methods for forming a semiconductor device and a finfet device are disclosed. A method comprises forming a dummy gate electrode layer over a substrate, the dummy gate electrode layer having a first height, forming a first etch stop layer on the dummy gate electrode layer, forming a first hard mask layer on the first etch stop layer, and patterning the first hard mask layer.
09/11/14
20140256093
Finfet device structure and methods of making same
Embodiments of the present disclosure are a method of forming a semiconductor device and a method of forming a finfet device. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first hardmask layer on the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width.
09/11/14
20140256091
Methods for bonding a die and a substrate
Embodiments of methods for forming a semiconductor device that includes a die and a substrate include pressing together the die and the substrate such that a first gold layer and one or more additional material layers are between the die and the substrate, and performing a bonding operation to form a die attach layer between the die and the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold.
09/11/14
20140256089
Stacked semiconductor packages
Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device..
09/11/14
20140256088
Semiconductor device having chip mounted on an interposer
A semiconductor device 100 includes: a first semiconductor package 10; a first interposer 12 having an upper surface on which the first semiconductor package 10 is mounted; a first molding resin 14 that is provided on the upper surface of the first interposer 12 and seals the first semiconductor package 10; a second semiconductor package 20 mounted on an upper surface of the first molding resin 14; a second interposer 22 on which the second semiconductor package 20 is mounted by flip chip bonding; and a second molding resin 40 that is provided on the upper surface of the first interposer 12 and seals the first molding resin 14, the second semiconductor package 20, and the second interposer 22. The second semiconductor package 20 is mounted, with a surface thereof opposite to another surface mounted on the second interposer 22 faced down, on the upper surface of the first molding resin 14 via an adhesive 30..
09/11/14
20140256086
Manufacturing method of semiconductor device
A transistor with superior electric characteristics is manufactured. An oxide insulating film is formed over a substrate, an oxide semiconductor film is formed over the oxide insulating film, heat treatment is then conducted at a temperature at which hydrogen contained in the oxide semiconductor film is desorbed and part of oxygen contained in the oxide insulating film is desorbed, then the heated oxide semiconductor film is etched into a predetermined shape to form an island-shaped oxide semiconductor film, a pair of electrodes is formed over the island-shaped oxide semiconductor film, a gate insulating film is formed over the pair of electrodes and the island-shaped oxide semiconductor film, and a gate electrode is formed over the gate insulating film..
09/11/14
20140256080
Semiconductor device pn junction fabrication using optical processing of amorphous semiconductor material
Systems and methods for semiconductor device pn junction fabrication are provided. In one embodiment, a method for fabricating an electrical device having a p-n junction comprises: depositing a layer of amorphous semiconductor material onto a crystalline semiconductor base, wherein the crystalline semiconductor base comprises a crystalline phase of a same semiconductor as the amorphous layer; and growing the layer of amorphous semiconductor material into a layer of crystalline semiconductor material that is epitaxially matched to the lattice structure of the crystalline semiconductor base by applying an optical energy that penetrates at least the amorphous semiconductor material..
09/11/14
20140255717
Sintered silver joints via controlled topography of electronic packaging subcomponents
Disclosed are sintered silver bonded electronic package subcomponents and methods for making the same. Embodiments of the sintered silver bonded epss include topography modification of one or more metal surfaces of semiconductor devices bonded together by the sintered silver joint.
09/11/14
20140254620
High-concentration active doping in semiconductors and semiconductor devices produced by such doping
In a method of forming a photonic device, a first silicon electrode is formed, and then a germanium active layer is formed on the first silicon electrode while including n-type dopant atoms in the germanium layer, during formation of the layer, to produce a background electrical dopant concentration that is greater than an intrinsic dopant concentration of germanium. A second silicon electrode is then formed on a surface of the germanium active layer.
09/11/14
20140254256
Vertical type semiconductor device, fabrication method thereof and operation method thereof
A vertical type semiconductor device and a fabrication method thereof are provided. The vertical type semiconductor device includes a pillar structure having a stacking structure of a conductive layer and a data storage material and formed on a common source region, and a gate electrode formed to surround the data storage material of the pillar structure..
09/11/14
20140254241
Semiconductor device and information reading method
A semiconductor device includes; a memory device configured to take a plurality of resistance states that are distinguishable from one another; a bias application section configured to apply, in a bias application period, a bias signal to the memory device; and a determination section configured to determine a resistance state of the memory device on the basis of a detection signal, in which the detection signal is generated in the memory device to which the bias signal is applied. The bias application section sets a length of the bias application period in accordance with a resistance value of the memory device, when the resistance state determined by the determination section is predetermined one of the resistance states..
09/11/14
20140254116
Semiconductor device
A control terminal of an intelligent power module has a structure in which it is possible to reduce the area used exclusively by the module. An insulating circuit substrate on which power semiconductor elements are mounted, and a printed substrate having a control circuit, are arranged in a tiered structure, and a structure is adopted in which control terminals through which to input control signals into a control substrate, as well as being formed into a linear shape, are caused to stand upright by being inserted into control terminal insertion holes provided in a case bottom portion of a module and the through holes of the printed substrate..
09/11/14
20140253533
Driving method of semiconductor device
A highly reliable semiconductor device and a method for driving the highly reliable semiconductor device is provided. In a semiconductor device in which a light-transmitting storage capacitor having a mos capacitor structure is provided and a light-transmitting semiconductor film functioning as one electrode of the storage capacitor is electrically connected to a capacitor line, a shift of a threshold voltage of the storage capacitor in the positive direction is suppressed in a period during which an image is not displayed.
09/11/14
20140253191
Semiconductor device and wireless communication device
A semiconductor device according to the present invention includes two diodes connected in parallel between power supplies, and a resistor circuit and a capacitance element connected in parallel between one power supply and each of the two diodes, and outputs a comparison result between voltages outputted from the two resistor circuits as a reset signal.. .
09/11/14
20140253182
Drive control apparatus
A drive control apparatus for a semiconductor device having a diode and a transistor includes: a current detection device of a current flowing through the diode; and a control device, which applies a gate drive voltage to the semiconductor device when an on-instruction signal is input. The control device compares the current detection signal with a current threshold value during a first period, in which the on-instruction signal is input, after a second period has elapsed from gate drive voltage application time, or gate drive voltage shut-off time.
09/11/14
20140253178
Semiconductor device including clock signal generation unit
A semiconductor device for stably generating a clock signal from a strobe signal includes a processor, a clock signal generation unit receiving a first strobe signal and a second strobe signal to generate the clock signal, and a data reception unit receiving at least one data signal to provide the received data signal to the processor. The clock signal generation unit may comprise a strobe comparator comparing a voltage of a first input terminal with that of a second input terminal to output logic high or logic low, a first switch selectively connecting one of a first and a second signal line to the first input terminal, a second switch selectively connecting one of the second signal line and a reference line to the second input terminal, and a voltage stabilizing circuit pulling up/down at least one of a voltage of the first and the second signal line..
09/11/14
20140253163
Inspection probe and an ic socket with the same
An inspection probe 16ai is formed by subjecting a thin sheet material made of a copper alloy to press working. The inspection probe 16ai includes: a device side plunger 16a having a contact point which selectively comes into contact with an electrode portion dvb of a semiconductor device dv; a board side plunger 16b having a contact point which selectively comes into contact with a contact pad of a printed wiring board 18; a spring portion 16d which biases the device side plunger 16a and the board side plunger 16b in a direction away from each other; and a cylindrical support stem 16c being disposed inside the spring portion 16d, making the spring portion 16d slidable thereon, and being configured to retain straight advancing property of the spring portion 16d..
09/11/14
20140253137
Test pattern design for semiconductor devices and method of utilizing thereof
Methods and systems for the detection of defects in semiconductors, semiconductor devices, or substrates are provided. Semiconductors, semiconductor devices or substrates having novel test patterns and or designs are also provided.
09/11/14
20140253099
Semiconductor device on device interface board and test system using the same
A semiconductor device, which is mounted on a device interface board to interface an electrical measuring signal between automated test equipment (ate) and a device under test (dut), includes an ac test unit, a dc test unit, a first input/output (i/o) interface unit, and a second i/o interface unit. The ac test unit tests an ac characteristic of the dut.
09/11/14
20140252971
Method of manufacturing a semiconductor device
An electromotive force generated by electromagnetic induction is rectified and shaped by using primary coils formed on a check substrate and secondary coils formed on an array substrate, whereby a power source voltage and a driving signal are supplied to circuits or circuit elements on a tft substrate so as to be driven.. .
09/11/14
20140252658
Semiconductor device
A semiconductor device has an fet, a mounting member, an output matching circuit board, a relay board, and first and second bonding wire. The fet has plural cell region arranged dispersedly and plural drain terminal electrodes connected to each cell region.
09/11/14
20140252657
Package alignment structure and method of forming same
An embodiment is a semiconductor device comprising a first bond pad on a first substrate, the first bond pad having a first center line through a center of the first bond pad and orthogonal to a top surface of the first substrate, and a first conductive connector on a second substrate, the first conductive connector having a second center line through a center of the first conductive connector and orthogonal to a top surface of the second substrate, the second substrate over the first substrate with the top surface of the first substrate facing the top surface of the second substrate. The semiconductor device further comprises a first alignment component adjacent the first bond pad on the first substrate, the first alignment component configured to align the first center line with the second center line..
09/11/14
20140252654
Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die
A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die.
09/11/14
20140252643
Semiconductor device manufacturing method and semiconductor device
To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented..
09/11/14
20140252641
Semiconductor device and method of forming ultra high density embedded semiconductor die package
A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die.
09/11/14
20140252638
Vertical interconnects crosstalk optimization
A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generate a plurality of interconnect patterns for a set of vertical interconnects.
09/11/14
20140252634
Packaging devices and methods for semiconductor devices
Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region.
09/11/14
20140252633
Method of fabricating an air gap using a damascene process and structure of same
The present disclosure provides a method for forming a semiconductor device. The method includes forming first conductive layer structures in a first dielectric layer on a substrate; forming a patterned photoresist layer having portions that are each disposed over a respective one of the first conductive layer structures; forming an energy removable film (erf) on the sidewalls of each of the portions; forming a second dielectric layer over the erfs, the portions of the patterned photoresist layer, and the first dielectric layer; removing the portions to leave behind a plurality of openings; filling a conductive material in the openings, the conductive material defining second conductive layer structures; forming a ceiling layer over the second conductive layer structures, the erfs, and the second dielectric layer; and applying energy to the erfs to partially remove the erfs on the sidewalls of the portions thereby forming air gaps..
09/11/14
20140252632
Semiconductor devices
A semiconductor device includes: a semiconductor chip; an extension layer extending laterally from a boundary of the semiconductor chip; a redistribution layer disposed over at least one side of the extension layer and the semiconductor chip, wherein the redistribution layer electrically couples at least one contact of the semiconductor chip to at least one contact of an interface, wherein at least a part of the interface extends laterally beyond the boundary of the semiconductor chip.. .
09/11/14
20140252624
Semiconductor devices and methods of forming same
A semiconductor device structure and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method comprising forming a first conductive line over a substrate, and conformally forming a first dielectric layer over a top surface and a sidewall of the first conductive line, the first dielectric layer having a first porosity percentage and a first carbon concentration.
09/11/14
20140252623
Semiconductor device with advanced pad structure resistant to plasma damage and method for forming the same
A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer.
09/11/14
20140252620
Material and process for copper barrier layer
A method of fabricating a semiconductor device comprises forming a first dielectric material layer on a semiconductor substrate. The first dielectric material layer is patterned to form a plurality of vias therein.
09/11/14
20140252615
Semiconductor device using carbon nanotube, and manufacturing method thereof
According to one embodiment, a semiconductor device includes a wiring, a first insulation film, an underlayer deactivation layer, an underlayer, a catalyst layer and a carbon nanotube. The first insulation film is formed on the wiring and includes a hole which exposes the wiring.
09/11/14
20140252613
Semiconductor device
The present invention reduces the occurrence of fracture in external terminal connecting sections and improves the reliability of secondary packaging of a semiconductor device. Specifically, the present invention provides a semiconductor device including a wiring board, a semiconductor chip mounted on one surface of the wiring board via a bonding member, and external electrodes formed on the other surface of the wiring board and electrically connected to the semiconductor chip.
09/11/14
20140252612
Wiring substrate for a semiconductor device having differential signal paths
A semiconductor device is provided with improved resistance to noise. Conductive planes are respectively formed over wiring layers.
09/11/14
20140252610
Packaging devices and methods of manufacture thereof
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad.
09/11/14
20140252607
Reflow film, solder bump formation method, solder joint formation method, and semiconductor device
The present invention relates to a reflow film containing a thermoplastic resin which is dissolvable in a solvent, and solder particles, wherein the solder particles are dispersed in the film, and also relates to a solder bump formation method which comprises: (a) a step of mounting the reflow film on the electrode surface side of a substrate, (b) a step of mounting and fixing a flat plate, (c) a step of heating, and (d) a step of dissolving and removing the reflow film, and herewith, a reflow film is provided which, by causing localization of the solder component on the electrodes of the substrate by self-assembly, exhibits excellent storage properties, transportability and handling properties during use, and can form solder bumps or solder joints selectively on only the electrodes.. .
09/11/14
20140252603
Semiconductor device having a conductive vias
A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.. .
09/11/14
20140252592
Pad defined contact for wafer level package
A device and fabrication techniques are described that employ wafer-level packaging techniques for fabricating semiconductor devices that include a pad defined contact. In implementations, the wafer-level package device that employs the techniques of the present disclosure includes a substrate, a passivation layer, a top metal contact pad, a thin film with a via formed therein, a redistribution layer structure configured to contact the top metal contact pad, and a dielectric layer on the thin film and the redistribution layer structure.
09/11/14
20140252591
Reinforcement structure and method for controlling warpage of chip mounted on substrate
A semiconductor device comprises a substrate, a die mounted on the substrate, a reinforcement plate bonded to the die, and an adhesive layer coupling the reinforcement plate to the die.. .
09/11/14
20140252590
Semiconductor module cooler and semiconductor module
A semiconductor module cooler for supplying a refrigerant from exterior into a water jacket and cooling a semiconductor device disposed on an outer surface of the cooler, includes a heat sink thermally connected to the semiconductor device; a first flow path extending from a refrigerant inlet and arranged with a guide portion having an inclined surface for guiding the refrigerant toward one side surface of the heat sink; a second flow path extending toward a refrigerant outlet and formed with a sidewall parallel to the other side surface of the heat sink; a flow velocity adjustment plate disposed in the second flow path and formed parallel to the other side surface of the heat sink at a distance therefrom; and a third flow path formed at a position communicating the first flow path and the second flow path. The heat sink is disposed in the third flow path..
09/11/14
20140252587
Semiconductor device, and on-board power conversion device
Provided is a semiconductor device capable of improving heat-radiating performance of a heating element. The semiconductor device of the present invention includes: a heating element (1); a heat-radiating member (2) including an element contact portion (2a) which is held surface contact with a mounting surface (1e); a first pressing member (3) and a second pressing member (4) held in contact with the heating element (1); and a fixation screw (6) for fixing the first pressing member (3) to the heat-radiating member (2) through a through hole (3c) formed through the first pressing member (3).
09/11/14
20140252586
Semiconductor devices that include a die bonded to a substrate with a gold interface layer
Embodiments of a semiconductor device include a primary portion of a substrate, a die, and a die attach layer between the die and the primary portion of the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold.
09/11/14
20140252585
Packages for semiconductor devices, packaged semiconductor devices, and methods of cooling packaged semiconductor devices
Packages for semiconductor devices, packaged semiconductor devices, and methods of cooling packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a substrate including a semiconductor device mounting region, a cover coupled to a perimeter of the substrate, and members disposed between the substrate and the cover.
09/11/14
20140252582
Lead frame and semiconductor device
A lead frame of high quality which can endure direct bonding to a semiconductor element, and a semiconductor device of high reliability which utilizing the lead frame. A lead frame includes a plurality of connected units, each unit including a pair of lead portions arranged spaced apart and opposite from each other, for mounting a semiconductor element and electrically connecting to a pair of electrodes of the semiconductor element respectively.
09/11/14
20140252578
Balanced stress assembly for semiconductor devices
An assembly for packaging one or more electronic devices in die form. The assembly includes substrates on opposite sides of the assembly, with lead frames between the electronic devices and the substrates.
09/11/14
20140252576
Semiconductor device and manufacturing method thereof
A semiconductor device has a packaging structure in which a top surface of a semiconductor chip 1 is electrically connected to a conductive member 4 through a deformation absorption layer 2a and a joining layer 3a and a bottom surface thereof is electrically connected to a conductive member 5 through a deformation absorption layer 2b and a joining layer 3b. Each of the deformation absorption layers 2a and 2b includes a nano-structure layer 7 arranged at a center of a thickness direction and plate layers 6 and 8 of two layers with the nano-structure layer 7 therebetween.
09/11/14
20140252574
Lead frame and semiconductor device
A lead frame of high quality which can endure direct bonding to the electrodes of a semiconductor element and a metal member, and a semiconductor device of high reliability which utilizing the lead frame. The lead frame includes a pair of lead frame portions which are arranged spaced apart from and opposite to each other to be electrically connected to a pair of electrodes of a semiconductor element respectively, and a pair of support bars which are arranged spaced apart from the lead portions and extending from a side of either one of the lead portions to a side of the other lead portion..
09/11/14
20140252573
Semiconductor device and method of forming embedded conductive layer for power/ground planes in fo-ewlb
A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die.
09/11/14
20140252569
High-frequency semiconductor package and high-frequency semiconductor device
Certain embodiments provide a high-frequency semiconductor package including: a base which is made of metal and is a grounding portion; a multi-layer wiring resin substrate; a first internal conductor film; and a lid. The multi-layer wiring resin substrate is provided on a top surface of the base, and has a frame shape in which a first cavity from which the top surface of the base is exposed is formed.
09/11/14
20140252567
Patterned silicon-on-plastic (sop) technology and methods of manufacturing the same
A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure attached to a wafer handle having at least one aperture that extends through the wafer handle to an exposed portion of the semiconductor stack structure.
09/11/14
20140252566
Silicon-on-dual plastic (sodp) technology and methods of manufacturing the same
A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure having a first surface and a second surface.
09/11/14
20140252563
Semiconductor device with trench structure and methods of manufacturing
A vertical semiconductor device includes a semiconductor body having semiconductor portions of semiconductor elements of the vertical semiconductor device, a front side contact on a front surface of the semiconductor body and a back side contact on an opposite back surface of the semiconductor body, and a trench structure extending from the front surface into the semiconductor body. The trench structure includes an etch stop layer lining an inner surface of the trench structure and surrounding a void within the trench structure..
09/11/14
20140252558
Methods and apparatus for wafer level packaging
A semiconductor device comprises a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may comprise a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (ppi) layer in contact with the bond pad, and a connector on the ppi layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring.
09/11/14
20140252557
Method for forming a semiconductor device and semiconductor device structures
Semiconductor device structures and methods for forming a semiconductor device are provided. In embodiments, one or more fins are provided, each of the one or more fins having a lower portion and an upper portion disposed on the lower portion.
09/11/14
20140252556
Single-mask spacer technique for semiconductor device features
A method for fabricating semiconductor features. The method includes forming a first layer over a substrate.
09/11/14
20140252552
Semiconductor dies having substrate shunts and related fabrication methods
Die structures for electronic device packages and related fabrication methods are provided. An exemplary die structure includes a substrate having a first layer of semiconductor material including a semiconductor device formed thereon, a handle layer of semiconductor material, and a buried layer of dielectric material between the handle layer and the first layer.
09/11/14
20140252547
Semiconductor device having integrated passive device and process for manufacturing the same
The present invention relates to a semiconductor device and a process for fabricating the same. In one embodiment, the semiconductor device includes a substrate and a plurality of integrated passive devices.
09/11/14
20140252544
Dc/ ac dual function power delivery network (pdn) decoupling capacitor
Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate.
09/11/14
20140252542
Structure and method for an inductor with metal dummy features
The present disclosure provides a semiconductor device. The semiconductor device includes an inductor formed on a substrate and configured to be operable with a current of a frequency; and dummy metal features configured between the inductor and the substrate, the dummy metal features having a first width less than 2 times of a skin depth associated with the frequency..
09/11/14
20140252540
Semiconductor device and method of manufacturing thereof
A semiconductor device includes a semiconductor substrate having a first main surface in which a recess is formed. Further, the semiconductor device includes an electrical interconnect structure which is arranged at a bottom of the recess.
09/11/14
20140252536
Semiconductor device and method of fabricating the same
A semiconductor device includes line patterns disposed on a substrate, the line patterns extending in a first direction and being parallel to one another. The semiconductor device includes conductive patterns spaced apart from each other in the first direction between an adjacent pair of the line patterns.
09/11/14
20140252534
Method of making deep trench, and devices formed by the method
A method for forming a semiconductor device includes providing a semiconductor-on-insulator (soi) structure, and forming at least one hard mask (hm) layer over the soi structure. The soi structure includes an insulator layer and a semiconductor layer over the insulator layer.
09/11/14
20140252532
Semiconductor device and method for fabricating the same
Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar.
09/11/14
20140252526
Semiconductor device, manufacturing method, and electronic apparatus
A method of manufacturing a semiconductor device includes: forming, on a cover glass, a film having a predetermined specific gravity and configured to shield an alpha ray that arises from the cover glass; and bonding the cover glass on which the film is formed and an image pickup device, by filling a transparent resin between the cover glass and the image pickup device.. .
09/11/14
20140252504
Method for fabricating a semiconductor device
A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (epi layer) in the recess to form a channel, wherein the channel includes a second dopant.
09/11/14
20140252497
Isolation region gap fill method
An isolation region gap fill method comprises depositing a first dielectric material over a semiconductor device through a flowable deposition process or other gap fill deposition processes, wherein the semiconductor device includes a first finfet comprising a plurality of first fins and a second finfet comprising a plurality of second fins. The method further comprises removing the first dielectric material between the first finfet and the second finfet to form an inter-device gap, depositing a second dielectric material into the inter-device gap and applying an annealing process to the semiconductor device..
09/11/14
20140252493
Gate stack including a high-k gate dielectric that is optimized for low voltage applications
A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer.
09/11/14
20140252492
Gate stack including a high-k gate dielectric that is optimized for low voltage applications
A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer.
09/11/14
20140252491
Semiconductor device and manufacturing method of the same
According to one embodiment, a semiconductor device includes a first epitaxial layer of a first material, a second epitaxial layer of a second material, a conductive material, a third epitaxial layer of the first material and a fourth epitaxial layer of the second material. The first epitaxial layer is formed in the source region and the drain region of a p-mos transistor.
09/11/14
20140252490
Semiconductor device and method of manufacturing the semiconductor device
Disclosed is a semiconductor device including a semiconductor device including a substrate, a nitride semiconductor layer formed over the substrate and including an active region and an element isolation region, inert atoms being introduced into the element isolation region, a source electrode formed over the nitride semiconductor layer in the active region, a gate electrode formed over the nitride semiconductor layer in the active region away from the source electrode, and a drain electrode formed over the nitride semiconductor layer in the active region away from the gate electrode, the drain electrode including an end portion provided away from a boundary between the element isolation region and the active region by a first distance, wherein the first distance is greater than a second distance, the second distance being a distance where a concentration of the inert atoms diffused from the element isolation region into the active region becomes a first concentration, and an electron density in the active region at a position where the concentration of the inert atoms is higher than the first concentration is lower than an electron density in a center portion of the active region.. .
09/11/14
20140252483
Semiconductor device having finfet structures and method of making same
A semiconductor device and method making it comprises pfets with an sige channel and nfets with an si channel, formed on an soi substrate. Improved uniformity of fin height and width is attained by forming the fins additively by depositing an sige layer on the soi substrate and forming first fins from the superposed sige layer and underlying thin si film of the soi substrate.
09/11/14
20140252480
Combination finfet and planar fet semiconductor device and methods of making such a device
A device includes a plurality of trenches and fins defined in a substantially un-doped layer of semiconducting material, a gate insulation layer positioned on the fins and on the bottom of the trenches, a gate electrode and a device isolation structure. One method disclosed herein involves identifying a top width of each of a plurality of fins and a depth of a plurality of trenches to be formed in a substantially un-doped layer of semiconducting material, wherein, during operation, the device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to the device, performing at least one process operation to define the trenches and fins in the layer of semiconducting material, forming a gate insulation layer on the fins and on a bottom of the trenches and forming a gate electrode above the gate insulation layer..
09/11/14
20140252479
Semiconductor fin isolation by a well trapping fin portion
A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate.
09/11/14
20140252477
Finfet with an asymmetric source/drain structure and method of making same
Embodiments of the present disclosure are a semiconductor device, a finfet device, and a method of forming a finfet device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin.
09/11/14
20140252472
Semiconductor device with increased safe operating area
A semiconductor device includes a substrate having a surface, a composite body region disposed in the substrate, having a first conductivity type, and comprising a body contact region at the surface of the substrate and a well in which a channel is formed during operation, a source region disposed in the semiconductor substrate adjacent the composite body region and having a second conductivity type, and an isolation region disposed between the body contact region and the source region. The composite body region further includes a body conduction path region contiguous with and under the source region, and the body conduction path region has a higher dopant concentration level than the well..
09/11/14
20140252470
Semiconductor device with integrated electrostatic discharge (esd) clamp
A device includes a substrate, a body region in the substrate and having a first conductivity type, source and drain regions in the substrate, having a second conductivity type, and spaced from one another to define a conduction path that passes through the body region, a doped isolating region in the substrate, having the second conductivity type, and configured to surround a device area in which the conduction path is disposed, an isolation contact region in the substrate, having the second conductivity type, and electrically coupled to the doped isolating region to define a collector region of a bipolar transistor, and first and second contact regions within the body region, having the first and second conductivity types, respectively, and configured to define a base contact region and an emitter region of the bipolar transistor, respectively.. .
09/11/14
20140252465
Semiconductor device and method of producing the same
A semiconductor device has a semiconductor substrate including a body region, a drift region, a trench that extends from a surface of the semiconductor substrate into the drift region through the body region, and a source region located adjacent to the trench in a range exposed to the surface of the semiconductor substrate, the source region being isolated from the drift region by the body region. A specific layer is disposed on a bottom of the trench, and it has a characteristic of forming a depletion layer at a junction between the specific layer and the drift region.
09/11/14
20140252462
Semiconductor device and method for fabricating the same
A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes: a trench disposed within a substrate, the trench comprising an upper trench part that is wider than a lower trench part in width; a gate disposed in the trench; an interlayer insulating layer pattern disposed above the gate in the upper trench part; a source region disposed within the substrate and contacting a sidewall of the upper trench part; a body region disposed below the source region in the substrate; and a contact trench disposed above the body region and filled with a conductive material..
09/11/14
20140252461
Semiconductor device and method for fabricating the same
A semiconductor device and a fabricating method thereof are provided. The semiconductor device include: a trench disposed within a substrate, the trench comprising an upper trench part that is wider than a lower trench part in width; a gate disposed in the trench; an interlayer insulating layer pattern disposed above the gate in the trench; a source region disposed within the substrate and contacting a sidewall of the upper trench part; a body region disposed below the source region in the substrate; and a contact trench disposed above the body region and filled with a conductive material..
09/11/14
20140252459
Method for fabricating semiconductor device
Provided is a method for fabricating a semiconductor device, which includes the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar, and a doped region is disposed at a bottom of each pillar.
09/11/14
20140252458
Semiconductor device having vertical channel transistor and method for fabricating the same
A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ild) layer insulating adjacent pillar structures; a gate contact penetrating the ild layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact.. .
09/11/14
20140252456
Semiconductor device and its manufacturing method
In one embodiment, a semiconductor device can include: (i) a first doped pillar region having a doping concentration that sequentially increases from bottom to top in a vertical direction; (ii) second doped pillar regions arranged on either side of the first doped pillar region in a horizontal direction; and (iii) where sidewalls of the second doped pillar regions form sides of an inverted trapezoidal structure.. .
09/11/14
20140252449
Semiconductor devices comprising floating gate transistors and methods of forming such semiconductor devices
Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions.
09/11/14
20140252448
Extremely thin semiconductor on insulator (etsoi) logic and memory hybrid chip
A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate.
09/11/14
20140252446
Extremely thin semiconductor on insulator (etsoi) logic and memory hybrid chip
A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate.
09/11/14
20140252444
Method of fabricating semiconductor device and device fabricated thereby
A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns.
09/11/14
20140252441
Semiconductor device and method of manufacturing same
A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed.
09/11/14
20140252440
Semiconductor devices including conductive plug
Semiconductor devices include a substrate having a target connection region; a conductive line having a first side wall spaced apart from the substrate by at least an insulating layer, and a conductive plug structure electrically connecting the conductive line to the target connection region, wherein the conductive plug includes a first conductive plug having a first side wall, a bottom surface contacting the target connection region of the substrate, and a second side wall facing the first side wall of the conductive line, and a second conductive plug between the conductive line and the first conductive plug. The second conductive plug contacts both the first side wall of the conductive line and the second side wall of the first conductive plug..
09/11/14
20140252436
Semiconductor device
There is provided a semiconductor device with basic electronic elements in a three-dimensional structure. The semiconductor device has a source region and a drain region each of which includes an electrode and a silicide region, and is formed with a plurality of different crystal planes.
09/11/14
20140252435
Semiconductor device
A semiconductor device concerning an embodiment is provided with a plate-like semiconductor substrate, electrode pads, electrode connecting conductors, and a source electrode back pad. The semiconductor substrate has a first cutout section in a first side, and has a second cutout section and a third cutout section in a second side.
09/11/14
20140252434
Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes forming isolation layers in a first direction at trenches at isolation regions defined at a semiconductor substrate and forming gate lines in a second direction crossing the first direction over the isolation layers and active regions defined between the isolation layers, performing a dry-etch process to remove the isolation layers, and forming an insulating layer over the semiconductor substrate to form a first air gap extending in the first direction in the trenches and a second air gap extending in the second direction between the gate lines.. .
09/11/14
20140252433
Multi-layer metal contacts
A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact..
09/11/14
20140252432
Semiconductor device and method for forming the same
A semiconductor device includes a substrate and a gate structure formed over the substrate. The semiconductor device further includes an insulator feature formed in the substrate.
09/11/14
20140252431
Semiconductor device structure and method of forming same
An embodiment is a semiconductor device comprising a first gate structure over a semiconductor substrate, a first etch stop layer (esl) over the semiconductor substrate and the first gate, the first esl having a curved top surface, and a first inter-layer dielectric (ild) on the first esl, the first ild having a curved top surface. The semiconductor device further comprises a second esl on the first ild, the second esl having a curved top surface, and a second ild on the second esl..
09/11/14
20140252429
Contact geometry having a gate silicon length decoupled from a transistor length
Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided.
09/11/14
20140252427
Self-aligned contacts for replacement metal gate transistors
Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface of the gate, depositing an insulating layer above the semiconductor device, and planarizing the insulating layer using the blocking region as a planarization stop.
09/11/14
20140252425
Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
One method includes performing a first etching process to form a contact opening in a layer of insulating material that exposes a portion of a gate structure of the transistor, performing a second etching process on the exposed portion of the gate structure to thereby define a gate recess, selectively forming an oxidizable material in the gate recess, converting the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to a source/drain region. A device includes an oxide material that is positioned at least partially in a recess formed in a gate structure, wherein the oxide material contacts a conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure..
09/11/14
20140252424
Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable material on the exposed gate structure, converting at least a portion of the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to the source/drain region. A novel transistor device disclosed herein includes an oxide material positioned between a conductive contact and a gate structure of the transistor, wherein the oxide material contacts the conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure..
09/11/14
20140252423
Semiconductor device having metal gate and manufacturing method thereof
A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided.
09/11/14
20140252420
Semiconductor devices including gate electrodes with multiple protrusions configured for charge transfer
An image sensor device can include device isolation regions in a substrate and a photoelectric conversion portion in the substrate that can be between the device isolation regions. A transfer gate of the image sensor device, can be located over, and be electrically coupled to, the photoelectric conversion portion.
09/11/14
20140252417
Semiconductor device and electronic apparatus
A semiconductor device includes: a device region having a semiconductor layer that includes a channel section; a device peripheral region adjoining the device region; a gate electrode provided within the device region, and having a boundary section that spans the device region and the device peripheral region; a conductive layer provided between the gate electrode and the semiconductor layer; and an insulating layer provided between the gate electrode in the boundary section and the semiconductor layer.. .
09/11/14
20140252416
Field effect transitor and semiconductor device using the same
An field effect transistor has a plurality of cells provided on a first straight line. Each cell has a plurality of multi-finger electrodes and is connected to a gate terminal electrode and a drain terminal electrode.
09/11/14
20140252414
Passivated iii-v or ge fin-shaped field effect transistor
A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting of (a) iii-v compound layers and (b) a ge layer, and a coating overlaying the core.
09/11/14
20140252378
Semiconductor substrate and semiconductor device
According to one embodiment, a semiconductor substrate includes a substrate and a semiconductor layer. The substrate has a first surface and containing a silicon carbide.
09/11/14
20140252377
Semiconductor device and method of manufacturing thereof
The semiconductor device includes a sic substrate; an aluminum nitride layer provided on the substrate and having an island-shaped pattern consisting of plural islands: a channel layer provided on the aln layer and comprising a nitride semiconductor; an electron supplying layer provided on the channel layer and having a band gap larger than that of the channel layer; and a gate, source and drain electrodes on the electron supply layer. The aln layer has an area-averaged circularity y/x of greater than 0.2.
09/11/14
20140252376
Silicon carbide substrate, method for manufacturing same and method for manufacturing silicon carbide semiconductor device
A method for manufacturing a silicon carbide substrate includes the following steps. A silicon carbide single-crystal substrate is prepared.
09/11/14
20140252374
Silicon carbide semiconductor device
A first drift layer has a first surface facing a first electrode and electrically connected to a first electrode, and a second surface opposite to the first surface. The first drift layer has an impurity concentration na.
09/11/14
20140252373
Semiconductor device and method for producing the same
A method for producing a semiconductor device is provided. The method includes providing a semiconductor substrate, providing at least one semiconductor device on the substrate, having a back face opposite the semiconductor substrate and a front face towards the semiconductor substrate, providing a contact layer on the back face of the semiconductor device, bonding the contact layer to an auxiliary carrier, and separating the at least one semiconductor device from the substrate.
09/11/14
20140252370
Nitride semiconductor device and method of manufacturing the same
Exemplary embodiments of the present invention disclose a unidirectional heterojunction transistor including a channel layer made of a first nitride-based semiconductor having a first energy bandgap, a barrier layer made of a second nitride-based semiconductor having a second energy bandgap different from the first energy bandgap, the barrier layer including a recess, a drain electrode disposed on a first region of the barrier layer, and a recessed-drain schottky electrode disposed in the recess of the barrier layer, the recessed-drain schottky electrode contacting the drain electrode.. .
09/11/14
20140252369
Nitride-based semiconductor device
A nitride-based semiconductor device including a substrate; a gan-containing layer on the substrate; a nitride-containing layer on the gan layer; a channel blocking layer on the nitride-containing layer, the channel blocking layer including a nitride-based semiconductor; a gate insulation layer on the channel blocking layer; and a gate electrode on the gate insulation layer.. .
09/11/14
20140252367
Driver for normally on iii-nitride transistors to get normally-off functionality
A semiconductor device includes a depletion mode gan fet and an integrated driver/cascode ic. The integrated driver/cascode ic includes an enhancement mode cascoded nmos transistor which is connected in series to a source node of the gan fet.
09/11/14
20140252360
Semiconductor device and manufacturing method of the same
An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions.
09/11/14
20140252359
Semiconductor device and method of making
The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by forming vias or contact holes in an insulator layer covering the transistor and at metal silicide contact regions corresponding to the source and drain, and by filling the vias with metal-semiconductor compound.
09/11/14
20140252357
Semiconductor device
Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (pop) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length.
09/11/14
20140252355
Semiconductor device and method for producing same
The semiconductor device (100a) according to the present invention has a thin film transistor (10a1) supported on a substrate; the thin film transistor (10a1) has an oxide semiconductor layer (5a1), a gate electrode (3a1), a source electrode (8a1), a drain electrode (9a1), and a metal oxide layer (6a, 7a) formed between the source electrode (8a1) and the oxide semiconductor layer (5a1) and/or between the drain electrode (9a1) and the oxide semiconductor layer (5a1); the metal oxide layer (6a, 7a) contains a metallic element included in the source electrode (8a1) and/or the drain electrode (9a1); and the thickness t1 of the oxide semiconductor layer, the thickness t2 of the metal oxide layer, and the distance d between the source electrode (8a1) and the drain electrode (9a1) satisfy the relationship d≧1.56×(t2/t1)+0.75.. .
09/11/14
20140252351
Semiconductor device and method for manufacturing the same
A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.. .
09/11/14
20140252348
Semiconductor device and method for manufacturing the same
An object is to increase field effect mobility of a thin film transistor including an oxide semiconductor. Another object is to stabilize electrical characteristics of the thin film transistor.
09/11/14
20140252347
Semiconductor device
Disclosed is a semiconductor device with a transistor in which an oxide semiconductor is used. An insulating layer on a back channel side of the oxide semiconductor layer has capacitance of lower than or equal to 2×10−4 f/m2.
09/11/14
20140252346
Semiconductor device
It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (pld).
09/11/14
20140252345
Semiconductor film and semiconductor device
An oxide semiconductor film having high stability with respect to light irradiation or a semiconductor device having high stability with respect to light irradiation is provided. One embodiment of the present invention is a semiconductor film including an oxide in which light absorption is observed by a constant photocurrent method (cpm) in a wavelength range of 400 nm to 800 nm, and in which an absorption coefficient of a defect level, which is obtained by removing light absorption due to a band tail from the light absorption, is lower than or equal to 5×10−2/cm.
09/11/14
20140252299
Semiconductor device and method for fabricating the same, and micro processor, processor, system, data storage system and memory system including the semiconductor device
A semiconductor device includes a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines extending in a second direction crossing the first direction; and a plurality of resistance variable lines interposed between the first and the second conductive lines and extending in a third direction crossing the first and the second directions.. .


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This listing is a sample listing of patent applications related to Semiconductor Device for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Semiconductor Device with additional patents listed. Browse our RSS directory or Search for other possible listings.
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