|| List of recent Semiconductor Circuit-related patents
|Sensor and method for manufacturing sensor|
A sensor includes: a substrate on which an active chip including a semiconductor circuit is disposed; and a passive chip including an acceleration sensor, and a thick portion and a thin portion, the thick portion being disposed on the substrate so as to be in contact therewith. An active chip terminal is disposed on the active chip.
|Capacitive sensor integrated onto semiconductor circuit|
There is disclosed a capacitive sensor on a passivation layer of a semiconductor circuit such as an asic, and a method for manufacturing such sensor. The system and method may comprise: forming a bottom electrode layer and landing pad on a portion of the passivation layer located over active circuitry of the asic; forming a gas sensitive layer onto the bottom electrode layer and the landing pad; creating a via through the gas sensitive layer to expose a portion of the landing pad; forming a top electrode layer onto the gas sensitive layer, wherein the top electrode layer completely overlays a surface area of the bottom electrode layer, and wherein the forming process for the top electrode layer deposits a portion of the top electrode layer into the via hole, thereby forming an electrical connection between the top electrode layer and the landing pad..
|Electrostatic discharge protection circuit and semiconductor circuit device|
The invention provides an electrostatic protection circuit that is effective in absorbing static electricity that is continuously input. The electrostatic protection circuit includes a circuit constituting a latch and a static electricity absorption circuit.
|Semiconductor circuit and method for operating the same|
Provided are a semiconductor circuit and method for operating the same. The semiconductor circuit includes a first flip-flop configured to, based on input data synchronized to a first clock, output first output data synchronized to a second clock different from the first clock, and a second flip-flop configured to, based on the first output data, output second output data synchronized to the second clock, wherein the first and the second flip-flops share an inverted second clock and a delayed second clock and output the first and the second output data based thereon, respectively..
|Power storage device control system, power storage system, and electrical appliance|
Deterioration of a power storage device is reduced. Switches that control the connections of a plurality of power storage devices separately are provided.
|Method for including decoupling capacitors into semiconductor circuit having logic circuit therein and semiconductor circuit thereof|
A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit.. .
|Semiconductor device integrating passive elements|
The present invention provides a semiconductor device integrating passive elements, which applies to analog circuits, wherein capacitors, resistors and inductors are fabricated by a tvs technology. The semiconductor device comprises a substrate; at least one passive element arranged in the substrate; and at least one semiconductor integrated circuit formed in the substrate.
|Stack type semiconductor circuit with impedance calibration|
A stack type semiconductor circuit includes a plurality of semiconductor chips stacked therein, wherein the plurality of semiconductor chips are configured to share impedance calibration information. The plurality of semiconductor chips include at least one resistance value of an external resistor and an impedance calibration signal as the impedance calibration information..
|Complementary metal oxide semiconductor circuit structure, preparation method thereof and display device|
Provided are a cmos circuit structure, a preparation method thereof and a display device, wherein a pmos region in the cmos circuit structure is of a ltps tft structure, that is, the pmos semiconductor layer is prepared from a p type doped polysilicon material; an nmos region is of an oxide tft structure, that is, the nmos semiconductor layer is made of an oxide material; three doping processes applied to the nmos region during the ltps process may be omitted in the case in which the nmos semiconductor layer in the nmos region is made of an oxide material instead of the polysilicon material, which may simplify the preparation of the cmos circuit structure as well as reduce a production cost. Furthermore, it is only required to crystallizing the pmos semiconductor layer, which may also extend the lifespan of laser tube, contributing to reduction of the production cost..
|Integrated circuits separated by through-wafer trench isolation|
An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material.. .
|Matching semiconductor circuits|
Devices, circuitry, and methods for improving matching between semiconductor circuits are shown and described. Measuring a difference in matching between semiconductor circuits may be performed with a test current generator and test current measurement circuit, and adjusting a threshold voltage of a semiconductor component of at least one circuit until the difference between the circuits is at a desired difference may be performed with a program circuit..
|Circuit arrangement for switching a current, and method for operating a semiconductor circuit breaker|
A control voltage is generated at a control input of a semiconductor circuit breaker by an actuation circuit at switching flanks of a switching signal, said control voltage having a profile which is flattened in relation to the profile of the switching signal. With the disclosed method, the switching losses in a semiconductor circuit breaker are reduced.
|Systems and methods for controlling power in semiconductor circuits|
A power control circuit includes a plurality of transistors coupled between a power supply node and a gated power supply node, wherein the gate electrode of a first transistor of the plurality of transistors is coupled to receive a power control signal, wherein, in response to assertion of the power control signal, the first transistor is placed into a conductive state; a first voltage comparator, wherein, in response to assertion of the power control signal, places a second transistor of the plurality of transistors in a conductive state when a voltage on the gated voltage supply node reaches a first reference voltage; and a second voltage comparator, wherein, in response to assertion of the power control signal, places a third transistor of the plurality of transistors in a conductive state when the voltage on the gated voltage supply node reaches a second reference voltage different from the first reference voltage.. .
|Cascoded semiconductor devices|
A cascoded power semiconductor circuit has a clamp circuit between the source and gate of a gallium nitride or silicon carbide fet to provide avalanche protection for the cascode mosfet transistor.. .
|Bus controller, bus control system and network interface|
In a bus control system for a semiconductor circuit, data is transmitted between first and second nodes over a network of buses. The bus controller is connected directly to the first node and includes: a route load detector which detects loads on routes that form at least one of a group of forward routes leading from the first to the second node and a group of backward routes leading from the second to the first node; a candidate route extraction circuit which extracts a candidate route from the group of routes so that loads on the routes that form the group become uniform; a route determining circuit which determines the route to transmit the data based on the candidate route and a predetermined selection rule; and a data communication circuit which transmits the data between the first and second nodes based on header information including route information indicating the route..
|Core circuit test architecture|
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths.
|Semiconductor device and method of manufacturing the same|
A semiconductor device of an embodiment includes: a substrate on which a semiconductor circuit is formed; an interlayer insulating film in which a contact hole is formed on the substrate; a catalyst metal film on a side wall of the contact hole; catalyst metal particles on a bottom of the contact hole; graphene on the catalyst metal film; and carbon nanotubes, which penetrates the contact hole, on the catalyst metal particles.. .
|Method for manufacturing a data carrier|
A method for manufacturing a portable data carrier includes the steps of: providing a carrier band having an upper side and a lower side disposed opposite the upper side including a contact field formed with at least one contact area; arranging a semiconductor circuit on the lower side of the carrier band and electroconductively connected with the corresponding contact area; and carrying out an injection molding process on the lower side a potting compound formed around the semiconductor circuit and having outer dimensions according to a portable data carrier standard specification. An injection channel for injecting the potting compound is arranged on a side of the potting compound mold parallel to the lower side, and after the injection of the potting compound a depression remains in the finished data carrier due to the injection channel.
|Nanotube array electronic and opto-electronic devices|
Carbon nanotube (cnt)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration.
|Light-emitting device, method for manufacturing the same, and cellular phone|
The invention relates to: a light-emitting device which includes a first flexible substrate having a first electrode, a light-emitting layer over the first electrode, and a second electrode with a projecting portion over the light-emitting layer and a second flexible substrate having a semiconductor circuit and a third electrode electrically connected to the semiconductor circuit, in which the projecting portion of the second electrode and the third electrode are electrically connected to each other, a method for manufacturing the light-emitting device; and a cellular phone which includes a housing incorporating the light-emitting device and having a longitudinal direction and a lateral direction, in which the light-emitting device is disposed on a front side and in an upper portion in the longitudinal direction of the housing.. .
|Multi-voltage supplied input buffer|
An input buffer capable of interfacing higher-voltage logic signals to lower voltage internal circuitry includes a first stage configured to generate a first output signal in response to an input signal, the first stage configured to receive a first power supply voltage and including semiconductor circuit components configured to be variably biased responsive to a variable voltage. The input buffer also includes a second stage configured to receive the first output voltage and to responsively generate a second output signal, the second stage biased according to the first power supply voltage.
|Methods of containing defects for non-silicon device engineering|
An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor.
|Layout method of semiconductor circuit structure|
A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto.
|Gradient aocv methodology enabling graph-based timing closure with aocv timing models|
A method of manufacturing semiconductor circuits seeks timing closure on a preliminarily select, placed and routed set of cells using a delay for each cell as derated by a derate value obtained from a timing model table having a derate value corresponding to a circuit path depth in the netlist. The derate value for a predetermined number of circuit path depths below k are identical.
|Method and system for pre-migration of metal ions in a semiconductor package|
Pre-migration of metal ions is achieved in a controlled manner to form a migrated metalover which an inhibitor is applied to prevent further migration. In a semiconductor circuit, pre-migration of metal ions is achieved by exposing a joined metal system to water, oxygen and an electrical field in a controlled manner.
In a semiconductor device including semiconductor modules, it is possible to average the temperatures of the semiconductor modules. At least two semiconductor modules, wherein a plurality of semiconductor circuits, on which are mounted one or more semiconductor chips having a gate terminal and gate resistors connected to the gate terminals, are disposed in parallel, are disposed above a cooling body so that an array direction of the semiconductor circuits is a direction intersecting a refrigerant flow.
|Semiconductor circuit and method in a safety concept for use in a motor vehicle|
A semiconductor circuit for an electronic control device for use in a system in a motor vehicle, said system not being mechanically intrinsically safe, and a method for monitoring the semiconductor circuit, wherein the semiconductor circuit comprises a functional computer (fr), at least one monitoring unit (mu) and a monitoring computer (ur), wherein the functional computer (fr), the monitoring unit (mu) and the monitoring computer (ur) are each physically independent of each other, and the full or a restricted function of the semiconductor circuit is ensured by the functional computer (fr) in the event of a failure of the monitoring computer (ur) and vice versa.. .
|Semiconductor circuit and methodology for in-system scan testing|
A semiconductor circuit comprising a digital circuit portion, which comprises a combinatorial logic block. The semiconductor circuit further comprises a scan chain for loading and applying a predefined digital test pattern to inputs of the combinatorial logic block.
|Multiple seal-ring structure for the design, fabrication, and packaging of integrated circuits|
A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit..
|Cascoded semiconductor devices|
A cascoded power semiconductor circuit is provided for power switches based on depletion-mode (normally on) devices. The control circuit makes use of a bootstrap arrangement that allows an active control of both power switches of a cascode circuit using a single gate driver..
|Pattern matching apparatus and computer program|
The semiconductor inspection apparatus includes means for imaging a shape on a wafer or on an exposure mask; means for storing an image inspected by the imaging means; means for storing design data of the semiconductor circuit corresponding to a position on the wafer or on the exposure mask which are to be imaged by the imaging means; means for storing a design-data image obtained as a result of converting the design data into an image; means for generating a design-data roi image by converting an interest drawing region found from a relative crude-density relation of a shape included in the design-data image into an image; and a position alignment section configured to carry out position alignment on the inspected image and the design-data image. The semiconductor inspection apparatus makes use of the design-data roi image in order to identify a position at which the inspected image and the design-data image match each other or compute the degree of coincidence..
|Semiconductor chip including heat radiation member, and display module|
A semiconductor chip includes a circuit region having an integrated semiconductor circuit on a semiconductor substrate, and a heat radiation member on at least a portion of a scribe lane region configured to at least partially surround the circuit region, the heat radiation member including a plurality of heat radiation fins that extend in a direction orthogonal to an upper surface of the semiconductor substrate.. .
|Semiconductor circuit pattern measuring apparatus and method|
Included is a multiple resolution image generating unit which applies a plurality of noise removing filters to a semiconductor circuit pattern image and generates a multiple resolution image, a multiple resolution differential image generating unit which generates a multiple resolution differential image from a difference of images between hierarchies of the multiple resolution image, and a contour extracting unit which extracts a contour of the semiconductor circuit pattern based on an intensity signal of the semiconductor circuit pattern image. The contour extracting unit calculates an intensity signal level upon extracting a contour of the semiconductor circuit pattern from the multiple resolution image by using an image signal of the multiple resolution differential image, and extracts a contour of the semiconductor circuit pattern based on the calculated intensity signal level..
|Internal voltage trimming circuit, method thereof and semiconductor circuit device comprising the same|
Task: to provide an internal voltage trimming circuit having a simple configuration and operated by a consumption current smaller than that using a comparator. Means for solving the problem: an internal voltage trimming circuit comprises a trimming controller using a change in a counting value of a clock according to a current flowing through a transistor of a power supply current source for a clock generator to trim an internal voltage generated by an internal voltage generator.
|Semiconductor circuit, driving circuit of electro-optical device, and electronic apparatus|
A semiconductor circuit includes a first circuit block, a second circuit block, and power wiring lines that supply a plurality of reference potentials. The first circuit block and the second circuit block are connected to a common power wiring line that is one of the power wiring lines and supplies a common reference potential.
|Static discharge system|
A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge distribution structure has a plurality of conductors with a floating potential.
|Method of producing semiconductor device|
A semiconductor device production method where separate semiconductor chips are stacked on a semiconductor substrate having a main surface on which multiple semiconductor chips including semiconductor integrated circuits are formed, the semiconductor chips in different layers are connected to each other to enable signal transmission, and a structure formed thereby is separated into multiple stacks of the semiconductor chips. The method includes a first step of forming an insulating layer on the main surface of the semiconductor substrate; a second step of stacking the separate semiconductor chips, which include the integrated semiconductor circuits on main surfaces thereof, via the insulating layer on the semiconductor chips formed on the semiconductor substrate such that opposite surfaces of the separate semiconductor chips opposite to the main surfaces face the insulating layer; and a third step of forming connecting parts that enable signal transmission between the semiconductor chips in different layers..
|Semiconductor integrated circuit and switching device|
A semiconductor circuit for supplying a signal for controlling a switching circuit includes a control terminal for receiving a control signal. The control signal is sent to a first inverter, which inverts the control signal to generate a first signal.
|Design support method, recording medium storing design support program and semiconductor device|
A design support method includes: selecting, by a computer, a power feed point of an integrated semiconductor circuit on a first board model in which a power supply layer and a ground layer are stacked; determining a first placement position of a first protrusion portion from the first board model on a side of the first board model, the first protrusion portion being corresponding to the power feed point; determining a second placement position of a second protrusion portion from the first board model on the side of the first board model, the second protrusion portion provided so as to separate from the first placement position by a distance; and placing the first protrusion portion and the second protrusion portion on the first placement position and the second placement position, respectively.. .
|Semiconductor device and method of manufacturing thereof|
A semiconductor device includes a substrate having a top surface. A semiconductor circuit defines a circuit area on the top surface of the substrate.
|Core circuit test architecture|
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths.
|Semiconductor device including semiconductor circuit made from semiconductor element and manufacturing method thereof|
In the present invention, a semiconductor film is formed through a sputtering method, and then, the semiconductor film is crystallized. After the crystallization, a patterning step is carried out to form an active layer with a desired shape.
|Cmp slurry regeneration apparatus and method|
The cmp slurry regeneration apparatus 200 for regenerating the cmp slurry used for a cmp process patterning metal conductive elements on a semiconductor circuit comprises a gravity separator 205 for precipitating solids in a diluted waste slurry used in the cmp process by gravity sedimentation; a concentrated slurry container 207 for reserving the solid through the gravity sedimentation in the gravity separator 205 as concentrated slurry 206; a solid-liquid separator 209 for catching components contained in the waste slurry as rinsed components through rinsing the waste slurry by remaining hydroxide corresponding to small amount metal ion while removing soluble and solid components formed by the cmp process; and a regenerated slurry container 211 for regenerating the small amount metal ion from the rinsed components.. .
|System and method for reducing layout-dependent effects|
A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool.
|Semiconductor circuit and semiconductor apparatus|
A semiconductor circuit includes an operational amplifier, a voltage drop circuit, and a switch. The operational amplifier has an output terminal connected to an active element that produces a load drive current.
|Dual profile shallow trench isolation apparatus and system|
The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps..
|Semiconductor circuit structure and process of making the same|
A semiconductor circuit structure and process of making the same is provided in the present invention, comprising the steps of providing a substrate having a target layer and a hard mask layer, forming a patterned small core body group and a large core body group on the hard mask layer, forming a spacer material layer conformally on the substrate and the core body groups, forming filling bodies in each recess of the spacer material layer, performing a first etching process to remove exposed spacer material layer, using the filling bodies as a mask to perform a second etching process for patterning the hard mask layer, and using the patterned hard mask layer as a mask to perform a third etching process for patterning the conductive layer.. .
|Process for semiconductor circuit|
A semiconductor process for forming specific pattern features comprising the steps of forming a target layer, a hard mask layer and a plurality of equally spaced-apart core bodies on a substrate, forming spacers on sidewalls of the core bodies, removing the core bodies so that the spacers are spaced-apart on the hard mask layer, using spacers as a mask to pattern the hard mask layer, removing the hard mask bodies outside of a predetermined region, forming photoresists on several outermost hard mask bodies of the predetermined region, and using the photoresists and remaining hard mask bodies as a mask to pattern the target layer.. .
|Conduction cooling of multi-channel flip chip based panel array circuits|
A method of forming a heat-dissipating structure for semiconductor circuits is provided. First and second semiconductor integrated circuit (ic) chips are provided, where the first and second semiconductor chips each have first and second opposing sides, wherein the first and second semiconductor ic chips are configured to be fixedly attached to a top surface of a substantially planar circuit board along their respective first sides.
|Semiconductor circuit, battery monitoring system, and diagnosis method|
A semiconductor circuit, battery monitoring system, diagnostic program and diagnosis method are provided enabling appropriate self-diagnosis of a measurement unit. An output value (a-b) output through respective power supply lines v (vn, vn−1), a cell selector switch, and a level shift circuit from an ad converter and an output value (b) of a directly input reference voltage b output from the ad converter are summed together.
|Direct bandgap substrates and methods of making and using|
An indirect bandgap thin film semiconductor circuit can be combined with a compound semiconductor led such as to provide an active matrix led array that can have high luminous capabilities such as for a light projector application. In another example, a highly efficient optical detector is achievable through the combination of indirect and direct bandgap semiconductors.
|Switching device of semiconductor circuit and switching method of the same|
Each of a plurality of redundantly formed semiconductor circuits integrally has a monitor transistor and is energized by being supplied with an enable signal. A monitor circuit associated with each semiconductor circuit detects a collector current of the monitor transistor and, when the collector current is less than a predetermined threshold value, outputs an alarm signal.
|Photoresist residue and polymer residue removing liquid composition|
Provided are a photoresist residue and polymer residue removing liquid composition, and a method of removing the residue used therewith, for removing photoresist residue and polymer residue produced during a process of manufacturing a semiconductor circuit element having metallic wiring. Specifically, the composition does not contain nitrogen-containing organic hydroxyl compounds, ammonia or fluorine compounds, and contains an aliphatic polycarboxylic acid having a melting point of 25° c.
|Field effect transistor and semiconductor device|
An object is to provide a field effect transistor (fet) having a conductor-semiconductor junction, which has excellent characteristics, which can be manufactured through an easy process, or which enables high integration. Owing to the junction between a semiconductor layer and a conductor having a work function lower than the electron affinity of the semiconductor layer, a region into which carriers are injected from the conductor is formed in the semiconductor layer.
|Semiconductor substrate, method of manufacturing semiconductor substrate, thin film transistor, semiconductor circuit, liquid crystal display apparatus, electroluminescence apparatus, wireless communication apparatus, and light emitting apparatus|
A semiconductor substrate (41) includes an insulating substrate (30), a plurality of semiconductor thin films (46) which are arranged on the insulating substrate (30) to be separated from each other, and a conductive film (33) which is arranged between the semiconductor thin films (46). Therefore, it is possible to uniformly thin the film thickness of each of the semiconductor thin films..
An optical module has a circuit board, a photoelectric conversion element mounted on a mount surface of the circuit board, an optical coupling member for holding an optical fiber and optically coupling the optical fiber and the photoelectric conversion element, a semiconductor circuit element mounted on the mount surface of the circuit board and electrically connected to the photoelectric conversion element, and a plate-shaped supporting substrate arranged to sandwich the optical coupling member between the supporting substrate and the circuit board. An electrically conductive metal foil which extends in a thickness direction of the supporting substrate is provided integrally with a side surface of the supporting substrate, and the metal foil is connected at one end thereof to an electrode provided on a non-mount surface of the circuit board..
|Optical module, optical transmission device and method of manufacturing optical transmission device|
An optical module includes a circuit board having flexibility, a photoelectric conversion element mounted on a mounting surface of the circuit board, a semiconductor circuit element mounted on the mounting surface of the circuit board and electrically connected to the photoelectric conversion element, a plate-shaped optical connection member having a groove into which an end part of an optical fiber is pushed so as to be housed and optically connecting the optical fiber and the photoelectric conversion element, and a supporting member arranged so as to sandwich the optical connection member between the circuit board. The groove is formed between the semiconductor circuit element and the supporting member so as to have an opening into which the optical fiber is pushed at the supporting member side.
An optical module includes a circuit board including a mount surface and a non-mount surface opposite the mount surface, a photoelectric conversion element mounted on the mount surface of the circuit board, an optical coupling member for holding an optical fiber and optically coupling the optical fiber and the photoelectric conversion element, a semiconductor circuit element mounted on the mount surface of the circuit board, and electrically connected to the photoelectric conversion element, a plate-shaped supporting member arranged so as to sandwich the optical coupling member between the supporting member and the circuit board, and an electrically conductive body supported by the supporting member, extended in a thickness direction of the supporting member, and connected at one end to an electrode provided on the non-mount surface of the circuit board.. .
|Semiconductor circuit design supporting apparatus and method, and non-transitory computer-readable medium|
A semiconductor circuit design supporting method includes: reading register transfer level (rtl) description circuit data; generating an equivalent circuit corresponding to the rtl description circuit data; extracting a plurality of arithmetic components included in the generated equivalent circuit; clustering some of the extracted arithmetic components as a single arithmetic component, wherein no storage element exists between said some of the extracted arithmetic components; reading a timing constraint on the rtl description circuit data; tracing an exception path of the rtl description circuit data when the timing constraint includes a timing exception; determining whether or not the timing exception is set for input pins of said some of the arithmetic components which are clustered as the single arithmetic component, based on the traced exception path of the rtl description circuit data; and separating a arithmetic component for which the timing exception is set, from said some of the arithmetic components which are clustered as the single arithmetic component.. .
|Optical element module and method of manufacturing the same|
A method of manufacturing an optical element module in which an optical element and a semiconductor circuit element are mounted on one surface of a silicon substrate, a mirror surface inclined at approximately 45 degrees is formed on the other surface, and an optical fiber facing the mirror surface is disposed in a v groove formed along the other surface, the method of manufacturing includes the steps of forming the mirror surface and v-shaped side surfaces of the v groove simultaneously by first crystal anisotropic etching on the other surface, and forming an attaching surface substantially perpendicular to the one surface and the other surface, which is formed at an end side of the v groove, and for attaching an end of the optical fiber, by second crystal anisotropic etching in a crystal plane orientation different from that of the first crystal anisotropic etching.. .
|Strain and pressure sensing device, microphone, method for manufacturing strain and pressure sensing device, and method for manufacturing microphone|
According to one embodiment, a strain and pressure sensing device includes a semiconductor circuit unit and a sensing unit. The semiconductor circuit unit includes a semiconductor substrate and a transistor.
|Piezoelectric oscillator and transmitter|
A piezoelectric oscillator includes: a piezoelectric resonator element having a piezoelectric substrate and an excitation electrode formed on a surface of the piezoelectric substrate; a semiconductor circuit element provided with an oscillation circuit for oscillating the piezoelectric resonator element and having a first insulating film formed on a principal surface; a package for airtightly housing the semiconductor circuit element and the piezoelectric resonator element; and a protruding section having at least of a thin film circuit component formed on the first insulating film and connected to the oscillation circuit; and a second insulating film formed on the first insulating film and covering the thin film circuit component. In the oscillator, the piezoelectric resonator element is fixed to an upper surface of the protruding section..
A semiconductor device includes a semiconductor circuit and a capacitor, the capacitor including: a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, the second semiconductor region being provided on the first semiconductor region of the first conductivity type and having a higher concentration of a first conductivity type impurity than the first semiconductor region of the first conductivity type, a semiconductor region of a second conductivity type provided on the second semiconductor region of the first conductivity type, a dielectric film provided on the semiconductor region of the second conductivity type, an upper electrode provided on the dielectric film, a first interconnection provided above the semiconductor region of the second conductivity type and electrically connected to the semiconductor region of the second conductivity type, and a second interconnection electrically connected to the upper electrode.. .
An optical module includes a circuit board, a photoelectric conversion element mounted on the circuit board, an optical connector for optically connecting the photoelectric conversion element and an optical fiber, a semiconductor circuit element mounted on the circuit board and electrically connected to the photoelectric conversion element, a pressing member for pressing and fixing the optical connector to the circuit board, and a supporting member for supporting the pressing member. The supporting member includes a heat-absorbing surface and a heat-dissipating surface.
|Semiconductor device and method for making same|
A semiconductor circuit pattern includes an angled conductive pattern having a line portion and a pad portion at an end of the line portion extending normal to the line portion on a first side of the line portion. The pad portion has a width greater than a width of the line portion.
|Semiconductor circuit design support technique|
A computer readable storage medium stores a semiconductor circuit design support program that causes a computer to execute a process. The process includes identifying wirings connected to a selected cell to be processed from an observation target circuit data storage device storing position data of each cell on a semiconductor chip on which an observation target circuit is implemented for which operations are observed in simulation and data of wirings connected to each cell.
|Power semiconductor device|
The purpose of the present invention is to provide a power semiconductor device which has a light weight, high heat dissipation efficiency, and high rigidity. The power semiconductor device including a base 1, semiconductor circuits 2 which are arranged on the base 1, and a cooling fin 3 which cools each of the semiconductor circuits 2, in which one or more protruding portions 1a, 1b are formed on the base 1, widths of the protruding portions 1a, 1b in a direction parallel to the base 1 surface being longer than a thickness of the base 1, thereby providing power semiconductor devices 100, 200, 300, 400 which have a light weight, high heat dissipation efficiency, and high rigidity..
In a dc/dc converter, a first operation section calculates a first operation value, based on a difference voltage between an instruction value for a high-voltage-side voltage and a detected value of a high-voltage-side voltage, a second operation section calculates a second operation value, based on a difference voltage between a voltage instruction value for a charge-discharge capacitor and a voltage detected value of the charge-discharge capacitor, and a switching control section obtains a conduction ratio, based on the first operation value and the second operation value, and controls, based on the conduction ratio, switching operations of first to fourth semiconductor circuits, thereby controlling the high-voltage-side voltage, and the voltage of the charge-discharge capacitor.. .
|Power semiconductor system|
A power semiconductor system and method for producing a power semiconductor system. In one embodiment, the application relates to a power semiconductor system, comprising a line system for a fluid working medium; wall element having an outer side and an inner side; and a power semiconductor circuit arranged at the outer side of the wall element, wherein the inner side of the wall element forms a fluid-tight wall of the line system..
|Nitride uv light sensors on silicon substrates|
An ultraviolet light sensor and method of manufacturing thereof are disclosed. The ultraviolet light sensor includes group-iii nitride layers adjacent to a silicon wafer with one of the layers at least partially exposed such that a surface thereof can receive uv light to be detected.
|Memory access controller, multi-core processor system, memory access control method, and computer product|
A memory access controller includes a semiconductor circuit configured to classify into a first group of cores having made an exclusive access request to shared memory and a second group of cores not having made an exclusive access request to the shared memory, multiple cores capable of accessing the shared memory; detect a core having completed the exclusive access among the first group of cores; and send to a core among the first group of cores and standing by for the exclusive access, a notification of release from a standby state, when detecting a core having completed the exclusive access.. .