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Semiconductor Circuit patents



      
           
This page is updated frequently with new Semiconductor Circuit-related patent applications. Subscribe to the Semiconductor Circuit RSS feed to automatically get the update: related Semiconductor RSS feeds. RSS updates for this page: Semiconductor Circuit RSS RSS


Test apparatus and test system

Test apparatus and test system

Integrated circuit with antenna for dielectric waveguide

Integrated circuit with antenna for dielectric waveguide

Integrated circuit with antenna for dielectric waveguide

Semiconductor circuit design method, memory compiler and computer program product

Date/App# patent app List of recent Semiconductor Circuit-related patents
10/02/14
20140294340
 Optical module, optical communication equipment, and optical transmission device patent thumbnailOptical module, optical communication equipment, and optical transmission device
An optical module includes a circuit board, an optical element on the circuit board, a semiconductor circuit element thereon and electrically coupled with the optical element, an optical connection member formed on a back surface of the circuit board and including an optical fiber receiving groove, and a pressing plate disposed on a side opposite to the circuit board of the optical connection member so as to fix the optical fiber. The semiconductor circuit element is mounted nearer a tip side of the circuit board in relation to the optical element such that the circuit board, the optical connection member and a tip part of the optical fiber are sandwiched between the semiconductor circuit element and the pressing plate.
09/25/14
20140288871
 Test apparatus and test system patent thumbnailTest apparatus and test system
A test apparatus of the present embodiment has a logic cell, a host and a first bus. The host includes: a conversion section configured to analyze a test vector and convert the test vector to signal control data and a waveform shape; and a judgment section configured to analyze an expected value comparison result to perform success/failure judgment of a test of a semiconductor circuit.
09/25/14
20140287703
 Integrated circuit with antenna for dielectric waveguide patent thumbnailIntegrated circuit with antenna for dielectric waveguide
A system includes an integrated circuit that has a substrate with a top surface and a bottom surface. Semiconductor circuitry is including a radio frequency (rf) amplifier configured to produce an rf signal or an rf receiver configured to receive an rf signal is formed on the top surface of the substrate.
09/18/14
20140282319
 Semiconductor circuit design method, memory compiler and computer program product patent thumbnailSemiconductor circuit design method, memory compiler and computer program product
A semiconductor circuit includes an array of repeating blocks, each of the blocks having a device, and at least one signal line connecting the devices of the blocks. A model of the semiconductor circuit is generated to include a functional area corresponding to at least one first block of the array, and a loading area corresponding to at least one second block of the array.
09/18/14
20140282318
 Timing delay characterization method, memory compiler and computer program product patent thumbnailTiming delay characterization method, memory compiler and computer program product
In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage.
09/18/14
20140282297
 Method for generating post-opc layout in consideration of top loss of etch mask layer patent thumbnailMethod for generating post-opc layout in consideration of top loss of etch mask layer
A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-opc layout.
09/18/14
20140266364
 Semiconductor circuit and method of operating the same patent thumbnailSemiconductor circuit and method of operating the same
Provided are a semiconductor circuit and a method of operating the same. The semiconductor circuit includes a first pulse generating circuit enabled to a rising edge of a clock signal and configured to generate a first read pulse, a second pulse generating circuit enabled to a rising edge of the clock signal and configured to generate a second read pulse independent of the first read pulse, a dynamic pull-down stage configured to develop a voltage level of a first dynamic node based at least on data values of an input signal and the first and second read pulses, and a dynamic pull-up stage configured to develop a voltage level of a second dynamic node based at least on data values of the input signal and the first and second read pulses..
09/18/14
20140265848
 Micro-plasma generation using micro-springs patent thumbnailMicro-plasma generation using micro-springs
An ionic wind engine unit for cooling semiconductor circuit assemblies includes a curved micro-spring and an associated electrode that are maintained apart at an appropriate gap distance such that, when subjected to a sufficiently high voltage potential (i.e., as determined by peek's law), current crowding at the spring's tip portion creates an electrical field that sufficiently ionizes neutral molecules in a portion of the air-filled region surrounding the tip portion to generate a micro-plasma event. In one engine type the electrode is a metal pad, and in a second engine type the electrode is a second micro-spring.
09/11/14
20140252353
 Field-effect transistor, and memory and semiconductor circuit including the same patent thumbnailField-effect transistor, and memory and semiconductor circuit including the same
Provided is a field-effect transistor (fet) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface and has a thickness of greater than or equal to 1 nm and less than or equal to 30 nm, a gate insulating film formed to cover the oxide semiconductor, and a strip-like gate which is formed to cover the gate insulating film and has a width of greater than or equal to 10 nm and less than or equal to 100 nm.
09/04/14
20140247677
 Method of accessing semiconductor memory and semiconductor circuit patent thumbnailMethod of accessing semiconductor memory and semiconductor circuit
A method of accessing a semiconductor memory is disclosed which includes outputting a row address and an active command to the semiconductor memory; outputting a column address and a read or write command to the semiconductor memory; and outputting a spare access command to the semiconductor memory to access data from a spare memory cell at a timing based on an additive latency of the semiconductor memory. Related devices and systems are also disclosed..
09/04/14
20140247077
Semiconductor circuit
Provided is a semiconductor circuit. The semiconductor circuit includes a pulse generator which is enabled by a rising edge of a clock signal and generates a read pulse which varies depending on a voltage of a feedback node; and a sense amplifier which generates a voltage of a dynamic node and the voltage of the feedback node in accordance with a data value of an input signal using the read pulse..
08/28/14
20140241017
Input circuit and power supply circuit
An input circuit connected to a semiconductor circuit is configured to receive a voltage indicating an on/off operation state of a power supply and to output a voltage that is lower than a breakdown voltage of the semiconductor circuit. The input circuit includes a first nmos transistor and a resistor element.
08/21/14
20140231871
Methods of containing defects for non-silicon device engineering
An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor.
08/14/14
20140227989
Semiconductor circuit, d/a converter, mixer circuit, radio communication device, method for adjusting threshold voltage, and method for determining quality of transistor
According to an embodiment, a semiconductor circuit includes a substrate, a tunnel oxide film, a charge storage film, a blocking layer, and plural nodes. The substrate is made of a semiconductor in which two diffusion layers each serving as either a source or a drain are formed.
08/14/14
20140225664
Semiconductor circuit with electrical connections having multiple signal or potential assignments
A semiconductor circuit provides at least one first electrical pin with multiple signal assignment or potential assignment in order to integrate several circuit variants in the semiconductor circuit. It has a switch element for isolating or connecting at least one first electrical pin from or to an input or output of a functional unit integrated in the semiconductor circuit..
07/24/14
20140204552
Sensor and method for manufacturing sensor
A sensor includes: a substrate on which an active chip including a semiconductor circuit is disposed; and a passive chip including an acceleration sensor, and a thick portion and a thin portion, the thick portion being disposed on the substrate so as to be in contact therewith. An active chip terminal is disposed on the active chip.
07/17/14
20140197500
Capacitive sensor integrated onto semiconductor circuit
There is disclosed a capacitive sensor on a passivation layer of a semiconductor circuit such as an asic, and a method for manufacturing such sensor. The system and method may comprise: forming a bottom electrode layer and landing pad on a portion of the passivation layer located over active circuitry of the asic; forming a gas sensitive layer onto the bottom electrode layer and the landing pad; creating a via through the gas sensitive layer to expose a portion of the landing pad; forming a top electrode layer onto the gas sensitive layer, wherein the top electrode layer completely overlays a surface area of the bottom electrode layer, and wherein the forming process for the top electrode layer deposits a portion of the top electrode layer into the via hole, thereby forming an electrical connection between the top electrode layer and the landing pad..
07/10/14
20140192445
Electrostatic discharge protection circuit and semiconductor circuit device
The invention provides an electrostatic protection circuit that is effective in absorbing static electricity that is continuously input. The electrostatic protection circuit includes a circuit constituting a latch and a static electricity absorption circuit.
07/03/14
20140184288
Semiconductor circuit and method for operating the same
Provided are a semiconductor circuit and method for operating the same. The semiconductor circuit includes a first flip-flop configured to, based on input data synchronized to a first clock, output first output data synchronized to a second clock different from the first clock, and a second flip-flop configured to, based on the first output data, output second output data synchronized to the second clock, wherein the first and the second flip-flops share an inverted second clock and a delayed second clock and output the first and the second output data based thereon, respectively..
07/03/14
20140184162
Power storage device control system, power storage system, and electrical appliance
Deterioration of a power storage device is reduced. Switches that control the connections of a plurality of power storage devices separately are provided.
06/26/14
20140175608
Method for including decoupling capacitors into semiconductor circuit having logic circuit therein and semiconductor circuit thereof
A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit.. .
06/26/14
20140175607
Semiconductor device integrating passive elements
The present invention provides a semiconductor device integrating passive elements, which applies to analog circuits, wherein capacitors, resistors and inductors are fabricated by a tvs technology. The semiconductor device comprises a substrate; at least one passive element arranged in the substrate; and at least one semiconductor integrated circuit formed in the substrate.
06/19/14
20140167281
Stack type semiconductor circuit with impedance calibration
A stack type semiconductor circuit includes a plurality of semiconductor chips stacked therein, wherein the plurality of semiconductor chips are configured to share impedance calibration information. The plurality of semiconductor chips include at least one resistance value of an external resistor and an impedance calibration signal as the impedance calibration information..
06/12/14
20140159038
Complementary metal oxide semiconductor circuit structure, preparation method thereof and display device
Provided are a cmos circuit structure, a preparation method thereof and a display device, wherein a pmos region in the cmos circuit structure is of a ltps tft structure, that is, the pmos semiconductor layer is prepared from a p type doped polysilicon material; an nmos region is of an oxide tft structure, that is, the nmos semiconductor layer is made of an oxide material; three doping processes applied to the nmos region during the ltps process may be omitted in the case in which the nmos semiconductor layer in the nmos region is made of an oxide material instead of the polysilicon material, which may simplify the preparation of the cmos circuit structure as well as reduce a production cost. Furthermore, it is only required to crystallizing the pmos semiconductor layer, which may also extend the lifespan of laser tube, contributing to reduction of the production cost..
06/05/14
20140151844
Integrated circuits separated by through-wafer trench isolation
An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material.. .
05/29/14
20140146616
Matching semiconductor circuits
Devices, circuitry, and methods for improving matching between semiconductor circuits are shown and described. Measuring a difference in matching between semiconductor circuits may be performed with a test current generator and test current measurement circuit, and adjusting a threshold voltage of a semiconductor component of at least one circuit until the difference between the circuits is at a desired difference may be performed with a program circuit..
05/29/14
20140145779
Circuit arrangement for switching a current, and method for operating a semiconductor circuit breaker
A control voltage is generated at a control input of a semiconductor circuit breaker by an actuation circuit at switching flanks of a switching signal, said control voltage having a profile which is flattened in relation to the profile of the switching signal. With the disclosed method, the switching losses in a semiconductor circuit breaker are reduced.
05/29/14
20140145699
Systems and methods for controlling power in semiconductor circuits
A power control circuit includes a plurality of transistors coupled between a power supply node and a gated power supply node, wherein the gate electrode of a first transistor of the plurality of transistors is coupled to receive a power control signal, wherein, in response to assertion of the power control signal, the first transistor is placed into a conductive state; a first voltage comparator, wherein, in response to assertion of the power control signal, places a second transistor of the plurality of transistors in a conductive state when a voltage on the gated voltage supply node reaches a first reference voltage; and a second voltage comparator, wherein, in response to assertion of the power control signal, places a third transistor of the plurality of transistors in a conductive state when the voltage on the gated voltage supply node reaches a second reference voltage different from the first reference voltage.. .
05/29/14
20140145208
Cascoded semiconductor devices
A cascoded power semiconductor circuit has a clamp circuit between the source and gate of a gallium nitride or silicon carbide fet to provide avalanche protection for the cascode mosfet transistor.. .
05/08/14
20140129750
Bus controller, bus control system and network interface
In a bus control system for a semiconductor circuit, data is transmitted between first and second nodes over a network of buses. The bus controller is connected directly to the first node and includes: a route load detector which detects loads on routes that form at least one of a group of forward routes leading from the first to the second node and a group of backward routes leading from the second to the first node; a candidate route extraction circuit which extracts a candidate route from the group of routes so that loads on the routes that form the group become uniform; a route determining circuit which determines the route to transmit the data based on the candidate route and a predetermined selection rule; and a data communication circuit which transmits the data between the first and second nodes based on header information including route information indicating the route..
05/01/14
20140122954
Core circuit test architecture
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths.
05/01/14
20140117548
Semiconductor device and method of manufacturing the same
A semiconductor device of an embodiment includes: a substrate on which a semiconductor circuit is formed; an interlayer insulating film in which a contact hole is formed on the substrate; a catalyst metal film on a side wall of the contact hole; catalyst metal particles on a bottom of the contact hole; graphene on the catalyst metal film; and carbon nanotubes, which penetrates the contact hole, on the catalyst metal particles.. .
05/01/14
20140117098
Method for manufacturing a data carrier
A method for manufacturing a portable data carrier includes the steps of: providing a carrier band having an upper side and a lower side disposed opposite the upper side including a contact field formed with at least one contact area; arranging a semiconductor circuit on the lower side of the carrier band and electroconductively connected with the corresponding contact area; and carrying out an injection molding process on the lower side a potting compound formed around the semiconductor circuit and having outer dimensions according to a portable data carrier standard specification. An injection channel for injecting the potting compound is arranged on a side of the potting compound mold parallel to the lower side, and after the injection of the potting compound a depression remains in the finished data carrier due to the injection channel.
04/17/14
20140103299
Nanotube array electronic and opto-electronic devices
Carbon nanotube (cnt)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration.
04/10/14
20140099999
Light-emitting device, method for manufacturing the same, and cellular phone
The invention relates to: a light-emitting device which includes a first flexible substrate having a first electrode, a light-emitting layer over the first electrode, and a second electrode with a projecting portion over the light-emitting layer and a second flexible substrate having a semiconductor circuit and a third electrode electrically connected to the semiconductor circuit, in which the projecting portion of the second electrode and the third electrode are electrically connected to each other, a method for manufacturing the light-emitting device; and a cellular phone which includes a housing incorporating the light-emitting device and having a longitudinal direction and a lateral direction, in which the light-emitting device is disposed on a front side and in an upper portion in the longitudinal direction of the housing.. .
04/10/14
20140097888
Multi-voltage supplied input buffer
An input buffer capable of interfacing higher-voltage logic signals to lower voltage internal circuitry includes a first stage configured to generate a first output signal in response to an input signal, the first stage configured to receive a first power supply voltage and including semiconductor circuit components configured to be variably biased responsive to a variable voltage. The input buffer also includes a second stage configured to receive the first output voltage and to responsively generate a second output signal, the second stage biased according to the first power supply voltage.
04/03/14
20140091361
Methods of containing defects for non-silicon device engineering
An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor.
03/27/14
20140089869
Layout method of semiconductor circuit structure
A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto.
03/20/14
20140082576
Gradient aocv methodology enabling graph-based timing closure with aocv timing models
A method of manufacturing semiconductor circuits seeks timing closure on a preliminarily select, placed and routed set of cells using a delay for each cell as derated by a derate value obtained from a timing model table having a derate value corresponding to a circuit path depth in the netlist. The derate value for a predetermined number of circuit path depths below k are identical.
03/20/14
20140077346
Method and system for pre-migration of metal ions in a semiconductor package
Pre-migration of metal ions is achieved in a controlled manner to form a migrated metalover which an inhibitor is applied to prevent further migration. In a semiconductor circuit, pre-migration of metal ions is achieved by exposing a joined metal system to water, oxygen and an electrical field in a controlled manner.
03/13/14
20140070400
Semiconductor device
In a semiconductor device including semiconductor modules, it is possible to average the temperatures of the semiconductor modules. At least two semiconductor modules, wherein a plurality of semiconductor circuits, on which are mounted one or more semiconductor chips having a gate terminal and gate resistors connected to the gate terminals, are disposed in parallel, are disposed above a cooling body so that an array direction of the semiconductor circuits is a direction intersecting a refrigerant flow.
02/20/14
20140052325
Semiconductor circuit and method in a safety concept for use in a motor vehicle
A semiconductor circuit for an electronic control device for use in a system in a motor vehicle, said system not being mechanically intrinsically safe, and a method for monitoring the semiconductor circuit, wherein the semiconductor circuit comprises a functional computer (fr), at least one monitoring unit (mu) and a monitoring computer (ur), wherein the functional computer (fr), the monitoring unit (mu) and the monitoring computer (ur) are each physically independent of each other, and the full or a restricted function of the semiconductor circuit is ensured by the functional computer (fr) in the event of a failure of the monitoring computer (ur) and vice versa.. .
02/13/14
20140047293
Semiconductor circuit and methodology for in-system scan testing
A semiconductor circuit comprising a digital circuit portion, which comprises a combinatorial logic block. The semiconductor circuit further comprises a scan chain for loading and applying a predefined digital test pattern to inputs of the combinatorial logic block.
02/06/14
20140035106
Multiple seal-ring structure for the design, fabrication, and packaging of integrated circuits
A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit..
01/30/14
20140027785
Cascoded semiconductor devices
A cascoded power semiconductor circuit is provided for power switches based on depletion-mode (normally on) devices. The control circuit makes use of a bootstrap arrangement that allows an active control of both power switches of a cascode circuit using a single gate driver..
01/23/14
20140023265
Pattern matching apparatus and computer program
The semiconductor inspection apparatus includes means for imaging a shape on a wafer or on an exposure mask; means for storing an image inspected by the imaging means; means for storing design data of the semiconductor circuit corresponding to a position on the wafer or on the exposure mask which are to be imaged by the imaging means; means for storing a design-data image obtained as a result of converting the design data into an image; means for generating a design-data roi image by converting an interest drawing region found from a relative crude-density relation of a shape included in the design-data image into an image; and a position alignment section configured to carry out position alignment on the inspected image and the design-data image. The semiconductor inspection apparatus makes use of the design-data roi image in order to identify a position at which the inspected image and the design-data image match each other or compute the degree of coincidence..
01/16/14
20140014975
Semiconductor chip including heat radiation member, and display module
A semiconductor chip includes a circuit region having an integrated semiconductor circuit on a semiconductor substrate, and a heat radiation member on at least a portion of a scribe lane region configured to at least partially surround the circuit region, the heat radiation member including a plurality of heat radiation fins that extend in a direction orthogonal to an upper surface of the semiconductor substrate.. .
01/02/14
20140003703
Semiconductor circuit pattern measuring apparatus and method
Included is a multiple resolution image generating unit which applies a plurality of noise removing filters to a semiconductor circuit pattern image and generates a multiple resolution image, a multiple resolution differential image generating unit which generates a multiple resolution differential image from a difference of images between hierarchies of the multiple resolution image, and a contour extracting unit which extracts a contour of the semiconductor circuit pattern based on an intensity signal of the semiconductor circuit pattern image. The contour extracting unit calculates an intensity signal level upon extracting a contour of the semiconductor circuit pattern from the multiple resolution image by using an image signal of the multiple resolution differential image, and extracts a contour of the semiconductor circuit pattern based on the calculated intensity signal level..
01/02/14
20140002179
Internal voltage trimming circuit, method thereof and semiconductor circuit device comprising the same
Task: to provide an internal voltage trimming circuit having a simple configuration and operated by a consumption current smaller than that using a comparator. Means for solving the problem: an internal voltage trimming circuit comprises a trimming controller using a change in a counting value of a clock according to a current flowing through a transistor of a power supply current source for a clock generator to trim an internal voltage generated by an internal voltage generator.
01/02/14
20140001965
Semiconductor circuit, driving circuit of electro-optical device, and electronic apparatus
A semiconductor circuit includes a first circuit block, a second circuit block, and power wiring lines that supply a plurality of reference potentials. The first circuit block and the second circuit block are connected to a common power wiring line that is one of the power wiring lines and supplies a common reference potential.
01/02/14
20140001515
Static discharge system
A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge distribution structure has a plurality of conductors with a floating potential.
12/26/13
20130344655
Method of producing semiconductor device
A semiconductor device production method where separate semiconductor chips are stacked on a semiconductor substrate having a main surface on which multiple semiconductor chips including semiconductor integrated circuits are formed, the semiconductor chips in different layers are connected to each other to enable signal transmission, and a structure formed thereby is separated into multiple stacks of the semiconductor chips. The method includes a first step of forming an insulating layer on the main surface of the semiconductor substrate; a second step of stacking the separate semiconductor chips, which include the integrated semiconductor circuits on main surfaces thereof, via the insulating layer on the semiconductor chips formed on the semiconductor substrate such that opposite surfaces of the separate semiconductor chips opposite to the main surfaces face the insulating layer; and a third step of forming connecting parts that enable signal transmission between the semiconductor chips in different layers..
12/26/13
20130342259
Semiconductor integrated circuit and switching device
A semiconductor circuit for supplying a signal for controlling a switching circuit includes a control terminal for receiving a control signal. The control signal is sent to a first inverter, which inverts the control signal to generate a first signal.
12/12/13
20130328156
Design support method, recording medium storing design support program and semiconductor device
A design support method includes: selecting, by a computer, a power feed point of an integrated semiconductor circuit on a first board model in which a power supply layer and a ground layer are stacked; determining a first placement position of a first protrusion portion from the first board model on a side of the first board model, the first protrusion portion being corresponding to the power feed point; determining a second placement position of a second protrusion portion from the first board model on the side of the first board model, the second protrusion portion provided so as to separate from the first placement position by a distance; and placing the first protrusion portion and the second protrusion portion on the first placement position and the second placement position, respectively.. .
12/05/13
20130320554
Semiconductor device and method of manufacturing thereof
A semiconductor device includes a substrate having a top surface. A semiconductor circuit defines a circuit area on the top surface of the substrate.
11/28/13
20130318409
Core circuit test architecture
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths.
11/14/13
20130299839
Semiconductor device including semiconductor circuit made from semiconductor element and manufacturing method thereof
In the present invention, a semiconductor film is formed through a sputtering method, and then, the semiconductor film is crystallized. After the crystallization, a patterning step is carried out to form an active layer with a desired shape.
11/07/13
20130291444
Cmp slurry regeneration apparatus and method
The cmp slurry regeneration apparatus 200 for regenerating the cmp slurry used for a cmp process patterning metal conductive elements on a semiconductor circuit comprises a gravity separator 205 for precipitating solids in a diluted waste slurry used in the cmp process by gravity sedimentation; a concentrated slurry container 207 for reserving the solid through the gravity sedimentation in the gravity separator 205 as concentrated slurry 206; a solid-liquid separator 209 for catching components contained in the waste slurry as rinsed components through rinsing the waste slurry by remaining hydroxide corresponding to small amount metal ion while removing soluble and solid components formed by the cmp process; and a regenerated slurry container 211 for regenerating the small amount metal ion from the rinsed components.. .
10/31/13
20130290916
System and method for reducing layout-dependent effects
A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool.
10/24/13
20130278166
Semiconductor circuit and semiconductor apparatus
A semiconductor circuit includes an operational amplifier, a voltage drop circuit, and a switch. The operational amplifier has an output terminal connected to an active element that produces a load drive current.
10/24/13
20130277790
Dual profile shallow trench isolation apparatus and system
The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps..
10/10/13
20130264622
Semiconductor circuit structure and process of making the same
A semiconductor circuit structure and process of making the same is provided in the present invention, comprising the steps of providing a substrate having a target layer and a hard mask layer, forming a patterned small core body group and a large core body group on the hard mask layer, forming a spacer material layer conformally on the substrate and the core body groups, forming filling bodies in each recess of the spacer material layer, performing a first etching process to remove exposed spacer material layer, using the filling bodies as a mask to perform a second etching process for patterning the hard mask layer, and using the patterned hard mask layer as a mask to perform a third etching process for patterning the conductive layer.. .
10/03/13
20130260557
Process for semiconductor circuit
A semiconductor process for forming specific pattern features comprising the steps of forming a target layer, a hard mask layer and a plurality of equally spaced-apart core bodies on a substrate, forming spacers on sidewalls of the core bodies, removing the core bodies so that the spacers are spaced-apart on the hard mask layer, using spacers as a mask to pattern the hard mask layer, removing the hard mask bodies outside of a predetermined region, forming photoresists on several outermost hard mask bodies of the predetermined region, and using the photoresists and remaining hard mask bodies as a mask to pattern the target layer.. .
10/03/13
20130258599
Conduction cooling of multi-channel flip chip based panel array circuits
A method of forming a heat-dissipating structure for semiconductor circuits is provided. First and second semiconductor integrated circuit (ic) chips are provided, where the first and second semiconductor chips each have first and second opposing sides, wherein the first and second semiconductor ic chips are configured to be fixedly attached to a top surface of a substantially planar circuit board along their respective first sides.
09/19/13
20130241566
Semiconductor circuit, battery monitoring system, and diagnosis method
A semiconductor circuit, battery monitoring system, diagnostic program and diagnosis method are provided enabling appropriate self-diagnosis of a measurement unit. An output value (a-b) output through respective power supply lines v (vn, vn−1), a cell selector switch, and a level shift circuit from an ad converter and an output value (b) of a directly input reference voltage b output from the ad converter are summed together.
09/19/13
20130240880
Direct bandgap substrates and methods of making and using
An indirect bandgap thin film semiconductor circuit can be combined with a compound semiconductor led such as to provide an active matrix led array that can have high luminous capabilities such as for a light projector application. In another example, a highly efficient optical detector is achievable through the combination of indirect and direct bandgap semiconductors.
09/12/13
20130234777
Switching device of semiconductor circuit and switching method of the same
Each of a plurality of redundantly formed semiconductor circuits integrally has a monitor transistor and is energized by being supplied with an enable signal. A monitor circuit associated with each semiconductor circuit detects a collector current of the monitor transistor and, when the collector current is less than a predetermined threshold value, outputs an alarm signal.
09/05/13
20130231271
Photoresist residue and polymer residue removing liquid composition
Provided are a photoresist residue and polymer residue removing liquid composition, and a method of removing the residue used therewith, for removing photoresist residue and polymer residue produced during a process of manufacturing a semiconductor circuit element having metallic wiring. Specifically, the composition does not contain nitrogen-containing organic hydroxyl compounds, ammonia or fluorine compounds, and contains an aliphatic polycarboxylic acid having a melting point of 25° c.
09/05/13
20130228776
Field effect transistor and semiconductor device
An object is to provide a field effect transistor (fet) having a conductor-semiconductor junction, which has excellent characteristics, which can be manufactured through an easy process, or which enables high integration. Owing to the junction between a semiconductor layer and a conductor having a work function lower than the electron affinity of the semiconductor layer, a region into which carriers are injected from the conductor is formed in the semiconductor layer.


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Semiconductor Circuit topics: Semiconductor, Semiconductor Circuit, Circuit Board, Reference Voltage, Semiconductor Substrate, Optical Fiber, Regenerate, Conductive Elements, Concentrated, Automation, Electronic Design Automation, Simulation, Electric Conversion, Shallow Trench Isolation, Photoelectric Conversion

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