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Planarization patents



      
           
This page is updated frequently with new Planarization-related patent applications. Subscribe to the Planarization RSS feed to automatically get the update: related Planarization RSS feeds. RSS updates for this page: Planarization RSS RSS


Flexible substrates and method of manufacturing the same

Organic light-emitting display apparatus and method of manufacturing the same

Date/App# patent app List of recent Planarization-related patents
08/28/14
20140242776
 Strained isolation regions patent thumbnailnew patent Strained isolation regions
A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material.
08/28/14
20140241509
 Mesoporous structured material, x-ray waveguide, and method of fabricating mesoporous structured material patent thumbnailnew patent Mesoporous structured material, x-ray waveguide, and method of fabricating mesoporous structured material
The planarization layer is existing in the mesopores exposed on the surface of the mesoporous matrix.. .
08/28/14
20140239361
 Methods and apparatus for suppressing cross talk in cmos image sensors patent thumbnailnew patent Methods and apparatus for suppressing cross talk in cmos image sensors
A cmos image sensor with reduced crosstalk includes a semiconductor substrate formed with a plurality of photodiodes formed therein, a dielectric layer formed on the semiconductor substrate, a reflective layer formed on the dielectric layer, and an insulating layer formed on the reflective layer. A plurality of grooves is formed in the dielectric layer, the reflective layer, and the insulating layer above a corresponding photodiode.
08/28/14
20140239266
 Organic light-emitting display apparatus and method of manufacturing the same patent thumbnailnew patent Organic light-emitting display apparatus and method of manufacturing the same
An organic light-emitting display apparatus whose defect rate is significantly decreased in a manufacturing procedure includes a substrate having a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region; and a planarization layer covering the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region, such that a distance between the substrate and a top surface of the planarization layer at the center of the first sub-pixel region is greater than a distance between the substrate and the top surface of the planarization layer at the center of the second sub-pixel region or a distance between the substrate and the top surface of the planarization layer at the center of the third sub-pixel region. A method of manufacturing the organic light-emitting display apparatus is also disclosed..
08/28/14
20140239265
 Organic light-emitting display apparatus and method of manufacturing the same patent thumbnailnew patent Organic light-emitting display apparatus and method of manufacturing the same
Provided are an organic light-emitting display apparatus having a very low defect rate in a manufacturing process, and a method of manufacturing the organic light-emitting display apparatus. The organic light-emitting display apparatus includes: a substrate; a planarization layer covering the substrate and having a top surface including a recessed portion; a pixel electrode in the recessed portion of the planarization layer; a step forming unit on the top surface of the planarization layer outside of the recessed portion; and a pixel-defining layer exposing at least a central portion of the pixel electrode, and covering the step forming unit so that a top surface of the pixel-defining layer includes a protruding portion corresponding to the step forming unit..
08/28/14
20140238582
 Flexible substrates and method of manufacturing the same patent thumbnailnew patent Flexible substrates and method of manufacturing the same
A flexible substrate includes a flexible mother substrate and a planarization layer on the flexible mother substrate. Here, the flexible mother substrate includes a transparent textile and a resin layer.
08/21/14
20140231986
 Through substrate via (tsuv) structures and method of making the same patent thumbnailThrough substrate via (tsuv) structures and method of making the same
Through substrate via (tsuv) structures and method of making the same are disclosed herein. In embodiments, tsuv structures are metal filled selectively to avoid forming significant metal overburden on non-via surfaces of the substrate.
08/21/14
20140231919
 Fin deformation modulation patent thumbnailFin deformation modulation
A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench.
08/21/14
20140231263
 Method and apparatus for maintaining parallelism of layers and/or achieving desired thicknesses of layers during the electrochemical fabrication of structures patent thumbnailMethod and apparatus for maintaining parallelism of layers and/or achieving desired thicknesses of layers during the electrochemical fabrication of structures
Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. Mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g.
08/14/14
20140227951
 Conductive chemical mechanical planarization polishing pad patent thumbnailConductive chemical mechanical planarization polishing pad
A polishing pad for polishing a substrate. The pad comprises a layer of material having an upper polishing surface and a lower surface interfacing with a proximate platen, the material comprising a mixture of a conductive polymer distributed in a structure of a dielectric polymeric material using predetermined relationships.
08/14/14
20140227945
Chemical mechanical planarization platen
A method and system for planarizing or polishing a semiconductor wafer. The system includes a carrier adaptable to hold a semiconductor wafer, a polishing pad, and a platen having a substantially planar surface in contact with the polishing pad, the planar surface having a distribution of holes.
08/07/14
20140220778
Planarization method and planarization apparatus
According to one embodiment, a planarization method and a planarization apparatus are provided. In the planarization method, a work surface of a work piece is planarized by bringing the work surface of the work piece containing a silicon oxide film and a surface of a solid plate onto which hydrogen ions are adsorbed, into contact or extremely close proximity with one another in a state in which a process liquid containing fluorine ions is supplied to the surface of the solid plate..
07/31/14
20140209913
Array substrate and display device comprising the same
An array substrate, which is formed with a gate electrode (2), a source electrode (5), a drain electrode (6), a gate insulating layer (3), an active layer (4) and a passivation layer (9) in a thin film transistor region, and with the gate insulating layer (3), a pixel electrode (7), the passivation layer (9) and a common electrode (8) in a pixel electrode pattern region, and a color resin layer (11) is formed between the passivation layer (9) and the common electrode (8). Since the color resin layer (11) for planarization is formed on the passivation layer (9), the horizontal driving manner may be suitably applied in order to reduce light leakage, to improve contrast ratio and aperture ratio of a panel and to lower production costs..
07/31/14
20140209473
Electrochemical fabrication methods incorporating dielectric materials and/or using dielectric substrates
Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material.
07/31/14
20140209239
Methods and apparatus for post-chemical mechanical planarization substrate cleaning
A method and apparatus for cleaning a substrate after chemical mechanical planarizing (cmp) is provided. The apparatus comprises a housing, a substrate holder rotatable on a first axis and configured to retain a substrate in a substantially vertical orientation, a first pad holder having a pad retaining surface facing the substrate holder in a parallel and spaced apart relation, the first pad holder rotatable on a second axis disposed parallel to the first axis, a first actuator operable to move the pad holder relative to the substrate holder to change a distance between the first axis and the second axis, and a second pad holder disposed in the housing, the second pad holder having a pad retaining surface facing the substrate holder in a parallel and spaced apart relation, the second pad holder rotatable on a third axis parallel to the first axis and the second axis..
07/24/14
20140206164
Chemical mechanical polish in the growth of semiconductor regions
A method includes performing a first planarization step to remove portions of a semiconductor region over isolation regions. The first planarization step has a first selectivity, with the first selectivity being a ratio of a first removal rate of the semiconductor region to a second removal rate of the isolation regions.
07/17/14
20140197904
Method for fabricating miniature structures or devices such as rf and microwave components
Multi-layer, multi-material fabrication methods include depositing at least one structural material and at least one sacrificial material during the formation of each of a plurality of layers wherein deposited materials for each layer are planarized to set a boundary level for the respective layer and wherein during formation of at least one layer at least three materials are deposited with a planarization operation occurring before deposition of the last material to set a planarization level above the layer boundary level and wherein a planarization occurs after deposition of the last material level above the layer boundary level and wherein a planarization occurs after deposition of the last material whereby the boundary level for the layer is set. Some formation processes use electrochemical fabrication techniques (e.g.
07/17/14
20140197520
Resistor and resistor fabrication for semiconductor devices
In a particular embodiment, a method includes removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer. A resistive layer is formed at least partially within the region.
07/17/14
20140197519
Mim capacitor and mim capacitor fabrication for semiconductor devices
In a particular embodiment, a method of forming a metal-insulator-metal (mim) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the mim capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region.
07/10/14
20140193963
Techniques for forming 3d structures
A technique for forming 3d semiconductor structure is disclosed. In one embodiment, a substrate having at least two vertically extending fins is provided.
07/10/14
20140191414
Semiconductor device and method for fabricating the same
A semiconductor device and a method for fabricating the same are provided. The semiconductor device comprising a substrate including a first surface and a second surface that face each other, a planarization layer formed on the first surface of the substrate, a passivation layer formed on the planarization layer, and a through via contact penetrating the substrate, the planarization layer, and the passivation layer, and being exposed from the passivation layer..
07/10/14
20140191239
Display device
Disclosed is a display device and an electronic apparatus incorporating the display device. The display device includes a transistor and a planarization film over the transistor.
07/10/14
20140191209
Organic light-emitting device and of preparing the same
An organic light emitting diode (oled) and a method of manufacturing the same. An auxiliary layer comprising a high density metallic compound and an emission layer are formed by a laser induced thermal imaging (liti) process.
07/03/14
20140187042
Method for chemical planarization and chemical planarization apparatus
According to one embodiment, a method is disclosed for chemical planarization. The method can include forming a surface layer on a to-be-processed film having irregularity.
07/03/14
20140183635
Thin film transistor and method for manufacturing the same
A thin film transistor including a first insulating layer disposed on a substrate and having a first hole; a second insulating layer disposed on the substrate and having a second hole; a gate insulating layer disposed between the first and second insulating layers; a gate electrode formed in the first hole; a source electrode and second drain electrode formed at both sides of an inner portion of the second hole; and an activated layer formed between the source electrode and the second drain electrode of the inner portion of the second hole, and having a planarization layer.. .
06/26/14
20140176895
Liquid crystal display device and method for fabricating the same
The present disclosure relates to a liquid crystal display device and a fabricating method thereof. The device includes a thin film transistor formed on a lower substrate, a pixel electrode formed on the lower substrate, a planarization layer formed on an entire surface of the lower substrate, a black matrix formed on the upper substrate, a color filter layer formed on a upper substrate, partition walls formed on the upper substrate and forming a space corresponding to a seal pattern insertion groove, a liquid crystal layer interposed between the lower substrate and the upper substrate, and a seal pattern inserted between the seal pattern insertion groove located on the non-display region of the lower substrate and the upper substrate and the partition walls..
06/26/14
20140176894
Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same
The present disclosure relates to an array substrate for a fringe field switching mode liquid crystal display device, and a fabricating method thereof, the array substrate including a gate line on an insulating substrate, an active layer on a gate electrode, a data line having a source electrode on one side of the active layer, the data line defining a pixel region, a large pixel electrode on another side of the active layer, a planarization layer on the data line and the source electrode, a passivation layer formed on the insulating substrate, and a common electrode on the passivation layer, and overlapping the pixel electrode and the data line.. .
06/26/14
20140175394
Organic light emitting diode display device and method of fabricating the same
An organic light emitting diode display device and method of fabricating the device according to an embodiment includes a substrate; an oxide semiconductor layer over the substrate; a planarization layer over the oxide semiconductor layer; an emitting diode over the planarization layer; a passivation layer over the emitting diode; and a hydrogen blocking layer between the planarization layer and the passivation layer to block hydrogen diffusion from the passivation layer to the oxide semiconductor layer.. .
06/26/14
20140175393
Organic light emitting diode display device and method of fabricating the same
An organic light emitting diode display device capable of improving capacitance cst of a storage capacitor and transmittance and a method of fabricating the same are disclosed. The organic light emitting diode display device includes a driving thin film transistor (tft) formed on the substrate, a passivation film formed to cover the tft driver, a color filter formed on the passivation film in a luminescent region, a planarization film formed to cover the color filter, a transparent metal layer formed on the planarization film, an insulating film formed on the transparent metal layer, a first electrode connected to the tft driver and overlapping the transparent metal layer while interposing the insulating film therebetween, an organic light emitting layer and a second electrode which are sequentially formed on the first electrode.
06/19/14
20140170853
Image reversal with ahm gap fill for multiple patterning
Methods and apparatuses for multiple patterning using image reversal are provided. The methods may include depositing gap-fill ashable hardmasks using a deposition-etch-ash method to fill gaps in a pattern of a semiconductor substrate and eliminating spacer etching steps using a single-etch planarization method.
06/19/14
20140170829
Lateral bipolar transistor and cmos hybrid technology
A method of forming a lateral bipolar transistor includes forming a silicon on insulator (soi) substrate having a bottom substrate layer, a buried oxide layer (box) on top of the substrate layer, and a silicon on insulator (soi) layer on top of the box layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the soi layer with positive or negative ions, depositing an inter layer dielectric (ild), using chemical mechanical planarization (cmp) to planarize the ild, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the soi layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process.. .
06/19/14
20140168805
Method for manufacturing a color filter, color filter and solid-state imaging device
The present disclosure relates to a method for manufacturing a color filter being capable of suppressing residue from being generated on a colored layer planarized by a planarization treatment, a color filter, and a solid-state imaging device.. .
06/19/14
20140167208
Chemical mechanical planarization process and structures
A semiconductor device includes a substrate having a first and second region, a first structure and a second structure. The first structure is formed over the substrate in the first region.
06/12/14
20140159050
Field effect transistor and method of fabricating the same
A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode..
06/12/14
20140159002
Organic light emitting diode device and method for fabricating the same
Disclosed are an organic light emitting diode device, and a method for fabricating the same. The organic light emitting diode device comprises a non-active area formed outside an active area of a substrate; a switching thin film transistor and a driving thin film transistor at each of the pixel regions; a planarization layer on the substrate; a first electrode on the planarization layer; a bank formed in the non-active area outside each pixel region; an organic light emitting layer on the first electrode; a second electrode on an entire surface of the substrate; a first passivation layer on the substrate; an organic layer on the first passivation layer; a second passivation layer on the organic layer and the first passivation layer; a barrier film disposed to face the substrate..
06/05/14
20140154881
Method of manufacturing metal silicide and semiconductor structure using the same
A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is provided.
06/05/14
20140151639
Nanomesh complementary metal-oxide-semiconductor field effect transistors
An alternating stack of first and second semiconductor layers is formed. Fin-defining mask structures are formed over the alternating stack.
06/05/14
20140151638
Hybrid nanomesh structures
An alternating stack of first and second semiconductor layers is formed. Fin-defining mask structures are formed over the alternating stack.
06/05/14
20140151237
Methods of and apparatus for electrochemically fabricating structures interlaced layers or via selective etching and filling of voids
Multi-layer structures are electrochemically fabricated by depositing a first material, selectively etching the first material (e.g. Via a mask), depositing a second material to fill in the voids created by the etching, and then planarizing the depositions so as to bound the layer being created and thereafter adding additional layers to previously formed layers.
05/29/14
20140148012
Tone inversion of self-assembled self-aligned structures
A stack of an organic planarization layer (opl) and a template layer is provided over a substrate. The template layer is patterned to induce self-assembly of a copolymer layer to be subsequently deposited.
05/22/14
20140140015
Substrate and display device including the same
In an aspect, a substrate for a display device that includes a plastic substrate and a planarization layer is provided.. .
05/22/14
20140139410
Multiple light management textures
An optoelectronic device providing improved light management is provided. The optoelectronic device includes a substrate having a substantially flat surface, a light management layer provided on the flat surface, such that the light management layer includes a first light management texture.
05/22/14
20140138631
Organic light-emitting display device and method of manufacturing the same
An organic light emitting display device including a sub-pixel including a pixel electrode, a counter electrode, and a light emitting layer between the pixel electrode and the counter electrode, a planarization layer covering the counter electrode, and an auxiliary electrode in the planarization layer and coupled to the counter electrode.. .
05/15/14
20140131893
Methods for selective reverse mask planarization and interconnect structures formed thereby
Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features.
05/15/14
20140131841
Metal pad structure over tsv to reduce shorting of upper metal layer
Various embodiments of mechanisms for forming a slotted metal pad over a tsv in substrate are provided. The dielectric structures in the slotted metal pad reduce dishing effect during planarization of the slotted metal pad.
05/15/14
20140131828
Solid-state imaging apparatus and method for manufacturing same
An insulating layer is layered above a substrate, and a plurality of pixel electrodes are formed above the insulating layer in a matrix with intervals therebetween. A photoelectric conversion layer and an opposing electrode are formed in respective order above the pixel electrodes.
05/15/14
20140131817
Gap-fill keyhole repair using printable dielectric material
Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures.
05/15/14
20140131699
Thin film transistor display panel and method of manufacturing the same
A thin film transistor display panel includes a gate electrode on a substrate; a gate insulating layer on the substrate and the gate electrode; a planarization layer on the gate insulating layer and at opposing sides of the gate electrode, where the planarization layer exposes the gate insulating layer; a semiconductor layer on the gate insulating layer; and a source electrode and a drain electrode on the semiconductor layer and spaced apart from each other.. .
05/08/14
20140127897
Dual damascene process
A method for forming dual damascene structures in a semiconductor structure is disclosed. The method generally includes etching a substrate using a first hard mask to form a plurality of first trenches and vias, forming a set of first conductive lines and via interconnects, removing the first hard mask, etching the substrate using a second hard mask to form a plurality of second trenches and vias, and forming a set of second conductive lines and via interconnects.
05/01/14
20140120804
Bellows driven air floatation abrading workholder
Flat-surfaced workpieces such as semiconductor wafers are attached to a rotatable floating workpiece holder carrier rotor that is supported by and rotationally driven by a bellows. The wafer carrier rotor is contained by a set of idlers that are attached to a stationary rotor housing to provide support against abrading forces that are imposed on the wafer by the moving abrasive coating on a rotary platen.
05/01/14
20140117466
Replacement gate electrode with multi-thickness conductive metallic nitride layers
Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities.
05/01/14
20140117463
Gate structure and manufacturing method thereof
A method for manufacturing a gate structure may include the following steps: providing a stack on a substrate, the first stack including (from top to bottom) a dummy layer, a first tin layer, a tan layer, a second tin layer, a high-k first dielectric layer, and an interfacial layer; etching the stack to result in a remaining stack that includes at least a remaining dummy layer, a first remaining tin layer, and a remaining tan layer; providing an etching stop layer on the substrate; providing a second dielectric layer on the etching stop layer; performing planarization according to the remaining dummy layer; removing the remaining dummy layer and a first portion of the first remaining tin layer using a dry etching process; removing a second portion of the first remaining tin layer using a wet etching process; and providing a metal gate layer on the remaining tan layer.. .
05/01/14
20140117421
Self-aligned contact structure for replacement metal gate
A metallic top surface of a replacement gate structure is oxidized to convert a top portion of the replacement gate structure into a dielectric oxide. After removal of a planarization dielectric layer, selective epitaxy is performed to form a raised source region and a raised drain region that extends higher than the topmost surface of the replacement gate structure.
04/24/14
20140113532
Chemical mechanical planarization conditioner
A pad conditioner for a cmp polishing pad is disclosed that includes a substrate that has a matrixical arrangement of protrusions that have a layer of poly crystalline diamond on at least their top surfaces. The protrusions may have varying shapes and elevations and may comprise a first set of protrusions and a second set of protrusions, the first set of protrusions have a first average height and the second set of protrusions have a second average height, the first average height different from the second average height, a top of each protrusion in the first set of protrusions has a non-flat surface and a top of each protrusion in the second set of protrusions has a non-flat surface..
04/24/14
20140113417
Cross-coupling of gate conductor line and active region in semiconductor devices
Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned.
04/24/14
20140113397
Enhancing planarization uniformity in optical devices
An optical device is formed from a device precursor having a layer of a light-transmitting medium on a base. A first feature is formed on the device precursor.
04/24/14
20140110846
Dual hard mask lithography process
A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (opl), and a first photoresist are applied above the first metallic hard mask layer.
04/17/14
20140103450
Hybrid orientation fin field effect transistor and planar field effect transistor
A substrate including a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. Semiconductor fins can be formed by patterning a portion of the buried semiconductor layer after removal of the upper insulator layer and the top semiconductor layer in a fin region, while a planar device region is protected by an etch mask.
04/17/14
20140103404
Replacement gate with an inner dielectric spacer
After formation of source and drain regions and a planarization dielectric layer, a disposable gate structure is removed to form a gate cavity. A gate dielectric and a lower gate electrode are formed within the gate cavity.
04/10/14
20140099784
Method for manufacturing a semiconductor device
A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern and a second metal gate film pattern in the trench, redepositing a second metal gate film on the first and second metal gate film patterns and the insulation film, and forming a redeposited second metal gate film pattern on the first and second metal gate film patterns by performing a planarization process for removing a portion of the redeposited second metal gate film so as to expose a top surface of the insulation film, and forming a blocking layer pattern on the redeposited second metal gate film pattern by oxidizing an exposed surface of the redeposited second metal gate film pattern.. .
04/03/14
20140094017
Manufacturing method for a shallow trench isolation
A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed.
04/03/14
20140091477
System and method for chemical-mechanical planarization of a metal layer
A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a semiconductor substrate, depositing a porogen-containing low-k layer over the low-k inter-metal layer, and etching a space for the via through the low-k inter-metal layer and the porogen-containing low-k layer.
04/03/14
20140091438
Multiple metal layer semiconductor device and low temperature stacking method of fabricating the same
A semiconductor device including a conductive element and an interface surface fabricated atop the conductive element, and a method for fabricating such a device are described. An exemplary device includes a substrate having a conductive element and a metal layer fabricated atop the conductive element.
04/03/14
20140091390
Protection layer for halftone process of third metal
A thin-film transistor having a protection layer for a planarization layer. The protection layer prevents reduction of the planarization layer during an ashing process, thereby preventing the formation of a steeply tapered via hole through the planarization layer.
03/27/14
20140087562
Method for processing silicon substrate and method for producing charged-particle beam lens
A method for processing a silicon substrate includes forming a mask layer on the silicon substrate; forming a hole is farmed in the silicon substrate by alternately repeating (i) an etching step in which plasma etching is performed in a thickness direction of the silicon substrate using the mask layer as a mask and (ii) a deposition step in which a protection film is deposited on an inner wall of the hole formed in the etching step; removing the protection film; and a planarizing a side wall of the hole by etching the inner wall of the hole from which the protection film has been removed. The mask layer includes a material that withstands the removal step.
03/27/14
20140084424
Semiconductor device with protective structure around semiconductor die for localized planarization of insulating layer
A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die.
03/27/14
20140083973
Method for manufacturing a device on a substrate
A method for manufacturing a device on a substrate includes forming a layer structure on the substrate, forming an auxiliary layer on the layer structure, forming a planarization layer on the auxiliary layer and on the substrate, exposing the auxiliary layer by a chemical mechanical polishing process and removing at least partly the auxiliary layer to form a planar surface of the remaining auxiliary layer or of the layer structure and the planarization layer. The chemical mechanical polishing process has a first removal rate with respect to the planarization layer and a second removal rate with respect to the auxiliary layer and the first removal rate is greater than the second removal rate..
03/20/14
20140078100
Touch panel and touch display panel
A touch panel includes a substrate, a touch device layer, a sensing circuit structure, and a planarization layer. The substrate includes a sensing region and a peripheral region that surrounds the sensing region.
03/20/14
20140077299
Strained semiconductor device and method of making the same
In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or soi layer). The gate electrode is electrically insulated from the semiconductor body.
03/13/14
20140073106
Lateral bipolar transistor and cmos hybrid technology
A method of forming a lateral bipolar transistor. The method includes forming a silicon on insulator (soi) substrate having a bottom substrate layer, a buried oxide layer (box) on top of the substrate layer, and a silicon on insulator (soi) layer on top of the box layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the soi layer with positive or negative ions, depositing an inter layer dielectric (ild), using chemical mechanical planarization (cmp) to planarize the ild, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the soi layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process..
03/06/14
20140065777
Dram with dual level word lines
A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer.
03/06/14
20140065774
Embedded planar source/drain stressors for a finfet including a plurality of fins
Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed.


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Planarization topics: Planarization, Semiconductor, Scattering, Semiconductor Substrate, Memory Cell, Electronic Apparatus, Integrated Circuit, Nanoparticle, Impregnated, Aqueous Solution, Semiconductor Material, Heterogeneous, Transistors, Semiconductor Memory, Memory Device

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This listing is a sample listing of patent applications related to Planarization for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Planarization with additional patents listed. Browse our RSS directory or Search for other possible listings.
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