|| List of recent Nonvolatile Memory-related patents
| Electronic control unit for vehicle and data communication method|
An electronic control unit for a vehicle includes a nonvolatile memory that is capable of erasing and writing data electrically, and capable of receiving a program to be written into the nonvolatile memory in units of a predetermined size by means of communication using a communication buffer. The electronic control unit for the vehicle uses communication buffers, the number of which is greater than the number of communication buffers used in an in-vehicle communication environment, to receive the program..
| Translation layer partitioned between host and controller|
A method for using a partitioned flash transition layer is disclosed. Step (a) receives, at an apparatus from a host, a write command having first write data.
| Variable-size flash translation layer|
A method for using a variable-size flash transition layer is disclosed. Step (a) receives a read request to read data corresponding to a logical block address from a nonvolatile memory.
| Multilevel cell nonvolatile memory system|
A multilevel cell (mlc) nonvolatile memory system including a plurality of memory cells each cell storing first bit data and second bit data, and a controller programming the plurality of memory cells on a page-by-page basis, the controller programming original data to an original block and programming copy data that is the same as the original data to a mirroring block, wherein first bit page data and second bit page data of the original data are programmed to memory cells connected to the same word line, but the first bit page data and second bit page data of the copy data are programmed to memory cells connected to different word lines.. .
| Nonvolatile memory devices, memory systems and related control methods|
A nonvolatile memory device includes a cell array including a plurality of cell strings extending on a substrate in a vertical direction, a page buffer connected to a plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured to provide voltages to a plurality of word lines and the plurality of bit lines, and an input/output buffer configured to temporarily store the sensing data received in a data dump from the page buffer and to output the temporarily stored data to an external device. The nonvolatile memory device further includes control logic configured to set a status of the nonvolatile memory device to a ready state after the sensing data is dumped to the input/output buffer and before recovery of the cell array from a bias voltage of the sensing operation is complete..
| Nonvolatile memory device, memory system having the same, external power controlling method thereof|
An external power control method includes determining whether to apply a second external voltage to a first node according to a drop of a first external voltage; generating a flag signal according to a drop of the second external voltage when the second external voltage is applied to the first node; transferring a voltage of the first node to a second node in response to the flag signal; and discharging at least one voltage of an internal circuit connected to the second node in response to the flag signal.. .
| High voltage switch and a nonvolatile memory device including the same|
A high voltage switch of a nonvolatile memory device includes a depletion type nmos transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage switch into a first driving voltage or a ground voltage, wherein the first and second driving voltages are received from an external device; and a pmos transistor configured to transfer the second driving voltage provided to a first terminal of the pmos transistor from the depletion type nmos transistor to a second terminal of the pmos transistor as the output signal in response to an output of the at least one inverter, wherein the output of the at least one inverter is transferred to a gate terminal of the pmos transistor.. .
| Nonvolatile resistive memory device and writing method|
A writing method for a resistive nonvolatile memory device includes writing data to a resistive nonvolatile memory cell using an up/down write pulse signal when the data is first data type, and writing data to the resistive nonvolatile memory cell using only one of an up write pulse signal and a down write pulse signal when the data is second data type.. .
| Variable resistance nonvolatile memory element and method of manufacturing the same|
A variable resistance nonvolatile memory element includes: first and second electrode layers; a first variable resistance layer between the first and second electrode layers; and a second variable resistance layer between the second electrode layer and the first variable resistance layer and having a higher resistance value than the first variable resistance layer. When viewed in a direction perpendicular to the major surface of the second variable resistance layer, an outline of the second variable resistance layer is located inwardly of the outline of any one of the second electrode layer and the first variable resistance layer, and an outline of a face of the second variable resistance layer, the face being in contact with the first variable resistance layer is located inwardly of an outline of a face of the first variable resistance layer, the face being in contact with the second variable resistance layer..
|Apparatus and method for encoding data for storage in multi-level nonvolatile memory|
A controller for a nonvolatile memory includes an encoder and a decoder. The memory includes memory cells that each store data using more than two levels.
|Distributed procedure execution and file systems on a memory interface|
Nonvolatile memory (e.g., flash memory, solid-state disk) is included on memory modules that are on a dram memory channel. Nonvolatile memory residing on a dram memory channel may be integrated into the existing file system structures of operating systems.
|Storage control apparatus, data storage apparatus and method for storage control|
According to one embodiment, a storage control apparatus includes a first buffer controller and a second buffer controller. The first buffer controller is configured to store data of a first unit in each of data buffer regions, and the data of the first unit is transmitted from a host and written in a nonvolatile memory, or read from the nonvolatile memory and transmitted to the host.
|Orchestrating management operations among a plurality of intelligent storage elements|
An apparatus and associated methodology contemplating a data storage system having a group of processor-controlled intelligent storage elements (ises). Each ise in the group individually includes storage resources and a network interface.
|Method and system for reducing the size of nonvolatile memories|
Embodiments relate to system and methods including a plurality of nonvolatile memory elements wherein sets of least two nonvolatile memory elements each share one select element for selecting one of the nonvolatile memory elements of a particular one of the sets of nonvolatile memory elements for a read operation or a program operation.. .
|Method of storing data in nonvolatile memory device and method of testing nonvolatile memory device|
A method of storing data in a nonvolatile memory device comprises performing a program operation on target memory cells among multiple memory cells, performing a first verify operation to determine whether the target memory cells are in a program pass state or a program fail state, and as a consequence of determining that the target memory cells are in the program pass state, performing a second verify operation to determine whether the target memory cells exhibit a program error symptom.. .
A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a mos type first transistor section (3) used for information storage, and a mos type second transistor section (4) which selects the first transistor section.
|Nonvolatile memory and manipulating method thereof|
A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided.
|Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution|
A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data states at which the memory cells may be read.. .
|Nonvolatile memory device using variable resistive element and memory system having the same|
A nonvolatile memory device, which has an improved read reliability through a refresh operation, and a memory system, are provided. The nonvolatile memory device includes a resistive memory cell, a reference resistor corresponding to the resistive memory cell, a reference sense amplifier electrically connected to the reference resistor and configured to change a transition time of an output value of the reference resistor, and a refresh request signal generator configured to output the refresh request signal for the resistive memory cell when the transition time of an output value of the reference resistor is in a preset refresh requiring period..
|Pad structures and wiring structures in a vertical type semiconductor device|
Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position.
|Vertical type semiconductor devices|
A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines.
|Nonvolatile memory devices with aligned trench isolation regions|
A nonvolatile memory device includes a substrate, an elongate isolation region including a field insulation film disposed in a trench in the substrate, and a word line crossing the insulation region and including a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer. A first plane index of a bottom surface of the trench has a first interface trap density and a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density.
|Nonvolatile memory element, nonvolatile memory device, nonvolatile memory element manufacturing method, and nonvolatile memory device manufacturing method|
A nonvolatile memory element including: a first electrode; a second electrode; a variable resistance layer that is between the first electrode and the second electrode and includes, as stacked layers, a first variable resistance layer connected to the first electrode and a second variable resistance layer connected to the second electrode; and a side wall protecting layer that has oxygen barrier properties and covers a side surface of the variable resistance layer. The first variable resistance layer includes a first metal oxide and a third metal oxide formed around the first metal oxide and having an oxygen deficiency lower than that of the first metal oxide, and the second variable resistance layer includes a second metal oxide having an oxygen deficiency lower than that of the first metal oxide..
|Nonvolatile memory with split substrate select gates and heirarchical bitline configuration|
Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells.
|Nonvolatile memory device and read method thereof|
A nonvolatile memory device is provided which includes a main area including main cells connected to word lines and main bit lines; a reference area including reference cells connected to the word lines and reference bit lines and programmed using the same write condition as that of the main area; a reference sense amplifier circuit configured to read data written at the reference area through the reference bit lines at a read operation; and control logic configured to control the reference sense amplifier circuit such that data written at the reference area is shifted with a weight scheme and then read, the data written at the reference area being used as a read reference value of the main area at a read operation.. .
|Nonvolatile memory devices with age-based variability of read operations and methods of operating same|
Integrated circuit memory systems and methods include comparing a number of erase cycles of a memory block corresponding to a read request to a first value and reading data stored in the memory block according to a first read condition corresponding to a first reliability improvement operation when the number of erase cycles of the memory block is less than the first value. An error of the data read according to the first read condition may be corrected using an error correction code (ecc) when the error of the data read according to the first read condition is correctable..
|Method and apparatus for a trust processor|
In an embodiment, an apparatus includes a cryptographic processor within a wireless device. The cryptographic processor includes at least one cryptographic unit.
|Semiconductor storage device and method of controlling the same|
A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories.. .
|Method of programming data into nonvolatile memory and method of reading data from nonvolatile memory|
Disclosed is a method of programming data into a nonvolatile memory that includes a plurality of memory cells connected with a word line, each memory cell storing first to mth bits of a plurality of bits, the plurality of bits forming first to mth pages. The method includes generating first to mth metadata based on first to mth page data received; rearranging the first to mth metadata to generate first to mth rearranged metadata; and programming the first to mth rearranged metadata and the first to mth page data into the first to mth pages, respectively..
|Memory allocation for fast platform hibernation and resumption of computing systems|
Memory allocation for fast platform hibernation and resumption of computing systems. An embodiment of an apparatus includes logic at least partially implemented in hardware, the logic to: dynamically allocate at least a first portion of a nonvolatile memory; in response to a command to enter the apparatus into a standby state, the logic to store at least a portion of a context data from a volatile memory to the dynamically allocated first portion of the nonvolatile memory; and in response to a resumption of operation of the apparatus, the logic to copy at least the portion of the context data from the first portion of the nonvolatile memory to the volatile memory, and to reclaim the first portion of the nonvolatile memory for dynamic allocation..
|Nonvolatile memory devices including simultaneous impedance calibration|
An operating method of a nonvolatile memory device is provided which includes receiving a command sequence; detecting whether the input command sequence accompanies an impedance calibration operation; and if the input command sequence accompanies the impedance calibration operation, simultaneously performing an operation corresponding to the input command sequence and the impedance calibration operation.. .
|Nonvolatile memory and method with improved i/o interface|
Each i/o channel between a controller and one or more memory dice of a memory device has a driver on one end and a receiver at the other end. The receiver is optionally terminated with a pseudo open-drain (“pod”) termination instead of the conventional center-tapped (“ctt”) termination to save energy.
|Nonvolatile memory apparatus having magnetoresistive memory elements and method for driving the same|
A semiconductor memory apparatus includes a source line, a first bit line disposed over the source line, a second bit line disposed under the source line, a first memory cell between the source line and the first bit line, and a second memory cell between the source line and the second bit line.. .
|Write method for writing to variable resistance nonvolatile memory element and variable resistance nonvolatile memory device|
A write method for writing to a variable resistance nonvolatile memory element, comprising applying a set of strong recovery-voltage pulses at least once to the variable resistance nonvolatile memory element when it is determined that the resistance state of the variable resistance nonvolatile memory element fails to change to a second resistance state, remaining in a first resistance state, the set of strong recovery-voltage pulses including pulses: (1) a first strong recovery-voltage pulse which has a greater amplitude than a normal second voltage for changing the resistance state to the first resistance state, and has the same polarity as the second voltage; and (2) a second strong recovery-voltage pulse which follows the first strong recovery-voltage pulse and has a longer pulse width than the pulse width of the normal first voltage for changing the resistance state to the second resistance state, and has the same polarity as the first voltage.. .
|Nonvolatile memory structure and fabrication method thereof|
A nonvolatile memory structure includes a semiconductor substrate having thereon a first oxide define (od) region, a second od region and a third od region arranged in a row. The first, second, and third od regions are separated from one another by an isolation region.
|Nonvolatile memory device having a current limiting element|
Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element.
A memory system includes a processor, one or more volatile memory dies stacked with the processor and one or more nonvolatile memory dies stacked with the processor and the volatile memory dies. The processor transfers data stored in the volatile memory die to the nonvolatile memory die in response to a backup signal, and transfers the data stored in the nonvolatile memory die to the volatile memory die in response to a recovery signal..
|Electronic device for storing data on pram and memory control method thereof|
The present disclosure relates to an electronic device for storing data on pram and a memory control method thereof the electronic device of the present disclosure comprises: a nonvolatile memory in which data is stored; a volatile memory in which an address conversion table of a nonvolatile memory is stored; and a controller that stores data on a nonvolatile memory by referencing an address conversion table of a nonvolatile memory stored on a volatile memory. Due to this, a nonvolatile memory having limitative number of write and read such as pram can be operated more effectively..
|Medical-technical device calibration|
Robotic surgical tools, systems, and methods for preparing for and performing robotic surgery include a memory mounted on the tool. The memory can perform a number of functions when the tool is loaded on the tool manipulator: first, the memory can provide a signal verifying that the tool is compatible with that particular robotic system.
|Nonvolatile memory apparatus|
A nonvolatile memory apparatus includes a memory cell configured to receive a first current and a second current through a bit line which is connected to a sensing node; a sensing node level control unit configured to be driven in response to a control signal, compare a reference voltage and a voltage of the sensing node, and output a driving signal to a driving node; a first current driving unit configured to output the first current to the driving node by using a first driving voltage in response to the driving signal; and a current control unit configured to perform a discharge operation of the bit line or electrically connect the driving node and the sensing node, in response to the control signal.. .
|Nonvolatile memory apparatus|
A nonvolatile memory apparatus includes a read driver. The read driver unit is configured to apply read current to a memory cell in a normal read operation for outputting data stored in the memory cell, and apply refresh current larger than the read current to the memory cell in a refresh operation..
|Nonvolatile memory apparatus|
A nonvolatile memory apparatus includes a read/write control unit and a voltage generation unit and the memory cell. The read/write control circuit is configured to supply a bias voltage in response to a read control signal, a write control signal and data.
|Nonvolatile memory device and related operating method|
A method is for driving a nonvolatile memory device, where the nonvolatile memory device includes a memory cell array composed of resistance memory cells. The method includes electrically connecting a clamping circuit, a line resistor and a selected one of the resistance memory cells in series between a sensing node and a ground.
|Nonvolatile memory apparatus|
A nonvolatile memory apparatus includes a sensing voltage generation unit, a memory cell, a current copy unit and a data sensing unit. The sensing voltage generation unit provides a sensing voltage with a constant level, to a sensing node.
|Semiconductor image sensor module and method of manufacturing the same|
A cmos type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an a/d converter array.
|Nonvolatile memory device and method for fabricating the same|
A nonvolatile memory device includes a memory gate including a memory layer provided over a substrate and a gate electrode provided over the memory layer, the memory gate having first and second opposing sidewalls disposed on first and second sides of the memory gate, respectively; first and second select gates disposed on the first and second sidewalls of the memory gate; a source region formed in the substrate proximate to the first side of the memory gate; a drain region formed in the substrate proximate to the second side of the memory gate; and a gate contact coupled to the gate electrode of the memory gate and to the first select gate, or the second select gate, or both.. .
|Nonvolatile memory device and method for fabricating the same|
A nonvolatile memory device includes a floating gate formed over a substrate; a contact plug formed on a first side of the floating gate and disposed parallel to the floating gate with a gap defined therebetween; and a spacer formed on a sidewall of the floating gate and filling the gap, wherein the contact plug and the floating gate have a sufficiently large overlapping area to enable the contact plug to operate as a control gate for the floating gate.. .
|Manufacturing method of nonvolatile memory device and nonvolatile memory device|
A method of manufacturing a non-volatile memory device comprises: forming a first electrode layer; a variable resistance material layer, a second electrode layer; and a hard mask layer, forming a first resist mask extending in a first direction on the hard mask layer; forming a first hard mask extending in the first direction by etching the hard mask layer using the first resist mask; forming a second resist mask extending in a second direction, on the first hard mask such that the width of the second resist mask is greater than the width of the first resist mask; forming a second hard mask by etching the first hard mask using the second resist mask; and forming a variable resistance element by patterning, by etching the second electrode layer, the variable resistance material layer and the first electrode layer using the second hard mask.. .
|Forming nonvolatile memory elements by diffusing oxygen into electrodes|
Provided are methods of forming nonvolatile memory elements including resistance switching layers. A method involves diffusing oxygen from a precursor layer to one or more reactive electrodes by annealing.
|Morphology control of ultra-thin meox layer|
A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and life and methods for forming the same. The nonvolatile memory device has a first layer on a substrate, a resistive switching layer on the first layer, and a second layer.
|Sequential atomic layer deposition of electrodes and resistive switching components|
Provided are methods of forming nonvolatile memory elements using atomic layer deposition techniques, in which at least two different layers of a memory element are deposited sequentially and without breaking vacuum in a deposition chamber. This approach may be used to prevent oxidation of various materials used for electrodes without a need for separate oxygen barrier layers.
|Information processing apparatus operable in power saving mode and method for controlling the same|
In an information processing apparatus operable in a power saving mode, a sub cpu reads out initial screen data pre-stored in a nonvolatile memory, and displays it on a display screen when the information processing apparatus returns from the power saving mode. Further, the sub cpu detects coordinate data of an area touched by a user on the initial screen, and stores it into the nonvolatile memory.
|Information processing apparatus, method for controlling information processing apparatus, non-transitory recording medium storing control tool, host device, non-transitory recording medium storing performance evaluation tool, and performance evaluation method for external memory device|
According to the embodiments, a nonvolatile memory device is configured to store a normal operating system, and store a bootloader. A host device is capable of initiating the normal operating system by using the bootloader.
|Computing system using nonvolatile memory as main memory and method for managing the same|
A method of managing data of a computing system is provided, where the computing system uses a nonvolatile memory as a main memory. The method includes loading a process into the nonvolatile memory in response to a first run request, freezing the process loaded into the nonvolatile memory in response to an exit request of the process, and activating the process frozen in the nonvolatile memory in response to a second run request of the process.
|Data storage device and operating method thereof|
A method of operating a data storage device includes setting program verify voltages for verifying whether memory cells of a nonvolatile memory device are programmed to desired program states; transmitting the set program verify voltages to the nonvolatile memory device; generating data patterns respectively corresponding to program states based on the program verify voltages; transmitting a data pattern corresponding to the program verify voltages to the nonvolatile memory device; and programming the memory cells with the transmitted data pattern.. .
|Data storage device and method of operating the same|
An operating method of a data storage device including nonvolatile memory devices includes making a victim block list for victim blocks for which a merge operation is to be performed and copying valid pages of the victim bocks to a merge block. The method also includes determining whether there is a victim block which has an erase-held valid page selectively erasing the victim blocks included in the victim block list, according to which victim blocks have an erase-held page, and updating the victim block list according to which victim blocks are erased..
|Nonvolatile flash memory structures including fullerene molecules and methods for manufacturing the same|
Embodiments of tunneling barriers and methods for same can embed molecules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding c60 molecules inbetween first and second insulating layers forming a dielectric layer, a field sensitive tunneling barrier can be implemented.
|Select transistor tuning|
In a nonvolatile memory array in which a select transistor includes a charge storage element, the threshold voltage of the select transistor is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range.. .
|Nonvolatile memory device having variable resistive elements and method of driving the same|
A method is provided for driving a nonvolatile memory device. The method includes selecting first write drivers based on a predetermined current, performing a first program operation on resistive memory cells corresponding to the first write drivers, verifying whether the resistive memory cells have passed or failed in the first program operation and sorting information regarding failed bit memory cells that failed in the first program operation, selecting second write drivers based on the sorted failed bit memory cell information, and performing a second program operation on resistive memory cells corresponding to the second write drivers..
A nonvolatile memory cell includes a first n-well, a second n-well separated from the first n-well in a first direction, a selection transistor formed in the first n-well, a floating gate electrode formed to overlap with a part of the first n-well and a part of the second n-well in a plan view, and an n-conductivity-type semiconductor regions formed in the second n-well on both sides of the floating gate electrode. In write operation, −7 v is applied to the drain of a selected nonvolatile memory cell, −8 v is applied to the gate electrode of the selection transistor, and further −3 v is applied to the n-conductivity-type semiconductor region for obtaining a higher write speed.
|Nonvolatile memory device using a tunnel oxide as a passive current steering element|
Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device.
|Nonvolatile memory cell comprising a diode and a resistance-switching material|
A nonvolatile memory cell is provided that includes a diode and a reversible resistance-switching element that includes a resistance-switching metal oxide or nitride, the metal oxide or nitride including only one metal. Numerous other aspects are provided..
|Il-free mim stack for clean rram devices|
A nonvolatile memory device that contains a resistive switching memory element with improved device switching performance and lifetime, and methods of forming the same. A nonvolatile memory element includes a first electrode layer formed on a substrate, a resistive switching layer formed on the first electrode layer, and a second electrode layer.
|Using saturated and unsaturated ald processes to deposit oxides as reram switching layer|
A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and lifetime by custom tailoring the average concentration of defects in the resistive switching film and methods of forming the same. The nonvolatile memory element includes a first electrode layer, a second electrode layer, and a resistive switching layer disposed between the first electrode layer and the second electrode layer.
|Error correction code rate management for nonvolatile memory|
An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile.
|Systems and methods for improved communications in a nonvolatile memory system|
Systems and methods are provided for improved communications in a nonvolatile memory (“nvm”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and nvm dies included in the system.
|Soc system and method for operating the same|
A soc system includes a central processing unit; a memory management unit receiving a virtual address from the central processing unit and converting the virtual address into a physical address; a main memory implemented by a volatile memory and directly accessed through the physical address converted by the memory management unit; and a storage implemented by a nonvolatile memory separate from the main memory and including a first area directly accessed through the physical address converted by the memory management unit.. .
|Nonvolatile memory apparatus, operating method thereof, and data processing system having the same|
A nonvolatile memory apparatus includes: a memory cell array; a write driver/sense amplifier (wd/sa) configured to program data into the memory cell array or read data from the memory cell array; and an i/o controller configured to receive the read data from the memory cell array from the wd/sa, decide a coding mode based on comparison data between write data and the read data, encode the write data according to the coding mode, and provide the encoded data to the wd/sa.. .
|Nonvolatile memory apparatus, operating method thereof, and data processing system having the same|
Provided is a nonvolatile memory apparatus which writes data into a memory cell according to a program and verify (pnv) operation, wherein the nonvolatile memory apparatus performs the pnv operation for first data during a first time, and performs a plurality of pnv operations for second data during the first time.. .
|Method of manufacturing nonvolatile memory device|
A nonvolatile memory device having a vertical structure and a method of manufacturing the same, the nonvolatile memory device including a channel region that vertically extends from a substrate; gate electrodes on the substrate, the gate electrodes being disposed along an outer side wall of the channel region and spaced apart from one another; and a channel pad that extends from one side of the channel region to an outside of the channel region, the channel pad covering a top surface of the channel region.. .
|Nonvolatile memory system and refresh method|
A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence..
|Non-volatile memory device, driving method of memory controller controlling the non-volatile memory device and memory system including the memory controller and the non-volatile memory device|
The present inventive concept provides a driving method of memory controller controlling nonvolatile memory device using variable resistive element. The memory controller may control a plurality of first memory devices and a second memory device.
|Nonvolatile memory device and memory system comprising same|
A nonvolatile memory device comprises a 3d memory cell array comprising multiple mats corresponding to different bit lines, each of the mats comprising multiple memory blocks, each of the memory blocks comprising multiple cell strings disposed perpendicular to a substrate and multiple string selection lines configured to select or unselect the cell strings, and each of the cell strings comprising at least one ground selection transistor, multiple memory cells, and at least one string selection transistor stacked in a direction perpendicular to the substrate. The nonvolatile memory device further comprises a string selection controller electrically connected to the mats through the string selection lines and configured to provide multiple string selection signals respectively corresponding to the string selection lines.
|Adaptive operation of multi level cell memory|
A multi level cell (mlc) nonvolatile memory is tested and, if it fails to meet an mlc specification, is reconfigured for operation as an slc memory by assigning two of the mlc memory cell states as slc states in a first slc mode, according to predefined sets of criteria. Subsequently, different mlc memory cell states are assigned as slc states in a second slc mode..
|Nonvolatile memory devices using variable resistive elements and related driving methods thereof|
Driving methods of a nonvolatile memory device are provided. The driving method includes providing a start pulse adjusted based on a previous write operation to a resistive memory cell to write data, verifying whether the data has accurately been written using the start pulse, and executing a write operation on the resistive memory cell by an incremental one-way write method or a decremental one-way write method according to the verify result.