|| List of recent Nonvolatile Memory-related patents
| Memory system|
According to one embodiment, a memory module which includes a plurality of nonvolatile memory cells with a plurality of pages and line-and-space word lines to which more than one of the memory cells are connected, and a controller which receives write data from a host device.. .
| Memory device and integrated circuit|
A memory device includes a nonvolatile memory, operated by using a plurality of voltages and configured to output stored repair information in response to a boot-up signal, a plurality of registers configured to store the repair information output from the nonvolatile memory, a plurality of memory banks configured to replace a normal cell with a redundancy cell using the repair information stored in registers corresponding to the plurality of memory banks among the plurality of registers, and a boot-up control circuit configured to activate the boot-up signal at a time of stabilization of the plurality of voltages.. .
To provide a microcontroller that can operate in a low power consumption mode. The microcontroller includes a cpu, a memory, and a peripheral circuit such as a timer circuit.
| Memory controller, method of operating memory controller, and system comprising memory controller|
A memory controller controls operation of a nonvolatile memory device comprising a memory area comprising a plurality of multi-level cells (mlcs). The memory controller receives an address of the memory area and data to be programmed to the memory area, analyzes access history information regarding the memory area based on the address, generates first mapping data corresponding to the data or second mapping data based on the data and previous mapping data that has been programmed to the mlcs according to a result of the analysis, and transmits a program command comprising one of the first mapping data and the second mapping data to the nonvolatile memory device..
| Information processing apparatus, information processing method, and program|
Provided is an information processing apparatus, including: a volatile memory; a nonvolatile memory including a rewritable area configured to store rewritable data, and a non-rewritable area configured to store non-rewritable data and a snapshot boot image, the snapshot boot image showing a home window corresponding to an execution status of the non-rewritable data; and a controller configured to load the rewritable data and the snapshot boot image into the volatile memory when booting, and to draw the home window based on difference information and the snapshot boot image, the difference information corresponding to difference data of the rewritable data before and after. .
| Memory system|
According to one embodiment, a memory system according to one embodiment is equipped with several nonvolatile memory chips and a memory controller that controls the nonvolatile memory chips based on a firmware. The firmware is written in a nonvolatile memory chip positioned the farthest distance from the memory controller..
| Heterogeneous data paths for systems having tiered memories|
A nonvolatile memory (“nvm”) buffer can be incorporated into an nvm system between a volatile memory buffer and an nvm to decrease the size of the volatile memory buffer and organize data for programming to the nvm. Heterogeneous data paths may be used for write and read operations such that the nonvolatile memory buffer is used only in certain situations..
| Method of forming nonvolatile memory device|
A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.. .
| Work function tailoring for nonvolatile memory applications|
Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.
| Nonvolatile memory device and operating method thereof|
A nonvolatile memory device includes a memory cell array including a main cell area and a retention flag cell area, a retention check unit configured to compare a read result for retention flag cells included in the retention flag cell area to a reference value, and determine a retention state of the retention flag cells according to a comparison result, and a control logic configured to provide a retention check result based on the retention state to the external device in response to a retention check request provided from an external device.. .
| Non-volatile memory devices and methods of manufacturing the same|
This technology relates to nonvolatile memory devices and methods of manufacturing the same. A nonvolatile memory device can include a memory cell array configured to include a plurality of strings, a page buffer unit connected to the plurality of strings, respectively, and configured to sense data, and a switching unit disposed between the memory cell array and the page buffer unit and configured to comprise a variable resistor..
| Programming method of nonvolatile memory device|
Provided is a programming method of a nonvolatile memory device which includes a plurality of strings each including a source select transistor, a plurality of memory cells, and a drain select transistor which are connected in series between a common source line and a bit line. The programming method includes: applying a first voltage to the common source line during a first period in which a channel of a plurality of memory cells of an unselected string is floated; and applying a second voltage increased more than the first in voltage to the common source line during a second period in which a selected memory cell is programmed, when a selected word line belongs to a word line group adjacent to the common source line..
| Nonvolatile memory device and operating method thereof|
A nonvolatile memory device includes: a page buffer block including a plurality of cache latches configured to temporarily store data inputted to program memory cells, and configured to program the inputted data into the memory cells; and a column decoder configured to provide column select signals for selecting the cache latches to the cache latches according to a column address, wherein the column decoder activates column select signals for selecting a part of the cache latches at substantially the same time, while data are set up in the cache latches.. .
| Storage device and control method of nonvolatile memory|
According to one embodiment, a storage device includes a nonvolatile memory, a controller configured to copy data stored in a first page in a first block to a second page in a second block, and an ecc circuit. The controller reads data from a part of the first page by using an upper limit voltage and lower limit voltage, performs a direct copy operation in the nonvolatile memory without via the ecc circuit if the number of error cells having threshold voltages higher than the lower limit voltage and lower than or equal to the upper limit voltage is less than or equal to a specified value, and performs error correction by using the ecc circuit if the number of error cells exceeds the specified value..
| Nonvolatile memory device and data storage device including the same|
A nonvolatile memory device includes: a plurality of memory cells arranged in a region where word lines and bit lines intersect, a data read/write circuit including a plurality of latches configured to temporarily store data inputted from an external device, and configured to perform a program operation on the memory cells based on data stored in the latches, and a skip data control unit configured to determine whether data to be programmed into the memory cells are available, and to store program-inhibit data in a latch corresponding to a memory cell which is determined to not contain any data.. .
| Read method for nonvolatile memory device, and data storage system using the same|
Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell.
| Nonvolatile memory device and sub-block managing method thereof|
A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate, the memory block being divided into sub-blocks configured to be erased independently.
| Nonvolatile memory element, nonvolatile memory device, and writing method for use in nonvolatile memory element|
In a nonvolatile memory element, when a voltage value of an electric pulse has a relationship of v2>v1>0 v>v3>v4 and a resistance value of a variable resistance layer has a relationship of r3>r2>r4>r1, the resistance value of the variable resistance layer becomes: r2, when the electric pulse having a voltage value of v2 or greater is applied between electrodes; r4, when the electric pulse having a voltage value of v4 or smaller is applied between the electrodes; r3, when the resistance value of the variable resistance layer is r2 and the electric pulse having a voltage value of v3 is applied between the electrodes; and r1, when the resistance value of the variable resistance layer is r4 and the electric pulse having a voltage value of v1 is applied between the electrodes.. .
| Nonvolatile memory apparatus and method for driving the same|
A method for driving a nonvolatile memory apparatus includes: a data storage preparation step of setting a write control voltage to a first level of voltage; a data storage step of driving a driving transistor through the write control voltage to generate a write current, and storing an external data in a memory cell through the write current; a data detection step of varying the write control voltage by a predetermined level from a preset voltage level, and reading the data stored in the memory cell; and a data verification step of determining whether the stored data coincides with the external data or not, and repeating the data storage step and the data detection step according to a result of the determining.. .
| Sheet conveying device capable of discharging sheet from conveying path at startup|
A sheet conveying device includes: a conveying unit; a nonvolatile memory; and a controller. The conveying unit is configured to convey a sheet along a conveying path.
| Image display apparatus and method for displaying image on display device|
An image display apparatus is coupled to a nonvolatile memory section, and includes an image processing part configured to display an image on a display device, an initial setting circuit, and a control register configured to control respective parts in the image display apparatus. At power-on or start-up of the image display apparatus, the initial setting circuit reads initialization data from the nonvolatile memory section and sets communication mode for communicating with the nonvolatile memory section to the control register.
| Non-volatile memory devices having charge storage layers at intersecting locations of word lines and active region|
Nonvolatile memory devices are provided. Devices include active regions that may be defined by device isolation layers formed on a semiconductor substrate and extend in a first direction.
| Nonvolatile memory device|
A non-volatile memory includes a channel layer to extend from a substrate in a vertical direction; a plurality of interlayer dielectric layers and a plurality of gate electrodes to be alternately stacked along the channel layer; and a memory layer to be interposed between the channel layer and each of the gate electrodes, wherein the memory layer comprises a tunnel dielectric layer to contact the channel layer, a first charge trap layer to contact the tunnel dielectric layer and formed of an insulating material, a charge storage layer to contact the first charge trap layer and formed of a semiconducting material or a conductive material, a second charge trap layer to contact the charge storage layer and formed of an insulating material, and a charge blocking layer to contact the second charge trap layer.. .
| Nonvolatile memory device and method for fabricating the same|
A nonvolatile memory device includes a plurality of gate structures, each gate structure formed over a substrate and including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate, which are sequentially stacked, and an interlayer dielectric layer covering the plurality of gate structures and having an air gap formed between adjacent gate structures, wherein the bottom surface of the air gap is positioned at a lower level than the surface of the tunnel insulating layer.. .
| Nonvolatile memory device and method of manufacturing the same|
In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate.
| Nonvolatile memory device and method for fabricating the same|
A nonvolatile memory device includes gate structures formed over a substrate, each gate structure including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate that are sequentially stacked, a protective layer formed on sidewalls of the floating gate, and a second insulating layer covering the gate structures and having an air gap formed between the gate structures, wherein an adhesive strength between the second insulating layer and the protective layer is smaller than an adhesive strength between the second insulating layer and the gate structure.. .
| Nonvolatile memory element and nonvolatile memory device|
A variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer including: a first oxide layer including a metal oxide having non-stoichiometric composition and including p-type carriers; a second oxide layer located between and in contact with the first oxide layer and a second electrode and including a metal oxide having non-stoichiometric composition and including n-type carriers; an oxygen reservoir region located in the first oxide layer, having no contact with the first electrode, and having an oxygen content atomic percentage higher than that of the first oxide layer; and a local region located in the second oxide layer, having contact with the oxygen reservoir region, and having an oxygen content atomic percentage lower than that of the second oxide layer.. .
| Nonvolatile memory element, nonvolatile memory device, and methods of manufacturing the same|
A nonvolatile memory element includes: a lower electrode formed above a substrate; a first variable resistance layer formed above the lower electrode and comprising a first metal oxide; a second variable resistance layer formed above the first variable resistance layer and comprising a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide; and an upper electrode formed above the second variable resistance layer. A single step is formed in an interface between the first variable resistance layer and the second variable resistance layer.
| Nonvolatile memory device|
According to one embodiment, a nonvolatile memory device includes a first wiring, a second wiring, and a memory cell provided between the first wiring and the second wiring. The memory cell includes a memory layer, a rectifying element layer, and a protective resistance layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type..
| Nonvolatile memory|
A nonvolatile memory according to an embodiment includes a first wiring line; a second wiring line arranged above the first wiring line and extending in a direction crossing the first wiring line; and a resistance change layer arranged in an intersection region of the first wiring line the second wiring line, the second wiring line including a first member extending in the direction in which the second wiring line extends, and an electrode layer containing a metal element arranged on a side surface of the first member along the direction in which the second wiring line extends, a lower surface of the electrode layer being in contact with an upper surface of the resistance change layer.. .
|Information processing apparatus and activation method|
An information processing apparatus manages activation of a program by a task which is a unit of execution, and executes a task for each sequence in units of process block. The information processing apparatus has a nonvolatile memory which keeps an execution state management table.
|Integrated circuitry comprising nonvolatile memory cells and methods of forming a nonvolatile memory cell|
An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material.
|Method and system for switchable erase or write operations in nonvolatile memory|
Embodiments relate to systems and methods including a step of switching between two or more erase operations and/or two or more write operations for erasing of and/or writing to least one memory cell of a nonvolatile memory enabling to select a most suitable erase and/or write operation for a particular erase and/or write operation within the memory.. .
|Very dense nonvolatile memory bitcell|
An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type.
|Nonvolatile memory device and method for driving the same|
A nonvolatile memory includes a memory cell array including a plurality of nonvolatile memory cells connected to bit lines and word lines crossing the bit lines, a voltage driver configured to provide a word line voltage to the word lines and provide a first voltage during a precharging operation and a second voltage during a sensing operation, based on a voltage setting signal, and a page buffer unit configured to adjust a precharging level of a sensing node connected to a bit line of a page included in a selected memory block of the memory cell array using the first voltage and adjust a sensing level of the sensing node using the second voltage.. .
|Nonvolatile memory device and nonvolatile memory system including the same|
A nonvolatile memory device includes a cell array including a plurality of pages, a selection unit configured to select one of the pages in response to a page selection address, an operation control unit configured to read data of a given number of pages adjacent to the selected page and output the read data as backup data, to erase data of the selected page, in response to a page erase command, and to reprogram update data and the backup data in the selected page and the adjacent pages, respectively, and a data storage unit configured to store the backup data.. .
|Nonvolatile memory device having near/far memory cell groupings and data processing method|
A nonvolatile memory device includes; a memory cell array designating a first memory cell group including first memory cells connected with a word line and disposed less than a reference distance from a word line voltage source in a word line direction, and a second memory cell group including second memory cells connected to the word line and disposed more than the reference distance from the word line voltage source in the word line direction, and control logic configured during a data processing operation to provide a first word line voltage to a first target memory cell among the first memory cells, and a second word line voltage different from the first word line voltage to a second target memory cell among the second memory cells.. .
|Method for reading data from nonvolatile memory element, and nonvolatile memory device|
A method for reading data from a nonvolatile memory element including a first electrode, a second electrode, and a variable resistance layer which includes a local region having a higher degree of oxygen deficiency than a surrounding region, the method including: applying a third voltage pulse between the first electrode and the second electrode, the third voltage pulse having a voltage with an absolute value smaller than absolute values of voltages of the first voltage pulse and the second voltage pulse; and reading the resistance state of the variable resistance layer by applying a fourth voltage pulse between the first electrode and the second electrode after the applying of a third voltage pulse, the fourth voltage pulse having a voltage with an absolute value smaller than the absolute values of the voltages of the first voltage pulse and the second voltage pulse.. .
|Variable resistance nonvolatile memory device, and accessing method for variable resistance nonvolatile memory device|
A variable resistance nonvolatile memory device includes: bit lines in layers; word lines in layers formed at intervals between the layers of the bit lines; a memory cell array including basic array planes and having memory cells formed at crosspoints of the bit lines in the layers and the word lines in the layers; global bit lines provided in one-to-one correspondence with the basic array planes; and sets provided in one-to-one correspondence with the basic array planes, and each including a first selection switch element and a second selection switch element, wherein memory cells connected to the same word line are successively accessed in different basic array planes, and memory cells are selected so that voltages applied to the word line and bit lines are not changed and a direction in which current flows through the memory cells is the same.. .
|One-bit memory cell for nonvolatile memory and associated controlling method|
A one-bit memory cell for a nonvolatile memory includes a bit line and a plurality of serially-connected storage units. The bit line is connected to the serially-connected storage units.
|Nonvolatile memory device and method for fabricating the same|
This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers.
|Nonvolatile memory device and method for fabricating the same|
This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each connected with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and metal silicide layers configured to be in contact with the pipe connection gate electrode.
|Nonvolatile memory device and method of fabricating the same|
This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a bottom buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled to the pipe channel layer and extended in a direction substantially perpendicular to the substrate, and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, wherein the pipe connection gate electrode includes a metal silicide layer formed within the groove.
|Nonvolatile memory device and method of fabricating the same|
This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and etch stop layers including metal silicide and formed over the pipe connection gate electrode..
|Film formation method and nonvolatile memory device|
According to one embodiment, a film formation method can include irradiating a layer to be processed provided on an underlayer with an ionized gas cluster containing any one of oxygen and nitrogen to modify at least part of the layer.. .
|Defect enhancement of a switching layer in a nonvolatile resistive memory element|
Embodiments of the invention set forth a nonvolatile memory element with a novel variable resistance layer and methods of forming the same. The novel variable resistance layer includes a metal-rich host oxide that operates with a reduced switching voltage and current and requires significantly reduced forming voltage when manufactured.
|Memory system and bus switch|
A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an mpu that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.. .
|Memory device having an integrated two-terminal current limiting resistor|
A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device.
|Nonvolatile memory elements|
Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer.
|Nonvolatile semiconductor memory device|
A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line.
|Nonvolatile memory element and nonvolatile memory device|
A nonvolatile memory element includes: a first electrode; a second electrode; and a variable resistance layer comprising a metal oxide positioned between the first electrode and the second electrode. The variable resistance layer includes: a first oxide layer having a resistivity ρx, on the first electrode; a second oxide layer having a resistivity ρy (ρx<ρy), on the first oxide layer; a third oxide layer having a resistivity ρz (ρy<ρz), on the second oxide layer; and a localized region that is positioned in the third oxide layer and the second oxide layer to be in contact with the second electrode and not to be in contact with the first oxide layer, and is, in resistivity, lower than the third oxide layer and different from the second oxide layer..
|Nonvolatile memory apparatus and method of operating the same|
Nonvolatile memory apparatuses and methods of operating the same. A nonvolatile memory apparatus includes a nonvolatile memory cell array including a plurality of memory cells; an address decoder configured to receive computation data that indicates a computation from among a plurality of computations and an input data for computation, and the address decoder configured to output an address of the nonvolatile memory cell array corresponding to the indicated computation and input data, the nonvolatile memory cell array being configured to output result data stored at the output address, the result data corresponding to a previous computation performed before receipt of the computation data; and a reading unit configured to read the result data output from the nonvolatile memory cell array..
|Variable resistance nonvolatile memory device and driving method of variable resistance nonvolatile memory device|
A stable operation is implemented by reducing an abnormal current. A variable resistance nonvolatile memory device includes: a memory cell array having memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional cross point of one of bit lines and one of word lines, and the current steering element being assumed to be conducting when a voltage exceeding a predetermined threshold voltage is applied; and a detection circuit that detects a faulty memory cell that is in a second low resistance state where a resistance value is lower than a resistance value in a first low resistance state.
|Nonvolatile memory device and a method for fabricating the same|
A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.. .
|Storage element, storage device, and signal processing circuit|
A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit.
|Invisible/transparent nonvolatile memory|
An optically transparent memory device comprises first and second electrodes, wherein the electrodes are formed from conductive material(s) that is transparent. The memory device also provides a resistive memory layer coupled to the first and second electrodes.
|Control device for vehicle and error processing method in control device for vehicle|
A control device for a vehicle including a nonvolatile memory which is electrically erasable and writable detects, on start-up, whether or not an error occurs in updated data read from the nonvolatile memory, and when an error has been detected, performs a reset after saving error information. When being restarted by the reset, the control device for a vehicle determines on the basis of the error information whether or not there is updated data in which an error has occurred, and when there is updated data in which an error has occurred, overwrites the updated data with a fixed value prior to the error detection.
|Nonvolatile memory device and method of controlling suspension of command execution of the same|
A nonvolatile memory device includes a memory cell array, a row decoder, a page buffer, and control logic. The memory cell array includes memory cells connected to word lines and bit lines, the memory cell array being configured to store data.
|Nonvolatile memory device and programming method|
A non-volatile memory (nvm) includes a memory cell array of multi-level memory cells (mlc) arranged in physical pages. A programming method for the nvm includes; receiving first data and partitioning the first data according to a single bit page capacity of a physical page to generate partitioned first data, programming the partitioned first data as single-bit data to a plurality of physical pages, and receiving second data and programming the second data as multi-bit data to a selected physical page among the plurality of physical pages, wherein the second data is simultaneously programmed to the mlc of the selected physical page..
|Method for fabricating nonvolatile memory device|
A method for fabricating a nonvolatile memory device includes forming a structure having a plurality of first interlayer insulating layers and a plurality of sacrificial layers alternately stacked over a substrate, forming main channel holes configured to penetrate the structure, sequentially forming a preliminary charge trap layer, a tunnel insulating layer, and a channel layer on the inner walls of the main channel holes, forming a trench configured to penetrate the plurality of sacrificial layers on both sides of each of the main channel holes, and forming insulating oxide layers by oxidizing the preliminary charge trap layer on inner sides of the first interlayer insulating layers. In accordance with this technology, since the charge trap layer is separated for each memory cell, the spread of charges may be prevented and the reliability of a nonvolatile memory device may be improved..
|Sense amplifier circuit for nonvolatile memory|
A sense amplifier circuit for a nonvolatile memory that includes a first amplifier to perform a switching operation to output a first signal on a sense amplifier based logic (sabl) node depending on the state of a sensing enable signal, a second amplifier to perform a switching operation to output a second signal on the sabl node depending on the state of the sensing enable signal, a current mirror that sinks current on the sabl node depending on the sensing enable signal and a bit line signal, and an inverter arranged to output the signal on the sabl node as a data signal.. .
|Nonvolatile memory device and method for voltage trimming thereof|
A non-volatile semiconductor storage device includes memory blocks that each includes multiple memory strings. A bit line connects to an end of each string in the memory blocks and to a sense amplifier circuit which includes a first transistor.
|Memory system comprising nonvolatile memory device and related method of operation|
A memory system performs a first sensing operation to sense whether multi-level cells assume an on-cell state or an off-cell state in response to a first read voltage applied to a selected word line. It then supplies a pre-charge voltage to bit lines corresponding to multi-level cells that have been sensed as assuming the off-cell state in response to the first read voltage, and it performs a second sensing operation with the supplied pre-charge voltage to sense whether each of the multi-level cells that have been sensed as assuming the off-cell state assumes an on-cell state or an off-cell state in response to a second read voltage applied to the selected word line..
|Nonvolatile memory device and operating method with variable memory cell state definitions|
A method operating a nonvolatile memory device includes successively programming a memory cell without physically erasing the memory cell. Each successive programming of the memory cell uses a different erase state region to indicate an erase state for the memory cell..
|Storage device and control method of nonvolatile memory|
According to one embodiment, a storage device includes a nonvolatile memory including physical sectors each of which comprises memory cells commonly connected to a word line, each of the memory cells being capable of storing data of not less than 2 bits, each of the physical sectors including pages corresponding to the number of bits storable in the memory cell, and a controller configured to receive a first write command and to write data associated with the first write command to the nonvolatile memory. In a write process using the first write command, the controller is configured to skip an upper page of a physical sector whose lower page is write-accessed by a second write command prior to the first write command..
|Common line current for program level determination in flash memory|
In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—is determined from the total current passing through the population of memory cells under read conditions, as observed on a common line, for example a source line in nand flash memory.. .
|Aggregating data latches for program level determination|
In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results..
|Semiconductor memory device having variable resistance memory and operating method|
A semiconductor memory device includes a memory cell array of nonvolatile memory cells having a variable resistance element, and a conductor line array capable of generating a compensation magnetic field for the nonvolatile memory cells. A current driver selectively supplies current to conductive lines, a magnetic field sensor senses an applied external magnetic field and generates external magnetic field information, and a controller controls generation of the compensation magnetic field in response to the external magnetic field information..
|Nonvolatile corruption resistent magnetic memory and method thereof|
A method and system for storing information in a nonvolatile memory comprising: a substrate comprising magnetic material operatively associated therewith, the magnetic material having at least one first portion of low permeability and at least one second portion of high permeability; a reader comprising a sensor for reading information by measuring the magnetic permeability for the at least one first portion and the at least one second portion; whereby the at least one first and second portions are subjected to a magnetic probe field from one of an external source, the sensor, or a combination of an external source and the sensor.. .
|Three-dimensional semiconductor memory devices|
Three-dimensional (3d) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., p-type) therein and a common source region of first conductivity type (e.g., n-type) on the well region. A recess extends partially (or completely) through the common source region.
|Nonvolatile memory device and method for fabricating the same|
A nonvolatile memory device may include a plurality of channel layers protruded substantially perpendicularly over a substrate having a well region, a structure configured to have a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked along each of the plurality of channel layers, a plurality of memory layers interposed respectively between each of the plurality of channel layers and each of the plurality of gate electrodes, a source line formed in the substrate between a plurality of the structures, a plurality of source contact plugs placed between the plurality of structures and connected with the source line, and a well pickup contact plug placed between the plurality of structures and connected with the well region.. .
|Resistive-switching nonvolatile memory elements|
Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer.