|| List of recent Nonvolatile Memory-related patents
| Microcontroller and method for manufacturing the same|
A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a cpu, a memory, and a peripheral circuit such as a timer circuit.
| Power management integrated circuit and operating method thereof|
A power management integrated circuit includes a nonvolatile memory configured to store code data for driving the power management integrated circuit; a processor configured to execute program data stored at a volatile memory; and a decompression logic separated from the processor, the decompression logic being formed of hardware, configured to decompress the code data to generate program data, and configured to store the program data at the volatile memory.. .
| Controllers controlling nonvolatile memory devices and operating methods for controllers|
An operating method of a controller includes selecting bits of code word to be punctured; detecting locations of incapable bits of an input word based on locations of the bits to be punctured and a structure of a generation matrix calculation unit; refreezing the input word such that frozen bits and incapable bits of the input word overlap; generating input word bits by replacing information word bits with frozen bits based on the refreezing result; generating the code word by performing generation matrix calculation on the input word bits; generating output bits by puncturing the code word based on locations of the bits to be punctured; and transmitting the output bits to a nonvolatile memory device.. .
| Data storage architecture and system for high performance computing|
Data storage systems and methods for storing data are described herein. The storage system may be integrated with or coupled with a compute cluster or super computer having multiple computing nodes.
| Marine vessel steering system|
A marine vessel steering system includes a basic target turning angle computing unit that computes a basic target turning angle δo* common to two outboard motors based on a steering angle θ detected by a steering angle sensor. A traveling state determining unit determines whether a traveling state of a marine vessel is a straight traveling state based on the received basic target turning angle δo*.
| Nonvolatile memory devices|
A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors.
| Programming nonvolatile memory device using program voltage with variable offset|
A method of programming a nonvolatile memory device comprises applying at least one test program pulse to selected memory cells located in a scan read area, performing a scan read operation on the selected memory cells following application of the at least one test program pulse to detect at least one one-shot upper cell, calculating an offset voltage corresponding to a scan read region at which the scan read operation is performed, setting a program start bias using the offset voltage, and executing at least one program loop using the program start bias.. .
| Split block decoder for a nonvolatile memory device|
A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address.
| Nonvolatile memory devices and methods forming the same|
Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line.
| Nonvolatile memory device and method of performing forming the same|
A nonvolatile memory device including a control unit configured to read resistance value information for each of memory cells as initial resistance value information and store it temporarily before a voltage pulse for forming is applied, to set resistance value information as a threshold value serving as a target for completion of the forming, the resistance value information being obtained by multiplying the initial resistance value information by a predetermined coefficient, and to repeat application of the voltage pulse for forming and reading of the resistance value information until a resistance value indicated by the resistance value information on the memory cell becomes lower than a resistance value indicated by the threshold value.. .
| Cross-point variable resistance nonvolatile memory device and reading method for cross-point variable resistance nonvolatile memory device|
A cross-point variable resistance nonvolatile memory device comprises: a memory cell array; a column decoder and pre-charge circuit which pre-charges a selected word line to a first voltage in a period p1 among the period p1, a period p2, and a period s that are included in this order in a read operation of a memory cell; a low decoder driver which pre-charges a selected word line to the first voltage in the periods p1 and p2 and sets the selected word line to a third voltage different from the first voltage in the period s; a feedback controlled bit line voltage clamp circuit which sets the selected bit line to a second voltage in the periods p2 and s; and a sense amplifier which determines the resistance state in a memory cell at a cross-point of the selected word line and the selected bit line in the period s.. .
| Low cost high density nonvolatile memory array device employing thin film transistors and back to back schottky diodes|
An improved crosspoint memory array device comprising a plurality of memory cells, each memory cell being disposed at an intersection region of bit and word conductive lines, electrically coupled to one of the first conductive lines at a first terminal and to one of the second conductive lines at a second terminal, and comprising a controllable electrical resistance, wherein a back to back schottky diode is located between each memory cell and one of the said conductive lines, and wherein each conductive line is electrically coupled to at least two thin film transistors (tfts). The device is substantially produced in beol facilities without need of front end semiconductor production facilities, yet can be made with ultra high density and low cost..
|Non-volatile memory device having adjustable read voltage, memory system comprising same, and method of operating same|
A nonvolatile memory device comprises a memory cell array comprising a selected page comprising multiple error correction code (ecc) units, and a voltage generation unit configured to generate a read voltage to read data from the selected page. Read voltage levels are set individually for the respective ecc units according to data detection results for each of the ecc units.
|Common hot spare for multiple raid groups|
A storage system assigns one or more large disks in a storage enclosure as a common dedicated hot spare that is used by multiple raid groups. Storage space equivalent to the smallest physical disk in a raid group is allocated on the common dedicated hot spare.
|Memory system and read reclaim method thereof|
A memory system includes a nonvolatile memory device including a first memory area formed of memory blocks which store n-bit data per cell and a second memory area formed of memory blocks which store m-bit data per cell, where n and m are different integers, and a memory controller configured to control the nonvolatile memory device. The memory controller is configured to execute a read operation, and to execute a read reclaim operation in which valid data of a target memory block of the second memory area is transferred to one or more memory blocks of the first memory area, the target memory block selected during the read operation.
|Systems and methods for nonvolatile memory performance throttling|
Systems and methods for nonvolatile memory (“nvm”) performance throttling are disclosed. Performance of an nvm system may be throttled to achieve particular data retention requirements.
|Main memory system storing operating system program and computer system including the same|
A main memory system is provided which includes a nonvolatile memory including a first memory area designated to store an operating system program and a second memory area designated to store user data; and a memory controller configured to control the nonvolatile memory such that the operating system program is loaded onto the second memory area from the first memory area. The nonvolatile memory may be one of a phase change ram, a resistive ram, and a magnetic ram..
|Cross point variable resistance nonvolatile memory device|
Each memory cell is formed at a different one of cross points of bit lines extending in an x direction and formed in a plurality of layers and word lines extending in a y direction. In a multilayer cross point structure in which a plurality of vertical array planes sharing the word lines are aligned in the y direction each for a group of bit lines aligned in a z direction, even and odd layer bit line selection switch elements switch connection and disconnection between a global bit line and the commonly-connected even layer bit line and the commonly-connected odd layer bit line, respectively.
|Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors|
Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., nand-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines..
|Nonvolatile memory device, operating method thereof and memory system including the same|
A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (ssls), the memory cells associated with the plurality of ssls constituting a memory block, and verifying the erasing operation to second memory cells associated with a second ssl after verifying the erasing operation to first memory cells associated with a first ssl.. .
|Cross-point variable resistance nonvolatile memory device|
A cross-point memory device including memory cells each includes: a variable resistance element that reversibly changes at least between a low resistance state and a high resistance state; and a current steering element that has nonlinear current-voltage characteristics, and the cross-point memory device comprises a read circuit which includes: a reference voltage generation circuit which comprises at least the current steering element; a differential amplifier circuit which performs current amplification on an output voltage in the reference voltage generation circuit; a feedback controlled bit line voltage clamp circuit which sets the low voltage side reference voltage to increase with an output of the differential amplifier circuit; and a sense amplifier circuit which determines a resistance state of a selected memory cell according to an amount of current flowing through the selected memory cell.. .
|Storage system and storage control method|
A storage system includes a plurality of nonvolatile memory devices that each includes a plurality of nonvolatile memory chips, and a storage controller configured to perform input and output of data to and from a raid group comprised by storage areas of the plurality of nonvolatile memory devices. A nonvolatile memory device identifies a failure occurrence area that is a storage area in which a failure occurred in the plurality of nonvolatile memory chips, excludes the failure occurrence area from a storage area allocated to the raid group, and transmits failure occurrence information that is information relating to the failure that has occurred in the nonvolatile memory device to the storage controller.
|Key information generation device and key information generation method|
In initial generation (for example, shipping from the factory), a security device generates an identifier w specific to the security device, with the puf technology, generates key information k (k=hf(k)) from the identifier w, generates encrypted confidential information x by encrypting (x=enc(mk, k)) confidential information mk with the key information k, and stores the encrypted confidential information x and an authentication code h (h=hf′(k)) of the key information k, in a nonvolatile memory. In operation, the security device generates the identifier w with the puf technology, generates the key information k from the identifier w, and decrypts the encrypted confidential information x with the key information k.
|Methods of manufacturing vertical structure nonvolatile memory devices|
A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer.
|Nonvolatile semiconductor memory device|
This nonvolatile semiconductor memory device comprises a transistor string formed on a substrate and including a plurality of first transistors connected in series with each other. A first bit line is connected to a first end of the transistor string.
|Nonvolatile memory device|
|Nonvolatile memory device|
According to one embodiment, a nonvolatile memory device includes: a magnetic memory element and a control unit. The magnetic memory element includes a stacked body, and a first and a second stacked units.
|Nonvolatile memory device and method for fabricating the same|
A nonvolatile memory device includes an insulating pattern extending in a first direction, a conductive pattern on the insulating pattern, and an electrode structure extending in the first direction. The electrode structure is adjacent the insulating pattern and conductive pattern, and includes an alternating pattern of gate electrodes and interlayer insulating films.
|Defect gradient to boost nonvolatile memory performance|
Embodiments of the present invention generally relate to a resistive switching nonvolatile memory element that is formed in a resistive switching memory device that may be used in a memory array to store digital data. The memory element is generally constructed as a metal-insulator-metal stack.
|Methods of performing error detection/correction in nonvolatile memory devices|
Methods of operating nonvolatile memory devices include testing strings of nonvolatile memory cells in the memory device to identify at least one weak string therein having a higher probability of yielding erroneous read data error relative to other strings. An identity of the at least one weak string may be stored as weak column information, which may be used to facilitate error detection and correction operations.
|Error correcting for improving reliability by combination of storage system and flash memory device|
According to this invention, a highly reliable memory device that uses up a life of a flash memory can be provided. The memory device is a nonvolatile memory device including a plurality of memory cells, in which: each of the plurality of memory cells is an fet which includes a floating gate; the plurality of memory cells are divided into a plurality of deletion blocks; and the nonvolatile memory device reads data stored in a first deletion block, detects and corrects an error contained in the read data, stores, when the number of bits of the detected error exceeds a threshold, the corrected data in a second deletion block, sets a smaller value as the threshold as an error frequency detected in the first deletion block is higher, and sets a smaller value as the threshold as the number of deletion times executed in the first deletion block is larger..
|Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory|
A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory.
|Data security for digital data storage|
A computing system includes data encryption in the data path between a data source and data storage devices. The data encryption may utilize a key which is derived at least in part from an identification code stored in a nonvolatile memory.
|Memory system having memory ranks and related tuning method|
A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.. .
|Crosspoint nonvolatile memory device and method of driving the same|
The nonvolatile memory device includes a control circuit that controls a sense amplification circuit and a writing circuit. The control circuit changes a value of at least one of (a) a load current and (b) a forming pulse current or a forming pulse voltage, according to a total number of sneak current paths formed by memory cells each including a variable resistance element in a second resistance state having a low resistance value except a selected memory cell in a memory cell array..
|Variable resistance nonvolatile memory element writing method and variable resistance nonvolatile memory device|
Provided is a method of writing to a variable resistance nonvolatile memory element which is capable of both improving retention characteristics and enlarging a window of operation. In the method of writing, to write “1” data (lr), first a weak hr writing process is performed in which a weak hr writing voltage pulse set for changing the variable resistance nonvolatile memory element to an intermediate resistance state is applied and, subsequently, a lr writing process is performed in which a lr writing voltage pulse set for changing the variable resistance nonvolatile memory element from the intermediate resistance state to a lr state is applied..
|Embedded nonvolatile memory elements having resistive switching characteristics|
Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer.
|Nonvolatile memory element and method of manufacturing nonvolatile memory element|
A nonvolatile memory element includes: a first electrode; a second electrode; and a variable resistance layer between the first and second electrodes. The variable resistance layer having a resistance value that reversibly changes according to an electrical signal provided between the electrodes.
|Interface for storage device access over memory bus|
A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices.
|Controller of a nonvolatile memory device and a command scheduling method thereof|
A controller which includes a working memory on which a command scheduler is loaded; and a processor configured to load at least one mapping table from a mapping table array onto the working memory. The command scheduler reorders commands provided from a host based on logical block addresses, and the processor loads at least one other mapping table onto the working memory according to logical block addresses of the commands reordered by the command scheduler..
|Storage device and method for controlling the same|
A storage device according to an embodiment includes: a host interface connected to a host; a memory including a first buffer that stores a logical address range designated by an invalidation instruction received from the host via the host interface and a second buffer that stores an internal logical address range which is an area combination with the logical address range; a nonvolatile memory; and a controller. The controller includes: an invalidation instruction processor that stores the logical address range designated by the invalidation instruction in the first buffer; an area combination executor that generates the internal logical address range by the area combination with the logical address range and stores the internal logical address range in the second buffer; and an invalidation executor that executes invalidation processing on the nonvolatile memory based on the internal logical address range..
|Atomic layer deposition of metal oxide materials for memory applications|
Embodiments of the invention generally relate to nonvolatile memory devices, such as a reram cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ald) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes.
|Nonvolatile memory device|
According to an embodiment, a nonvolatile memory device includes a plurality of memory cell strings disposed in parallel in a first direction, a bit line and a first contact plug. Each of the memory cell strings extends in a second direction orthogonal to the first direction and includes a plurality of memory cells disposed in parallel in the second direction.
|Nonvolatile memory systems with embedded fast read and write memories|
A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system..
|Nonvolatile memory module, memory system including nonvolatile memory module, and controlling method of nonvolatile memory module|
A memory system is provided, which includes a nonvolatile memory module including a plurality of nonvolatile memory devices, and a memory module controller configured to control the nonvolatile memory module. At least two nonvolatile memory devices of the plurality of nonvolatile memory devices are configured to store serial presence detect (spd) information.
|Memory system including nonvolatile memory device and control method thereof|
A memory system is provided including a host configured to generate data bit inversion (dbi) information of data according to a major bit of the data, and a nonvolatile memory device configured to invert one or more bits of the data according to the dbi information, and to program the dbi information and the data. A control method of a memory system comprises generating dbi information according to the number of “1” bits of data relative to the number of “0” bits of the data, transferring the data and the dbi information, and inverting bits of the data according to the dbi information, the inverted bits of the data being programmed at the nonvolatile memory device..
|Nonvolatile memory device and method for manufacturing same|
According to an embodiment, a nonvolatile memory device includes a memory cell string, a control gate, first and second insulating films. The memory cell string includes a semiconductor layer and a plurality of memory cells disposed on the semiconductor layer.
|Nonvolatile memory device|
According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, a variable resistance layer. The variable resistance layer is provided between the first electrode and the second electrode.
According to one embodiment, a memory module which includes a plurality of nonvolatile memory cells with a plurality of pages and line-and-space word lines to which more than one of the memory cells are connected, and a controller which receives write data from a host device.. .
|Memory device and integrated circuit|
A memory device includes a nonvolatile memory, operated by using a plurality of voltages and configured to output stored repair information in response to a boot-up signal, a plurality of registers configured to store the repair information output from the nonvolatile memory, a plurality of memory banks configured to replace a normal cell with a redundancy cell using the repair information stored in registers corresponding to the plurality of memory banks among the plurality of registers, and a boot-up control circuit configured to activate the boot-up signal at a time of stabilization of the plurality of voltages.. .
To provide a microcontroller that can operate in a low power consumption mode. The microcontroller includes a cpu, a memory, and a peripheral circuit such as a timer circuit.
|Memory controller, method of operating memory controller, and system comprising memory controller|
A memory controller controls operation of a nonvolatile memory device comprising a memory area comprising a plurality of multi-level cells (mlcs). The memory controller receives an address of the memory area and data to be programmed to the memory area, analyzes access history information regarding the memory area based on the address, generates first mapping data corresponding to the data or second mapping data based on the data and previous mapping data that has been programmed to the mlcs according to a result of the analysis, and transmits a program command comprising one of the first mapping data and the second mapping data to the nonvolatile memory device..
|Information processing apparatus, information processing method, and program|
Provided is an information processing apparatus, including: a volatile memory; a nonvolatile memory including a rewritable area configured to store rewritable data, and a non-rewritable area configured to store non-rewritable data and a snapshot boot image, the snapshot boot image showing a home window corresponding to an execution status of the non-rewritable data; and a controller configured to load the rewritable data and the snapshot boot image into the volatile memory when booting, and to draw the home window based on difference information and the snapshot boot image, the difference information corresponding to difference data of the rewritable data before and after. .
According to one embodiment, a memory system according to one embodiment is equipped with several nonvolatile memory chips and a memory controller that controls the nonvolatile memory chips based on a firmware. The firmware is written in a nonvolatile memory chip positioned the farthest distance from the memory controller..
|Heterogeneous data paths for systems having tiered memories|
A nonvolatile memory (“nvm”) buffer can be incorporated into an nvm system between a volatile memory buffer and an nvm to decrease the size of the volatile memory buffer and organize data for programming to the nvm. Heterogeneous data paths may be used for write and read operations such that the nonvolatile memory buffer is used only in certain situations..
|Method of forming nonvolatile memory device|
A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.. .
|Work function tailoring for nonvolatile memory applications|
Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.
|Nonvolatile memory device and operating method thereof|
A nonvolatile memory device includes a memory cell array including a main cell area and a retention flag cell area, a retention check unit configured to compare a read result for retention flag cells included in the retention flag cell area to a reference value, and determine a retention state of the retention flag cells according to a comparison result, and a control logic configured to provide a retention check result based on the retention state to the external device in response to a retention check request provided from an external device.. .
|Non-volatile memory devices and methods of manufacturing the same|
This technology relates to nonvolatile memory devices and methods of manufacturing the same. A nonvolatile memory device can include a memory cell array configured to include a plurality of strings, a page buffer unit connected to the plurality of strings, respectively, and configured to sense data, and a switching unit disposed between the memory cell array and the page buffer unit and configured to comprise a variable resistor..
|Programming method of nonvolatile memory device|
Provided is a programming method of a nonvolatile memory device which includes a plurality of strings each including a source select transistor, a plurality of memory cells, and a drain select transistor which are connected in series between a common source line and a bit line. The programming method includes: applying a first voltage to the common source line during a first period in which a channel of a plurality of memory cells of an unselected string is floated; and applying a second voltage increased more than the first in voltage to the common source line during a second period in which a selected memory cell is programmed, when a selected word line belongs to a word line group adjacent to the common source line..
|Nonvolatile memory device and operating method thereof|
A nonvolatile memory device includes: a page buffer block including a plurality of cache latches configured to temporarily store data inputted to program memory cells, and configured to program the inputted data into the memory cells; and a column decoder configured to provide column select signals for selecting the cache latches to the cache latches according to a column address, wherein the column decoder activates column select signals for selecting a part of the cache latches at substantially the same time, while data are set up in the cache latches.. .
|Storage device and control method of nonvolatile memory|
According to one embodiment, a storage device includes a nonvolatile memory, a controller configured to copy data stored in a first page in a first block to a second page in a second block, and an ecc circuit. The controller reads data from a part of the first page by using an upper limit voltage and lower limit voltage, performs a direct copy operation in the nonvolatile memory without via the ecc circuit if the number of error cells having threshold voltages higher than the lower limit voltage and lower than or equal to the upper limit voltage is less than or equal to a specified value, and performs error correction by using the ecc circuit if the number of error cells exceeds the specified value..
|Nonvolatile memory device and data storage device including the same|
A nonvolatile memory device includes: a plurality of memory cells arranged in a region where word lines and bit lines intersect, a data read/write circuit including a plurality of latches configured to temporarily store data inputted from an external device, and configured to perform a program operation on the memory cells based on data stored in the latches, and a skip data control unit configured to determine whether data to be programmed into the memory cells are available, and to store program-inhibit data in a latch corresponding to a memory cell which is determined to not contain any data.. .
|Read method for nonvolatile memory device, and data storage system using the same|
Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell.
|Nonvolatile memory device and sub-block managing method thereof|
A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate, the memory block being divided into sub-blocks configured to be erased independently.
|Nonvolatile memory element, nonvolatile memory device, and writing method for use in nonvolatile memory element|
In a nonvolatile memory element, when a voltage value of an electric pulse has a relationship of v2>v1>0 v>v3>v4 and a resistance value of a variable resistance layer has a relationship of r3>r2>r4>r1, the resistance value of the variable resistance layer becomes: r2, when the electric pulse having a voltage value of v2 or greater is applied between electrodes; r4, when the electric pulse having a voltage value of v4 or smaller is applied between the electrodes; r3, when the resistance value of the variable resistance layer is r2 and the electric pulse having a voltage value of v3 is applied between the electrodes; and r1, when the resistance value of the variable resistance layer is r4 and the electric pulse having a voltage value of v1 is applied between the electrodes.. .
|Nonvolatile memory apparatus and method for driving the same|
A method for driving a nonvolatile memory apparatus includes: a data storage preparation step of setting a write control voltage to a first level of voltage; a data storage step of driving a driving transistor through the write control voltage to generate a write current, and storing an external data in a memory cell through the write current; a data detection step of varying the write control voltage by a predetermined level from a preset voltage level, and reading the data stored in the memory cell; and a data verification step of determining whether the stored data coincides with the external data or not, and repeating the data storage step and the data detection step according to a result of the determining.. .
|Sheet conveying device capable of discharging sheet from conveying path at startup|
A sheet conveying device includes: a conveying unit; a nonvolatile memory; and a controller. The conveying unit is configured to convey a sheet along a conveying path.
|Image display apparatus and method for displaying image on display device|
An image display apparatus is coupled to a nonvolatile memory section, and includes an image processing part configured to display an image on a display device, an initial setting circuit, and a control register configured to control respective parts in the image display apparatus. At power-on or start-up of the image display apparatus, the initial setting circuit reads initialization data from the nonvolatile memory section and sets communication mode for communicating with the nonvolatile memory section to the control register.
|Non-volatile memory devices having charge storage layers at intersecting locations of word lines and active region|
Nonvolatile memory devices are provided. Devices include active regions that may be defined by device isolation layers formed on a semiconductor substrate and extend in a first direction.
|Nonvolatile memory device|
A non-volatile memory includes a channel layer to extend from a substrate in a vertical direction; a plurality of interlayer dielectric layers and a plurality of gate electrodes to be alternately stacked along the channel layer; and a memory layer to be interposed between the channel layer and each of the gate electrodes, wherein the memory layer comprises a tunnel dielectric layer to contact the channel layer, a first charge trap layer to contact the tunnel dielectric layer and formed of an insulating material, a charge storage layer to contact the first charge trap layer and formed of a semiconducting material or a conductive material, a second charge trap layer to contact the charge storage layer and formed of an insulating material, and a charge blocking layer to contact the second charge trap layer.. .
|Nonvolatile memory device and method for fabricating the same|
A nonvolatile memory device includes a plurality of gate structures, each gate structure formed over a substrate and including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate, which are sequentially stacked, and an interlayer dielectric layer covering the plurality of gate structures and having an air gap formed between adjacent gate structures, wherein the bottom surface of the air gap is positioned at a lower level than the surface of the tunnel insulating layer.. .
|Nonvolatile memory device and method of manufacturing the same|
In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate.
|Nonvolatile memory device and method for fabricating the same|
A nonvolatile memory device includes gate structures formed over a substrate, each gate structure including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate that are sequentially stacked, a protective layer formed on sidewalls of the floating gate, and a second insulating layer covering the gate structures and having an air gap formed between the gate structures, wherein an adhesive strength between the second insulating layer and the protective layer is smaller than an adhesive strength between the second insulating layer and the gate structure.. .
|Nonvolatile memory element and nonvolatile memory device|
A variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer including: a first oxide layer including a metal oxide having non-stoichiometric composition and including p-type carriers; a second oxide layer located between and in contact with the first oxide layer and a second electrode and including a metal oxide having non-stoichiometric composition and including n-type carriers; an oxygen reservoir region located in the first oxide layer, having no contact with the first electrode, and having an oxygen content atomic percentage higher than that of the first oxide layer; and a local region located in the second oxide layer, having contact with the oxygen reservoir region, and having an oxygen content atomic percentage lower than that of the second oxide layer.. .
|Nonvolatile memory element, nonvolatile memory device, and methods of manufacturing the same|
A nonvolatile memory element includes: a lower electrode formed above a substrate; a first variable resistance layer formed above the lower electrode and comprising a first metal oxide; a second variable resistance layer formed above the first variable resistance layer and comprising a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide; and an upper electrode formed above the second variable resistance layer. A single step is formed in an interface between the first variable resistance layer and the second variable resistance layer.
|Nonvolatile memory device|
According to one embodiment, a nonvolatile memory device includes a first wiring, a second wiring, and a memory cell provided between the first wiring and the second wiring. The memory cell includes a memory layer, a rectifying element layer, and a protective resistance layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type..
A nonvolatile memory according to an embodiment includes a first wiring line; a second wiring line arranged above the first wiring line and extending in a direction crossing the first wiring line; and a resistance change layer arranged in an intersection region of the first wiring line the second wiring line, the second wiring line including a first member extending in the direction in which the second wiring line extends, and an electrode layer containing a metal element arranged on a side surface of the first member along the direction in which the second wiring line extends, a lower surface of the electrode layer being in contact with an upper surface of the resistance change layer.. .