|| List of recent Nonvolatile Memory-related patents
| Nonvolatile memory device having authentication, and methods of operation and manufacture thereof|
A memory device package encloses two separate die, one being a standard nonvolatile memory integrated circuit (“ic”) die, and the other being any suitable authentication ic die. Either die may be stacked upon the other, or the die may be placed side-by-side.
| Memory controller, storage device, and memory control method|
According to one embodiment, a memory controller includes: a first flash encoding unit that performs flash encoding on user data according to a first scheme to generate user data flash codes; an encoding unit that performs an error correction encoding process on the user data flash codes to generate parities; a second flash encoding unit that performs flash encoding on the parities according to a second scheme to generate parity flash codes; and a memory i/f that writes the user data flash codes and the parity flash codes to the nonvolatile memory.. .
| Virtual memory management apparatus|
A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages.
| Pinning content in nonvolatile memory|
Systems and methods relating to pinning selected data to sectors in non-volatile memory. A graphical user interface allows a user to specify certain data (e.g., directories or files) to be pinned.
| Method of manufacturing semiconductor device|
To improve a semiconductor device having a nonvolatile memory. A first misfet, a second misfet, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover.
| Method for fabricating nonvolatile memory structure|
A nonvolatile memory structure includes a semiconductor substrate having thereon a first oxide define (od) region, a second od region and a third od region arranged in a row. The first, second, and third od regions are separated from one another by an isolation region.
| Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device|
A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.. .
| Memory system and memory access method|
Systems and methods of sequentially accessing memory cells in a nonvolatile memory device (nvm) are provided. The nvm has a plurality of strings and a common signal line coupled to the plurality of strings.
| Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors|
Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., nand-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines..
| Nonvolatile memory and operating method of nonvolatile memory|
An operating method of a nonvolatile memory is provided which includes adjusting a threshold voltage of at least one first memory cell adjacent to a substrate in each cell string to be higher than a threshold voltage distribution of an erase state; and reading a second memory cell located above the at least one first memory cell in each cell string, wherein the at least one first memory cell in each cell string is a dummy memory cell.. .
| Method and system for reducing the complexity of electronically programmable nonvolatile memory|
Embodiments relate to memory devices and methods for firmly programming at least a portion of a plurality of electronically programmable and erasable nonvolatile memory cells in a processing of the nonvolatile memory devices.. .
| Method for sharing by wireless non-volatile memory|
The present invention includes steps of providing the image capturing device with a wireless transmitting non-volatile memory, wherein the image capturing device includes a first display, and wherein the wireless transmitting nonvolatile memory is used to store an image captured by the image capturing device and includes embedded wireless transmitting module, and the wireless transmitting non-volatile memory is separable from the image capturing device, the wireless transmitting non-volatile memory includes a sharing mode for sharing the image, a pair-wise application is coupled to the control unit for pairing with the wireless transmitting non-volatile memory for sharing the image by wireless transmission.. .
| Three-dimensional nonvolatile memory and method of fabrication|
A three-dimensional memory is provided that includes a first memory level and a second memory level monolithically formed above the first memory level. The first memory level includes a first steering element coupled in series with and vertically stacked above or below a first non-volatile state change element.
| Vertical mosfet transistor, in particular operating as a selector in nonvolatile memory devices|
A vertical mosfet transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region of the first conductivity type, arranged on top of the channel region and the buried conductive region; a gate insulation region, extending at the sides of and contiguous to the channel region; and a gate region extending at the sides of and contiguous to the gate insulation region..
| Sealed infrared imagers|
The architecture, design and fabrication of array of suspended micro-elements with individual seals are described. Read out integrated circuit is integrated monolithically with the suspended elements for low parasitics and high signal to noise ratio detection of changes of their electrical resistance.
|Nonvolatile memory device and method of operating the same|
A nonvolatile memory device includes a nonvolatile memory, a buffer memory configured to store a plurality of read data transmitted from the nonvolatile memory, an error detection and correction circuit configured to detect an error in partial data of each of the plurality of read data and judging whether the partial data is correctable or not on the basis of the detected error, and a controller configured to analyze the uncorrectable partial data with respect to the plurality of read data to determine a representative value, and to transmit the representative value to the error detection and correction circuit. The plurality of read data is read through a read operation with respect to a same page..
|Memory system performing address mapping according to bad page map|
A memory system comprises a nonvolatile memory comprising a memory block having multiple pages, and a controller configured to control the nonvolatile memory to store data in the memory block according to a command and logical address received from an external source. The controller is configured to determine whether the logical address is currently mapped to a bad page of the memory block by referring to a bad page map, and as a consequence of determining that the logical address corresponds to the bad page, remaps the logical address to a different page and stores dummy data in the bad page..
|Memory system and management method therof|
A memory system having multiple memory layers is provided. The memory system includes an upper memory layer and an intermediate memory layer comprising a first sub-memory consisting of a nonvolatile memory and a second sub-memory consisting of a volatile memory in a parallel structure positioned below the upper memory layer, and a memory management unit that controls operations of the upper memory layer and the intermediate memory layer.
|Apparatus and methods for peak power management in memory systems|
Disclosed are apparatus and techniques for managing power in a memory system having a controller and nonvolatile memory array. In one embodiment, prior to execution of each command with respect to the memory array, a request for execution of such command is received with respect to the memory array.
|Memory controller, method of operating the same and memory system including the same|
A memory controller controlling a nonvolatile memory device having a plurality of memory blocks as a data storage space includes an error detection and correction circuit and a reclaim control unit. The error detection and correction circuit receives data from a memory block and calculates a comparison result by comparing a bit error rate of the received data and a predetermined value.
|Bipolar multistate nonvolatile memory|
Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states.
|Nonvolatile memory device and memory system including the same|
A nonvolatile memory device includes a memory cell array; and a high voltage generator arranged to generate a high voltage to be supplied to the memory cell array. The high voltage generator includes a pump unit block having a plurality of pump units supplied with an external voltage and at least one of the pumps is engaged in pumping the external voltage to a higher, output, voltage, at a steady clock rate.
|Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate|
A one-time programmable (otp) memory cell includes a dual date transistor and, in some embodiments, two transistors. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device.
|Memory system and programming method thereof|
A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be the pre-pulse mode, applying a pre-pulse having a predetermined level to a string selection line connected with a gate of a string selection transistor of at least one unselected vertical string of the plurality of vertical strings for a particular time period; and performing a verification operation on the programmed memory cell.. .
|Nand flash memory device|
A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.. .
|Method of manufacturing semiconductor device|
Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a misfet is formed.
|Nonvolatile memory device|
According to one embodiment, a nonvolatile memory device includes a core unit and a peripheral circuit unit. The core unit is configured to be capable of storing data.
|Memory system and method of driving memory system using zone voltages|
A method is provided for driving a nonvolatile memory device, including multiple strings, where each string is formed by penetrating plate-shaped word lines stacked on a substrate. The method includes configuring the word lines of a string in multiple zones based on zone configuration information, and applying zone voltages to the zones, respectively.
According to one embodiment, a semiconductor device includes a nonvolatile memory, a volatile memory, and a controller. The controller is configured to transition a part of the volatile memory to a self-refresh mode when a request for stopping supplying of power to the nonvolatile memory is received..
|Nonvolatile memory device and control method thereof|
A vertical nonvolatile memory device which includes a plurality of cell strings formed in a direction intersecting with a substrate is provided. The vertical nonvolatile memory device is configured to apply a non-selection read voltage to at least one selection line connected to a cell string from among the plurality of cell strings.
|Integrated circuit, method for driving the same, and semiconductor device|
An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided.
|Electronic device including a nonvolatile memory structure having an antifuse component|
An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include a substrate, an access transistor, a read transistor, and an antifuse component. Each of the access and read transistors can include source/drain regions at least partly within the substrate, a gate dielectric layer overlying the substrate, and a gate electrode overlying the gate dielectric layer.
|Nonvolatile memory device and method for manufacturing the same|
A variable resistance layer includes a first variable resistance layer comprising a first metal oxide that is oxygen deficient and a second variable resistance layer comprising a second metal oxide having a degree of oxygen deficiency that is different from that of the first metal oxide, wherein the second variable resistance layer includes a non-metal element a that is different from oxygen, x<(y+z) is satisfied where a composition of the first variable resistance layer is represented by mox and a composition of the second variable resistance layer is represented by noyaz, the second variable resistance layer has a higher resistivity than a resistivity of the first variable resistance layer, and a film density of the second variable resistance layer is lower than a theoretical film density of the second metal oxide which has a stoichiometric composition.. .
A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 Ωcm.
|Semiconducotr memory device including non-volatile memory cell array|
A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a dram cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit.
According to one embodiment, a memory system includes a nonvolatile memory, a controller configured to control an operation of the nonvolatile memory, a connector electrically connected to a host device, a power supply circuit configured to electrically connect the connector to the controller and the nonvolatile memory, and a power supply control circuit electrically connected to the connector and configured to control an operation of the power supply circuit in response to a first request sent from the host device. The power supply circuit cuts power supplies to the controller and the nonvolatile memory in response to the first request..
|Information processing device, external storage device, host device, relay device, control program, and control method of information processing device|
According to the embodiments, an external storage device switches to an interface controller for supporting only a read operation of nonvolatile memory when a shift condition for shifting to a read only mode is met. A host device switches to an interface driver for supporting only the read operation of the nonvolatile memory when determining to recognize as read only memory based on information acquired from the external storage device..
|Memory systems and operating methods of memory controllers|
A memory system is provided which includes a nonvolatile memory; and a controller configured to control the nonvolatile memory, wherein the controller comprises a voltage detector configured to detect a level of a power supply voltage; and wherein when a level of the power supply voltage is lower than a first threshold value, the controller issues a reset command to the nonvolatile memory and then performs a reset operation.. .
|Memory system and related method of operation|
A method of operating a memory system comprises determining whether a write request from a host is a random write request, and as a consequence of determining that the write request is a random write request, programming a lower page of a selected word line of a nonvolatile memory device with restorable data of the nonvolatile memory device, and programming an upper page of the selected word line with write data corresponding to the write request after programming the lower page.. .
According to one embodiment, a memory system includes a nonvolatile memory, a command managing unit, a command issuing unit, a data control unit and a command monitoring unit. The command issuing unit issues a command received by the command managing unit to the nonvolatile memory.
|Method and system for reducing write latency in a data storage system by using a command-push model|
A data storage system is provided that implements a command-push model that reduces latencies. The host system has access to a nonvolatile memory (nvm) device of the memory controller to allow the host system to push commands into a command queue located in the nvm device.
|Program and read methods of memory devices using bit line sharing|
A program method of a nonvolatile memory device includes loading first word line data to be stored in first memory cells connected to a first word line and second word line data to be stored in second memory cells connected to a second word line; setting up upper bit lines according to the first word line data; turning off bit line sharing transistors after the upper bit lines are set up; setting up lower bit lines according to the second word line data; performing a first program operation on the first memory cells using the upper bit lines; turning on the bit line sharing transistors; and performing a second program operation on the second memory cells using the lower bit lines. The bit line sharing transistors electrically connect the upper bit lines and the lower bit lines in response to a bit line sharing signal..
|Memory system comprising nonvolatile memory device and program method thereof|
A memory system includes a nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device such that memory cells connected with a selected row of the nonvolatile memory device are programmed by one of a first program mode and a second program mode. At the first program mode, a plurality of logical pages corresponding in number to a maximum page number is stored at the memory cells, and at the second program mode, one or more logical pages the number of which is less than the maximum page number are stored at the memory cells using a bias condition that is different from that used in the first program mode..
|Nonvolatile memory device and writing method thereof|
A writing method of a nonvolatile memory device is provided which receiving data, a target time, and a target resistance value; writing the data at a memory cell; calculating a resistance drift coefficient based on resistance values of the memory cell read on at least two times; calculating a resistance value of the memory cell on the target time using the resistance drift coefficient; and determining whether the resistance value calculated satisfies the target resistance value.. .
|Nonvolatile memory device and method of fabricating the same|
In a nonvolatile memory device and a method for fabricating the same, a device comprises a substrate, a trench in the substrate and a first gate pattern comprising a first bottom gate electrode having a first portion in the trench and having a second portion on the first portion and protruding in an upward direction relative to an upper surface of the substrate. A second gate pattern comprising a second gate electrode is on the substrate at a side of the first gate pattern and insulated from the first gate pattern.
|One-time programmable memory and method for making the same|
A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate..
|Transition metal oxide bilayers|
Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed.
|Memory system and related block management method|
A memory system manages memory blocks of a nonvolatile memory device by determining at least one memory block property of a selected memory block among the multiple memory blocks in the nonvolatile memory device, storing memory block property information indicating the at least one memory block property, arranging a free memory block list based on the stored memory block property information, and designating a free memory block from the arranged free memory block list as an active memory block, wherein the designation of the free memory block as an active memory block is based on an ordering of the free memory block list.. .
|Data randomization in 3-d memory|
In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is randomized so that data of different strings along the same bit line are randomized using different keys and portions of data along neighboring word lines are randomized using different keys. Keys may be rotated so that data of a particular word line is randomized according to different keys in different strings..
|Nonvolatile logic array with built-in test drivers|
A system on chip (soc) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data.
|Nonvolatile logic array with built-in test result signal|
A system on chip (soc) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data.
|Methods of programming multi-level cell nonvolatile memory devices and devices so operating|
To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line a preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level a secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.. .
|Resistive memory device comprising selectively disabled write driver|
A nonvolatile memory device comprises a resistive memory cell, a write driver configured to write data to the resistive memory cell during a write period comprising a plurality of loops, and a sense amplifier configured to verify whether the data is correctly written to the resistive memory cell in each of the loops. Where the sense amplifier verifies that the data is correctly written in a k-th loop among the loops, the write driver is disabled from a (k+1)-th loop to an end of the write period..
|Error detection in nonvolatile logic arrays using parity|
A system on chip (soc) has a nonvolatile memory array of n rows by m columns coupled to one or more of the core logic blocks. M is constrained to be an odd number.
|Semiconductor device and manufacturing method of semiconductor device|
A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion.
|Nonvolatile memory bitcell|
A multiple time programmable nonvolatile memory device having a single polysilicon memory cell includes a select transistor and a bitcell transistor. The bitcell transistor has asymmetrically configured source, drain, and channel regions including asymmetrically configured source-body and drain-body junctions.
|Strongly correlated nonvolatile memory element|
In aspects of the invention, a strongly correlated nonvolatile memory element is provided which exhibits phase transitions and nonvolatile switching functions through electrical means. In an aspect of the invention, a strongly correlated nonvolatile memory element is provided including, on a substrate, a channel layer, a gate electrode, a gate insulator, a source electrode, and a drain electrode.
|Semiconductor device and control method of the same|
The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened..
|Electronic control unit for vehicle and data communication method|
An electronic control unit for a vehicle includes a nonvolatile memory that is capable of erasing and writing data electrically, and capable of receiving a program to be written into the nonvolatile memory in units of a predetermined size by means of communication using a communication buffer. The electronic control unit for the vehicle uses communication buffers, the number of which is greater than the number of communication buffers used in an in-vehicle communication environment, to receive the program..
|Translation layer partitioned between host and controller|
A method for using a partitioned flash transition layer is disclosed. Step (a) receives, at an apparatus from a host, a write command having first write data.
|Variable-size flash translation layer|
A method for using a variable-size flash transition layer is disclosed. Step (a) receives a read request to read data corresponding to a logical block address from a nonvolatile memory.
|Multilevel cell nonvolatile memory system|
A multilevel cell (mlc) nonvolatile memory system including a plurality of memory cells each cell storing first bit data and second bit data, and a controller programming the plurality of memory cells on a page-by-page basis, the controller programming original data to an original block and programming copy data that is the same as the original data to a mirroring block, wherein first bit page data and second bit page data of the original data are programmed to memory cells connected to the same word line, but the first bit page data and second bit page data of the copy data are programmed to memory cells connected to different word lines.. .
|Nonvolatile memory devices, memory systems and related control methods|
A nonvolatile memory device includes a cell array including a plurality of cell strings extending on a substrate in a vertical direction, a page buffer connected to a plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured to provide voltages to a plurality of word lines and the plurality of bit lines, and an input/output buffer configured to temporarily store the sensing data received in a data dump from the page buffer and to output the temporarily stored data to an external device. The nonvolatile memory device further includes control logic configured to set a status of the nonvolatile memory device to a ready state after the sensing data is dumped to the input/output buffer and before recovery of the cell array from a bias voltage of the sensing operation is complete..
|Nonvolatile memory device, memory system having the same, external power controlling method thereof|
An external power control method includes determining whether to apply a second external voltage to a first node according to a drop of a first external voltage; generating a flag signal according to a drop of the second external voltage when the second external voltage is applied to the first node; transferring a voltage of the first node to a second node in response to the flag signal; and discharging at least one voltage of an internal circuit connected to the second node in response to the flag signal.. .
|High voltage switch and a nonvolatile memory device including the same|
A high voltage switch of a nonvolatile memory device includes a depletion type nmos transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage switch into a first driving voltage or a ground voltage, wherein the first and second driving voltages are received from an external device; and a pmos transistor configured to transfer the second driving voltage provided to a first terminal of the pmos transistor from the depletion type nmos transistor to a second terminal of the pmos transistor as the output signal in response to an output of the at least one inverter, wherein the output of the at least one inverter is transferred to a gate terminal of the pmos transistor.. .
|Nonvolatile resistive memory device and writing method|
A writing method for a resistive nonvolatile memory device includes writing data to a resistive nonvolatile memory cell using an up/down write pulse signal when the data is first data type, and writing data to the resistive nonvolatile memory cell using only one of an up write pulse signal and a down write pulse signal when the data is second data type.. .
|Variable resistance nonvolatile memory element and method of manufacturing the same|
A variable resistance nonvolatile memory element includes: first and second electrode layers; a first variable resistance layer between the first and second electrode layers; and a second variable resistance layer between the second electrode layer and the first variable resistance layer and having a higher resistance value than the first variable resistance layer. When viewed in a direction perpendicular to the major surface of the second variable resistance layer, an outline of the second variable resistance layer is located inwardly of the outline of any one of the second electrode layer and the first variable resistance layer, and an outline of a face of the second variable resistance layer, the face being in contact with the first variable resistance layer is located inwardly of an outline of a face of the first variable resistance layer, the face being in contact with the second variable resistance layer..
|Apparatus and method for encoding data for storage in multi-level nonvolatile memory|
A controller for a nonvolatile memory includes an encoder and a decoder. The memory includes memory cells that each store data using more than two levels.
|Distributed procedure execution and file systems on a memory interface|
Nonvolatile memory (e.g., flash memory, solid-state disk) is included on memory modules that are on a dram memory channel. Nonvolatile memory residing on a dram memory channel may be integrated into the existing file system structures of operating systems.
|Storage control apparatus, data storage apparatus and method for storage control|
According to one embodiment, a storage control apparatus includes a first buffer controller and a second buffer controller. The first buffer controller is configured to store data of a first unit in each of data buffer regions, and the data of the first unit is transmitted from a host and written in a nonvolatile memory, or read from the nonvolatile memory and transmitted to the host.
|Orchestrating management operations among a plurality of intelligent storage elements|
An apparatus and associated methodology contemplating a data storage system having a group of processor-controlled intelligent storage elements (ises). Each ise in the group individually includes storage resources and a network interface.