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Nand Flash patents



      
           
This page is updated frequently with new Nand Flash-related patents. Subscribe to the Nand Flash RSS feed to automatically get the update: related Nand RSS feeds.

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Date/App# patent app List of recent Nand Flash-related patents
04/10/14
20140101370
 Apparatus and method for low power low latency high capacity storage class memory patent thumbnailApparatus and method for low power low latency high capacity storage class memory
A method and a storage system are provided for implementing enhanced solid-state storage class memory (escm) including a direct attached dual in line memory (dimm) card containing dynamic random access memory (dram), and at least one non-volatile memory, for example, phase change memory (pcm), resistive ram (reram), spin-transfer-torque ram (stt-ram), and nand flash chips. An escm processor controls selectively allocating data among the dram, and the at least one non-volatile memory primarily based upon a data set size..
04/10/14
20140097482
 Full metal gate replacement process for nand flash memory patent thumbnailFull metal gate replacement process for nand flash memory
A nand flash memory chip is made by forming sacrificial control gate structures and sacrificial select structures, and subsequently replacing these sacrificial structures with metal. Filler structures are formed between sacrificial control gate structures and are subsequently removed to form air gaps between neighboring control gate lines and between floating gates..
04/03/14
20140091381
 Support lines to prevent line collapse in arrays patent thumbnailSupport lines to prevent line collapse in arrays
Methods for preventing line collapse during the fabrication of nand flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication.
03/27/14
20140089567
 Hardware integrity verification patent thumbnailHardware integrity verification
A flash memory management method and apparatus provides for the separation of the command and data paths so that communication paths may be used more efficiently, taking account of the characteristics of nand flash circuits where the times to read, write and erase data differ substantially. A unique sequence identifier is assigned to a write command and associated data and association of the data and commands are validated prior to writing to the memory by comparing the unique sequence numbers of the data and command prior to executing the command.
03/20/14
20140082264
 Nand flash storage chip checking method and device patent thumbnailNand flash storage chip checking method and device
A nand flash storage chip correcting method is provided in the present invention. The method can correct one or two bits errors and find a number of bits errors according to the row and column xor value and hash value of each page written into the spare area, comparing the data stored in the data area and the computed hash value of data area to correct one or two bits of errors, thus ensures the accuracy and integrity of the data stored in the nand flash chip and reduces the risk of crash of the file system..
03/20/14
20140080299
 Processes for nand flash memory fabrication patent thumbnailProcesses for nand flash memory fabrication
Narrow word lines are formed in a nand flash memory array using a double patterning process in which sidewall spacers define word lines. Sidewall spacers also define edges of select gates so that spacing between a select gate and the closest word line is equal to spacing between adjacent word lines..
03/20/14
20140078826
 Methods of making word lines and select lines in nand flash memory patent thumbnailMethods of making word lines and select lines in nand flash memory
A nand flash memory chip includes word lines formed by etching through concentric conductive loops and, in the same etch step, etching through a conductive strip to form select lines. A conductive loop forms two word lines which are in different erase blocks and are separately controlled by peripheral circuits..
03/13/14
20140075268
 Method for dodging bad page and bad block caused by suddenly power off patent thumbnailMethod for dodging bad page and bad block caused by suddenly power off
A method for dodging bad page and bad block caused by suddenly power off is disclosed. This method is to avoid a new data from host program to potential hurt block or page caused by power off during nand flash erasing or programming..
02/27/14
20140054669
 Structures and methods for making nand flash memory patent thumbnailStructures and methods for making nand flash memory
A nand flash memory chip includes wide openings in an inter-poly dielectric layer through which gaps are later etched to define structures such as select gates. Such select gates are asymmetric, with inter-poly dielectric on a side adjacent to a memory cell and no inter-poly dielectric on a side away from a memory cell.
02/13/14
20140047269
 Operating method for memory system including nonvolatile ram and nand flash memory patent thumbnailOperating method for memory system including nonvolatile ram and nand flash memory
An operating method for a memory system including a nonvolatile random access memory (nvram) and a nand flash memory includes; performing a normal read operation directed to the target memory cell in response to a read request, determining that a read fail has occurred as a result of the normal read operation, then performing a read retry operation by iterations directed to the target memory cell according to a first read retry scheme until a pass read retry iteration successfully reads the target memory cell, and storing pass information associated with the pass read retry iteration in the nvram.. .
02/13/14
20140043898
Common line current for program level determination in flash memory
In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—is determined from the total current passing through the population of memory cells under read conditions, as observed on a common line, for example a source line in nand flash memory.. .
01/30/14
20140029341
Non-volatile solid state memory-based mass storage device and methods thereof
Non-volatile solid state mass storage device and methods for improving write performance thereof. The storage device includes a nand flash controller, an array of nand flash memory integrated circuits, and means for determining a lowest unused page number of each write target block in a group of the nand flash memory integrated circuits that are simultaneously accessible at any given time by a write command.
01/23/14
20140022847
Nand flash memory programming
A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described..
01/23/14
20140022846
Nand flash memory having multiple cell substrates
A nand flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where nand cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage.
01/16/14
20140019741
Method and system for booting electronic device from nand flash memory
A method and system for booting an electronic device from a nand flash memory includes a nand flash controller that receives an event trigger for fetching a pre-boot code stored in the nand flash memory. Based on the event trigger type, booting parameters are loaded into the controller including a boot frequency of the nand flash memory.
01/09/14
20140013032
Method and apparatus for controlling writing data in storage unit based on nand flash memory
A method and apparatus for controlling writing of data in a storage unit based on a nand flash memory are provided. The method includes determining reference values for classifying dirty pages to be written in the storage unit into a plurality of groups; calculating, with respect to each of the dirty pages, a hotness indicating a possibility of a change of data; classifying the dirty pages into the groups corresponding to reference values most similar to the calculated hotness; determining whether sizes of the groups are greater than a size of a segment, where the segment is a unit for performing a write request in the storage unit; and requesting a write operation for each segment with respect to groups having a size at least equal to the size of the segment to the storage unit..
01/02/14
20140003148
Three dimensional nand flash with self-aligned select gate
An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor material, and two or more memory cells, stacked vertically on top of the field effect transistor, and having channels that are formed in the pillar semiconductor of material.. .
12/26/13
20130346671
On-chip bad block management for nand flash memory
Certain functions relating to creation and use of a look-up table for bad block mapping may be implemented “on chip” in the memory device itself, that is on the same die in an additional circuit, or even within the command and control logic of the memory device, so as to reduce the overhead. Moreover, the on-chip implementation of the look-up table may be tightly integrated with other functions of the command and control logic to enable powerful new commands for nand flash memory, such as a continuous read command and variations thereof..
12/26/13
20130343130
Nand flash biasing operation
A charge storage memory is configured in a nand array, and includes nand strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the nand array.
12/05/13
20130322179
Hot carrier programming in nand flash
A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a nand string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection using a boosted channel potential to establish the heating field.
11/28/13
20130316537
Self-aligned nand flash select-gate wordlines for spacer double patterning
A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed.
11/21/13
20130308388
Apparatus and method for reduced peak power consumption during common operation of multi-nand flash memory devices
System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently.
11/07/13
20130297987
Method and apparatus for reading nand flash memory
A page buffer for a nand memory array has a data register and a cache register that are suitably organized and operated to eliminate gaps and discontinuities in the output data during a continuous page read. The cache register may be organized in two portions, and the page data in the cache may be output from the cache portions in alternation.
10/31/13
20130286737
Nand flash memory having c/a pin and flash memory system including the same
A nand flash memory in which a command/address pin is separated from a data input/output pin. The nand flash memory includes a memory cell array used for storing data, a command/address pin through which a command and an address are received for transmitting data in the memory cell array, and a data input/output pin through which data are transmitted in the memory cell array.
10/31/13
20130286734
Nand flash memory
A nand flash memory includes a plurality of nand flash memory structures separated by an insulating layer. In one embodiment of the present disclosure, the nand flash memory structure includes a first bitline extending along a first direction, a first charge-trapping region positioned over the first bitline, a wordline positioned over the first charge-trapping region and extending along a second direction, a second charge-trapping region positioned over the wordline, and a second bitline positioned over the second charge-trapping region, wherein the first charge-trapping region and the second charge-trapping region are stacked along a third direction substantially perpendicular to the first direction and the second direction..
10/24/13
20130279251
Novel shielding 2-cycle half-page read and program schemes for advanced nand flash design
The present invention provides a two-cycle half-page read scheme by dividing whole nand array bit lines (bls) into an odd-bl group and an even-bl group. During the half-plane reading of nand cells in the odd(even)-bl group, the half-plane even(odd)-bl group acts as the shielding bls to protect over the odd(even)-bl string reading so that each half-page read operation is substantially reliable and free from bl coupling noise effect.
10/24/13
20130279249
Operating method of memory system including nand flash memory, variable resistance memory and controller
An operating method is for a memory system which includes a nand flash memory, a resistance variable memory, and a controller controlling the nand flash memory and the resistance variable memory. The operating method includes receiving data, programming the received data in the nand flash memory when the received data is at least a super page of data, programming the received data in the resistance variable memory when the received data is not a super page of data, and programming data accumulated in the resistance variable memory in the nand flash memory when the accumulated data is a super page of data.
10/03/13
20130262901
Memory system and server system
According to one embodiment, a memory system includes a nand flash memory includes a memory cell array includes pages, and a volatile data register with a storage capacity of one page, and configured to write page data to the memory cell array through the data register, each of the pages includes nonvolatile memory cells and being a unit of data write, a volatile ram, and a controller includes a power saving mode in which power consumption of the ram is reduced, and configured to transfer data of the ram to the data register before entering the power saving mode.. .
10/03/13
20130262744
Nand flash memory interface
A nand flash memory chip has a configurable interface that can communicate with a nand flash memory controller using either parallel communication or serial communication. Serial communication requires fewer channels.
10/03/13
20130258780
Method of programming selection transistors for nand flash memory
Disclosed herein is a method that includes providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to associated one of the cells, and a selection line coupled in common to the gates of the selection transistors, applying a first program voltage to the selection line, and applying a second program voltage to the selection line when at least one of the selection transistors have not been shifted to a program condition.. .
10/03/13
20130256775
Three-dimensional microelectronic devices including horizontal and vertical patterns
A vertical nand flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face.
09/19/13
20130246892
Architecture for storage of data on nand flash memory
Systems, methods, apparatus, and techniques are provided for processing data from a storage medium. A stripe of data stored on the storage medium is read, where the stripe comprises a plurality of data allocation units (aus) and a parity au.
09/19/13
20130246890
Architecture to allow efficient storage of data on nand flash memory
Systems, methods, apparatus, and techniques are provided for writing data to a storage medium. A stripe of the storage medium is interfaced via one or more data transfer channels, where the stripe comprises a plurality of pages of the storage medium.
09/19/13
20130246694
Multilevel memory bus system for solid-state mass storage
The present invention relates to a multilevel memory bus system for transferring information between at least one dma controller and at least one solid-state semiconductor memory device, such as nand flash memory devices or the like. This multilevel memory bus system includes at least one dma controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus.
09/19/13
20130246693
Flash-aware storage optimized for mobile and embedded dbms on nand flash memory
Reliable storage for database management systems (dbms) running on memory devices such as nand type flash memory utilizes minimum i/o overhead and provides maximum data durability. A virtual page map is utilized between the flash memory and a page access component to record changes to the dbms pages and prevent overwriting or data loss.
08/29/13
20130227203
Dynamic slc/mlc blocks allocations for non-volatile memory
Apparatus and methods are disclosed, such as those that provide dynamic block allocations in nand flash memory between single-level cells (slc) and multi-level cells (mlc) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between slc mode and mlc mode based on the amount of memory available for use.
08/29/13
20130223142
3d stacked nand flash memory array enabling to operate by lsm and operation method thereof
This invention provides a 3d stacked nand flash memory array and operation method thereof enabling to operate by lsm (a layer selection by multi-level operation) and to get rid of the waste of unnecessary areas by minimizing the number of ssls needed for a layer selection though the number of layers vertically stacked is increased.. .
08/08/13
20130205072
Asynchronous bad block management in nand flash memory
Methods for receiving data from a file system and storing it in a flash storage medium, wherein a bad block management process comprises queuing, at a bad block manager, one or more write requests, and receiving data associated with each of the one or more write requests and storing the received data in the bad block manager buffer; and performing cache management of data in the bad block manager buffer and subsequently returning a success status to the file system; and executing the one or more queued write requests in a separate task, wherein the executing comprises programming the received data to the flash storage medium during the bad block management process. Corresponding devices are also provided..
08/01/13
20130194871
Nand flash memory unit, nand flash memory array, and methods for operating them
A nand flash memory unit is described, including a string of memory cells connected in series, s/d regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an s/d region, and at least one erase transistor couple between the at least one select transistor and an s/d region. The select transistor is for selecting the string of memory cells.
07/18/13
20130185550
Method and system for nand flash support in an autonomously loaded secure reprogrammable system
A system and method that enables secure system boot up with a restricted central processing unit (cpu). The system includes a memory, a segmenting device, and a security sub-system.
07/18/13
20130185484
File programming method and associated device for nand flash
A file programming method for a flash memory is provided. The method includes steps of: obtaining a section description file and corresponding allocation information and user data while generating burning files, wherein the section description file includes section description information of at least one section and the allocation information includes the number that the burning file is to be generated; determining a file type corresponding to a section file according to the section description information; and generating the burning files utilizing the user data according to section description information, the number that the burning file is to be generated corresponding to the section description information, and the file types corresponding to the section files..
07/11/13
20130179728
Repair method and device for abnormal-erase memory block of non-volatile flash memory
A repair method for an abnormal-erase memory block of a non-volatile flash memory is provided. The method includes steps of: sequentially scanning bit data in a page of a block when reading data in a nand flash; determining whether the page is an abnormal-erase page; setting logic “0” bit data in the page to logic “1” when the page is an abnormal-erase page; and re-erasing the block..
07/11/13
20130179624
Systems and methods for tracking and managing non-volatile memory wear
Systems and methods are disclosed that may be implemented to manage operation and tracking memory wear of flash devices, such as relatively large mixed use embedded nand flash devices or other non-volatile memory (nvm) devices employed in information handling systems such as servers. The disclosed systems and methods may advantageously be implemented to perform tasks such as tracking and/or predicting actual wear for nvm devices, and optionally controlling write operations to a nvm device.
07/11/13
20130178026
Method for fabricating a field side sub-bitline nor flash array
Field side sub-bitline nor-type (fsnor) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor non-volatile memory (nvm) cells in a nor-type flash array of the invention.
07/11/13
20130176790
Charge cycling by equalizing the source and bit line levels between pulses during no-verify write operations for nand flash memory
In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse.
07/11/13
20130176788
Device selection schemes in multi chip package nand flash memory system
Systems and methods are provided for perform device selection in multi-chip package nand flash memory systems. In some embodiments, the memory controller performs device selection by command.
07/11/13
20130176777
Charge cycling by equalizing and regulating the source, well, and bit line levels during write operations for nand flash memory: verify to program transition
In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse.
07/11/13
20130176776
Charge cycling by equalizing and regulating the source, well, and bit line levels during write operations for nand flash memory: program to verify transition
In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse.
07/04/13
20130173972
System and method for solid state disk flash plane failure detection
A system and method for early detection and reporting of an impending nand flash device plane failure. Each time that a data unit is retrieved from a nand flash array the number of bits in error and the memory location associated with the errors is observed.
06/27/13
20130166857
Storage device and method for controlling storage device
A write dma includes a write unit, a read unit and a parity generation unit. The read unit reads parity data from one of two nand flashes storing the parity data therein.
06/06/13
20130141975
Semiconductor memory device and method for controlling the same
A semiconductor memory device capable of reducing the size of a nand flash memory device includes a latch unit configured to store a bad block address, a comparator configured to compare the bad block address with an access address so as to output a bad-block detection signal, and a bad block controller configured to sequentially output a plurality of bad block pulses corresponding to the bad-block detection signal during a predetermined period in response to a plurality of bad-block flag signals that are sequentially activated.. .
05/30/13
20130138875
Storing/reading several data streams into/from an array of memories
High speed mass storage devices using nand flash memories (mdy.x) are suitable for recording and playing back a video data stream under real-time conditions, wherein the data are handled page-wise in the flash memories and are written in parallel to multiple memory buses (mby). However, for operating with multiple independent data streams a significant buffer size is required.
05/30/13
20130133339
Hot/cold test equipment for nand flash memory with dehumidifying function
Disclosed herein is hot/cold test equipment for a nand flash memory. The test equipment includes a mounting unit that contains the nand flash memory together with a socket to test whether the memory is defective or not, a chamber provided above the mounting unit and moving up and down to come into contact with the socket and thereby provide a target temperature, and a temperature display displaying the target temperature.
05/16/13
20130124787
Nand flash-based storage device and methods of using
A solid state drive having at least one nand flash memory component organized in blocks, pages and cells. Each cell is adapted to store at least two bits.
05/16/13
20130119455
Nand flash with non-trapping switch transistors
A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures.
05/02/13
20130111113
Nand flash memory controller exporting a nand interface
A nand controller for interfacing between a host device and a flash memory device (e.g., a nand flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed nand controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g.
04/25/13
20130103889
Page-buffer management of non-volatile memory-based mass storage devices
Mass storage devices and methods that use at least one non-volatile solid-state memory device, for example, one or more nand flash memory devices, that defines a memory space for permanent storage of data. The mass storage device is adapted to be operatively connected to a host computer system having an operating system and a file system.
04/25/13
20130102151
Methods of manufacturing nand flash memory devices
A nand flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction. .
04/25/13
20130100735
Flash memory device and operating method for concurrently applying different bias voltages to dummy memory cells and regular memory cells during erasure
Integrated circuit flash memory devices, such as nand flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than to the regular flash memory cells during an erase operation of the integrated circuit flash memory device.
04/18/13
20130092996
Nand flash memory devices
Nand flash memory device includes a common bit line, a first cell string including a first string selecting transistor having a first gate length, a second string selecting transistor having a second gate length, first cell transistors each having a third gate length and a first ground selecting transistor having a fourth gate length, a second cell string including a third string selecting transistor having the first gate length, a fourth string selecting transistor having the second gate length, second cell transistors each having the third gate length and a second ground selecting transistor having the fourth gate length and a common source line commonly connected to end portions of the first and second ground selecting transistors included in the first and second cell strings. At least one of the first gate length and the second gate length is smaller than the fourth gate length..
04/11/13
20130091321
Method and apparatus for utilizing nand flash in a memory system hierarchy
In one embodiment, a method includes obtaining a request for data, determining if the data is present in a physical memory, and obtaining the data from a non-volatile random access memory if it is determined that the data is not present in the physical memory. The request is obtained by an overall system that includes the physical memory and the non-volatile random access memory, and the overall system is configured to push information from the physical memory to the non-volatile random access memory..
04/11/13
20130088920
Low voltage programming in nand flash with two stage source side bias
A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a nand string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection.
04/11/13
20130088755
Device and method for controlling initialization of image forming apparatus using nand flash memory
A device and method for controlling the initiation of an image forming apparatus are provided using a nand flash memory. The device for controlling initiation of an image forming apparatus includes: a nand flash memory for storing a boot program and system control programs for initiating the image forming apparatus; a random-access-memory (ram) for temporarily storing an execution program and data; and a driving unit arranged to first read the boot program and an engine control program among the system control programs from the nand flash memory, execute the boot program and the engine control program, then read remaining system control programs from the nand flash memory and store the remaining system control programs in the ram when the boot program and the engine control program are being executed.
04/11/13
20130087849
Method of fabricating a charge trap nand flash memory device
Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a charge trap nand flash memory device.. .
03/28/13
20130080862
System and method for correcting errors in data using a compound code
Storage of digital data in non-volatile media such as nand flash needs to take account of the errors in data retrieved from the memory. The error rate tends to increase with the number of write/erase cycles of a cell of memory and with the time that the data has been stored.
03/28/13
20130080858
Method of reading data from a non-volatile memory and devices and systems to implement same
Methods of performing a read retry, including reading a non-volatile memory with new read parameters, and devices for performing such methods are disclosed. The read retry operation and/or subsequent read retry operation may be initiated and/or completed before it is determined that such read retry operation is warranted.
03/28/13
20130080683
Memory system provided with nand flash memory and method of controlling the same
According to one embodiment, a memory system includes first, and second districts, and control section. Each of the first and second districts includes a memory cell array.
03/21/13
20130073792
Electronic apparatus using nand flash and memory management method thereof
An electronic apparatus using nand flash memory and a memory management method thereof are provided. The electronic apparatus uses the nand flash memory to record data in the system memory.
02/28/13
20130055019
Pilot process method for system boot and associated apparatus
A pilot process method for system boot and an associated are provided. An environment variable is read from a nand flash memory.
02/28/13
20130054879
Data storage device based on spi and its controlling method
A data storage device based on spi includes an spi circuit, a nand flash memory for storing data, a nand flash interface connected between the spi interface and the nand flash memory for controlling data transmission therebetween, an instruction controlling circuit connected between the spi circuit and the nand flash memory interface for converting an instruction received by the spi circuit into an instruction recognizable to the nand flash memory and a data converting circuit connected between the spi circuit and the nand flash memory interface for accomplishing conversion between serial data and parallel data. A data storage controlling method based on spi is also disclosed.
02/14/13
20130039125
Flash memory program inhibit scheme
A method for minimizing program disturb in flash memories. To reduce program disturb in a nand flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used.


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Nand Flash topics: Nand Flash, Flash Memory, Memory Cell, Memory Device, Memory Cells, Volatile Memory, Allocation, Data Transfer, Alternation, Interleaving, Electronic Device, Transistors, Memory Chip, Nonvolatile Memory, Database Management System

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