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Nand Flash patents



      
           
This page is updated frequently with new Nand Flash-related patent applications. Subscribe to the Nand Flash RSS feed to automatically get the update: related Nand RSS feeds. RSS updates for this page: Nand Flash RSS RSS


3d stacked nand flash memory array having ssl status check buildings for monitoring threshold voltages of string…

3d nand flash memory

Nand flash memory device

Date/App# patent app List of recent Nand Flash-related patents
08/21/14
20140233322
 Adaptive architecture in a channel detector for nand flash channels patent thumbnailAdaptive architecture in a channel detector for nand flash channels
An apparatus comprising a memory configured to store data and a controller. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory.
08/21/14
20140233315
 3d stacked nand flash memory array having ssl status check buildings for monitoring threshold voltages of string selection transistors and methods for monitoring and operating the same patent thumbnail3d stacked nand flash memory array having ssl status check buildings for monitoring threshold voltages of string selection transistors and methods for monitoring and operating the same
Disclosed is a 3d stacked nand flash memory array having ssl status check buildings for monitoring threshold voltages of string selection transistors, a monitoring method of threshold voltages of string selection transistors by the ssl status check buildings, and an operating method thereof.. .
08/21/14
20140231954
 3d nand flash memory patent thumbnail3d nand flash memory
A memory device includes an array of nand strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips.
08/21/14
20140231953
 Nand flash memory device patent thumbnailNand flash memory device
A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.. .
08/14/14
20140226411
 Method of programming flash memory patent thumbnailMethod of programming flash memory
A method of programming a nand flash memory cell string. The method includes a pre-boost stage configured to elevate channel voltage of a selected memory cell, and a boost stage is introduced after the pre-boost stage.
08/14/14
20140226402
 Fast-reading nand flash memory patent thumbnailFast-reading nand flash memory
In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.. .
07/31/14
20140215129
 Cooperative flash memory control patent thumbnailCooperative flash memory control
This disclosure provides for host-controller cooperation in managing nand flash memory. The controller maintains information for each erase unit which tracks memory usage.
07/31/14
20140211563
 Hot carrier generation and programming in nand flash patent thumbnailHot carrier generation and programming in nand flash
A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines.
07/31/14
20140210095
 Methods of manufacturing nand flash memory devices patent thumbnailMethods of manufacturing nand flash memory devices
A nand flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction. .
06/26/14
20140175534
 Semiconductor device manufacturing method patent thumbnailSemiconductor device manufacturing method
In a process of dividing gates of multi-layered films in fabricating a nand flash memory having a three-dimensional structure, a pattern is prevented from deforming and falling. A ratio of a length l to a height h of control gate groups configuring a memory cell of the flash memory is set to be less than 1.65 which is a range in which buckling does not occur.
06/19/14
20140169093
Erase and soft program for vertical nand flash
Methods, and apparatuses to erase and or soft program a block of nand memory may include performing an erase cycle on a block of nand memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of nand memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify. .
06/12/14
20140164678
Intelligent detection device of solid state hard disk combining a plurality of nand flash memory cards and detecting method for the same
An intelligent detection device of solid state hard disks combining a plurality of nand flash memory card, and detecting method for the same. Wherein, a central processing unit (cpu) controls a control unit, and is connected electrically to a plurality of flash card insertion slots, for a plurality of nand flash memory card to be inserted in.
06/12/14
20140160855
Systems and methods for generating soft information in nand flash
Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins.
06/12/14
20140159246
Methods of manufacturing nand flash memory devices
A nand flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction. .
06/12/14
20140159172
Transistors, semiconductor devices, and electronic devices including transistor gates with conductive elements including cobalt silicide
A method for fabricating a transistor gate with a conductive element that includes cobalt silicide includes use of a sacrificial material as a place-holder between sidewall spacers of the transistor gate until after high temperature processes, such as the fabrication of raised source and drain regions, have been completed. In addition, semiconductor devices (e.g., dram devices and nand flash memory devices) with transistor gates that include cobalt silicide in their conductive elements are also disclosed, as are transistors with raised source and drain regions and cobalt silicide in the transistor gates thereof.
06/12/14
20140159138
Gate fringine effect based channel formation for semiconductor device
Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a nand flash memory device comprises multiple nand strings of memory transistors.
06/05/14
20140151774
Nand flash memory with vertical cell stack structure and method for manufacturing same
Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines.
05/29/14
20140149641
Optimized configurable nand parameters
Configurable parameters may be used to access nand flash memory according to schemes that optimize such parameters according to predicted characteristics of memory cells, for example, as a function of certain memory cell device geometry, which may be predicted based on the location of a particular device within a memory array.. .
05/22/14
20140143481
Management of memory array with magnetic random access memory (mram)
An embodiment of the invention includes a mass storage device with a storage media that includes magnetic random access memory (mram) devices with a nand flash interface and nand flash memory devices that are coupled to the mram devices. The storage media is partitioned into a hybrid reserved area made of a combination of mram array nand array and hybrid user area made of a combination of mram array and nand array and further includes a controller with a host interface and flash interface coupled to the mram and nand flash memory devices through a flash interface..
05/22/14
20140143480
Management of memory array with magnetic random access memory (mram)
An embodiment of the invention includes a mass storage device with a storage media that includes magnetic random access memory (mram) devices with a nand flash interface and nand flash memory devices that are coupled to the mram devices. The storage media is partitioned into a hybrid reserved area made of a combination of mram array nand array and hybrid user area made of a combination of mram array and nand array and further includes a controller with a host interface and flash interface coupled to the mram and nand flash memory devices through a flash interface..
05/22/14
20140140129
Programming method for nand flash memory device to reduce electrons in channels
In a programming method for a nand flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity.
05/15/14
20140136762
Data search using bloom filters and nand based content addressable memory
A nand flash based content addressable memory (cam) is used for a key-value addressed storage drive. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a cam nand portion of the drive and stores the value in the drive.
05/15/14
20140136761
Architectures for data analytics using computational nand memory
A data analytic system allows for analytic operations be moved from a server on to a solid state drive (ssd) type analytic system, where a cam nand structure can be used in the analytic operations. The server can run a software using database language can issue command to the analytic system.
05/15/14
20140136760
De-duplication system using nand flash based content addressable memory
A nand flash based content addressable memory (cam) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as pci-e, sas, sata, emmc, scsi, and so on.
05/15/14
20140136759
De-duplication techniques using nand flash based content addressable memory
A nand flash based content addressable memory (cam) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as pci-e, sas, sata, emmc, scsi, and so on.
05/15/14
20140136758
Key value addressed storage drive using nand flash based content addressable memory
A nand flash based content addressable memory (cam) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as pci-e, sas, sata, emmc, scsi, and so on.
05/15/14
20140136757
Nand flash based content addressable memory
A nand flash based content addressable memory (cam) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as pci-e, sas, sata, emmc, scsi, and so on.
05/15/14
20140136756
Nand flash based content addressable memory
A nand flash based content addressable memory (cam) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as pci-e, sas, sata, emmc, scsi, and so on.
05/15/14
20140133238
Method and system for programming non-volatile memory with junctionless cells
A non-volatile memory system that has junctionless transistors is provided that uses suppression of the formation of an inversion-layer source and drain in the junctionless transistors to cause a discontinuous channel in at least one string. The system may include nand flash memory cells composed of junctionless transistors, and has a set of wordlines.
05/15/14
20140133237
On-device data analytics using nand flash based intelligent memory
A nand flash based content addressable memory (cam) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as pci-e, sas, sata, emmc, scsi, and so on.
05/15/14
20140133236
Hierarchical common source line structure in nand flash memory
Each memory cell string in a generic nand flash cell block connects to a common source line (cls). A value for applying to the csl is centrally generated and distributed to a local switch logic unit corresponding to each nand flash cell block.
05/15/14
20140133228
Key-value addressed storage drive using nand flash based content addressable memory
A nand flash based content addressable memory (cam) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as pci-e, sas, sata, emmc, scsi, and so on.
05/15/14
20140133226
Erasing physical memory blocks of non-volatile memory
Apparatus and methods are disclosed, such as those that provide dynamic block allocations in nand flash memory between single-level cells (slc) and multi-level cells (mlc) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between slc mode and mlc mode based on the amount of memory available for use.
05/08/14
20140126292
Flash memory with data retention bias
Charge leakage from a floating gate in a nand flash memory die is reduced by applying a data retention bias to a word line extending over the floating gates. The data retention bias is applied to one or more selected word lines when the memory die is in idle mode, when no read, write, erase, or other commands are being executed in the memory die..
05/01/14
20140119113
Threshold acquisition and adaption in nand flash memory
A method, apparatus, and controller for acquiring and tracking at least one threshold voltage of at least one cell of at least one flash chip. The method can include acquiring the at least one threshold voltage of a particular cell of the at least one flash cell.
04/24/14
20140115230
Flash memory with data retention partition
A nand flash memory chip includes a first partition that has smaller memory cells, with smaller charge storage elements, and a second partition that has larger memory cells, with larger charge storage elements, in the same memory array. Data is selected for storage in the first or second partition according to characteristics, or expected characteristics, of the data..
04/17/14
20140108705
Use of high endurance non-volatile memory for read acceleration
A high endurance, short retention nand memory is used as a read cache for a memory of a higher level of non-volatility, such as standard nand flash memory or a hard drive. The combined memory system identifies frequently read logical addresses of the main non-volatile memory or specific read sequences and stores the corresponding data in cache nand to accelerate host reads.
04/10/14
20140101370
Apparatus and method for low power low latency high capacity storage class memory
A method and a storage system are provided for implementing enhanced solid-state storage class memory (escm) including a direct attached dual in line memory (dimm) card containing dynamic random access memory (dram), and at least one non-volatile memory, for example, phase change memory (pcm), resistive ram (reram), spin-transfer-torque ram (stt-ram), and nand flash chips. An escm processor controls selectively allocating data among the dram, and the at least one non-volatile memory primarily based upon a data set size..
04/10/14
20140097482
Full metal gate replacement process for nand flash memory
A nand flash memory chip is made by forming sacrificial control gate structures and sacrificial select structures, and subsequently replacing these sacrificial structures with metal. Filler structures are formed between sacrificial control gate structures and are subsequently removed to form air gaps between neighboring control gate lines and between floating gates..
04/03/14
20140091381
Support lines to prevent line collapse in arrays
Methods for preventing line collapse during the fabrication of nand flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication.
03/27/14
20140089567
Hardware integrity verification
A flash memory management method and apparatus provides for the separation of the command and data paths so that communication paths may be used more efficiently, taking account of the characteristics of nand flash circuits where the times to read, write and erase data differ substantially. A unique sequence identifier is assigned to a write command and associated data and association of the data and commands are validated prior to writing to the memory by comparing the unique sequence numbers of the data and command prior to executing the command.
03/20/14
20140082264
Nand flash storage chip checking method and device
A nand flash storage chip correcting method is provided in the present invention. The method can correct one or two bits errors and find a number of bits errors according to the row and column xor value and hash value of each page written into the spare area, comparing the data stored in the data area and the computed hash value of data area to correct one or two bits of errors, thus ensures the accuracy and integrity of the data stored in the nand flash chip and reduces the risk of crash of the file system..
03/20/14
20140080299
Processes for nand flash memory fabrication
Narrow word lines are formed in a nand flash memory array using a double patterning process in which sidewall spacers define word lines. Sidewall spacers also define edges of select gates so that spacing between a select gate and the closest word line is equal to spacing between adjacent word lines..
03/20/14
20140078826
Methods of making word lines and select lines in nand flash memory
A nand flash memory chip includes word lines formed by etching through concentric conductive loops and, in the same etch step, etching through a conductive strip to form select lines. A conductive loop forms two word lines which are in different erase blocks and are separately controlled by peripheral circuits..
03/13/14
20140075268
Method for dodging bad page and bad block caused by suddenly power off
A method for dodging bad page and bad block caused by suddenly power off is disclosed. This method is to avoid a new data from host program to potential hurt block or page caused by power off during nand flash erasing or programming..
02/27/14
20140054669
Structures and methods for making nand flash memory
A nand flash memory chip includes wide openings in an inter-poly dielectric layer through which gaps are later etched to define structures such as select gates. Such select gates are asymmetric, with inter-poly dielectric on a side adjacent to a memory cell and no inter-poly dielectric on a side away from a memory cell.
02/13/14
20140047269
Operating method for memory system including nonvolatile ram and nand flash memory
An operating method for a memory system including a nonvolatile random access memory (nvram) and a nand flash memory includes; performing a normal read operation directed to the target memory cell in response to a read request, determining that a read fail has occurred as a result of the normal read operation, then performing a read retry operation by iterations directed to the target memory cell according to a first read retry scheme until a pass read retry iteration successfully reads the target memory cell, and storing pass information associated with the pass read retry iteration in the nvram.. .
02/13/14
20140043898
Common line current for program level determination in flash memory
In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—is determined from the total current passing through the population of memory cells under read conditions, as observed on a common line, for example a source line in nand flash memory.. .
01/30/14
20140029341
Non-volatile solid state memory-based mass storage device and methods thereof
Non-volatile solid state mass storage device and methods for improving write performance thereof. The storage device includes a nand flash controller, an array of nand flash memory integrated circuits, and means for determining a lowest unused page number of each write target block in a group of the nand flash memory integrated circuits that are simultaneously accessible at any given time by a write command.
01/23/14
20140022847
Nand flash memory programming
A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described..
01/23/14
20140022846
Nand flash memory having multiple cell substrates
A nand flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where nand cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage.
01/16/14
20140019741
Method and system for booting electronic device from nand flash memory
A method and system for booting an electronic device from a nand flash memory includes a nand flash controller that receives an event trigger for fetching a pre-boot code stored in the nand flash memory. Based on the event trigger type, booting parameters are loaded into the controller including a boot frequency of the nand flash memory.
01/09/14
20140013032
Method and apparatus for controlling writing data in storage unit based on nand flash memory
A method and apparatus for controlling writing of data in a storage unit based on a nand flash memory are provided. The method includes determining reference values for classifying dirty pages to be written in the storage unit into a plurality of groups; calculating, with respect to each of the dirty pages, a hotness indicating a possibility of a change of data; classifying the dirty pages into the groups corresponding to reference values most similar to the calculated hotness; determining whether sizes of the groups are greater than a size of a segment, where the segment is a unit for performing a write request in the storage unit; and requesting a write operation for each segment with respect to groups having a size at least equal to the size of the segment to the storage unit..
01/02/14
20140003148
Three dimensional nand flash with self-aligned select gate
An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor material, and two or more memory cells, stacked vertically on top of the field effect transistor, and having channels that are formed in the pillar semiconductor of material.. .
12/26/13
20130346671
On-chip bad block management for nand flash memory
Certain functions relating to creation and use of a look-up table for bad block mapping may be implemented “on chip” in the memory device itself, that is on the same die in an additional circuit, or even within the command and control logic of the memory device, so as to reduce the overhead. Moreover, the on-chip implementation of the look-up table may be tightly integrated with other functions of the command and control logic to enable powerful new commands for nand flash memory, such as a continuous read command and variations thereof..
12/26/13
20130343130
Nand flash biasing operation
A charge storage memory is configured in a nand array, and includes nand strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the nand array.
12/05/13
20130322179
Hot carrier programming in nand flash
A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a nand string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection using a boosted channel potential to establish the heating field.
11/28/13
20130316537
Self-aligned nand flash select-gate wordlines for spacer double patterning
A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed.
11/21/13
20130308388
Apparatus and method for reduced peak power consumption during common operation of multi-nand flash memory devices
System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently.
11/07/13
20130297987
Method and apparatus for reading nand flash memory
A page buffer for a nand memory array has a data register and a cache register that are suitably organized and operated to eliminate gaps and discontinuities in the output data during a continuous page read. The cache register may be organized in two portions, and the page data in the cache may be output from the cache portions in alternation.
10/31/13
20130286737
Nand flash memory having c/a pin and flash memory system including the same
A nand flash memory in which a command/address pin is separated from a data input/output pin. The nand flash memory includes a memory cell array used for storing data, a command/address pin through which a command and an address are received for transmitting data in the memory cell array, and a data input/output pin through which data are transmitted in the memory cell array.
10/31/13
20130286734
Nand flash memory
A nand flash memory includes a plurality of nand flash memory structures separated by an insulating layer. In one embodiment of the present disclosure, the nand flash memory structure includes a first bitline extending along a first direction, a first charge-trapping region positioned over the first bitline, a wordline positioned over the first charge-trapping region and extending along a second direction, a second charge-trapping region positioned over the wordline, and a second bitline positioned over the second charge-trapping region, wherein the first charge-trapping region and the second charge-trapping region are stacked along a third direction substantially perpendicular to the first direction and the second direction..
10/24/13
20130279251
Novel shielding 2-cycle half-page read and program schemes for advanced nand flash design
The present invention provides a two-cycle half-page read scheme by dividing whole nand array bit lines (bls) into an odd-bl group and an even-bl group. During the half-plane reading of nand cells in the odd(even)-bl group, the half-plane even(odd)-bl group acts as the shielding bls to protect over the odd(even)-bl string reading so that each half-page read operation is substantially reliable and free from bl coupling noise effect.
10/24/13
20130279249
Operating method of memory system including nand flash memory, variable resistance memory and controller
An operating method is for a memory system which includes a nand flash memory, a resistance variable memory, and a controller controlling the nand flash memory and the resistance variable memory. The operating method includes receiving data, programming the received data in the nand flash memory when the received data is at least a super page of data, programming the received data in the resistance variable memory when the received data is not a super page of data, and programming data accumulated in the resistance variable memory in the nand flash memory when the accumulated data is a super page of data.
10/03/13
20130262901
Memory system and server system
According to one embodiment, a memory system includes a nand flash memory includes a memory cell array includes pages, and a volatile data register with a storage capacity of one page, and configured to write page data to the memory cell array through the data register, each of the pages includes nonvolatile memory cells and being a unit of data write, a volatile ram, and a controller includes a power saving mode in which power consumption of the ram is reduced, and configured to transfer data of the ram to the data register before entering the power saving mode.. .
10/03/13
20130262744
Nand flash memory interface
A nand flash memory chip has a configurable interface that can communicate with a nand flash memory controller using either parallel communication or serial communication. Serial communication requires fewer channels.
10/03/13
20130258780
Method of programming selection transistors for nand flash memory
Disclosed herein is a method that includes providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to associated one of the cells, and a selection line coupled in common to the gates of the selection transistors, applying a first program voltage to the selection line, and applying a second program voltage to the selection line when at least one of the selection transistors have not been shifted to a program condition.. .
10/03/13
20130256775
Three-dimensional microelectronic devices including horizontal and vertical patterns
A vertical nand flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face.
09/19/13
20130246892
Architecture for storage of data on nand flash memory
Systems, methods, apparatus, and techniques are provided for processing data from a storage medium. A stripe of data stored on the storage medium is read, where the stripe comprises a plurality of data allocation units (aus) and a parity au.
09/19/13
20130246890
Architecture to allow efficient storage of data on nand flash memory
Systems, methods, apparatus, and techniques are provided for writing data to a storage medium. A stripe of the storage medium is interfaced via one or more data transfer channels, where the stripe comprises a plurality of pages of the storage medium.
09/19/13
20130246694
Multilevel memory bus system for solid-state mass storage
The present invention relates to a multilevel memory bus system for transferring information between at least one dma controller and at least one solid-state semiconductor memory device, such as nand flash memory devices or the like. This multilevel memory bus system includes at least one dma controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus.
09/19/13
20130246693
Flash-aware storage optimized for mobile and embedded dbms on nand flash memory
Reliable storage for database management systems (dbms) running on memory devices such as nand type flash memory utilizes minimum i/o overhead and provides maximum data durability. A virtual page map is utilized between the flash memory and a page access component to record changes to the dbms pages and prevent overwriting or data loss.


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Nand Flash topics: Nand Flash, Flash Memory, Memory Cell, Memory Device, Memory Cells, Volatile Memory, Allocation, Data Transfer, Alternation, Interleaving, Electronic Device, Transistors, Memory Chip, Nonvolatile Memory, Database Management System

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This listing is a sample listing of patent applications related to Nand Flash for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Nand Flash with additional patents listed. Browse our RSS directory or Search for other possible listings.
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