|| List of recent Mute-related patents
| Context aware synchronization|
Examples are disclosed for context aware synchronization. A mutual exclusion (mutex) lock object or monitor may be created to enable threads to acquire a lock to access a shared data structure when executing a critical section of code.
|System performance enhancement with smi on multi-core systems|
Mechanisms for providing enhanced system performance and reliability on multi-core computing devices are discussed. Embodiments use modified hardware and/or software so that when a system management interrupt (smi#) is generated, only a single targeted cpu core enters system management mode (smm) in response to the smi while the remaining cpu cores continue operating in normal mode.
Insyde Software Corp.
When different types of shared resources need mutex protection, the shared resources can be organized into classes. Each class of shared resources can have multiple types of resources.
|Maintaining concurrency and consistency of globally unique identifiers|
Systems, methods, and computer-readable storage media for ensuring data consistency and concurrency for globally unique identifiers (guids) and associated content items via locking. A content management system configured to practice the method can receive, from a client device, a request to perform a content item operation in a storage environment that affects a guid.
|Method and system for software licensing under machine virtualization|
A method and system implementing software licensing management under machine virtualization are disclosed. According to one embodiment, a system comprises a virtual platform running on a physical machine; a binding agent running on a host operating system of the virtual platform; a license enforcement module running on a virtual machine instance of the virtual platform.
|Distributed symmetric multiprocessing computing architecture|
Example embodiments of the present invention includes systems and methods for implementing a scalable symmetric multiprocessing (shared memory) computer architecture using a network of homogeneous multi-core servers. The level of processor and memory performance achieved is suitable for running applications that currently require cache coherent shared memory mainframes and supercomputers.
|System and method to provide single thread access to a specific memory region|
Processing logic and a method to provide single thread access to a specific memory region without suspending processing activity for all other cores and/or threads within or in association with a processor, computer system, or other processing apparatus. Single thread access may be provided through implementation of microcode which may control thread access to model specific registers (“msrs”) within a processor.
|Hardware control method and apparatus|
A hardware control method for multitasking drivers under a user mode is provided. The control method includes steps of: receiving a request for access to a hardware device from a current process under the user mode; determining whether the current process has obtained a mutual exclusion (mutex) of the hardware device; if affirmative, determining whether an identification of the current process and an identification of a previous process accessed the hardware device are the same; if negative, performing a context switch on the current process and the previous process accessed the hardware device to allow the current process to access the hardware device.
|Mute drive circuit|
A mute drive circuit includes a micro-controller including an i/o port; a mute circuit; and an npn transistor. When an electronic device using the mute circuit is plugged into an ac power source, the i/o port is set to the logic low, the mute circuit performs the mute mode.
|Earphone jack drive circuit|
An earphone jack drive circuit applied in an electronic device is provided. The earphone jack drive circuit includes a mute circuit; a micro-controller including a detect pin and a control pin; a delay switch circuit including a resistance, a capacitance, an npn transistor and a first current-limiting resistance.
Managing shared computer resources
Various systems, processes, and products may be used to manage shared computer resources. In particular implementations, managing shared computer resources may include the ability to execute a first process on a first central processing unit and execute a second process on a second central processing units, wherein the first process and the second process are operable to access a first resource, and to determine at a mutex controller which of the first process and the second process is allowed to access the first resource at a given time..
System and supporting parallel threads in a multiprocessor environment
A method and system for supporting parallel processing of threads includes receiving a read request for a container from one or more read threads. Next, parallel read access to the container for each read thread may be controlled with a manager module that is coupled to the container.
Methods, systems, and computer-readable media with executable instructions stored thereon for preventing deadlocks are provided. An inter-device mutex (idm) can be locked for a first client.
Cpu/gpu synchronization mechanism
A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory..
Providing automatic power control for a power amplifier
A power control circuit is coupled to receive a feedback signal from a power amplifier (pa) and generate a control signal to control a variable gain amplifier (vga) coupled to an input to the pa based on the feedback signal. The power control circuit may include, in one embodiment, a mute circuit to generate a mute signal to be provided to the vga when the control signal is less than a first level and a clamp circuit to clamp a control voltage used to generate the control signal from exceeding a threshold level..