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Memristor

Memristor-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Printhead having a number of single-dimensional memristor banks
Hewlett-packard Development Company, L.p.
October 12, 2017 - N°20170291414

A printhead having a number of single-dimensional memristor banks is described. The printhead includes a number of nozzles to deposit an amount of fluid onto a print medium. Each nozzle includes a firing chamber to hold the amount of fluid, an opening to dispense the amount of fluid onto the print medium, and an ejector to eject the amount of ...
Memristor-based processor integrating computing and memory and method for using the processor
Huazhong University Of Science And Technology
October 05, 2017 - N°20170287558

A processor including a computing and memory structure including x in number integration units and x in number communication units, and a control unit. The integration units are computing and memory units (cmus), each computing and memory unit (cmu) is connected to a corresponding communication unit. The control unit is configured to produce control signals according to the commands, connect ...
Memristors with oxide switching layers
Hewlett-packard Development Company, L.p.
September 28, 2017 - N°20170279044

An example memristor includes a first conductive layer, a switching layer, and a second conductive layer. The first conductive layer may include a first conductive material and a second conductive material. The second conductive material may have a higher diffusivity than the first conductive material. The switching layer may be coupled to the first conductive layer and may include a ...
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Multilayered memristors
Hewlett Packard Enterprise Development Lp
September 21, 2017 - N°20170271591

A multilayered memristor includes a semiconducting n-type layer, a semiconducting p-type layer, and a semiconducting intrinsic layer. The semiconducting n-type layer includes one or both of anion vacancies and metal cations. The semiconducting p-type layer includes one or both of metal cation vacancies and anions. The semiconducting intrinsic layer is coupled between the n-type layer and the p-type layer to ...
Resistive memory arrays with a negative temperature coefficient of resistance material
Hewlett Packard Enterprise Development Lp
September 21, 2017 - N°20170271589

A resistive memory array includes a plurality of resistive memory devices. A sneak path current in the resistive memory array is reduced when a negative temperature coefficient of resistance material is incorporated in series with a negative differential resistance selector that is in series with a memristor switching material at a junction formed at a cross-point between two conductors of ...
Resistive memory devices and arrays
Hewlett Packard Enterprise Development Lp
September 21, 2017 - N°20170271409

A resistive memory device includes a first electrode, a memristor coupled in electrical series with the first electrode, a second electrode coupled in electrical series with the memristor, a selector coupled in electrical series with the second electrode, and a third electrode coupled in electrical series with the selector. The memristor includes oxygen or nitrogen elements. The selector includes a ...
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Determining resistance states of memristors in a crossbar array
Hewlett Packard Enterprise Development Lp
September 21, 2017 - N°20170271003

In one example in accordance with the present disclosure a method of determining a resistance state of a memristor in a crossbar array is disclosed. In the method, a combined reference-sneak current is determined based on a reference voltage, a sense voltage, a non-access voltage, and a voltage applied to a target row line. Also in the method a combined ...
Memristive dot product engine with a nulling amplifier
Hewlett Packard Enterprise Development Lp
August 31, 2017 - N°20170249989

A method of obtaining a dot product using a memristive dot product engine with a nulling amplifier includes applying a number of programming voltages to a number of row lines within a memristive crossbar array to change the resistance values of a corresponding number of memristors located at intersections between the row lines and a number of column lines. The ...
Bi-polar memristor
Hewlett-packard Development Company, L.p.
August 24, 2017 - N°20170243645

A circuit comprising an input, a ground, a first switch, a second switch and a bi-polar memristor, wherein the first switch is a first transistor and a gate of the first transistor is connected to a line to instruct setting of the bi-polar memristor, and the second switch is a second transistor and a gate of the second transistor is ...
Printhead with a number of memristors and inverters
Hewlett-packard Development Company, L.p.
August 24, 2017 - N°20170239941

A print head with a number of memristors and inverters is described. The print head includes a number of nozzles to deposit an amount of fluid onto a print medium. Each nozzle includes a firing chamber to hold the amount of fluid, an opening to dispense the amount of fluid onto the print medium, and an ejector to eject the ...
Generating a representative logic indicator of grouped memristors
Hewlett-packard Development Company, L.p.
August 10, 2017 - N°20170229170

A device for generating a representative logic indicator of grouped memristors is described. The device includes a memristor array. The memristor array includes a number of first memristors having a first set of logic indicators and a number of second memristors having a second set of logic indicators. The second set of logic indicators is different than the first set ...
Analog co-processor
Spero Devices, Inc.
August 10, 2017 - N°20170228345

A co-processor is configured for performing vector matrix multiplication (vmm) to solve computational problems such as partial differential equations (pdes). An analog discrete fourier transform (dft) can be implemented by invoking vmm of input signals with fourier basis functions using analog crossbar arrays. Linear and non-linear pdes can be solved by implementing spectral pde solution methods as an alternative to ...
Memristor apparatus with variable transmission delay
Hewlett Packard Enterprise Development Lp
August 03, 2017 - N°20170221558

In an example, a memristor apparatus with variable transmission delay may include a first memristor programmable to have one of a plurality of distinct resistance levels, a second memristor, a transistor connected between the first memristor and the second memristor, and a capacitor having a capacitance, in which the capacitor is connected between the first memristor and the transistor. In ...
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Memristor programming error reduction
Hewlett Packard Enterprise Development Lp
July 20, 2017 - N°20170206962

Error reduction in memristor programming includes programming an n-th switched memristor of a switched memristor array with an error-corrected target resistance. The error-corrected target resistance is a function of a resistance error of the switched memristor array and a target resistance of the n-th switched memristor. The n-th switched memristor programming is to reduce a total resistance error of the ...
Memristor cell read margin enhancement
Hewlett Packard Enterprise Development Lp
July 20, 2017 - N°20170206955

Memristor cell read margin enhancement employs programming switched memristor sub-bits of a memristor cell with a first resistive state to increase a relative read margin of the memristor cell. The switched memristor sub-bits of the memristor cell are connected in series. The read margin of the memristor cell is increased relative to a read margin of either of the switched ...
Printhead with a number of memristor cells and a parallel current distributor
Hewlett- Packard Development Company, L.p .
July 20, 2017 - N°20170203561

A printhead with a number of memristors and a parallel current distributor is described. The printhead includes a number of nozzles to deposit an amount of fluid onto a print medium. Each nozzle includes a firing chamber to hold the amount of fluid, an opening to dispense the amount of fluid onto the print medium, and an ejector to eject ...
Increasing a read margin in a read cell
Hewlett Packard Enterprise Development Lp
July 13, 2017 - N°20170200496

A method of increasing a read margin in a memory cell may include sensing an input current created from the application of a read voltage across a memristive device, squaring the input current, and comparing the squared input current to a reference current. A memristive device may include a memristor and a sense amplifier communicatively coupled to the memristor wherein ...
Apparatus having a memory cell and a shunt device
Hewlett Packard Enterprise Development Lp
July 13, 2017 - N°20170200495

According to an example, an apparatus may include an input line, an output line, and a memory cell connected between the input line and the output line. The memory cell may include a memristor connected in series with a selector. The apparatus may also include a shunt device connected to the input line, in which the shunt device is to ...
Memory controllers
Hewlett Parkard Enterprise Development Lp
July 13, 2017 - N°20170200494

A memory controller includes a voltage control module that operates to isolate a target memristor of a memory crossbar array. The voltage control module applies a column voltage to a column line coupled to the target memristor, applies a first row voltage to all row lines not coupled to the target memristor and a second row voltage to a row ...
Method for updating weights of synapses of a neuromorphic device
Sk Hynix Inc.
July 06, 2017 - N°20170193363

A method for updating a weight of a synapse of a neuromorphic device is provided. The synapse may include a transistor and a memristor. The memristor may have a first electrode coupled to a source electrode of the transistor. The method may include inputting a row spike to a drain electrode of the transistor at a first time; inputting a ...
Memristive dot product engine for vector processing
Hewlett Packard Enterprise Development Lp
June 22, 2017 - N°20170178725

A memristive dot-product system for vector processing is described. The memristive dot-product system includes a crossbar array having a number of memory elements. Each memory element includes a memristor. Each memory element includes a transistor. The system also includes a vector input register. The system also includes a vector output register.
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