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Memristor

Memristor-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Logic design with unipolar memristors
Technion Research & Development Foundation Limited
November 30, 2017 - N°20170345497

Logic gates are made from first and second resistive elements connected together to form a voltage divider. One or both of the resistive elements is a unipolar memristor. Or and not gates may be constructed to make a digital logic system.
Method for implementing memristive logic gates
Technion Research & Development Foundation Limited
November 23, 2017 - N°20170337968

An embodiment of the present invention provides a method for implementing boolean functionality to create and, or, nand, nor, or not logic gates using a single memristor. In an embodiment, a first voltage is applied to the memristor within a predetermined range of one of the prescribed boolean functions to be performed by the memristor. A second voltage is then ...
Memristive cross-bar array for determining a dot product
Technion Research & Development Foundation Limited
November 02, 2017 - N°20170316827

A method of obtaining a dot product includes applying a number of first voltages to a corresponding number of row lines within a memristive cross-bar array to change the resistive values of a corresponding number of memristors located a junctions between the row lines and a number of column lines. The first voltages define a corresponding number of values within ...
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Integrated circuit devices comprising memristors
Hewlett-packard Development Company, L.p.
October 26, 2017 - N°20170305153

In some examples, an integrated circuit device includes a substrate, a memristor over the substrate and comprising a first metal layer as a first electrode, a second metal layer as a second electrode, and a switching oxide layer between the first and second metal layers, and a thermal resistor layer over the substrate.
Coupled memristor devices to enable feedback control and sensing of micro/nanoelectromechanical actuator and sencors
Hewlett-packard Development Company, L.p.
October 19, 2017 - N°20170297908

A mems apparatus with dynamic displacement control includes a mems parallel plate capacitor integrated with one or more memristors in a series configuration wherein a displacement is observable as a function of memristance, such that an upper electrode position is capable of being interpreted in a form of a resistance rather than a capacitance. The current is limited by said ...
Printhead having a number of single-dimensional memristor banks
Hewlett-packard Development Company, L.p.
October 12, 2017 - N°20170291414

A printhead having a number of single-dimensional memristor banks is described. The printhead includes a number of nozzles to deposit an amount of fluid onto a print medium. Each nozzle includes a firing chamber to hold the amount of fluid, an opening to dispense the amount of fluid onto the print medium, and an ejector to eject the amount of ...
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Memristors with oxide switching layers
Hewlett-packard Development Company, L.p.
September 28, 2017 - N°20170279044

An example memristor includes a first conductive layer, a switching layer, and a second conductive layer. The first conductive layer may include a first conductive material and a second conductive material. The second conductive material may have a higher diffusivity than the first conductive material. The switching layer may be coupled to the first conductive layer and may include a ...
Fast erasing memristors
Hewlett-packard Development Company, L.p.
September 28, 2017 - N°20170279042

A fast erasing memristor includes an active region, a resistive heater, and a dielectric sheath. The active region has a switching layer coupled between a first conducting layer and second conducting layer. The resistive heater is coupled to the active region to provide heat to the active region. The dielectric sheath separates the active region and the resistive heater.
Multilayered memristors
Hewlett Packard Enterprise Development Lp
September 21, 2017 - N°20170271591

A multilayered memristor includes a semiconducting n-type layer, a semiconducting p-type layer, and a semiconducting intrinsic layer. The semiconducting n-type layer includes one or both of anion vacancies and metal cations. The semiconducting p-type layer includes one or both of metal cation vacancies and anions. The semiconducting intrinsic layer is coupled between the n-type layer and the p-type layer to ...
Resistive memory arrays with a negative temperature coefficient of resistance material
Hewlett Packard Enterprise Development Lp
September 21, 2017 - N°20170271589

A resistive memory array includes a plurality of resistive memory devices. A sneak path current in the resistive memory array is reduced when a negative temperature coefficient of resistance material is incorporated in series with a negative differential resistance selector that is in series with a memristor switching material at a junction formed at a cross-point between two conductors of ...
Resistive memory devices and arrays
Hewlett Packard Enterprise Development Lp
September 21, 2017 - N°20170271409

A resistive memory device includes a first electrode, a memristor coupled in electrical series with the first electrode, a second electrode coupled in electrical series with the memristor, a selector coupled in electrical series with the second electrode, and a third electrode coupled in electrical series with the selector. The memristor includes oxygen or nitrogen elements. The selector includes a ...
Determining a state of memristors in a crossbar array
Hewlett Packard Enterprise Development Lp
September 21, 2017 - N°20170271004

In one example in accordance with the present disclosure a method of determining a state of a memristor in a crossbar array is described. In the method a bias voltage is applied to a target row line in the crossbar array, which bias voltage causes a bias current to pass through a target memristor along the target row line. The ...
Determining resistance states of memristors in a crossbar array
Hewlett Packard Enterprise Development Lp
September 21, 2017 - N°20170271003

In one example in accordance with the present disclosure a method of determining a resistance state of a memristor in a crossbar array is disclosed. In the method, a combined reference-sneak current is determined based on a reference voltage, a sense voltage, a non-access voltage, and a voltage applied to a target row line. Also in the method a combined ...
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Bi-polar memristor
Hewlett-packard Development Company, L.p.
August 24, 2017 - N°20170243645

A circuit comprising an input, a ground, a first switch, a second switch and a bi-polar memristor, wherein the first switch is a first transistor and a gate of the first transistor is connected to a line to instruct setting of the bi-polar memristor, and the second switch is a second transistor and a gate of the second transistor is ...
Printhead with a number of memristors and inverters
Hewlett-packard Development Company, L.p.
August 24, 2017 - N°20170239941

A print head with a number of memristors and inverters is described. The print head includes a number of nozzles to deposit an amount of fluid onto a print medium. Each nozzle includes a firing chamber to hold the amount of fluid, an opening to dispense the amount of fluid onto the print medium, and an ejector to eject the ...
Generating a representative logic indicator of grouped memristors
Hewlett-packard Development Company, L.p.
August 10, 2017 - N°20170229170

A device for generating a representative logic indicator of grouped memristors is described. The device includes a memristor array. The memristor array includes a number of first memristors having a first set of logic indicators and a number of second memristors having a second set of logic indicators. The second set of logic indicators is different than the first set ...
Analog co-processor
Spero Devices, Inc.
August 10, 2017 - N°20170228345

A co-processor is configured for performing vector matrix multiplication (vmm) to solve computational problems such as partial differential equations (pdes). An analog discrete fourier transform (dft) can be implemented by invoking vmm of input signals with fourier basis functions using analog crossbar arrays. Linear and non-linear pdes can be solved by implementing spectral pde solution methods as an alternative to ...
Memristor apparatus with variable transmission delay
Hewlett Packard Enterprise Development Lp
August 03, 2017 - N°20170221558

In an example, a memristor apparatus with variable transmission delay may include a first memristor programmable to have one of a plurality of distinct resistance levels, a second memristor, a transistor connected between the first memristor and the second memristor, and a capacitor having a capacitance, in which the capacitor is connected between the first memristor and the transistor. In ...
Printhead with a memristor
Hewlett-packard Development Company, L.p.
August 03, 2017 - N°20170217168

In an example, a printhead includes a memristor, in which the memristor may include a first electrode, a second electrode positioned in a crossed relationship with the first electrode to form a junction, and a switching element positioned at the junction between the first electrode and the second electrode, in which the switching layer includes a via formed in the ...
Memristor programming error reduction
Hewlett Packard Enterprise Development Lp
July 20, 2017 - N°20170206962

Error reduction in memristor programming includes programming an n-th switched memristor of a switched memristor array with an error-corrected target resistance. The error-corrected target resistance is a function of a resistance error of the switched memristor array and a target resistance of the n-th switched memristor. The n-th switched memristor programming is to reduce a total resistance error of the ...
Memristor cell read margin enhancement
Hewlett Packard Enterprise Development Lp
July 20, 2017 - N°20170206955

Memristor cell read margin enhancement employs programming switched memristor sub-bits of a memristor cell with a first resistive state to increase a relative read margin of the memristor cell. The switched memristor sub-bits of the memristor cell are connected in series. The read margin of the memristor cell is increased relative to a read margin of either of the switched ...
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